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Blackfin SPI Driver: pass DMA overflow error to the higher level
[net-next-2.6.git] / drivers / spi / spi_bfin5xx.c
CommitLineData
a5f6abd4 1/*
26fdc1f0 2 * Blackfin On-Chip SPI Driver
a5f6abd4 3 *
131b17d4 4 * Copyright 2004-2007 Analog Devices Inc.
a5f6abd4 5 *
26fdc1f0 6 * Enter bugs at http://blackfin.uclinux.org/
a5f6abd4 7 *
26fdc1f0 8 * Licensed under the GPL-2 or later.
a5f6abd4
WB		 9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
131b17d4 13#include <linux/delay.h>
a5f6abd4 14#include <linux/device.h>
131b17d4 15#include <linux/io.h>
a5f6abd4 16#include <linux/ioport.h>
131b17d4 17#include <linux/irq.h>
a5f6abd4
WB		 18#include <linux/errno.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22#include <linux/spi/spi.h>
23#include <linux/workqueue.h>
a5f6abd4 24
a5f6abd4 25#include <asm/dma.h>
131b17d4 26#include <asm/portmux.h>
a5f6abd4 27#include <asm/bfin5xx_spi.h>
8cf5858c
VM		 28#include <asm/cacheflush.h>
29
a32c691d
BW		 30#define DRV_NAME "bfin-spi"
31#define DRV_AUTHOR "Bryan Wu, Luke Yang"
6b1a8028 32#define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
a32c691d
BW		 33#define DRV_VERSION "1.0"
34
35MODULE_AUTHOR(DRV_AUTHOR);
36MODULE_DESCRIPTION(DRV_DESC);
a5f6abd4
WB		 37MODULE_LICENSE("GPL");
38
bb90eb00 39#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
a5f6abd4 40
bb90eb00
BW		 41#define START_STATE ((void *)0)
42#define RUNNING_STATE ((void *)1)
43#define DONE_STATE ((void *)2)
44#define ERROR_STATE ((void *)-1)
45#define QUEUE_RUNNING 0
46#define QUEUE_STOPPED 1
a5f6abd4
WB		 47
48struct driver_data {
49 /* Driver model hookup */
50 struct platform_device *pdev;
51
52 /* SPI framework hookup */
53 struct spi_master *master;
54
bb90eb00 55 /* Regs base of SPI controller */
f452126c 56 void __iomem *regs_base;
bb90eb00 57
003d9226
BW		 58 /* Pin request list */
59 u16 *pin_req;
60
a5f6abd4
WB		 61 /* BFIN hookup */
62 struct bfin5xx_spi_master *master_info;
63
64 /* Driver message queue */
65 struct workqueue_struct *workqueue;
66 struct work_struct pump_messages;
67 spinlock_t lock;
68 struct list_head queue;
69 int busy;
70 int run;
71
72 /* Message Transfer pump */
73 struct tasklet_struct pump_transfers;
74
75 /* Current message transfer state info */
76 struct spi_message *cur_msg;
77 struct spi_transfer *cur_transfer;
78 struct chip_data *cur_chip;
79 size_t len_in_bytes;
80 size_t len;
81 void *tx;
82 void *tx_end;
83 void *rx;
84 void *rx_end;
bb90eb00
BW		 85
86 /* DMA stuffs */
87 int dma_channel;
a5f6abd4 88 int dma_mapped;
bb90eb00 89 int dma_requested;
a5f6abd4
WB		 90 dma_addr_t rx_dma;
91 dma_addr_t tx_dma;
bb90eb00 92
a5f6abd4
WB		 93 size_t rx_map_len;
94 size_t tx_map_len;
95 u8 n_bytes;
fad91c89 96 int cs_change;
a5f6abd4
WB		 97 void (*write) (struct driver_data *);
98 void (*read) (struct driver_data *);
99 void (*duplex) (struct driver_data *);
100};
101
102struct chip_data {
103 u16 ctl_reg;
104 u16 baud;
105 u16 flag;
106
107 u8 chip_select_num;
108 u8 n_bytes;
88b40369 109 u8 width; /* 0 or 1 */
a5f6abd4
WB		 110 u8 enable_dma;
111 u8 bits_per_word; /* 8 or 16 */
112 u8 cs_change_per_word;
62310e51 113 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
a5f6abd4
WB		 114 void (*write) (struct driver_data *);
115 void (*read) (struct driver_data *);
116 void (*duplex) (struct driver_data *);
117};
118
bb90eb00
BW		 119#define DEFINE_SPI_REG(reg, off) \
120static inline u16 read_##reg(struct driver_data *drv_data) \
121 { return bfin_read16(drv_data->regs_base + off); } \
122static inline void write_##reg(struct driver_data *drv_data, u16 v) \
123 { bfin_write16(drv_data->regs_base + off, v); }
124
125DEFINE_SPI_REG(CTRL, 0x00)
126DEFINE_SPI_REG(FLAG, 0x04)
127DEFINE_SPI_REG(STAT, 0x08)
128DEFINE_SPI_REG(TDBR, 0x0C)
129DEFINE_SPI_REG(RDBR, 0x10)
130DEFINE_SPI_REG(BAUD, 0x14)
131DEFINE_SPI_REG(SHAW, 0x18)
132
88b40369 133static void bfin_spi_enable(struct driver_data *drv_data)
a5f6abd4
WB		 134{
135 u16 cr;
136
bb90eb00
BW		 137 cr = read_CTRL(drv_data);
138 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
a5f6abd4
WB		 139}
140
88b40369 141static void bfin_spi_disable(struct driver_data *drv_data)
a5f6abd4
WB		 142{
143 u16 cr;
144
bb90eb00
BW		 145 cr = read_CTRL(drv_data);
146 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
a5f6abd4
WB		 147}
148
149/* Caculate the SPI_BAUD register value based on input HZ */
150static u16 hz_to_spi_baud(u32 speed_hz)
151{
152 u_long sclk = get_sclk();
153 u16 spi_baud = (sclk / (2 * speed_hz));
154
155 if ((sclk % (2 * speed_hz)) > 0)
156 spi_baud++;
157
7513e006
MH		 158 if (spi_baud < MIN_SPI_BAUD_VAL)
159 spi_baud = MIN_SPI_BAUD_VAL;
160
a5f6abd4
WB		 161 return spi_baud;
162}
163
164static int flush(struct driver_data *drv_data)
165{
166 unsigned long limit = loops_per_jiffy << 1;
167
168 /* wait for stop and clear stat */
bb90eb00 169 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
d8c05008 170 cpu_relax();
a5f6abd4 171
bb90eb00 172 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4
WB		 173
174 return limit;
175}
176
fad91c89 177/* Chip select operation functions for cs_change flag */
bb90eb00 178static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 179{
bb90eb00 180 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 181
182 flag |= chip->flag;
183 flag &= ~(chip->flag << 8);
184
bb90eb00 185 write_FLAG(drv_data, flag);
fad91c89
BW		 186}
187
bb90eb00 188static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 189{
bb90eb00 190 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 191
192 flag |= (chip->flag << 8);
193
bb90eb00 194 write_FLAG(drv_data, flag);
62310e51
BW		 195
196 /* Move delay here for consistency */
197 if (chip->cs_chg_udelay)
198 udelay(chip->cs_chg_udelay);
fad91c89
BW		 199}
200
7c4ef094 201#define MAX_SPI_SSEL 7
5fec5b5a 202
a5f6abd4 203/* stop controller and re-config current chip*/
8d20d0a7 204static void restore_state(struct driver_data *drv_data)
a5f6abd4
WB		 205{
206 struct chip_data *chip = drv_data->cur_chip;
12e17c42 207
a5f6abd4 208 /* Clear status and disable clock */
bb90eb00 209 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4 210 bfin_spi_disable(drv_data);
88b40369 211 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
a5f6abd4 212
5fec5b5a 213 /* Load the registers */
bb90eb00 214 write_CTRL(drv_data, chip->ctl_reg);
092e1fda 215 write_BAUD(drv_data, chip->baud);
cc487e73
SZ		 216
217 bfin_spi_enable(drv_data);
07612e5f 218 cs_active(drv_data, chip);
a5f6abd4
WB		 219}
220
221/* used to kick off transfer in rx mode */
bb90eb00 222static unsigned short dummy_read(struct driver_data *drv_data)
a5f6abd4
WB		 223{
224 unsigned short tmp;
bb90eb00 225 tmp = read_RDBR(drv_data);
a5f6abd4
WB		 226 return tmp;
227}
228
229static void null_writer(struct driver_data *drv_data)
230{
231 u8 n_bytes = drv_data->n_bytes;
232
233 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 234 write_TDBR(drv_data, 0);
235 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 236 cpu_relax();
a5f6abd4
WB		 237 drv_data->tx += n_bytes;
238 }
239}
240
241static void null_reader(struct driver_data *drv_data)
242{
243 u8 n_bytes = drv_data->n_bytes;
bb90eb00 244 dummy_read(drv_data);
a5f6abd4
WB		 245
246 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 247 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 248 cpu_relax();
bb90eb00 249 dummy_read(drv_data);
a5f6abd4
WB		 250 drv_data->rx += n_bytes;
251 }
252}
253
254static void u8_writer(struct driver_data *drv_data)
255{
131b17d4 256 dev_dbg(&drv_data->pdev->dev,
bb90eb00 257 "cr8-s is 0x%x\n", read_STAT(drv_data));
cc487e73 258
a5f6abd4 259 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 260 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
261 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 262 cpu_relax();
a5f6abd4
WB		 263 ++drv_data->tx;
264 }
13f3e642
SZ		 265
266 /* poll for SPI completion before return */
267 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
268 cpu_relax();
a5f6abd4
WB		 269}
270
271static void u8_cs_chg_writer(struct driver_data *drv_data)
272{
273 struct chip_data *chip = drv_data->cur_chip;
274
275 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 276 cs_active(drv_data, chip);
a5f6abd4 277
bb90eb00
BW		 278 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
279 while (read_STAT(drv_data) & BIT_STAT_TXS)
d8c05008 280 cpu_relax();
e26aa015
BW		 281 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
282 cpu_relax();
62310e51 283
bb90eb00 284 cs_deactive(drv_data, chip);
5fec5b5a 285
a5f6abd4
WB		 286 ++drv_data->tx;
287 }
a5f6abd4
WB		 288}
289
290static void u8_reader(struct driver_data *drv_data)
291{
131b17d4 292 dev_dbg(&drv_data->pdev->dev,
bb90eb00 293 "cr-8 is 0x%x\n", read_STAT(drv_data));
a5f6abd4 294
3f479a65 295 /* poll for SPI completion before start */
bb90eb00 296 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 297 cpu_relax();
3f479a65 298
a5f6abd4 299 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 300 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 301
bb90eb00 302 dummy_read(drv_data);
cc487e73 303
a5f6abd4 304 while (drv_data->rx < drv_data->rx_end - 1) {
bb90eb00 305 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 306 cpu_relax();
bb90eb00 307 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 308 ++drv_data->rx;
309 }
310
bb90eb00 311 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 312 cpu_relax();
bb90eb00 313 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 314 ++drv_data->rx;
315}
316
317static void u8_cs_chg_reader(struct driver_data *drv_data)
318{
319 struct chip_data *chip = drv_data->cur_chip;
320
e26aa015
BW		 321 while (drv_data->rx < drv_data->rx_end) {
322 cs_active(drv_data, chip);
323 read_RDBR(drv_data); /* kick off */
a5f6abd4 324
e26aa015
BW		 325 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
326 cpu_relax();
327 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
328 cpu_relax();
cc487e73 329
e26aa015 330 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
bb90eb00 331 cs_deactive(drv_data, chip);
5fec5b5a 332
a5f6abd4
WB		 333 ++drv_data->rx;
334 }
a5f6abd4
WB		 335}
336
337static void u8_duplex(struct driver_data *drv_data)
338{
339 /* in duplex mode, clk is triggered by writing of TDBR */
340 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 341 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
4fd432d9 342 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 343 cpu_relax();
bb90eb00 344 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 345 cpu_relax();
bb90eb00 346 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 347 ++drv_data->rx;
348 ++drv_data->tx;
349 }
350}
351
352static void u8_cs_chg_duplex(struct driver_data *drv_data)
353{
354 struct chip_data *chip = drv_data->cur_chip;
355
356 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 357 cs_active(drv_data, chip);
5fec5b5a 358
bb90eb00 359 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
e26aa015
BW		 360
361 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 362 cpu_relax();
bb90eb00 363 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 364 cpu_relax();
bb90eb00 365 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 366
bb90eb00 367 cs_deactive(drv_data, chip);
5fec5b5a 368
a5f6abd4
WB		 369 ++drv_data->rx;
370 ++drv_data->tx;
371 }
a5f6abd4
WB		 372}
373
374static void u16_writer(struct driver_data *drv_data)
375{
131b17d4 376 dev_dbg(&drv_data->pdev->dev,
bb90eb00 377 "cr16 is 0x%x\n", read_STAT(drv_data));
88b40369 378
a5f6abd4 379 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 380 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
381 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 382 cpu_relax();
a5f6abd4
WB		 383 drv_data->tx += 2;
384 }
13f3e642
SZ		 385
386 /* poll for SPI completion before return */
387 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
388 cpu_relax();
a5f6abd4
WB		 389}
390
391static void u16_cs_chg_writer(struct driver_data *drv_data)
392{
393 struct chip_data *chip = drv_data->cur_chip;
394
395 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 396 cs_active(drv_data, chip);
a5f6abd4 397
bb90eb00
BW		 398 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
399 while ((read_STAT(drv_data) & BIT_STAT_TXS))
d8c05008 400 cpu_relax();
13f3e642
SZ		 401 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
402 cpu_relax();
62310e51 403
bb90eb00 404 cs_deactive(drv_data, chip);
5fec5b5a 405
a5f6abd4
WB		 406 drv_data->tx += 2;
407 }
a5f6abd4
WB		 408}
409
410static void u16_reader(struct driver_data *drv_data)
411{
88b40369 412 dev_dbg(&drv_data->pdev->dev,
bb90eb00 413 "cr-16 is 0x%x\n", read_STAT(drv_data));
cc487e73 414
3f479a65 415 /* poll for SPI completion before start */
bb90eb00 416 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 417 cpu_relax();
3f479a65 418
cc487e73 419 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 420 write_TDBR(drv_data, 0xFFFF);
cc487e73 421
bb90eb00 422 dummy_read(drv_data);
a5f6abd4
WB		 423
424 while (drv_data->rx < (drv_data->rx_end - 2)) {
bb90eb00 425 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 426 cpu_relax();
bb90eb00 427 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 428 drv_data->rx += 2;
429 }
430
bb90eb00 431 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 432 cpu_relax();
bb90eb00 433 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 434 drv_data->rx += 2;
435}
436
437static void u16_cs_chg_reader(struct driver_data *drv_data)
438{
439 struct chip_data *chip = drv_data->cur_chip;
440
3f479a65 441 /* poll for SPI completion before start */
bb90eb00 442 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 443 cpu_relax();
3f479a65 444
cc487e73 445 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 446 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 447
bb90eb00
BW		 448 cs_active(drv_data, chip);
449 dummy_read(drv_data);
cc487e73 450
c3061abb 451 while (drv_data->rx < drv_data->rx_end - 2) {
bb90eb00 452 cs_deactive(drv_data, chip);
5fec5b5a 453
bb90eb00 454 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 455 cpu_relax();
bb90eb00
BW		 456 cs_active(drv_data, chip);
457 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 458 drv_data->rx += 2;
459 }
bb90eb00 460 cs_deactive(drv_data, chip);
cc487e73 461
bb90eb00 462 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 463 cpu_relax();
bb90eb00 464 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
cc487e73 465 drv_data->rx += 2;
a5f6abd4
WB		 466}
467
468static void u16_duplex(struct driver_data *drv_data)
469{
470 /* in duplex mode, clk is triggered by writing of TDBR */
471 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 472 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
4fd432d9 473 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 474 cpu_relax();
bb90eb00 475 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 476 cpu_relax();
bb90eb00 477 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 478 drv_data->rx += 2;
479 drv_data->tx += 2;
480 }
481}
482
483static void u16_cs_chg_duplex(struct driver_data *drv_data)
484{
485 struct chip_data *chip = drv_data->cur_chip;
486
487 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 488 cs_active(drv_data, chip);
a5f6abd4 489
bb90eb00 490 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
4fd432d9 491 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 492 cpu_relax();
bb90eb00 493 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
d8c05008 494 cpu_relax();
bb90eb00 495 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
62310e51 496
bb90eb00 497 cs_deactive(drv_data, chip);
5fec5b5a 498
a5f6abd4
WB		 499 drv_data->rx += 2;
500 drv_data->tx += 2;
501 }
a5f6abd4
WB		 502}
503
504/* test if ther is more transfer to be done */
505static void *next_transfer(struct driver_data *drv_data)
506{
507 struct spi_message *msg = drv_data->cur_msg;
508 struct spi_transfer *trans = drv_data->cur_transfer;
509
510 /* Move to next transfer */
511 if (trans->transfer_list.next != &msg->transfers) {
512 drv_data->cur_transfer =
513 list_entry(trans->transfer_list.next,
514 struct spi_transfer, transfer_list);
515 return RUNNING_STATE;
516 } else
517 return DONE_STATE;
518}
519
520/*
521 * caller already set message->status;
522 * dma and pio irqs are blocked give finished message back
523 */
524static void giveback(struct driver_data *drv_data)
525{
fad91c89 526 struct chip_data *chip = drv_data->cur_chip;
a5f6abd4
WB		 527 struct spi_transfer *last_transfer;
528 unsigned long flags;
529 struct spi_message *msg;
530
531 spin_lock_irqsave(&drv_data->lock, flags);
532 msg = drv_data->cur_msg;
533 drv_data->cur_msg = NULL;
534 drv_data->cur_transfer = NULL;
535 drv_data->cur_chip = NULL;
536 queue_work(drv_data->workqueue, &drv_data->pump_messages);
537 spin_unlock_irqrestore(&drv_data->lock, flags);
538
539 last_transfer = list_entry(msg->transfers.prev,
540 struct spi_transfer, transfer_list);
541
542 msg->state = NULL;
543
544 /* disable chip select signal. And not stop spi in autobuffer mode */
545 if (drv_data->tx_dma != 0xFFFF) {
bb90eb00 546 cs_deactive(drv_data, chip);
a5f6abd4
WB		 547 bfin_spi_disable(drv_data);
548 }
549
fad91c89 550 if (!drv_data->cs_change)
bb90eb00 551 cs_deactive(drv_data, chip);
fad91c89 552
a5f6abd4
WB		 553 if (msg->complete)
554 msg->complete(msg->context);
555}
556
88b40369 557static irqreturn_t dma_irq_handler(int irq, void *dev_id)
a5f6abd4 558{
15aafa2f 559 struct driver_data *drv_data = dev_id;
fad91c89 560 struct chip_data *chip = drv_data->cur_chip;
bb90eb00 561 struct spi_message *msg = drv_data->cur_msg;
04b95d2f 562 u16 spistat = read_STAT(drv_data);
a5f6abd4 563
88b40369 564 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
bb90eb00 565 clear_dma_irqstat(drv_data->dma_channel);
a5f6abd4 566
d6fe89b0 567 /* Wait for DMA to complete */
bb90eb00 568 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
d8c05008 569 cpu_relax();
d6fe89b0 570
a5f6abd4 571 /*
d6fe89b0
BW		 572 * wait for the last transaction shifted out. HRM states:
573 * at this point there may still be data in the SPI DMA FIFO waiting
574 * to be transmitted ... software needs to poll TXS in the SPI_STAT
575 * register until it goes low for 2 successive reads
a5f6abd4
WB		 576 */
577 if (drv_data->tx != NULL) {
bb90eb00
BW		 578 while ((read_STAT(drv_data) & TXS) ||
579 (read_STAT(drv_data) & TXS))
d8c05008 580 cpu_relax();
a5f6abd4
WB		 581 }
582
bb90eb00 583 while (!(read_STAT(drv_data) & SPIF))
d8c05008 584 cpu_relax();
a5f6abd4 585
04b95d2f
MF		 586 if (spistat & RBSY) {
587 msg->state = ERROR_STATE;
588 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
589 } else {
590 msg->actual_length += drv_data->len_in_bytes;
a5f6abd4 591
04b95d2f
MF		 592 if (drv_data->cs_change)
593 cs_deactive(drv_data, chip);
fad91c89 594
04b95d2f
MF		 595 /* Move to next transfer */
596 msg->state = next_transfer(drv_data);
597 }
a5f6abd4
WB		 598
599 /* Schedule transfer tasklet */
600 tasklet_schedule(&drv_data->pump_transfers);
601
602 /* free the irq handler before next transfer */
88b40369
BW		 603 dev_dbg(&drv_data->pdev->dev,
604 "disable dma channel irq%d\n",
bb90eb00
BW		 605 drv_data->dma_channel);
606 dma_disable_irq(drv_data->dma_channel);
a5f6abd4
WB		 607
608 return IRQ_HANDLED;
609}
610
611static void pump_transfers(unsigned long data)
612{
613 struct driver_data *drv_data = (struct driver_data *)data;
614 struct spi_message *message = NULL;
615 struct spi_transfer *transfer = NULL;
616 struct spi_transfer *previous = NULL;
617 struct chip_data *chip = NULL;
88b40369
BW		 618 u8 width;
619 u16 cr, dma_width, dma_config;
a5f6abd4 620 u32 tranf_success = 1;
8eeb12e5 621 u8 full_duplex = 0;
a5f6abd4
WB		 622
623 /* Get current state information */
624 message = drv_data->cur_msg;
625 transfer = drv_data->cur_transfer;
626 chip = drv_data->cur_chip;
092e1fda 627
a5f6abd4
WB		 628 /*
629 * if msg is error or done, report it back using complete() callback
630 */
631
632 /* Handle for abort */
633 if (message->state == ERROR_STATE) {
634 message->status = -EIO;
635 giveback(drv_data);
636 return;
637 }
638
639 /* Handle end of message */
640 if (message->state == DONE_STATE) {
641 message->status = 0;
642 giveback(drv_data);
643 return;
644 }
645
646 /* Delay if requested at end of transfer */
647 if (message->state == RUNNING_STATE) {
648 previous = list_entry(transfer->transfer_list.prev,
649 struct spi_transfer, transfer_list);
650 if (previous->delay_usecs)
651 udelay(previous->delay_usecs);
652 }
653
654 /* Setup the transfer state based on the type of transfer */
655 if (flush(drv_data) == 0) {
656 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
657 message->status = -EIO;
658 giveback(drv_data);
659 return;
660 }
661
662 if (transfer->tx_buf != NULL) {
663 drv_data->tx = (void *)transfer->tx_buf;
664 drv_data->tx_end = drv_data->tx + transfer->len;
88b40369
BW		 665 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
666 transfer->tx_buf, drv_data->tx_end);
a5f6abd4
WB		 667 } else {
668 drv_data->tx = NULL;
669 }
670
671 if (transfer->rx_buf != NULL) {
8eeb12e5 672 full_duplex = transfer->tx_buf != NULL;
a5f6abd4
WB		 673 drv_data->rx = transfer->rx_buf;
674 drv_data->rx_end = drv_data->rx + transfer->len;
88b40369
BW		 675 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
676 transfer->rx_buf, drv_data->rx_end);
a5f6abd4
WB		 677 } else {
678 drv_data->rx = NULL;
679 }
680
681 drv_data->rx_dma = transfer->rx_dma;
682 drv_data->tx_dma = transfer->tx_dma;
683 drv_data->len_in_bytes = transfer->len;
fad91c89 684 drv_data->cs_change = transfer->cs_change;
a5f6abd4 685
092e1fda
BW		 686 /* Bits per word setup */
687 switch (transfer->bits_per_word) {
688 case 8:
689 drv_data->n_bytes = 1;
690 width = CFG_SPI_WORDSIZE8;
691 drv_data->read = chip->cs_change_per_word ?
692 u8_cs_chg_reader : u8_reader;
693 drv_data->write = chip->cs_change_per_word ?
694 u8_cs_chg_writer : u8_writer;
695 drv_data->duplex = chip->cs_change_per_word ?
696 u8_cs_chg_duplex : u8_duplex;
697 break;
698
699 case 16:
700 drv_data->n_bytes = 2;
701 width = CFG_SPI_WORDSIZE16;
702 drv_data->read = chip->cs_change_per_word ?
703 u16_cs_chg_reader : u16_reader;
704 drv_data->write = chip->cs_change_per_word ?
705 u16_cs_chg_writer : u16_writer;
706 drv_data->duplex = chip->cs_change_per_word ?
707 u16_cs_chg_duplex : u16_duplex;
708 break;
709
710 default:
711 /* No change, the same as default setting */
712 drv_data->n_bytes = chip->n_bytes;
713 width = chip->width;
714 drv_data->write = drv_data->tx ? chip->write : null_writer;
715 drv_data->read = drv_data->rx ? chip->read : null_reader;
716 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
717 break;
718 }
719 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
720 cr |= (width << 8);
721 write_CTRL(drv_data, cr);
722
a5f6abd4
WB		 723 if (width == CFG_SPI_WORDSIZE16) {
724 drv_data->len = (transfer->len) >> 1;
725 } else {
726 drv_data->len = transfer->len;
727 }
4fb98efa
MF		 728 dev_dbg(&drv_data->pdev->dev,
729 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
131b17d4 730 drv_data->write, chip->write, null_writer);
a5f6abd4
WB		 731
732 /* speed and width has been set on per message */
733 message->state = RUNNING_STATE;
734 dma_config = 0;
735
092e1fda
BW		 736 /* Speed setup (surely valid because already checked) */
737 if (transfer->speed_hz)
738 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
739 else
740 write_BAUD(drv_data, chip->baud);
741
bb90eb00
BW		 742 write_STAT(drv_data, BIT_STAT_CLR);
743 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
744 cs_active(drv_data, chip);
a5f6abd4 745
88b40369
BW		 746 dev_dbg(&drv_data->pdev->dev,
747 "now pumping a transfer: width is %d, len is %d\n",
748 width, transfer->len);
a5f6abd4
WB		 749
750 /*
8cf5858c
VM		 751 * Try to map dma buffer and do a dma transfer. If successful use,
752 * different way to r/w according to the enable_dma settings and if
753 * we are not doing a full duplex transfer (since the hardware does
754 * not support full duplex DMA transfers).
a5f6abd4 755 */
8eeb12e5
VM		 756 if (!full_duplex && drv_data->cur_chip->enable_dma
757 && drv_data->len > 6) {
a5f6abd4 758
bb90eb00
BW		 759 disable_dma(drv_data->dma_channel);
760 clear_dma_irqstat(drv_data->dma_channel);
07612e5f 761 bfin_spi_disable(drv_data);
a5f6abd4
WB		 762
763 /* config dma channel */
88b40369 764 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
a5f6abd4 765 if (width == CFG_SPI_WORDSIZE16) {
bb90eb00
BW		 766 set_dma_x_count(drv_data->dma_channel, drv_data->len);
767 set_dma_x_modify(drv_data->dma_channel, 2);
a5f6abd4
WB		 768 dma_width = WDSIZE_16;
769 } else {
bb90eb00
BW		 770 set_dma_x_count(drv_data->dma_channel, drv_data->len);
771 set_dma_x_modify(drv_data->dma_channel, 1);
a5f6abd4
WB		 772 dma_width = WDSIZE_8;
773 }
774
3f479a65 775 /* poll for SPI completion before start */
bb90eb00 776 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
d8c05008 777 cpu_relax();
3f479a65 778
a5f6abd4
WB		 779 /* dirty hack for autobuffer DMA mode */
780 if (drv_data->tx_dma == 0xFFFF) {
88b40369
BW		 781 dev_dbg(&drv_data->pdev->dev,
782 "doing autobuffer DMA out.\n");
a5f6abd4
WB		 783
784 /* no irq in autobuffer mode */
785 dma_config =
786 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
bb90eb00
BW		 787 set_dma_config(drv_data->dma_channel, dma_config);
788 set_dma_start_addr(drv_data->dma_channel,
a32c691d 789 (unsigned long)drv_data->tx);
bb90eb00 790 enable_dma(drv_data->dma_channel);
a5f6abd4 791
07612e5f
SZ		 792 /* start SPI transfer */
793 write_CTRL(drv_data,
794 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
795
796 /* just return here, there can only be one transfer
797 * in this mode
798 */
a5f6abd4
WB		 799 message->status = 0;
800 giveback(drv_data);
801 return;
802 }
803
804 /* In dma mode, rx or tx must be NULL in one transfer */
805 if (drv_data->rx != NULL) {
806 /* set transfer mode, and enable SPI */
88b40369 807 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
a5f6abd4 808
8cf5858c
VM		 809 /* invalidate caches, if needed */
810 if (bfin_addr_dcachable((unsigned long) drv_data->rx))
811 invalidate_dcache_range((unsigned long) drv_data->rx,
812 (unsigned long) (drv_data->rx +
ace32865 813 drv_data->len_in_bytes));
8cf5858c 814
a5f6abd4 815 /* clear tx reg soformer data is not shifted out */
bb90eb00 816 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 817
bb90eb00 818 set_dma_x_count(drv_data->dma_channel, drv_data->len);
a5f6abd4
WB		 819
820 /* start dma */
bb90eb00 821 dma_enable_irq(drv_data->dma_channel);
a5f6abd4 822 dma_config = (WNR | RESTART | dma_width | DI_EN);
bb90eb00
BW		 823 set_dma_config(drv_data->dma_channel, dma_config);
824 set_dma_start_addr(drv_data->dma_channel,
a32c691d 825 (unsigned long)drv_data->rx);
bb90eb00 826 enable_dma(drv_data->dma_channel);
a5f6abd4 827
07612e5f
SZ		 828 /* start SPI transfer */
829 write_CTRL(drv_data,
830 (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
831
a5f6abd4 832 } else if (drv_data->tx != NULL) {
88b40369 833 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
a5f6abd4 834
8cf5858c
VM		 835 /* flush caches, if needed */
836 if (bfin_addr_dcachable((unsigned long) drv_data->tx))
837 flush_dcache_range((unsigned long) drv_data->tx,
838 (unsigned long) (drv_data->tx +
ace32865 839 drv_data->len_in_bytes));
8cf5858c 840
a5f6abd4 841 /* start dma */
bb90eb00 842 dma_enable_irq(drv_data->dma_channel);
a5f6abd4 843 dma_config = (RESTART | dma_width | DI_EN);
bb90eb00
BW		 844 set_dma_config(drv_data->dma_channel, dma_config);
845 set_dma_start_addr(drv_data->dma_channel,
a32c691d 846 (unsigned long)drv_data->tx);
bb90eb00 847 enable_dma(drv_data->dma_channel);
07612e5f
SZ		 848
849 /* start SPI transfer */
850 write_CTRL(drv_data,
851 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
a5f6abd4
WB		 852 }
853 } else {
854 /* IO mode write then read */
88b40369 855 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
a5f6abd4 856
8eeb12e5 857 if (full_duplex) {
a5f6abd4
WB		 858 /* full duplex mode */
859 BUG_ON((drv_data->tx_end - drv_data->tx) !=
860 (drv_data->rx_end - drv_data->rx));
88b40369
BW		 861 dev_dbg(&drv_data->pdev->dev,
862 "IO duplex: cr is 0x%x\n", cr);
a5f6abd4 863
cc487e73 864 /* set SPI transfer mode */
bb90eb00 865 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 866
867 drv_data->duplex(drv_data);
868
869 if (drv_data->tx != drv_data->tx_end)
870 tranf_success = 0;
871 } else if (drv_data->tx != NULL) {
872 /* write only half duplex */
131b17d4 873 dev_dbg(&drv_data->pdev->dev,
88b40369 874 "IO write: cr is 0x%x\n", cr);
a5f6abd4 875
cc487e73 876 /* set SPI transfer mode */
bb90eb00 877 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 878
879 drv_data->write(drv_data);
880
881 if (drv_data->tx != drv_data->tx_end)
882 tranf_success = 0;
883 } else if (drv_data->rx != NULL) {
884 /* read only half duplex */
131b17d4 885 dev_dbg(&drv_data->pdev->dev,
88b40369 886 "IO read: cr is 0x%x\n", cr);
a5f6abd4 887
cc487e73 888 /* set SPI transfer mode */
bb90eb00 889 write_CTRL(drv_data, (cr | CFG_SPI_READ));
a5f6abd4
WB		 890
891 drv_data->read(drv_data);
892 if (drv_data->rx != drv_data->rx_end)
893 tranf_success = 0;
894 }
895
896 if (!tranf_success) {
131b17d4 897 dev_dbg(&drv_data->pdev->dev,
88b40369 898 "IO write error!\n");
a5f6abd4
WB		 899 message->state = ERROR_STATE;
900 } else {
901 /* Update total byte transfered */
ace32865 902 message->actual_length += drv_data->len_in_bytes;
a5f6abd4
WB		 903
904 /* Move to next transfer of this msg */
905 message->state = next_transfer(drv_data);
906 }
907
908 /* Schedule next transfer tasklet */
909 tasklet_schedule(&drv_data->pump_transfers);
910
911 }
912}
913
914/* pop a msg from queue and kick off real transfer */
915static void pump_messages(struct work_struct *work)
916{
131b17d4 917 struct driver_data *drv_data;
a5f6abd4
WB		 918 unsigned long flags;
919
131b17d4
BW		 920 drv_data = container_of(work, struct driver_data, pump_messages);
921
a5f6abd4
WB		 922 /* Lock queue and check for queue work */
923 spin_lock_irqsave(&drv_data->lock, flags);
924 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
925 /* pumper kicked off but no work to do */
926 drv_data->busy = 0;
927 spin_unlock_irqrestore(&drv_data->lock, flags);
928 return;
929 }
930
931 /* Make sure we are not already running a message */
932 if (drv_data->cur_msg) {
933 spin_unlock_irqrestore(&drv_data->lock, flags);
934 return;
935 }
936
937 /* Extract head of queue */
938 drv_data->cur_msg = list_entry(drv_data->queue.next,
939 struct spi_message, queue);
5fec5b5a
BW		 940
941 /* Setup the SSP using the per chip configuration */
942 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
8d20d0a7 943 restore_state(drv_data);
5fec5b5a 944
a5f6abd4
WB		 945 list_del_init(&drv_data->cur_msg->queue);
946
947 /* Initial message state */
948 drv_data->cur_msg->state = START_STATE;
949 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
950 struct spi_transfer, transfer_list);
951
5fec5b5a
BW		 952 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
953 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
954 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
955 drv_data->cur_chip->ctl_reg);
131b17d4
BW		 956
957 dev_dbg(&drv_data->pdev->dev,
88b40369
BW		 958 "the first transfer len is %d\n",
959 drv_data->cur_transfer->len);
a5f6abd4
WB		 960
961 /* Mark as busy and launch transfers */
962 tasklet_schedule(&drv_data->pump_transfers);
963
964 drv_data->busy = 1;
965 spin_unlock_irqrestore(&drv_data->lock, flags);
966}
967
968/*
969 * got a msg to transfer, queue it in drv_data->queue.
970 * And kick off message pumper
971 */
972static int transfer(struct spi_device *spi, struct spi_message *msg)
973{
974 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
975 unsigned long flags;
976
977 spin_lock_irqsave(&drv_data->lock, flags);
978
979 if (drv_data->run == QUEUE_STOPPED) {
980 spin_unlock_irqrestore(&drv_data->lock, flags);
981 return -ESHUTDOWN;
982 }
983
984 msg->actual_length = 0;
985 msg->status = -EINPROGRESS;
986 msg->state = START_STATE;
987
88b40369 988 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
a5f6abd4
WB		 989 list_add_tail(&msg->queue, &drv_data->queue);
990
991 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
992 queue_work(drv_data->workqueue, &drv_data->pump_messages);
993
994 spin_unlock_irqrestore(&drv_data->lock, flags);
995
996 return 0;
997}
998
12e17c42
SZ		 999#define MAX_SPI_SSEL 7
1000
1001static u16 ssel[3][MAX_SPI_SSEL] = {
1002 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1003 P_SPI0_SSEL4, P_SPI0_SSEL5,
1004 P_SPI0_SSEL6, P_SPI0_SSEL7},
1005
1006 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1007 P_SPI1_SSEL4, P_SPI1_SSEL5,
1008 P_SPI1_SSEL6, P_SPI1_SSEL7},
1009
1010 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1011 P_SPI2_SSEL4, P_SPI2_SSEL5,
1012 P_SPI2_SSEL6, P_SPI2_SSEL7},
1013};
1014
a5f6abd4
WB		 1015/* first setup for new devices */
1016static int setup(struct spi_device *spi)
1017{
1018 struct bfin5xx_spi_chip *chip_info = NULL;
1019 struct chip_data *chip;
1020 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1021 u8 spi_flg;
1022
1023 /* Abort device setup if requested features are not supported */
1024 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1025 dev_err(&spi->dev, "requested mode not fully supported\n");
1026 return -EINVAL;
1027 }
1028
1029 /* Zero (the default) here means 8 bits */
1030 if (!spi->bits_per_word)
1031 spi->bits_per_word = 8;
1032
1033 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1034 return -EINVAL;
1035
1036 /* Only alloc (or use chip_info) on first setup */
1037 chip = spi_get_ctldata(spi);
1038 if (chip == NULL) {
1039 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1040 if (!chip)
1041 return -ENOMEM;
1042
1043 chip->enable_dma = 0;
1044 chip_info = spi->controller_data;
1045 }
1046
1047 /* chip_info isn't always needed */
1048 if (chip_info) {
2ed35516
MF		 1049 /* Make sure people stop trying to set fields via ctl_reg
1050 * when they should actually be using common SPI framework.
1051 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1052 * Not sure if a user actually needs/uses any of these,
1053 * but let's assume (for now) they do.
1054 */
1055 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1056 dev_err(&spi->dev, "do not set bits in ctl_reg "
1057 "that the SPI framework manages\n");
1058 return -EINVAL;
1059 }
1060
a5f6abd4
WB		 1061 chip->enable_dma = chip_info->enable_dma != 0
1062 && drv_data->master_info->enable_dma;
1063 chip->ctl_reg = chip_info->ctl_reg;
1064 chip->bits_per_word = chip_info->bits_per_word;
1065 chip->cs_change_per_word = chip_info->cs_change_per_word;
1066 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1067 }
1068
1069 /* translate common spi framework into our register */
1070 if (spi->mode & SPI_CPOL)
1071 chip->ctl_reg |= CPOL;
1072 if (spi->mode & SPI_CPHA)
1073 chip->ctl_reg |= CPHA;
1074 if (spi->mode & SPI_LSB_FIRST)
1075 chip->ctl_reg |= LSBF;
1076 /* we dont support running in slave mode (yet?) */
1077 chip->ctl_reg |= MSTR;
1078
1079 /*
1080 * if any one SPI chip is registered and wants DMA, request the
1081 * DMA channel for it
1082 */
bb90eb00 1083 if (chip->enable_dma && !drv_data->dma_requested) {
a5f6abd4 1084 /* register dma irq handler */
bb90eb00 1085 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
88b40369
BW		 1086 dev_dbg(&spi->dev,
1087 "Unable to request BlackFin SPI DMA channel\n");
a5f6abd4
WB		 1088 return -ENODEV;
1089 }
bb90eb00
BW		 1090 if (set_dma_callback(drv_data->dma_channel,
1091 (void *)dma_irq_handler, drv_data) < 0) {
88b40369 1092 dev_dbg(&spi->dev, "Unable to set dma callback\n");
a5f6abd4
WB		 1093 return -EPERM;
1094 }
bb90eb00
BW		 1095 dma_disable_irq(drv_data->dma_channel);
1096 drv_data->dma_requested = 1;
a5f6abd4
WB		 1097 }
1098
1099 /*
1100 * Notice: for blackfin, the speed_hz is the value of register
1101 * SPI_BAUD, not the real baudrate
1102 */
1103 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1104 spi_flg = ~(1 << (spi->chip_select));
1105 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1106 chip->chip_select_num = spi->chip_select;
1107
1108 switch (chip->bits_per_word) {
1109 case 8:
1110 chip->n_bytes = 1;
1111 chip->width = CFG_SPI_WORDSIZE8;
1112 chip->read = chip->cs_change_per_word ?
1113 u8_cs_chg_reader : u8_reader;
1114 chip->write = chip->cs_change_per_word ?
1115 u8_cs_chg_writer : u8_writer;
1116 chip->duplex = chip->cs_change_per_word ?
1117 u8_cs_chg_duplex : u8_duplex;
1118 break;
1119
1120 case 16:
1121 chip->n_bytes = 2;
1122 chip->width = CFG_SPI_WORDSIZE16;
1123 chip->read = chip->cs_change_per_word ?
1124 u16_cs_chg_reader : u16_reader;
1125 chip->write = chip->cs_change_per_word ?
1126 u16_cs_chg_writer : u16_writer;
1127 chip->duplex = chip->cs_change_per_word ?
1128 u16_cs_chg_duplex : u16_duplex;
1129 break;
1130
1131 default:
1132 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1133 chip->bits_per_word);
1134 kfree(chip);
1135 return -ENODEV;
1136 }
1137
898eb71c 1138 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
a5f6abd4 1139 spi->modalias, chip->width, chip->enable_dma);
88b40369 1140 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
a5f6abd4
WB		 1141 chip->ctl_reg, chip->flag);
1142
1143 spi_set_ctldata(spi, chip);
1144
12e17c42
SZ		 1145 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1146 if ((chip->chip_select_num > 0)
1147 && (chip->chip_select_num <= spi->master->num_chipselect))
1148 peripheral_request(ssel[spi->master->bus_num]
aab0d83e 1149 [chip->chip_select_num-1], spi->modalias);
12e17c42 1150
07612e5f
SZ		 1151 cs_deactive(drv_data, chip);
1152
a5f6abd4
WB		 1153 return 0;
1154}
1155
1156/*
1157 * callback for spi framework.
1158 * clean driver specific data
1159 */
88b40369 1160static void cleanup(struct spi_device *spi)
a5f6abd4 1161{
27bb9e79 1162 struct chip_data *chip = spi_get_ctldata(spi);
a5f6abd4 1163
12e17c42
SZ		 1164 if ((chip->chip_select_num > 0)
1165 && (chip->chip_select_num <= spi->master->num_chipselect))
1166 peripheral_free(ssel[spi->master->bus_num]
1167 [chip->chip_select_num-1]);
1168
a5f6abd4
WB		 1169 kfree(chip);
1170}
1171
1172static inline int init_queue(struct driver_data *drv_data)
1173{
1174 INIT_LIST_HEAD(&drv_data->queue);
1175 spin_lock_init(&drv_data->lock);
1176
1177 drv_data->run = QUEUE_STOPPED;
1178 drv_data->busy = 0;
1179
1180 /* init transfer tasklet */
1181 tasklet_init(&drv_data->pump_transfers,
1182 pump_transfers, (unsigned long)drv_data);
1183
1184 /* init messages workqueue */
1185 INIT_WORK(&drv_data->pump_messages, pump_messages);
6c7377ab
KS		 1186 drv_data->workqueue = create_singlethread_workqueue(
1187 dev_name(drv_data->master->dev.parent));
a5f6abd4
WB		 1188 if (drv_data->workqueue == NULL)
1189 return -EBUSY;
1190
1191 return 0;
1192}
1193
1194static inline int start_queue(struct driver_data *drv_data)
1195{
1196 unsigned long flags;
1197
1198 spin_lock_irqsave(&drv_data->lock, flags);
1199
1200 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1201 spin_unlock_irqrestore(&drv_data->lock, flags);
1202 return -EBUSY;
1203 }
1204
1205 drv_data->run = QUEUE_RUNNING;
1206 drv_data->cur_msg = NULL;
1207 drv_data->cur_transfer = NULL;
1208 drv_data->cur_chip = NULL;
1209 spin_unlock_irqrestore(&drv_data->lock, flags);
1210
1211 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1212
1213 return 0;
1214}
1215
1216static inline int stop_queue(struct driver_data *drv_data)
1217{
1218 unsigned long flags;
1219 unsigned limit = 500;
1220 int status = 0;
1221
1222 spin_lock_irqsave(&drv_data->lock, flags);
1223
1224 /*
1225 * This is a bit lame, but is optimized for the common execution path.
1226 * A wait_queue on the drv_data->busy could be used, but then the common
1227 * execution path (pump_messages) would be required to call wake_up or
1228 * friends on every SPI message. Do this instead
1229 */
1230 drv_data->run = QUEUE_STOPPED;
1231 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1232 spin_unlock_irqrestore(&drv_data->lock, flags);
1233 msleep(10);
1234 spin_lock_irqsave(&drv_data->lock, flags);
1235 }
1236
1237 if (!list_empty(&drv_data->queue) || drv_data->busy)
1238 status = -EBUSY;
1239
1240 spin_unlock_irqrestore(&drv_data->lock, flags);
1241
1242 return status;
1243}
1244
1245static inline int destroy_queue(struct driver_data *drv_data)
1246{
1247 int status;
1248
1249 status = stop_queue(drv_data);
1250 if (status != 0)
1251 return status;
1252
1253 destroy_workqueue(drv_data->workqueue);
1254
1255 return 0;
1256}
1257
1258static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1259{
1260 struct device *dev = &pdev->dev;
1261 struct bfin5xx_spi_master *platform_info;
1262 struct spi_master *master;
1263 struct driver_data *drv_data = 0;
a32c691d 1264 struct resource *res;
a5f6abd4
WB		 1265 int status = 0;
1266
1267 platform_info = dev->platform_data;
1268
1269 /* Allocate master with space for drv_data */
1270 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1271 if (!master) {
1272 dev_err(&pdev->dev, "can not alloc spi_master\n");
1273 return -ENOMEM;
1274 }
131b17d4 1275
a5f6abd4
WB		 1276 drv_data = spi_master_get_devdata(master);
1277 drv_data->master = master;
1278 drv_data->master_info = platform_info;
1279 drv_data->pdev = pdev;
003d9226 1280 drv_data->pin_req = platform_info->pin_req;
a5f6abd4
WB		 1281
1282 master->bus_num = pdev->id;
1283 master->num_chipselect = platform_info->num_chipselect;
1284 master->cleanup = cleanup;
1285 master->setup = setup;
1286 master->transfer = transfer;
1287
a32c691d
BW		 1288 /* Find and map our resources */
1289 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1290 if (res == NULL) {
1291 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1292 status = -ENOENT;
1293 goto out_error_get_res;
1294 }
1295
f452126c
BW		 1296 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1297 if (drv_data->regs_base == NULL) {
a32c691d
BW		 1298 dev_err(dev, "Cannot map IO\n");
1299 status = -ENXIO;
1300 goto out_error_ioremap;
1301 }
1302
bb90eb00
BW		 1303 drv_data->dma_channel = platform_get_irq(pdev, 0);
1304 if (drv_data->dma_channel < 0) {
a32c691d
BW		 1305 dev_err(dev, "No DMA channel specified\n");
1306 status = -ENOENT;
1307 goto out_error_no_dma_ch;
1308 }
1309
a5f6abd4
WB		 1310 /* Initial and start queue */
1311 status = init_queue(drv_data);
1312 if (status != 0) {
a32c691d 1313 dev_err(dev, "problem initializing queue\n");
a5f6abd4
WB		 1314 goto out_error_queue_alloc;
1315 }
a32c691d 1316
a5f6abd4
WB		 1317 status = start_queue(drv_data);
1318 if (status != 0) {
a32c691d 1319 dev_err(dev, "problem starting queue\n");
a5f6abd4
WB		 1320 goto out_error_queue_alloc;
1321 }
1322
f9e522ca
VM		 1323 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1324 if (status != 0) {
1325 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1326 goto out_error_queue_alloc;
1327 }
1328
a5f6abd4
WB		 1329 /* Register with the SPI framework */
1330 platform_set_drvdata(pdev, drv_data);
1331 status = spi_register_master(master);
1332 if (status != 0) {
a32c691d 1333 dev_err(dev, "problem registering spi master\n");
a5f6abd4
WB		 1334 goto out_error_queue_alloc;
1335 }
a32c691d 1336
f452126c 1337 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
bb90eb00
BW		 1338 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1339 drv_data->dma_channel);
a5f6abd4
WB		 1340 return status;
1341
cc2f81a6 1342out_error_queue_alloc:
a5f6abd4 1343 destroy_queue(drv_data);
a32c691d 1344out_error_no_dma_ch:
bb90eb00 1345 iounmap((void *) drv_data->regs_base);
a32c691d
BW		 1346out_error_ioremap:
1347out_error_get_res:
a5f6abd4 1348 spi_master_put(master);
cc2f81a6 1349
a5f6abd4
WB		 1350 return status;
1351}
1352
1353/* stop hardware and remove the driver */
1354static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1355{
1356 struct driver_data *drv_data = platform_get_drvdata(pdev);
1357 int status = 0;
1358
1359 if (!drv_data)
1360 return 0;
1361
1362 /* Remove the queue */
1363 status = destroy_queue(drv_data);
1364 if (status != 0)
1365 return status;
1366
1367 /* Disable the SSP at the peripheral and SOC level */
1368 bfin_spi_disable(drv_data);
1369
1370 /* Release DMA */
1371 if (drv_data->master_info->enable_dma) {
bb90eb00
BW		 1372 if (dma_channel_active(drv_data->dma_channel))
1373 free_dma(drv_data->dma_channel);
a5f6abd4
WB		 1374 }
1375
1376 /* Disconnect from the SPI framework */
1377 spi_unregister_master(drv_data->master);
1378
003d9226 1379 peripheral_free_list(drv_data->pin_req);
cc2f81a6 1380
a5f6abd4
WB		 1381 /* Prevent double remove */
1382 platform_set_drvdata(pdev, NULL);
1383
1384 return 0;
1385}
1386
1387#ifdef CONFIG_PM
1388static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1389{
1390 struct driver_data *drv_data = platform_get_drvdata(pdev);
1391 int status = 0;
1392
1393 status = stop_queue(drv_data);
1394 if (status != 0)
1395 return status;
1396
1397 /* stop hardware */
1398 bfin_spi_disable(drv_data);
1399
1400 return 0;
1401}
1402
1403static int bfin5xx_spi_resume(struct platform_device *pdev)
1404{
1405 struct driver_data *drv_data = platform_get_drvdata(pdev);
1406 int status = 0;
1407
1408 /* Enable the SPI interface */
1409 bfin_spi_enable(drv_data);
1410
1411 /* Start the queue running */
1412 status = start_queue(drv_data);
1413 if (status != 0) {
1414 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1415 return status;
1416 }
1417
1418 return 0;
1419}
1420#else
1421#define bfin5xx_spi_suspend NULL
1422#define bfin5xx_spi_resume NULL
1423#endif /* CONFIG_PM */
1424
7e38c3c4 1425MODULE_ALIAS("platform:bfin-spi");
a5f6abd4 1426static struct platform_driver bfin5xx_spi_driver = {
fc3ba952 1427 .driver = {
a32c691d 1428 .name = DRV_NAME,
88b40369
BW		 1429 .owner = THIS_MODULE,
1430 },
1431 .suspend = bfin5xx_spi_suspend,
1432 .resume = bfin5xx_spi_resume,
1433 .remove = __devexit_p(bfin5xx_spi_remove),
a5f6abd4
WB		 1434};
1435
1436static int __init bfin5xx_spi_init(void)
1437{
88b40369 1438 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
a5f6abd4 1439}
a5f6abd4
WB		 1440module_init(bfin5xx_spi_init);
1441
1442static void __exit bfin5xx_spi_exit(void)
1443{
1444 platform_driver_unregister(&bfin5xx_spi_driver);
1445}
a5f6abd4 1446module_exit(bfin5xx_spi_exit);
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