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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[net-next-2.6.git] / drivers / spi / amba-pl022.c
CommitLineData
b43d65f7
LW		 1/*
2 * drivers/spi/amba-pl022.c
3 *
4 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
5 *
6 * Copyright (C) 2008-2009 ST-Ericsson AB
7 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
8 *
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 *
11 * Initial version inspired by:
12 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
13 * Initial adoption to PL022 by:
14 * Sachin Verma <sachin.verma@st.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 */
26
27/*
28 * TODO:
29 * - add timeout on polled transfers
30 * - add generic DMA framework support
31 */
32
33#include <linux/init.h>
34#include <linux/module.h>
35#include <linux/device.h>
36#include <linux/ioport.h>
37#include <linux/errno.h>
38#include <linux/interrupt.h>
39#include <linux/spi/spi.h>
40#include <linux/workqueue.h>
b43d65f7
LW		 41#include <linux/delay.h>
42#include <linux/clk.h>
43#include <linux/err.h>
44#include <linux/amba/bus.h>
45#include <linux/amba/pl022.h>
46#include <linux/io.h>
5a0e3ad6 47#include <linux/slab.h>
b43d65f7
LW		 48
49/*
50 * This macro is used to define some register default values.
51 * reg is masked with mask, the OR:ed with an (again masked)
52 * val shifted sb steps to the left.
53 */
54#define SSP_WRITE_BITS(reg, val, mask, sb) \
55 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
56
57/*
58 * This macro is also used to define some default values.
59 * It will just shift val by sb steps to the left and mask
60 * the result with mask.
61 */
62#define GEN_MASK_BITS(val, mask, sb) \
63 (((val)<<(sb)) & (mask))
64
65#define DRIVE_TX 0
66#define DO_NOT_DRIVE_TX 1
67
68#define DO_NOT_QUEUE_DMA 0
69#define QUEUE_DMA 1
70
71#define RX_TRANSFER 1
72#define TX_TRANSFER 2
73
74/*
75 * Macros to access SSP Registers with their offsets
76 */
77#define SSP_CR0(r) (r + 0x000)
78#define SSP_CR1(r) (r + 0x004)
79#define SSP_DR(r) (r + 0x008)
80#define SSP_SR(r) (r + 0x00C)
81#define SSP_CPSR(r) (r + 0x010)
82#define SSP_IMSC(r) (r + 0x014)
83#define SSP_RIS(r) (r + 0x018)
84#define SSP_MIS(r) (r + 0x01C)
85#define SSP_ICR(r) (r + 0x020)
86#define SSP_DMACR(r) (r + 0x024)
87#define SSP_ITCR(r) (r + 0x080)
88#define SSP_ITIP(r) (r + 0x084)
89#define SSP_ITOP(r) (r + 0x088)
90#define SSP_TDR(r) (r + 0x08C)
91
92#define SSP_PID0(r) (r + 0xFE0)
93#define SSP_PID1(r) (r + 0xFE4)
94#define SSP_PID2(r) (r + 0xFE8)
95#define SSP_PID3(r) (r + 0xFEC)
96
97#define SSP_CID0(r) (r + 0xFF0)
98#define SSP_CID1(r) (r + 0xFF4)
99#define SSP_CID2(r) (r + 0xFF8)
100#define SSP_CID3(r) (r + 0xFFC)
101
102/*
103 * SSP Control Register 0 - SSP_CR0
104 */
556f4aeb
LW		 105#define SSP_CR0_MASK_DSS (0x0FUL << 0)
106#define SSP_CR0_MASK_FRF (0x3UL << 4)
b43d65f7
LW		 107#define SSP_CR0_MASK_SPO (0x1UL << 6)
108#define SSP_CR0_MASK_SPH (0x1UL << 7)
109#define SSP_CR0_MASK_SCR (0xFFUL << 8)
556f4aeb
LW		 110
111/*
112 * The ST version of this block moves som bits
113 * in SSP_CR0 and extends it to 32 bits
114 */
115#define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
116#define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
117#define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
118#define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
119
b43d65f7
LW		 120
121/*
122 * SSP Control Register 0 - SSP_CR1
123 */
124#define SSP_CR1_MASK_LBM (0x1UL << 0)
125#define SSP_CR1_MASK_SSE (0x1UL << 1)
126#define SSP_CR1_MASK_MS (0x1UL << 2)
127#define SSP_CR1_MASK_SOD (0x1UL << 3)
b43d65f7
LW		 128
129/*
556f4aeb
LW		 130 * The ST version of this block adds some bits
131 * in SSP_CR1
b43d65f7 132 */
556f4aeb
LW		 133#define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
134#define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
135#define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
136#define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
137#define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
781c7b12
LW		 138/* This one is only in the PL023 variant */
139#define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
b43d65f7
LW		 140
141/*
142 * SSP Status Register - SSP_SR
143 */
144#define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
145#define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
146#define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
556f4aeb 147#define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
b43d65f7
LW		 148#define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
149
150/*
151 * SSP Clock Prescale Register - SSP_CPSR
152 */
153#define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
154
155/*
156 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
157 */
158#define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
159#define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
160#define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
161#define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
162
163/*
164 * SSP Raw Interrupt Status Register - SSP_RIS
165 */
166/* Receive Overrun Raw Interrupt status */
167#define SSP_RIS_MASK_RORRIS (0x1UL << 0)
168/* Receive Timeout Raw Interrupt status */
169#define SSP_RIS_MASK_RTRIS (0x1UL << 1)
170/* Receive FIFO Raw Interrupt status */
171#define SSP_RIS_MASK_RXRIS (0x1UL << 2)
172/* Transmit FIFO Raw Interrupt status */
173#define SSP_RIS_MASK_TXRIS (0x1UL << 3)
174
175/*
176 * SSP Masked Interrupt Status Register - SSP_MIS
177 */
178/* Receive Overrun Masked Interrupt status */
179#define SSP_MIS_MASK_RORMIS (0x1UL << 0)
180/* Receive Timeout Masked Interrupt status */
181#define SSP_MIS_MASK_RTMIS (0x1UL << 1)
182/* Receive FIFO Masked Interrupt status */
183#define SSP_MIS_MASK_RXMIS (0x1UL << 2)
184/* Transmit FIFO Masked Interrupt status */
185#define SSP_MIS_MASK_TXMIS (0x1UL << 3)
186
187/*
188 * SSP Interrupt Clear Register - SSP_ICR
189 */
190/* Receive Overrun Raw Clear Interrupt bit */
191#define SSP_ICR_MASK_RORIC (0x1UL << 0)
192/* Receive Timeout Clear Interrupt bit */
193#define SSP_ICR_MASK_RTIC (0x1UL << 1)
194
195/*
196 * SSP DMA Control Register - SSP_DMACR
197 */
198/* Receive DMA Enable bit */
199#define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
200/* Transmit DMA Enable bit */
201#define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
202
203/*
204 * SSP Integration Test control Register - SSP_ITCR
205 */
206#define SSP_ITCR_MASK_ITEN (0x1UL << 0)
207#define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
208
209/*
210 * SSP Integration Test Input Register - SSP_ITIP
211 */
212#define ITIP_MASK_SSPRXD (0x1UL << 0)
213#define ITIP_MASK_SSPFSSIN (0x1UL << 1)
214#define ITIP_MASK_SSPCLKIN (0x1UL << 2)
215#define ITIP_MASK_RXDMAC (0x1UL << 3)
216#define ITIP_MASK_TXDMAC (0x1UL << 4)
217#define ITIP_MASK_SSPTXDIN (0x1UL << 5)
218
219/*
220 * SSP Integration Test output Register - SSP_ITOP
221 */
222#define ITOP_MASK_SSPTXD (0x1UL << 0)
223#define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
224#define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
225#define ITOP_MASK_SSPOEn (0x1UL << 3)
226#define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
227#define ITOP_MASK_RORINTR (0x1UL << 5)
228#define ITOP_MASK_RTINTR (0x1UL << 6)
229#define ITOP_MASK_RXINTR (0x1UL << 7)
230#define ITOP_MASK_TXINTR (0x1UL << 8)
231#define ITOP_MASK_INTR (0x1UL << 9)
232#define ITOP_MASK_RXDMABREQ (0x1UL << 10)
233#define ITOP_MASK_RXDMASREQ (0x1UL << 11)
234#define ITOP_MASK_TXDMABREQ (0x1UL << 12)
235#define ITOP_MASK_TXDMASREQ (0x1UL << 13)
236
237/*
238 * SSP Test Data Register - SSP_TDR
239 */
556f4aeb 240#define TDR_MASK_TESTDATA (0xFFFFFFFF)
b43d65f7
LW		 241
242/*
243 * Message State
244 * we use the spi_message.state (void *) pointer to
245 * hold a single state value, that's why all this
246 * (void *) casting is done here.
247 */
556f4aeb
LW		 248#define STATE_START ((void *) 0)
249#define STATE_RUNNING ((void *) 1)
250#define STATE_DONE ((void *) 2)
251#define STATE_ERROR ((void *) -1)
b43d65f7
LW		 252
253/*
254 * Queue State
255 */
556f4aeb
LW		 256#define QUEUE_RUNNING (0)
257#define QUEUE_STOPPED (1)
b43d65f7
LW		 258/*
259 * SSP State - Whether Enabled or Disabled
260 */
556f4aeb
LW		 261#define SSP_DISABLED (0)
262#define SSP_ENABLED (1)
b43d65f7
LW		 263
264/*
265 * SSP DMA State - Whether DMA Enabled or Disabled
266 */
556f4aeb
LW		 267#define SSP_DMA_DISABLED (0)
268#define SSP_DMA_ENABLED (1)
b43d65f7
LW		 269
270/*
271 * SSP Clock Defaults
272 */
556f4aeb
LW		 273#define SSP_DEFAULT_CLKRATE 0x2
274#define SSP_DEFAULT_PRESCALE 0x40
b43d65f7
LW		 275
276/*
277 * SSP Clock Parameter ranges
278 */
279#define CPSDVR_MIN 0x02
280#define CPSDVR_MAX 0xFE
281#define SCR_MIN 0x00
282#define SCR_MAX 0xFF
283
284/*
285 * SSP Interrupt related Macros
286 */
287#define DEFAULT_SSP_REG_IMSC 0x0UL
288#define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
289#define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
290
291#define CLEAR_ALL_INTERRUPTS 0x3
292
293
294/*
295 * The type of reading going on on this chip
296 */
297enum ssp_reading {
298 READING_NULL,
299 READING_U8,
300 READING_U16,
301 READING_U32
302};
303
304/**
305 * The type of writing going on on this chip
306 */
307enum ssp_writing {
308 WRITING_NULL,
309 WRITING_U8,
310 WRITING_U16,
311 WRITING_U32
312};
313
314/**
315 * struct vendor_data - vendor-specific config parameters
316 * for PL022 derivates
317 * @fifodepth: depth of FIFOs (both)
318 * @max_bpw: maximum number of bits per word
319 * @unidir: supports unidirection transfers
556f4aeb
LW		 320 * @extended_cr: 32 bit wide control register 0 with extra
321 * features and extra features in CR1 as found in the ST variants
781c7b12 322 * @pl023: supports a subset of the ST extensions called "PL023"
b43d65f7
LW		 323 */
324struct vendor_data {
325 int fifodepth;
326 int max_bpw;
327 bool unidir;
556f4aeb 328 bool extended_cr;
781c7b12 329 bool pl023;
b43d65f7
LW		 330};
331
332/**
333 * struct pl022 - This is the private SSP driver data structure
334 * @adev: AMBA device model hookup
556f4aeb 335 * @vendor: Vendor data for the IP block
b43d65f7
LW		 336 * @phybase: The physical memory where the SSP device resides
337 * @virtbase: The virtual memory where the SSP is mapped
338 * @master: SPI framework hookup
339 * @master_info: controller-specific data from machine setup
340 * @regs: SSP controller register's virtual address
341 * @pump_messages: Work struct for scheduling work to the workqueue
342 * @lock: spinlock to syncronise access to driver data
343 * @workqueue: a workqueue on which any spi_message request is queued
344 * @busy: workqueue is busy
345 * @run: workqueue is running
346 * @pump_transfers: Tasklet used in Interrupt Transfer mode
347 * @cur_msg: Pointer to current spi_message being processed
348 * @cur_transfer: Pointer to current spi_transfer
349 * @cur_chip: pointer to current clients chip(assigned from controller_state)
350 * @tx: current position in TX buffer to be read
351 * @tx_end: end position in TX buffer to be read
352 * @rx: current position in RX buffer to be written
353 * @rx_end: end position in RX buffer to be written
354 * @readingtype: the type of read currently going on
355 * @writingtype: the type or write currently going on
356 */
357struct pl022 {
358 struct amba_device *adev;
359 struct vendor_data *vendor;
360 resource_size_t phybase;
361 void __iomem *virtbase;
362 struct clk *clk;
363 struct spi_master *master;
364 struct pl022_ssp_controller *master_info;
365 /* Driver message queue */
366 struct workqueue_struct *workqueue;
367 struct work_struct pump_messages;
368 spinlock_t queue_lock;
369 struct list_head queue;
370 int busy;
371 int run;
372 /* Message transfer pump */
373 struct tasklet_struct pump_transfers;
374 struct spi_message *cur_msg;
375 struct spi_transfer *cur_transfer;
376 struct chip_data *cur_chip;
377 void *tx;
378 void *tx_end;
379 void *rx;
380 void *rx_end;
381 enum ssp_reading read;
382 enum ssp_writing write;
fc05475f 383 u32 exp_fifo_level;
b43d65f7
LW		 384};
385
386/**
387 * struct chip_data - To maintain runtime state of SSP for each client chip
556f4aeb
LW		 388 * @cr0: Value of control register CR0 of SSP - on later ST variants this
389 * register is 32 bits wide rather than just 16
b43d65f7
LW		 390 * @cr1: Value of control register CR1 of SSP
391 * @dmacr: Value of DMA control Register of SSP
392 * @cpsr: Value of Clock prescale register
393 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
394 * @enable_dma: Whether to enable DMA or not
395 * @write: function ptr to be used to write when doing xfer for this chip
396 * @read: function ptr to be used to read when doing xfer for this chip
397 * @cs_control: chip select callback provided by chip
398 * @xfer_type: polling/interrupt/DMA
399 *
400 * Runtime state of the SSP controller, maintained per chip,
401 * This would be set according to the current message that would be served
402 */
403struct chip_data {
556f4aeb 404 u32 cr0;
b43d65f7
LW		 405 u16 cr1;
406 u16 dmacr;
407 u16 cpsr;
408 u8 n_bytes;
409 u8 enable_dma:1;
410 enum ssp_reading read;
411 enum ssp_writing write;
412 void (*cs_control) (u32 command);
413 int xfer_type;
414};
415
416/**
417 * null_cs_control - Dummy chip select function
418 * @command: select/delect the chip
419 *
420 * If no chip select function is provided by client this is used as dummy
421 * chip select
422 */
423static void null_cs_control(u32 command)
424{
425 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
426}
427
428/**
429 * giveback - current spi_message is over, schedule next message and call
430 * callback of this message. Assumes that caller already
431 * set message->status; dma and pio irqs are blocked
432 * @pl022: SSP driver private data structure
433 */
434static void giveback(struct pl022 *pl022)
435{
436 struct spi_transfer *last_transfer;
437 unsigned long flags;
438 struct spi_message *msg;
439 void (*curr_cs_control) (u32 command);
440
441 /*
442 * This local reference to the chip select function
443 * is needed because we set curr_chip to NULL
444 * as a step toward termininating the message.
445 */
446 curr_cs_control = pl022->cur_chip->cs_control;
447 spin_lock_irqsave(&pl022->queue_lock, flags);
448 msg = pl022->cur_msg;
449 pl022->cur_msg = NULL;
450 pl022->cur_transfer = NULL;
451 pl022->cur_chip = NULL;
452 queue_work(pl022->workqueue, &pl022->pump_messages);
453 spin_unlock_irqrestore(&pl022->queue_lock, flags);
454
455 last_transfer = list_entry(msg->transfers.prev,
456 struct spi_transfer,
457 transfer_list);
458
459 /* Delay if requested before any change in chip select */
460 if (last_transfer->delay_usecs)
461 /*
462 * FIXME: This runs in interrupt context.
463 * Is this really smart?
464 */
465 udelay(last_transfer->delay_usecs);
466
467 /*
468 * Drop chip select UNLESS cs_change is true or we are returning
469 * a message with an error, or next message is for another chip
470 */
471 if (!last_transfer->cs_change)
472 curr_cs_control(SSP_CHIP_DESELECT);
473 else {
474 struct spi_message *next_msg;
475
476 /* Holding of cs was hinted, but we need to make sure
477 * the next message is for the same chip. Don't waste
478 * time with the following tests unless this was hinted.
479 *
480 * We cannot postpone this until pump_messages, because
481 * after calling msg->complete (below) the driver that
482 * sent the current message could be unloaded, which
483 * could invalidate the cs_control() callback...
484 */
485
486 /* get a pointer to the next message, if any */
487 spin_lock_irqsave(&pl022->queue_lock, flags);
488 if (list_empty(&pl022->queue))
489 next_msg = NULL;
490 else
491 next_msg = list_entry(pl022->queue.next,
492 struct spi_message, queue);
493 spin_unlock_irqrestore(&pl022->queue_lock, flags);
494
495 /* see if the next and current messages point
496 * to the same chip
497 */
498 if (next_msg && next_msg->spi != msg->spi)
499 next_msg = NULL;
500 if (!next_msg || msg->state == STATE_ERROR)
501 curr_cs_control(SSP_CHIP_DESELECT);
502 }
503 msg->state = NULL;
504 if (msg->complete)
505 msg->complete(msg->context);
545074fb 506 /* This message is completed, so let's turn off the clocks! */
b43d65f7 507 clk_disable(pl022->clk);
545074fb 508 amba_pclk_disable(pl022->adev);
b43d65f7
LW		 509}
510
511/**
512 * flush - flush the FIFO to reach a clean state
513 * @pl022: SSP driver private data structure
514 */
515static int flush(struct pl022 *pl022)
516{
517 unsigned long limit = loops_per_jiffy << 1;
518
519 dev_dbg(&pl022->adev->dev, "flush\n");
520 do {
521 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
522 readw(SSP_DR(pl022->virtbase));
523 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
fc05475f
LW		 524
525 pl022->exp_fifo_level = 0;
526
b43d65f7
LW		 527 return limit;
528}
529
530/**
531 * restore_state - Load configuration of current chip
532 * @pl022: SSP driver private data structure
533 */
534static void restore_state(struct pl022 *pl022)
535{
536 struct chip_data *chip = pl022->cur_chip;
537
556f4aeb
LW		 538 if (pl022->vendor->extended_cr)
539 writel(chip->cr0, SSP_CR0(pl022->virtbase));
540 else
541 writew(chip->cr0, SSP_CR0(pl022->virtbase));
b43d65f7
LW		 542 writew(chip->cr1, SSP_CR1(pl022->virtbase));
543 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
544 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
545 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
546 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
547}
548
b43d65f7
LW		 549/*
550 * Default SSP Register Values
551 */
552#define DEFAULT_SSP_REG_CR0 ( \
553 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
556f4aeb
LW		 554 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
555 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
556 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
557 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
558)
559
560/* ST versions have slightly different bit layout */
561#define DEFAULT_SSP_REG_CR0_ST ( \
562 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
563 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
b43d65f7 564 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
ee2b805c 565 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
556f4aeb
LW		 566 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
567 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
568 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
b43d65f7
LW		 569)
570
781c7b12
LW		 571/* The PL023 version is slightly different again */
572#define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
573 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
574 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
575 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
576 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
577)
578
b43d65f7
LW		 579#define DEFAULT_SSP_REG_CR1 ( \
580 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
581 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
582 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
556f4aeb 583 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
b43d65f7
LW		 584)
585
556f4aeb
LW		 586/* ST versions extend this register to use all 16 bits */
587#define DEFAULT_SSP_REG_CR1_ST ( \
588 DEFAULT_SSP_REG_CR1 | \
589 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
590 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
591 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
592 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
593 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
594)
595
781c7b12
LW		 596/*
597 * The PL023 variant has further differences: no loopback mode, no microwire
598 * support, and a new clock feedback delay setting.
599 */
600#define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
601 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
602 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
603 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
604 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
605 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
606 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
607 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
608 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
609)
556f4aeb 610
b43d65f7 611#define DEFAULT_SSP_REG_CPSR ( \
556f4aeb 612 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
b43d65f7
LW		 613)
614
615#define DEFAULT_SSP_REG_DMACR (\
616 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
617 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
618)
619
781c7b12
LW		 620/**
621 * load_ssp_default_config - Load default configuration for SSP
622 * @pl022: SSP driver private data structure
623 */
b43d65f7
LW		 624static void load_ssp_default_config(struct pl022 *pl022)
625{
781c7b12
LW		 626 if (pl022->vendor->pl023) {
627 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
628 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
629 } else if (pl022->vendor->extended_cr) {
556f4aeb
LW		 630 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
631 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
632 } else {
633 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
634 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
635 }
b43d65f7
LW		 636 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
637 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
638 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
639 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
640}
641
642/**
643 * This will write to TX and read from RX according to the parameters
644 * set in pl022.
645 */
646static void readwriter(struct pl022 *pl022)
647{
648
649 /*
650 * The FIFO depth is different inbetween primecell variants.
651 * I believe filling in too much in the FIFO might cause
652 * errons in 8bit wide transfers on ARM variants (just 8 words
653 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
654 *
fc05475f
LW		 655 * To prevent this issue, the TX FIFO is only filled to the
656 * unused RX FIFO fill length, regardless of what the TX
657 * FIFO status flag indicates.
b43d65f7
LW		 658 */
659 dev_dbg(&pl022->adev->dev,
660 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
661 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
662
663 /* Read as much as you can */
664 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
665 && (pl022->rx < pl022->rx_end)) {
666 switch (pl022->read) {
667 case READING_NULL:
668 readw(SSP_DR(pl022->virtbase));
669 break;
670 case READING_U8:
671 *(u8 *) (pl022->rx) =
672 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
673 break;
674 case READING_U16:
675 *(u16 *) (pl022->rx) =
676 (u16) readw(SSP_DR(pl022->virtbase));
677 break;
678 case READING_U32:
679 *(u32 *) (pl022->rx) =
680 readl(SSP_DR(pl022->virtbase));
681 break;
682 }
683 pl022->rx += (pl022->cur_chip->n_bytes);
fc05475f 684 pl022->exp_fifo_level--;
b43d65f7
LW		 685 }
686 /*
fc05475f 687 * Write as much as possible up to the RX FIFO size
b43d65f7 688 */
fc05475f 689 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
b43d65f7
LW		 690 && (pl022->tx < pl022->tx_end)) {
691 switch (pl022->write) {
692 case WRITING_NULL:
693 writew(0x0, SSP_DR(pl022->virtbase));
694 break;
695 case WRITING_U8:
696 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
697 break;
698 case WRITING_U16:
699 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
700 break;
701 case WRITING_U32:
702 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
703 break;
704 }
705 pl022->tx += (pl022->cur_chip->n_bytes);
fc05475f 706 pl022->exp_fifo_level++;
b43d65f7
LW		 707 /*
708 * This inner reader takes care of things appearing in the RX
709 * FIFO as we're transmitting. This will happen a lot since the
710 * clock starts running when you put things into the TX FIFO,
711 * and then things are continously clocked into the RX FIFO.
712 */
713 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
714 && (pl022->rx < pl022->rx_end)) {
715 switch (pl022->read) {
716 case READING_NULL:
717 readw(SSP_DR(pl022->virtbase));
718 break;
719 case READING_U8:
720 *(u8 *) (pl022->rx) =
721 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
722 break;
723 case READING_U16:
724 *(u16 *) (pl022->rx) =
725 (u16) readw(SSP_DR(pl022->virtbase));
726 break;
727 case READING_U32:
728 *(u32 *) (pl022->rx) =
729 readl(SSP_DR(pl022->virtbase));
730 break;
731 }
732 pl022->rx += (pl022->cur_chip->n_bytes);
fc05475f 733 pl022->exp_fifo_level--;
b43d65f7
LW		 734 }
735 }
736 /*
737 * When we exit here the TX FIFO should be full and the RX FIFO
738 * should be empty
739 */
740}
741
742
743/**
744 * next_transfer - Move to the Next transfer in the current spi message
745 * @pl022: SSP driver private data structure
746 *
747 * This function moves though the linked list of spi transfers in the
748 * current spi message and returns with the state of current spi
749 * message i.e whether its last transfer is done(STATE_DONE) or
750 * Next transfer is ready(STATE_RUNNING)
751 */
752static void *next_transfer(struct pl022 *pl022)
753{
754 struct spi_message *msg = pl022->cur_msg;
755 struct spi_transfer *trans = pl022->cur_transfer;
756
757 /* Move to next transfer */
758 if (trans->transfer_list.next != &msg->transfers) {
759 pl022->cur_transfer =
760 list_entry(trans->transfer_list.next,
761 struct spi_transfer, transfer_list);
762 return STATE_RUNNING;
763 }
764 return STATE_DONE;
765}
766/**
767 * pl022_interrupt_handler - Interrupt handler for SSP controller
768 *
769 * This function handles interrupts generated for an interrupt based transfer.
770 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
771 * current message's state as STATE_ERROR and schedule the tasklet
772 * pump_transfers which will do the postprocessing of the current message by
773 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
774 * more data, and writes data in TX FIFO till it is not full. If we complete
775 * the transfer we move to the next transfer and schedule the tasklet.
776 */
777static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
778{
779 struct pl022 *pl022 = dev_id;
780 struct spi_message *msg = pl022->cur_msg;
781 u16 irq_status = 0;
782 u16 flag = 0;
783
784 if (unlikely(!msg)) {
785 dev_err(&pl022->adev->dev,
786 "bad message state in interrupt handler");
787 /* Never fail */
788 return IRQ_HANDLED;
789 }
790
791 /* Read the Interrupt Status Register */
792 irq_status = readw(SSP_MIS(pl022->virtbase));
793
794 if (unlikely(!irq_status))
795 return IRQ_NONE;
796
797 /* This handles the error code interrupts */
798 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
799 /*
800 * Overrun interrupt - bail out since our Data has been
801 * corrupted
802 */
803 dev_err(&pl022->adev->dev,
804 "FIFO overrun\n");
805 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
806 dev_err(&pl022->adev->dev,
807 "RXFIFO is full\n");
808 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
809 dev_err(&pl022->adev->dev,
810 "TXFIFO is full\n");
811
812 /*
813 * Disable and clear interrupts, disable SSP,
814 * mark message with bad status so it can be
815 * retried.
816 */
817 writew(DISABLE_ALL_INTERRUPTS,
818 SSP_IMSC(pl022->virtbase));
819 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
820 writew((readw(SSP_CR1(pl022->virtbase)) &
821 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
822 msg->state = STATE_ERROR;
823
824 /* Schedule message queue handler */
825 tasklet_schedule(&pl022->pump_transfers);
826 return IRQ_HANDLED;
827 }
828
829 readwriter(pl022);
830
831 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
832 flag = 1;
833 /* Disable Transmit interrupt */
834 writew(readw(SSP_IMSC(pl022->virtbase)) &
835 (~SSP_IMSC_MASK_TXIM),
836 SSP_IMSC(pl022->virtbase));
837 }
838
839 /*
840 * Since all transactions must write as much as shall be read,
841 * we can conclude the entire transaction once RX is complete.
842 * At this point, all TX will always be finished.
843 */
844 if (pl022->rx >= pl022->rx_end) {
845 writew(DISABLE_ALL_INTERRUPTS,
846 SSP_IMSC(pl022->virtbase));
847 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
848 if (unlikely(pl022->rx > pl022->rx_end)) {
849 dev_warn(&pl022->adev->dev, "read %u surplus "
850 "bytes (did you request an odd "
851 "number of bytes on a 16bit bus?)\n",
852 (u32) (pl022->rx - pl022->rx_end));
853 }
854 /* Update total bytes transfered */
855 msg->actual_length += pl022->cur_transfer->len;
856 if (pl022->cur_transfer->cs_change)
857 pl022->cur_chip->
858 cs_control(SSP_CHIP_DESELECT);
859 /* Move to next transfer */
860 msg->state = next_transfer(pl022);
861 tasklet_schedule(&pl022->pump_transfers);
862 return IRQ_HANDLED;
863 }
864
865 return IRQ_HANDLED;
866}
867
868/**
869 * This sets up the pointers to memory for the next message to
870 * send out on the SPI bus.
871 */
872static int set_up_next_transfer(struct pl022 *pl022,
873 struct spi_transfer *transfer)
874{
875 int residue;
876
877 /* Sanity check the message for this bus width */
878 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
879 if (unlikely(residue != 0)) {
880 dev_err(&pl022->adev->dev,
881 "message of %u bytes to transmit but the current "
882 "chip bus has a data width of %u bytes!\n",
883 pl022->cur_transfer->len,
884 pl022->cur_chip->n_bytes);
885 dev_err(&pl022->adev->dev, "skipping this message\n");
886 return -EIO;
887 }
888 pl022->tx = (void *)transfer->tx_buf;
889 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
890 pl022->rx = (void *)transfer->rx_buf;
891 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
892 pl022->write =
893 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
894 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
895 return 0;
896}
897
898/**
899 * pump_transfers - Tasklet function which schedules next interrupt transfer
900 * when running in interrupt transfer mode.
901 * @data: SSP driver private data structure
902 *
903 */
904static void pump_transfers(unsigned long data)
905{
906 struct pl022 *pl022 = (struct pl022 *) data;
907 struct spi_message *message = NULL;
908 struct spi_transfer *transfer = NULL;
909 struct spi_transfer *previous = NULL;
910
911 /* Get current state information */
912 message = pl022->cur_msg;
913 transfer = pl022->cur_transfer;
914
915 /* Handle for abort */
916 if (message->state == STATE_ERROR) {
917 message->status = -EIO;
918 giveback(pl022);
919 return;
920 }
921
922 /* Handle end of message */
923 if (message->state == STATE_DONE) {
924 message->status = 0;
925 giveback(pl022);
926 return;
927 }
928
929 /* Delay if requested at end of transfer before CS change */
930 if (message->state == STATE_RUNNING) {
931 previous = list_entry(transfer->transfer_list.prev,
932 struct spi_transfer,
933 transfer_list);
934 if (previous->delay_usecs)
935 /*
936 * FIXME: This runs in interrupt context.
937 * Is this really smart?
938 */
939 udelay(previous->delay_usecs);
940
941 /* Drop chip select only if cs_change is requested */
942 if (previous->cs_change)
943 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
944 } else {
945 /* STATE_START */
946 message->state = STATE_RUNNING;
947 }
948
949 if (set_up_next_transfer(pl022, transfer)) {
950 message->state = STATE_ERROR;
951 message->status = -EIO;
952 giveback(pl022);
953 return;
954 }
955 /* Flush the FIFOs and let's go! */
956 flush(pl022);
957 writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
958}
959
960/**
961 * NOT IMPLEMENTED
962 * configure_dma - It configures the DMA pipes for DMA transfers
963 * @data: SSP driver's private data structure
964 *
965 */
966static int configure_dma(void *data)
967{
968 struct pl022 *pl022 = data;
969 dev_dbg(&pl022->adev->dev, "configure DMA\n");
970 return -ENOTSUPP;
971}
972
973/**
974 * do_dma_transfer - It handles transfers of the current message
975 * if it is DMA xfer.
976 * NOT FULLY IMPLEMENTED
977 * @data: SSP driver's private data structure
978 */
979static void do_dma_transfer(void *data)
980{
981 struct pl022 *pl022 = data;
982
983 if (configure_dma(data)) {
984 dev_dbg(&pl022->adev->dev, "configuration of DMA Failed!\n");
985 goto err_config_dma;
986 }
987
988 /* TODO: Implememt DMA setup of pipes here */
989
990 /* Enable target chip, set up transfer */
991 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
992 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
993 /* Error path */
994 pl022->cur_msg->state = STATE_ERROR;
995 pl022->cur_msg->status = -EIO;
996 giveback(pl022);
997 return;
998 }
999 /* Enable SSP */
1000 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1001 SSP_CR1(pl022->virtbase));
1002
1003 /* TODO: Enable the DMA transfer here */
1004 return;
1005
1006 err_config_dma:
1007 pl022->cur_msg->state = STATE_ERROR;
1008 pl022->cur_msg->status = -EIO;
1009 giveback(pl022);
1010 return;
1011}
1012
1013static void do_interrupt_transfer(void *data)
1014{
1015 struct pl022 *pl022 = data;
1016
1017 /* Enable target chip */
1018 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1019 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1020 /* Error path */
1021 pl022->cur_msg->state = STATE_ERROR;
1022 pl022->cur_msg->status = -EIO;
1023 giveback(pl022);
1024 return;
1025 }
1026 /* Enable SSP, turn on interrupts */
1027 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1028 SSP_CR1(pl022->virtbase));
1029 writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
1030}
1031
1032static void do_polling_transfer(void *data)
1033{
1034 struct pl022 *pl022 = data;
1035 struct spi_message *message = NULL;
1036 struct spi_transfer *transfer = NULL;
1037 struct spi_transfer *previous = NULL;
1038 struct chip_data *chip;
1039
1040 chip = pl022->cur_chip;
1041 message = pl022->cur_msg;
1042
1043 while (message->state != STATE_DONE) {
1044 /* Handle for abort */
1045 if (message->state == STATE_ERROR)
1046 break;
1047 transfer = pl022->cur_transfer;
1048
1049 /* Delay if requested at end of transfer */
1050 if (message->state == STATE_RUNNING) {
1051 previous =
1052 list_entry(transfer->transfer_list.prev,
1053 struct spi_transfer, transfer_list);
1054 if (previous->delay_usecs)
1055 udelay(previous->delay_usecs);
1056 if (previous->cs_change)
1057 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1058 } else {
1059 /* STATE_START */
1060 message->state = STATE_RUNNING;
1061 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1062 }
1063
1064 /* Configuration Changing Per Transfer */
1065 if (set_up_next_transfer(pl022, transfer)) {
1066 /* Error path */
1067 message->state = STATE_ERROR;
1068 break;
1069 }
1070 /* Flush FIFOs and enable SSP */
1071 flush(pl022);
1072 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1073 SSP_CR1(pl022->virtbase));
1074
556f4aeb 1075 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
b43d65f7
LW		 1076 /* FIXME: insert a timeout so we don't hang here indefinately */
1077 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end)
1078 readwriter(pl022);
1079
1080 /* Update total byte transfered */
1081 message->actual_length += pl022->cur_transfer->len;
1082 if (pl022->cur_transfer->cs_change)
1083 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT);
1084 /* Move to next transfer */
1085 message->state = next_transfer(pl022);
1086 }
1087
1088 /* Handle end of message */
1089 if (message->state == STATE_DONE)
1090 message->status = 0;
1091 else
1092 message->status = -EIO;
1093
1094 giveback(pl022);
1095 return;
1096}
1097
1098/**
1099 * pump_messages - Workqueue function which processes spi message queue
1100 * @data: pointer to private data of SSP driver
1101 *
1102 * This function checks if there is any spi message in the queue that
1103 * needs processing and delegate control to appropriate function
1104 * do_polling_transfer()/do_interrupt_transfer()/do_dma_transfer()
1105 * based on the kind of the transfer
1106 *
1107 */
1108static void pump_messages(struct work_struct *work)
1109{
1110 struct pl022 *pl022 =
1111 container_of(work, struct pl022, pump_messages);
1112 unsigned long flags;
1113
1114 /* Lock queue and check for queue work */
1115 spin_lock_irqsave(&pl022->queue_lock, flags);
1116 if (list_empty(&pl022->queue) || pl022->run == QUEUE_STOPPED) {
1117 pl022->busy = 0;
1118 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1119 return;
1120 }
1121 /* Make sure we are not already running a message */
1122 if (pl022->cur_msg) {
1123 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1124 return;
1125 }
1126 /* Extract head of queue */
1127 pl022->cur_msg =
1128 list_entry(pl022->queue.next, struct spi_message, queue);
1129
1130 list_del_init(&pl022->cur_msg->queue);
1131 pl022->busy = 1;
1132 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1133
1134 /* Initial message state */
1135 pl022->cur_msg->state = STATE_START;
1136 pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next,
1137 struct spi_transfer,
1138 transfer_list);
1139
1140 /* Setup the SPI using the per chip configuration */
1141 pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi);
1142 /*
545074fb 1143 * We enable the clocks here, then the clocks will be disabled when
b43d65f7
LW		 1144 * giveback() is called in each method (poll/interrupt/DMA)
1145 */
545074fb 1146 amba_pclk_enable(pl022->adev);
b43d65f7
LW		 1147 clk_enable(pl022->clk);
1148 restore_state(pl022);
1149 flush(pl022);
1150
1151 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1152 do_polling_transfer(pl022);
1153 else if (pl022->cur_chip->xfer_type == INTERRUPT_TRANSFER)
1154 do_interrupt_transfer(pl022);
1155 else
1156 do_dma_transfer(pl022);
1157}
1158
1159
1160static int __init init_queue(struct pl022 *pl022)
1161{
1162 INIT_LIST_HEAD(&pl022->queue);
1163 spin_lock_init(&pl022->queue_lock);
1164
1165 pl022->run = QUEUE_STOPPED;
1166 pl022->busy = 0;
1167
1168 tasklet_init(&pl022->pump_transfers,
1169 pump_transfers, (unsigned long)pl022);
1170
1171 INIT_WORK(&pl022->pump_messages, pump_messages);
1172 pl022->workqueue = create_singlethread_workqueue(
1173 dev_name(pl022->master->dev.parent));
1174 if (pl022->workqueue == NULL)
1175 return -EBUSY;
1176
1177 return 0;
1178}
1179
1180
1181static int start_queue(struct pl022 *pl022)
1182{
1183 unsigned long flags;
1184
1185 spin_lock_irqsave(&pl022->queue_lock, flags);
1186
1187 if (pl022->run == QUEUE_RUNNING || pl022->busy) {
1188 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1189 return -EBUSY;
1190 }
1191
1192 pl022->run = QUEUE_RUNNING;
1193 pl022->cur_msg = NULL;
1194 pl022->cur_transfer = NULL;
1195 pl022->cur_chip = NULL;
1196 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1197
1198 queue_work(pl022->workqueue, &pl022->pump_messages);
1199
1200 return 0;
1201}
1202
1203
1204static int stop_queue(struct pl022 *pl022)
1205{
1206 unsigned long flags;
1207 unsigned limit = 500;
1208 int status = 0;
1209
1210 spin_lock_irqsave(&pl022->queue_lock, flags);
1211
1212 /* This is a bit lame, but is optimized for the common execution path.
1213 * A wait_queue on the pl022->busy could be used, but then the common
1214 * execution path (pump_messages) would be required to call wake_up or
1215 * friends on every SPI message. Do this instead */
b43d65f7
LW		 1216 while (!list_empty(&pl022->queue) && pl022->busy && limit--) {
1217 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1218 msleep(10);
1219 spin_lock_irqsave(&pl022->queue_lock, flags);
1220 }
1221
1222 if (!list_empty(&pl022->queue) || pl022->busy)
1223 status = -EBUSY;
4a12404d 1224 else pl022->run = QUEUE_STOPPED;
b43d65f7
LW		 1225
1226 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1227
1228 return status;
1229}
1230
1231static int destroy_queue(struct pl022 *pl022)
1232{
1233 int status;
1234
1235 status = stop_queue(pl022);
1236 /* we are unloading the module or failing to load (only two calls
1237 * to this routine), and neither call can handle a return value.
1238 * However, destroy_workqueue calls flush_workqueue, and that will
1239 * block until all work is done. If the reason that stop_queue
1240 * timed out is that the work will never finish, then it does no
1241 * good to call destroy_workqueue, so return anyway. */
1242 if (status != 0)
1243 return status;
1244
1245 destroy_workqueue(pl022->workqueue);
1246
1247 return 0;
1248}
1249
1250static int verify_controller_parameters(struct pl022 *pl022,
1251 struct pl022_config_chip *chip_info)
1252{
1253 if ((chip_info->lbm != LOOPBACK_ENABLED)
1254 && (chip_info->lbm != LOOPBACK_DISABLED)) {
1255 dev_err(chip_info->dev,
1256 "loopback Mode is configured incorrectly\n");
1257 return -EINVAL;
1258 }
1259 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1260 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1261 dev_err(chip_info->dev,
1262 "interface is configured incorrectly\n");
1263 return -EINVAL;
1264 }
1265 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1266 (!pl022->vendor->unidir)) {
1267 dev_err(chip_info->dev,
1268 "unidirectional mode not supported in this "
1269 "hardware version\n");
1270 return -EINVAL;
1271 }
1272 if ((chip_info->hierarchy != SSP_MASTER)
1273 && (chip_info->hierarchy != SSP_SLAVE)) {
1274 dev_err(chip_info->dev,
1275 "hierarchy is configured incorrectly\n");
1276 return -EINVAL;
1277 }
1278 if (((chip_info->clk_freq).cpsdvsr < CPSDVR_MIN)
1279 || ((chip_info->clk_freq).cpsdvsr > CPSDVR_MAX)) {
1280 dev_err(chip_info->dev,
1281 "cpsdvsr is configured incorrectly\n");
1282 return -EINVAL;
1283 }
1284 if ((chip_info->endian_rx != SSP_RX_MSB)
1285 && (chip_info->endian_rx != SSP_RX_LSB)) {
1286 dev_err(chip_info->dev,
1287 "RX FIFO endianess is configured incorrectly\n");
1288 return -EINVAL;
1289 }
1290 if ((chip_info->endian_tx != SSP_TX_MSB)
1291 && (chip_info->endian_tx != SSP_TX_LSB)) {
1292 dev_err(chip_info->dev,
1293 "TX FIFO endianess is configured incorrectly\n");
1294 return -EINVAL;
1295 }
1296 if ((chip_info->data_size < SSP_DATA_BITS_4)
1297 || (chip_info->data_size > SSP_DATA_BITS_32)) {
1298 dev_err(chip_info->dev,
1299 "DATA Size is configured incorrectly\n");
1300 return -EINVAL;
1301 }
1302 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1303 && (chip_info->com_mode != DMA_TRANSFER)
1304 && (chip_info->com_mode != POLLING_TRANSFER)) {
1305 dev_err(chip_info->dev,
1306 "Communication mode is configured incorrectly\n");
1307 return -EINVAL;
1308 }
1309 if ((chip_info->rx_lev_trig < SSP_RX_1_OR_MORE_ELEM)
1310 || (chip_info->rx_lev_trig > SSP_RX_32_OR_MORE_ELEM)) {
1311 dev_err(chip_info->dev,
1312 "RX FIFO Trigger Level is configured incorrectly\n");
1313 return -EINVAL;
1314 }
1315 if ((chip_info->tx_lev_trig < SSP_TX_1_OR_MORE_EMPTY_LOC)
1316 || (chip_info->tx_lev_trig > SSP_TX_32_OR_MORE_EMPTY_LOC)) {
1317 dev_err(chip_info->dev,
1318 "TX FIFO Trigger Level is configured incorrectly\n");
1319 return -EINVAL;
1320 }
1321 if (chip_info->iface == SSP_INTERFACE_MOTOROLA_SPI) {
ee2b805c
LW		 1322 if ((chip_info->clk_phase != SSP_CLK_FIRST_EDGE)
1323 && (chip_info->clk_phase != SSP_CLK_SECOND_EDGE)) {
b43d65f7
LW		 1324 dev_err(chip_info->dev,
1325 "Clock Phase is configured incorrectly\n");
1326 return -EINVAL;
1327 }
1328 if ((chip_info->clk_pol != SSP_CLK_POL_IDLE_LOW)
1329 && (chip_info->clk_pol != SSP_CLK_POL_IDLE_HIGH)) {
1330 dev_err(chip_info->dev,
1331 "Clock Polarity is configured incorrectly\n");
1332 return -EINVAL;
1333 }
1334 }
1335 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1336 if ((chip_info->ctrl_len < SSP_BITS_4)
1337 || (chip_info->ctrl_len > SSP_BITS_32)) {
1338 dev_err(chip_info->dev,
1339 "CTRL LEN is configured incorrectly\n");
1340 return -EINVAL;
1341 }
1342 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1343 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1344 dev_err(chip_info->dev,
1345 "Wait State is configured incorrectly\n");
1346 return -EINVAL;
1347 }
556f4aeb
LW		 1348 /* Half duplex is only available in the ST Micro version */
1349 if (pl022->vendor->extended_cr) {
1350 if ((chip_info->duplex !=
1351 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1352 && (chip_info->duplex !=
1353 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX))
1354 dev_err(chip_info->dev,
1355 "Microwire duplex mode is configured incorrectly\n");
1356 return -EINVAL;
1357 } else {
1358 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1359 dev_err(chip_info->dev,
1360 "Microwire half duplex mode requested,"
1361 " but this is only available in the"
1362 " ST version of PL022\n");
b43d65f7
LW		 1363 return -EINVAL;
1364 }
1365 }
1366 if (chip_info->cs_control == NULL) {
1367 dev_warn(chip_info->dev,
1368 "Chip Select Function is NULL for this chip\n");
1369 chip_info->cs_control = null_cs_control;
1370 }
1371 return 0;
1372}
1373
1374/**
1375 * pl022_transfer - transfer function registered to SPI master framework
1376 * @spi: spi device which is requesting transfer
1377 * @msg: spi message which is to handled is queued to driver queue
1378 *
1379 * This function is registered to the SPI framework for this SPI master
1380 * controller. It will queue the spi_message in the queue of driver if
1381 * the queue is not stopped and return.
1382 */
1383static int pl022_transfer(struct spi_device *spi, struct spi_message *msg)
1384{
1385 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1386 unsigned long flags;
1387
1388 spin_lock_irqsave(&pl022->queue_lock, flags);
1389
1390 if (pl022->run == QUEUE_STOPPED) {
1391 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1392 return -ESHUTDOWN;
1393 }
1394 msg->actual_length = 0;
1395 msg->status = -EINPROGRESS;
1396 msg->state = STATE_START;
1397
1398 list_add_tail(&msg->queue, &pl022->queue);
1399 if (pl022->run == QUEUE_RUNNING && !pl022->busy)
1400 queue_work(pl022->workqueue, &pl022->pump_messages);
1401
1402 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1403 return 0;
1404}
1405
1406static int calculate_effective_freq(struct pl022 *pl022,
1407 int freq,
1408 struct ssp_clock_params *clk_freq)
1409{
1410 /* Lets calculate the frequency parameters */
1411 u16 cpsdvsr = 2;
1412 u16 scr = 0;
1413 bool freq_found = false;
1414 u32 rate;
1415 u32 max_tclk;
1416 u32 min_tclk;
1417
1418 rate = clk_get_rate(pl022->clk);
1419 /* cpsdvscr = 2 & scr 0 */
1420 max_tclk = (rate / (CPSDVR_MIN * (1 + SCR_MIN)));
1421 /* cpsdvsr = 254 & scr = 255 */
1422 min_tclk = (rate / (CPSDVR_MAX * (1 + SCR_MAX)));
1423
1424 if ((freq <= max_tclk) && (freq >= min_tclk)) {
1425 while (cpsdvsr <= CPSDVR_MAX && !freq_found) {
1426 while (scr <= SCR_MAX && !freq_found) {
1427 if ((rate /
1428 (cpsdvsr * (1 + scr))) > freq)
1429 scr += 1;
1430 else {
1431 /*
1432 * This bool is made true when
1433 * effective frequency >=
1434 * target frequency is found
1435 */
1436 freq_found = true;
1437 if ((rate /
1438 (cpsdvsr * (1 + scr))) != freq) {
1439 if (scr == SCR_MIN) {
1440 cpsdvsr -= 2;
1441 scr = SCR_MAX;
1442 } else
1443 scr -= 1;
1444 }
1445 }
1446 }
1447 if (!freq_found) {
1448 cpsdvsr += 2;
1449 scr = SCR_MIN;
1450 }
1451 }
1452 if (cpsdvsr != 0) {
1453 dev_dbg(&pl022->adev->dev,
1454 "SSP Effective Frequency is %u\n",
1455 (rate / (cpsdvsr * (1 + scr))));
1456 clk_freq->cpsdvsr = (u8) (cpsdvsr & 0xFF);
1457 clk_freq->scr = (u8) (scr & 0xFF);
1458 dev_dbg(&pl022->adev->dev,
1459 "SSP cpsdvsr = %d, scr = %d\n",
1460 clk_freq->cpsdvsr, clk_freq->scr);
1461 }
1462 } else {
1463 dev_err(&pl022->adev->dev,
1464 "controller data is incorrect: out of range frequency");
1465 return -EINVAL;
1466 }
1467 return 0;
1468}
1469
1470/**
1471 * NOT IMPLEMENTED
1472 * process_dma_info - Processes the DMA info provided by client drivers
1473 * @chip_info: chip info provided by client device
1474 * @chip: Runtime state maintained by the SSP controller for each spi device
1475 *
1476 * This function processes and stores DMA config provided by client driver
1477 * into the runtime state maintained by the SSP controller driver
1478 */
1479static int process_dma_info(struct pl022_config_chip *chip_info,
1480 struct chip_data *chip)
1481{
1482 dev_err(chip_info->dev,
1483 "cannot process DMA info, DMA not implemented!\n");
1484 return -ENOTSUPP;
1485}
1486
1487/**
1488 * pl022_setup - setup function registered to SPI master framework
1489 * @spi: spi device which is requesting setup
1490 *
1491 * This function is registered to the SPI framework for this SPI master
1492 * controller. If it is the first time when setup is called by this device,
1493 * this function will initialize the runtime state for this chip and save
1494 * the same in the device structure. Else it will update the runtime info
1495 * with the updated chip info. Nothing is really being written to the
1496 * controller hardware here, that is not done until the actual transfer
1497 * commence.
1498 */
1499
1500/* FIXME: JUST GUESSING the spi->mode bits understood by this driver */
1501#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1502 | SPI_LSB_FIRST | SPI_LOOP)
1503
1504static int pl022_setup(struct spi_device *spi)
1505{
1506 struct pl022_config_chip *chip_info;
1507 struct chip_data *chip;
1508 int status = 0;
1509 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1510
1511 if (spi->mode & ~MODEBITS) {
1512 dev_dbg(&spi->dev, "unsupported mode bits %x\n",
1513 spi->mode & ~MODEBITS);
1514 return -EINVAL;
1515 }
1516
1517 if (!spi->max_speed_hz)
1518 return -EINVAL;
1519
1520 /* Get controller_state if one is supplied */
1521 chip = spi_get_ctldata(spi);
1522
1523 if (chip == NULL) {
1524 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1525 if (!chip) {
1526 dev_err(&spi->dev,
1527 "cannot allocate controller state\n");
1528 return -ENOMEM;
1529 }
1530 dev_dbg(&spi->dev,
1531 "allocated memory for controller's runtime state\n");
1532 }
1533
1534 /* Get controller data if one is supplied */
1535 chip_info = spi->controller_data;
1536
1537 if (chip_info == NULL) {
1538 /* spi_board_info.controller_data not is supplied */
1539 dev_dbg(&spi->dev,
1540 "using default controller_data settings\n");
1541
1542 chip_info =
1543 kzalloc(sizeof(struct pl022_config_chip), GFP_KERNEL);
1544
1545 if (!chip_info) {
1546 dev_err(&spi->dev,
1547 "cannot allocate controller data\n");
1548 status = -ENOMEM;
1549 goto err_first_setup;
1550 }
1551
1552 dev_dbg(&spi->dev, "allocated memory for controller data\n");
1553
1554 /* Pointer back to the SPI device */
1555 chip_info->dev = &spi->dev;
1556 /*
1557 * Set controller data default values:
1558 * Polling is supported by default
1559 */
1560 chip_info->lbm = LOOPBACK_DISABLED;
1561 chip_info->com_mode = POLLING_TRANSFER;
1562 chip_info->iface = SSP_INTERFACE_MOTOROLA_SPI;
1563 chip_info->hierarchy = SSP_SLAVE;
1564 chip_info->slave_tx_disable = DO_NOT_DRIVE_TX;
1565 chip_info->endian_tx = SSP_TX_LSB;
1566 chip_info->endian_rx = SSP_RX_LSB;
1567 chip_info->data_size = SSP_DATA_BITS_12;
1568 chip_info->rx_lev_trig = SSP_RX_1_OR_MORE_ELEM;
1569 chip_info->tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC;
ee2b805c 1570 chip_info->clk_phase = SSP_CLK_SECOND_EDGE;
b43d65f7
LW		 1571 chip_info->clk_pol = SSP_CLK_POL_IDLE_LOW;
1572 chip_info->ctrl_len = SSP_BITS_8;
1573 chip_info->wait_state = SSP_MWIRE_WAIT_ZERO;
1574 chip_info->duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX;
1575 chip_info->cs_control = null_cs_control;
1576 } else {
1577 dev_dbg(&spi->dev,
1578 "using user supplied controller_data settings\n");
1579 }
1580
1581 /*
1582 * We can override with custom divisors, else we use the board
1583 * frequency setting
1584 */
1585 if ((0 == chip_info->clk_freq.cpsdvsr)
1586 && (0 == chip_info->clk_freq.scr)) {
1587 status = calculate_effective_freq(pl022,
1588 spi->max_speed_hz,
1589 &chip_info->clk_freq);
1590 if (status < 0)
1591 goto err_config_params;
1592 } else {
1593 if ((chip_info->clk_freq.cpsdvsr % 2) != 0)
1594 chip_info->clk_freq.cpsdvsr =
1595 chip_info->clk_freq.cpsdvsr - 1;
1596 }
1597 status = verify_controller_parameters(pl022, chip_info);
1598 if (status) {
1599 dev_err(&spi->dev, "controller data is incorrect");
1600 goto err_config_params;
1601 }
1602 /* Now set controller state based on controller data */
1603 chip->xfer_type = chip_info->com_mode;
1604 chip->cs_control = chip_info->cs_control;
1605
1606 if (chip_info->data_size <= 8) {
1607 dev_dbg(&spi->dev, "1 <= n <=8 bits per word\n");
1608 chip->n_bytes = 1;
1609 chip->read = READING_U8;
1610 chip->write = WRITING_U8;
1611 } else if (chip_info->data_size <= 16) {
1612 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1613 chip->n_bytes = 2;
1614 chip->read = READING_U16;
1615 chip->write = WRITING_U16;
1616 } else {
1617 if (pl022->vendor->max_bpw >= 32) {
1618 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1619 chip->n_bytes = 4;
1620 chip->read = READING_U32;
1621 chip->write = WRITING_U32;
1622 } else {
1623 dev_err(&spi->dev,
1624 "illegal data size for this controller!\n");
1625 dev_err(&spi->dev,
1626 "a standard pl022 can only handle "
1627 "1 <= n <= 16 bit words\n");
1628 goto err_config_params;
1629 }
1630 }
1631
1632 /* Now Initialize all register settings required for this chip */
1633 chip->cr0 = 0;
1634 chip->cr1 = 0;
1635 chip->dmacr = 0;
1636 chip->cpsr = 0;
1637 if ((chip_info->com_mode == DMA_TRANSFER)
1638 && ((pl022->master_info)->enable_dma)) {
1639 chip->enable_dma = 1;
1640 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
1641 status = process_dma_info(chip_info, chip);
1642 if (status < 0)
1643 goto err_config_params;
1644 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1645 SSP_DMACR_MASK_RXDMAE, 0);
1646 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1647 SSP_DMACR_MASK_TXDMAE, 1);
1648 } else {
1649 chip->enable_dma = 0;
1650 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1651 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1652 SSP_DMACR_MASK_RXDMAE, 0);
1653 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1654 SSP_DMACR_MASK_TXDMAE, 1);
1655 }
1656
1657 chip->cpsr = chip_info->clk_freq.cpsdvsr;
1658
556f4aeb
LW		 1659 /* Special setup for the ST micro extended control registers */
1660 if (pl022->vendor->extended_cr) {
781c7b12
LW		 1661 if (pl022->vendor->pl023) {
1662 /* These bits are only in the PL023 */
1663 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1664 SSP_CR1_MASK_FBCLKDEL_ST, 13);
1665 } else {
1666 /* These bits are in the PL022 but not PL023 */
1667 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1668 SSP_CR0_MASK_HALFDUP_ST, 5);
1669 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1670 SSP_CR0_MASK_CSS_ST, 16);
1671 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1672 SSP_CR0_MASK_FRF_ST, 21);
1673 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
1674 SSP_CR1_MASK_MWAIT_ST, 6);
1675 }
556f4aeb
LW		 1676 SSP_WRITE_BITS(chip->cr0, chip_info->data_size,
1677 SSP_CR0_MASK_DSS_ST, 0);
556f4aeb
LW		 1678 SSP_WRITE_BITS(chip->cr1, chip_info->endian_rx,
1679 SSP_CR1_MASK_RENDN_ST, 4);
1680 SSP_WRITE_BITS(chip->cr1, chip_info->endian_tx,
1681 SSP_CR1_MASK_TENDN_ST, 5);
556f4aeb
LW		 1682 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
1683 SSP_CR1_MASK_RXIFLSEL_ST, 7);
1684 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
1685 SSP_CR1_MASK_TXIFLSEL_ST, 10);
1686 } else {
1687 SSP_WRITE_BITS(chip->cr0, chip_info->data_size,
1688 SSP_CR0_MASK_DSS, 0);
1689 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1690 SSP_CR0_MASK_FRF, 4);
1691 }
1692 /* Stuff that is common for all versions */
b43d65f7
LW		 1693 SSP_WRITE_BITS(chip->cr0, chip_info->clk_pol, SSP_CR0_MASK_SPO, 6);
1694 SSP_WRITE_BITS(chip->cr0, chip_info->clk_phase, SSP_CR0_MASK_SPH, 7);
1695 SSP_WRITE_BITS(chip->cr0, chip_info->clk_freq.scr, SSP_CR0_MASK_SCR, 8);
781c7b12
LW		 1696 /* Loopback is available on all versions except PL023 */
1697 if (!pl022->vendor->pl023)
1698 SSP_WRITE_BITS(chip->cr1, chip_info->lbm, SSP_CR1_MASK_LBM, 0);
b43d65f7
LW		 1699 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
1700 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
1701 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3);
b43d65f7
LW		 1702
1703 /* Save controller_state */
1704 spi_set_ctldata(spi, chip);
1705 return status;
1706 err_config_params:
1707 err_first_setup:
1708 kfree(chip);
1709 return status;
1710}
1711
1712/**
1713 * pl022_cleanup - cleanup function registered to SPI master framework
1714 * @spi: spi device which is requesting cleanup
1715 *
1716 * This function is registered to the SPI framework for this SPI master
1717 * controller. It will free the runtime state of chip.
1718 */
1719static void pl022_cleanup(struct spi_device *spi)
1720{
1721 struct chip_data *chip = spi_get_ctldata(spi);
1722
1723 spi_set_ctldata(spi, NULL);
1724 kfree(chip);
1725}
1726
1727
b4225885 1728static int __devinit
b43d65f7
LW		 1729pl022_probe(struct amba_device *adev, struct amba_id *id)
1730{
1731 struct device *dev = &adev->dev;
1732 struct pl022_ssp_controller *platform_info = adev->dev.platform_data;
1733 struct spi_master *master;
1734 struct pl022 *pl022 = NULL; /*Data for this driver */
1735 int status = 0;
1736
1737 dev_info(&adev->dev,
1738 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
1739 if (platform_info == NULL) {
1740 dev_err(&adev->dev, "probe - no platform data supplied\n");
1741 status = -ENODEV;
1742 goto err_no_pdata;
1743 }
1744
1745 /* Allocate master with space for data */
1746 master = spi_alloc_master(dev, sizeof(struct pl022));
1747 if (master == NULL) {
1748 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
1749 status = -ENOMEM;
1750 goto err_no_master;
1751 }
1752
1753 pl022 = spi_master_get_devdata(master);
1754 pl022->master = master;
1755 pl022->master_info = platform_info;
1756 pl022->adev = adev;
1757 pl022->vendor = id->data;
1758
1759 /*
1760 * Bus Number Which has been Assigned to this SSP controller
1761 * on this board
1762 */
1763 master->bus_num = platform_info->bus_id;
1764 master->num_chipselect = platform_info->num_chipselect;
1765 master->cleanup = pl022_cleanup;
1766 master->setup = pl022_setup;
1767 master->transfer = pl022_transfer;
1768
1769 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
1770
1771 status = amba_request_regions(adev, NULL);
1772 if (status)
1773 goto err_no_ioregion;
1774
1775 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
1776 if (pl022->virtbase == NULL) {
1777 status = -ENOMEM;
1778 goto err_no_ioremap;
1779 }
1780 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
1781 adev->res.start, pl022->virtbase);
1782
1783 pl022->clk = clk_get(&adev->dev, NULL);
1784 if (IS_ERR(pl022->clk)) {
1785 status = PTR_ERR(pl022->clk);
1786 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
1787 goto err_no_clk;
1788 }
1789
1790 /* Disable SSP */
b43d65f7
LW		 1791 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
1792 SSP_CR1(pl022->virtbase));
1793 load_ssp_default_config(pl022);
b43d65f7
LW		 1794
1795 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022",
1796 pl022);
1797 if (status < 0) {
1798 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
1799 goto err_no_irq;
1800 }
1801 /* Initialize and start queue */
1802 status = init_queue(pl022);
1803 if (status != 0) {
1804 dev_err(&adev->dev, "probe - problem initializing queue\n");
1805 goto err_init_queue;
1806 }
1807 status = start_queue(pl022);
1808 if (status != 0) {
1809 dev_err(&adev->dev, "probe - problem starting queue\n");
1810 goto err_start_queue;
1811 }
1812 /* Register with the SPI framework */
1813 amba_set_drvdata(adev, pl022);
1814 status = spi_register_master(master);
1815 if (status != 0) {
1816 dev_err(&adev->dev,
1817 "probe - problem registering spi master\n");
1818 goto err_spi_register;
1819 }
1820 dev_dbg(dev, "probe succeded\n");
545074fb
LW		 1821 /* Disable the silicon block pclk and clock it when needed */
1822 amba_pclk_disable(adev);
b43d65f7
LW		 1823 return 0;
1824
1825 err_spi_register:
1826 err_start_queue:
1827 err_init_queue:
1828 destroy_queue(pl022);
1829 free_irq(adev->irq[0], pl022);
1830 err_no_irq:
1831 clk_put(pl022->clk);
1832 err_no_clk:
1833 iounmap(pl022->virtbase);
1834 err_no_ioremap:
1835 amba_release_regions(adev);
1836 err_no_ioregion:
1837 spi_master_put(master);
1838 err_no_master:
1839 err_no_pdata:
1840 return status;
1841}
1842
b4225885 1843static int __devexit
b43d65f7
LW		 1844pl022_remove(struct amba_device *adev)
1845{
1846 struct pl022 *pl022 = amba_get_drvdata(adev);
1847 int status = 0;
1848 if (!pl022)
1849 return 0;
1850
1851 /* Remove the queue */
1852 status = destroy_queue(pl022);
1853 if (status != 0) {
1854 dev_err(&adev->dev,
1855 "queue remove failed (%d)\n", status);
1856 return status;
1857 }
1858 load_ssp_default_config(pl022);
1859 free_irq(adev->irq[0], pl022);
1860 clk_disable(pl022->clk);
1861 clk_put(pl022->clk);
1862 iounmap(pl022->virtbase);
1863 amba_release_regions(adev);
1864 tasklet_disable(&pl022->pump_transfers);
1865 spi_unregister_master(pl022->master);
1866 spi_master_put(pl022->master);
1867 amba_set_drvdata(adev, NULL);
1868 dev_dbg(&adev->dev, "remove succeded\n");
1869 return 0;
1870}
1871
1872#ifdef CONFIG_PM
1873static int pl022_suspend(struct amba_device *adev, pm_message_t state)
1874{
1875 struct pl022 *pl022 = amba_get_drvdata(adev);
1876 int status = 0;
1877
1878 status = stop_queue(pl022);
1879 if (status) {
1880 dev_warn(&adev->dev, "suspend cannot stop queue\n");
1881 return status;
1882 }
1883
545074fb 1884 amba_pclk_enable(adev);
b43d65f7 1885 load_ssp_default_config(pl022);
545074fb 1886 amba_pclk_disable(adev);
b43d65f7
LW		 1887 dev_dbg(&adev->dev, "suspended\n");
1888 return 0;
1889}
1890
1891static int pl022_resume(struct amba_device *adev)
1892{
1893 struct pl022 *pl022 = amba_get_drvdata(adev);
1894 int status = 0;
1895
1896 /* Start the queue running */
1897 status = start_queue(pl022);
1898 if (status)
1899 dev_err(&adev->dev, "problem starting queue (%d)\n", status);
1900 else
1901 dev_dbg(&adev->dev, "resumed\n");
1902
1903 return status;
1904}
1905#else
1906#define pl022_suspend NULL
1907#define pl022_resume NULL
1908#endif /* CONFIG_PM */
1909
1910static struct vendor_data vendor_arm = {
1911 .fifodepth = 8,
1912 .max_bpw = 16,
1913 .unidir = false,
556f4aeb 1914 .extended_cr = false,
781c7b12 1915 .pl023 = false,
b43d65f7
LW		 1916};
1917
1918
1919static struct vendor_data vendor_st = {
1920 .fifodepth = 32,
1921 .max_bpw = 32,
1922 .unidir = false,
556f4aeb 1923 .extended_cr = true,
781c7b12
LW		 1924 .pl023 = false,
1925};
1926
1927static struct vendor_data vendor_st_pl023 = {
1928 .fifodepth = 32,
1929 .max_bpw = 32,
1930 .unidir = false,
1931 .extended_cr = true,
1932 .pl023 = true,
b43d65f7
LW		 1933};
1934
1935static struct amba_id pl022_ids[] = {
1936 {
1937 /*
1938 * ARM PL022 variant, this has a 16bit wide
1939 * and 8 locations deep TX/RX FIFO
1940 */
1941 .id = 0x00041022,
1942 .mask = 0x000fffff,
1943 .data = &vendor_arm,
1944 },
1945 {
1946 /*
1947 * ST Micro derivative, this has 32bit wide
1948 * and 32 locations deep TX/RX FIFO
1949 */
e89e04fc 1950 .id = 0x01080022,
b43d65f7
LW		 1951 .mask = 0xffffffff,
1952 .data = &vendor_st,
1953 },
781c7b12
LW		 1954 {
1955 /*
1956 * ST-Ericsson derivative "PL023" (this is not
1957 * an official ARM number), this is a PL022 SSP block
1958 * stripped to SPI mode only, it has 32bit wide
1959 * and 32 locations deep TX/RX FIFO but no extended
1960 * CR0/CR1 register
1961 */
1962 .id = 0x00080023,
1963 .mask = 0xffffffff,
1964 .data = &vendor_st_pl023,
1965 },
b43d65f7
LW		 1966 { 0, 0 },
1967};
1968
1969static struct amba_driver pl022_driver = {
1970 .drv = {
1971 .name = "ssp-pl022",
1972 },
1973 .id_table = pl022_ids,
1974 .probe = pl022_probe,
b4225885 1975 .remove = __devexit_p(pl022_remove),
b43d65f7
LW		 1976 .suspend = pl022_suspend,
1977 .resume = pl022_resume,
1978};
1979
1980
1981static int __init pl022_init(void)
1982{
1983 return amba_driver_register(&pl022_driver);
1984}
1985
25c8e03b 1986subsys_initcall(pl022_init);
b43d65f7
LW		 1987
1988static void __exit pl022_exit(void)
1989{
1990 amba_driver_unregister(&pl022_driver);
1991}
1992
1993module_exit(pl022_exit);
1994
1995MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
1996MODULE_DESCRIPTION("PL022 SSP Controller Driver");
1997MODULE_LICENSE("GPL");
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