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DMAENGINE: generic slave control v2
[net-next-2.6.git] / drivers / serial / sh-sci.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
7ff731ae 6 * Copyright (C) 2002 - 2008 Paul Mundt
3ea6bc3d 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 16 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
0b3d4ef6
PM		 22#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23#define SUPPORT_SYSRQ
24#endif
1da177e4
LT		 25
26#undef DEBUG
27
1da177e4
LT		 28#include <linux/module.h>
29#include <linux/errno.h>
1da177e4
LT		 30#include <linux/timer.h>
31#include <linux/interrupt.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial.h>
35#include <linux/major.h>
36#include <linux/string.h>
37#include <linux/sysrq.h>
1da177e4
LT		 38#include <linux/ioport.h>
39#include <linux/mm.h>
1da177e4
LT		 40#include <linux/init.h>
41#include <linux/delay.h>
42#include <linux/console.h>
e108b2ca 43#include <linux/platform_device.h>
96de1a8f 44#include <linux/serial_sci.h>
1da177e4
LT		 45#include <linux/notifier.h>
46#include <linux/cpufreq.h>
85f094ec 47#include <linux/clk.h>
fa5da2f7 48#include <linux/ctype.h>
7ff731ae 49#include <linux/err.h>
e552de24 50#include <linux/list.h>
73a19e4c
GL		 51#include <linux/dmaengine.h>
52#include <linux/scatterlist.h>
85f094ec
PM		 53
54#ifdef CONFIG_SUPERH
1da177e4
LT		 55#include <asm/sh_bios.h>
56#endif
57
168f3623
YS		 58#ifdef CONFIG_H8300
59#include <asm/gpio.h>
60#endif
61
1da177e4
LT		 62#include "sh-sci.h"
63
e108b2ca
PM		 64struct sci_port {
65 struct uart_port port;
66
67 /* Port type */
68 unsigned int type;
69
70 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
32351a28 71 unsigned int irqs[SCIx_NR_IRQS];
e108b2ca 72
e108b2ca
PM		 73 /* Port enable callback */
74 void (*enable)(struct uart_port *port);
75
76 /* Port disable callback */
77 void (*disable)(struct uart_port *port);
78
79 /* Break timer */
80 struct timer_list break_timer;
81 int break_flag;
1534a3b3 82
501b825d
MD		 83 /* Interface clock */
84 struct clk *iclk;
85 /* Data clock */
86 struct clk *dclk;
edad1f20 87
e552de24 88 struct list_head node;
73a19e4c
GL		 89 struct dma_chan *chan_tx;
90 struct dma_chan *chan_rx;
91#ifdef CONFIG_SERIAL_SH_SCI_DMA
92 struct device *dma_dev;
93 enum sh_dmae_slave_chan_id slave_tx;
94 enum sh_dmae_slave_chan_id slave_rx;
95 struct dma_async_tx_descriptor *desc_tx;
96 struct dma_async_tx_descriptor *desc_rx[2];
97 dma_cookie_t cookie_tx;
98 dma_cookie_t cookie_rx[2];
99 dma_cookie_t active_rx;
100 struct scatterlist sg_tx;
101 unsigned int sg_len_tx;
102 struct scatterlist sg_rx[2];
103 size_t buf_len_rx;
104 struct sh_dmae_slave param_tx;
105 struct sh_dmae_slave param_rx;
106 struct work_struct work_tx;
107 struct work_struct work_rx;
108 struct timer_list rx_timer;
109#endif
e552de24
MD		 110};
111
112struct sh_sci_priv {
113 spinlock_t lock;
114 struct list_head ports;
e552de24 115 struct notifier_block clk_nb;
e108b2ca
PM		 116};
117
1da177e4 118/* Function prototypes */
b129a8cc 119static void sci_stop_tx(struct uart_port *port);
1da177e4 120
e108b2ca 121#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 122
e108b2ca
PM		 123static struct sci_port sci_ports[SCI_NPORTS];
124static struct uart_driver sci_uart_driver;
1da177e4 125
e7c98dc7
MT		 126static inline struct sci_port *
127to_sci_port(struct uart_port *uart)
128{
129 return container_of(uart, struct sci_port, port);
130}
131
07d2a1a1 132#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 133
134#ifdef CONFIG_CONSOLE_POLL
e108b2ca
PM		 135static inline void handle_error(struct uart_port *port)
136{
137 /* Clear error flags */
1da177e4
LT		 138 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
139}
140
07d2a1a1 141static int sci_poll_get_char(struct uart_port *port)
1da177e4 142{
1da177e4
LT		 143 unsigned short status;
144 int c;
145
e108b2ca 146 do {
1da177e4
LT		 147 status = sci_in(port, SCxSR);
148 if (status & SCxSR_ERRORS(port)) {
149 handle_error(port);
150 continue;
151 }
152 } while (!(status & SCxSR_RDxF(port)));
07d2a1a1 153
1da177e4 154 c = sci_in(port, SCxRDR);
07d2a1a1 155
e7c98dc7
MT		 156 /* Dummy read */
157 sci_in(port, SCxSR);
1da177e4 158 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 159
160 return c;
161}
1f6fd5c9 162#endif
1da177e4 163
07d2a1a1 164static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 165{
1da177e4
LT		 166 unsigned short status;
167
1da177e4
LT		 168 do {
169 status = sci_in(port, SCxSR);
170 } while (!(status & SCxSR_TDxE(port)));
171
272966c0 172 sci_out(port, SCxTDR, c);
dd0a3e77 173 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 174}
07d2a1a1 175#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 176
15c73aaa 177#if defined(__H8300H__) || defined(__H8300S__)
d5701647 178static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4
LT		 179{
180 int ch = (port->mapbase - SMR0) >> 3;
181
182 /* set DDR regs */
e108b2ca
PM		 183 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
184 h8300_sci_pins[ch].rx,
185 H8300_GPIO_INPUT);
186 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
187 h8300_sci_pins[ch].tx,
188 H8300_GPIO_OUTPUT);
189
1da177e4
LT		 190 /* tx mark output*/
191 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
192}
d5701647
PM		 193#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
194static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
e108b2ca 195{
d5701647
PM		 196 if (port->mapbase == 0xA4400000) {
197 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
198 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
199 } else if (port->mapbase == 0xA4410000)
200 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
9465a54f 201}
31a49c4b 202#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
d5701647 203static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
3ea6bc3d 204{
3ea6bc3d
MB		 205 unsigned short data;
206
207 if (cflag & CRTSCTS) {
208 /* enable RTS/CTS */
209 if (port->mapbase == 0xa4430000) { /* SCIF0 */
210 /* Clear PTCR bit 9-2; enable all scif pins but sck */
d5701647
PM		 211 data = __raw_readw(PORT_PTCR);
212 __raw_writew((data & 0xfc03), PORT_PTCR);
3ea6bc3d
MB		 213 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
214 /* Clear PVCR bit 9-2 */
d5701647
PM		 215 data = __raw_readw(PORT_PVCR);
216 __raw_writew((data & 0xfc03), PORT_PVCR);
3ea6bc3d 217 }
3ea6bc3d
MB		 218 } else {
219 if (port->mapbase == 0xa4430000) { /* SCIF0 */
220 /* Clear PTCR bit 5-2; enable only tx and rx */
d5701647
PM		 221 data = __raw_readw(PORT_PTCR);
222 __raw_writew((data & 0xffc3), PORT_PTCR);
3ea6bc3d
MB		 223 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
224 /* Clear PVCR bit 5-2 */
d5701647
PM		 225 data = __raw_readw(PORT_PVCR);
226 __raw_writew((data & 0xffc3), PORT_PVCR);
3ea6bc3d
MB		 227 }
228 }
3ea6bc3d 229}
b7a76e4b 230#elif defined(CONFIG_CPU_SH3)
e108b2ca 231/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
d5701647 232static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 233{
b7a76e4b
PM		 234 unsigned short data;
235
236 /* We need to set SCPCR to enable RTS/CTS */
d5701647 237 data = __raw_readw(SCPCR);
b7a76e4b 238 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
d5701647 239 __raw_writew(data & 0x0fcf, SCPCR);
1da177e4 240
d5701647 241 if (!(cflag & CRTSCTS)) {
1da177e4 242 /* We need to set SCPCR to enable RTS/CTS */
d5701647 243 data = __raw_readw(SCPCR);
1da177e4
LT		 244 /* Clear out SCP7MD1,0, SCP4MD1,0,
245 Set SCP6MD1,0 = {01} (output) */
d5701647 246 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
1da177e4 247
32b53076 248 data = __raw_readb(SCPDR);
1da177e4 249 /* Set /RTS2 (bit6) = 0 */
32b53076 250 __raw_writeb(data & 0xbf, SCPDR);
1da177e4 251 }
1da177e4 252}
41504c39 253#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
d5701647 254static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
41504c39 255{
346b7463 256 unsigned short data;
41504c39 257
346b7463 258 if (port->mapbase == 0xffe00000) {
d5701647 259 data = __raw_readw(PSCR);
346b7463 260 data &= ~0x03cf;
d5701647 261 if (!(cflag & CRTSCTS))
346b7463 262 data |= 0x0340;
41504c39 263
d5701647 264 __raw_writew(data, PSCR);
41504c39 265 }
178dd0cd 266}
c01f0f1a
YS		 267#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
268 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
7d740a06 269 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac 270 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
55ba99eb 271 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
2b1bd1ac 272 defined(CONFIG_CPU_SUBTYPE_SHX3)
d5701647
PM		 273static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
274{
275 if (!(cflag & CRTSCTS))
276 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
277}
b0c50ad7 278#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
d5701647
PM		 279static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
280{
281 if (!(cflag & CRTSCTS))
282 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
283}
b7a76e4b 284#else
d5701647
PM		 285static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
286{
287 /* Nothing to do */
1da177e4 288}
e108b2ca
PM		 289#endif
290
32351a28
PM		 291#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
292 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
55ba99eb
KM		 293 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
294 defined(CONFIG_CPU_SUBTYPE_SH7786)
73a19e4c 295static int scif_txfill(struct uart_port *port)
e108b2ca 296{
73a19e4c 297 return sci_in(port, SCTFDR) & 0xff;
e108b2ca
PM		 298}
299
73a19e4c
GL		 300static int scif_txroom(struct uart_port *port)
301{
302 return SCIF_TXROOM_MAX - scif_txfill(port);
303}
304
305static int scif_rxfill(struct uart_port *port)
e108b2ca 306{
cae167d3 307 return sci_in(port, SCRFDR) & 0xff;
e108b2ca 308}
c63847a3 309#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
73a19e4c 310static int scif_txfill(struct uart_port *port)
c63847a3 311{
73a19e4c
GL		 312 if (port->mapbase == 0xffe00000 ||
313 port->mapbase == 0xffe08000)
e7c98dc7 314 /* SCIF0/1*/
73a19e4c
GL		 315 return sci_in(port, SCTFDR) & 0xff;
316 else
e7c98dc7 317 /* SCIF2 */
73a19e4c
GL		 318 return sci_in(port, SCFDR) >> 8;
319}
320
321static int scif_txroom(struct uart_port *port)
322{
323 if (port->mapbase == 0xffe00000 ||
324 port->mapbase == 0xffe08000)
325 /* SCIF0/1*/
326 return SCIF_TXROOM_MAX - scif_txfill(port);
327 else
328 /* SCIF2 */
329 return SCIF2_TXROOM_MAX - scif_txfill(port);
c63847a3
NI		 330}
331
73a19e4c 332static int scif_rxfill(struct uart_port *port)
c63847a3 333{
e7c98dc7
MT		 334 if ((port->mapbase == 0xffe00000) ||
335 (port->mapbase == 0xffe08000)) {
336 /* SCIF0/1*/
c63847a3 337 return sci_in(port, SCRFDR) & 0xff;
e7c98dc7
MT		 338 } else {
339 /* SCIF2 */
c63847a3 340 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
e7c98dc7 341 }
c63847a3 342}
e108b2ca 343#else
73a19e4c 344static int scif_txfill(struct uart_port *port)
e108b2ca 345{
73a19e4c 346 return sci_in(port, SCFDR) >> 8;
e108b2ca 347}
1da177e4 348
73a19e4c
GL		 349static int scif_txroom(struct uart_port *port)
350{
351 return SCIF_TXROOM_MAX - scif_txfill(port);
352}
353
354static int scif_rxfill(struct uart_port *port)
e108b2ca
PM		 355{
356 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
357}
1da177e4 358#endif
1da177e4 359
73a19e4c 360static int sci_txfill(struct uart_port *port)
e108b2ca 361{
73a19e4c 362 return !(sci_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 363}
364
73a19e4c
GL		 365static int sci_txroom(struct uart_port *port)
366{
367 return !sci_txfill(port);
368}
369
370static int sci_rxfill(struct uart_port *port)
e108b2ca 371{
e7c98dc7 372 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 373}
374
1da177e4
LT		 375/* ********************************************************************** *
376 * the interrupt related routines *
377 * ********************************************************************** */
378
379static void sci_transmit_chars(struct uart_port *port)
380{
ebd2c8f6 381 struct circ_buf *xmit = &port->state->xmit;
1da177e4 382 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 383 unsigned short status;
384 unsigned short ctrl;
e108b2ca 385 int count;
1da177e4
LT		 386
387 status = sci_in(port, SCxSR);
388 if (!(status & SCxSR_TDxE(port))) {
1da177e4 389 ctrl = sci_in(port, SCSCR);
e7c98dc7 390 if (uart_circ_empty(xmit))
1da177e4 391 ctrl &= ~SCI_CTRL_FLAGS_TIE;
e7c98dc7 392 else
1da177e4 393 ctrl |= SCI_CTRL_FLAGS_TIE;
1da177e4 394 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 395 return;
396 }
397
1a22f08d 398 if (port->type == PORT_SCI)
e108b2ca 399 count = sci_txroom(port);
1a22f08d
YS		 400 else
401 count = scif_txroom(port);
1da177e4
LT		 402
403 do {
404 unsigned char c;
405
406 if (port->x_char) {
407 c = port->x_char;
408 port->x_char = 0;
409 } else if (!uart_circ_empty(xmit) && !stopped) {
410 c = xmit->buf[xmit->tail];
411 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
412 } else {
413 break;
414 }
415
416 sci_out(port, SCxTDR, c);
417
418 port->icount.tx++;
419 } while (--count > 0);
420
421 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
422
423 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
424 uart_write_wakeup(port);
425 if (uart_circ_empty(xmit)) {
b129a8cc 426 sci_stop_tx(port);
1da177e4 427 } else {
1da177e4
LT		 428 ctrl = sci_in(port, SCSCR);
429
1a22f08d 430 if (port->type != PORT_SCI) {
1da177e4
LT		 431 sci_in(port, SCxSR); /* Dummy read */
432 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
433 }
1da177e4
LT		 434
435 ctrl |= SCI_CTRL_FLAGS_TIE;
436 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 437 }
438}
439
440/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 441#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 442
7d12e780 443static inline void sci_receive_chars(struct uart_port *port)
1da177e4 444{
e7c98dc7 445 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 446 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 447 int i, count, copied = 0;
448 unsigned short status;
33f0f88f 449 unsigned char flag;
1da177e4
LT		 450
451 status = sci_in(port, SCxSR);
452 if (!(status & SCxSR_RDxF(port)))
453 return;
454
455 while (1) {
1a22f08d 456 if (port->type == PORT_SCI)
73a19e4c 457 count = sci_rxfill(port);
1a22f08d 458 else
73a19e4c 459 count = scif_rxfill(port);
1da177e4
LT		 460
461 /* Don't copy more bytes than there is room for in the buffer */
33f0f88f 462 count = tty_buffer_request_room(tty, count);
1da177e4
LT		 463
464 /* If for any reason we can't copy more data, we're done! */
465 if (count == 0)
466 break;
467
468 if (port->type == PORT_SCI) {
469 char c = sci_in(port, SCxRDR);
e7c98dc7
MT		 470 if (uart_handle_sysrq_char(port, c) ||
471 sci_port->break_flag)
1da177e4 472 count = 0;
e7c98dc7 473 else
e108b2ca 474 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 475 } else {
e7c98dc7 476 for (i = 0; i < count; i++) {
1da177e4
LT		 477 char c = sci_in(port, SCxRDR);
478 status = sci_in(port, SCxSR);
479#if defined(CONFIG_CPU_SH3)
480 /* Skip "chars" during break */
e108b2ca 481 if (sci_port->break_flag) {
1da177e4
LT		 482 if ((c == 0) &&
483 (status & SCxSR_FER(port))) {
484 count--; i--;
485 continue;
486 }
e108b2ca 487
1da177e4 488 /* Nonzero => end-of-break */
762c69e3 489 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 490 sci_port->break_flag = 0;
491
1da177e4
LT		 492 if (STEPFN(c)) {
493 count--; i--;
494 continue;
495 }
496 }
497#endif /* CONFIG_CPU_SH3 */
7d12e780 498 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 499 count--; i--;
500 continue;
501 }
502
503 /* Store data and status */
73a19e4c 504 if (status & SCxSR_FER(port)) {
33f0f88f 505 flag = TTY_FRAME;
762c69e3 506 dev_notice(port->dev, "frame error\n");
73a19e4c 507 } else if (status & SCxSR_PER(port)) {
33f0f88f 508 flag = TTY_PARITY;
762c69e3 509 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 510 } else
511 flag = TTY_NORMAL;
762c69e3 512
33f0f88f 513 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 514 }
515 }
516
517 sci_in(port, SCxSR); /* dummy read */
518 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
519
1da177e4
LT		 520 copied += count;
521 port->icount.rx += count;
522 }
523
524 if (copied) {
525 /* Tell the rest of the system the news. New characters! */
526 tty_flip_buffer_push(tty);
527 } else {
528 sci_in(port, SCxSR); /* dummy read */
529 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
530 }
531}
532
533#define SCI_BREAK_JIFFIES (HZ/20)
534/* The sci generates interrupts during the break,
535 * 1 per millisecond or so during the break period, for 9600 baud.
536 * So dont bother disabling interrupts.
537 * But dont want more than 1 break event.
538 * Use a kernel timer to periodically poll the rx line until
539 * the break is finished.
540 */
541static void sci_schedule_break_timer(struct sci_port *port)
542{
543 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
544 add_timer(&port->break_timer);
545}
546/* Ensure that two consecutive samples find the break over. */
547static void sci_break_timer(unsigned long data)
548{
e108b2ca
PM		 549 struct sci_port *port = (struct sci_port *)data;
550
551 if (sci_rxd_in(&port->port) == 0) {
1da177e4 552 port->break_flag = 1;
e108b2ca
PM		 553 sci_schedule_break_timer(port);
554 } else if (port->break_flag == 1) {
1da177e4
LT		 555 /* break is over. */
556 port->break_flag = 2;
e108b2ca
PM		 557 sci_schedule_break_timer(port);
558 } else
559 port->break_flag = 0;
1da177e4
LT		 560}
561
562static inline int sci_handle_errors(struct uart_port *port)
563{
564 int copied = 0;
565 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 566 struct tty_struct *tty = port->state->port.tty;
1da177e4 567
e108b2ca 568 if (status & SCxSR_ORER(port)) {
1da177e4 569 /* overrun error */
e108b2ca 570 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
33f0f88f 571 copied++;
762c69e3
PM		 572
573 dev_notice(port->dev, "overrun error");
1da177e4
LT		 574 }
575
e108b2ca 576 if (status & SCxSR_FER(port)) {
1da177e4
LT		 577 if (sci_rxd_in(port) == 0) {
578 /* Notify of BREAK */
e7c98dc7 579 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 580
581 if (!sci_port->break_flag) {
582 sci_port->break_flag = 1;
583 sci_schedule_break_timer(sci_port);
584
1da177e4 585 /* Do sysrq handling. */
e108b2ca 586 if (uart_handle_break(port))
1da177e4 587 return 0;
762c69e3
PM		 588
589 dev_dbg(port->dev, "BREAK detected\n");
590
e108b2ca 591 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 592 copied++;
593 }
594
e108b2ca 595 } else {
1da177e4 596 /* frame error */
e108b2ca 597 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 598 copied++;
762c69e3
PM		 599
600 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 601 }
602 }
603
e108b2ca 604 if (status & SCxSR_PER(port)) {
1da177e4 605 /* parity error */
e108b2ca
PM		 606 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
607 copied++;
762c69e3
PM		 608
609 dev_notice(port->dev, "parity error");
1da177e4
LT		 610 }
611
33f0f88f 612 if (copied)
1da177e4 613 tty_flip_buffer_push(tty);
1da177e4
LT		 614
615 return copied;
616}
617
d830fa45
PM		 618static inline int sci_handle_fifo_overrun(struct uart_port *port)
619{
ebd2c8f6 620 struct tty_struct *tty = port->state->port.tty;
d830fa45
PM		 621 int copied = 0;
622
623 if (port->type != PORT_SCIF)
624 return 0;
625
626 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
627 sci_out(port, SCLSR, 0);
628
629 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
630 tty_flip_buffer_push(tty);
631
632 dev_notice(port->dev, "overrun error\n");
633 copied++;
634 }
635
636 return copied;
637}
638
1da177e4
LT		 639static inline int sci_handle_breaks(struct uart_port *port)
640{
641 int copied = 0;
642 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 643 struct tty_struct *tty = port->state->port.tty;
a5660ada 644 struct sci_port *s = to_sci_port(port);
1da177e4 645
0b3d4ef6
PM		 646 if (uart_handle_break(port))
647 return 0;
648
b7a76e4b 649 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 650#if defined(CONFIG_CPU_SH3)
651 /* Debounce break */
652 s->break_flag = 1;
653#endif
654 /* Notify of BREAK */
e108b2ca 655 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 656 copied++;
762c69e3
PM		 657
658 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 659 }
660
33f0f88f 661 if (copied)
1da177e4 662 tty_flip_buffer_push(tty);
e108b2ca 663
d830fa45
PM		 664 copied += sci_handle_fifo_overrun(port);
665
1da177e4
LT		 666 return copied;
667}
668
73a19e4c 669static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 670{
73a19e4c
GL		 671#ifdef CONFIG_SERIAL_SH_SCI_DMA
672 struct uart_port *port = ptr;
673 struct sci_port *s = to_sci_port(port);
674
675 if (s->chan_rx) {
676 unsigned long tout;
677 u16 scr = sci_in(port, SCSCR);
678 u16 ssr = sci_in(port, SCxSR);
679
680 /* Disable future Rx interrupts */
681 sci_out(port, SCSCR, scr & ~SCI_CTRL_FLAGS_RIE);
682 /* Clear current interrupt */
683 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
684 /* Calculate delay for 1.5 DMA buffers */
685 tout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
686 port->fifosize / 2;
c6efd46b 687 dev_dbg(port->dev, "Rx IRQ: setup timeout in %lu ms\n",
73a19e4c
GL		 688 tout * 1000 / HZ);
689 if (tout < 2)
690 tout = 2;
691 mod_timer(&s->rx_timer, jiffies + tout);
692
693 return IRQ_HANDLED;
694 }
695#endif
696
1da177e4
LT		 697 /* I think sci_receive_chars has to be called irrespective
698 * of whether the I_IXOFF is set, otherwise, how is the interrupt
699 * to be disabled?
700 */
73a19e4c 701 sci_receive_chars(ptr);
1da177e4
LT		 702
703 return IRQ_HANDLED;
704}
705
7d12e780 706static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 707{
708 struct uart_port *port = ptr;
fd78a76a 709 unsigned long flags;
1da177e4 710
fd78a76a 711 spin_lock_irqsave(&port->lock, flags);
1da177e4 712 sci_transmit_chars(port);
fd78a76a 713 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 714
715 return IRQ_HANDLED;
716}
717
7d12e780 718static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 719{
720 struct uart_port *port = ptr;
721
722 /* Handle errors */
723 if (port->type == PORT_SCI) {
724 if (sci_handle_errors(port)) {
725 /* discard character in rx buffer */
726 sci_in(port, SCxSR);
727 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
728 }
729 } else {
d830fa45 730 sci_handle_fifo_overrun(port);
7d12e780 731 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 732 }
733
734 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
735
736 /* Kick the transmission */
7d12e780 737 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 738
739 return IRQ_HANDLED;
740}
741
7d12e780 742static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 743{
744 struct uart_port *port = ptr;
745
746 /* Handle BREAKs */
747 sci_handle_breaks(port);
748 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
749
750 return IRQ_HANDLED;
751}
752
7d12e780 753static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 754{
44e18e9e 755 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 756 struct uart_port *port = ptr;
73a19e4c 757 struct sci_port *s = to_sci_port(port);
a8884e34 758 irqreturn_t ret = IRQ_NONE;
1da177e4 759
e7c98dc7
MT		 760 ssr_status = sci_in(port, SCxSR);
761 scr_status = sci_in(port, SCSCR);
44e18e9e 762 err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE);
1da177e4
LT		 763
764 /* Tx Interrupt */
73a19e4c
GL		 765 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE) &&
766 !s->chan_tx)
a8884e34 767 ret = sci_tx_interrupt(irq, ptr);
73a19e4c
GL		 768 /*
769 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
770 * DR flags
771 */
772 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
773 (scr_status & SCI_CTRL_FLAGS_RIE))
a8884e34 774 ret = sci_rx_interrupt(irq, ptr);
1da177e4 775 /* Error Interrupt */
dd4da3a5 776 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 777 ret = sci_er_interrupt(irq, ptr);
1da177e4 778 /* Break Interrupt */
dd4da3a5 779 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 780 ret = sci_br_interrupt(irq, ptr);
1da177e4 781
73a19e4c
GL		 782 WARN_ONCE(ret == IRQ_NONE,
783 "%s: %d IRQ %d, status %x, control %x\n", __func__,
784 irq, port->line, ssr_status, scr_status);
785
a8884e34 786 return ret;
1da177e4
LT		 787}
788
1da177e4
LT		 789/*
790 * Here we define a transistion notifier so that we can update all of our
791 * ports' baud rate when the peripheral clock changes.
792 */
e108b2ca
PM		 793static int sci_notifier(struct notifier_block *self,
794 unsigned long phase, void *p)
1da177e4 795{
e552de24
MD		 796 struct sh_sci_priv *priv = container_of(self,
797 struct sh_sci_priv, clk_nb);
798 struct sci_port *sci_port;
799 unsigned long flags;
1da177e4
LT		 800
801 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24
MD		 802 (phase == CPUFREQ_RESUMECHANGE)) {
803 spin_lock_irqsave(&priv->lock, flags);
804 list_for_each_entry(sci_port, &priv->ports, node)
501b825d 805 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
e552de24
MD		 806 spin_unlock_irqrestore(&priv->lock, flags);
807 }
1da177e4 808
1da177e4
LT		 809 return NOTIFY_OK;
810}
501b825d
MD		 811
812static void sci_clk_enable(struct uart_port *port)
813{
814 struct sci_port *sci_port = to_sci_port(port);
815
816 clk_enable(sci_port->dclk);
817 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
818
819 if (sci_port->iclk)
820 clk_enable(sci_port->iclk);
821}
822
823static void sci_clk_disable(struct uart_port *port)
824{
825 struct sci_port *sci_port = to_sci_port(port);
826
827 if (sci_port->iclk)
828 clk_disable(sci_port->iclk);
829
830 clk_disable(sci_port->dclk);
831}
1da177e4
LT		 832
833static int sci_request_irq(struct sci_port *port)
834{
835 int i;
7d12e780 836 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
1da177e4
LT		 837 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
838 sci_br_interrupt,
839 };
840 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
841 "SCI Transmit Data Empty", "SCI Break" };
842
843 if (port->irqs[0] == port->irqs[1]) {
762c69e3 844 if (unlikely(!port->irqs[0]))
1da177e4 845 return -ENODEV;
e108b2ca
PM		 846
847 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
35f3c518 848 IRQF_DISABLED, "sci", port)) {
762c69e3 849 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 850 return -ENODEV;
851 }
852 } else {
853 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
762c69e3 854 if (unlikely(!port->irqs[i]))
1da177e4 855 continue;
762c69e3 856
e108b2ca 857 if (request_irq(port->irqs[i], handlers[i],
35f3c518 858 IRQF_DISABLED, desc[i], port)) {
762c69e3 859 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 860 return -ENODEV;
861 }
862 }
863 }
864
865 return 0;
866}
867
868static void sci_free_irq(struct sci_port *port)
869{
870 int i;
871
762c69e3
PM		 872 if (port->irqs[0] == port->irqs[1])
873 free_irq(port->irqs[0], port);
874 else {
1da177e4
LT		 875 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
876 if (!port->irqs[i])
877 continue;
878
879 free_irq(port->irqs[i], port);
880 }
881 }
882}
883
884static unsigned int sci_tx_empty(struct uart_port *port)
885{
b1516803 886 unsigned short status = sci_in(port, SCxSR);
73a19e4c
GL		 887 unsigned short in_tx_fifo = scif_txfill(port);
888
889 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 890}
891
892static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
893{
894 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
895 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
896 /* If you have signals for DTR and DCD, please implement here. */
897}
898
899static unsigned int sci_get_mctrl(struct uart_port *port)
900{
73a19e4c 901 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
1da177e4
LT		 902 and CTS/RTS */
903
904 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
905}
906
73a19e4c
GL		 907#ifdef CONFIG_SERIAL_SH_SCI_DMA
908static void sci_dma_tx_complete(void *arg)
909{
910 struct sci_port *s = arg;
911 struct uart_port *port = &s->port;
912 struct circ_buf *xmit = &port->state->xmit;
913 unsigned long flags;
914
915 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
916
917 spin_lock_irqsave(&port->lock, flags);
918
919 xmit->tail += s->sg_tx.length;
920 xmit->tail &= UART_XMIT_SIZE - 1;
921
922 port->icount.tx += s->sg_tx.length;
923
924 async_tx_ack(s->desc_tx);
925 s->cookie_tx = -EINVAL;
926 s->desc_tx = NULL;
927
928 spin_unlock_irqrestore(&port->lock, flags);
929
930 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
931 uart_write_wakeup(port);
932
933 if (uart_circ_chars_pending(xmit))
934 schedule_work(&s->work_tx);
935}
936
937/* Locking: called with port lock held */
938static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
939 size_t count)
940{
941 struct uart_port *port = &s->port;
942 int i, active, room;
943
944 room = tty_buffer_request_room(tty, count);
945
946 if (s->active_rx == s->cookie_rx[0]) {
947 active = 0;
948 } else if (s->active_rx == s->cookie_rx[1]) {
949 active = 1;
950 } else {
951 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
952 return 0;
953 }
954
955 if (room < count)
956 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
957 count - room);
958 if (!room)
959 return room;
960
961 for (i = 0; i < room; i++)
962 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
963 TTY_NORMAL);
964
965 port->icount.rx += room;
966
967 return room;
968}
969
970static void sci_dma_rx_complete(void *arg)
971{
972 struct sci_port *s = arg;
973 struct uart_port *port = &s->port;
974 struct tty_struct *tty = port->state->port.tty;
975 unsigned long flags;
976 int count;
977
978 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
979
980 spin_lock_irqsave(&port->lock, flags);
981
982 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
983
984 mod_timer(&s->rx_timer, jiffies + msecs_to_jiffies(5));
985
986 spin_unlock_irqrestore(&port->lock, flags);
987
988 if (count)
989 tty_flip_buffer_push(tty);
990
991 schedule_work(&s->work_rx);
992}
993
994static void sci_start_rx(struct uart_port *port);
995static void sci_start_tx(struct uart_port *port);
996
997static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
998{
999 struct dma_chan *chan = s->chan_rx;
1000 struct uart_port *port = &s->port;
73a19e4c
GL		 1001
1002 s->chan_rx = NULL;
1003 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1004 dma_release_channel(chan);
1005 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1006 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1007 if (enable_pio)
1008 sci_start_rx(port);
1009}
1010
1011static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1012{
1013 struct dma_chan *chan = s->chan_tx;
1014 struct uart_port *port = &s->port;
73a19e4c
GL		 1015
1016 s->chan_tx = NULL;
1017 s->cookie_tx = -EINVAL;
1018 dma_release_channel(chan);
1019 if (enable_pio)
1020 sci_start_tx(port);
1021}
1022
1023static void sci_submit_rx(struct sci_port *s)
1024{
1025 struct dma_chan *chan = s->chan_rx;
1026 int i;
1027
1028 for (i = 0; i < 2; i++) {
1029 struct scatterlist *sg = &s->sg_rx[i];
1030 struct dma_async_tx_descriptor *desc;
1031
1032 desc = chan->device->device_prep_slave_sg(chan,
1033 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1034
1035 if (desc) {
1036 s->desc_rx[i] = desc;
1037 desc->callback = sci_dma_rx_complete;
1038 desc->callback_param = s;
1039 s->cookie_rx[i] = desc->tx_submit(desc);
1040 }
1041
1042 if (!desc || s->cookie_rx[i] < 0) {
1043 if (i) {
1044 async_tx_ack(s->desc_rx[0]);
1045 s->cookie_rx[0] = -EINVAL;
1046 }
1047 if (desc) {
1048 async_tx_ack(desc);
1049 s->cookie_rx[i] = -EINVAL;
1050 }
1051 dev_warn(s->port.dev,
1052 "failed to re-start DMA, using PIO\n");
1053 sci_rx_dma_release(s, true);
1054 return;
1055 }
1056 }
1057
1058 s->active_rx = s->cookie_rx[0];
1059
1060 dma_async_issue_pending(chan);
1061}
1062
1063static void work_fn_rx(struct work_struct *work)
1064{
1065 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1066 struct uart_port *port = &s->port;
1067 struct dma_async_tx_descriptor *desc;
1068 int new;
1069
1070 if (s->active_rx == s->cookie_rx[0]) {
1071 new = 0;
1072 } else if (s->active_rx == s->cookie_rx[1]) {
1073 new = 1;
1074 } else {
1075 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1076 return;
1077 }
1078 desc = s->desc_rx[new];
1079
1080 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1081 DMA_SUCCESS) {
1082 /* Handle incomplete DMA receive */
1083 struct tty_struct *tty = port->state->port.tty;
1084 struct dma_chan *chan = s->chan_rx;
1085 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1086 async_tx);
1087 unsigned long flags;
1088 int count;
1089
c3635c78 1090 chan->device->device_control(chan, DMA_TERMINATE_ALL);
73a19e4c
GL		 1091 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1092 sh_desc->partial, sh_desc->cookie);
1093
1094 spin_lock_irqsave(&port->lock, flags);
1095 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1096 spin_unlock_irqrestore(&port->lock, flags);
1097
1098 if (count)
1099 tty_flip_buffer_push(tty);
1100
1101 sci_submit_rx(s);
1102
1103 return;
1104 }
1105
1106 s->cookie_rx[new] = desc->tx_submit(desc);
1107 if (s->cookie_rx[new] < 0) {
1108 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1109 sci_rx_dma_release(s, true);
1110 return;
1111 }
1112
1113 dev_dbg(port->dev, "%s: cookie %d #%d\n", __func__,
1114 s->cookie_rx[new], new);
1115
1116 s->active_rx = s->cookie_rx[!new];
1117}
1118
1119static void work_fn_tx(struct work_struct *work)
1120{
1121 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1122 struct dma_async_tx_descriptor *desc;
1123 struct dma_chan *chan = s->chan_tx;
1124 struct uart_port *port = &s->port;
1125 struct circ_buf *xmit = &port->state->xmit;
1126 struct scatterlist *sg = &s->sg_tx;
1127
1128 /*
1129 * DMA is idle now.
1130 * Port xmit buffer is already mapped, and it is one page... Just adjust
1131 * offsets and lengths. Since it is a circular buffer, we have to
1132 * transmit till the end, and then the rest. Take the port lock to get a
1133 * consistent xmit buffer state.
1134 */
1135 spin_lock_irq(&port->lock);
1136 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1137 sg->dma_address = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1138 sg->offset;
1139 sg->length = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1140 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1141 sg->dma_length = sg->length;
1142 spin_unlock_irq(&port->lock);
1143
1144 BUG_ON(!sg->length);
1145
1146 desc = chan->device->device_prep_slave_sg(chan,
1147 sg, s->sg_len_tx, DMA_TO_DEVICE,
1148 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1149 if (!desc) {
1150 /* switch to PIO */
1151 sci_tx_dma_release(s, true);
1152 return;
1153 }
1154
1155 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1156
1157 spin_lock_irq(&port->lock);
1158 s->desc_tx = desc;
1159 desc->callback = sci_dma_tx_complete;
1160 desc->callback_param = s;
1161 spin_unlock_irq(&port->lock);
1162 s->cookie_tx = desc->tx_submit(desc);
1163 if (s->cookie_tx < 0) {
1164 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1165 /* switch to PIO */
1166 sci_tx_dma_release(s, true);
1167 return;
1168 }
1169
1170 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1171 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1172
1173 dma_async_issue_pending(chan);
1174}
1175#endif
1176
b129a8cc 1177static void sci_start_tx(struct uart_port *port)
1da177e4 1178{
e108b2ca 1179 unsigned short ctrl;
1da177e4 1180
73a19e4c
GL		 1181#ifdef CONFIG_SERIAL_SH_SCI_DMA
1182 struct sci_port *s = to_sci_port(port);
1183
1184 if (s->chan_tx) {
1185 if (!uart_circ_empty(&s->port.state->xmit) && s->cookie_tx < 0)
1186 schedule_work(&s->work_tx);
1187
1188 return;
1189 }
1190#endif
1191
e108b2ca
PM		 1192 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1193 ctrl = sci_in(port, SCSCR);
1194 ctrl |= SCI_CTRL_FLAGS_TIE;
1195 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1196}
1197
b129a8cc 1198static void sci_stop_tx(struct uart_port *port)
1da177e4 1199{
1da177e4
LT		 1200 unsigned short ctrl;
1201
1202 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1da177e4
LT		 1203 ctrl = sci_in(port, SCSCR);
1204 ctrl &= ~SCI_CTRL_FLAGS_TIE;
1205 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1206}
1207
73a19e4c 1208static void sci_start_rx(struct uart_port *port)
1da177e4 1209{
73a19e4c 1210 unsigned short ctrl = SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
1da177e4
LT		 1211
1212 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
73a19e4c 1213 ctrl |= sci_in(port, SCSCR);
1da177e4 1214 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1215}
1216
1217static void sci_stop_rx(struct uart_port *port)
1218{
1da177e4
LT		 1219 unsigned short ctrl;
1220
1221 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1da177e4
LT		 1222 ctrl = sci_in(port, SCSCR);
1223 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
1224 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1225}
1226
1227static void sci_enable_ms(struct uart_port *port)
1228{
1229 /* Nothing here yet .. */
1230}
1231
1232static void sci_break_ctl(struct uart_port *port, int break_state)
1233{
1234 /* Nothing here yet .. */
1235}
1236
73a19e4c
GL		 1237#ifdef CONFIG_SERIAL_SH_SCI_DMA
1238static bool filter(struct dma_chan *chan, void *slave)
1239{
1240 struct sh_dmae_slave *param = slave;
1241
1242 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1243 param->slave_id);
1244
1245 if (param->dma_dev == chan->device->dev) {
1246 chan->private = param;
1247 return true;
1248 } else {
1249 return false;
1250 }
1251}
1252
1253static void rx_timer_fn(unsigned long arg)
1254{
1255 struct sci_port *s = (struct sci_port *)arg;
1256 struct uart_port *port = &s->port;
1257
1258 u16 scr = sci_in(port, SCSCR);
1259 sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE);
1260 dev_dbg(port->dev, "DMA Rx timed out\n");
1261 schedule_work(&s->work_rx);
1262}
1263
1264static void sci_request_dma(struct uart_port *port)
1265{
1266 struct sci_port *s = to_sci_port(port);
1267 struct sh_dmae_slave *param;
1268 struct dma_chan *chan;
1269 dma_cap_mask_t mask;
1270 int nent;
1271
1272 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
1273 port->line, s->dma_dev);
1274
1275 if (!s->dma_dev)
1276 return;
1277
1278 dma_cap_zero(mask);
1279 dma_cap_set(DMA_SLAVE, mask);
1280
1281 param = &s->param_tx;
1282
1283 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1284 param->slave_id = s->slave_tx;
1285 param->dma_dev = s->dma_dev;
1286
1287 s->cookie_tx = -EINVAL;
1288 chan = dma_request_channel(mask, filter, param);
1289 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1290 if (chan) {
1291 s->chan_tx = chan;
1292 sg_init_table(&s->sg_tx, 1);
1293 /* UART circular tx buffer is an aligned page. */
1294 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1295 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1296 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1297 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1298 if (!nent)
1299 sci_tx_dma_release(s, false);
1300 else
1301 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1302 sg_dma_len(&s->sg_tx),
1303 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1304
1305 s->sg_len_tx = nent;
1306
1307 INIT_WORK(&s->work_tx, work_fn_tx);
1308 }
1309
1310 param = &s->param_rx;
1311
1312 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1313 param->slave_id = s->slave_rx;
1314 param->dma_dev = s->dma_dev;
1315
1316 chan = dma_request_channel(mask, filter, param);
1317 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1318 if (chan) {
1319 dma_addr_t dma[2];
1320 void *buf[2];
1321 int i;
1322
1323 s->chan_rx = chan;
1324
1325 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1326 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1327 &dma[0], GFP_KERNEL);
1328
1329 if (!buf[0]) {
1330 dev_warn(port->dev,
1331 "failed to allocate dma buffer, using PIO\n");
1332 sci_rx_dma_release(s, true);
1333 return;
1334 }
1335
1336 buf[1] = buf[0] + s->buf_len_rx;
1337 dma[1] = dma[0] + s->buf_len_rx;
1338
1339 for (i = 0; i < 2; i++) {
1340 struct scatterlist *sg = &s->sg_rx[i];
1341
1342 sg_init_table(sg, 1);
1343 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1344 (int)buf[i] & ~PAGE_MASK);
1345 sg->dma_address = dma[i];
1346 sg->dma_length = sg->length;
1347 }
1348
1349 INIT_WORK(&s->work_rx, work_fn_rx);
1350 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1351
1352 sci_submit_rx(s);
1353 }
1354}
1355
1356static void sci_free_dma(struct uart_port *port)
1357{
1358 struct sci_port *s = to_sci_port(port);
1359
1360 if (!s->dma_dev)
1361 return;
1362
1363 if (s->chan_tx)
1364 sci_tx_dma_release(s, false);
1365 if (s->chan_rx)
1366 sci_rx_dma_release(s, false);
1367}
1368#endif
1369
1da177e4
LT		 1370static int sci_startup(struct uart_port *port)
1371{
a5660ada 1372 struct sci_port *s = to_sci_port(port);
1da177e4 1373
73a19e4c
GL		 1374 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1375
e108b2ca
PM		 1376 if (s->enable)
1377 s->enable(port);
1da177e4
LT		 1378
1379 sci_request_irq(s);
73a19e4c
GL		 1380#ifdef CONFIG_SERIAL_SH_SCI_DMA
1381 sci_request_dma(port);
1382#endif
d656901b 1383 sci_start_tx(port);
73a19e4c 1384 sci_start_rx(port);
1da177e4
LT		 1385
1386 return 0;
1387}
1388
1389static void sci_shutdown(struct uart_port *port)
1390{
a5660ada 1391 struct sci_port *s = to_sci_port(port);
1da177e4 1392
73a19e4c
GL		 1393 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1394
1da177e4 1395 sci_stop_rx(port);
b129a8cc 1396 sci_stop_tx(port);
73a19e4c
GL		 1397#ifdef CONFIG_SERIAL_SH_SCI_DMA
1398 sci_free_dma(port);
1399#endif
1da177e4
LT		 1400 sci_free_irq(s);
1401
e108b2ca
PM		 1402 if (s->disable)
1403 s->disable(port);
1da177e4
LT		 1404}
1405
606d099c
AC		 1406static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1407 struct ktermios *old)
1da177e4 1408{
154280fd 1409 unsigned int status, baud, smr_val, max_baud;
a2159b52 1410 int t = -1;
1da177e4 1411
154280fd
MD		 1412 /*
1413 * earlyprintk comes here early on with port->uartclk set to zero.
1414 * the clock framework is not up and running at this point so here
1415 * we assume that 115200 is the maximum baud rate. please note that
1416 * the baud rate is not programmed during earlyprintk - it is assumed
1417 * that the previous boot loader has enabled required clocks and
1418 * setup the baud rate generator hardware for us already.
1419 */
1420 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1421
1422 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1423 if (likely(baud && port->uartclk))
a2159b52 1424 t = SCBRR_VALUE(baud, port->uartclk);
e108b2ca 1425
1da177e4
LT		 1426 do {
1427 status = sci_in(port, SCxSR);
1428 } while (!(status & SCxSR_TEND(port)));
1429
1430 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1431
1a22f08d 1432 if (port->type != PORT_SCI)
1da177e4 1433 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1da177e4
LT		 1434
1435 smr_val = sci_in(port, SCSMR) & 3;
1436 if ((termios->c_cflag & CSIZE) == CS7)
1437 smr_val |= 0x40;
1438 if (termios->c_cflag & PARENB)
1439 smr_val |= 0x20;
1440 if (termios->c_cflag & PARODD)
1441 smr_val |= 0x30;
1442 if (termios->c_cflag & CSTOPB)
1443 smr_val |= 0x08;
1444
1445 uart_update_timeout(port, termios->c_cflag, baud);
1446
1447 sci_out(port, SCSMR, smr_val);
1448
73a19e4c
GL		 1449 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
1450 SCSCR_INIT(port));
1451
1da177e4 1452 if (t > 0) {
e7c98dc7 1453 if (t >= 256) {
1da177e4
LT		 1454 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1455 t >>= 2;
e7c98dc7 1456 } else
1da177e4 1457 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
e7c98dc7 1458
1da177e4
LT		 1459 sci_out(port, SCBRR, t);
1460 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1461 }
1462
d5701647
PM		 1463 sci_init_pins(port, termios->c_cflag);
1464 sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
b7a76e4b 1465
1da177e4
LT		 1466 sci_out(port, SCSCR, SCSCR_INIT(port));
1467
1468 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1469 sci_start_rx(port);
1da177e4
LT		 1470}
1471
1472static const char *sci_type(struct uart_port *port)
1473{
1474 switch (port->type) {
e7c98dc7
MT		 1475 case PORT_IRDA:
1476 return "irda";
1477 case PORT_SCI:
1478 return "sci";
1479 case PORT_SCIF:
1480 return "scif";
1481 case PORT_SCIFA:
1482 return "scifa";
1da177e4
LT		 1483 }
1484
fa43972f 1485 return NULL;
1da177e4
LT		 1486}
1487
1488static void sci_release_port(struct uart_port *port)
1489{
1490 /* Nothing here yet .. */
1491}
1492
1493static int sci_request_port(struct uart_port *port)
1494{
1495 /* Nothing here yet .. */
1496 return 0;
1497}
1498
1499static void sci_config_port(struct uart_port *port, int flags)
1500{
a5660ada 1501 struct sci_port *s = to_sci_port(port);
1da177e4
LT		 1502
1503 port->type = s->type;
1504
08f8cb31
MD		 1505 if (port->membase)
1506 return;
1507
1508 if (port->flags & UPF_IOREMAP) {
7ff731ae 1509 port->membase = ioremap_nocache(port->mapbase, 0x40);
08f8cb31
MD		 1510
1511 if (IS_ERR(port->membase))
1512 dev_err(port->dev, "can't remap port#%d\n", port->line);
1513 } else {
1514 /*
1515 * For the simple (and majority of) cases where we don't
1516 * need to do any remapping, just cast the cookie
1517 * directly.
1518 */
1519 port->membase = (void __iomem *)port->mapbase;
7ff731ae 1520 }
1da177e4
LT		 1521}
1522
1523static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1524{
a5660ada 1525 struct sci_port *s = to_sci_port(port);
1da177e4 1526
a62c4133 1527 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 1528 return -EINVAL;
1529 if (ser->baud_base < 2400)
1530 /* No paper tape reader for Mitch.. */
1531 return -EINVAL;
1532
1533 return 0;
1534}
1535
1536static struct uart_ops sci_uart_ops = {
1537 .tx_empty = sci_tx_empty,
1538 .set_mctrl = sci_set_mctrl,
1539 .get_mctrl = sci_get_mctrl,
1540 .start_tx = sci_start_tx,
1541 .stop_tx = sci_stop_tx,
1542 .stop_rx = sci_stop_rx,
1543 .enable_ms = sci_enable_ms,
1544 .break_ctl = sci_break_ctl,
1545 .startup = sci_startup,
1546 .shutdown = sci_shutdown,
1547 .set_termios = sci_set_termios,
1548 .type = sci_type,
1549 .release_port = sci_release_port,
1550 .request_port = sci_request_port,
1551 .config_port = sci_config_port,
1552 .verify_port = sci_verify_port,
07d2a1a1
PM		 1553#ifdef CONFIG_CONSOLE_POLL
1554 .poll_get_char = sci_poll_get_char,
1555 .poll_put_char = sci_poll_put_char,
1556#endif
1da177e4
LT		 1557};
1558
501b825d
MD		 1559static void __devinit sci_init_single(struct platform_device *dev,
1560 struct sci_port *sci_port,
08f8cb31
MD		 1561 unsigned int index,
1562 struct plat_sci_port *p)
e108b2ca 1563{
73a19e4c
GL		 1564 struct uart_port *port = &sci_port->port;
1565
1566 port->ops = &sci_uart_ops;
1567 port->iotype = UPIO_MEM;
1568 port->line = index;
75136d48
MP		 1569
1570 switch (p->type) {
1571 case PORT_SCIFA:
73a19e4c 1572 port->fifosize = 64;
75136d48
MP		 1573 break;
1574 case PORT_SCIF:
73a19e4c 1575 port->fifosize = 16;
75136d48
MP		 1576 break;
1577 default:
73a19e4c 1578 port->fifosize = 1;
75136d48
MP		 1579 break;
1580 }
7b6fd3bf
MD		 1581
1582 if (dev) {
1583 sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL;
1584 sci_port->dclk = clk_get(&dev->dev, "peripheral_clk");
1585 sci_port->enable = sci_clk_enable;
1586 sci_port->disable = sci_clk_disable;
73a19e4c 1587 port->dev = &dev->dev;
7b6fd3bf 1588 }
e108b2ca 1589
7ed7e071
MD		 1590 sci_port->break_timer.data = (unsigned long)sci_port;
1591 sci_port->break_timer.function = sci_break_timer;
1592 init_timer(&sci_port->break_timer);
1593
73a19e4c
GL		 1594 port->mapbase = p->mapbase;
1595 port->membase = p->membase;
7ed7e071 1596
73a19e4c
GL		 1597 port->irq = p->irqs[SCIx_TXI_IRQ];
1598 port->flags = p->flags;
1599 sci_port->type = port->type = p->type;
1600
1601#ifdef CONFIG_SERIAL_SH_SCI_DMA
1602 sci_port->dma_dev = p->dma_dev;
1603 sci_port->slave_tx = p->dma_slave_tx;
1604 sci_port->slave_rx = p->dma_slave_rx;
1605
1606 dev_dbg(port->dev, "%s: DMA device %p, tx %d, rx %d\n", __func__,
1607 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
1608#endif
7ed7e071
MD		 1609
1610 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
e108b2ca
PM		 1611}
1612
1da177e4 1613#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 1614static struct tty_driver *serial_console_device(struct console *co, int *index)
1615{
1616 struct uart_driver *p = &sci_uart_driver;
1617 *index = co->index;
1618 return p->tty_driver;
1619}
1620
1621static void serial_console_putchar(struct uart_port *port, int ch)
1622{
1623 sci_poll_put_char(port, ch);
1624}
1625
1da177e4
LT		 1626/*
1627 * Print a string to the serial port trying not to disturb
1628 * any possible real use of the port...
1629 */
1630static void serial_console_write(struct console *co, const char *s,
1631 unsigned count)
1632{
dc8e6f5b 1633 struct uart_port *port = co->data;
501b825d 1634 struct sci_port *sci_port = to_sci_port(port);
973e5d52 1635 unsigned short bits;
07d2a1a1 1636
501b825d
MD		 1637 if (sci_port->enable)
1638 sci_port->enable(port);
1639
1640 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 1641
1642 /* wait until fifo is empty and last bit has been transmitted */
1643 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1644 while ((sci_in(port, SCxSR) & bits) != bits)
1645 cpu_relax();
501b825d 1646
345e5a76 1647 if (sci_port->disable)
501b825d 1648 sci_port->disable(port);
1da177e4
LT		 1649}
1650
7b6fd3bf 1651static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 1652{
dc8e6f5b 1653 struct sci_port *sci_port;
1da177e4
LT		 1654 struct uart_port *port;
1655 int baud = 115200;
1656 int bits = 8;
1657 int parity = 'n';
1658 int flow = 'n';
1659 int ret;
1660
e108b2ca
PM		 1661 /*
1662 * Check whether an invalid uart number has been specified, and
1663 * if so, search for the first available port that does have
1664 * console support.
1665 */
1666 if (co->index >= SCI_NPORTS)
1667 co->index = 0;
1668
7b6fd3bf
MD		 1669 if (co->data) {
1670 port = co->data;
1671 sci_port = to_sci_port(port);
1672 } else {
1673 sci_port = &sci_ports[co->index];
1674 port = &sci_port->port;
1675 co->data = port;
1676 }
1da177e4
LT		 1677
1678 /*
e108b2ca
PM		 1679 * Also need to check port->type, we don't actually have any
1680 * UPIO_PORT ports, but uart_report_port() handily misreports
1681 * it anyways if we don't have a port available by the time this is
1682 * called.
1da177e4 1683 */
e108b2ca
PM		 1684 if (!port->type)
1685 return -ENODEV;
e108b2ca 1686
08f8cb31 1687 sci_config_port(port, 0);
e108b2ca 1688
dc8e6f5b
MD		 1689 if (sci_port->enable)
1690 sci_port->enable(port);
b7a76e4b 1691
1da177e4
LT		 1692 if (options)
1693 uart_parse_options(options, &baud, &parity, &bits, &flow);
1694
1695 ret = uart_set_options(port, co, baud, parity, bits, flow);
1696#if defined(__H8300H__) || defined(__H8300S__)
1697 /* disable rx interrupt */
1698 if (ret == 0)
1699 sci_stop_rx(port);
1700#endif
501b825d 1701 /* TODO: disable clock */
1da177e4
LT		 1702 return ret;
1703}
1704
1705static struct console serial_console = {
1706 .name = "ttySC",
dc8e6f5b 1707 .device = serial_console_device,
1da177e4
LT		 1708 .write = serial_console_write,
1709 .setup = serial_console_setup,
fa5da2f7 1710 .flags = CON_PRINTBUFFER,
1da177e4 1711 .index = -1,
1da177e4
LT		 1712};
1713
1714static int __init sci_console_init(void)
1715{
1716 register_console(&serial_console);
1717 return 0;
1718}
1da177e4 1719console_initcall(sci_console_init);
7b6fd3bf
MD		 1720
1721static struct sci_port early_serial_port;
1722static struct console early_serial_console = {
1723 .name = "early_ttySC",
1724 .write = serial_console_write,
1725 .flags = CON_PRINTBUFFER,
1726};
1727static char early_serial_buf[32];
1728
1da177e4
LT		 1729#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1730
07d2a1a1 1731#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
e7c98dc7 1732#define SCI_CONSOLE (&serial_console)
1da177e4 1733#else
b7a76e4b 1734#define SCI_CONSOLE 0
1da177e4
LT		 1735#endif
1736
1737static char banner[] __initdata =
1738 KERN_INFO "SuperH SCI(F) driver initialized\n";
1739
1740static struct uart_driver sci_uart_driver = {
1741 .owner = THIS_MODULE,
1742 .driver_name = "sci",
1da177e4
LT		 1743 .dev_name = "ttySC",
1744 .major = SCI_MAJOR,
1745 .minor = SCI_MINOR_START,
e108b2ca 1746 .nr = SCI_NPORTS,
1da177e4
LT		 1747 .cons = SCI_CONSOLE,
1748};
1749
e552de24 1750
54507f6e 1751static int sci_remove(struct platform_device *dev)
e552de24
MD		 1752{
1753 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1754 struct sci_port *p;
1755 unsigned long flags;
1756
e552de24 1757 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
e552de24
MD		 1758
1759 spin_lock_irqsave(&priv->lock, flags);
1760 list_for_each_entry(p, &priv->ports, node)
1761 uart_remove_one_port(&sci_uart_driver, &p->port);
e552de24
MD		 1762 spin_unlock_irqrestore(&priv->lock, flags);
1763
1764 kfree(priv);
1765 return 0;
1766}
1767
0ee70712
MD		 1768static int __devinit sci_probe_single(struct platform_device *dev,
1769 unsigned int index,
1770 struct plat_sci_port *p,
1771 struct sci_port *sciport)
1772{
1773 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1774 unsigned long flags;
1775 int ret;
1776
1777 /* Sanity check */
1778 if (unlikely(index >= SCI_NPORTS)) {
1779 dev_notice(&dev->dev, "Attempting to register port "
1780 "%d when only %d are available.\n",
1781 index+1, SCI_NPORTS);
1782 dev_notice(&dev->dev, "Consider bumping "
1783 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1784 return 0;
1785 }
1786
501b825d 1787 sci_init_single(dev, sciport, index, p);
0ee70712
MD		 1788
1789 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
08f8cb31 1790 if (ret)
0ee70712 1791 return ret;
0ee70712
MD		 1792
1793 INIT_LIST_HEAD(&sciport->node);
1794
1795 spin_lock_irqsave(&priv->lock, flags);
1796 list_add(&sciport->node, &priv->ports);
1797 spin_unlock_irqrestore(&priv->lock, flags);
1798
1799 return 0;
1800}
1801
e108b2ca
PM		 1802/*
1803 * Register a set of serial devices attached to a platform device. The
1804 * list is terminated with a zero flags entry, which means we expect
1805 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1806 * remapping (such as sh64) should also set UPF_IOREMAP.
1807 */
1808static int __devinit sci_probe(struct platform_device *dev)
1da177e4 1809{
e108b2ca 1810 struct plat_sci_port *p = dev->dev.platform_data;
e552de24 1811 struct sh_sci_priv *priv;
7ff731ae 1812 int i, ret = -EINVAL;
e552de24 1813
7b6fd3bf
MD		 1814#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1815 if (is_early_platform_device(dev)) {
1816 if (dev->id == -1)
1817 return -ENOTSUPP;
1818 early_serial_console.index = dev->id;
1819 early_serial_console.data = &early_serial_port.port;
1820 sci_init_single(NULL, &early_serial_port, dev->id, p);
1821 serial_console_setup(&early_serial_console, early_serial_buf);
1822 if (!strstr(early_serial_buf, "keep"))
1823 early_serial_console.flags |= CON_BOOT;
1824 register_console(&early_serial_console);
1825 return 0;
1826 }
1827#endif
1828
e552de24
MD		 1829 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1830 if (!priv)
1831 return -ENOMEM;
1832
1833 INIT_LIST_HEAD(&priv->ports);
1834 spin_lock_init(&priv->lock);
1835 platform_set_drvdata(dev, priv);
1836
e552de24
MD		 1837 priv->clk_nb.notifier_call = sci_notifier;
1838 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1da177e4 1839
0ee70712
MD		 1840 if (dev->id != -1) {
1841 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
1842 if (ret)
e552de24 1843 goto err_unreg;
0ee70712
MD		 1844 } else {
1845 for (i = 0; p && p->flags != 0; p++, i++) {
1846 ret = sci_probe_single(dev, i, p, &sci_ports[i]);
1847 if (ret)
1848 goto err_unreg;
e552de24 1849 }
e552de24 1850 }
1da177e4
LT		 1851
1852#ifdef CONFIG_SH_STANDARD_BIOS
1853 sh_bios_gdb_detach();
1854#endif
1855
e108b2ca 1856 return 0;
7ff731ae
PM		 1857
1858err_unreg:
e552de24 1859 sci_remove(dev);
7ff731ae 1860 return ret;
1da177e4
LT		 1861}
1862
6daa79b3 1863static int sci_suspend(struct device *dev)
1da177e4 1864{
6daa79b3 1865 struct sh_sci_priv *priv = dev_get_drvdata(dev);
e552de24
MD		 1866 struct sci_port *p;
1867 unsigned long flags;
e108b2ca 1868
e552de24
MD		 1869 spin_lock_irqsave(&priv->lock, flags);
1870 list_for_each_entry(p, &priv->ports, node)
1871 uart_suspend_port(&sci_uart_driver, &p->port);
e552de24 1872 spin_unlock_irqrestore(&priv->lock, flags);
1da177e4 1873
e108b2ca
PM		 1874 return 0;
1875}
1da177e4 1876
6daa79b3 1877static int sci_resume(struct device *dev)
e108b2ca 1878{
6daa79b3 1879 struct sh_sci_priv *priv = dev_get_drvdata(dev);
e552de24
MD		 1880 struct sci_port *p;
1881 unsigned long flags;
e108b2ca 1882
e552de24
MD		 1883 spin_lock_irqsave(&priv->lock, flags);
1884 list_for_each_entry(p, &priv->ports, node)
1885 uart_resume_port(&sci_uart_driver, &p->port);
e552de24 1886 spin_unlock_irqrestore(&priv->lock, flags);
e108b2ca
PM		 1887
1888 return 0;
1889}
1890
47145210 1891static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 1892 .suspend = sci_suspend,
1893 .resume = sci_resume,
1894};
1895
e108b2ca
PM		 1896static struct platform_driver sci_driver = {
1897 .probe = sci_probe,
b9e39c89 1898 .remove = sci_remove,
e108b2ca
PM		 1899 .driver = {
1900 .name = "sh-sci",
1901 .owner = THIS_MODULE,
6daa79b3 1902 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 1903 },
1904};
1905
1906static int __init sci_init(void)
1907{
1908 int ret;
1909
1910 printk(banner);
1911
e108b2ca
PM		 1912 ret = uart_register_driver(&sci_uart_driver);
1913 if (likely(ret == 0)) {
1914 ret = platform_driver_register(&sci_driver);
1915 if (unlikely(ret))
1916 uart_unregister_driver(&sci_uart_driver);
1917 }
1918
1919 return ret;
1920}
1921
1922static void __exit sci_exit(void)
1923{
1924 platform_driver_unregister(&sci_driver);
1da177e4
LT		 1925 uart_unregister_driver(&sci_uart_driver);
1926}
1927
7b6fd3bf
MD		 1928#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1929early_platform_init_buffer("earlyprintk", &sci_driver,
1930 early_serial_buf, ARRAY_SIZE(early_serial_buf));
1931#endif
1da177e4
LT		 1932module_init(sci_init);
1933module_exit(sci_exit);
1934
e108b2ca 1935MODULE_LICENSE("GPL");
e169c139 1936MODULE_ALIAS("platform:sh-sci");
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