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1da177e4
LT
1/*
2 * drivers/serial/mpc52xx_uart.c
3 *
4 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
5 *
6 * FIXME According to the usermanual the status bits in the status register
7 * are only updated when the peripherals access the FIFO and not when the
8 * CPU access them. So since we use this bits to know when we stop writing
9 * and reading, they may not be updated in-time and a race condition may
10 * exists. But I haven't be able to prove this and I don't care. But if
11 * any problem arises, it might worth checking. The TX/RX FIFO Stats
12 * registers should be used in addition.
13 * Update: Actually, they seem updated ... At least the bits we use.
14 *
15 *
16 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
17 *
18 * Some of the code has been inspired/copied from the 2.4 code written
19 * by Dale Farnsworth <dfarnsworth@mvista.com>.
20 *
21 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
22 * Copyright (C) 2003 MontaVista, Software, Inc.
23 *
24 * This file is licensed under the terms of the GNU General Public License
25 * version 2. This program is licensed "as is" without any warranty of any
26 * kind, whether express or implied.
27 */
28
29/* Platform device Usage :
30 *
31 * Since PSCs can have multiple function, the correct driver for each one
32 * is selected by calling mpc52xx_match_psc_function(...). The function
33 * handled by this driver is "uart".
34 *
35 * The driver init all necessary registers to place the PSC in uart mode without
36 * DCD. However, the pin multiplexing aren't changed and should be set either
37 * by the bootloader or in the platform init code.
38 *
39 * The idx field must be equal to the PSC index ( e.g. 0 for PSC1, 1 for PSC2,
d62de3aa
SM
40 * and so on). So the PSC1 is mapped to /dev/ttyPSC0, PSC2 to /dev/ttyPSC1 and
41 * so on. But be warned, it's an ABSOLUTE REQUIREMENT ! This is needed mainly
42 * fpr the console code : without this 1:1 mapping, at early boot time, when we
c30fe7f7 43 * are parsing the kernel args console=ttyPSC?, we wouldn't know which PSC it
d62de3aa 44 * will be mapped to.
1da177e4
LT
45 */
46
d052d1be 47#include <linux/platform_device.h>
1da177e4
LT
48#include <linux/module.h>
49#include <linux/tty.h>
50#include <linux/serial.h>
51#include <linux/sysrq.h>
52#include <linux/console.h>
53
54#include <asm/delay.h>
55#include <asm/io.h>
56
57#include <asm/mpc52xx.h>
58#include <asm/mpc52xx_psc.h>
59
60#if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
61#define SUPPORT_SYSRQ
62#endif
63
64#include <linux/serial_core.h>
65
66
d62de3aa
SM
67/* We've been assigned a range on the "Low-density serial ports" major */
68#define SERIAL_PSC_MAJOR 204
69#define SERIAL_PSC_MINOR 148
70
1da177e4
LT
71
72#define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
73
74
75static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
76 /* Rem: - We use the read_status_mask as a shadow of
77 * psc->mpc52xx_psc_imr
78 * - It's important that is array is all zero on start as we
79 * use it to know if it's initialized or not ! If it's not sure
80 * it's cleared, then a memset(...,0,...) should be added to
81 * the console_init
82 */
83
84#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
85
86
87/* Forward declaration of the interruption handling routine */
88static irqreturn_t mpc52xx_uart_int(int irq,void *dev_id,struct pt_regs *regs);
89
90
91/* Simple macro to test if a port is console or not. This one is taken
92 * for serial_core.c and maybe should be moved to serial_core.h ? */
93#ifdef CONFIG_SERIAL_CORE_CONSOLE
94#define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line)
95#else
96#define uart_console(port) (0)
97#endif
98
99
100/* ======================================================================== */
101/* UART operations */
102/* ======================================================================== */
103
104static unsigned int
105mpc52xx_uart_tx_empty(struct uart_port *port)
106{
107 int status = in_be16(&PSC(port)->mpc52xx_psc_status);
108 return (status & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0;
109}
110
111static void
112mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
113{
114 /* Not implemented */
115}
116
117static unsigned int
118mpc52xx_uart_get_mctrl(struct uart_port *port)
119{
120 /* Not implemented */
121 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
122}
123
124static void
b129a8cc 125mpc52xx_uart_stop_tx(struct uart_port *port)
1da177e4
LT
126{
127 /* port->lock taken by caller */
128 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
129 out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask);
130}
131
132static void
b129a8cc 133mpc52xx_uart_start_tx(struct uart_port *port)
1da177e4
LT
134{
135 /* port->lock taken by caller */
136 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
137 out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask);
138}
139
140static void
141mpc52xx_uart_send_xchar(struct uart_port *port, char ch)
142{
143 unsigned long flags;
144 spin_lock_irqsave(&port->lock, flags);
145
146 port->x_char = ch;
147 if (ch) {
148 /* Make sure tx interrupts are on */
149 /* Truly necessary ??? They should be anyway */
150 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
151 out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask);
152 }
153
154 spin_unlock_irqrestore(&port->lock, flags);
155}
156
157static void
158mpc52xx_uart_stop_rx(struct uart_port *port)
159{
160 /* port->lock taken by caller */
161 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
162 out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask);
163}
164
165static void
166mpc52xx_uart_enable_ms(struct uart_port *port)
167{
168 /* Not implemented */
169}
170
171static void
172mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
173{
174 unsigned long flags;
175 spin_lock_irqsave(&port->lock, flags);
176
177 if ( ctl == -1 )
178 out_8(&PSC(port)->command,MPC52xx_PSC_START_BRK);
179 else
180 out_8(&PSC(port)->command,MPC52xx_PSC_STOP_BRK);
181
182 spin_unlock_irqrestore(&port->lock, flags);
183}
184
185static int
186mpc52xx_uart_startup(struct uart_port *port)
187{
188 struct mpc52xx_psc __iomem *psc = PSC(port);
189 int ret;
190
191 /* Request IRQ */
192 ret = request_irq(port->irq, mpc52xx_uart_int,
40663cc7 193 IRQF_DISABLED | IRQF_SAMPLE_RANDOM, "mpc52xx_psc_uart", port);
1da177e4
LT
194 if (ret)
195 return ret;
196
197 /* Reset/activate the port, clear and enable interrupts */
198 out_8(&psc->command,MPC52xx_PSC_RST_RX);
199 out_8(&psc->command,MPC52xx_PSC_RST_TX);
200
201 out_be32(&psc->sicr,0); /* UART mode DCD ignored */
202
203 out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00); /* /16 prescaler on */
204
205 out_8(&psc->rfcntl, 0x00);
206 out_be16(&psc->rfalarm, 0x1ff);
207 out_8(&psc->tfcntl, 0x07);
208 out_be16(&psc->tfalarm, 0x80);
209
210 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
211 out_be16(&psc->mpc52xx_psc_imr,port->read_status_mask);
212
213 out_8(&psc->command,MPC52xx_PSC_TX_ENABLE);
214 out_8(&psc->command,MPC52xx_PSC_RX_ENABLE);
215
216 return 0;
217}
218
219static void
220mpc52xx_uart_shutdown(struct uart_port *port)
221{
222 struct mpc52xx_psc __iomem *psc = PSC(port);
223
224 /* Shut down the port, interrupt and all */
225 out_8(&psc->command,MPC52xx_PSC_RST_RX);
226 out_8(&psc->command,MPC52xx_PSC_RST_TX);
227
228 port->read_status_mask = 0;
229 out_be16(&psc->mpc52xx_psc_imr,port->read_status_mask);
230
231 /* Release interrupt */
232 free_irq(port->irq, port);
233}
234
235static void
236mpc52xx_uart_set_termios(struct uart_port *port, struct termios *new,
237 struct termios *old)
238{
239 struct mpc52xx_psc __iomem *psc = PSC(port);
240 unsigned long flags;
241 unsigned char mr1, mr2;
242 unsigned short ctr;
243 unsigned int j, baud, quot;
244
245 /* Prepare what we're gonna write */
246 mr1 = 0;
247
248 switch (new->c_cflag & CSIZE) {
249 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
250 break;
251 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
252 break;
253 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
254 break;
255 case CS8:
256 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
257 }
258
259 if (new->c_cflag & PARENB) {
260 mr1 |= (new->c_cflag & PARODD) ?
261 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
262 } else
263 mr1 |= MPC52xx_PSC_MODE_PARNONE;
264
265
266 mr2 = 0;
267
268 if (new->c_cflag & CSTOPB)
269 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
270 else
271 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
272 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
273 MPC52xx_PSC_MODE_ONE_STOP;
274
275
276 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
277 quot = uart_get_divisor(port, baud);
278 ctr = quot & 0xffff;
279
280 /* Get the lock */
281 spin_lock_irqsave(&port->lock, flags);
282
283 /* Update the per-port timeout */
284 uart_update_timeout(port, new->c_cflag, baud);
285
286 /* Do our best to flush TX & RX, so we don't loose anything */
287 /* But we don't wait indefinitly ! */
288 j = 5000000; /* Maximum wait */
289 /* FIXME Can't receive chars since set_termios might be called at early
290 * boot for the console, all stuff is not yet ready to receive at that
291 * time and that just makes the kernel oops */
292 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
293 while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP) &&
294 --j)
295 udelay(1);
296
297 if (!j)
298 printk( KERN_ERR "mpc52xx_uart.c: "
299 "Unable to flush RX & TX fifos in-time in set_termios."
300 "Some chars may have been lost.\n" );
301
302 /* Reset the TX & RX */
303 out_8(&psc->command,MPC52xx_PSC_RST_RX);
304 out_8(&psc->command,MPC52xx_PSC_RST_TX);
305
306 /* Send new mode settings */
307 out_8(&psc->command,MPC52xx_PSC_SEL_MODE_REG_1);
308 out_8(&psc->mode,mr1);
309 out_8(&psc->mode,mr2);
310 out_8(&psc->ctur,ctr >> 8);
311 out_8(&psc->ctlr,ctr & 0xff);
312
313 /* Reenable TX & RX */
314 out_8(&psc->command,MPC52xx_PSC_TX_ENABLE);
315 out_8(&psc->command,MPC52xx_PSC_RX_ENABLE);
316
317 /* We're all set, release the lock */
318 spin_unlock_irqrestore(&port->lock, flags);
319}
320
321static const char *
322mpc52xx_uart_type(struct uart_port *port)
323{
324 return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL;
325}
326
327static void
328mpc52xx_uart_release_port(struct uart_port *port)
329{
330 if (port->flags & UPF_IOREMAP) { /* remapped by us ? */
331 iounmap(port->membase);
332 port->membase = NULL;
333 }
334
335 release_mem_region(port->mapbase, MPC52xx_PSC_SIZE);
336}
337
338static int
339mpc52xx_uart_request_port(struct uart_port *port)
340{
be618f55
AL
341 int err;
342
1da177e4
LT
343 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
344 port->membase = ioremap(port->mapbase, MPC52xx_PSC_SIZE);
345
346 if (!port->membase)
347 return -EINVAL;
348
be618f55 349 err = request_mem_region(port->mapbase, MPC52xx_PSC_SIZE,
1da177e4 350 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
be618f55
AL
351
352 if (err && (port->flags & UPF_IOREMAP)) {
353 iounmap(port->membase);
354 port->membase = NULL;
355 }
356
357 return err;
1da177e4
LT
358}
359
360static void
361mpc52xx_uart_config_port(struct uart_port *port, int flags)
362{
363 if ( (flags & UART_CONFIG_TYPE) &&
364 (mpc52xx_uart_request_port(port) == 0) )
365 port->type = PORT_MPC52xx;
366}
367
368static int
369mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
370{
371 if ( ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx )
372 return -EINVAL;
373
374 if ( (ser->irq != port->irq) ||
375 (ser->io_type != SERIAL_IO_MEM) ||
376 (ser->baud_base != port->uartclk) ||
377 (ser->iomem_base != (void*)port->mapbase) ||
378 (ser->hub6 != 0 ) )
379 return -EINVAL;
380
381 return 0;
382}
383
384
385static struct uart_ops mpc52xx_uart_ops = {
386 .tx_empty = mpc52xx_uart_tx_empty,
387 .set_mctrl = mpc52xx_uart_set_mctrl,
388 .get_mctrl = mpc52xx_uart_get_mctrl,
389 .stop_tx = mpc52xx_uart_stop_tx,
390 .start_tx = mpc52xx_uart_start_tx,
391 .send_xchar = mpc52xx_uart_send_xchar,
392 .stop_rx = mpc52xx_uart_stop_rx,
393 .enable_ms = mpc52xx_uart_enable_ms,
394 .break_ctl = mpc52xx_uart_break_ctl,
395 .startup = mpc52xx_uart_startup,
396 .shutdown = mpc52xx_uart_shutdown,
397 .set_termios = mpc52xx_uart_set_termios,
398/* .pm = mpc52xx_uart_pm, Not supported yet */
399/* .set_wake = mpc52xx_uart_set_wake, Not supported yet */
400 .type = mpc52xx_uart_type,
401 .release_port = mpc52xx_uart_release_port,
402 .request_port = mpc52xx_uart_request_port,
403 .config_port = mpc52xx_uart_config_port,
404 .verify_port = mpc52xx_uart_verify_port
405};
406
407
408/* ======================================================================== */
409/* Interrupt handling */
410/* ======================================================================== */
411
412static inline int
413mpc52xx_uart_int_rx_chars(struct uart_port *port, struct pt_regs *regs)
414{
415 struct tty_struct *tty = port->info->tty;
33f0f88f 416 unsigned char ch, flag;
1da177e4
LT
417 unsigned short status;
418
419 /* While we can read, do so ! */
420 while ( (status = in_be16(&PSC(port)->mpc52xx_psc_status)) &
421 MPC52xx_PSC_SR_RXRDY) {
422
1da177e4
LT
423 /* Get the char */
424 ch = in_8(&PSC(port)->mpc52xx_psc_buffer_8);
425
426 /* Handle sysreq char */
427#ifdef SUPPORT_SYSRQ
428 if (uart_handle_sysrq_char(port, ch, regs)) {
429 port->sysrq = 0;
430 continue;
431 }
432#endif
433
434 /* Store it */
33f0f88f
AC
435
436 flag = TTY_NORMAL;
1da177e4
LT
437 port->icount.rx++;
438
439 if ( status & (MPC52xx_PSC_SR_PE |
440 MPC52xx_PSC_SR_FE |
33f0f88f 441 MPC52xx_PSC_SR_RB) ) {
1da177e4
LT
442
443 if (status & MPC52xx_PSC_SR_RB) {
33f0f88f 444 flag = TTY_BREAK;
1da177e4
LT
445 uart_handle_break(port);
446 } else if (status & MPC52xx_PSC_SR_PE)
33f0f88f 447 flag = TTY_PARITY;
1da177e4 448 else if (status & MPC52xx_PSC_SR_FE)
33f0f88f 449 flag = TTY_FRAME;
1da177e4
LT
450
451 /* Clear error condition */
452 out_8(&PSC(port)->command,MPC52xx_PSC_RST_ERR_STAT);
453
454 }
33f0f88f
AC
455 tty_insert_flip_char(tty, ch, flag);
456 if (status & MPC52xx_PSC_SR_OE) {
457 /*
458 * Overrun is special, since it's
459 * reported immediately, and doesn't
460 * affect the current character
461 */
462 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
463 }
1da177e4
LT
464 }
465
466 tty_flip_buffer_push(tty);
467
468 return in_be16(&PSC(port)->mpc52xx_psc_status) & MPC52xx_PSC_SR_RXRDY;
469}
470
471static inline int
472mpc52xx_uart_int_tx_chars(struct uart_port *port)
473{
474 struct circ_buf *xmit = &port->info->xmit;
475
476 /* Process out of band chars */
477 if (port->x_char) {
478 out_8(&PSC(port)->mpc52xx_psc_buffer_8, port->x_char);
479 port->icount.tx++;
480 port->x_char = 0;
481 return 1;
482 }
483
484 /* Nothing to do ? */
485 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
b129a8cc 486 mpc52xx_uart_stop_tx(port);
1da177e4
LT
487 return 0;
488 }
489
490 /* Send chars */
491 while (in_be16(&PSC(port)->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXRDY) {
492 out_8(&PSC(port)->mpc52xx_psc_buffer_8, xmit->buf[xmit->tail]);
493 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
494 port->icount.tx++;
495 if (uart_circ_empty(xmit))
496 break;
497 }
498
499 /* Wake up */
500 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
501 uart_write_wakeup(port);
502
503 /* Maybe we're done after all */
504 if (uart_circ_empty(xmit)) {
b129a8cc 505 mpc52xx_uart_stop_tx(port);
1da177e4
LT
506 return 0;
507 }
508
509 return 1;
510}
511
512static irqreturn_t
513mpc52xx_uart_int(int irq, void *dev_id, struct pt_regs *regs)
514{
515 struct uart_port *port = (struct uart_port *) dev_id;
516 unsigned long pass = ISR_PASS_LIMIT;
517 unsigned int keepgoing;
518 unsigned short status;
519
520 if ( irq != port->irq ) {
521 printk( KERN_WARNING
522 "mpc52xx_uart_int : " \
523 "Received wrong int %d. Waiting for %d\n",
524 irq, port->irq);
525 return IRQ_NONE;
526 }
527
528 spin_lock(&port->lock);
529
530 /* While we have stuff to do, we continue */
531 do {
532 /* If we don't find anything to do, we stop */
533 keepgoing = 0;
534
535 /* Read status */
536 status = in_be16(&PSC(port)->mpc52xx_psc_isr);
537 status &= port->read_status_mask;
538
539 /* Do we need to receive chars ? */
540 /* For this RX interrupts must be on and some chars waiting */
541 if ( status & MPC52xx_PSC_IMR_RXRDY )
542 keepgoing |= mpc52xx_uart_int_rx_chars(port, regs);
543
544 /* Do we need to send chars ? */
545 /* For this, TX must be ready and TX interrupt enabled */
546 if ( status & MPC52xx_PSC_IMR_TXRDY )
547 keepgoing |= mpc52xx_uart_int_tx_chars(port);
548
549 /* Limit number of iteration */
550 if ( !(--pass) )
551 keepgoing = 0;
552
553 } while (keepgoing);
554
555 spin_unlock(&port->lock);
556
557 return IRQ_HANDLED;
558}
559
560
561/* ======================================================================== */
562/* Console ( if applicable ) */
563/* ======================================================================== */
564
565#ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
566
567static void __init
568mpc52xx_console_get_options(struct uart_port *port,
569 int *baud, int *parity, int *bits, int *flow)
570{
571 struct mpc52xx_psc __iomem *psc = PSC(port);
572 unsigned char mr1;
573
574 /* Read the mode registers */
575 out_8(&psc->command,MPC52xx_PSC_SEL_MODE_REG_1);
576 mr1 = in_8(&psc->mode);
577
578 /* CT{U,L}R are write-only ! */
579 *baud = __res.bi_baudrate ?
580 __res.bi_baudrate : CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
581
582 /* Parse them */
583 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
584 case MPC52xx_PSC_MODE_5_BITS: *bits = 5; break;
585 case MPC52xx_PSC_MODE_6_BITS: *bits = 6; break;
586 case MPC52xx_PSC_MODE_7_BITS: *bits = 7; break;
587 case MPC52xx_PSC_MODE_8_BITS:
588 default: *bits = 8;
589 }
590
591 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
592 *parity = 'n';
593 else
594 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
595}
596
597static void
598mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
599{
600 struct uart_port *port = &mpc52xx_uart_ports[co->index];
601 struct mpc52xx_psc __iomem *psc = PSC(port);
602 unsigned int i, j;
603
604 /* Disable interrupts */
605 out_be16(&psc->mpc52xx_psc_imr, 0);
606
607 /* Wait the TX buffer to be empty */
608 j = 5000000; /* Maximum wait */
609 while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP) &&
610 --j)
611 udelay(1);
612
613 /* Write all the chars */
d358788f 614 for (i = 0; i < count; i++, s++) {
1da177e4 615 /* Line return handling */
d358788f 616 if (*s == '\n')
1da177e4
LT
617 out_8(&psc->mpc52xx_psc_buffer_8, '\r');
618
d358788f
RK
619 /* Send the char */
620 out_8(&psc->mpc52xx_psc_buffer_8, *s);
621
1da177e4
LT
622 /* Wait the TX buffer to be empty */
623 j = 20000; /* Maximum wait */
624 while (!(in_be16(&psc->mpc52xx_psc_status) &
625 MPC52xx_PSC_SR_TXEMP) && --j)
626 udelay(1);
627 }
628
629 /* Restore interrupt state */
630 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
631}
632
633static int __init
634mpc52xx_console_setup(struct console *co, char *options)
635{
636 struct uart_port *port = &mpc52xx_uart_ports[co->index];
637
638 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
639 int bits = 8;
640 int parity = 'n';
641 int flow = 'n';
642
643 if (co->index < 0 || co->index >= MPC52xx_PSC_MAXNUM)
644 return -EINVAL;
645
646 /* Basic port init. Needed since we use some uart_??? func before
647 * real init for early access */
648 spin_lock_init(&port->lock);
649 port->uartclk = __res.bi_ipbfreq / 2; /* Look at CTLR doc */
650 port->ops = &mpc52xx_uart_ops;
651 port->mapbase = MPC52xx_PA(MPC52xx_PSCx_OFFSET(co->index+1));
652
653 /* We ioremap ourself */
654 port->membase = ioremap(port->mapbase, MPC52xx_PSC_SIZE);
655 if (port->membase == NULL)
656 return -EINVAL;
657
658 /* Setup the port parameters accoding to options */
659 if (options)
660 uart_parse_options(options, &baud, &parity, &bits, &flow);
661 else
662 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
663
664 return uart_set_options(port, co, baud, parity, bits, flow);
665}
666
667
2d8179c0 668static struct uart_driver mpc52xx_uart_driver;
1da177e4
LT
669
670static struct console mpc52xx_console = {
d62de3aa 671 .name = "ttyPSC",
1da177e4
LT
672 .write = mpc52xx_console_write,
673 .device = uart_console_device,
674 .setup = mpc52xx_console_setup,
675 .flags = CON_PRINTBUFFER,
d62de3aa 676 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0 ) */
1da177e4
LT
677 .data = &mpc52xx_uart_driver,
678};
679
680
681static int __init
682mpc52xx_console_init(void)
683{
684 register_console(&mpc52xx_console);
685 return 0;
686}
687
688console_initcall(mpc52xx_console_init);
689
690#define MPC52xx_PSC_CONSOLE &mpc52xx_console
691#else
692#define MPC52xx_PSC_CONSOLE NULL
693#endif
694
695
696/* ======================================================================== */
697/* UART Driver */
698/* ======================================================================== */
699
700static struct uart_driver mpc52xx_uart_driver = {
701 .owner = THIS_MODULE,
702 .driver_name = "mpc52xx_psc_uart",
d62de3aa 703 .dev_name = "ttyPSC",
d62de3aa
SM
704 .major = SERIAL_PSC_MAJOR,
705 .minor = SERIAL_PSC_MINOR,
1da177e4
LT
706 .nr = MPC52xx_PSC_MAXNUM,
707 .cons = MPC52xx_PSC_CONSOLE,
708};
709
710
711/* ======================================================================== */
712/* Platform Driver */
713/* ======================================================================== */
714
715static int __devinit
3ae5eaec 716mpc52xx_uart_probe(struct platform_device *dev)
1da177e4 717{
3ae5eaec 718 struct resource *res = dev->resource;
1da177e4
LT
719
720 struct uart_port *port = NULL;
721 int i, idx, ret;
722
723 /* Check validity & presence */
38801e2e 724 idx = dev->id;
1da177e4
LT
725 if (idx < 0 || idx >= MPC52xx_PSC_MAXNUM)
726 return -EINVAL;
727
728 if (!mpc52xx_match_psc_function(idx,"uart"))
729 return -ENODEV;
730
731 /* Init the port structure */
732 port = &mpc52xx_uart_ports[idx];
733
734 memset(port, 0x00, sizeof(struct uart_port));
735
736 spin_lock_init(&port->lock);
737 port->uartclk = __res.bi_ipbfreq / 2; /* Look at CTLR doc */
947deee8 738 port->fifosize = 512;
1da177e4
LT
739 port->iotype = UPIO_MEM;
740 port->flags = UPF_BOOT_AUTOCONF |
741 ( uart_console(port) ? 0 : UPF_IOREMAP );
742 port->line = idx;
743 port->ops = &mpc52xx_uart_ops;
744
745 /* Search for IRQ and mapbase */
38801e2e 746 for (i=0 ; i<dev->num_resources ; i++, res++) {
1da177e4
LT
747 if (res->flags & IORESOURCE_MEM)
748 port->mapbase = res->start;
749 else if (res->flags & IORESOURCE_IRQ)
750 port->irq = res->start;
751 }
752 if (!port->irq || !port->mapbase)
753 return -EINVAL;
754
755 /* Add the port to the uart sub-system */
756 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
757 if (!ret)
3ae5eaec 758 platform_set_drvdata(dev, (void*)port);
1da177e4
LT
759
760 return ret;
761}
762
763static int
3ae5eaec 764mpc52xx_uart_remove(struct platform_device *dev)
1da177e4 765{
3ae5eaec 766 struct uart_port *port = (struct uart_port *) platform_get_drvdata(dev);
1da177e4 767
3ae5eaec 768 platform_set_drvdata(dev, NULL);
1da177e4
LT
769
770 if (port)
771 uart_remove_one_port(&mpc52xx_uart_driver, port);
772
773 return 0;
774}
775
776#ifdef CONFIG_PM
777static int
3ae5eaec 778mpc52xx_uart_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 779{
3ae5eaec 780 struct uart_port *port = (struct uart_port *) platform_get_drvdata(dev);
1da177e4 781
9480e307 782 if (sport)
1da177e4
LT
783 uart_suspend_port(&mpc52xx_uart_driver, port);
784
785 return 0;
786}
787
788static int
3ae5eaec 789mpc52xx_uart_resume(struct platform_device *dev)
1da177e4 790{
3ae5eaec 791 struct uart_port *port = (struct uart_port *) platform_get_drvdata(dev);
1da177e4 792
9480e307 793 if (port)
1da177e4
LT
794 uart_resume_port(&mpc52xx_uart_driver, port);
795
796 return 0;
797}
798#endif
799
3ae5eaec 800static struct platform_driver mpc52xx_uart_platform_driver = {
1da177e4
LT
801 .probe = mpc52xx_uart_probe,
802 .remove = mpc52xx_uart_remove,
803#ifdef CONFIG_PM
804 .suspend = mpc52xx_uart_suspend,
805 .resume = mpc52xx_uart_resume,
806#endif
3ae5eaec
RK
807 .driver = {
808 .name = "mpc52xx-psc",
809 },
1da177e4
LT
810};
811
812
813/* ======================================================================== */
814/* Module */
815/* ======================================================================== */
816
817static int __init
818mpc52xx_uart_init(void)
819{
820 int ret;
821
822 printk(KERN_INFO "Serial: MPC52xx PSC driver\n");
823
824 ret = uart_register_driver(&mpc52xx_uart_driver);
825 if (ret == 0) {
3ae5eaec 826 ret = platform_driver_register(&mpc52xx_uart_platform_driver);
1da177e4
LT
827 if (ret)
828 uart_unregister_driver(&mpc52xx_uart_driver);
829 }
830
831 return ret;
832}
833
834static void __exit
835mpc52xx_uart_exit(void)
836{
3ae5eaec 837 platform_driver_unregister(&mpc52xx_uart_platform_driver);
1da177e4
LT
838 uart_unregister_driver(&mpc52xx_uart_driver);
839}
840
841
842module_init(mpc52xx_uart_init);
843module_exit(mpc52xx_uart_exit);
844
845MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
846MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
847MODULE_LICENSE("GPL");