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2f351741 | 1 | /* |
ccf68e59 | 2 | * Blackfin On-Chip Sport Emulated UART Driver |
2f351741 | 3 | * |
ccf68e59 | 4 | * Copyright 2006-2009 Analog Devices Inc. |
2f351741 | 5 | * |
ccf68e59 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
2f351741 | 7 | * |
ccf68e59 | 8 | * Licensed under the GPL-2 or later. |
2f351741 BW |
9 | */ |
10 | ||
11 | /* | |
12 | * This driver and the hardware supported are in term of EE-191 of ADI. | |
13 | * http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf | |
14 | * This application note describe how to implement a UART on a Sharc DSP, | |
15 | * but this driver is implemented on Blackfin Processor. | |
ccf68e59 | 16 | * Transmit Frame Sync is not used by this driver to transfer data out. |
2f351741 BW |
17 | */ |
18 | ||
ccf68e59 | 19 | /* #define DEBUG */ |
2f351741 | 20 | |
ccf68e59 | 21 | #define DRV_NAME "bfin-sport-uart" |
22 | #define DEVICE_NAME "ttySS" | |
23 | #define pr_fmt(fmt) DRV_NAME ": " fmt | |
2f351741 BW |
24 | |
25 | #include <linux/module.h> | |
26 | #include <linux/ioport.h> | |
ccf68e59 | 27 | #include <linux/io.h> |
2f351741 BW |
28 | #include <linux/init.h> |
29 | #include <linux/console.h> | |
30 | #include <linux/sysrq.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2f351741 BW |
32 | #include <linux/platform_device.h> |
33 | #include <linux/tty.h> | |
34 | #include <linux/tty_flip.h> | |
35 | #include <linux/serial_core.h> | |
36 | ||
37 | #include <asm/delay.h> | |
38 | #include <asm/portmux.h> | |
39 | ||
40 | #include "bfin_sport_uart.h" | |
41 | ||
2f351741 BW |
42 | struct sport_uart_port { |
43 | struct uart_port port; | |
2f351741 | 44 | int err_irq; |
ccf68e59 | 45 | unsigned short csize; |
46 | unsigned short rxmask; | |
47 | unsigned short txmask1; | |
48 | unsigned short txmask2; | |
49 | unsigned char stopb; | |
50 | /* unsigned char parib; */ | |
2f351741 BW |
51 | }; |
52 | ||
53 | static void sport_uart_tx_chars(struct sport_uart_port *up); | |
54 | static void sport_stop_tx(struct uart_port *port); | |
55 | ||
56 | static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value) | |
57 | { | |
ccf68e59 | 58 | pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value, |
59 | up->txmask1, up->txmask2); | |
60 | ||
61 | /* Place Start and Stop bits */ | |
4328e3e5 | 62 | __asm__ __volatile__ ( |
ccf68e59 | 63 | "%[val] <<= 1;" |
64 | "%[val] = %[val] & %[mask1];" | |
65 | "%[val] = %[val] | %[mask2];" | |
66 | : [val]"+d"(value) | |
67 | : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2) | |
68 | : "ASTAT" | |
4328e3e5 | 69 | ); |
6ef53066 | 70 | pr_debug("%s value:%x\n", __func__, value); |
2f351741 BW |
71 | |
72 | SPORT_PUT_TX(up, value); | |
73 | } | |
74 | ||
ccf68e59 | 75 | static inline unsigned char rx_one_byte(struct sport_uart_port *up) |
2f351741 | 76 | { |
ccf68e59 | 77 | unsigned int value; |
78 | unsigned char extract; | |
4328e3e5 | 79 | u32 tmp_mask1, tmp_mask2, tmp_shift, tmp; |
2f351741 | 80 | |
ccf68e59 | 81 | if ((up->csize + up->stopb) > 7) |
82 | value = SPORT_GET_RX32(up); | |
83 | else | |
84 | value = SPORT_GET_RX(up); | |
85 | ||
86 | pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value, | |
87 | up->csize, up->rxmask); | |
2f351741 | 88 | |
ccf68e59 | 89 | /* Extract data */ |
4328e3e5 MF |
90 | __asm__ __volatile__ ( |
91 | "%[extr] = 0;" | |
ccf68e59 | 92 | "%[mask1] = %[rxmask];" |
93 | "%[mask2] = 0x0200(Z);" | |
4328e3e5 MF |
94 | "%[shift] = 0;" |
95 | "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];" | |
96 | ".Lloop_s:" | |
97 | "%[tmp] = extract(%[val], %[mask1].L)(Z);" | |
98 | "%[tmp] <<= %[shift];" | |
99 | "%[extr] = %[extr] | %[tmp];" | |
100 | "%[mask1] = %[mask1] - %[mask2];" | |
101 | ".Lloop_e:" | |
102 | "%[shift] += 1;" | |
ccf68e59 | 103 | : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp), |
104 | [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2) | |
105 | : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize) | |
4328e3e5 MF |
106 | : "ASTAT", "LB0", "LC0", "LT0" |
107 | ); | |
2f351741 BW |
108 | |
109 | pr_debug(" extract:%x\n", extract); | |
110 | return extract; | |
111 | } | |
112 | ||
ccf68e59 | 113 | static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate) |
2f351741 | 114 | { |
ccf68e59 | 115 | int tclkdiv, rclkdiv; |
116 | unsigned int sclk = get_sclk(); | |
2f351741 | 117 | |
ccf68e59 | 118 | /* Set TCR1 and TCR2, TFSR is not enabled for uart */ |
119 | SPORT_PUT_TCR1(up, (ITFS | TLSBIT | ITCLK)); | |
120 | SPORT_PUT_TCR2(up, size + 1); | |
6ef53066 | 121 | pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up)); |
2f351741 BW |
122 | |
123 | /* Set RCR1 and RCR2 */ | |
124 | SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK)); | |
ccf68e59 | 125 | SPORT_PUT_RCR2(up, (size + 1) * 2 - 1); |
6ef53066 | 126 | pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up)); |
2f351741 | 127 | |
ccf68e59 | 128 | tclkdiv = sclk / (2 * baud_rate) - 1; |
129 | rclkdiv = sclk / (2 * baud_rate * 2) - 1; | |
2f351741 | 130 | SPORT_PUT_TCLKDIV(up, tclkdiv); |
2f351741 BW |
131 | SPORT_PUT_RCLKDIV(up, rclkdiv); |
132 | SSYNC(); | |
ccf68e59 | 133 | pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n", |
134 | __func__, sclk, baud_rate, tclkdiv, rclkdiv); | |
2f351741 BW |
135 | |
136 | return 0; | |
137 | } | |
138 | ||
139 | static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id) | |
140 | { | |
141 | struct sport_uart_port *up = dev_id; | |
ebd2c8f6 | 142 | struct tty_struct *tty = up->port.state->port.tty; |
2f351741 BW |
143 | unsigned int ch; |
144 | ||
ccf68e59 | 145 | spin_lock(&up->port.lock); |
146 | ||
147 | while (SPORT_GET_STAT(up) & RXNE) { | |
2f351741 BW |
148 | ch = rx_one_byte(up); |
149 | up->port.icount.rx++; | |
150 | ||
ccf68e59 | 151 | if (!uart_handle_sysrq_char(&up->port, ch)) |
2f351741 | 152 | tty_insert_flip_char(tty, ch, TTY_NORMAL); |
ccf68e59 | 153 | } |
2f351741 BW |
154 | tty_flip_buffer_push(tty); |
155 | ||
ccf68e59 | 156 | spin_unlock(&up->port.lock); |
157 | ||
2f351741 BW |
158 | return IRQ_HANDLED; |
159 | } | |
160 | ||
161 | static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id) | |
162 | { | |
ccf68e59 | 163 | struct sport_uart_port *up = dev_id; |
164 | ||
165 | spin_lock(&up->port.lock); | |
166 | sport_uart_tx_chars(up); | |
167 | spin_unlock(&up->port.lock); | |
2f351741 BW |
168 | |
169 | return IRQ_HANDLED; | |
170 | } | |
171 | ||
172 | static irqreturn_t sport_uart_err_irq(int irq, void *dev_id) | |
173 | { | |
174 | struct sport_uart_port *up = dev_id; | |
ebd2c8f6 | 175 | struct tty_struct *tty = up->port.state->port.tty; |
2f351741 BW |
176 | unsigned int stat = SPORT_GET_STAT(up); |
177 | ||
ccf68e59 | 178 | spin_lock(&up->port.lock); |
179 | ||
2f351741 BW |
180 | /* Overflow in RX FIFO */ |
181 | if (stat & ROVF) { | |
182 | up->port.icount.overrun++; | |
183 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
184 | SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */ | |
185 | } | |
186 | /* These should not happen */ | |
187 | if (stat & (TOVF | TUVF | RUVF)) { | |
ccf68e59 | 188 | pr_err("SPORT Error:%s %s %s\n", |
189 | (stat & TOVF) ? "TX overflow" : "", | |
190 | (stat & TUVF) ? "TX underflow" : "", | |
191 | (stat & RUVF) ? "RX underflow" : ""); | |
2f351741 BW |
192 | SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN); |
193 | SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN); | |
194 | } | |
195 | SSYNC(); | |
196 | ||
ccf68e59 | 197 | spin_unlock(&up->port.lock); |
2f351741 BW |
198 | return IRQ_HANDLED; |
199 | } | |
200 | ||
201 | /* Reqeust IRQ, Setup clock */ | |
202 | static int sport_startup(struct uart_port *port) | |
203 | { | |
204 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
ccf68e59 | 205 | int ret; |
2f351741 | 206 | |
6ef53066 | 207 | pr_debug("%s enter\n", __func__); |
ccf68e59 | 208 | ret = request_irq(up->port.irq, sport_uart_rx_irq, 0, |
209 | "SPORT_UART_RX", up); | |
210 | if (ret) { | |
211 | dev_err(port->dev, "unable to request SPORT RX interrupt\n"); | |
212 | return ret; | |
2f351741 BW |
213 | } |
214 | ||
ccf68e59 | 215 | ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0, |
216 | "SPORT_UART_TX", up); | |
217 | if (ret) { | |
218 | dev_err(port->dev, "unable to request SPORT TX interrupt\n"); | |
2f351741 BW |
219 | goto fail1; |
220 | } | |
221 | ||
ccf68e59 | 222 | ret = request_irq(up->err_irq, sport_uart_err_irq, 0, |
223 | "SPORT_UART_STATUS", up); | |
224 | if (ret) { | |
225 | dev_err(port->dev, "unable to request SPORT status interrupt\n"); | |
2f351741 BW |
226 | goto fail2; |
227 | } | |
228 | ||
2f351741 | 229 | return 0; |
ccf68e59 | 230 | fail2: |
231 | free_irq(up->port.irq+1, up); | |
232 | fail1: | |
233 | free_irq(up->port.irq, up); | |
2f351741 | 234 | |
ccf68e59 | 235 | return ret; |
2f351741 BW |
236 | } |
237 | ||
238 | static void sport_uart_tx_chars(struct sport_uart_port *up) | |
239 | { | |
ebd2c8f6 | 240 | struct circ_buf *xmit = &up->port.state->xmit; |
2f351741 BW |
241 | |
242 | if (SPORT_GET_STAT(up) & TXF) | |
243 | return; | |
244 | ||
245 | if (up->port.x_char) { | |
246 | tx_one_byte(up, up->port.x_char); | |
247 | up->port.icount.tx++; | |
248 | up->port.x_char = 0; | |
249 | return; | |
250 | } | |
251 | ||
252 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
3f3a978b SZ |
253 | /* The waiting loop to stop SPORT TX from TX interrupt is |
254 | * too long. This may block SPORT RX interrupts and cause | |
255 | * RX FIFO overflow. So, do stop sport TX only after the last | |
256 | * char in TX FIFO is moved into the shift register. | |
257 | */ | |
258 | if (SPORT_GET_STAT(up) & TXHRE) | |
259 | sport_stop_tx(&up->port); | |
2f351741 BW |
260 | return; |
261 | } | |
262 | ||
263 | while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) { | |
264 | tx_one_byte(up, xmit->buf[xmit->tail]); | |
265 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1); | |
266 | up->port.icount.tx++; | |
267 | } | |
268 | ||
269 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
270 | uart_write_wakeup(&up->port); | |
271 | } | |
272 | ||
273 | static unsigned int sport_tx_empty(struct uart_port *port) | |
274 | { | |
275 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
276 | unsigned int stat; | |
277 | ||
278 | stat = SPORT_GET_STAT(up); | |
6ef53066 | 279 | pr_debug("%s stat:%04x\n", __func__, stat); |
2f351741 BW |
280 | if (stat & TXHRE) { |
281 | return TIOCSER_TEMT; | |
282 | } else | |
283 | return 0; | |
284 | } | |
285 | ||
286 | static unsigned int sport_get_mctrl(struct uart_port *port) | |
287 | { | |
6ef53066 | 288 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
289 | return (TIOCM_CTS | TIOCM_CD | TIOCM_DSR); |
290 | } | |
291 | ||
292 | static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
293 | { | |
6ef53066 | 294 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
295 | } |
296 | ||
297 | static void sport_stop_tx(struct uart_port *port) | |
298 | { | |
299 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
2f351741 | 300 | |
6ef53066 | 301 | pr_debug("%s enter\n", __func__); |
2f351741 | 302 | |
2f351741 | 303 | /* Although the hold register is empty, last byte is still in shift |
ccf68e59 | 304 | * register and not sent out yet. So, put a dummy data into TX FIFO. |
305 | * Then, sport tx stops when last byte is shift out and the dummy | |
306 | * data is moved into the shift register. | |
307 | */ | |
308 | SPORT_PUT_TX(up, 0xffff); | |
309 | while (!(SPORT_GET_STAT(up) & TXHRE)) | |
310 | cpu_relax(); | |
2f351741 BW |
311 | |
312 | SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN)); | |
313 | SSYNC(); | |
314 | ||
315 | return; | |
316 | } | |
317 | ||
318 | static void sport_start_tx(struct uart_port *port) | |
319 | { | |
320 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
321 | ||
6ef53066 | 322 | pr_debug("%s enter\n", __func__); |
ccf68e59 | 323 | |
2f351741 BW |
324 | /* Write data into SPORT FIFO before enable SPROT to transmit */ |
325 | sport_uart_tx_chars(up); | |
326 | ||
327 | /* Enable transmit, then an interrupt will generated */ | |
328 | SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN)); | |
329 | SSYNC(); | |
6ef53066 | 330 | pr_debug("%s exit\n", __func__); |
2f351741 BW |
331 | } |
332 | ||
333 | static void sport_stop_rx(struct uart_port *port) | |
334 | { | |
335 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
336 | ||
6ef53066 | 337 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
338 | /* Disable sport to stop rx */ |
339 | SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN)); | |
340 | SSYNC(); | |
341 | } | |
342 | ||
343 | static void sport_enable_ms(struct uart_port *port) | |
344 | { | |
6ef53066 | 345 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
346 | } |
347 | ||
348 | static void sport_break_ctl(struct uart_port *port, int break_state) | |
349 | { | |
6ef53066 | 350 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
351 | } |
352 | ||
353 | static void sport_shutdown(struct uart_port *port) | |
354 | { | |
355 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
356 | ||
ccf68e59 | 357 | dev_dbg(port->dev, "%s enter\n", __func__); |
2f351741 BW |
358 | |
359 | /* Disable sport */ | |
360 | SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN)); | |
361 | SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN)); | |
362 | SSYNC(); | |
363 | ||
ccf68e59 | 364 | free_irq(up->port.irq, up); |
365 | free_irq(up->port.irq+1, up); | |
2f351741 BW |
366 | free_irq(up->err_irq, up); |
367 | } | |
368 | ||
2f351741 BW |
369 | static const char *sport_type(struct uart_port *port) |
370 | { | |
371 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
372 | ||
6ef53066 | 373 | pr_debug("%s enter\n", __func__); |
ccf68e59 | 374 | return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL; |
2f351741 BW |
375 | } |
376 | ||
377 | static void sport_release_port(struct uart_port *port) | |
378 | { | |
6ef53066 | 379 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
380 | } |
381 | ||
382 | static int sport_request_port(struct uart_port *port) | |
383 | { | |
6ef53066 | 384 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
385 | return 0; |
386 | } | |
387 | ||
388 | static void sport_config_port(struct uart_port *port, int flags) | |
389 | { | |
390 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
391 | ||
6ef53066 | 392 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
393 | up->port.type = PORT_BFIN_SPORT; |
394 | } | |
395 | ||
396 | static int sport_verify_port(struct uart_port *port, struct serial_struct *ser) | |
397 | { | |
6ef53066 | 398 | pr_debug("%s enter\n", __func__); |
2f351741 BW |
399 | return 0; |
400 | } | |
401 | ||
ccf68e59 | 402 | static void sport_set_termios(struct uart_port *port, |
403 | struct ktermios *termios, struct ktermios *old) | |
404 | { | |
405 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
406 | unsigned long flags; | |
407 | int i; | |
408 | ||
409 | pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag); | |
410 | ||
411 | switch (termios->c_cflag & CSIZE) { | |
412 | case CS8: | |
413 | up->csize = 8; | |
414 | break; | |
415 | case CS7: | |
416 | up->csize = 7; | |
417 | break; | |
418 | case CS6: | |
419 | up->csize = 6; | |
420 | break; | |
421 | case CS5: | |
422 | up->csize = 5; | |
423 | break; | |
424 | default: | |
425 | pr_warning("requested word length not supported\n"); | |
426 | } | |
427 | ||
428 | if (termios->c_cflag & CSTOPB) { | |
429 | up->stopb = 1; | |
430 | } | |
431 | if (termios->c_cflag & PARENB) { | |
432 | pr_warning("PAREN bits is not supported yet\n"); | |
433 | /* up->parib = 1; */ | |
434 | } | |
435 | ||
436 | port->read_status_mask = OE; | |
437 | if (termios->c_iflag & INPCK) | |
438 | port->read_status_mask |= (FE | PE); | |
439 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
440 | port->read_status_mask |= BI; | |
441 | ||
442 | /* | |
443 | * Characters to ignore | |
444 | */ | |
445 | port->ignore_status_mask = 0; | |
446 | if (termios->c_iflag & IGNPAR) | |
447 | port->ignore_status_mask |= FE | PE; | |
448 | if (termios->c_iflag & IGNBRK) { | |
449 | port->ignore_status_mask |= BI; | |
450 | /* | |
451 | * If we're ignoring parity and break indicators, | |
452 | * ignore overruns too (for real raw support). | |
453 | */ | |
454 | if (termios->c_iflag & IGNPAR) | |
455 | port->ignore_status_mask |= OE; | |
456 | } | |
457 | ||
458 | /* RX extract mask */ | |
459 | up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8); | |
460 | /* TX masks, 8 bit data and 1 bit stop for example: | |
461 | * mask1 = b#0111111110 | |
462 | * mask2 = b#1000000000 | |
463 | */ | |
464 | for (i = 0, up->txmask1 = 0; i < up->csize; i++) | |
465 | up->txmask1 |= (1<<i); | |
466 | up->txmask2 = (1<<i); | |
467 | if (up->stopb) { | |
468 | ++i; | |
469 | up->txmask2 |= (1<<i); | |
470 | } | |
471 | up->txmask1 <<= 1; | |
472 | up->txmask2 <<= 1; | |
473 | /* uart baud rate */ | |
474 | port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16); | |
475 | ||
476 | spin_lock_irqsave(&up->port.lock, flags); | |
477 | ||
478 | /* Disable UART */ | |
479 | SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN); | |
480 | SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN); | |
481 | ||
482 | sport_uart_setup(up, up->csize + up->stopb, port->uartclk); | |
483 | ||
484 | /* driver TX line high after config, one dummy data is | |
485 | * necessary to stop sport after shift one byte | |
486 | */ | |
487 | SPORT_PUT_TX(up, 0xffff); | |
488 | SPORT_PUT_TX(up, 0xffff); | |
489 | SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN)); | |
490 | SSYNC(); | |
491 | while (!(SPORT_GET_STAT(up) & TXHRE)) | |
492 | cpu_relax(); | |
493 | SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN); | |
494 | SSYNC(); | |
495 | ||
496 | /* Port speed changed, update the per-port timeout. */ | |
497 | uart_update_timeout(port, termios->c_cflag, port->uartclk); | |
498 | ||
499 | /* Enable sport rx */ | |
500 | SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN); | |
501 | SSYNC(); | |
502 | ||
503 | spin_unlock_irqrestore(&up->port.lock, flags); | |
504 | } | |
505 | ||
2f351741 BW |
506 | struct uart_ops sport_uart_ops = { |
507 | .tx_empty = sport_tx_empty, | |
508 | .set_mctrl = sport_set_mctrl, | |
509 | .get_mctrl = sport_get_mctrl, | |
510 | .stop_tx = sport_stop_tx, | |
511 | .start_tx = sport_start_tx, | |
512 | .stop_rx = sport_stop_rx, | |
513 | .enable_ms = sport_enable_ms, | |
514 | .break_ctl = sport_break_ctl, | |
515 | .startup = sport_startup, | |
516 | .shutdown = sport_shutdown, | |
517 | .set_termios = sport_set_termios, | |
518 | .type = sport_type, | |
519 | .release_port = sport_release_port, | |
520 | .request_port = sport_request_port, | |
521 | .config_port = sport_config_port, | |
522 | .verify_port = sport_verify_port, | |
523 | }; | |
524 | ||
ccf68e59 | 525 | #define BFIN_SPORT_UART_MAX_PORTS 4 |
526 | ||
527 | static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS]; | |
528 | ||
529 | #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE | |
530 | static int __init | |
531 | sport_uart_console_setup(struct console *co, char *options) | |
532 | { | |
533 | struct sport_uart_port *up; | |
534 | int baud = 57600; | |
535 | int bits = 8; | |
536 | int parity = 'n'; | |
537 | int flow = 'n'; | |
538 | ||
539 | /* Check whether an invalid uart number has been specified */ | |
540 | if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS) | |
541 | return -ENODEV; | |
542 | ||
543 | up = bfin_sport_uart_ports[co->index]; | |
544 | if (!up) | |
545 | return -ENODEV; | |
546 | ||
547 | if (options) | |
548 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
549 | ||
550 | return uart_set_options(&up->port, co, baud, parity, bits, flow); | |
551 | } | |
552 | ||
553 | static void sport_uart_console_putchar(struct uart_port *port, int ch) | |
554 | { | |
555 | struct sport_uart_port *up = (struct sport_uart_port *)port; | |
556 | ||
557 | while (SPORT_GET_STAT(up) & TXF) | |
558 | barrier(); | |
559 | ||
560 | tx_one_byte(up, ch); | |
561 | } | |
562 | ||
563 | /* | |
564 | * Interrupts are disabled on entering | |
565 | */ | |
566 | static void | |
567 | sport_uart_console_write(struct console *co, const char *s, unsigned int count) | |
568 | { | |
569 | struct sport_uart_port *up = bfin_sport_uart_ports[co->index]; | |
570 | unsigned long flags; | |
571 | ||
572 | spin_lock_irqsave(&up->port.lock, flags); | |
573 | ||
574 | if (SPORT_GET_TCR1(up) & TSPEN) | |
575 | uart_console_write(&up->port, s, count, sport_uart_console_putchar); | |
576 | else { | |
577 | /* dummy data to start sport */ | |
578 | while (SPORT_GET_STAT(up) & TXF) | |
579 | barrier(); | |
580 | SPORT_PUT_TX(up, 0xffff); | |
581 | /* Enable transmit, then an interrupt will generated */ | |
582 | SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN)); | |
583 | SSYNC(); | |
584 | ||
585 | uart_console_write(&up->port, s, count, sport_uart_console_putchar); | |
586 | ||
587 | /* Although the hold register is empty, last byte is still in shift | |
588 | * register and not sent out yet. So, put a dummy data into TX FIFO. | |
589 | * Then, sport tx stops when last byte is shift out and the dummy | |
590 | * data is moved into the shift register. | |
591 | */ | |
592 | while (SPORT_GET_STAT(up) & TXF) | |
593 | barrier(); | |
594 | SPORT_PUT_TX(up, 0xffff); | |
595 | while (!(SPORT_GET_STAT(up) & TXHRE)) | |
596 | barrier(); | |
597 | ||
598 | /* Stop sport tx transfer */ | |
599 | SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN)); | |
600 | SSYNC(); | |
2f351741 | 601 | } |
ccf68e59 | 602 | |
603 | spin_unlock_irqrestore(&up->port.lock, flags); | |
604 | } | |
605 | ||
606 | static struct uart_driver sport_uart_reg; | |
607 | ||
608 | static struct console sport_uart_console = { | |
609 | .name = DEVICE_NAME, | |
610 | .write = sport_uart_console_write, | |
611 | .device = uart_console_device, | |
612 | .setup = sport_uart_console_setup, | |
613 | .flags = CON_PRINTBUFFER, | |
614 | .index = -1, | |
615 | .data = &sport_uart_reg, | |
2f351741 BW |
616 | }; |
617 | ||
ccf68e59 | 618 | #define SPORT_UART_CONSOLE (&sport_uart_console) |
619 | #else | |
620 | #define SPORT_UART_CONSOLE NULL | |
621 | #endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */ | |
622 | ||
623 | ||
2f351741 BW |
624 | static struct uart_driver sport_uart_reg = { |
625 | .owner = THIS_MODULE, | |
ccf68e59 | 626 | .driver_name = DRV_NAME, |
627 | .dev_name = DEVICE_NAME, | |
2f351741 BW |
628 | .major = 204, |
629 | .minor = 84, | |
ccf68e59 | 630 | .nr = BFIN_SPORT_UART_MAX_PORTS, |
631 | .cons = SPORT_UART_CONSOLE, | |
2f351741 BW |
632 | }; |
633 | ||
ccf68e59 | 634 | #ifdef CONFIG_PM |
635 | static int sport_uart_suspend(struct device *dev) | |
2f351741 | 636 | { |
ccf68e59 | 637 | struct sport_uart_port *sport = dev_get_drvdata(dev); |
2f351741 | 638 | |
ccf68e59 | 639 | dev_dbg(dev, "%s enter\n", __func__); |
2f351741 BW |
640 | if (sport) |
641 | uart_suspend_port(&sport_uart_reg, &sport->port); | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
ccf68e59 | 646 | static int sport_uart_resume(struct device *dev) |
2f351741 | 647 | { |
ccf68e59 | 648 | struct sport_uart_port *sport = dev_get_drvdata(dev); |
2f351741 | 649 | |
ccf68e59 | 650 | dev_dbg(dev, "%s enter\n", __func__); |
2f351741 BW |
651 | if (sport) |
652 | uart_resume_port(&sport_uart_reg, &sport->port); | |
653 | ||
654 | return 0; | |
655 | } | |
656 | ||
ccf68e59 | 657 | static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = { |
658 | .suspend = sport_uart_suspend, | |
659 | .resume = sport_uart_resume, | |
660 | }; | |
661 | #endif | |
662 | ||
663 | static int __devinit sport_uart_probe(struct platform_device *pdev) | |
2f351741 | 664 | { |
ccf68e59 | 665 | struct resource *res; |
666 | struct sport_uart_port *sport; | |
667 | int ret = 0; | |
2f351741 | 668 | |
ccf68e59 | 669 | dev_dbg(&pdev->dev, "%s enter\n", __func__); |
670 | ||
671 | if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) { | |
672 | dev_err(&pdev->dev, "Wrong sport uart platform device id.\n"); | |
673 | return -ENOENT; | |
674 | } | |
675 | ||
676 | if (bfin_sport_uart_ports[pdev->id] == NULL) { | |
677 | bfin_sport_uart_ports[pdev->id] = | |
678 | kmalloc(sizeof(struct sport_uart_port), GFP_KERNEL); | |
679 | sport = bfin_sport_uart_ports[pdev->id]; | |
680 | if (!sport) { | |
681 | dev_err(&pdev->dev, | |
682 | "Fail to kmalloc sport_uart_port\n"); | |
683 | return -ENOMEM; | |
684 | } | |
685 | ||
686 | ret = peripheral_request_list( | |
687 | (unsigned short *)pdev->dev.platform_data, DRV_NAME); | |
688 | if (ret) { | |
689 | dev_err(&pdev->dev, | |
690 | "Fail to request SPORT peripherals\n"); | |
691 | goto out_error_free_mem; | |
692 | } | |
693 | ||
694 | spin_lock_init(&sport->port.lock); | |
695 | sport->port.fifosize = SPORT_TX_FIFO_SIZE, | |
696 | sport->port.ops = &sport_uart_ops; | |
697 | sport->port.line = pdev->id; | |
698 | sport->port.iotype = UPIO_MEM; | |
699 | sport->port.flags = UPF_BOOT_AUTOCONF; | |
700 | ||
701 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
702 | if (res == NULL) { | |
703 | dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); | |
704 | ret = -ENOENT; | |
705 | goto out_error_free_peripherals; | |
706 | } | |
707 | ||
708 | sport->port.membase = ioremap(res->start, | |
709 | res->end - res->start); | |
710 | if (!sport->port.membase) { | |
711 | dev_err(&pdev->dev, "Cannot map sport IO\n"); | |
712 | ret = -ENXIO; | |
713 | goto out_error_free_peripherals; | |
714 | } | |
715 | ||
716 | sport->port.irq = platform_get_irq(pdev, 0); | |
717 | if (sport->port.irq < 0) { | |
718 | dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n"); | |
719 | ret = -ENOENT; | |
720 | goto out_error_unmap; | |
721 | } | |
722 | ||
723 | sport->err_irq = platform_get_irq(pdev, 1); | |
724 | if (sport->err_irq < 0) { | |
725 | dev_err(&pdev->dev, "No sport status IRQ specified\n"); | |
726 | ret = -ENOENT; | |
727 | goto out_error_unmap; | |
728 | } | |
729 | } | |
730 | ||
731 | #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE | |
732 | if (!is_early_platform_device(pdev)) { | |
733 | #endif | |
734 | sport = bfin_sport_uart_ports[pdev->id]; | |
735 | sport->port.dev = &pdev->dev; | |
736 | dev_set_drvdata(&pdev->dev, sport); | |
737 | ret = uart_add_one_port(&sport_uart_reg, &sport->port); | |
738 | #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE | |
739 | } | |
740 | #endif | |
741 | if (!ret) | |
742 | return 0; | |
743 | ||
744 | if (sport) { | |
745 | out_error_unmap: | |
746 | iounmap(sport->port.membase); | |
747 | out_error_free_peripherals: | |
748 | peripheral_free_list( | |
749 | (unsigned short *)pdev->dev.platform_data); | |
750 | out_error_free_mem: | |
751 | kfree(sport); | |
752 | bfin_sport_uart_ports[pdev->id] = NULL; | |
753 | } | |
754 | ||
755 | return ret; | |
2f351741 BW |
756 | } |
757 | ||
ccf68e59 | 758 | static int __devexit sport_uart_remove(struct platform_device *pdev) |
2f351741 | 759 | { |
ccf68e59 | 760 | struct sport_uart_port *sport = platform_get_drvdata(pdev); |
2f351741 | 761 | |
ccf68e59 | 762 | dev_dbg(&pdev->dev, "%s enter\n", __func__); |
763 | dev_set_drvdata(&pdev->dev, NULL); | |
2f351741 | 764 | |
ccf68e59 | 765 | if (sport) { |
2f351741 | 766 | uart_remove_one_port(&sport_uart_reg, &sport->port); |
ccf68e59 | 767 | iounmap(sport->port.membase); |
768 | peripheral_free_list( | |
769 | (unsigned short *)pdev->dev.platform_data); | |
770 | kfree(sport); | |
771 | bfin_sport_uart_ports[pdev->id] = NULL; | |
772 | } | |
2f351741 BW |
773 | |
774 | return 0; | |
775 | } | |
776 | ||
777 | static struct platform_driver sport_uart_driver = { | |
778 | .probe = sport_uart_probe, | |
ccf68e59 | 779 | .remove = __devexit_p(sport_uart_remove), |
2f351741 BW |
780 | .driver = { |
781 | .name = DRV_NAME, | |
ccf68e59 | 782 | #ifdef CONFIG_PM |
783 | .pm = &bfin_sport_uart_dev_pm_ops, | |
784 | #endif | |
2f351741 BW |
785 | }, |
786 | }; | |
787 | ||
ccf68e59 | 788 | #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE |
789 | static __initdata struct early_platform_driver early_sport_uart_driver = { | |
790 | .class_str = DRV_NAME, | |
791 | .pdrv = &sport_uart_driver, | |
792 | .requested_id = EARLY_PLATFORM_ID_UNSET, | |
793 | }; | |
794 | ||
795 | static int __init sport_uart_rs_console_init(void) | |
796 | { | |
797 | early_platform_driver_register(&early_sport_uart_driver, DRV_NAME); | |
798 | ||
799 | early_platform_driver_probe(DRV_NAME, BFIN_SPORT_UART_MAX_PORTS, 0); | |
800 | ||
801 | register_console(&sport_uart_console); | |
802 | ||
803 | return 0; | |
804 | } | |
805 | console_initcall(sport_uart_rs_console_init); | |
806 | #endif | |
807 | ||
2f351741 BW |
808 | static int __init sport_uart_init(void) |
809 | { | |
810 | int ret; | |
811 | ||
ccf68e59 | 812 | pr_info("Serial: Blackfin uart over sport driver\n"); |
813 | ||
2f351741 | 814 | ret = uart_register_driver(&sport_uart_reg); |
ccf68e59 | 815 | if (ret) { |
816 | pr_err("failed to register %s:%d\n", | |
2f351741 BW |
817 | sport_uart_reg.driver_name, ret); |
818 | return ret; | |
819 | } | |
820 | ||
821 | ret = platform_driver_register(&sport_uart_driver); | |
ccf68e59 | 822 | if (ret) { |
823 | pr_err("failed to register sport uart driver:%d\n", ret); | |
2f351741 BW |
824 | uart_unregister_driver(&sport_uart_reg); |
825 | } | |
826 | ||
2f351741 BW |
827 | return ret; |
828 | } | |
ccf68e59 | 829 | module_init(sport_uart_init); |
2f351741 BW |
830 | |
831 | static void __exit sport_uart_exit(void) | |
832 | { | |
2f351741 BW |
833 | platform_driver_unregister(&sport_uart_driver); |
834 | uart_unregister_driver(&sport_uart_reg); | |
835 | } | |
2f351741 BW |
836 | module_exit(sport_uart_exit); |
837 | ||
ccf68e59 | 838 | MODULE_AUTHOR("Sonic Zhang, Roy Huang"); |
839 | MODULE_DESCRIPTION("Blackfin serial over SPORT driver"); | |
2f351741 | 840 | MODULE_LICENSE("GPL"); |