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[Blackfin] serial driver: fix bug - cache the bits of the LSR on systems where the...
[net-next-2.6.git] / drivers / serial / bfin_5xx.c
CommitLineData
194de561
BW
1/*
2 * File: drivers/serial/bfin_5xx.c
3 * Based on: Based on drivers/serial/sa1100.c
4 * Author: Aubrey Li <aubrey.li@analog.com>
5 *
6 * Created:
7 * Description: Driver for blackfin 5xx serial ports
8 *
194de561
BW
9 * Modified:
10 * Copyright 2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31#define SUPPORT_SYSRQ
32#endif
33
34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/init.h>
37#include <linux/console.h>
38#include <linux/sysrq.h>
39#include <linux/platform_device.h>
40#include <linux/tty.h>
41#include <linux/tty_flip.h>
42#include <linux/serial_core.h>
43
474f1a66
SZ
44#ifdef CONFIG_KGDB_UART
45#include <linux/kgdb.h>
46#include <asm/irq_regs.h>
47#endif
48
194de561
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49#include <asm/gpio.h>
50#include <asm/mach/bfin_serial_5xx.h>
51
52#ifdef CONFIG_SERIAL_BFIN_DMA
53#include <linux/dma-mapping.h>
54#include <asm/io.h>
55#include <asm/irq.h>
56#include <asm/cacheflush.h>
57#endif
58
59/* UART name and device definitions */
60#define BFIN_SERIAL_NAME "ttyBF"
61#define BFIN_SERIAL_MAJOR 204
62#define BFIN_SERIAL_MINOR 64
63
64/*
65 * Setup for console. Argument comes from the menuconfig
66 */
67#define DMA_RX_XCOUNT 512
68#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
69
70#define DMA_RX_FLUSH_JIFFIES 5
71
72#ifdef CONFIG_SERIAL_BFIN_DMA
73static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
74#else
75static void bfin_serial_do_work(struct work_struct *work);
76static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
194de561
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77#endif
78
79static void bfin_serial_mctrl_check(struct bfin_serial_port *uart);
80
81/*
82 * interrupts are disabled on entry
83 */
84static void bfin_serial_stop_tx(struct uart_port *port)
85{
86 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1b73351c 87#if !defined(CONFIG_BF54x) && !defined(CONFIG_SERIAL_BFIN_DMA)
759eb040
SZ
88 unsigned short ier;
89#endif
194de561 90
f4d640c9
RH
91 while (!(UART_GET_LSR(uart) & TEMT))
92 continue;
f4d640c9 93
194de561
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94#ifdef CONFIG_SERIAL_BFIN_DMA
95 disable_dma(uart->tx_dma_channel);
f4d640c9
RH
96#else
97#ifdef CONFIG_BF54x
f4d640c9
RH
98 /* Clear TFI bit */
99 UART_PUT_LSR(uart, TFI);
100 UART_CLEAR_IER(uart, ETBEI);
194de561 101#else
194de561
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102 ier = UART_GET_IER(uart);
103 ier &= ~ETBEI;
104 UART_PUT_IER(uart, ier);
105#endif
f4d640c9 106#endif
194de561
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107}
108
109/*
110 * port is locked and interrupts are disabled
111 */
112static void bfin_serial_start_tx(struct uart_port *port)
113{
114 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
115
116#ifdef CONFIG_SERIAL_BFIN_DMA
117 bfin_serial_dma_tx_chars(uart);
f4d640c9
RH
118#else
119#ifdef CONFIG_BF54x
120 UART_SET_IER(uart, ETBEI);
194de561
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121#else
122 unsigned short ier;
123 ier = UART_GET_IER(uart);
124 ier |= ETBEI;
125 UART_PUT_IER(uart, ier);
194de561 126#endif
a359cca7 127 bfin_serial_tx_chars(uart);
f4d640c9 128#endif
194de561
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129}
130
131/*
132 * Interrupts are enabled
133 */
134static void bfin_serial_stop_rx(struct uart_port *port)
135{
136 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
a359cca7
SZ
137#ifdef CONFIG_KGDB_UART
138 if (uart->port.line != CONFIG_KGDB_UART_PORT) {
139#endif
f4d640c9
RH
140#ifdef CONFIG_BF54x
141 UART_CLEAR_IER(uart, ERBFI);
142#else
194de561
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143 unsigned short ier;
144
145 ier = UART_GET_IER(uart);
146 ier &= ~ERBFI;
147 UART_PUT_IER(uart, ier);
f4d640c9 148#endif
a359cca7
SZ
149#ifdef CONFIG_KGDB_UART
150 }
151#endif
194de561
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152}
153
154/*
155 * Set the modem control timer to fire immediately.
156 */
157static void bfin_serial_enable_ms(struct uart_port *port)
158{
159}
160
474f1a66
SZ
161#ifdef CONFIG_KGDB_UART
162static int kgdb_entry_state;
163
164void kgdb_put_debug_char(int chr)
165{
166 struct bfin_serial_port *uart;
167
168 if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS)
169 uart = &bfin_serial_ports[0];
170 else
171 uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
172
173 while (!(UART_GET_LSR(uart) & THRE)) {
d5148ffa 174 SSYNC();
474f1a66 175 }
a359cca7
SZ
176
177#ifndef CONFIG_BF54x
474f1a66 178 UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
d5148ffa 179 SSYNC();
a359cca7 180#endif
474f1a66 181 UART_PUT_CHAR(uart, (unsigned char)chr);
d5148ffa 182 SSYNC();
474f1a66
SZ
183}
184
185int kgdb_get_debug_char(void)
186{
187 struct bfin_serial_port *uart;
188 unsigned char chr;
189
190 if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS)
191 uart = &bfin_serial_ports[0];
192 else
193 uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
194
195 while(!(UART_GET_LSR(uart) & DR)) {
d5148ffa 196 SSYNC();
474f1a66 197 }
a359cca7 198#ifndef CONFIG_BF54x
474f1a66 199 UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
d5148ffa 200 SSYNC();
a359cca7 201#endif
474f1a66 202 chr = UART_GET_CHAR(uart);
d5148ffa 203 SSYNC();
474f1a66
SZ
204
205 return chr;
206}
207#endif
208
194de561 209#ifdef CONFIG_SERIAL_BFIN_PIO
194de561
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210static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
211{
2ac5ee47 212 struct tty_struct *tty = uart->port.info->tty;
194de561 213 unsigned int status, ch, flg;
bbf275f0 214 static int in_break = 0;
474f1a66
SZ
215#ifdef CONFIG_KGDB_UART
216 struct pt_regs *regs = get_irq_regs();
217#endif
194de561 218
759eb040 219 status = UART_GET_LSR(uart);
0bcfd70e
MF
220 UART_CLEAR_LSR(uart);
221
222 ch = UART_GET_CHAR(uart);
194de561
BW
223 uart->port.icount.rx++;
224
474f1a66
SZ
225#ifdef CONFIG_KGDB_UART
226 if (uart->port.line == CONFIG_KGDB_UART_PORT) {
227 if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */
228 kgdb_breakkey_pressed(regs);
229 return;
230 } else if (kgdb_entry_state == 0 && ch == '$') {/* connection from KGDB */
231 kgdb_entry_state = 1;
232 } else if (kgdb_entry_state == 1 && ch == 'q') {
233 kgdb_entry_state = 0;
234 kgdb_breakkey_pressed(regs);
235 return;
236 } else if (ch == 0x3) {/* Ctrl + C */
237 kgdb_entry_state = 0;
238 kgdb_breakkey_pressed(regs);
239 return;
240 } else {
241 kgdb_entry_state = 0;
242 }
243 }
244#endif
bbf275f0
MF
245
246 if (ANOMALY_05000230) {
247 /* The BF533 family of processors have a nice misbehavior where
248 * they continuously generate characters for a "single" break.
249 * We have to basically ignore this flood until the "next" valid
250 * character comes across. All other Blackfin families operate
251 * properly though.
252 * Note: While Anomaly 05000230 does not directly address this,
253 * the changes that went in for it also fixed this issue.
254 */
255 if (in_break) {
256 if (ch != 0) {
257 in_break = 0;
258 ch = UART_GET_CHAR(uart);
259 if (bfin_revid() < 5)
260 return;
261 } else
2ac5ee47 262 return;
bbf275f0 263 }
194de561 264 }
194de561
BW
265
266 if (status & BI) {
bbf275f0
MF
267 if (ANOMALY_05000230)
268 in_break = 1;
194de561
BW
269 uart->port.icount.brk++;
270 if (uart_handle_break(&uart->port))
271 goto ignore_char;
9808901b 272 status &= ~(PE | FE);
2ac5ee47
MF
273 }
274 if (status & PE)
194de561 275 uart->port.icount.parity++;
2ac5ee47 276 if (status & OE)
194de561 277 uart->port.icount.overrun++;
2ac5ee47 278 if (status & FE)
194de561 279 uart->port.icount.frame++;
2ac5ee47
MF
280
281 status &= uart->port.read_status_mask;
282
283 if (status & BI)
284 flg = TTY_BREAK;
285 else if (status & PE)
286 flg = TTY_PARITY;
287 else if (status & FE)
288 flg = TTY_FRAME;
289 else
194de561
BW
290 flg = TTY_NORMAL;
291
292 if (uart_handle_sysrq_char(&uart->port, ch))
293 goto ignore_char;
194de561 294
2ac5ee47
MF
295 uart_insert_char(&uart->port, status, OE, ch, flg);
296
297 ignore_char:
298 tty_flip_buffer_push(tty);
194de561
BW
299}
300
301static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
302{
303 struct circ_buf *xmit = &uart->port.info->xmit;
304
305 if (uart->port.x_char) {
306 UART_PUT_CHAR(uart, uart->port.x_char);
307 uart->port.icount.tx++;
308 uart->port.x_char = 0;
194de561
BW
309 }
310 /*
311 * Check the modem control lines before
312 * transmitting anything.
313 */
314 bfin_serial_mctrl_check(uart);
315
316 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
317 bfin_serial_stop_tx(&uart->port);
318 return;
319 }
320
759eb040
SZ
321 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
322 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
323 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
324 uart->port.icount.tx++;
325 SSYNC();
326 }
194de561
BW
327
328 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
329 uart_write_wakeup(&uart->port);
330
331 if (uart_circ_empty(xmit))
332 bfin_serial_stop_tx(&uart->port);
333}
334
5c4e472b
AL
335static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
336{
337 struct bfin_serial_port *uart = dev_id;
338
f4d640c9 339 spin_lock(&uart->port.lock);
0bcfd70e 340 while (UART_GET_LSR(uart) & DR)
f4d640c9 341 bfin_serial_rx_chars(uart);
f4d640c9 342 spin_unlock(&uart->port.lock);
759eb040 343
5c4e472b
AL
344 return IRQ_HANDLED;
345}
346
347static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
194de561
BW
348{
349 struct bfin_serial_port *uart = dev_id;
194de561 350
f4d640c9 351 spin_lock(&uart->port.lock);
0bcfd70e 352 if (UART_GET_LSR(uart) & THRE)
f4d640c9 353 bfin_serial_tx_chars(uart);
f4d640c9 354 spin_unlock(&uart->port.lock);
759eb040 355
194de561
BW
356 return IRQ_HANDLED;
357}
358
5c4e472b 359
194de561
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360static void bfin_serial_do_work(struct work_struct *work)
361{
362 struct bfin_serial_port *uart = container_of(work, struct bfin_serial_port, cts_workqueue);
363
364 bfin_serial_mctrl_check(uart);
365}
194de561
BW
366#endif
367
368#ifdef CONFIG_SERIAL_BFIN_DMA
369static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
370{
371 struct circ_buf *xmit = &uart->port.info->xmit;
372 unsigned short ier;
373 int flags = 0;
374
375 if (!uart->tx_done)
376 return;
194de561
BW
377 uart->tx_done = 0;
378
1b73351c
SZ
379 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
380 bfin_serial_stop_tx(&uart->port);
381 uart->tx_done = 1;
382 return;
383 }
384
194de561
BW
385 if (uart->port.x_char) {
386 UART_PUT_CHAR(uart, uart->port.x_char);
387 uart->port.icount.tx++;
388 uart->port.x_char = 0;
194de561 389 }
1b73351c 390
194de561
BW
391 /*
392 * Check the modem control lines before
393 * transmitting anything.
394 */
395 bfin_serial_mctrl_check(uart);
396
194de561
BW
397 spin_lock_irqsave(&uart->port.lock, flags);
398 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
399 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
400 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
401 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
402 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
403 set_dma_config(uart->tx_dma_channel,
404 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
405 INTR_ON_BUF,
406 DIMENSION_LINEAR,
2047e40d
MH
407 DATA_SIZE_8,
408 DMA_SYNC_RESTART));
194de561
BW
409 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
410 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
411 set_dma_x_modify(uart->tx_dma_channel, 1);
412 enable_dma(uart->tx_dma_channel);
99ee7b5f
SZ
413
414 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
415 uart->port.icount.tx += uart->tx_count;
416
f4d640c9
RH
417#ifdef CONFIG_BF54x
418 UART_SET_IER(uart, ETBEI);
419#else
194de561
BW
420 ier = UART_GET_IER(uart);
421 ier |= ETBEI;
422 UART_PUT_IER(uart, ier);
f4d640c9 423#endif
194de561
BW
424 spin_unlock_irqrestore(&uart->port.lock, flags);
425}
426
2ac5ee47 427static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
194de561
BW
428{
429 struct tty_struct *tty = uart->port.info->tty;
430 int i, flg, status;
431
432 status = UART_GET_LSR(uart);
0bcfd70e
MF
433 UART_CLEAR_LSR(uart);
434
194de561
BW
435 uart->port.icount.rx += CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail, UART_XMIT_SIZE);;
436
437 if (status & BI) {
438 uart->port.icount.brk++;
439 if (uart_handle_break(&uart->port))
440 goto dma_ignore_char;
9808901b 441 status &= ~(PE | FE);
2ac5ee47
MF
442 }
443 if (status & PE)
194de561 444 uart->port.icount.parity++;
2ac5ee47 445 if (status & OE)
194de561 446 uart->port.icount.overrun++;
2ac5ee47 447 if (status & FE)
194de561 448 uart->port.icount.frame++;
2ac5ee47
MF
449
450 status &= uart->port.read_status_mask;
451
452 if (status & BI)
453 flg = TTY_BREAK;
454 else if (status & PE)
455 flg = TTY_PARITY;
456 else if (status & FE)
457 flg = TTY_FRAME;
458 else
194de561
BW
459 flg = TTY_NORMAL;
460
461 for (i = uart->rx_dma_buf.head; i < uart->rx_dma_buf.tail; i++) {
462 if (uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
463 goto dma_ignore_char;
2ac5ee47 464 uart_insert_char(&uart->port, status, OE, uart->rx_dma_buf.buf[i], flg);
194de561 465 }
2ac5ee47
MF
466
467 dma_ignore_char:
194de561
BW
468 tty_flip_buffer_push(tty);
469}
470
471void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
472{
473 int x_pos, pos;
474 int flags = 0;
475
194de561
BW
476 spin_lock_irqsave(&uart->port.lock, flags);
477 x_pos = DMA_RX_XCOUNT - get_dma_curr_xcount(uart->rx_dma_channel);
478 if (x_pos == DMA_RX_XCOUNT)
479 x_pos = 0;
480
481 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
482
483 if (pos>uart->rx_dma_buf.tail) {
484 uart->rx_dma_buf.tail = pos;
485 bfin_serial_dma_rx_chars(uart);
486 uart->rx_dma_buf.head = uart->rx_dma_buf.tail;
487 }
488 spin_unlock_irqrestore(&uart->port.lock, flags);
489 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
490 add_timer(&(uart->rx_dma_timer));
491}
492
493static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
494{
495 struct bfin_serial_port *uart = dev_id;
496 struct circ_buf *xmit = &uart->port.info->xmit;
497 unsigned short ier;
498
499 spin_lock(&uart->port.lock);
500 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
501 clear_dma_irqstat(uart->tx_dma_channel);
502 disable_dma(uart->tx_dma_channel);
f4d640c9
RH
503#ifdef CONFIG_BF54x
504 UART_CLEAR_IER(uart, ETBEI);
505#else
194de561
BW
506 ier = UART_GET_IER(uart);
507 ier &= ~ETBEI;
508 UART_PUT_IER(uart, ier);
f4d640c9 509#endif
194de561
BW
510 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
511 uart_write_wakeup(&uart->port);
512
194de561 513 uart->tx_done = 1;
1b73351c
SZ
514
515 bfin_serial_dma_tx_chars(uart);
194de561
BW
516 }
517
518 spin_unlock(&uart->port.lock);
519 return IRQ_HANDLED;
520}
521
522static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
523{
524 struct bfin_serial_port *uart = dev_id;
525 unsigned short irqstat;
526
527 uart->rx_dma_nrows++;
528 if (uart->rx_dma_nrows == DMA_RX_YCOUNT) {
529 uart->rx_dma_nrows = 0;
530 uart->rx_dma_buf.tail = DMA_RX_XCOUNT*DMA_RX_YCOUNT;
531 bfin_serial_dma_rx_chars(uart);
532 uart->rx_dma_buf.head = uart->rx_dma_buf.tail = 0;
533 }
534 spin_lock(&uart->port.lock);
535 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
536 clear_dma_irqstat(uart->rx_dma_channel);
537
538 spin_unlock(&uart->port.lock);
539 return IRQ_HANDLED;
540}
541#endif
542
543/*
544 * Return TIOCSER_TEMT when transmitter is not busy.
545 */
546static unsigned int bfin_serial_tx_empty(struct uart_port *port)
547{
548 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
549 unsigned short lsr;
550
551 lsr = UART_GET_LSR(uart);
552 if (lsr & TEMT)
553 return TIOCSER_TEMT;
554 else
555 return 0;
556}
557
558static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
559{
560#ifdef CONFIG_SERIAL_BFIN_CTSRTS
561 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
562 if (uart->cts_pin < 0)
563 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
564
565 if (gpio_get_value(uart->cts_pin))
566 return TIOCM_DSR | TIOCM_CAR;
567 else
568#endif
569 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
570}
571
572static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
573{
574#ifdef CONFIG_SERIAL_BFIN_CTSRTS
575 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
576 if (uart->rts_pin < 0)
577 return;
578
579 if (mctrl & TIOCM_RTS)
580 gpio_set_value(uart->rts_pin, 0);
581 else
582 gpio_set_value(uart->rts_pin, 1);
583#endif
584}
585
586/*
587 * Handle any change of modem status signal since we were last called.
588 */
589static void bfin_serial_mctrl_check(struct bfin_serial_port *uart)
590{
591#ifdef CONFIG_SERIAL_BFIN_CTSRTS
592 unsigned int status;
593# ifdef CONFIG_SERIAL_BFIN_DMA
594 struct uart_info *info = uart->port.info;
595 struct tty_struct *tty = info->tty;
596
597 status = bfin_serial_get_mctrl(&uart->port);
598 if (!(status & TIOCM_CTS)) {
599 tty->hw_stopped = 1;
600 } else {
601 tty->hw_stopped = 0;
602 }
603# else
604 status = bfin_serial_get_mctrl(&uart->port);
605 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
606 if (!(status & TIOCM_CTS))
607 schedule_work(&uart->cts_workqueue);
608# endif
609#endif
610}
611
612/*
613 * Interrupts are always disabled.
614 */
615static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
616{
cf686762
MF
617 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
618 u16 lcr = UART_GET_LCR(uart);
619 if (break_state)
620 lcr |= SB;
621 else
622 lcr &= ~SB;
623 UART_PUT_LCR(uart, lcr);
624 SSYNC();
194de561
BW
625}
626
627static int bfin_serial_startup(struct uart_port *port)
628{
629 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
630
631#ifdef CONFIG_SERIAL_BFIN_DMA
632 dma_addr_t dma_handle;
633
634 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
635 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
636 return -EBUSY;
637 }
638
639 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
640 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
641 free_dma(uart->rx_dma_channel);
642 return -EBUSY;
643 }
644
645 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
646 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
647
648 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
649 uart->rx_dma_buf.head = 0;
650 uart->rx_dma_buf.tail = 0;
651 uart->rx_dma_nrows = 0;
652
653 set_dma_config(uart->rx_dma_channel,
654 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
655 INTR_ON_ROW, DIMENSION_2D,
2047e40d
MH
656 DATA_SIZE_8,
657 DMA_SYNC_RESTART));
194de561
BW
658 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
659 set_dma_x_modify(uart->rx_dma_channel, 1);
660 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
661 set_dma_y_modify(uart->rx_dma_channel, 1);
662 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
663 enable_dma(uart->rx_dma_channel);
664
665 uart->rx_dma_timer.data = (unsigned long)(uart);
666 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
667 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
668 add_timer(&(uart->rx_dma_timer));
669#else
a359cca7
SZ
670 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
671 "BFIN_UART_RX", uart)) {
474f1a66 672# ifdef CONFIG_KGDB_UART
a359cca7 673 if (uart->port.line != CONFIG_KGDB_UART_PORT) {
474f1a66 674# endif
194de561
BW
675 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
676 return -EBUSY;
a359cca7
SZ
677# ifdef CONFIG_KGDB_UART
678 }
679# endif
194de561
BW
680 }
681
a359cca7 682
194de561 683 if (request_irq
5c4e472b 684 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
194de561
BW
685 "BFIN_UART_TX", uart)) {
686 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
687 free_irq(uart->port.irq, uart);
688 return -EBUSY;
689 }
690#endif
f4d640c9
RH
691#ifdef CONFIG_BF54x
692 UART_SET_IER(uart, ERBFI);
693#else
194de561 694 UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
f4d640c9 695#endif
194de561
BW
696 return 0;
697}
698
699static void bfin_serial_shutdown(struct uart_port *port)
700{
701 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
702
703#ifdef CONFIG_SERIAL_BFIN_DMA
704 disable_dma(uart->tx_dma_channel);
705 free_dma(uart->tx_dma_channel);
706 disable_dma(uart->rx_dma_channel);
707 free_dma(uart->rx_dma_channel);
708 del_timer(&(uart->rx_dma_timer));
75b780bd 709 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
194de561 710#else
474f1a66
SZ
711#ifdef CONFIG_KGDB_UART
712 if (uart->port.line != CONFIG_KGDB_UART_PORT)
713#endif
194de561
BW
714 free_irq(uart->port.irq, uart);
715 free_irq(uart->port.irq+1, uart);
716#endif
717}
718
719static void
720bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
721 struct ktermios *old)
722{
723 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
724 unsigned long flags;
725 unsigned int baud, quot;
726 unsigned short val, ier, lsr, lcr = 0;
727
728 switch (termios->c_cflag & CSIZE) {
729 case CS8:
730 lcr = WLS(8);
731 break;
732 case CS7:
733 lcr = WLS(7);
734 break;
735 case CS6:
736 lcr = WLS(6);
737 break;
738 case CS5:
739 lcr = WLS(5);
740 break;
741 default:
742 printk(KERN_ERR "%s: word lengh not supported\n",
743 __FUNCTION__);
744 }
745
746 if (termios->c_cflag & CSTOPB)
747 lcr |= STB;
19aa6382 748 if (termios->c_cflag & PARENB)
194de561 749 lcr |= PEN;
19aa6382
MF
750 if (!(termios->c_cflag & PARODD))
751 lcr |= EPS;
752 if (termios->c_cflag & CMSPAR)
753 lcr |= STP;
194de561 754
2ac5ee47
MF
755 port->read_status_mask = OE;
756 if (termios->c_iflag & INPCK)
757 port->read_status_mask |= (FE | PE);
758 if (termios->c_iflag & (BRKINT | PARMRK))
759 port->read_status_mask |= BI;
194de561 760
2ac5ee47
MF
761 /*
762 * Characters to ignore
763 */
764 port->ignore_status_mask = 0;
765 if (termios->c_iflag & IGNPAR)
766 port->ignore_status_mask |= FE | PE;
767 if (termios->c_iflag & IGNBRK) {
768 port->ignore_status_mask |= BI;
769 /*
770 * If we're ignoring parity and break indicators,
771 * ignore overruns too (for real raw support).
772 */
773 if (termios->c_iflag & IGNPAR)
774 port->ignore_status_mask |= OE;
775 }
194de561
BW
776
777 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
778 quot = uart_get_divisor(port, baud);
779 spin_lock_irqsave(&uart->port.lock, flags);
780
781 do {
782 lsr = UART_GET_LSR(uart);
783 } while (!(lsr & TEMT));
784
785 /* Disable UART */
786 ier = UART_GET_IER(uart);
f4d640c9
RH
787#ifdef CONFIG_BF54x
788 UART_CLEAR_IER(uart, 0xF);
789#else
194de561 790 UART_PUT_IER(uart, 0);
f4d640c9 791#endif
194de561 792
f4d640c9 793#ifndef CONFIG_BF54x
194de561
BW
794 /* Set DLAB in LCR to Access DLL and DLH */
795 val = UART_GET_LCR(uart);
796 val |= DLAB;
797 UART_PUT_LCR(uart, val);
798 SSYNC();
f4d640c9 799#endif
194de561
BW
800
801 UART_PUT_DLL(uart, quot & 0xFF);
802 SSYNC();
803 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
804 SSYNC();
805
f4d640c9 806#ifndef CONFIG_BF54x
194de561
BW
807 /* Clear DLAB in LCR to Access THR RBR IER */
808 val = UART_GET_LCR(uart);
809 val &= ~DLAB;
810 UART_PUT_LCR(uart, val);
811 SSYNC();
f4d640c9 812#endif
194de561
BW
813
814 UART_PUT_LCR(uart, lcr);
815
816 /* Enable UART */
f4d640c9
RH
817#ifdef CONFIG_BF54x
818 UART_SET_IER(uart, ier);
819#else
194de561 820 UART_PUT_IER(uart, ier);
f4d640c9 821#endif
194de561
BW
822
823 val = UART_GET_GCTL(uart);
824 val |= UCEN;
825 UART_PUT_GCTL(uart, val);
826
827 spin_unlock_irqrestore(&uart->port.lock, flags);
828}
829
830static const char *bfin_serial_type(struct uart_port *port)
831{
832 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
833
834 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
835}
836
837/*
838 * Release the memory region(s) being used by 'port'.
839 */
840static void bfin_serial_release_port(struct uart_port *port)
841{
842}
843
844/*
845 * Request the memory region(s) being used by 'port'.
846 */
847static int bfin_serial_request_port(struct uart_port *port)
848{
849 return 0;
850}
851
852/*
853 * Configure/autoconfigure the port.
854 */
855static void bfin_serial_config_port(struct uart_port *port, int flags)
856{
857 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
858
859 if (flags & UART_CONFIG_TYPE &&
860 bfin_serial_request_port(&uart->port) == 0)
861 uart->port.type = PORT_BFIN;
862}
863
864/*
865 * Verify the new serial_struct (for TIOCSSERIAL).
866 * The only change we allow are to the flags and type, and
867 * even then only between PORT_BFIN and PORT_UNKNOWN
868 */
869static int
870bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
871{
872 return 0;
873}
874
875static struct uart_ops bfin_serial_pops = {
876 .tx_empty = bfin_serial_tx_empty,
877 .set_mctrl = bfin_serial_set_mctrl,
878 .get_mctrl = bfin_serial_get_mctrl,
879 .stop_tx = bfin_serial_stop_tx,
880 .start_tx = bfin_serial_start_tx,
881 .stop_rx = bfin_serial_stop_rx,
882 .enable_ms = bfin_serial_enable_ms,
883 .break_ctl = bfin_serial_break_ctl,
884 .startup = bfin_serial_startup,
885 .shutdown = bfin_serial_shutdown,
886 .set_termios = bfin_serial_set_termios,
887 .type = bfin_serial_type,
888 .release_port = bfin_serial_release_port,
889 .request_port = bfin_serial_request_port,
890 .config_port = bfin_serial_config_port,
891 .verify_port = bfin_serial_verify_port,
892};
893
894static void __init bfin_serial_init_ports(void)
895{
896 static int first = 1;
897 int i;
898
899 if (!first)
900 return;
901 first = 0;
902
903 for (i = 0; i < nr_ports; i++) {
904 bfin_serial_ports[i].port.uartclk = get_sclk();
905 bfin_serial_ports[i].port.ops = &bfin_serial_pops;
906 bfin_serial_ports[i].port.line = i;
907 bfin_serial_ports[i].port.iotype = UPIO_MEM;
908 bfin_serial_ports[i].port.membase =
909 (void __iomem *)bfin_serial_resource[i].uart_base_addr;
910 bfin_serial_ports[i].port.mapbase =
911 bfin_serial_resource[i].uart_base_addr;
912 bfin_serial_ports[i].port.irq =
913 bfin_serial_resource[i].uart_irq;
914 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
915#ifdef CONFIG_SERIAL_BFIN_DMA
916 bfin_serial_ports[i].tx_done = 1;
917 bfin_serial_ports[i].tx_count = 0;
918 bfin_serial_ports[i].tx_dma_channel =
919 bfin_serial_resource[i].uart_tx_dma_channel;
920 bfin_serial_ports[i].rx_dma_channel =
921 bfin_serial_resource[i].uart_rx_dma_channel;
922 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
923#else
924 INIT_WORK(&bfin_serial_ports[i].cts_workqueue, bfin_serial_do_work);
925#endif
926#ifdef CONFIG_SERIAL_BFIN_CTSRTS
927 bfin_serial_ports[i].cts_pin =
928 bfin_serial_resource[i].uart_cts_pin;
929 bfin_serial_ports[i].rts_pin =
930 bfin_serial_resource[i].uart_rts_pin;
931#endif
932 bfin_serial_hw_init(&bfin_serial_ports[i]);
194de561 933 }
f4d640c9 934
194de561
BW
935}
936
937#ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW
938/*
939 * If the port was already initialised (eg, by a boot loader),
940 * try to determine the current setup.
941 */
942static void __init
943bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
944 int *parity, int *bits)
945{
946 unsigned short status;
947
948 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
949 if (status == (ERBFI | ETBEI)) {
950 /* ok, the port was enabled */
951 unsigned short lcr, val;
952 unsigned short dlh, dll;
953
954 lcr = UART_GET_LCR(uart);
955
956 *parity = 'n';
957 if (lcr & PEN) {
958 if (lcr & EPS)
959 *parity = 'e';
960 else
961 *parity = 'o';
962 }
963 switch (lcr & 0x03) {
964 case 0: *bits = 5; break;
965 case 1: *bits = 6; break;
966 case 2: *bits = 7; break;
967 case 3: *bits = 8; break;
968 }
f4d640c9 969#ifndef CONFIG_BF54x
194de561
BW
970 /* Set DLAB in LCR to Access DLL and DLH */
971 val = UART_GET_LCR(uart);
972 val |= DLAB;
973 UART_PUT_LCR(uart, val);
f4d640c9 974#endif
194de561
BW
975
976 dll = UART_GET_DLL(uart);
977 dlh = UART_GET_DLH(uart);
978
f4d640c9 979#ifndef CONFIG_BF54x
194de561
BW
980 /* Clear DLAB in LCR to Access THR RBR IER */
981 val = UART_GET_LCR(uart);
982 val &= ~DLAB;
983 UART_PUT_LCR(uart, val);
f4d640c9 984#endif
194de561
BW
985
986 *baud = get_sclk() / (16*(dll | dlh << 8));
987 }
988 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __FUNCTION__, *baud, *parity, *bits);
989}
0ae53640
RG
990#endif
991
992#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
993static struct uart_driver bfin_serial_reg;
194de561
BW
994
995static int __init
996bfin_serial_console_setup(struct console *co, char *options)
997{
998 struct bfin_serial_port *uart;
0ae53640 999# ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW
1000 int baud = 57600;
1001 int bits = 8;
1002 int parity = 'n';
0ae53640 1003# ifdef CONFIG_SERIAL_BFIN_CTSRTS
194de561 1004 int flow = 'r';
0ae53640 1005# else
194de561 1006 int flow = 'n';
0ae53640
RG
1007# endif
1008# endif
194de561
BW
1009
1010 /*
1011 * Check whether an invalid uart number has been specified, and
1012 * if so, search for the first available port that does have
1013 * console support.
1014 */
1015 if (co->index == -1 || co->index >= nr_ports)
1016 co->index = 0;
1017 uart = &bfin_serial_ports[co->index];
1018
0ae53640 1019# ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW
1020 if (options)
1021 uart_parse_options(options, &baud, &parity, &bits, &flow);
1022 else
1023 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1024
1025 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
0ae53640
RG
1026# else
1027 return 0;
1028# endif
1029}
1030#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1031 defined (CONFIG_EARLY_PRINTK) */
1032
1033#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1034static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1035{
1036 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1037 while (!(UART_GET_LSR(uart) & THRE))
1038 barrier();
1039 UART_PUT_CHAR(uart, ch);
1040 SSYNC();
1041}
1042
1043/*
1044 * Interrupts are disabled on entering
1045 */
1046static void
1047bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1048{
1049 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
1050 int flags = 0;
1051
1052 spin_lock_irqsave(&uart->port.lock, flags);
1053 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1054 spin_unlock_irqrestore(&uart->port.lock, flags);
1055
194de561
BW
1056}
1057
194de561
BW
1058static struct console bfin_serial_console = {
1059 .name = BFIN_SERIAL_NAME,
1060 .write = bfin_serial_console_write,
1061 .device = uart_console_device,
1062 .setup = bfin_serial_console_setup,
1063 .flags = CON_PRINTBUFFER,
1064 .index = -1,
1065 .data = &bfin_serial_reg,
1066};
1067
1068static int __init bfin_serial_rs_console_init(void)
1069{
1070 bfin_serial_init_ports();
1071 register_console(&bfin_serial_console);
474f1a66
SZ
1072#ifdef CONFIG_KGDB_UART
1073 kgdb_entry_state = 0;
1074 init_kgdb_uart();
1075#endif
194de561
BW
1076 return 0;
1077}
1078console_initcall(bfin_serial_rs_console_init);
1079
1080#define BFIN_SERIAL_CONSOLE &bfin_serial_console
1081#else
1082#define BFIN_SERIAL_CONSOLE NULL
0ae53640
RG
1083#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1084
1085
1086#ifdef CONFIG_EARLY_PRINTK
1087static __init void early_serial_putc(struct uart_port *port, int ch)
1088{
1089 unsigned timeout = 0xffff;
1090 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1091
1092 while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1093 cpu_relax();
1094 UART_PUT_CHAR(uart, ch);
1095}
1096
1097static __init void early_serial_write(struct console *con, const char *s,
1098 unsigned int n)
1099{
1100 struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1101 unsigned int i;
1102
1103 for (i = 0; i < n; i++, s++) {
1104 if (*s == '\n')
1105 early_serial_putc(&uart->port, '\r');
1106 early_serial_putc(&uart->port, *s);
1107 }
1108}
1109
1110static struct __init console bfin_early_serial_console = {
1111 .name = "early_BFuart",
1112 .write = early_serial_write,
1113 .device = uart_console_device,
1114 .flags = CON_PRINTBUFFER,
1115 .setup = bfin_serial_console_setup,
1116 .index = -1,
1117 .data = &bfin_serial_reg,
1118};
1119
1120struct console __init *bfin_earlyserial_init(unsigned int port,
1121 unsigned int cflag)
1122{
1123 struct bfin_serial_port *uart;
1124 struct ktermios t;
1125
1126 if (port == -1 || port >= nr_ports)
1127 port = 0;
1128 bfin_serial_init_ports();
1129 bfin_early_serial_console.index = port;
0ae53640
RG
1130 uart = &bfin_serial_ports[port];
1131 t.c_cflag = cflag;
1132 t.c_iflag = 0;
1133 t.c_oflag = 0;
1134 t.c_lflag = ICANON;
1135 t.c_line = port;
1136 bfin_serial_set_termios(&uart->port, &t, &t);
1137 return &bfin_early_serial_console;
1138}
1139
1140#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
194de561
BW
1141
1142static struct uart_driver bfin_serial_reg = {
1143 .owner = THIS_MODULE,
1144 .driver_name = "bfin-uart",
1145 .dev_name = BFIN_SERIAL_NAME,
1146 .major = BFIN_SERIAL_MAJOR,
1147 .minor = BFIN_SERIAL_MINOR,
1148 .nr = NR_PORTS,
1149 .cons = BFIN_SERIAL_CONSOLE,
1150};
1151
1152static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1153{
1154 struct bfin_serial_port *uart = platform_get_drvdata(dev);
1155
1156 if (uart)
1157 uart_suspend_port(&bfin_serial_reg, &uart->port);
1158
1159 return 0;
1160}
1161
1162static int bfin_serial_resume(struct platform_device *dev)
1163{
1164 struct bfin_serial_port *uart = platform_get_drvdata(dev);
1165
1166 if (uart)
1167 uart_resume_port(&bfin_serial_reg, &uart->port);
1168
1169 return 0;
1170}
1171
1172static int bfin_serial_probe(struct platform_device *dev)
1173{
1174 struct resource *res = dev->resource;
1175 int i;
1176
1177 for (i = 0; i < dev->num_resources; i++, res++)
1178 if (res->flags & IORESOURCE_MEM)
1179 break;
1180
1181 if (i < dev->num_resources) {
1182 for (i = 0; i < nr_ports; i++, res++) {
1183 if (bfin_serial_ports[i].port.mapbase != res->start)
1184 continue;
1185 bfin_serial_ports[i].port.dev = &dev->dev;
1186 uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1187 platform_set_drvdata(dev, &bfin_serial_ports[i]);
1188 }
1189 }
1190
1191 return 0;
1192}
1193
1194static int bfin_serial_remove(struct platform_device *pdev)
1195{
1196 struct bfin_serial_port *uart = platform_get_drvdata(pdev);
1197
1198
1199#ifdef CONFIG_SERIAL_BFIN_CTSRTS
1200 gpio_free(uart->cts_pin);
1201 gpio_free(uart->rts_pin);
1202#endif
1203
1204 platform_set_drvdata(pdev, NULL);
1205
1206 if (uart)
1207 uart_remove_one_port(&bfin_serial_reg, &uart->port);
1208
1209 return 0;
1210}
1211
1212static struct platform_driver bfin_serial_driver = {
1213 .probe = bfin_serial_probe,
1214 .remove = bfin_serial_remove,
1215 .suspend = bfin_serial_suspend,
1216 .resume = bfin_serial_resume,
1217 .driver = {
1218 .name = "bfin-uart",
1219 },
1220};
1221
1222static int __init bfin_serial_init(void)
1223{
1224 int ret;
474f1a66
SZ
1225#ifdef CONFIG_KGDB_UART
1226 struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
a359cca7 1227 struct ktermios t;
474f1a66 1228#endif
194de561
BW
1229
1230 pr_info("Serial: Blackfin serial driver\n");
1231
1232 bfin_serial_init_ports();
1233
1234 ret = uart_register_driver(&bfin_serial_reg);
1235 if (ret == 0) {
1236 ret = platform_driver_register(&bfin_serial_driver);
1237 if (ret) {
1238 pr_debug("uart register failed\n");
1239 uart_unregister_driver(&bfin_serial_reg);
1240 }
1241 }
474f1a66
SZ
1242#ifdef CONFIG_KGDB_UART
1243 if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) {
a359cca7 1244 request_irq(uart->port.irq, bfin_serial_rx_int,
474f1a66
SZ
1245 IRQF_DISABLED, "BFIN_UART_RX", uart);
1246 pr_info("Request irq for kgdb uart port\n");
a359cca7
SZ
1247#ifdef CONFIG_BF54x
1248 UART_SET_IER(uart, ERBFI);
1249#else
474f1a66 1250 UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
a359cca7 1251#endif
d5148ffa 1252 SSYNC();
474f1a66
SZ
1253 t.c_cflag = CS8|B57600;
1254 t.c_iflag = 0;
1255 t.c_oflag = 0;
1256 t.c_lflag = ICANON;
1257 t.c_line = CONFIG_KGDB_UART_PORT;
1258 bfin_serial_set_termios(&uart->port, &t, &t);
1259 }
1260#endif
194de561
BW
1261 return ret;
1262}
1263
1264static void __exit bfin_serial_exit(void)
1265{
1266 platform_driver_unregister(&bfin_serial_driver);
1267 uart_unregister_driver(&bfin_serial_reg);
1268}
1269
1270module_init(bfin_serial_init);
1271module_exit(bfin_serial_exit);
1272
1273MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1274MODULE_DESCRIPTION("Blackfin generic serial port driver");
1275MODULE_LICENSE("GPL");
1276MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);