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[PATCH] Serial: Add support for SIIG Quartet serial card
[net-next-2.6.git] / drivers / serial / 8250_pci.c
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1da177e4
LT		 1/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/pci.h>
19#include <linux/sched.h>
20#include <linux/string.h>
21#include <linux/kernel.h>
22#include <linux/slab.h>
23#include <linux/delay.h>
24#include <linux/tty.h>
25#include <linux/serial_core.h>
26#include <linux/8250_pci.h>
27#include <linux/bitops.h>
28
29#include <asm/byteorder.h>
30#include <asm/io.h>
31
32#include "8250.h"
33
34#undef SERIAL_DEBUG_PCI
35
36/*
37 * Definitions for PCI support.
38 */
39#define FL_BASE_MASK 0x0007
40#define FL_BASE0 0x0000
41#define FL_BASE1 0x0001
42#define FL_BASE2 0x0002
43#define FL_BASE3 0x0003
44#define FL_BASE4 0x0004
45#define FL_GET_BASE(x) (x & FL_BASE_MASK)
46
47/* Use successive BARs (PCI base address registers),
48 else use offset into some specified BAR */
49#define FL_BASE_BARS 0x0008
50
51/* do not assign an irq */
52#define FL_NOIRQ 0x0080
53
54/* Use the Base address register size to cap number of ports */
55#define FL_REGION_SZ_CAP 0x0100
56
57struct pci_board {
58 unsigned int flags;
59 unsigned int num_ports;
60 unsigned int base_baud;
61 unsigned int uart_offset;
62 unsigned int reg_shift;
63 unsigned int first_offset;
64};
65
66/*
67 * init function returns:
68 * > 0 - number of ports
69 * = 0 - use board->num_ports
70 * < 0 - error
71 */
72struct pci_serial_quirk {
73 u32 vendor;
74 u32 device;
75 u32 subvendor;
76 u32 subdevice;
77 int (*init)(struct pci_dev *dev);
78 int (*setup)(struct pci_dev *dev, struct pci_board *board,
79 struct uart_port *port, int idx);
80 void (*exit)(struct pci_dev *dev);
81};
82
83#define PCI_NUM_BAR_RESOURCES 6
84
85struct serial_private {
86 unsigned int nr;
87 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
88 struct pci_serial_quirk *quirk;
89 int line[0];
90};
91
92static void moan_device(const char *str, struct pci_dev *dev)
93{
94 printk(KERN_WARNING "%s: %s\n"
95 KERN_WARNING "Please send the output of lspci -vv, this\n"
96 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
97 KERN_WARNING "manufacturer and name of serial board or\n"
98 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
99 pci_name(dev), str, dev->vendor, dev->device,
100 dev->subsystem_vendor, dev->subsystem_device);
101}
102
103static int
104setup_port(struct pci_dev *dev, struct uart_port *port,
105 int bar, int offset, int regshift)
106{
107 struct serial_private *priv = pci_get_drvdata(dev);
108 unsigned long base, len;
109
110 if (bar >= PCI_NUM_BAR_RESOURCES)
111 return -EINVAL;
112
113 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
114 base = pci_resource_start(dev, bar);
115 len = pci_resource_len(dev, bar);
116
117 if (!priv->remapped_bar[bar])
118 priv->remapped_bar[bar] = ioremap(base, len);
119 if (!priv->remapped_bar[bar])
120 return -ENOMEM;
121
122 port->iotype = UPIO_MEM;
123 port->mapbase = base + offset;
124 port->membase = priv->remapped_bar[bar] + offset;
125 port->regshift = regshift;
126 } else {
127 base = pci_resource_start(dev, bar) + offset;
128 port->iotype = UPIO_PORT;
129 port->iobase = base;
130 }
131 return 0;
132}
133
134/*
135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
137 */
138static int
139afavlab_setup(struct pci_dev *dev, struct pci_board *board,
140 struct uart_port *port, int idx)
141{
142 unsigned int bar, offset = board->first_offset;
143
144 bar = FL_GET_BASE(board->flags);
145 if (idx < 4)
146 bar += idx;
147 else {
148 bar = 4;
149 offset += (idx - 4) * board->uart_offset;
150 }
151
152 return setup_port(dev, port, bar, offset, board->reg_shift);
153}
154
155/*
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
161 */
162static int __devinit pci_hp_diva_init(struct pci_dev *dev)
163{
164 int rc = 0;
165
166 switch (dev->subsystem_device) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
171 rc = 3;
172 break;
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
174 rc = 2;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
177 rc = 4;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
180 rc = 1;
181 break;
182 }
183
184 return rc;
185}
186
187/*
188 * HP's Diva chip puts the 4th/5th serial port further out, and
189 * some serial ports are supposed to be hidden on certain models.
190 */
191static int
192pci_hp_diva_setup(struct pci_dev *dev, struct pci_board *board,
193 struct uart_port *port, int idx)
194{
195 unsigned int offset = board->first_offset;
196 unsigned int bar = FL_GET_BASE(board->flags);
197
198 switch (dev->subsystem_device) {
199 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
200 if (idx == 3)
201 idx++;
202 break;
203 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
204 if (idx > 0)
205 idx++;
206 if (idx > 2)
207 idx++;
208 break;
209 }
210 if (idx > 2)
211 offset = 0x18;
212
213 offset += idx * board->uart_offset;
214
215 return setup_port(dev, port, bar, offset, board->reg_shift);
216}
217
218/*
219 * Added for EKF Intel i960 serial boards
220 */
221static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
222{
223 unsigned long oldval;
224
225 if (!(dev->subsystem_device & 0x1000))
226 return -ENODEV;
227
228 /* is firmware started? */
229 pci_read_config_dword(dev, 0x44, (void*) &oldval);
230 if (oldval == 0x00001000L) { /* RESET value */
231 printk(KERN_DEBUG "Local i960 firmware missing");
232 return -ENODEV;
233 }
234 return 0;
235}
236
237/*
238 * Some PCI serial cards using the PLX 9050 PCI interface chip require
239 * that the card interrupt be explicitly enabled or disabled. This
240 * seems to be mainly needed on card using the PLX which also use I/O
241 * mapped memory.
242 */
243static int __devinit pci_plx9050_init(struct pci_dev *dev)
244{
245 u8 irq_config;
246 void __iomem *p;
247
248 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
249 moan_device("no memory in bar 0", dev);
250 return 0;
251 }
252
253 irq_config = 0x41;
254 if (dev->vendor == PCI_VENDOR_ID_PANACOM)
255 irq_config = 0x43;
256 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
257 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
258 /*
259 * As the megawolf cards have the int pins active
260 * high, and have 2 UART chips, both ints must be
261 * enabled on the 9050. Also, the UARTS are set in
262 * 16450 mode by default, so we have to enable the
263 * 16C950 'enhanced' mode so that we can use the
264 * deep FIFOs
265 */
266 irq_config = 0x5b;
267 }
268
269 /*
270 * enable/disable interrupts
271 */
272 p = ioremap(pci_resource_start(dev, 0), 0x80);
273 if (p == NULL)
274 return -ENOMEM;
275 writel(irq_config, p + 0x4c);
276
277 /*
278 * Read the register back to ensure that it took effect.
279 */
280 readl(p + 0x4c);
281 iounmap(p);
282
283 return 0;
284}
285
286static void __devexit pci_plx9050_exit(struct pci_dev *dev)
287{
288 u8 __iomem *p;
289
290 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
291 return;
292
293 /*
294 * disable interrupts
295 */
296 p = ioremap(pci_resource_start(dev, 0), 0x80);
297 if (p != NULL) {
298 writel(0, p + 0x4c);
299
300 /*
301 * Read the register back to ensure that it took effect.
302 */
303 readl(p + 0x4c);
304 iounmap(p);
305 }
306}
307
308/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
309static int
310sbs_setup(struct pci_dev *dev, struct pci_board *board,
311 struct uart_port *port, int idx)
312{
313 unsigned int bar, offset = board->first_offset;
314
315 bar = 0;
316
317 if (idx < 4) {
318 /* first four channels map to 0, 0x100, 0x200, 0x300 */
319 offset += idx * board->uart_offset;
320 } else if (idx < 8) {
321 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
322 offset += idx * board->uart_offset + 0xC00;
323 } else /* we have only 8 ports on PMC-OCTALPRO */
324 return 1;
325
326 return setup_port(dev, port, bar, offset, board->reg_shift);
327}
328
329/*
330* This does initialization for PMC OCTALPRO cards:
331* maps the device memory, resets the UARTs (needed, bc
332* if the module is removed and inserted again, the card
333* is in the sleep mode) and enables global interrupt.
334*/
335
336/* global control register offset for SBS PMC-OctalPro */
337#define OCT_REG_CR_OFF 0x500
338
339static int __devinit sbs_init(struct pci_dev *dev)
340{
341 u8 __iomem *p;
342
343 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
344
345 if (p == NULL)
346 return -ENOMEM;
347 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
348 writeb(0x10,p + OCT_REG_CR_OFF);
349 udelay(50);
350 writeb(0x0,p + OCT_REG_CR_OFF);
351
352 /* Set bit-2 (INTENABLE) of Control Register */
353 writeb(0x4, p + OCT_REG_CR_OFF);
354 iounmap(p);
355
356 return 0;
357}
358
359/*
360 * Disables the global interrupt of PMC-OctalPro
361 */
362
363static void __devexit sbs_exit(struct pci_dev *dev)
364{
365 u8 __iomem *p;
366
367 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
368 if (p != NULL) {
369 writeb(0, p + OCT_REG_CR_OFF);
370 }
371 iounmap(p);
372}
373
374/*
375 * SIIG serial cards have an PCI interface chip which also controls
376 * the UART clocking frequency. Each UART can be clocked independently
377 * (except cards equiped with 4 UARTs) and initial clocking settings
378 * are stored in the EEPROM chip. It can cause problems because this
379 * version of serial driver doesn't support differently clocked UART's
380 * on single PCI card. To prevent this, initialization functions set
381 * high frequency clocking for all UART's on given card. It is safe (I
382 * hope) because it doesn't touch EEPROM settings to prevent conflicts
383 * with other OSes (like M$ DOS).
384 *
385 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
386 *
387 * There is two family of SIIG serial cards with different PCI
388 * interface chip and different configuration methods:
389 * - 10x cards have control registers in IO and/or memory space;
390 * - 20x cards have control registers in standard PCI configuration space.
391 *
fbc0dc0d
AP		 392 * There are also Quartet Serial cards which use Oxford Semiconductor
393 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
394 *
1da177e4
LT		 395 * Note: some SIIG cards are probed by the parport_serial object.
396 */
397
398#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
399#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
400
401static int pci_siig10x_init(struct pci_dev *dev)
402{
403 u16 data;
404 void __iomem *p;
405
406 switch (dev->device & 0xfff8) {
407 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
408 data = 0xffdf;
409 break;
410 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
411 data = 0xf7ff;
412 break;
413 default: /* 1S1P, 4S */
414 data = 0xfffb;
415 break;
416 }
417
418 p = ioremap(pci_resource_start(dev, 0), 0x80);
419 if (p == NULL)
420 return -ENOMEM;
421
422 writew(readw(p + 0x28) & data, p + 0x28);
423 readw(p + 0x28);
424 iounmap(p);
425 return 0;
426}
427
428#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
429#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
430
431static int pci_siig20x_init(struct pci_dev *dev)
432{
433 u8 data;
434
435 /* Change clock frequency for the first UART. */
436 pci_read_config_byte(dev, 0x6f, &data);
437 pci_write_config_byte(dev, 0x6f, data & 0xef);
438
439 /* If this card has 2 UART, we have to do the same with second UART. */
440 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
441 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
442 pci_read_config_byte(dev, 0x73, &data);
443 pci_write_config_byte(dev, 0x73, data & 0xef);
444 }
445 return 0;
446}
447
448int pci_siig10x_fn(struct pci_dev *dev, int enable)
449{
450 int ret = 0;
451 if (enable)
452 ret = pci_siig10x_init(dev);
453 return ret;
454}
455
456int pci_siig20x_fn(struct pci_dev *dev, int enable)
457{
458 int ret = 0;
459 if (enable)
460 ret = pci_siig20x_init(dev);
461 return ret;
462}
463
464EXPORT_SYMBOL(pci_siig10x_fn);
465EXPORT_SYMBOL(pci_siig20x_fn);
466
467/*
468 * Timedia has an explosion of boards, and to avoid the PCI table from
469 * growing *huge*, we use this function to collapse some 70 entries
470 * in the PCI table into one, for sanity's and compactness's sake.
471 */
472static unsigned short timedia_single_port[] = {
473 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
474};
475
476static unsigned short timedia_dual_port[] = {
477 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
478 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
479 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
480 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
481 0xD079, 0
482};
483
484static unsigned short timedia_quad_port[] = {
485 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
486 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
487 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
488 0xB157, 0
489};
490
491static unsigned short timedia_eight_port[] = {
492 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
493 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
494};
495
496static struct timedia_struct {
497 int num;
498 unsigned short *ids;
499} timedia_data[] = {
500 { 1, timedia_single_port },
501 { 2, timedia_dual_port },
502 { 4, timedia_quad_port },
503 { 8, timedia_eight_port },
504 { 0, NULL }
505};
506
507static int __devinit pci_timedia_init(struct pci_dev *dev)
508{
509 unsigned short *ids;
510 int i, j;
511
512 for (i = 0; timedia_data[i].num; i++) {
513 ids = timedia_data[i].ids;
514 for (j = 0; ids[j]; j++)
515 if (dev->subsystem_device == ids[j])
516 return timedia_data[i].num;
517 }
518 return 0;
519}
520
521/*
522 * Timedia/SUNIX uses a mixture of BARs and offsets
523 * Ugh, this is ugly as all hell --- TYT
524 */
525static int
526pci_timedia_setup(struct pci_dev *dev, struct pci_board *board,
527 struct uart_port *port, int idx)
528{
529 unsigned int bar = 0, offset = board->first_offset;
530
531 switch (idx) {
532 case 0:
533 bar = 0;
534 break;
535 case 1:
536 offset = board->uart_offset;
537 bar = 0;
538 break;
539 case 2:
540 bar = 1;
541 break;
542 case 3:
543 offset = board->uart_offset;
544 bar = 1;
545 case 4: /* BAR 2 */
546 case 5: /* BAR 3 */
547 case 6: /* BAR 4 */
548 case 7: /* BAR 5 */
549 bar = idx - 2;
550 }
551
552 return setup_port(dev, port, bar, offset, board->reg_shift);
553}
554
555/*
556 * Some Titan cards are also a little weird
557 */
558static int
559titan_400l_800l_setup(struct pci_dev *dev, struct pci_board *board,
560 struct uart_port *port, int idx)
561{
562 unsigned int bar, offset = board->first_offset;
563
564 switch (idx) {
565 case 0:
566 bar = 1;
567 break;
568 case 1:
569 bar = 2;
570 break;
571 default:
572 bar = 4;
573 offset = (idx - 2) * board->uart_offset;
574 }
575
576 return setup_port(dev, port, bar, offset, board->reg_shift);
577}
578
579static int __devinit pci_xircom_init(struct pci_dev *dev)
580{
581 msleep(100);
582 return 0;
583}
584
585static int __devinit pci_netmos_init(struct pci_dev *dev)
586{
587 /* subdevice 0x00PS means <P> parallel, <S> serial */
588 unsigned int num_serial = dev->subsystem_device & 0xf;
589
590 if (num_serial == 0)
591 return -ENODEV;
592 return num_serial;
593}
594
595static int
596pci_default_setup(struct pci_dev *dev, struct pci_board *board,
597 struct uart_port *port, int idx)
598{
599 unsigned int bar, offset = board->first_offset, maxnr;
600
601 bar = FL_GET_BASE(board->flags);
602 if (board->flags & FL_BASE_BARS)
603 bar += idx;
604 else
605 offset += idx * board->uart_offset;
606
607 maxnr = (pci_resource_len(dev, bar) - board->first_offset) /
608 (8 << board->reg_shift);
609
610 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
611 return 1;
612
613 return setup_port(dev, port, bar, offset, board->reg_shift);
614}
615
616/* This should be in linux/pci_ids.h */
617#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
618#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
619#define PCI_DEVICE_ID_OCTPRO 0x0001
620#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
621#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
622#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
623#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
624
625/*
626 * Master list of serial port init/setup/exit quirks.
627 * This does not describe the general nature of the port.
628 * (ie, baud base, number and location of ports, etc)
629 *
630 * This list is ordered alphabetically by vendor then device.
631 * Specific entries must come before more generic entries.
632 */
633static struct pci_serial_quirk pci_serial_quirks[] = {
634 /*
635 * AFAVLAB cards.
636 * It is not clear whether this applies to all products.
637 */
638 {
639 .vendor = PCI_VENDOR_ID_AFAVLAB,
640 .device = PCI_ANY_ID,
641 .subvendor = PCI_ANY_ID,
642 .subdevice = PCI_ANY_ID,
643 .setup = afavlab_setup,
644 },
645 /*
646 * HP Diva
647 */
648 {
649 .vendor = PCI_VENDOR_ID_HP,
650 .device = PCI_DEVICE_ID_HP_DIVA,
651 .subvendor = PCI_ANY_ID,
652 .subdevice = PCI_ANY_ID,
653 .init = pci_hp_diva_init,
654 .setup = pci_hp_diva_setup,
655 },
656 /*
657 * Intel
658 */
659 {
660 .vendor = PCI_VENDOR_ID_INTEL,
661 .device = PCI_DEVICE_ID_INTEL_80960_RP,
662 .subvendor = 0xe4bf,
663 .subdevice = PCI_ANY_ID,
664 .init = pci_inteli960ni_init,
665 .setup = pci_default_setup,
666 },
667 /*
668 * Panacom
669 */
670 {
671 .vendor = PCI_VENDOR_ID_PANACOM,
672 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
673 .subvendor = PCI_ANY_ID,
674 .subdevice = PCI_ANY_ID,
675 .init = pci_plx9050_init,
676 .setup = pci_default_setup,
677 .exit = __devexit_p(pci_plx9050_exit),
678 },
679 {
680 .vendor = PCI_VENDOR_ID_PANACOM,
681 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
682 .subvendor = PCI_ANY_ID,
683 .subdevice = PCI_ANY_ID,
684 .init = pci_plx9050_init,
685 .setup = pci_default_setup,
686 .exit = __devexit_p(pci_plx9050_exit),
687 },
688 /*
689 * PLX
690 */
691 {
692 .vendor = PCI_VENDOR_ID_PLX,
693 .device = PCI_DEVICE_ID_PLX_9050,
694 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
695 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
696 .init = pci_plx9050_init,
697 .setup = pci_default_setup,
698 .exit = __devexit_p(pci_plx9050_exit),
699 },
700 {
701 .vendor = PCI_VENDOR_ID_PLX,
702 .device = PCI_DEVICE_ID_PLX_ROMULUS,
703 .subvendor = PCI_VENDOR_ID_PLX,
704 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
705 .init = pci_plx9050_init,
706 .setup = pci_default_setup,
707 .exit = __devexit_p(pci_plx9050_exit),
708 },
709 /*
710 * SBS Technologies, Inc., PMC-OCTALPRO 232
711 */
712 {
713 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
714 .device = PCI_DEVICE_ID_OCTPRO,
715 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
716 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
717 .init = sbs_init,
718 .setup = sbs_setup,
719 .exit = __devexit_p(sbs_exit),
720 },
721 /*
722 * SBS Technologies, Inc., PMC-OCTALPRO 422
723 */
724 {
725 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
726 .device = PCI_DEVICE_ID_OCTPRO,
727 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
728 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
729 .init = sbs_init,
730 .setup = sbs_setup,
731 .exit = __devexit_p(sbs_exit),
732 },
733 /*
734 * SBS Technologies, Inc., P-Octal 232
735 */
736 {
737 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
738 .device = PCI_DEVICE_ID_OCTPRO,
739 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
740 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
741 .init = sbs_init,
742 .setup = sbs_setup,
743 .exit = __devexit_p(sbs_exit),
744 },
745 /*
746 * SBS Technologies, Inc., P-Octal 422
747 */
748 {
749 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
750 .device = PCI_DEVICE_ID_OCTPRO,
751 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
752 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
753 .init = sbs_init,
754 .setup = sbs_setup,
755 .exit = __devexit_p(sbs_exit),
756 },
757
758 /*
759 * SIIG cards.
760 * It is not clear whether these could be collapsed.
761 */
762 {
763 .vendor = PCI_VENDOR_ID_SIIG,
764 .device = PCI_DEVICE_ID_SIIG_1S_10x_550,
765 .subvendor = PCI_ANY_ID,
766 .subdevice = PCI_ANY_ID,
767 .init = pci_siig10x_init,
768 .setup = pci_default_setup,
769 },
770 {
771 .vendor = PCI_VENDOR_ID_SIIG,
772 .device = PCI_DEVICE_ID_SIIG_1S_10x_650,
773 .subvendor = PCI_ANY_ID,
774 .subdevice = PCI_ANY_ID,
775 .init = pci_siig10x_init,
776 .setup = pci_default_setup,
777 },
778 {
779 .vendor = PCI_VENDOR_ID_SIIG,
780 .device = PCI_DEVICE_ID_SIIG_1S_10x_850,
781 .subvendor = PCI_ANY_ID,
782 .subdevice = PCI_ANY_ID,
783 .init = pci_siig10x_init,
784 .setup = pci_default_setup,
785 },
786 {
787 .vendor = PCI_VENDOR_ID_SIIG,
788 .device = PCI_DEVICE_ID_SIIG_2S_10x_550,
789 .subvendor = PCI_ANY_ID,
790 .subdevice = PCI_ANY_ID,
791 .init = pci_siig10x_init,
792 .setup = pci_default_setup,
793 },
794 {
795 .vendor = PCI_VENDOR_ID_SIIG,
796 .device = PCI_DEVICE_ID_SIIG_2S_10x_650,
797 .subvendor = PCI_ANY_ID,
798 .subdevice = PCI_ANY_ID,
799 .init = pci_siig10x_init,
800 .setup = pci_default_setup,
801 },
802 {
803 .vendor = PCI_VENDOR_ID_SIIG,
804 .device = PCI_DEVICE_ID_SIIG_2S_10x_850,
805 .subvendor = PCI_ANY_ID,
806 .subdevice = PCI_ANY_ID,
807 .init = pci_siig10x_init,
808 .setup = pci_default_setup,
809 },
810 {
811 .vendor = PCI_VENDOR_ID_SIIG,
812 .device = PCI_DEVICE_ID_SIIG_4S_10x_550,
813 .subvendor = PCI_ANY_ID,
814 .subdevice = PCI_ANY_ID,
815 .init = pci_siig10x_init,
816 .setup = pci_default_setup,
817 },
818 {
819 .vendor = PCI_VENDOR_ID_SIIG,
820 .device = PCI_DEVICE_ID_SIIG_4S_10x_650,
821 .subvendor = PCI_ANY_ID,
822 .subdevice = PCI_ANY_ID,
823 .init = pci_siig10x_init,
824 .setup = pci_default_setup,
825 },
826 {
827 .vendor = PCI_VENDOR_ID_SIIG,
828 .device = PCI_DEVICE_ID_SIIG_4S_10x_850,
829 .subvendor = PCI_ANY_ID,
830 .subdevice = PCI_ANY_ID,
831 .init = pci_siig10x_init,
832 .setup = pci_default_setup,
833 },
834 {
835 .vendor = PCI_VENDOR_ID_SIIG,
836 .device = PCI_DEVICE_ID_SIIG_1S_20x_550,
837 .subvendor = PCI_ANY_ID,
838 .subdevice = PCI_ANY_ID,
839 .init = pci_siig20x_init,
840 .setup = pci_default_setup,
841 },
842 {
843 .vendor = PCI_VENDOR_ID_SIIG,
844 .device = PCI_DEVICE_ID_SIIG_1S_20x_650,
845 .subvendor = PCI_ANY_ID,
846 .subdevice = PCI_ANY_ID,
847 .init = pci_siig20x_init,
848 .setup = pci_default_setup,
849 },
850 {
851 .vendor = PCI_VENDOR_ID_SIIG,
852 .device = PCI_DEVICE_ID_SIIG_1S_20x_850,
853 .subvendor = PCI_ANY_ID,
854 .subdevice = PCI_ANY_ID,
855 .init = pci_siig20x_init,
856 .setup = pci_default_setup,
857 },
858 {
859 .vendor = PCI_VENDOR_ID_SIIG,
860 .device = PCI_DEVICE_ID_SIIG_2S_20x_550,
861 .subvendor = PCI_ANY_ID,
862 .subdevice = PCI_ANY_ID,
863 .init = pci_siig20x_init,
864 .setup = pci_default_setup,
865 },
866 { .vendor = PCI_VENDOR_ID_SIIG,
867 .device = PCI_DEVICE_ID_SIIG_2S_20x_650,
868 .subvendor = PCI_ANY_ID,
869 .subdevice = PCI_ANY_ID,
870 .init = pci_siig20x_init,
871 .setup = pci_default_setup,
872 },
873 {
874 .vendor = PCI_VENDOR_ID_SIIG,
875 .device = PCI_DEVICE_ID_SIIG_2S_20x_850,
876 .subvendor = PCI_ANY_ID,
877 .subdevice = PCI_ANY_ID,
878 .init = pci_siig20x_init,
879 .setup = pci_default_setup,
880 },
881 {
882 .vendor = PCI_VENDOR_ID_SIIG,
883 .device = PCI_DEVICE_ID_SIIG_4S_20x_550,
884 .subvendor = PCI_ANY_ID,
885 .subdevice = PCI_ANY_ID,
886 .init = pci_siig20x_init,
887 .setup = pci_default_setup,
888 },
889 {
890 .vendor = PCI_VENDOR_ID_SIIG,
891 .device = PCI_DEVICE_ID_SIIG_4S_20x_650,
892 .subvendor = PCI_ANY_ID,
893 .subdevice = PCI_ANY_ID,
894 .init = pci_siig20x_init,
895 .setup = pci_default_setup,
896 },
897 {
898 .vendor = PCI_VENDOR_ID_SIIG,
899 .device = PCI_DEVICE_ID_SIIG_4S_20x_850,
900 .subvendor = PCI_ANY_ID,
901 .subdevice = PCI_ANY_ID,
902 .init = pci_siig20x_init,
903 .setup = pci_default_setup,
904 },
905 /*
906 * Titan cards
907 */
908 {
909 .vendor = PCI_VENDOR_ID_TITAN,
910 .device = PCI_DEVICE_ID_TITAN_400L,
911 .subvendor = PCI_ANY_ID,
912 .subdevice = PCI_ANY_ID,
913 .setup = titan_400l_800l_setup,
914 },
915 {
916 .vendor = PCI_VENDOR_ID_TITAN,
917 .device = PCI_DEVICE_ID_TITAN_800L,
918 .subvendor = PCI_ANY_ID,
919 .subdevice = PCI_ANY_ID,
920 .setup = titan_400l_800l_setup,
921 },
922 /*
923 * Timedia cards
924 */
925 {
926 .vendor = PCI_VENDOR_ID_TIMEDIA,
927 .device = PCI_DEVICE_ID_TIMEDIA_1889,
928 .subvendor = PCI_VENDOR_ID_TIMEDIA,
929 .subdevice = PCI_ANY_ID,
930 .init = pci_timedia_init,
931 .setup = pci_timedia_setup,
932 },
933 {
934 .vendor = PCI_VENDOR_ID_TIMEDIA,
935 .device = PCI_ANY_ID,
936 .subvendor = PCI_ANY_ID,
937 .subdevice = PCI_ANY_ID,
938 .setup = pci_timedia_setup,
939 },
940 /*
941 * Xircom cards
942 */
943 {
944 .vendor = PCI_VENDOR_ID_XIRCOM,
945 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
946 .subvendor = PCI_ANY_ID,
947 .subdevice = PCI_ANY_ID,
948 .init = pci_xircom_init,
949 .setup = pci_default_setup,
950 },
951 /*
952 * Netmos cards
953 */
954 {
955 .vendor = PCI_VENDOR_ID_NETMOS,
956 .device = PCI_ANY_ID,
957 .subvendor = PCI_ANY_ID,
958 .subdevice = PCI_ANY_ID,
959 .init = pci_netmos_init,
960 .setup = pci_default_setup,
961 },
962 /*
963 * Default "match everything" terminator entry
964 */
965 {
966 .vendor = PCI_ANY_ID,
967 .device = PCI_ANY_ID,
968 .subvendor = PCI_ANY_ID,
969 .subdevice = PCI_ANY_ID,
970 .setup = pci_default_setup,
971 }
972};
973
974static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
975{
976 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
977}
978
979static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
980{
981 struct pci_serial_quirk *quirk;
982
983 for (quirk = pci_serial_quirks; ; quirk++)
984 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
985 quirk_id_matches(quirk->device, dev->device) &&
986 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
987 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
988 break;
989 return quirk;
990}
991
992static _INLINE_ int
993get_pci_irq(struct pci_dev *dev, struct pci_board *board, int idx)
994{
995 if (board->flags & FL_NOIRQ)
996 return 0;
997 else
998 return dev->irq;
999}
1000
1001/*
1002 * This is the configuration table for all of the PCI serial boards
1003 * which we support. It is directly indexed by the pci_board_num_t enum
1004 * value, which is encoded in the pci_device_id PCI probe table's
1005 * driver_data member.
1006 *
1007 * The makeup of these names are:
1008 * pbn_bn{_bt}_n_baud
1009 *
1010 * bn = PCI BAR number
1011 * bt = Index using PCI BARs
1012 * n = number of serial ports
1013 * baud = baud rate
1014 *
f1690f37
RK		 1015 * This table is sorted by (in order): baud, bt, bn, n.
1016 *
1da177e4
LT		 1017 * Please note: in theory if n = 1, _bt infix should make no difference.
1018 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1019 */
1020enum pci_board_num_t {
1021 pbn_default = 0,
1022
1023 pbn_b0_1_115200,
1024 pbn_b0_2_115200,
1025 pbn_b0_4_115200,
1026 pbn_b0_5_115200,
1027
1028 pbn_b0_1_921600,
1029 pbn_b0_2_921600,
1030 pbn_b0_4_921600,
1031
fbc0dc0d
AP		 1032 pbn_b0_4_1152000,
1033
1da177e4
LT		 1034 pbn_b0_bt_1_115200,
1035 pbn_b0_bt_2_115200,
1036 pbn_b0_bt_8_115200,
1037
1038 pbn_b0_bt_1_460800,
1039 pbn_b0_bt_2_460800,
1040 pbn_b0_bt_4_460800,
1041
1042 pbn_b0_bt_1_921600,
1043 pbn_b0_bt_2_921600,
1044 pbn_b0_bt_4_921600,
1045 pbn_b0_bt_8_921600,
1046
1047 pbn_b1_1_115200,
1048 pbn_b1_2_115200,
1049 pbn_b1_4_115200,
1050 pbn_b1_8_115200,
1051
1052 pbn_b1_1_921600,
1053 pbn_b1_2_921600,
1054 pbn_b1_4_921600,
1055 pbn_b1_8_921600,
1056
1057 pbn_b1_bt_2_921600,
1058
1059 pbn_b1_1_1382400,
1060 pbn_b1_2_1382400,
1061 pbn_b1_4_1382400,
1062 pbn_b1_8_1382400,
1063
1064 pbn_b2_1_115200,
1065 pbn_b2_8_115200,
1066
1067 pbn_b2_1_460800,
1068 pbn_b2_4_460800,
1069 pbn_b2_8_460800,
1070 pbn_b2_16_460800,
1071
1072 pbn_b2_1_921600,
1073 pbn_b2_4_921600,
1074 pbn_b2_8_921600,
1075
1076 pbn_b2_bt_1_115200,
1077 pbn_b2_bt_2_115200,
1078 pbn_b2_bt_4_115200,
1079
1080 pbn_b2_bt_2_921600,
1081 pbn_b2_bt_4_921600,
1082
1083 pbn_b3_4_115200,
1084 pbn_b3_8_115200,
1085
1086 /*
1087 * Board-specific versions.
1088 */
1089 pbn_panacom,
1090 pbn_panacom2,
1091 pbn_panacom4,
1092 pbn_plx_romulus,
1093 pbn_oxsemi,
1094 pbn_intel_i960,
1095 pbn_sgi_ioc3,
1096 pbn_nec_nile4,
1097 pbn_computone_4,
1098 pbn_computone_6,
1099 pbn_computone_8,
1100 pbn_sbsxrsio,
1101 pbn_exar_XR17C152,
1102 pbn_exar_XR17C154,
1103 pbn_exar_XR17C158,
1104};
1105
1106/*
1107 * uart_offset - the space between channels
1108 * reg_shift - describes how the UART registers are mapped
1109 * to PCI memory by the card.
1110 * For example IER register on SBS, Inc. PMC-OctPro is located at
1111 * offset 0x10 from the UART base, while UART_IER is defined as 1
1112 * in include/linux/serial_reg.h,
1113 * see first lines of serial_in() and serial_out() in 8250.c
1114*/
1115
1116static struct pci_board pci_boards[] __devinitdata = {
1117 [pbn_default] = {
1118 .flags = FL_BASE0,
1119 .num_ports = 1,
1120 .base_baud = 115200,
1121 .uart_offset = 8,
1122 },
1123 [pbn_b0_1_115200] = {
1124 .flags = FL_BASE0,
1125 .num_ports = 1,
1126 .base_baud = 115200,
1127 .uart_offset = 8,
1128 },
1129 [pbn_b0_2_115200] = {
1130 .flags = FL_BASE0,
1131 .num_ports = 2,
1132 .base_baud = 115200,
1133 .uart_offset = 8,
1134 },
1135 [pbn_b0_4_115200] = {
1136 .flags = FL_BASE0,
1137 .num_ports = 4,
1138 .base_baud = 115200,
1139 .uart_offset = 8,
1140 },
1141 [pbn_b0_5_115200] = {
1142 .flags = FL_BASE0,
1143 .num_ports = 5,
1144 .base_baud = 115200,
1145 .uart_offset = 8,
1146 },
1147
1148 [pbn_b0_1_921600] = {
1149 .flags = FL_BASE0,
1150 .num_ports = 1,
1151 .base_baud = 921600,
1152 .uart_offset = 8,
1153 },
1154 [pbn_b0_2_921600] = {
1155 .flags = FL_BASE0,
1156 .num_ports = 2,
1157 .base_baud = 921600,
1158 .uart_offset = 8,
1159 },
1160 [pbn_b0_4_921600] = {
1161 .flags = FL_BASE0,
1162 .num_ports = 4,
1163 .base_baud = 921600,
1164 .uart_offset = 8,
1165 },
fbc0dc0d
AP		 1166 [pbn_b0_4_1152000] = {
1167 .flags = FL_BASE0,
1168 .num_ports = 4,
1169 .base_baud = 1152000,
1170 .uart_offset = 8,
1171 },
1da177e4
LT		 1172
1173 [pbn_b0_bt_1_115200] = {
1174 .flags = FL_BASE0|FL_BASE_BARS,
1175 .num_ports = 1,
1176 .base_baud = 115200,
1177 .uart_offset = 8,
1178 },
1179 [pbn_b0_bt_2_115200] = {
1180 .flags = FL_BASE0|FL_BASE_BARS,
1181 .num_ports = 2,
1182 .base_baud = 115200,
1183 .uart_offset = 8,
1184 },
1185 [pbn_b0_bt_8_115200] = {
1186 .flags = FL_BASE0|FL_BASE_BARS,
1187 .num_ports = 8,
1188 .base_baud = 115200,
1189 .uart_offset = 8,
1190 },
1191
1192 [pbn_b0_bt_1_460800] = {
1193 .flags = FL_BASE0|FL_BASE_BARS,
1194 .num_ports = 1,
1195 .base_baud = 460800,
1196 .uart_offset = 8,
1197 },
1198 [pbn_b0_bt_2_460800] = {
1199 .flags = FL_BASE0|FL_BASE_BARS,
1200 .num_ports = 2,
1201 .base_baud = 460800,
1202 .uart_offset = 8,
1203 },
1204 [pbn_b0_bt_4_460800] = {
1205 .flags = FL_BASE0|FL_BASE_BARS,
1206 .num_ports = 4,
1207 .base_baud = 460800,
1208 .uart_offset = 8,
1209 },
1210
1211 [pbn_b0_bt_1_921600] = {
1212 .flags = FL_BASE0|FL_BASE_BARS,
1213 .num_ports = 1,
1214 .base_baud = 921600,
1215 .uart_offset = 8,
1216 },
1217 [pbn_b0_bt_2_921600] = {
1218 .flags = FL_BASE0|FL_BASE_BARS,
1219 .num_ports = 2,
1220 .base_baud = 921600,
1221 .uart_offset = 8,
1222 },
1223 [pbn_b0_bt_4_921600] = {
1224 .flags = FL_BASE0|FL_BASE_BARS,
1225 .num_ports = 4,
1226 .base_baud = 921600,
1227 .uart_offset = 8,
1228 },
1229 [pbn_b0_bt_8_921600] = {
1230 .flags = FL_BASE0|FL_BASE_BARS,
1231 .num_ports = 8,
1232 .base_baud = 921600,
1233 .uart_offset = 8,
1234 },
1235
1236 [pbn_b1_1_115200] = {
1237 .flags = FL_BASE1,
1238 .num_ports = 1,
1239 .base_baud = 115200,
1240 .uart_offset = 8,
1241 },
1242 [pbn_b1_2_115200] = {
1243 .flags = FL_BASE1,
1244 .num_ports = 2,
1245 .base_baud = 115200,
1246 .uart_offset = 8,
1247 },
1248 [pbn_b1_4_115200] = {
1249 .flags = FL_BASE1,
1250 .num_ports = 4,
1251 .base_baud = 115200,
1252 .uart_offset = 8,
1253 },
1254 [pbn_b1_8_115200] = {
1255 .flags = FL_BASE1,
1256 .num_ports = 8,
1257 .base_baud = 115200,
1258 .uart_offset = 8,
1259 },
1260
1261 [pbn_b1_1_921600] = {
1262 .flags = FL_BASE1,
1263 .num_ports = 1,
1264 .base_baud = 921600,
1265 .uart_offset = 8,
1266 },
1267 [pbn_b1_2_921600] = {
1268 .flags = FL_BASE1,
1269 .num_ports = 2,
1270 .base_baud = 921600,
1271 .uart_offset = 8,
1272 },
1273 [pbn_b1_4_921600] = {
1274 .flags = FL_BASE1,
1275 .num_ports = 4,
1276 .base_baud = 921600,
1277 .uart_offset = 8,
1278 },
1279 [pbn_b1_8_921600] = {
1280 .flags = FL_BASE1,
1281 .num_ports = 8,
1282 .base_baud = 921600,
1283 .uart_offset = 8,
1284 },
1285
1286 [pbn_b1_bt_2_921600] = {
1287 .flags = FL_BASE1|FL_BASE_BARS,
1288 .num_ports = 2,
1289 .base_baud = 921600,
1290 .uart_offset = 8,
1291 },
1292
1293 [pbn_b1_1_1382400] = {
1294 .flags = FL_BASE1,
1295 .num_ports = 1,
1296 .base_baud = 1382400,
1297 .uart_offset = 8,
1298 },
1299 [pbn_b1_2_1382400] = {
1300 .flags = FL_BASE1,
1301 .num_ports = 2,
1302 .base_baud = 1382400,
1303 .uart_offset = 8,
1304 },
1305 [pbn_b1_4_1382400] = {
1306 .flags = FL_BASE1,
1307 .num_ports = 4,
1308 .base_baud = 1382400,
1309 .uart_offset = 8,
1310 },
1311 [pbn_b1_8_1382400] = {
1312 .flags = FL_BASE1,
1313 .num_ports = 8,
1314 .base_baud = 1382400,
1315 .uart_offset = 8,
1316 },
1317
1318 [pbn_b2_1_115200] = {
1319 .flags = FL_BASE2,
1320 .num_ports = 1,
1321 .base_baud = 115200,
1322 .uart_offset = 8,
1323 },
1324 [pbn_b2_8_115200] = {
1325 .flags = FL_BASE2,
1326 .num_ports = 8,
1327 .base_baud = 115200,
1328 .uart_offset = 8,
1329 },
1330
1331 [pbn_b2_1_460800] = {
1332 .flags = FL_BASE2,
1333 .num_ports = 1,
1334 .base_baud = 460800,
1335 .uart_offset = 8,
1336 },
1337 [pbn_b2_4_460800] = {
1338 .flags = FL_BASE2,
1339 .num_ports = 4,
1340 .base_baud = 460800,
1341 .uart_offset = 8,
1342 },
1343 [pbn_b2_8_460800] = {
1344 .flags = FL_BASE2,
1345 .num_ports = 8,
1346 .base_baud = 460800,
1347 .uart_offset = 8,
1348 },
1349 [pbn_b2_16_460800] = {
1350 .flags = FL_BASE2,
1351 .num_ports = 16,
1352 .base_baud = 460800,
1353 .uart_offset = 8,
1354 },
1355
1356 [pbn_b2_1_921600] = {
1357 .flags = FL_BASE2,
1358 .num_ports = 1,
1359 .base_baud = 921600,
1360 .uart_offset = 8,
1361 },
1362 [pbn_b2_4_921600] = {
1363 .flags = FL_BASE2,
1364 .num_ports = 4,
1365 .base_baud = 921600,
1366 .uart_offset = 8,
1367 },
1368 [pbn_b2_8_921600] = {
1369 .flags = FL_BASE2,
1370 .num_ports = 8,
1371 .base_baud = 921600,
1372 .uart_offset = 8,
1373 },
1374
1375 [pbn_b2_bt_1_115200] = {
1376 .flags = FL_BASE2|FL_BASE_BARS,
1377 .num_ports = 1,
1378 .base_baud = 115200,
1379 .uart_offset = 8,
1380 },
1381 [pbn_b2_bt_2_115200] = {
1382 .flags = FL_BASE2|FL_BASE_BARS,
1383 .num_ports = 2,
1384 .base_baud = 115200,
1385 .uart_offset = 8,
1386 },
1387 [pbn_b2_bt_4_115200] = {
1388 .flags = FL_BASE2|FL_BASE_BARS,
1389 .num_ports = 4,
1390 .base_baud = 115200,
1391 .uart_offset = 8,
1392 },
1393
1394 [pbn_b2_bt_2_921600] = {
1395 .flags = FL_BASE2|FL_BASE_BARS,
1396 .num_ports = 2,
1397 .base_baud = 921600,
1398 .uart_offset = 8,
1399 },
1400 [pbn_b2_bt_4_921600] = {
1401 .flags = FL_BASE2|FL_BASE_BARS,
1402 .num_ports = 4,
1403 .base_baud = 921600,
1404 .uart_offset = 8,
1405 },
1406
1407 [pbn_b3_4_115200] = {
1408 .flags = FL_BASE3,
1409 .num_ports = 4,
1410 .base_baud = 115200,
1411 .uart_offset = 8,
1412 },
1413 [pbn_b3_8_115200] = {
1414 .flags = FL_BASE3,
1415 .num_ports = 8,
1416 .base_baud = 115200,
1417 .uart_offset = 8,
1418 },
1419
1420 /*
1421 * Entries following this are board-specific.
1422 */
1423
1424 /*
1425 * Panacom - IOMEM
1426 */
1427 [pbn_panacom] = {
1428 .flags = FL_BASE2,
1429 .num_ports = 2,
1430 .base_baud = 921600,
1431 .uart_offset = 0x400,
1432 .reg_shift = 7,
1433 },
1434 [pbn_panacom2] = {
1435 .flags = FL_BASE2|FL_BASE_BARS,
1436 .num_ports = 2,
1437 .base_baud = 921600,
1438 .uart_offset = 0x400,
1439 .reg_shift = 7,
1440 },
1441 [pbn_panacom4] = {
1442 .flags = FL_BASE2|FL_BASE_BARS,
1443 .num_ports = 4,
1444 .base_baud = 921600,
1445 .uart_offset = 0x400,
1446 .reg_shift = 7,
1447 },
1448
1449 /* I think this entry is broken - the first_offset looks wrong --rmk */
1450 [pbn_plx_romulus] = {
1451 .flags = FL_BASE2,
1452 .num_ports = 4,
1453 .base_baud = 921600,
1454 .uart_offset = 8 << 2,
1455 .reg_shift = 2,
1456 .first_offset = 0x03,
1457 },
1458
1459 /*
1460 * This board uses the size of PCI Base region 0 to
1461 * signal now many ports are available
1462 */
1463 [pbn_oxsemi] = {
1464 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1465 .num_ports = 32,
1466 .base_baud = 115200,
1467 .uart_offset = 8,
1468 },
1469
1470 /*
1471 * EKF addition for i960 Boards form EKF with serial port.
1472 * Max 256 ports.
1473 */
1474 [pbn_intel_i960] = {
1475 .flags = FL_BASE0,
1476 .num_ports = 32,
1477 .base_baud = 921600,
1478 .uart_offset = 8 << 2,
1479 .reg_shift = 2,
1480 .first_offset = 0x10000,
1481 },
1482 [pbn_sgi_ioc3] = {
1483 .flags = FL_BASE0|FL_NOIRQ,
1484 .num_ports = 1,
1485 .base_baud = 458333,
1486 .uart_offset = 8,
1487 .reg_shift = 0,
1488 .first_offset = 0x20178,
1489 },
1490
1491 /*
1492 * NEC Vrc-5074 (Nile 4) builtin UART.
1493 */
1494 [pbn_nec_nile4] = {
1495 .flags = FL_BASE0,
1496 .num_ports = 1,
1497 .base_baud = 520833,
1498 .uart_offset = 8 << 3,
1499 .reg_shift = 3,
1500 .first_offset = 0x300,
1501 },
1502
1503 /*
1504 * Computone - uses IOMEM.
1505 */
1506 [pbn_computone_4] = {
1507 .flags = FL_BASE0,
1508 .num_ports = 4,
1509 .base_baud = 921600,
1510 .uart_offset = 0x40,
1511 .reg_shift = 2,
1512 .first_offset = 0x200,
1513 },
1514 [pbn_computone_6] = {
1515 .flags = FL_BASE0,
1516 .num_ports = 6,
1517 .base_baud = 921600,
1518 .uart_offset = 0x40,
1519 .reg_shift = 2,
1520 .first_offset = 0x200,
1521 },
1522 [pbn_computone_8] = {
1523 .flags = FL_BASE0,
1524 .num_ports = 8,
1525 .base_baud = 921600,
1526 .uart_offset = 0x40,
1527 .reg_shift = 2,
1528 .first_offset = 0x200,
1529 },
1530 [pbn_sbsxrsio] = {
1531 .flags = FL_BASE0,
1532 .num_ports = 8,
1533 .base_baud = 460800,
1534 .uart_offset = 256,
1535 .reg_shift = 4,
1536 },
1537 /*
1538 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1539 * Only basic 16550A support.
1540 * XR17C15[24] are not tested, but they should work.
1541 */
1542 [pbn_exar_XR17C152] = {
1543 .flags = FL_BASE0,
1544 .num_ports = 2,
1545 .base_baud = 921600,
1546 .uart_offset = 0x200,
1547 },
1548 [pbn_exar_XR17C154] = {
1549 .flags = FL_BASE0,
1550 .num_ports = 4,
1551 .base_baud = 921600,
1552 .uart_offset = 0x200,
1553 },
1554 [pbn_exar_XR17C158] = {
1555 .flags = FL_BASE0,
1556 .num_ports = 8,
1557 .base_baud = 921600,
1558 .uart_offset = 0x200,
1559 },
1560};
1561
1562/*
1563 * Given a complete unknown PCI device, try to use some heuristics to
1564 * guess what the configuration might be, based on the pitiful PCI
1565 * serial specs. Returns 0 on success, 1 on failure.
1566 */
1567static int __devinit
1568serial_pci_guess_board(struct pci_dev *dev, struct pci_board *board)
1569{
1570 int num_iomem, num_port, first_port = -1, i;
1571
1572 /*
1573 * If it is not a communications device or the programming
1574 * interface is greater than 6, give up.
1575 *
1576 * (Should we try to make guesses for multiport serial devices
1577 * later?)
1578 */
1579 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1580 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1581 (dev->class & 0xff) > 6)
1582 return -ENODEV;
1583
1584 num_iomem = num_port = 0;
1585 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1586 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1587 num_port++;
1588 if (first_port == -1)
1589 first_port = i;
1590 }
1591 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1592 num_iomem++;
1593 }
1594
1595 /*
1596 * If there is 1 or 0 iomem regions, and exactly one port,
1597 * use it. We guess the number of ports based on the IO
1598 * region size.
1599 */
1600 if (num_iomem <= 1 && num_port == 1) {
1601 board->flags = first_port;
1602 board->num_ports = pci_resource_len(dev, first_port) / 8;
1603 return 0;
1604 }
1605
1606 /*
1607 * Now guess if we've got a board which indexes by BARs.
1608 * Each IO BAR should be 8 bytes, and they should follow
1609 * consecutively.
1610 */
1611 first_port = -1;
1612 num_port = 0;
1613 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1614 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1615 pci_resource_len(dev, i) == 8 &&
1616 (first_port == -1 || (first_port + num_port) == i)) {
1617 num_port++;
1618 if (first_port == -1)
1619 first_port = i;
1620 }
1621 }
1622
1623 if (num_port > 1) {
1624 board->flags = first_port | FL_BASE_BARS;
1625 board->num_ports = num_port;
1626 return 0;
1627 }
1628
1629 return -ENODEV;
1630}
1631
1632static inline int
1633serial_pci_matches(struct pci_board *board, struct pci_board *guessed)
1634{
1635 return
1636 board->num_ports == guessed->num_ports &&
1637 board->base_baud == guessed->base_baud &&
1638 board->uart_offset == guessed->uart_offset &&
1639 board->reg_shift == guessed->reg_shift &&
1640 board->first_offset == guessed->first_offset;
1641}
1642
1643/*
1644 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1645 * to the arrangement of serial ports on a PCI card.
1646 */
1647static int __devinit
1648pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1649{
1650 struct serial_private *priv;
1651 struct pci_board *board, tmp;
1652 struct pci_serial_quirk *quirk;
1653 int rc, nr_ports, i;
1654
1655 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1656 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1657 ent->driver_data);
1658 return -EINVAL;
1659 }
1660
1661 board = &pci_boards[ent->driver_data];
1662
1663 rc = pci_enable_device(dev);
1664 if (rc)
1665 return rc;
1666
1667 if (ent->driver_data == pbn_default) {
1668 /*
1669 * Use a copy of the pci_board entry for this;
1670 * avoid changing entries in the table.
1671 */
1672 memcpy(&tmp, board, sizeof(struct pci_board));
1673 board = &tmp;
1674
1675 /*
1676 * We matched one of our class entries. Try to
1677 * determine the parameters of this board.
1678 */
1679 rc = serial_pci_guess_board(dev, board);
1680 if (rc)
1681 goto disable;
1682 } else {
1683 /*
1684 * We matched an explicit entry. If we are able to
1685 * detect this boards settings with our heuristic,
1686 * then we no longer need this entry.
1687 */
1688 memcpy(&tmp, &pci_boards[pbn_default], sizeof(struct pci_board));
1689 rc = serial_pci_guess_board(dev, &tmp);
1690 if (rc == 0 && serial_pci_matches(board, &tmp))
1691 moan_device("Redundant entry in serial pci_table.",
1692 dev);
1693 }
1694
1695 nr_ports = board->num_ports;
1696
1697 /*
1698 * Find an init and setup quirks.
1699 */
1700 quirk = find_quirk(dev);
1701
1702 /*
1703 * Run the new-style initialization function.
1704 * The initialization function returns:
1705 * <0 - error
1706 * 0 - use board->num_ports
1707 * >0 - number of ports
1708 */
1709 if (quirk->init) {
1710 rc = quirk->init(dev);
1711 if (rc < 0)
1712 goto disable;
1713 if (rc)
1714 nr_ports = rc;
1715 }
1716
1717 priv = kmalloc(sizeof(struct serial_private) +
1718 sizeof(unsigned int) * nr_ports,
1719 GFP_KERNEL);
1720 if (!priv) {
1721 rc = -ENOMEM;
1722 goto deinit;
1723 }
1724
1725 memset(priv, 0, sizeof(struct serial_private) +
1726 sizeof(unsigned int) * nr_ports);
1727
1728 priv->quirk = quirk;
1729 pci_set_drvdata(dev, priv);
1730
1731 for (i = 0; i < nr_ports; i++) {
1732 struct uart_port serial_port;
1733 memset(&serial_port, 0, sizeof(struct uart_port));
1734
1735 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF |
1736 UPF_SHARE_IRQ;
1737 serial_port.uartclk = board->base_baud * 16;
1738 serial_port.irq = get_pci_irq(dev, board, i);
1739 serial_port.dev = &dev->dev;
1740 if (quirk->setup(dev, board, &serial_port, i))
1741 break;
1742#ifdef SERIAL_DEBUG_PCI
1743 printk("Setup PCI port: port %x, irq %d, type %d\n",
1744 serial_port.iobase, serial_port.irq, serial_port.iotype);
1745#endif
1746
1747 priv->line[i] = serial8250_register_port(&serial_port);
1748 if (priv->line[i] < 0) {
1749 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1750 break;
1751 }
1752 }
1753
1754 priv->nr = i;
1755
1756 return 0;
1757
1758 deinit:
1759 if (quirk->exit)
1760 quirk->exit(dev);
1761 disable:
1762 pci_disable_device(dev);
1763 return rc;
1764}
1765
1766static void __devexit pciserial_remove_one(struct pci_dev *dev)
1767{
1768 struct serial_private *priv = pci_get_drvdata(dev);
1769
1770 pci_set_drvdata(dev, NULL);
1771
1772 if (priv) {
1773 struct pci_serial_quirk *quirk;
1774 int i;
1775
1776 for (i = 0; i < priv->nr; i++)
1777 serial8250_unregister_port(priv->line[i]);
1778
1779 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1780 if (priv->remapped_bar[i])
1781 iounmap(priv->remapped_bar[i]);
1782 priv->remapped_bar[i] = NULL;
1783 }
1784
1785 /*
1786 * Find the exit quirks.
1787 */
1788 quirk = find_quirk(dev);
1789 if (quirk->exit)
1790 quirk->exit(dev);
1791
1792 pci_disable_device(dev);
1793
1794 kfree(priv);
1795 }
1796}
1797
1798static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1799{
1800 struct serial_private *priv = pci_get_drvdata(dev);
1801
1802 if (priv) {
1803 int i;
1804
1805 for (i = 0; i < priv->nr; i++)
1806 serial8250_suspend_port(priv->line[i]);
1807 }
1808 pci_save_state(dev);
1809 pci_set_power_state(dev, pci_choose_state(dev, state));
1810 return 0;
1811}
1812
1813static int pciserial_resume_one(struct pci_dev *dev)
1814{
1815 struct serial_private *priv = pci_get_drvdata(dev);
1816
1817 pci_set_power_state(dev, PCI_D0);
1818 pci_restore_state(dev);
1819
1820 if (priv) {
1821 int i;
1822
1823 /*
1824 * The device may have been disabled. Re-enable it.
1825 */
1826 pci_enable_device(dev);
1827
1828 /*
1829 * Ensure that the board is correctly configured.
1830 */
1831 if (priv->quirk->init)
1832 priv->quirk->init(dev);
1833
1834 for (i = 0; i < priv->nr; i++)
1835 serial8250_resume_port(priv->line[i]);
1836 }
1837 return 0;
1838}
1839
1840static struct pci_device_id serial_pci_tbl[] = {
1841 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1842 PCI_SUBVENDOR_ID_CONNECT_TECH,
1843 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1844 pbn_b1_8_1382400 },
1845 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1846 PCI_SUBVENDOR_ID_CONNECT_TECH,
1847 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1848 pbn_b1_4_1382400 },
1849 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1850 PCI_SUBVENDOR_ID_CONNECT_TECH,
1851 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1852 pbn_b1_2_1382400 },
1853 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1854 PCI_SUBVENDOR_ID_CONNECT_TECH,
1855 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1856 pbn_b1_8_1382400 },
1857 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1858 PCI_SUBVENDOR_ID_CONNECT_TECH,
1859 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1860 pbn_b1_4_1382400 },
1861 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1862 PCI_SUBVENDOR_ID_CONNECT_TECH,
1863 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1864 pbn_b1_2_1382400 },
1865 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1866 PCI_SUBVENDOR_ID_CONNECT_TECH,
1867 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1868 pbn_b1_8_921600 },
1869 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1870 PCI_SUBVENDOR_ID_CONNECT_TECH,
1871 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1872 pbn_b1_8_921600 },
1873 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1874 PCI_SUBVENDOR_ID_CONNECT_TECH,
1875 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1876 pbn_b1_4_921600 },
1877 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1878 PCI_SUBVENDOR_ID_CONNECT_TECH,
1879 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1880 pbn_b1_4_921600 },
1881 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1882 PCI_SUBVENDOR_ID_CONNECT_TECH,
1883 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1884 pbn_b1_2_921600 },
1885 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1886 PCI_SUBVENDOR_ID_CONNECT_TECH,
1887 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1888 pbn_b1_8_921600 },
1889 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1890 PCI_SUBVENDOR_ID_CONNECT_TECH,
1891 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1892 pbn_b1_8_921600 },
1893 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1894 PCI_SUBVENDOR_ID_CONNECT_TECH,
1895 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1896 pbn_b1_4_921600 },
1897
1898 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1900 pbn_b2_bt_1_115200 },
1901 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1903 pbn_b2_bt_2_115200 },
1904 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1906 pbn_b2_bt_4_115200 },
1907 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1909 pbn_b2_bt_2_115200 },
1910 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1912 pbn_b2_bt_4_115200 },
1913 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1915 pbn_b2_8_115200 },
1916 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1918 pbn_b2_8_115200 },
1919
1920 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1922 pbn_b2_bt_2_115200 },
1923 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1925 pbn_b2_bt_2_921600 },
1926 /*
1927 * VScom SPCOM800, from sl@s.pl
1928 */
1929 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1931 pbn_b2_8_921600 },
1932 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1934 pbn_b2_4_921600 },
1935 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1936 PCI_SUBVENDOR_ID_KEYSPAN,
1937 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1938 pbn_panacom },
1939 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1941 pbn_panacom4 },
1942 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1944 pbn_panacom2 },
1945 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1946 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1947 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1948 pbn_b2_4_460800 },
1949 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1950 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1951 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1952 pbn_b2_8_460800 },
1953 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1954 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1955 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1956 pbn_b2_16_460800 },
1957 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1958 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1959 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1960 pbn_b2_16_460800 },
1961 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1962 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1963 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1964 pbn_b2_4_460800 },
1965 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1966 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1967 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1968 pbn_b2_8_460800 },
1969 /*
1970 * Megawolf Romulus PCI Serial Card, from Mike Hudson
1971 * (Exoray@isys.ca)
1972 */
1973 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1974 0x10b5, 0x106a, 0, 0,
1975 pbn_plx_romulus },
1976 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1978 pbn_b1_4_115200 },
1979 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1981 pbn_b1_2_115200 },
1982 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1984 pbn_b1_8_115200 },
1985 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1987 pbn_b1_8_115200 },
1988 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1989 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1990 pbn_b0_4_921600 },
fbc0dc0d
AP		 1991 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1992 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
1993 pbn_b0_4_1152000 },
1da177e4
LT		 1994 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1996 pbn_b0_4_115200 },
1997 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1999 pbn_b0_bt_2_921600 },
2000
2001 /*
2002 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2003 * from skokodyn@yahoo.com
2004 */
2005 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2006 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2007 pbn_sbsxrsio },
2008 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2009 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2010 pbn_sbsxrsio },
2011 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2012 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2013 pbn_sbsxrsio },
2014 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2015 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2016 pbn_sbsxrsio },
2017
2018 /*
2019 * Digitan DS560-558, from jimd@esoft.com
2020 */
2021 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2023 pbn_b1_1_115200 },
2024
2025 /*
2026 * Titan Electronic cards
2027 * The 400L and 800L have a custom setup quirk.
2028 */
2029 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2031 pbn_b0_1_921600 },
2032 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2034 pbn_b0_2_921600 },
2035 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2037 pbn_b0_4_921600 },
2038 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2040 pbn_b0_4_921600 },
2041 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2043 pbn_b1_1_921600 },
2044 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2045 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2046 pbn_b1_bt_2_921600 },
2047 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2049 pbn_b0_bt_4_921600 },
2050 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2052 pbn_b0_bt_8_921600 },
2053
2054 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2056 pbn_b2_1_460800 },
2057 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2059 pbn_b2_1_460800 },
2060 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2062 pbn_b2_1_460800 },
2063 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2065 pbn_b2_bt_2_921600 },
2066 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2067 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2068 pbn_b2_bt_2_921600 },
2069 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2071 pbn_b2_bt_2_921600 },
2072 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2074 pbn_b2_bt_4_921600 },
2075 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2077 pbn_b2_bt_4_921600 },
2078 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2080 pbn_b2_bt_4_921600 },
2081 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2083 pbn_b0_1_921600 },
2084 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2086 pbn_b0_1_921600 },
2087 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2089 pbn_b0_1_921600 },
2090 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2092 pbn_b0_bt_2_921600 },
2093 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2095 pbn_b0_bt_2_921600 },
2096 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2098 pbn_b0_bt_2_921600 },
2099 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2101 pbn_b0_bt_4_921600 },
2102 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2104 pbn_b0_bt_4_921600 },
2105 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2107 pbn_b0_bt_4_921600 },
2108
2109 /*
2110 * Computone devices submitted by Doug McNash dmcnash@computone.com
2111 */
2112 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2113 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2114 0, 0, pbn_computone_4 },
2115 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2116 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2117 0, 0, pbn_computone_8 },
2118 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2119 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2120 0, 0, pbn_computone_6 },
2121
2122 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2124 pbn_oxsemi },
2125 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2126 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2127 pbn_b0_bt_1_921600 },
2128
2129 /*
2130 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2131 */
2132 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2134 pbn_b0_bt_8_115200 },
2135 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2137 pbn_b0_bt_8_115200 },
2138
2139 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2141 pbn_b0_bt_2_115200 },
2142 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2144 pbn_b0_bt_2_115200 },
2145 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2147 pbn_b0_bt_2_115200 },
2148 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2150 pbn_b0_bt_4_460800 },
2151 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2153 pbn_b0_bt_4_460800 },
2154 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2156 pbn_b0_bt_2_460800 },
2157 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2159 pbn_b0_bt_2_460800 },
2160 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2162 pbn_b0_bt_2_460800 },
2163 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2165 pbn_b0_bt_1_115200 },
2166 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2168 pbn_b0_bt_1_460800 },
2169
2170 /*
2171 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2172 */
2173 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2175 pbn_b1_1_1382400 },
2176
2177 /*
2178 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2179 */
2180 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2182 pbn_b1_1_1382400 },
2183
2184 /*
2185 * RAStel 2 port modem, gerg@moreton.com.au
2186 */
2187 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2189 pbn_b2_bt_2_115200 },
2190
2191 /*
2192 * EKF addition for i960 Boards form EKF with serial port
2193 */
2194 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2195 0xE4BF, PCI_ANY_ID, 0, 0,
2196 pbn_intel_i960 },
2197
2198 /*
2199 * Xircom Cardbus/Ethernet combos
2200 */
2201 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2203 pbn_b0_1_115200 },
2204 /*
2205 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2206 */
2207 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2209 pbn_b0_1_115200 },
2210
2211 /*
2212 * Untested PCI modems, sent in from various folks...
2213 */
2214
2215 /*
2216 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2217 */
2218 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2219 0x1048, 0x1500, 0, 0,
2220 pbn_b1_1_115200 },
2221
2222 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2223 0xFF00, 0, 0, 0,
2224 pbn_sgi_ioc3 },
2225
2226 /*
2227 * HP Diva card
2228 */
2229 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2230 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2231 pbn_b1_1_115200 },
2232 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2234 pbn_b0_5_115200 },
2235 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2237 pbn_b2_1_115200 },
2238
2239 /*
2240 * NEC Vrc-5074 (Nile 4) builtin UART.
2241 */
2242 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2244 pbn_nec_nile4 },
2245
2246 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2247 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2248 pbn_b3_4_115200 },
2249 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2251 pbn_b3_8_115200 },
2252
2253 /*
2254 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2255 */
2256 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2257 PCI_ANY_ID, PCI_ANY_ID,
2258 0,
2259 0, pbn_exar_XR17C152 },
2260 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2261 PCI_ANY_ID, PCI_ANY_ID,
2262 0,
2263 0, pbn_exar_XR17C154 },
2264 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2265 PCI_ANY_ID, PCI_ANY_ID,
2266 0,
2267 0, pbn_exar_XR17C158 },
2268
2269 /*
2270 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2271 */
2272 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2274 pbn_b0_1_115200 },
2275
2276 /*
2277 * These entries match devices with class COMMUNICATION_SERIAL,
2278 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2279 */
2280 { PCI_ANY_ID, PCI_ANY_ID,
2281 PCI_ANY_ID, PCI_ANY_ID,
2282 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2283 0xffff00, pbn_default },
2284 { PCI_ANY_ID, PCI_ANY_ID,
2285 PCI_ANY_ID, PCI_ANY_ID,
2286 PCI_CLASS_COMMUNICATION_MODEM << 8,
2287 0xffff00, pbn_default },
2288 { PCI_ANY_ID, PCI_ANY_ID,
2289 PCI_ANY_ID, PCI_ANY_ID,
2290 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2291 0xffff00, pbn_default },
2292 { 0, }
2293};
2294
2295static struct pci_driver serial_pci_driver = {
2296 .name = "serial",
2297 .probe = pciserial_init_one,
2298 .remove = __devexit_p(pciserial_remove_one),
2299 .suspend = pciserial_suspend_one,
2300 .resume = pciserial_resume_one,
2301 .id_table = serial_pci_tbl,
2302};
2303
2304static int __init serial8250_pci_init(void)
2305{
2306 return pci_register_driver(&serial_pci_driver);
2307}
2308
2309static void __exit serial8250_pci_exit(void)
2310{
2311 pci_unregister_driver(&serial_pci_driver);
2312}
2313
2314module_init(serial8250_pci_init);
2315module_exit(serial8250_pci_exit);
2316
2317MODULE_LICENSE("GPL");
2318MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2319MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
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