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tty: Fix race in the flush for some ldiscs
[net-next-2.6.git] / drivers / serial / 8250_pci.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
1da177e4
LT		 13 */
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/pci.h>
1da177e4
LT		 17#include <linux/string.h>
18#include <linux/kernel.h>
19#include <linux/slab.h>
20#include <linux/delay.h>
21#include <linux/tty.h>
22#include <linux/serial_core.h>
23#include <linux/8250_pci.h>
24#include <linux/bitops.h>
25
26#include <asm/byteorder.h>
27#include <asm/io.h>
28
29#include "8250.h"
30
31#undef SERIAL_DEBUG_PCI
32
1da177e4
LT		 33/*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
44 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
05caac58 47 struct uart_port *, int);
1da177e4
LT		 48 void (*exit)(struct pci_dev *dev);
49};
50
51#define PCI_NUM_BAR_RESOURCES 6
52
53struct serial_private {
70db3d91 54 struct pci_dev *dev;
1da177e4
LT		 55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59};
60
61static void moan_device(const char *str, struct pci_dev *dev)
62{
63 printk(KERN_WARNING "%s: %s\n"
64 KERN_WARNING "Please send the output of lspci -vv, this\n"
65 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
66 KERN_WARNING "manufacturer and name of serial board or\n"
67 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
68 pci_name(dev), str, dev->vendor, dev->device,
69 dev->subsystem_vendor, dev->subsystem_device);
70}
71
72static int
70db3d91 73setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 74 int bar, int offset, int regshift)
75{
70db3d91 76 struct pci_dev *dev = priv->dev;
1da177e4
LT		 77 unsigned long base, len;
78
79 if (bar >= PCI_NUM_BAR_RESOURCES)
80 return -EINVAL;
81
72ce9a83
RK		 82 base = pci_resource_start(dev, bar);
83
1da177e4 84 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 85 len = pci_resource_len(dev, bar);
86
87 if (!priv->remapped_bar[bar])
6f441fe9 88 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 89 if (!priv->remapped_bar[bar])
90 return -ENOMEM;
91
92 port->iotype = UPIO_MEM;
72ce9a83 93 port->iobase = 0;
1da177e4
LT		 94 port->mapbase = base + offset;
95 port->membase = priv->remapped_bar[bar] + offset;
96 port->regshift = regshift;
97 } else {
1da177e4 98 port->iotype = UPIO_PORT;
72ce9a83
RK		 99 port->iobase = base + offset;
100 port->mapbase = 0;
101 port->membase = NULL;
102 port->regshift = 0;
1da177e4
LT		 103 }
104 return 0;
105}
106
02c9b5cf
KJ		 107/*
108 * ADDI-DATA GmbH communication cards <info@addi-data.com>
109 */
110static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 111 const struct pciserial_board *board,
02c9b5cf
KJ		 112 struct uart_port *port, int idx)
113{
114 unsigned int bar = 0, offset = board->first_offset;
115 bar = FL_GET_BASE(board->flags);
116
117 if (idx < 2) {
118 offset += idx * board->uart_offset;
119 } else if ((idx >= 2) && (idx < 4)) {
120 bar += 1;
121 offset += ((idx - 2) * board->uart_offset);
122 } else if ((idx >= 4) && (idx < 6)) {
123 bar += 2;
124 offset += ((idx - 4) * board->uart_offset);
125 } else if (idx >= 6) {
126 bar += 3;
127 offset += ((idx - 6) * board->uart_offset);
128 }
129
130 return setup_port(priv, port, bar, offset, board->reg_shift);
131}
132
1da177e4
LT		 133/*
134 * AFAVLAB uses a different mixture of BARs and offsets
135 * Not that ugly ;) -- HW
136 */
137static int
975a1a7d 138afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 139 struct uart_port *port, int idx)
140{
141 unsigned int bar, offset = board->first_offset;
5756ee99 142
1da177e4
LT		 143 bar = FL_GET_BASE(board->flags);
144 if (idx < 4)
145 bar += idx;
146 else {
147 bar = 4;
148 offset += (idx - 4) * board->uart_offset;
149 }
150
70db3d91 151 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 152}
153
154/*
155 * HP's Remote Management Console. The Diva chip came in several
156 * different versions. N-class, L2000 and A500 have two Diva chips, each
157 * with 3 UARTs (the third UART on the second chip is unused). Superdome
158 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
159 * one Diva chip, but it has been expanded to 5 UARTs.
160 */
61a116ef 161static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 162{
163 int rc = 0;
164
165 switch (dev->subsystem_device) {
166 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
167 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
168 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
169 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
170 rc = 3;
171 break;
172 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
173 rc = 2;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
176 rc = 4;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 179 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 180 rc = 1;
181 break;
182 }
183
184 return rc;
185}
186
187/*
188 * HP's Diva chip puts the 4th/5th serial port further out, and
189 * some serial ports are supposed to be hidden on certain models.
190 */
191static int
975a1a7d
RK		 192pci_hp_diva_setup(struct serial_private *priv,
193 const struct pciserial_board *board,
194 struct uart_port *port, int idx)
1da177e4
LT		 195{
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
198
70db3d91 199 switch (priv->dev->subsystem_device) {
1da177e4
LT		 200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
201 if (idx == 3)
202 idx++;
203 break;
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
205 if (idx > 0)
206 idx++;
207 if (idx > 2)
208 idx++;
209 break;
210 }
211 if (idx > 2)
212 offset = 0x18;
213
214 offset += idx * board->uart_offset;
215
70db3d91 216 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 217}
218
219/*
220 * Added for EKF Intel i960 serial boards
221 */
61a116ef 222static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 223{
224 unsigned long oldval;
225
226 if (!(dev->subsystem_device & 0x1000))
227 return -ENODEV;
228
229 /* is firmware started? */
5756ee99
AC		 230 pci_read_config_dword(dev, 0x44, (void *)&oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
1da177e4
LT		 232 printk(KERN_DEBUG "Local i960 firmware missing");
233 return -ENODEV;
234 }
235 return 0;
236}
237
238/*
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
242 * mapped memory.
243 */
61a116ef 244static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 245{
246 u8 irq_config;
247 void __iomem *p;
248
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
251 return 0;
252 }
253
254 irq_config = 0x41;
add7b58e 255 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 257 irq_config = 0x43;
5756ee99 258
1da177e4 259 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 261 /*
262 * As the megawolf cards have the int pins active
263 * high, and have 2 UART chips, both ints must be
264 * enabled on the 9050. Also, the UARTS are set in
265 * 16450 mode by default, so we have to enable the
266 * 16C950 'enhanced' mode so that we can use the
267 * deep FIFOs
268 */
269 irq_config = 0x5b;
1da177e4
LT		 270 /*
271 * enable/disable interrupts
272 */
6f441fe9 273 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 274 if (p == NULL)
275 return -ENOMEM;
276 writel(irq_config, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283
284 return 0;
285}
286
287static void __devexit pci_plx9050_exit(struct pci_dev *dev)
288{
289 u8 __iomem *p;
290
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292 return;
293
294 /*
295 * disable interrupts
296 */
6f441fe9 297 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 298 if (p != NULL) {
299 writel(0, p + 0x4c);
300
301 /*
302 * Read the register back to ensure that it took effect.
303 */
304 readl(p + 0x4c);
305 iounmap(p);
306 }
307}
308
309/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
310static int
975a1a7d 311sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 312 struct uart_port *port, int idx)
313{
314 unsigned int bar, offset = board->first_offset;
315
316 bar = 0;
317
318 if (idx < 4) {
319 /* first four channels map to 0, 0x100, 0x200, 0x300 */
320 offset += idx * board->uart_offset;
321 } else if (idx < 8) {
322 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
323 offset += idx * board->uart_offset + 0xC00;
324 } else /* we have only 8 ports on PMC-OCTALPRO */
325 return 1;
326
70db3d91 327 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 328}
329
330/*
331* This does initialization for PMC OCTALPRO cards:
332* maps the device memory, resets the UARTs (needed, bc
333* if the module is removed and inserted again, the card
334* is in the sleep mode) and enables global interrupt.
335*/
336
337/* global control register offset for SBS PMC-OctalPro */
338#define OCT_REG_CR_OFF 0x500
339
61a116ef 340static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 341{
342 u8 __iomem *p;
343
6f441fe9
AC		 344 p = ioremap_nocache(pci_resource_start(dev, 0),
345 pci_resource_len(dev, 0));
1da177e4
LT		 346
347 if (p == NULL)
348 return -ENOMEM;
349 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 350 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 351 udelay(50);
5756ee99 352 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 353
354 /* Set bit-2 (INTENABLE) of Control Register */
355 writeb(0x4, p + OCT_REG_CR_OFF);
356 iounmap(p);
357
358 return 0;
359}
360
361/*
362 * Disables the global interrupt of PMC-OctalPro
363 */
364
365static void __devexit sbs_exit(struct pci_dev *dev)
366{
367 u8 __iomem *p;
368
6f441fe9
AC		 369 p = ioremap_nocache(pci_resource_start(dev, 0),
370 pci_resource_len(dev, 0));
5756ee99
AC		 371 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
372 if (p != NULL)
1da177e4 373 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 374 iounmap(p);
375}
376
377/*
378 * SIIG serial cards have an PCI interface chip which also controls
379 * the UART clocking frequency. Each UART can be clocked independently
380 * (except cards equiped with 4 UARTs) and initial clocking settings
381 * are stored in the EEPROM chip. It can cause problems because this
382 * version of serial driver doesn't support differently clocked UART's
383 * on single PCI card. To prevent this, initialization functions set
384 * high frequency clocking for all UART's on given card. It is safe (I
385 * hope) because it doesn't touch EEPROM settings to prevent conflicts
386 * with other OSes (like M$ DOS).
387 *
388 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 389 *
1da177e4
LT		 390 * There is two family of SIIG serial cards with different PCI
391 * interface chip and different configuration methods:
392 * - 10x cards have control registers in IO and/or memory space;
393 * - 20x cards have control registers in standard PCI configuration space.
394 *
67d74b87
RK		 395 * Note: all 10x cards have PCI device ids 0x10..
396 * all 20x cards have PCI device ids 0x20..
397 *
fbc0dc0d
AP		 398 * There are also Quartet Serial cards which use Oxford Semiconductor
399 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
400 *
1da177e4
LT		 401 * Note: some SIIG cards are probed by the parport_serial object.
402 */
403
404#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
405#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
406
407static int pci_siig10x_init(struct pci_dev *dev)
408{
409 u16 data;
410 void __iomem *p;
411
412 switch (dev->device & 0xfff8) {
413 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
414 data = 0xffdf;
415 break;
416 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
417 data = 0xf7ff;
418 break;
419 default: /* 1S1P, 4S */
420 data = 0xfffb;
421 break;
422 }
423
6f441fe9 424 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 425 if (p == NULL)
426 return -ENOMEM;
427
428 writew(readw(p + 0x28) & data, p + 0x28);
429 readw(p + 0x28);
430 iounmap(p);
431 return 0;
432}
433
434#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
435#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
436
437static int pci_siig20x_init(struct pci_dev *dev)
438{
439 u8 data;
440
441 /* Change clock frequency for the first UART. */
442 pci_read_config_byte(dev, 0x6f, &data);
443 pci_write_config_byte(dev, 0x6f, data & 0xef);
444
445 /* If this card has 2 UART, we have to do the same with second UART. */
446 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
447 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
448 pci_read_config_byte(dev, 0x73, &data);
449 pci_write_config_byte(dev, 0x73, data & 0xef);
450 }
451 return 0;
452}
453
67d74b87
RK		 454static int pci_siig_init(struct pci_dev *dev)
455{
456 unsigned int type = dev->device & 0xff00;
457
458 if (type == 0x1000)
459 return pci_siig10x_init(dev);
460 else if (type == 0x2000)
461 return pci_siig20x_init(dev);
462
463 moan_device("Unknown SIIG card", dev);
464 return -ENODEV;
465}
466
3ec9c594 467static int pci_siig_setup(struct serial_private *priv,
975a1a7d 468 const struct pciserial_board *board,
3ec9c594
AP		 469 struct uart_port *port, int idx)
470{
471 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
472
473 if (idx > 3) {
474 bar = 4;
475 offset = (idx - 4) * 8;
476 }
477
478 return setup_port(priv, port, bar, offset, 0);
479}
480
1da177e4
LT		 481/*
482 * Timedia has an explosion of boards, and to avoid the PCI table from
483 * growing *huge*, we use this function to collapse some 70 entries
484 * in the PCI table into one, for sanity's and compactness's sake.
485 */
e9422e09 486static const unsigned short timedia_single_port[] = {
1da177e4
LT		 487 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
488};
489
e9422e09 490static const unsigned short timedia_dual_port[] = {
1da177e4 491 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 492 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
493 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 494 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
495 0xD079, 0
496};
497
e9422e09 498static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 499 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
500 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 501 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
502 0xB157, 0
503};
504
e9422e09 505static const unsigned short timedia_eight_port[] = {
5756ee99 506 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 507 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
508};
509
cb3592be 510static const struct timedia_struct {
1da177e4 511 int num;
e9422e09 512 const unsigned short *ids;
1da177e4
LT		 513} timedia_data[] = {
514 { 1, timedia_single_port },
515 { 2, timedia_dual_port },
516 { 4, timedia_quad_port },
e9422e09 517 { 8, timedia_eight_port }
1da177e4
LT		 518};
519
61a116ef 520static int pci_timedia_init(struct pci_dev *dev)
1da177e4 521{
e9422e09 522 const unsigned short *ids;
1da177e4
LT		 523 int i, j;
524
e9422e09 525 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 526 ids = timedia_data[i].ids;
527 for (j = 0; ids[j]; j++)
528 if (dev->subsystem_device == ids[j])
529 return timedia_data[i].num;
530 }
531 return 0;
532}
533
534/*
535 * Timedia/SUNIX uses a mixture of BARs and offsets
536 * Ugh, this is ugly as all hell --- TYT
537 */
538static int
975a1a7d
RK		 539pci_timedia_setup(struct serial_private *priv,
540 const struct pciserial_board *board,
1da177e4
LT		 541 struct uart_port *port, int idx)
542{
543 unsigned int bar = 0, offset = board->first_offset;
544
545 switch (idx) {
546 case 0:
547 bar = 0;
548 break;
549 case 1:
550 offset = board->uart_offset;
551 bar = 0;
552 break;
553 case 2:
554 bar = 1;
555 break;
556 case 3:
557 offset = board->uart_offset;
c2cd6d3c 558 /* FALLTHROUGH */
1da177e4
LT		 559 case 4: /* BAR 2 */
560 case 5: /* BAR 3 */
561 case 6: /* BAR 4 */
562 case 7: /* BAR 5 */
563 bar = idx - 2;
564 }
565
70db3d91 566 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 567}
568
569/*
570 * Some Titan cards are also a little weird
571 */
572static int
70db3d91 573titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 574 const struct pciserial_board *board,
1da177e4
LT		 575 struct uart_port *port, int idx)
576{
577 unsigned int bar, offset = board->first_offset;
578
579 switch (idx) {
580 case 0:
581 bar = 1;
582 break;
583 case 1:
584 bar = 2;
585 break;
586 default:
587 bar = 4;
588 offset = (idx - 2) * board->uart_offset;
589 }
590
70db3d91 591 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 592}
593
61a116ef 594static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 595{
596 msleep(100);
597 return 0;
598}
599
61a116ef 600static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 601{
602 /* subdevice 0x00PS means <P> parallel, <S> serial */
603 unsigned int num_serial = dev->subsystem_device & 0xf;
604
605 if (num_serial == 0)
606 return -ENODEV;
607 return num_serial;
608}
609
84f8c6fc
NV		 610/*
611 * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
612 *
613 * These chips are available with optionally one parallel port and up to
614 * two serial ports. Unfortunately they all have the same product id.
615 *
616 * Basic configuration is done over a region of 32 I/O ports. The base
617 * ioport is called INTA or INTC, depending on docs/other drivers.
618 *
619 * The region of the 32 I/O ports is configured in POSIO0R...
620 */
621
622/* registers */
623#define ITE_887x_MISCR 0x9c
624#define ITE_887x_INTCBAR 0x78
625#define ITE_887x_UARTBAR 0x7c
626#define ITE_887x_PS0BAR 0x10
627#define ITE_887x_POSIO0 0x60
628
629/* I/O space size */
630#define ITE_887x_IOSIZE 32
631/* I/O space size (bits 26-24; 8 bytes = 011b) */
632#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
633/* I/O space size (bits 26-24; 32 bytes = 101b) */
634#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
635/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
636#define ITE_887x_POSIO_SPEED (3 << 29)
637/* enable IO_Space bit */
638#define ITE_887x_POSIO_ENABLE (1 << 31)
639
f79abb82 640static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 641{
642 /* inta_addr are the configuration addresses of the ITE */
643 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
644 0x200, 0x280, 0 };
645 int ret, i, type;
646 struct resource *iobase = NULL;
647 u32 miscr, uartbar, ioport;
648
649 /* search for the base-ioport */
650 i = 0;
651 while (inta_addr[i] && iobase == NULL) {
652 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
653 "ite887x");
654 if (iobase != NULL) {
655 /* write POSIO0R - speed | size | ioport */
656 pci_write_config_dword(dev, ITE_887x_POSIO0,
657 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
658 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
659 /* write INTCBAR - ioport */
5756ee99
AC		 660 pci_write_config_dword(dev, ITE_887x_INTCBAR,
661 inta_addr[i]);
84f8c6fc
NV		 662 ret = inb(inta_addr[i]);
663 if (ret != 0xff) {
664 /* ioport connected */
665 break;
666 }
667 release_region(iobase->start, ITE_887x_IOSIZE);
668 iobase = NULL;
669 }
670 i++;
671 }
672
673 if (!inta_addr[i]) {
674 printk(KERN_ERR "ite887x: could not find iobase\n");
675 return -ENODEV;
676 }
677
678 /* start of undocumented type checking (see parport_pc.c) */
679 type = inb(iobase->start + 0x18) & 0x0f;
680
681 switch (type) {
682 case 0x2: /* ITE8871 (1P) */
683 case 0xa: /* ITE8875 (1P) */
684 ret = 0;
685 break;
686 case 0xe: /* ITE8872 (2S1P) */
687 ret = 2;
688 break;
689 case 0x6: /* ITE8873 (1S) */
690 ret = 1;
691 break;
692 case 0x8: /* ITE8874 (2S) */
693 ret = 2;
694 break;
695 default:
696 moan_device("Unknown ITE887x", dev);
697 ret = -ENODEV;
698 }
699
700 /* configure all serial ports */
701 for (i = 0; i < ret; i++) {
702 /* read the I/O port from the device */
703 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
704 &ioport);
705 ioport &= 0x0000FF00; /* the actual base address */
706 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
707 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
708 ITE_887x_POSIO_IOSIZE_8 | ioport);
709
710 /* write the ioport to the UARTBAR */
711 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
712 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
713 uartbar |= (ioport << (16 * i)); /* set the ioport */
714 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
715
716 /* get current config */
717 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
718 /* disable interrupts (UARTx_Routing[3:0]) */
719 miscr &= ~(0xf << (12 - 4 * i));
720 /* activate the UART (UARTx_En) */
721 miscr |= 1 << (23 - i);
722 /* write new config with activated UART */
723 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
724 }
725
726 if (ret <= 0) {
727 /* the device has no UARTs if we get here */
728 release_region(iobase->start, ITE_887x_IOSIZE);
729 }
730
731 return ret;
732}
733
734static void __devexit pci_ite887x_exit(struct pci_dev *dev)
735{
736 u32 ioport;
737 /* the ioport is bit 0-15 in POSIO0R */
738 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
739 ioport &= 0xffff;
740 release_region(ioport, ITE_887x_IOSIZE);
741}
742
9f2a036a
RK		 743/*
744 * Oxford Semiconductor Inc.
745 * Check that device is part of the Tornado range of devices, then determine
746 * the number of ports available on the device.
747 */
748static int pci_oxsemi_tornado_init(struct pci_dev *dev)
749{
750 u8 __iomem *p;
751 unsigned long deviceID;
752 unsigned int number_uarts = 0;
753
754 /* OxSemi Tornado devices are all 0xCxxx */
755 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
756 (dev->device & 0xF000) != 0xC000)
757 return 0;
758
759 p = pci_iomap(dev, 0, 5);
760 if (p == NULL)
761 return -ENOMEM;
762
763 deviceID = ioread32(p);
764 /* Tornado device */
765 if (deviceID == 0x07000200) {
766 number_uarts = ioread8(p + 4);
767 printk(KERN_DEBUG
768 "%d ports detected on Oxford PCI Express device\n",
769 number_uarts);
770 }
771 pci_iounmap(dev, p);
772 return number_uarts;
773}
774
1da177e4 775static int
975a1a7d
RK		 776pci_default_setup(struct serial_private *priv,
777 const struct pciserial_board *board,
1da177e4
LT		 778 struct uart_port *port, int idx)
779{
780 unsigned int bar, offset = board->first_offset, maxnr;
781
782 bar = FL_GET_BASE(board->flags);
783 if (board->flags & FL_BASE_BARS)
784 bar += idx;
785 else
786 offset += idx * board->uart_offset;
787
2427ddd8
GKH		 788 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
789 (board->reg_shift + 3);
1da177e4
LT		 790
791 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
792 return 1;
5756ee99 793
70db3d91 794 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 795}
796
797/* This should be in linux/pci_ids.h */
798#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
799#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
800#define PCI_DEVICE_ID_OCTPRO 0x0001
801#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
802#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
803#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
804#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
805
b76c5a07
CB		 806/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
807#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
808
1da177e4
LT		 809/*
810 * Master list of serial port init/setup/exit quirks.
811 * This does not describe the general nature of the port.
812 * (ie, baud base, number and location of ports, etc)
813 *
814 * This list is ordered alphabetically by vendor then device.
815 * Specific entries must come before more generic entries.
816 */
7a63ce5a 817static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 818 /*
819 * ADDI-DATA GmbH communication cards <info@addi-data.com>
820 */
821 {
822 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
823 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
824 .subvendor = PCI_ANY_ID,
825 .subdevice = PCI_ANY_ID,
826 .setup = addidata_apci7800_setup,
827 },
1da177e4 828 /*
61a116ef 829 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 830 * It is not clear whether this applies to all products.
831 */
832 {
833 .vendor = PCI_VENDOR_ID_AFAVLAB,
834 .device = PCI_ANY_ID,
835 .subvendor = PCI_ANY_ID,
836 .subdevice = PCI_ANY_ID,
837 .setup = afavlab_setup,
838 },
839 /*
840 * HP Diva
841 */
842 {
843 .vendor = PCI_VENDOR_ID_HP,
844 .device = PCI_DEVICE_ID_HP_DIVA,
845 .subvendor = PCI_ANY_ID,
846 .subdevice = PCI_ANY_ID,
847 .init = pci_hp_diva_init,
848 .setup = pci_hp_diva_setup,
849 },
850 /*
851 * Intel
852 */
853 {
854 .vendor = PCI_VENDOR_ID_INTEL,
855 .device = PCI_DEVICE_ID_INTEL_80960_RP,
856 .subvendor = 0xe4bf,
857 .subdevice = PCI_ANY_ID,
858 .init = pci_inteli960ni_init,
859 .setup = pci_default_setup,
860 },
84f8c6fc
NV		 861 /*
862 * ITE
863 */
864 {
865 .vendor = PCI_VENDOR_ID_ITE,
866 .device = PCI_DEVICE_ID_ITE_8872,
867 .subvendor = PCI_ANY_ID,
868 .subdevice = PCI_ANY_ID,
869 .init = pci_ite887x_init,
870 .setup = pci_default_setup,
871 .exit = __devexit_p(pci_ite887x_exit),
872 },
1da177e4
LT		 873 /*
874 * Panacom
875 */
876 {
877 .vendor = PCI_VENDOR_ID_PANACOM,
878 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
879 .subvendor = PCI_ANY_ID,
880 .subdevice = PCI_ANY_ID,
881 .init = pci_plx9050_init,
882 .setup = pci_default_setup,
883 .exit = __devexit_p(pci_plx9050_exit),
5756ee99 884 },
1da177e4
LT		 885 {
886 .vendor = PCI_VENDOR_ID_PANACOM,
887 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
888 .subvendor = PCI_ANY_ID,
889 .subdevice = PCI_ANY_ID,
890 .init = pci_plx9050_init,
891 .setup = pci_default_setup,
892 .exit = __devexit_p(pci_plx9050_exit),
893 },
894 /*
895 * PLX
896 */
48212008
TH		 897 {
898 .vendor = PCI_VENDOR_ID_PLX,
899 .device = PCI_DEVICE_ID_PLX_9030,
900 .subvendor = PCI_SUBVENDOR_ID_PERLE,
901 .subdevice = PCI_ANY_ID,
902 .setup = pci_default_setup,
903 },
add7b58e
BH		 904 {
905 .vendor = PCI_VENDOR_ID_PLX,
906 .device = PCI_DEVICE_ID_PLX_9050,
907 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
908 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
909 .init = pci_plx9050_init,
910 .setup = pci_default_setup,
911 .exit = __devexit_p(pci_plx9050_exit),
912 },
1da177e4
LT		 913 {
914 .vendor = PCI_VENDOR_ID_PLX,
915 .device = PCI_DEVICE_ID_PLX_9050,
916 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
917 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
918 .init = pci_plx9050_init,
919 .setup = pci_default_setup,
920 .exit = __devexit_p(pci_plx9050_exit),
921 },
b76c5a07
CB		 922 {
923 .vendor = PCI_VENDOR_ID_PLX,
924 .device = PCI_DEVICE_ID_PLX_9050,
925 .subvendor = PCI_VENDOR_ID_PLX,
926 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
927 .init = pci_plx9050_init,
928 .setup = pci_default_setup,
929 .exit = __devexit_p(pci_plx9050_exit),
930 },
1da177e4
LT		 931 {
932 .vendor = PCI_VENDOR_ID_PLX,
933 .device = PCI_DEVICE_ID_PLX_ROMULUS,
934 .subvendor = PCI_VENDOR_ID_PLX,
935 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
936 .init = pci_plx9050_init,
937 .setup = pci_default_setup,
938 .exit = __devexit_p(pci_plx9050_exit),
939 },
940 /*
941 * SBS Technologies, Inc., PMC-OCTALPRO 232
942 */
943 {
944 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
945 .device = PCI_DEVICE_ID_OCTPRO,
946 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
947 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
948 .init = sbs_init,
949 .setup = sbs_setup,
950 .exit = __devexit_p(sbs_exit),
951 },
952 /*
953 * SBS Technologies, Inc., PMC-OCTALPRO 422
954 */
955 {
956 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
957 .device = PCI_DEVICE_ID_OCTPRO,
958 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
959 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
960 .init = sbs_init,
961 .setup = sbs_setup,
962 .exit = __devexit_p(sbs_exit),
963 },
964 /*
965 * SBS Technologies, Inc., P-Octal 232
966 */
967 {
968 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
969 .device = PCI_DEVICE_ID_OCTPRO,
970 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
971 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
972 .init = sbs_init,
973 .setup = sbs_setup,
974 .exit = __devexit_p(sbs_exit),
975 },
976 /*
977 * SBS Technologies, Inc., P-Octal 422
978 */
979 {
980 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
981 .device = PCI_DEVICE_ID_OCTPRO,
982 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
983 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
984 .init = sbs_init,
985 .setup = sbs_setup,
986 .exit = __devexit_p(sbs_exit),
987 },
1da177e4 988 /*
61a116ef 989 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 990 */
991 {
992 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 993 .device = PCI_ANY_ID,
1da177e4
LT		 994 .subvendor = PCI_ANY_ID,
995 .subdevice = PCI_ANY_ID,
67d74b87 996 .init = pci_siig_init,
3ec9c594 997 .setup = pci_siig_setup,
1da177e4
LT		 998 },
999 /*
1000 * Titan cards
1001 */
1002 {
1003 .vendor = PCI_VENDOR_ID_TITAN,
1004 .device = PCI_DEVICE_ID_TITAN_400L,
1005 .subvendor = PCI_ANY_ID,
1006 .subdevice = PCI_ANY_ID,
1007 .setup = titan_400l_800l_setup,
1008 },
1009 {
1010 .vendor = PCI_VENDOR_ID_TITAN,
1011 .device = PCI_DEVICE_ID_TITAN_800L,
1012 .subvendor = PCI_ANY_ID,
1013 .subdevice = PCI_ANY_ID,
1014 .setup = titan_400l_800l_setup,
1015 },
1016 /*
1017 * Timedia cards
1018 */
1019 {
1020 .vendor = PCI_VENDOR_ID_TIMEDIA,
1021 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1022 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1023 .subdevice = PCI_ANY_ID,
1024 .init = pci_timedia_init,
1025 .setup = pci_timedia_setup,
1026 },
1027 {
1028 .vendor = PCI_VENDOR_ID_TIMEDIA,
1029 .device = PCI_ANY_ID,
1030 .subvendor = PCI_ANY_ID,
1031 .subdevice = PCI_ANY_ID,
1032 .setup = pci_timedia_setup,
1033 },
1034 /*
1035 * Xircom cards
1036 */
1037 {
1038 .vendor = PCI_VENDOR_ID_XIRCOM,
1039 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1040 .subvendor = PCI_ANY_ID,
1041 .subdevice = PCI_ANY_ID,
1042 .init = pci_xircom_init,
1043 .setup = pci_default_setup,
1044 },
1045 /*
61a116ef 1046 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 1047 */
1048 {
1049 .vendor = PCI_VENDOR_ID_NETMOS,
1050 .device = PCI_ANY_ID,
1051 .subvendor = PCI_ANY_ID,
1052 .subdevice = PCI_ANY_ID,
1053 .init = pci_netmos_init,
1054 .setup = pci_default_setup,
1055 },
9f2a036a
RK		 1056 /*
1057 * For Oxford Semiconductor and Mainpine
1058 */
1059 {
1060 .vendor = PCI_VENDOR_ID_OXSEMI,
1061 .device = PCI_ANY_ID,
1062 .subvendor = PCI_ANY_ID,
1063 .subdevice = PCI_ANY_ID,
1064 .init = pci_oxsemi_tornado_init,
1065 .setup = pci_default_setup,
1066 },
1067 {
1068 .vendor = PCI_VENDOR_ID_MAINPINE,
1069 .device = PCI_ANY_ID,
1070 .subvendor = PCI_ANY_ID,
1071 .subdevice = PCI_ANY_ID,
1072 .init = pci_oxsemi_tornado_init,
1073 .setup = pci_default_setup,
1074 },
1da177e4
LT		 1075 /*
1076 * Default "match everything" terminator entry
1077 */
1078 {
1079 .vendor = PCI_ANY_ID,
1080 .device = PCI_ANY_ID,
1081 .subvendor = PCI_ANY_ID,
1082 .subdevice = PCI_ANY_ID,
1083 .setup = pci_default_setup,
1084 }
1085};
1086
1087static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1088{
1089 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1090}
1091
1092static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1093{
1094 struct pci_serial_quirk *quirk;
1095
1096 for (quirk = pci_serial_quirks; ; quirk++)
1097 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1098 quirk_id_matches(quirk->device, dev->device) &&
1099 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1100 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 1101 break;
1da177e4
LT		 1102 return quirk;
1103}
1104
dd68e88c 1105static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 1106 const struct pciserial_board *board)
1da177e4
LT		 1107{
1108 if (board->flags & FL_NOIRQ)
1109 return 0;
1110 else
1111 return dev->irq;
1112}
1113
1114/*
1115 * This is the configuration table for all of the PCI serial boards
1116 * which we support. It is directly indexed by the pci_board_num_t enum
1117 * value, which is encoded in the pci_device_id PCI probe table's
1118 * driver_data member.
1119 *
1120 * The makeup of these names are:
26e92861 1121 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 1122 *
26e92861
GH		 1123 * bn = PCI BAR number
1124 * bt = Index using PCI BARs
1125 * n = number of serial ports
1126 * baud = baud rate
1127 * offsetinhex = offset for each sequential port (in hex)
1da177e4 1128 *
26e92861 1129 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 1130 *
1da177e4
LT		 1131 * Please note: in theory if n = 1, _bt infix should make no difference.
1132 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1133 */
1134enum pci_board_num_t {
1135 pbn_default = 0,
1136
1137 pbn_b0_1_115200,
1138 pbn_b0_2_115200,
1139 pbn_b0_4_115200,
1140 pbn_b0_5_115200,
bf0df636 1141 pbn_b0_8_115200,
1da177e4
LT		 1142
1143 pbn_b0_1_921600,
1144 pbn_b0_2_921600,
1145 pbn_b0_4_921600,
1146
db1de159
DR		 1147 pbn_b0_2_1130000,
1148
fbc0dc0d
AP		 1149 pbn_b0_4_1152000,
1150
26e92861
GH		 1151 pbn_b0_2_1843200,
1152 pbn_b0_4_1843200,
1153
1154 pbn_b0_2_1843200_200,
1155 pbn_b0_4_1843200_200,
1156 pbn_b0_8_1843200_200,
1157
7106b4e3
LH		 1158 pbn_b0_1_4000000,
1159
1da177e4
LT		 1160 pbn_b0_bt_1_115200,
1161 pbn_b0_bt_2_115200,
1162 pbn_b0_bt_8_115200,
1163
1164 pbn_b0_bt_1_460800,
1165 pbn_b0_bt_2_460800,
1166 pbn_b0_bt_4_460800,
1167
1168 pbn_b0_bt_1_921600,
1169 pbn_b0_bt_2_921600,
1170 pbn_b0_bt_4_921600,
1171 pbn_b0_bt_8_921600,
1172
1173 pbn_b1_1_115200,
1174 pbn_b1_2_115200,
1175 pbn_b1_4_115200,
1176 pbn_b1_8_115200,
1177
1178 pbn_b1_1_921600,
1179 pbn_b1_2_921600,
1180 pbn_b1_4_921600,
1181 pbn_b1_8_921600,
1182
26e92861
GH		 1183 pbn_b1_2_1250000,
1184
84f8c6fc 1185 pbn_b1_bt_1_115200,
1da177e4
LT		 1186 pbn_b1_bt_2_921600,
1187
1188 pbn_b1_1_1382400,
1189 pbn_b1_2_1382400,
1190 pbn_b1_4_1382400,
1191 pbn_b1_8_1382400,
1192
1193 pbn_b2_1_115200,
737c1756 1194 pbn_b2_2_115200,
a9cccd34 1195 pbn_b2_4_115200,
1da177e4
LT		 1196 pbn_b2_8_115200,
1197
1198 pbn_b2_1_460800,
1199 pbn_b2_4_460800,
1200 pbn_b2_8_460800,
1201 pbn_b2_16_460800,
1202
1203 pbn_b2_1_921600,
1204 pbn_b2_4_921600,
1205 pbn_b2_8_921600,
1206
1207 pbn_b2_bt_1_115200,
1208 pbn_b2_bt_2_115200,
1209 pbn_b2_bt_4_115200,
1210
1211 pbn_b2_bt_2_921600,
1212 pbn_b2_bt_4_921600,
1213
d9004eb4 1214 pbn_b3_2_115200,
1da177e4
LT		 1215 pbn_b3_4_115200,
1216 pbn_b3_8_115200,
1217
1218 /*
1219 * Board-specific versions.
1220 */
1221 pbn_panacom,
1222 pbn_panacom2,
1223 pbn_panacom4,
add7b58e 1224 pbn_exsys_4055,
1da177e4
LT		 1225 pbn_plx_romulus,
1226 pbn_oxsemi,
7106b4e3
LH		 1227 pbn_oxsemi_1_4000000,
1228 pbn_oxsemi_2_4000000,
1229 pbn_oxsemi_4_4000000,
1230 pbn_oxsemi_8_4000000,
1da177e4
LT		 1231 pbn_intel_i960,
1232 pbn_sgi_ioc3,
1da177e4
LT		 1233 pbn_computone_4,
1234 pbn_computone_6,
1235 pbn_computone_8,
1236 pbn_sbsxrsio,
1237 pbn_exar_XR17C152,
1238 pbn_exar_XR17C154,
1239 pbn_exar_XR17C158,
aa798505 1240 pbn_pasemi_1682M,
1da177e4
LT		 1241};
1242
1243/*
1244 * uart_offset - the space between channels
1245 * reg_shift - describes how the UART registers are mapped
1246 * to PCI memory by the card.
1247 * For example IER register on SBS, Inc. PMC-OctPro is located at
1248 * offset 0x10 from the UART base, while UART_IER is defined as 1
1249 * in include/linux/serial_reg.h,
1250 * see first lines of serial_in() and serial_out() in 8250.c
1251*/
1252
1c7c1fe5 1253static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 1254 [pbn_default] = {
1255 .flags = FL_BASE0,
1256 .num_ports = 1,
1257 .base_baud = 115200,
1258 .uart_offset = 8,
1259 },
1260 [pbn_b0_1_115200] = {
1261 .flags = FL_BASE0,
1262 .num_ports = 1,
1263 .base_baud = 115200,
1264 .uart_offset = 8,
1265 },
1266 [pbn_b0_2_115200] = {
1267 .flags = FL_BASE0,
1268 .num_ports = 2,
1269 .base_baud = 115200,
1270 .uart_offset = 8,
1271 },
1272 [pbn_b0_4_115200] = {
1273 .flags = FL_BASE0,
1274 .num_ports = 4,
1275 .base_baud = 115200,
1276 .uart_offset = 8,
1277 },
1278 [pbn_b0_5_115200] = {
1279 .flags = FL_BASE0,
1280 .num_ports = 5,
1281 .base_baud = 115200,
1282 .uart_offset = 8,
1283 },
bf0df636
AC		 1284 [pbn_b0_8_115200] = {
1285 .flags = FL_BASE0,
1286 .num_ports = 8,
1287 .base_baud = 115200,
1288 .uart_offset = 8,
1289 },
1da177e4
LT		 1290 [pbn_b0_1_921600] = {
1291 .flags = FL_BASE0,
1292 .num_ports = 1,
1293 .base_baud = 921600,
1294 .uart_offset = 8,
1295 },
1296 [pbn_b0_2_921600] = {
1297 .flags = FL_BASE0,
1298 .num_ports = 2,
1299 .base_baud = 921600,
1300 .uart_offset = 8,
1301 },
1302 [pbn_b0_4_921600] = {
1303 .flags = FL_BASE0,
1304 .num_ports = 4,
1305 .base_baud = 921600,
1306 .uart_offset = 8,
1307 },
db1de159
DR		 1308
1309 [pbn_b0_2_1130000] = {
1310 .flags = FL_BASE0,
1311 .num_ports = 2,
1312 .base_baud = 1130000,
1313 .uart_offset = 8,
1314 },
1315
fbc0dc0d
AP		 1316 [pbn_b0_4_1152000] = {
1317 .flags = FL_BASE0,
1318 .num_ports = 4,
1319 .base_baud = 1152000,
1320 .uart_offset = 8,
1321 },
1da177e4 1322
26e92861
GH		 1323 [pbn_b0_2_1843200] = {
1324 .flags = FL_BASE0,
1325 .num_ports = 2,
1326 .base_baud = 1843200,
1327 .uart_offset = 8,
1328 },
1329 [pbn_b0_4_1843200] = {
1330 .flags = FL_BASE0,
1331 .num_ports = 4,
1332 .base_baud = 1843200,
1333 .uart_offset = 8,
1334 },
1335
1336 [pbn_b0_2_1843200_200] = {
1337 .flags = FL_BASE0,
1338 .num_ports = 2,
1339 .base_baud = 1843200,
1340 .uart_offset = 0x200,
1341 },
1342 [pbn_b0_4_1843200_200] = {
1343 .flags = FL_BASE0,
1344 .num_ports = 4,
1345 .base_baud = 1843200,
1346 .uart_offset = 0x200,
1347 },
1348 [pbn_b0_8_1843200_200] = {
1349 .flags = FL_BASE0,
1350 .num_ports = 8,
1351 .base_baud = 1843200,
1352 .uart_offset = 0x200,
1353 },
7106b4e3
LH		 1354 [pbn_b0_1_4000000] = {
1355 .flags = FL_BASE0,
1356 .num_ports = 1,
1357 .base_baud = 4000000,
1358 .uart_offset = 8,
1359 },
26e92861 1360
1da177e4
LT		 1361 [pbn_b0_bt_1_115200] = {
1362 .flags = FL_BASE0|FL_BASE_BARS,
1363 .num_ports = 1,
1364 .base_baud = 115200,
1365 .uart_offset = 8,
1366 },
1367 [pbn_b0_bt_2_115200] = {
1368 .flags = FL_BASE0|FL_BASE_BARS,
1369 .num_ports = 2,
1370 .base_baud = 115200,
1371 .uart_offset = 8,
1372 },
1373 [pbn_b0_bt_8_115200] = {
1374 .flags = FL_BASE0|FL_BASE_BARS,
1375 .num_ports = 8,
1376 .base_baud = 115200,
1377 .uart_offset = 8,
1378 },
1379
1380 [pbn_b0_bt_1_460800] = {
1381 .flags = FL_BASE0|FL_BASE_BARS,
1382 .num_ports = 1,
1383 .base_baud = 460800,
1384 .uart_offset = 8,
1385 },
1386 [pbn_b0_bt_2_460800] = {
1387 .flags = FL_BASE0|FL_BASE_BARS,
1388 .num_ports = 2,
1389 .base_baud = 460800,
1390 .uart_offset = 8,
1391 },
1392 [pbn_b0_bt_4_460800] = {
1393 .flags = FL_BASE0|FL_BASE_BARS,
1394 .num_ports = 4,
1395 .base_baud = 460800,
1396 .uart_offset = 8,
1397 },
1398
1399 [pbn_b0_bt_1_921600] = {
1400 .flags = FL_BASE0|FL_BASE_BARS,
1401 .num_ports = 1,
1402 .base_baud = 921600,
1403 .uart_offset = 8,
1404 },
1405 [pbn_b0_bt_2_921600] = {
1406 .flags = FL_BASE0|FL_BASE_BARS,
1407 .num_ports = 2,
1408 .base_baud = 921600,
1409 .uart_offset = 8,
1410 },
1411 [pbn_b0_bt_4_921600] = {
1412 .flags = FL_BASE0|FL_BASE_BARS,
1413 .num_ports = 4,
1414 .base_baud = 921600,
1415 .uart_offset = 8,
1416 },
1417 [pbn_b0_bt_8_921600] = {
1418 .flags = FL_BASE0|FL_BASE_BARS,
1419 .num_ports = 8,
1420 .base_baud = 921600,
1421 .uart_offset = 8,
1422 },
1423
1424 [pbn_b1_1_115200] = {
1425 .flags = FL_BASE1,
1426 .num_ports = 1,
1427 .base_baud = 115200,
1428 .uart_offset = 8,
1429 },
1430 [pbn_b1_2_115200] = {
1431 .flags = FL_BASE1,
1432 .num_ports = 2,
1433 .base_baud = 115200,
1434 .uart_offset = 8,
1435 },
1436 [pbn_b1_4_115200] = {
1437 .flags = FL_BASE1,
1438 .num_ports = 4,
1439 .base_baud = 115200,
1440 .uart_offset = 8,
1441 },
1442 [pbn_b1_8_115200] = {
1443 .flags = FL_BASE1,
1444 .num_ports = 8,
1445 .base_baud = 115200,
1446 .uart_offset = 8,
1447 },
1448
1449 [pbn_b1_1_921600] = {
1450 .flags = FL_BASE1,
1451 .num_ports = 1,
1452 .base_baud = 921600,
1453 .uart_offset = 8,
1454 },
1455 [pbn_b1_2_921600] = {
1456 .flags = FL_BASE1,
1457 .num_ports = 2,
1458 .base_baud = 921600,
1459 .uart_offset = 8,
1460 },
1461 [pbn_b1_4_921600] = {
1462 .flags = FL_BASE1,
1463 .num_ports = 4,
1464 .base_baud = 921600,
1465 .uart_offset = 8,
1466 },
1467 [pbn_b1_8_921600] = {
1468 .flags = FL_BASE1,
1469 .num_ports = 8,
1470 .base_baud = 921600,
1471 .uart_offset = 8,
1472 },
26e92861
GH		 1473 [pbn_b1_2_1250000] = {
1474 .flags = FL_BASE1,
1475 .num_ports = 2,
1476 .base_baud = 1250000,
1477 .uart_offset = 8,
1478 },
1da177e4 1479
84f8c6fc
NV		 1480 [pbn_b1_bt_1_115200] = {
1481 .flags = FL_BASE1|FL_BASE_BARS,
1482 .num_ports = 1,
1483 .base_baud = 115200,
1484 .uart_offset = 8,
1485 },
1486
1da177e4
LT		 1487 [pbn_b1_bt_2_921600] = {
1488 .flags = FL_BASE1|FL_BASE_BARS,
1489 .num_ports = 2,
1490 .base_baud = 921600,
1491 .uart_offset = 8,
1492 },
1493
1494 [pbn_b1_1_1382400] = {
1495 .flags = FL_BASE1,
1496 .num_ports = 1,
1497 .base_baud = 1382400,
1498 .uart_offset = 8,
1499 },
1500 [pbn_b1_2_1382400] = {
1501 .flags = FL_BASE1,
1502 .num_ports = 2,
1503 .base_baud = 1382400,
1504 .uart_offset = 8,
1505 },
1506 [pbn_b1_4_1382400] = {
1507 .flags = FL_BASE1,
1508 .num_ports = 4,
1509 .base_baud = 1382400,
1510 .uart_offset = 8,
1511 },
1512 [pbn_b1_8_1382400] = {
1513 .flags = FL_BASE1,
1514 .num_ports = 8,
1515 .base_baud = 1382400,
1516 .uart_offset = 8,
1517 },
1518
1519 [pbn_b2_1_115200] = {
1520 .flags = FL_BASE2,
1521 .num_ports = 1,
1522 .base_baud = 115200,
1523 .uart_offset = 8,
1524 },
737c1756
PH		 1525 [pbn_b2_2_115200] = {
1526 .flags = FL_BASE2,
1527 .num_ports = 2,
1528 .base_baud = 115200,
1529 .uart_offset = 8,
1530 },
a9cccd34
MF		 1531 [pbn_b2_4_115200] = {
1532 .flags = FL_BASE2,
1533 .num_ports = 4,
1534 .base_baud = 115200,
1535 .uart_offset = 8,
1536 },
1da177e4
LT		 1537 [pbn_b2_8_115200] = {
1538 .flags = FL_BASE2,
1539 .num_ports = 8,
1540 .base_baud = 115200,
1541 .uart_offset = 8,
1542 },
1543
1544 [pbn_b2_1_460800] = {
1545 .flags = FL_BASE2,
1546 .num_ports = 1,
1547 .base_baud = 460800,
1548 .uart_offset = 8,
1549 },
1550 [pbn_b2_4_460800] = {
1551 .flags = FL_BASE2,
1552 .num_ports = 4,
1553 .base_baud = 460800,
1554 .uart_offset = 8,
1555 },
1556 [pbn_b2_8_460800] = {
1557 .flags = FL_BASE2,
1558 .num_ports = 8,
1559 .base_baud = 460800,
1560 .uart_offset = 8,
1561 },
1562 [pbn_b2_16_460800] = {
1563 .flags = FL_BASE2,
1564 .num_ports = 16,
1565 .base_baud = 460800,
1566 .uart_offset = 8,
1567 },
1568
1569 [pbn_b2_1_921600] = {
1570 .flags = FL_BASE2,
1571 .num_ports = 1,
1572 .base_baud = 921600,
1573 .uart_offset = 8,
1574 },
1575 [pbn_b2_4_921600] = {
1576 .flags = FL_BASE2,
1577 .num_ports = 4,
1578 .base_baud = 921600,
1579 .uart_offset = 8,
1580 },
1581 [pbn_b2_8_921600] = {
1582 .flags = FL_BASE2,
1583 .num_ports = 8,
1584 .base_baud = 921600,
1585 .uart_offset = 8,
1586 },
1587
1588 [pbn_b2_bt_1_115200] = {
1589 .flags = FL_BASE2|FL_BASE_BARS,
1590 .num_ports = 1,
1591 .base_baud = 115200,
1592 .uart_offset = 8,
1593 },
1594 [pbn_b2_bt_2_115200] = {
1595 .flags = FL_BASE2|FL_BASE_BARS,
1596 .num_ports = 2,
1597 .base_baud = 115200,
1598 .uart_offset = 8,
1599 },
1600 [pbn_b2_bt_4_115200] = {
1601 .flags = FL_BASE2|FL_BASE_BARS,
1602 .num_ports = 4,
1603 .base_baud = 115200,
1604 .uart_offset = 8,
1605 },
1606
1607 [pbn_b2_bt_2_921600] = {
1608 .flags = FL_BASE2|FL_BASE_BARS,
1609 .num_ports = 2,
1610 .base_baud = 921600,
1611 .uart_offset = 8,
1612 },
1613 [pbn_b2_bt_4_921600] = {
1614 .flags = FL_BASE2|FL_BASE_BARS,
1615 .num_ports = 4,
1616 .base_baud = 921600,
1617 .uart_offset = 8,
1618 },
1619
d9004eb4
ABL		 1620 [pbn_b3_2_115200] = {
1621 .flags = FL_BASE3,
1622 .num_ports = 2,
1623 .base_baud = 115200,
1624 .uart_offset = 8,
1625 },
1da177e4
LT		 1626 [pbn_b3_4_115200] = {
1627 .flags = FL_BASE3,
1628 .num_ports = 4,
1629 .base_baud = 115200,
1630 .uart_offset = 8,
1631 },
1632 [pbn_b3_8_115200] = {
1633 .flags = FL_BASE3,
1634 .num_ports = 8,
1635 .base_baud = 115200,
1636 .uart_offset = 8,
1637 },
1638
1639 /*
1640 * Entries following this are board-specific.
1641 */
1642
1643 /*
1644 * Panacom - IOMEM
1645 */
1646 [pbn_panacom] = {
1647 .flags = FL_BASE2,
1648 .num_ports = 2,
1649 .base_baud = 921600,
1650 .uart_offset = 0x400,
1651 .reg_shift = 7,
1652 },
1653 [pbn_panacom2] = {
1654 .flags = FL_BASE2|FL_BASE_BARS,
1655 .num_ports = 2,
1656 .base_baud = 921600,
1657 .uart_offset = 0x400,
1658 .reg_shift = 7,
1659 },
1660 [pbn_panacom4] = {
1661 .flags = FL_BASE2|FL_BASE_BARS,
1662 .num_ports = 4,
1663 .base_baud = 921600,
1664 .uart_offset = 0x400,
1665 .reg_shift = 7,
1666 },
1667
add7b58e
BH		 1668 [pbn_exsys_4055] = {
1669 .flags = FL_BASE2,
1670 .num_ports = 4,
1671 .base_baud = 115200,
1672 .uart_offset = 8,
1673 },
1674
1da177e4
LT		 1675 /* I think this entry is broken - the first_offset looks wrong --rmk */
1676 [pbn_plx_romulus] = {
1677 .flags = FL_BASE2,
1678 .num_ports = 4,
1679 .base_baud = 921600,
1680 .uart_offset = 8 << 2,
1681 .reg_shift = 2,
1682 .first_offset = 0x03,
1683 },
1684
1685 /*
1686 * This board uses the size of PCI Base region 0 to
1687 * signal now many ports are available
1688 */
1689 [pbn_oxsemi] = {
1690 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1691 .num_ports = 32,
1692 .base_baud = 115200,
1693 .uart_offset = 8,
1694 },
7106b4e3
LH		 1695 [pbn_oxsemi_1_4000000] = {
1696 .flags = FL_BASE0,
1697 .num_ports = 1,
1698 .base_baud = 4000000,
1699 .uart_offset = 0x200,
1700 .first_offset = 0x1000,
1701 },
1702 [pbn_oxsemi_2_4000000] = {
1703 .flags = FL_BASE0,
1704 .num_ports = 2,
1705 .base_baud = 4000000,
1706 .uart_offset = 0x200,
1707 .first_offset = 0x1000,
1708 },
1709 [pbn_oxsemi_4_4000000] = {
1710 .flags = FL_BASE0,
1711 .num_ports = 4,
1712 .base_baud = 4000000,
1713 .uart_offset = 0x200,
1714 .first_offset = 0x1000,
1715 },
1716 [pbn_oxsemi_8_4000000] = {
1717 .flags = FL_BASE0,
1718 .num_ports = 8,
1719 .base_baud = 4000000,
1720 .uart_offset = 0x200,
1721 .first_offset = 0x1000,
1722 },
1723
1da177e4
LT		 1724
1725 /*
1726 * EKF addition for i960 Boards form EKF with serial port.
1727 * Max 256 ports.
1728 */
1729 [pbn_intel_i960] = {
1730 .flags = FL_BASE0,
1731 .num_ports = 32,
1732 .base_baud = 921600,
1733 .uart_offset = 8 << 2,
1734 .reg_shift = 2,
1735 .first_offset = 0x10000,
1736 },
1737 [pbn_sgi_ioc3] = {
1738 .flags = FL_BASE0|FL_NOIRQ,
1739 .num_ports = 1,
1740 .base_baud = 458333,
1741 .uart_offset = 8,
1742 .reg_shift = 0,
1743 .first_offset = 0x20178,
1744 },
1745
1da177e4
LT		 1746 /*
1747 * Computone - uses IOMEM.
1748 */
1749 [pbn_computone_4] = {
1750 .flags = FL_BASE0,
1751 .num_ports = 4,
1752 .base_baud = 921600,
1753 .uart_offset = 0x40,
1754 .reg_shift = 2,
1755 .first_offset = 0x200,
1756 },
1757 [pbn_computone_6] = {
1758 .flags = FL_BASE0,
1759 .num_ports = 6,
1760 .base_baud = 921600,
1761 .uart_offset = 0x40,
1762 .reg_shift = 2,
1763 .first_offset = 0x200,
1764 },
1765 [pbn_computone_8] = {
1766 .flags = FL_BASE0,
1767 .num_ports = 8,
1768 .base_baud = 921600,
1769 .uart_offset = 0x40,
1770 .reg_shift = 2,
1771 .first_offset = 0x200,
1772 },
1773 [pbn_sbsxrsio] = {
1774 .flags = FL_BASE0,
1775 .num_ports = 8,
1776 .base_baud = 460800,
1777 .uart_offset = 256,
1778 .reg_shift = 4,
1779 },
1780 /*
1781 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1782 * Only basic 16550A support.
1783 * XR17C15[24] are not tested, but they should work.
1784 */
1785 [pbn_exar_XR17C152] = {
1786 .flags = FL_BASE0,
1787 .num_ports = 2,
1788 .base_baud = 921600,
1789 .uart_offset = 0x200,
1790 },
1791 [pbn_exar_XR17C154] = {
1792 .flags = FL_BASE0,
1793 .num_ports = 4,
1794 .base_baud = 921600,
1795 .uart_offset = 0x200,
1796 },
1797 [pbn_exar_XR17C158] = {
1798 .flags = FL_BASE0,
1799 .num_ports = 8,
1800 .base_baud = 921600,
1801 .uart_offset = 0x200,
1802 },
aa798505
OJ		 1803 /*
1804 * PA Semi PWRficient PA6T-1682M on-chip UART
1805 */
1806 [pbn_pasemi_1682M] = {
1807 .flags = FL_BASE0,
1808 .num_ports = 1,
1809 .base_baud = 8333333,
1810 },
1da177e4
LT		 1811};
1812
436bbd43 1813static const struct pci_device_id softmodem_blacklist[] = {
5756ee99 1814 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
436bbd43
CS		 1815};
1816
1da177e4
LT		 1817/*
1818 * Given a complete unknown PCI device, try to use some heuristics to
1819 * guess what the configuration might be, based on the pitiful PCI
1820 * serial specs. Returns 0 on success, 1 on failure.
1821 */
1822static int __devinit
1c7c1fe5 1823serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 1824{
436bbd43 1825 const struct pci_device_id *blacklist;
1da177e4 1826 int num_iomem, num_port, first_port = -1, i;
5756ee99 1827
1da177e4
LT		 1828 /*
1829 * If it is not a communications device or the programming
1830 * interface is greater than 6, give up.
1831 *
1832 * (Should we try to make guesses for multiport serial devices
5756ee99 1833 * later?)
1da177e4
LT		 1834 */
1835 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1836 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1837 (dev->class & 0xff) > 6)
1838 return -ENODEV;
1839
436bbd43
CS		 1840 /*
1841 * Do not access blacklisted devices that are known not to
1842 * feature serial ports.
1843 */
1844 for (blacklist = softmodem_blacklist;
1845 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
1846 blacklist++) {
1847 if (dev->vendor == blacklist->vendor &&
1848 dev->device == blacklist->device)
1849 return -ENODEV;
1850 }
1851
1da177e4
LT		 1852 num_iomem = num_port = 0;
1853 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1854 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1855 num_port++;
1856 if (first_port == -1)
1857 first_port = i;
1858 }
1859 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1860 num_iomem++;
1861 }
1862
1863 /*
1864 * If there is 1 or 0 iomem regions, and exactly one port,
1865 * use it. We guess the number of ports based on the IO
1866 * region size.
1867 */
1868 if (num_iomem <= 1 && num_port == 1) {
1869 board->flags = first_port;
1870 board->num_ports = pci_resource_len(dev, first_port) / 8;
1871 return 0;
1872 }
1873
1874 /*
1875 * Now guess if we've got a board which indexes by BARs.
1876 * Each IO BAR should be 8 bytes, and they should follow
1877 * consecutively.
1878 */
1879 first_port = -1;
1880 num_port = 0;
1881 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1882 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1883 pci_resource_len(dev, i) == 8 &&
1884 (first_port == -1 || (first_port + num_port) == i)) {
1885 num_port++;
1886 if (first_port == -1)
1887 first_port = i;
1888 }
1889 }
1890
1891 if (num_port > 1) {
1892 board->flags = first_port | FL_BASE_BARS;
1893 board->num_ports = num_port;
1894 return 0;
1895 }
1896
1897 return -ENODEV;
1898}
1899
1900static inline int
975a1a7d
RK		 1901serial_pci_matches(const struct pciserial_board *board,
1902 const struct pciserial_board *guessed)
1da177e4
LT		 1903{
1904 return
1905 board->num_ports == guessed->num_ports &&
1906 board->base_baud == guessed->base_baud &&
1907 board->uart_offset == guessed->uart_offset &&
1908 board->reg_shift == guessed->reg_shift &&
1909 board->first_offset == guessed->first_offset;
1910}
1911
241fc436 1912struct serial_private *
975a1a7d 1913pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 1914{
72ce9a83 1915 struct uart_port serial_port;
1da177e4 1916 struct serial_private *priv;
1da177e4
LT		 1917 struct pci_serial_quirk *quirk;
1918 int rc, nr_ports, i;
1919
1da177e4
LT		 1920 nr_ports = board->num_ports;
1921
1922 /*
1923 * Find an init and setup quirks.
1924 */
1925 quirk = find_quirk(dev);
1926
1927 /*
1928 * Run the new-style initialization function.
1929 * The initialization function returns:
1930 * <0 - error
1931 * 0 - use board->num_ports
1932 * >0 - number of ports
1933 */
1934 if (quirk->init) {
1935 rc = quirk->init(dev);
241fc436
RK		 1936 if (rc < 0) {
1937 priv = ERR_PTR(rc);
1938 goto err_out;
1939 }
1da177e4
LT		 1940 if (rc)
1941 nr_ports = rc;
1942 }
1943
8f31bb39 1944 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 1945 sizeof(unsigned int) * nr_ports,
1946 GFP_KERNEL);
1947 if (!priv) {
241fc436
RK		 1948 priv = ERR_PTR(-ENOMEM);
1949 goto err_deinit;
1da177e4
LT		 1950 }
1951
70db3d91 1952 priv->dev = dev;
1da177e4 1953 priv->quirk = quirk;
1da177e4 1954
72ce9a83
RK		 1955 memset(&serial_port, 0, sizeof(struct uart_port));
1956 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1957 serial_port.uartclk = board->base_baud * 16;
1958 serial_port.irq = get_pci_irq(dev, board);
1959 serial_port.dev = &dev->dev;
1960
1da177e4 1961 for (i = 0; i < nr_ports; i++) {
70db3d91 1962 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 1963 break;
72ce9a83 1964
1da177e4 1965#ifdef SERIAL_DEBUG_PCI
5756ee99 1966 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
1da177e4
LT		 1967 serial_port.iobase, serial_port.irq, serial_port.iotype);
1968#endif
5756ee99 1969
1da177e4
LT		 1970 priv->line[i] = serial8250_register_port(&serial_port);
1971 if (priv->line[i] < 0) {
1972 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1973 break;
1974 }
1975 }
1da177e4 1976 priv->nr = i;
241fc436 1977 return priv;
1da177e4 1978
5756ee99 1979err_deinit:
1da177e4
LT		 1980 if (quirk->exit)
1981 quirk->exit(dev);
5756ee99 1982err_out:
241fc436 1983 return priv;
1da177e4 1984}
241fc436 1985EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 1986
241fc436 1987void pciserial_remove_ports(struct serial_private *priv)
1da177e4 1988{
056a8763
RK		 1989 struct pci_serial_quirk *quirk;
1990 int i;
1da177e4 1991
056a8763
RK		 1992 for (i = 0; i < priv->nr; i++)
1993 serial8250_unregister_port(priv->line[i]);
1da177e4 1994
056a8763
RK		 1995 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1996 if (priv->remapped_bar[i])
1997 iounmap(priv->remapped_bar[i]);
1998 priv->remapped_bar[i] = NULL;
1999 }
1da177e4 2000
056a8763
RK		 2001 /*
2002 * Find the exit quirks.
2003 */
241fc436 2004 quirk = find_quirk(priv->dev);
056a8763 2005 if (quirk->exit)
241fc436
RK		 2006 quirk->exit(priv->dev);
2007
2008 kfree(priv);
2009}
2010EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2011
2012void pciserial_suspend_ports(struct serial_private *priv)
2013{
2014 int i;
2015
2016 for (i = 0; i < priv->nr; i++)
2017 if (priv->line[i] >= 0)
2018 serial8250_suspend_port(priv->line[i]);
2019}
2020EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2021
2022void pciserial_resume_ports(struct serial_private *priv)
2023{
2024 int i;
2025
2026 /*
2027 * Ensure that the board is correctly configured.
2028 */
2029 if (priv->quirk->init)
2030 priv->quirk->init(priv->dev);
2031
2032 for (i = 0; i < priv->nr; i++)
2033 if (priv->line[i] >= 0)
2034 serial8250_resume_port(priv->line[i]);
2035}
2036EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2037
2038/*
2039 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2040 * to the arrangement of serial ports on a PCI card.
2041 */
2042static int __devinit
2043pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2044{
2045 struct serial_private *priv;
975a1a7d
RK		 2046 const struct pciserial_board *board;
2047 struct pciserial_board tmp;
241fc436
RK		 2048 int rc;
2049
2050 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2051 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2052 ent->driver_data);
2053 return -EINVAL;
2054 }
2055
2056 board = &pci_boards[ent->driver_data];
2057
2058 rc = pci_enable_device(dev);
2059 if (rc)
2060 return rc;
2061
2062 if (ent->driver_data == pbn_default) {
2063 /*
2064 * Use a copy of the pci_board entry for this;
2065 * avoid changing entries in the table.
2066 */
2067 memcpy(&tmp, board, sizeof(struct pciserial_board));
2068 board = &tmp;
2069
2070 /*
2071 * We matched one of our class entries. Try to
2072 * determine the parameters of this board.
2073 */
975a1a7d 2074 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 2075 if (rc)
2076 goto disable;
2077 } else {
2078 /*
2079 * We matched an explicit entry. If we are able to
2080 * detect this boards settings with our heuristic,
2081 * then we no longer need this entry.
2082 */
2083 memcpy(&tmp, &pci_boards[pbn_default],
2084 sizeof(struct pciserial_board));
2085 rc = serial_pci_guess_board(dev, &tmp);
2086 if (rc == 0 && serial_pci_matches(board, &tmp))
2087 moan_device("Redundant entry in serial pci_table.",
2088 dev);
2089 }
2090
2091 priv = pciserial_init_ports(dev, board);
2092 if (!IS_ERR(priv)) {
2093 pci_set_drvdata(dev, priv);
2094 return 0;
2095 }
2096
2097 rc = PTR_ERR(priv);
1da177e4 2098
241fc436 2099 disable:
056a8763 2100 pci_disable_device(dev);
241fc436
RK		 2101 return rc;
2102}
1da177e4 2103
241fc436
RK		 2104static void __devexit pciserial_remove_one(struct pci_dev *dev)
2105{
2106 struct serial_private *priv = pci_get_drvdata(dev);
2107
2108 pci_set_drvdata(dev, NULL);
2109
2110 pciserial_remove_ports(priv);
2111
2112 pci_disable_device(dev);
1da177e4
LT		 2113}
2114
1d5e7996 2115#ifdef CONFIG_PM
1da177e4
LT		 2116static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2117{
2118 struct serial_private *priv = pci_get_drvdata(dev);
2119
241fc436
RK		 2120 if (priv)
2121 pciserial_suspend_ports(priv);
1da177e4 2122
1da177e4
LT		 2123 pci_save_state(dev);
2124 pci_set_power_state(dev, pci_choose_state(dev, state));
2125 return 0;
2126}
2127
2128static int pciserial_resume_one(struct pci_dev *dev)
2129{
ccb9d59e 2130 int err;
1da177e4
LT		 2131 struct serial_private *priv = pci_get_drvdata(dev);
2132
2133 pci_set_power_state(dev, PCI_D0);
2134 pci_restore_state(dev);
2135
2136 if (priv) {
1da177e4
LT		 2137 /*
2138 * The device may have been disabled. Re-enable it.
2139 */
ccb9d59e 2140 err = pci_enable_device(dev);
40836c48 2141 /* FIXME: We cannot simply error out here */
ccb9d59e 2142 if (err)
40836c48 2143 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
241fc436 2144 pciserial_resume_ports(priv);
1da177e4
LT		 2145 }
2146 return 0;
2147}
1d5e7996 2148#endif
1da177e4
LT		 2149
2150static struct pci_device_id serial_pci_tbl[] = {
2151 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2152 PCI_SUBVENDOR_ID_CONNECT_TECH,
2153 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2154 pbn_b1_8_1382400 },
2155 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2156 PCI_SUBVENDOR_ID_CONNECT_TECH,
2157 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2158 pbn_b1_4_1382400 },
2159 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2160 PCI_SUBVENDOR_ID_CONNECT_TECH,
2161 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2162 pbn_b1_2_1382400 },
2163 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2164 PCI_SUBVENDOR_ID_CONNECT_TECH,
2165 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2166 pbn_b1_8_1382400 },
2167 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2168 PCI_SUBVENDOR_ID_CONNECT_TECH,
2169 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2170 pbn_b1_4_1382400 },
2171 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2172 PCI_SUBVENDOR_ID_CONNECT_TECH,
2173 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2174 pbn_b1_2_1382400 },
2175 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2176 PCI_SUBVENDOR_ID_CONNECT_TECH,
2177 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2178 pbn_b1_8_921600 },
2179 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2180 PCI_SUBVENDOR_ID_CONNECT_TECH,
2181 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2182 pbn_b1_8_921600 },
2183 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2184 PCI_SUBVENDOR_ID_CONNECT_TECH,
2185 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2186 pbn_b1_4_921600 },
2187 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2188 PCI_SUBVENDOR_ID_CONNECT_TECH,
2189 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2190 pbn_b1_4_921600 },
2191 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2192 PCI_SUBVENDOR_ID_CONNECT_TECH,
2193 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2194 pbn_b1_2_921600 },
2195 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2196 PCI_SUBVENDOR_ID_CONNECT_TECH,
2197 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2198 pbn_b1_8_921600 },
2199 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2200 PCI_SUBVENDOR_ID_CONNECT_TECH,
2201 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2202 pbn_b1_8_921600 },
2203 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2204 PCI_SUBVENDOR_ID_CONNECT_TECH,
2205 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2206 pbn_b1_4_921600 },
26e92861
GH		 2207 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2208 PCI_SUBVENDOR_ID_CONNECT_TECH,
2209 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2210 pbn_b1_2_1250000 },
2211 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2212 PCI_SUBVENDOR_ID_CONNECT_TECH,
2213 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2214 pbn_b0_2_1843200 },
2215 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2216 PCI_SUBVENDOR_ID_CONNECT_TECH,
2217 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2218 pbn_b0_4_1843200 },
85d1494e
YY		 2219 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2220 PCI_VENDOR_ID_AFAVLAB,
2221 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2222 pbn_b0_4_1152000 },
26e92861
GH		 2223 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2224 PCI_SUBVENDOR_ID_CONNECT_TECH,
2225 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2226 pbn_b0_2_1843200_200 },
2227 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2228 PCI_SUBVENDOR_ID_CONNECT_TECH,
2229 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2230 pbn_b0_4_1843200_200 },
2231 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2232 PCI_SUBVENDOR_ID_CONNECT_TECH,
2233 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2234 pbn_b0_8_1843200_200 },
2235 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2236 PCI_SUBVENDOR_ID_CONNECT_TECH,
2237 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2238 pbn_b0_2_1843200_200 },
2239 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2240 PCI_SUBVENDOR_ID_CONNECT_TECH,
2241 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2242 pbn_b0_4_1843200_200 },
2243 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2244 PCI_SUBVENDOR_ID_CONNECT_TECH,
2245 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2246 pbn_b0_8_1843200_200 },
2247 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2248 PCI_SUBVENDOR_ID_CONNECT_TECH,
2249 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2250 pbn_b0_2_1843200_200 },
2251 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2252 PCI_SUBVENDOR_ID_CONNECT_TECH,
2253 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2254 pbn_b0_4_1843200_200 },
2255 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2256 PCI_SUBVENDOR_ID_CONNECT_TECH,
2257 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2258 pbn_b0_8_1843200_200 },
2259 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2260 PCI_SUBVENDOR_ID_CONNECT_TECH,
2261 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2262 pbn_b0_2_1843200_200 },
2263 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2264 PCI_SUBVENDOR_ID_CONNECT_TECH,
2265 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2266 pbn_b0_4_1843200_200 },
2267 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2268 PCI_SUBVENDOR_ID_CONNECT_TECH,
2269 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2270 pbn_b0_8_1843200_200 },
1da177e4
LT		 2271
2272 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 2273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2274 pbn_b2_bt_1_115200 },
2275 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 2276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2277 pbn_b2_bt_2_115200 },
2278 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 2279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2280 pbn_b2_bt_4_115200 },
2281 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 2282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2283 pbn_b2_bt_2_115200 },
2284 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 2285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2286 pbn_b2_bt_4_115200 },
2287 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 2288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 2289 pbn_b2_8_115200 },
e65f0f82
FL		 2290 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2292 pbn_b2_8_460800 },
1da177e4
LT		 2293 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2295 pbn_b2_8_115200 },
2296
2297 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2299 pbn_b2_bt_2_115200 },
2300 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2302 pbn_b2_bt_2_921600 },
2303 /*
2304 * VScom SPCOM800, from sl@s.pl
2305 */
5756ee99
AC		 2306 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2307 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2308 pbn_b2_8_921600 },
2309 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 2310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 2311 pbn_b2_4_921600 },
b76c5a07
CB		 2312 /* Unknown card - subdevice 0x1584 */
2313 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2314 PCI_VENDOR_ID_PLX,
2315 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2316 pbn_b0_4_115200 },
1da177e4
LT		 2317 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2318 PCI_SUBVENDOR_ID_KEYSPAN,
2319 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2320 pbn_panacom },
2321 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2323 pbn_panacom4 },
2324 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2326 pbn_panacom2 },
a9cccd34
MF		 2327 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2328 PCI_VENDOR_ID_ESDGMBH,
2329 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2330 pbn_b2_4_115200 },
1da177e4
LT		 2331 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2332 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2333 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 2334 pbn_b2_4_460800 },
2335 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2336 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2337 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 2338 pbn_b2_8_460800 },
2339 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2340 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2341 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 2342 pbn_b2_16_460800 },
2343 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2344 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2345 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 2346 pbn_b2_16_460800 },
2347 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2348 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 2349 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 2350 pbn_b2_4_460800 },
2351 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2352 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 2353 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 2354 pbn_b2_8_460800 },
add7b58e
BH		 2355 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2356 PCI_SUBVENDOR_ID_EXSYS,
2357 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2358 pbn_exsys_4055 },
1da177e4
LT		 2359 /*
2360 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2361 * (Exoray@isys.ca)
2362 */
2363 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2364 0x10b5, 0x106a, 0, 0,
2365 pbn_plx_romulus },
2366 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2367 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2368 pbn_b1_4_115200 },
2369 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2370 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2371 pbn_b1_2_115200 },
2372 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2373 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2374 pbn_b1_8_115200 },
2375 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2376 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2377 pbn_b1_8_115200 },
2378 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 2379 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2380 0, 0,
1da177e4 2381 pbn_b0_4_921600 },
fbc0dc0d 2382 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 2383 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2384 0, 0,
fbc0dc0d 2385 pbn_b0_4_1152000 },
db1de159
DR		 2386
2387 /*
2388 * The below card is a little controversial since it is the
2389 * subject of a PCI vendor/device ID clash. (See
2390 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2391 * For now just used the hex ID 0x950a.
2392 */
39aced68
NV		 2393 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2394 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2395 pbn_b0_2_115200 },
db1de159
DR		 2396 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2398 pbn_b0_2_1130000 },
1da177e4
LT		 2399 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2401 pbn_b0_4_115200 },
2402 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2404 pbn_b0_bt_2_921600 },
2405
7106b4e3
LH		 2406 /*
2407 * Oxford Semiconductor Inc. Tornado PCI express device range.
2408 */
2409 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2411 pbn_b0_1_4000000 },
2412 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2414 pbn_b0_1_4000000 },
2415 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2417 pbn_oxsemi_1_4000000 },
2418 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2420 pbn_oxsemi_1_4000000 },
2421 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2423 pbn_b0_1_4000000 },
2424 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2426 pbn_b0_1_4000000 },
2427 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2429 pbn_oxsemi_1_4000000 },
2430 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2432 pbn_oxsemi_1_4000000 },
2433 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2435 pbn_b0_1_4000000 },
2436 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2438 pbn_b0_1_4000000 },
2439 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2441 pbn_b0_1_4000000 },
2442 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2444 pbn_b0_1_4000000 },
2445 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2447 pbn_oxsemi_2_4000000 },
2448 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2450 pbn_oxsemi_2_4000000 },
2451 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2453 pbn_oxsemi_4_4000000 },
2454 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2456 pbn_oxsemi_4_4000000 },
2457 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2459 pbn_oxsemi_8_4000000 },
2460 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2462 pbn_oxsemi_8_4000000 },
2463 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2465 pbn_oxsemi_1_4000000 },
2466 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2468 pbn_oxsemi_1_4000000 },
2469 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2471 pbn_oxsemi_1_4000000 },
2472 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2474 pbn_oxsemi_1_4000000 },
2475 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2477 pbn_oxsemi_1_4000000 },
2478 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2480 pbn_oxsemi_1_4000000 },
2481 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
2482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2483 pbn_oxsemi_1_4000000 },
2484 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
2485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2486 pbn_oxsemi_1_4000000 },
2487 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
2488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2489 pbn_oxsemi_1_4000000 },
2490 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
2491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2492 pbn_oxsemi_1_4000000 },
2493 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
2494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2495 pbn_oxsemi_1_4000000 },
2496 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
2497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2498 pbn_oxsemi_1_4000000 },
2499 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
2500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2501 pbn_oxsemi_1_4000000 },
2502 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
2503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2504 pbn_oxsemi_1_4000000 },
2505 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
2506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2507 pbn_oxsemi_1_4000000 },
2508 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
2509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2510 pbn_oxsemi_1_4000000 },
2511 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
2512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2513 pbn_oxsemi_1_4000000 },
2514 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
2515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2516 pbn_oxsemi_1_4000000 },
2517 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
2518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2519 pbn_oxsemi_1_4000000 },
2520 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
2521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2522 pbn_oxsemi_1_4000000 },
2523 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
2524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2525 pbn_oxsemi_1_4000000 },
2526 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
2527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2528 pbn_oxsemi_1_4000000 },
2529 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
2530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2531 pbn_oxsemi_1_4000000 },
2532 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
2533 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2534 pbn_oxsemi_1_4000000 },
2535 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
2536 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2537 pbn_oxsemi_1_4000000 },
2538 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
2539 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2540 pbn_oxsemi_1_4000000 },
b80de369
LH		 2541 /*
2542 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2543 */
2544 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2545 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
2546 pbn_oxsemi_1_4000000 },
2547 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2548 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
2549 pbn_oxsemi_2_4000000 },
2550 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2551 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
2552 pbn_oxsemi_4_4000000 },
2553 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2554 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
2555 pbn_oxsemi_8_4000000 },
1da177e4
LT		 2556 /*
2557 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2558 * from skokodyn@yahoo.com
2559 */
2560 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2561 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2562 pbn_sbsxrsio },
2563 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2564 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2565 pbn_sbsxrsio },
2566 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2567 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2568 pbn_sbsxrsio },
2569 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2570 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2571 pbn_sbsxrsio },
2572
2573 /*
2574 * Digitan DS560-558, from jimd@esoft.com
2575 */
2576 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 2577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2578 pbn_b1_1_115200 },
2579
2580 /*
2581 * Titan Electronic cards
2582 * The 400L and 800L have a custom setup quirk.
2583 */
2584 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 2585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2586 pbn_b0_1_921600 },
2587 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 2588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2589 pbn_b0_2_921600 },
2590 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 2591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2592 pbn_b0_4_921600 },
2593 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 2594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2595 pbn_b0_4_921600 },
2596 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2598 pbn_b1_1_921600 },
2599 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2601 pbn_b1_bt_2_921600 },
2602 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2604 pbn_b0_bt_4_921600 },
2605 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2607 pbn_b0_bt_8_921600 },
2608
2609 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2611 pbn_b2_1_460800 },
2612 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2614 pbn_b2_1_460800 },
2615 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2617 pbn_b2_1_460800 },
2618 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2620 pbn_b2_bt_2_921600 },
2621 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2623 pbn_b2_bt_2_921600 },
2624 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2626 pbn_b2_bt_2_921600 },
2627 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2629 pbn_b2_bt_4_921600 },
2630 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2632 pbn_b2_bt_4_921600 },
2633 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2635 pbn_b2_bt_4_921600 },
2636 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2638 pbn_b0_1_921600 },
2639 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2641 pbn_b0_1_921600 },
2642 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2644 pbn_b0_1_921600 },
2645 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2647 pbn_b0_bt_2_921600 },
2648 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2650 pbn_b0_bt_2_921600 },
2651 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2653 pbn_b0_bt_2_921600 },
2654 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2656 pbn_b0_bt_4_921600 },
2657 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2658 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2659 pbn_b0_bt_4_921600 },
2660 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2662 pbn_b0_bt_4_921600 },
3ec9c594
AP		 2663 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2664 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2665 pbn_b0_bt_8_921600 },
2666 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2667 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2668 pbn_b0_bt_8_921600 },
2669 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2670 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2671 pbn_b0_bt_8_921600 },
1da177e4
LT		 2672
2673 /*
2674 * Computone devices submitted by Doug McNash dmcnash@computone.com
2675 */
2676 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2677 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2678 0, 0, pbn_computone_4 },
2679 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2680 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2681 0, 0, pbn_computone_8 },
2682 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2683 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2684 0, 0, pbn_computone_6 },
2685
2686 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2688 pbn_oxsemi },
2689 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2690 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2691 pbn_b0_bt_1_921600 },
2692
2693 /*
2694 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2695 */
2696 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2698 pbn_b0_bt_8_115200 },
2699 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2701 pbn_b0_bt_8_115200 },
2702
2703 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2705 pbn_b0_bt_2_115200 },
2706 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2708 pbn_b0_bt_2_115200 },
2709 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2711 pbn_b0_bt_2_115200 },
2712 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2714 pbn_b0_bt_4_460800 },
2715 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2717 pbn_b0_bt_4_460800 },
2718 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2720 pbn_b0_bt_2_460800 },
2721 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2722 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2723 pbn_b0_bt_2_460800 },
2724 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2726 pbn_b0_bt_2_460800 },
2727 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2728 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2729 pbn_b0_bt_1_115200 },
2730 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2732 pbn_b0_bt_1_460800 },
2733
1fb8cacc
RK		 2734 /*
2735 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2736 * Cards are identified by their subsystem vendor IDs, which
2737 * (in hex) match the model number.
2738 *
2739 * Note that JC140x are RS422/485 cards which require ox950
2740 * ACR = 0x10, and as such are not currently fully supported.
2741 */
2742 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2743 0x1204, 0x0004, 0, 0,
2744 pbn_b0_4_921600 },
2745 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2746 0x1208, 0x0004, 0, 0,
2747 pbn_b0_4_921600 },
2748/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2749 0x1402, 0x0002, 0, 0,
2750 pbn_b0_2_921600 }, */
2751/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2752 0x1404, 0x0004, 0, 0,
2753 pbn_b0_4_921600 }, */
2754 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2755 0x1208, 0x0004, 0, 0,
2756 pbn_b0_4_921600 },
2757
1da177e4
LT		 2758 /*
2759 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2760 */
2761 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2763 pbn_b1_1_1382400 },
2764
2765 /*
2766 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2767 */
2768 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2770 pbn_b1_1_1382400 },
2771
2772 /*
2773 * RAStel 2 port modem, gerg@moreton.com.au
2774 */
2775 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2776 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2777 pbn_b2_bt_2_115200 },
2778
2779 /*
2780 * EKF addition for i960 Boards form EKF with serial port
2781 */
2782 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2783 0xE4BF, PCI_ANY_ID, 0, 0,
2784 pbn_intel_i960 },
2785
2786 /*
2787 * Xircom Cardbus/Ethernet combos
2788 */
2789 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2791 pbn_b0_1_115200 },
2792 /*
2793 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2794 */
2795 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2797 pbn_b0_1_115200 },
2798
2799 /*
2800 * Untested PCI modems, sent in from various folks...
2801 */
2802
2803 /*
2804 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2805 */
2806 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2807 0x1048, 0x1500, 0, 0,
2808 pbn_b1_1_115200 },
2809
2810 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2811 0xFF00, 0, 0, 0,
2812 pbn_sgi_ioc3 },
2813
2814 /*
2815 * HP Diva card
2816 */
2817 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2818 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2819 pbn_b1_1_115200 },
2820 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2822 pbn_b0_5_115200 },
2823 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2825 pbn_b2_1_115200 },
2826
d9004eb4
ABL		 2827 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2829 pbn_b3_2_115200 },
1da177e4
LT		 2830 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2832 pbn_b3_4_115200 },
2833 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2834 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2835 pbn_b3_8_115200 },
2836
2837 /*
2838 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2839 */
2840 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2841 PCI_ANY_ID, PCI_ANY_ID,
2842 0,
2843 0, pbn_exar_XR17C152 },
2844 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2845 PCI_ANY_ID, PCI_ANY_ID,
2846 0,
2847 0, pbn_exar_XR17C154 },
2848 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2849 PCI_ANY_ID, PCI_ANY_ID,
2850 0,
2851 0, pbn_exar_XR17C158 },
2852
2853 /*
2854 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2855 */
2856 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2857 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2858 pbn_b0_1_115200 },
84f8c6fc
NV		 2859 /*
2860 * ITE
2861 */
2862 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2863 PCI_ANY_ID, PCI_ANY_ID,
2864 0, 0,
2865 pbn_b1_bt_1_115200 },
1da177e4 2866
737c1756
PH		 2867 /*
2868 * IntaShield IS-200
2869 */
2870 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2871 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
2872 pbn_b2_2_115200 },
4b6f6ce9
IGP		 2873 /*
2874 * IntaShield IS-400
2875 */
2876 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
2877 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
2878 pbn_b2_4_115200 },
48212008
TH		 2879 /*
2880 * Perle PCI-RAS cards
2881 */
2882 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2883 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2884 0, 0, pbn_b2_4_921600 },
2885 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2886 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2887 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 2888
2889 /*
2890 * Mainpine series cards: Fairly standard layout but fools
2891 * parts of the autodetect in some cases and uses otherwise
2892 * unmatched communications subclasses in the PCI Express case
2893 */
2894
2895 { /* RockForceDUO */
2896 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2897 PCI_VENDOR_ID_MAINPINE, 0x0200,
2898 0, 0, pbn_b0_2_115200 },
2899 { /* RockForceQUATRO */
2900 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2901 PCI_VENDOR_ID_MAINPINE, 0x0300,
2902 0, 0, pbn_b0_4_115200 },
2903 { /* RockForceDUO+ */
2904 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2905 PCI_VENDOR_ID_MAINPINE, 0x0400,
2906 0, 0, pbn_b0_2_115200 },
2907 { /* RockForceQUATRO+ */
2908 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2909 PCI_VENDOR_ID_MAINPINE, 0x0500,
2910 0, 0, pbn_b0_4_115200 },
2911 { /* RockForce+ */
2912 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2913 PCI_VENDOR_ID_MAINPINE, 0x0600,
2914 0, 0, pbn_b0_2_115200 },
2915 { /* RockForce+ */
2916 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2917 PCI_VENDOR_ID_MAINPINE, 0x0700,
2918 0, 0, pbn_b0_4_115200 },
2919 { /* RockForceOCTO+ */
2920 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2921 PCI_VENDOR_ID_MAINPINE, 0x0800,
2922 0, 0, pbn_b0_8_115200 },
2923 { /* RockForceDUO+ */
2924 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2925 PCI_VENDOR_ID_MAINPINE, 0x0C00,
2926 0, 0, pbn_b0_2_115200 },
2927 { /* RockForceQUARTRO+ */
2928 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2929 PCI_VENDOR_ID_MAINPINE, 0x0D00,
2930 0, 0, pbn_b0_4_115200 },
2931 { /* RockForceOCTO+ */
2932 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2933 PCI_VENDOR_ID_MAINPINE, 0x1D00,
2934 0, 0, pbn_b0_8_115200 },
2935 { /* RockForceD1 */
2936 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2937 PCI_VENDOR_ID_MAINPINE, 0x2000,
2938 0, 0, pbn_b0_1_115200 },
2939 { /* RockForceF1 */
2940 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2941 PCI_VENDOR_ID_MAINPINE, 0x2100,
2942 0, 0, pbn_b0_1_115200 },
2943 { /* RockForceD2 */
2944 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2945 PCI_VENDOR_ID_MAINPINE, 0x2200,
2946 0, 0, pbn_b0_2_115200 },
2947 { /* RockForceF2 */
2948 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2949 PCI_VENDOR_ID_MAINPINE, 0x2300,
2950 0, 0, pbn_b0_2_115200 },
2951 { /* RockForceD4 */
2952 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2953 PCI_VENDOR_ID_MAINPINE, 0x2400,
2954 0, 0, pbn_b0_4_115200 },
2955 { /* RockForceF4 */
2956 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2957 PCI_VENDOR_ID_MAINPINE, 0x2500,
2958 0, 0, pbn_b0_4_115200 },
2959 { /* RockForceD8 */
2960 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2961 PCI_VENDOR_ID_MAINPINE, 0x2600,
2962 0, 0, pbn_b0_8_115200 },
2963 { /* RockForceF8 */
2964 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2965 PCI_VENDOR_ID_MAINPINE, 0x2700,
2966 0, 0, pbn_b0_8_115200 },
2967 { /* IQ Express D1 */
2968 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2969 PCI_VENDOR_ID_MAINPINE, 0x3000,
2970 0, 0, pbn_b0_1_115200 },
2971 { /* IQ Express F1 */
2972 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2973 PCI_VENDOR_ID_MAINPINE, 0x3100,
2974 0, 0, pbn_b0_1_115200 },
2975 { /* IQ Express D2 */
2976 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2977 PCI_VENDOR_ID_MAINPINE, 0x3200,
2978 0, 0, pbn_b0_2_115200 },
2979 { /* IQ Express F2 */
2980 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2981 PCI_VENDOR_ID_MAINPINE, 0x3300,
2982 0, 0, pbn_b0_2_115200 },
2983 { /* IQ Express D4 */
2984 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2985 PCI_VENDOR_ID_MAINPINE, 0x3400,
2986 0, 0, pbn_b0_4_115200 },
2987 { /* IQ Express F4 */
2988 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2989 PCI_VENDOR_ID_MAINPINE, 0x3500,
2990 0, 0, pbn_b0_4_115200 },
2991 { /* IQ Express D8 */
2992 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2993 PCI_VENDOR_ID_MAINPINE, 0x3C00,
2994 0, 0, pbn_b0_8_115200 },
2995 { /* IQ Express F8 */
2996 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2997 PCI_VENDOR_ID_MAINPINE, 0x3D00,
2998 0, 0, pbn_b0_8_115200 },
2999
3000
aa798505
OJ		 3001 /*
3002 * PA Semi PA6T-1682M on-chip UART
3003 */
3004 { PCI_VENDOR_ID_PASEMI, 0xa004,
3005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3006 pbn_pasemi_1682M },
3007
02c9b5cf
KJ		 3008 /*
3009 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3010 */
3011 { PCI_VENDOR_ID_ADDIDATA,
3012 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3013 PCI_ANY_ID,
3014 PCI_ANY_ID,
3015 0,
3016 0,
3017 pbn_b0_4_115200 },
3018
3019 { PCI_VENDOR_ID_ADDIDATA,
3020 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3021 PCI_ANY_ID,
3022 PCI_ANY_ID,
3023 0,
3024 0,
3025 pbn_b0_2_115200 },
3026
3027 { PCI_VENDOR_ID_ADDIDATA,
3028 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3029 PCI_ANY_ID,
3030 PCI_ANY_ID,
3031 0,
3032 0,
3033 pbn_b0_1_115200 },
3034
3035 { PCI_VENDOR_ID_ADDIDATA_OLD,
3036 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3037 PCI_ANY_ID,
3038 PCI_ANY_ID,
3039 0,
3040 0,
3041 pbn_b1_8_115200 },
3042
3043 { PCI_VENDOR_ID_ADDIDATA,
3044 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3045 PCI_ANY_ID,
3046 PCI_ANY_ID,
3047 0,
3048 0,
3049 pbn_b0_4_115200 },
3050
3051 { PCI_VENDOR_ID_ADDIDATA,
3052 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3053 PCI_ANY_ID,
3054 PCI_ANY_ID,
3055 0,
3056 0,
3057 pbn_b0_2_115200 },
3058
3059 { PCI_VENDOR_ID_ADDIDATA,
3060 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3061 PCI_ANY_ID,
3062 PCI_ANY_ID,
3063 0,
3064 0,
3065 pbn_b0_1_115200 },
3066
3067 { PCI_VENDOR_ID_ADDIDATA,
3068 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3069 PCI_ANY_ID,
3070 PCI_ANY_ID,
3071 0,
3072 0,
3073 pbn_b0_4_115200 },
3074
3075 { PCI_VENDOR_ID_ADDIDATA,
3076 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3077 PCI_ANY_ID,
3078 PCI_ANY_ID,
3079 0,
3080 0,
3081 pbn_b0_2_115200 },
3082
3083 { PCI_VENDOR_ID_ADDIDATA,
3084 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3085 PCI_ANY_ID,
3086 PCI_ANY_ID,
3087 0,
3088 0,
3089 pbn_b0_1_115200 },
3090
3091 { PCI_VENDOR_ID_ADDIDATA,
3092 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3093 PCI_ANY_ID,
3094 PCI_ANY_ID,
3095 0,
3096 0,
3097 pbn_b0_8_115200 },
3098
1da177e4
LT		 3099 /*
3100 * These entries match devices with class COMMUNICATION_SERIAL,
3101 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3102 */
3103 { PCI_ANY_ID, PCI_ANY_ID,
3104 PCI_ANY_ID, PCI_ANY_ID,
3105 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3106 0xffff00, pbn_default },
3107 { PCI_ANY_ID, PCI_ANY_ID,
3108 PCI_ANY_ID, PCI_ANY_ID,
3109 PCI_CLASS_COMMUNICATION_MODEM << 8,
3110 0xffff00, pbn_default },
3111 { PCI_ANY_ID, PCI_ANY_ID,
3112 PCI_ANY_ID, PCI_ANY_ID,
3113 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3114 0xffff00, pbn_default },
3115 { 0, }
3116};
3117
3118static struct pci_driver serial_pci_driver = {
3119 .name = "serial",
3120 .probe = pciserial_init_one,
3121 .remove = __devexit_p(pciserial_remove_one),
1d5e7996 3122#ifdef CONFIG_PM
1da177e4
LT		 3123 .suspend = pciserial_suspend_one,
3124 .resume = pciserial_resume_one,
1d5e7996 3125#endif
1da177e4
LT		 3126 .id_table = serial_pci_tbl,
3127};
3128
3129static int __init serial8250_pci_init(void)
3130{
3131 return pci_register_driver(&serial_pci_driver);
3132}
3133
3134static void __exit serial8250_pci_exit(void)
3135{
3136 pci_unregister_driver(&serial_pci_driver);
3137}
3138
3139module_init(serial8250_pci_init);
3140module_exit(serial8250_pci_exit);
3141
3142MODULE_LICENSE("GPL");
3143MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3144MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
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