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8250_pci: add support for National Instruments 843x RS232 devices
[net-next-2.6.git] / drivers / serial / 8250_pci.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
1da177e4
LT		 13 */
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/pci.h>
1da177e4
LT		 17#include <linux/string.h>
18#include <linux/kernel.h>
19#include <linux/slab.h>
20#include <linux/delay.h>
21#include <linux/tty.h>
22#include <linux/serial_core.h>
23#include <linux/8250_pci.h>
24#include <linux/bitops.h>
25
26#include <asm/byteorder.h>
27#include <asm/io.h>
28
29#include "8250.h"
30
31#undef SERIAL_DEBUG_PCI
32
1da177e4
LT		 33/*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
44 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
05caac58 47 struct uart_port *, int);
1da177e4
LT		 48 void (*exit)(struct pci_dev *dev);
49};
50
51#define PCI_NUM_BAR_RESOURCES 6
52
53struct serial_private {
70db3d91 54 struct pci_dev *dev;
1da177e4
LT		 55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59};
60
61static void moan_device(const char *str, struct pci_dev *dev)
62{
63 printk(KERN_WARNING "%s: %s\n"
64 KERN_WARNING "Please send the output of lspci -vv, this\n"
65 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
66 KERN_WARNING "manufacturer and name of serial board or\n"
67 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
68 pci_name(dev), str, dev->vendor, dev->device,
69 dev->subsystem_vendor, dev->subsystem_device);
70}
71
72static int
70db3d91 73setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 74 int bar, int offset, int regshift)
75{
70db3d91 76 struct pci_dev *dev = priv->dev;
1da177e4
LT		 77 unsigned long base, len;
78
79 if (bar >= PCI_NUM_BAR_RESOURCES)
80 return -EINVAL;
81
72ce9a83
RK		 82 base = pci_resource_start(dev, bar);
83
1da177e4 84 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 85 len = pci_resource_len(dev, bar);
86
87 if (!priv->remapped_bar[bar])
6f441fe9 88 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 89 if (!priv->remapped_bar[bar])
90 return -ENOMEM;
91
92 port->iotype = UPIO_MEM;
72ce9a83 93 port->iobase = 0;
1da177e4
LT		 94 port->mapbase = base + offset;
95 port->membase = priv->remapped_bar[bar] + offset;
96 port->regshift = regshift;
97 } else {
1da177e4 98 port->iotype = UPIO_PORT;
72ce9a83
RK		 99 port->iobase = base + offset;
100 port->mapbase = 0;
101 port->membase = NULL;
102 port->regshift = 0;
1da177e4
LT		 103 }
104 return 0;
105}
106
02c9b5cf
KJ		 107/*
108 * ADDI-DATA GmbH communication cards <info@addi-data.com>
109 */
110static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 111 const struct pciserial_board *board,
02c9b5cf
KJ		 112 struct uart_port *port, int idx)
113{
114 unsigned int bar = 0, offset = board->first_offset;
115 bar = FL_GET_BASE(board->flags);
116
117 if (idx < 2) {
118 offset += idx * board->uart_offset;
119 } else if ((idx >= 2) && (idx < 4)) {
120 bar += 1;
121 offset += ((idx - 2) * board->uart_offset);
122 } else if ((idx >= 4) && (idx < 6)) {
123 bar += 2;
124 offset += ((idx - 4) * board->uart_offset);
125 } else if (idx >= 6) {
126 bar += 3;
127 offset += ((idx - 6) * board->uart_offset);
128 }
129
130 return setup_port(priv, port, bar, offset, board->reg_shift);
131}
132
1da177e4
LT		 133/*
134 * AFAVLAB uses a different mixture of BARs and offsets
135 * Not that ugly ;) -- HW
136 */
137static int
975a1a7d 138afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 139 struct uart_port *port, int idx)
140{
141 unsigned int bar, offset = board->first_offset;
5756ee99 142
1da177e4
LT		 143 bar = FL_GET_BASE(board->flags);
144 if (idx < 4)
145 bar += idx;
146 else {
147 bar = 4;
148 offset += (idx - 4) * board->uart_offset;
149 }
150
70db3d91 151 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 152}
153
154/*
155 * HP's Remote Management Console. The Diva chip came in several
156 * different versions. N-class, L2000 and A500 have two Diva chips, each
157 * with 3 UARTs (the third UART on the second chip is unused). Superdome
158 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
159 * one Diva chip, but it has been expanded to 5 UARTs.
160 */
61a116ef 161static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 162{
163 int rc = 0;
164
165 switch (dev->subsystem_device) {
166 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
167 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
168 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
169 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
170 rc = 3;
171 break;
172 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
173 rc = 2;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
176 rc = 4;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 179 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 180 rc = 1;
181 break;
182 }
183
184 return rc;
185}
186
187/*
188 * HP's Diva chip puts the 4th/5th serial port further out, and
189 * some serial ports are supposed to be hidden on certain models.
190 */
191static int
975a1a7d
RK		 192pci_hp_diva_setup(struct serial_private *priv,
193 const struct pciserial_board *board,
194 struct uart_port *port, int idx)
1da177e4
LT		 195{
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
198
70db3d91 199 switch (priv->dev->subsystem_device) {
1da177e4
LT		 200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
201 if (idx == 3)
202 idx++;
203 break;
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
205 if (idx > 0)
206 idx++;
207 if (idx > 2)
208 idx++;
209 break;
210 }
211 if (idx > 2)
212 offset = 0x18;
213
214 offset += idx * board->uart_offset;
215
70db3d91 216 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 217}
218
219/*
220 * Added for EKF Intel i960 serial boards
221 */
61a116ef 222static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 223{
224 unsigned long oldval;
225
226 if (!(dev->subsystem_device & 0x1000))
227 return -ENODEV;
228
229 /* is firmware started? */
5756ee99
AC		 230 pci_read_config_dword(dev, 0x44, (void *)&oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
1da177e4
LT		 232 printk(KERN_DEBUG "Local i960 firmware missing");
233 return -ENODEV;
234 }
235 return 0;
236}
237
238/*
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
242 * mapped memory.
243 */
61a116ef 244static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 245{
246 u8 irq_config;
247 void __iomem *p;
248
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
251 return 0;
252 }
253
254 irq_config = 0x41;
add7b58e 255 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 257 irq_config = 0x43;
5756ee99 258
1da177e4 259 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 261 /*
262 * As the megawolf cards have the int pins active
263 * high, and have 2 UART chips, both ints must be
264 * enabled on the 9050. Also, the UARTS are set in
265 * 16450 mode by default, so we have to enable the
266 * 16C950 'enhanced' mode so that we can use the
267 * deep FIFOs
268 */
269 irq_config = 0x5b;
1da177e4
LT		 270 /*
271 * enable/disable interrupts
272 */
6f441fe9 273 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 274 if (p == NULL)
275 return -ENOMEM;
276 writel(irq_config, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283
284 return 0;
285}
286
287static void __devexit pci_plx9050_exit(struct pci_dev *dev)
288{
289 u8 __iomem *p;
290
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292 return;
293
294 /*
295 * disable interrupts
296 */
6f441fe9 297 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 298 if (p != NULL) {
299 writel(0, p + 0x4c);
300
301 /*
302 * Read the register back to ensure that it took effect.
303 */
304 readl(p + 0x4c);
305 iounmap(p);
306 }
307}
308
46a0fac9
SB		 309/* MITE registers */
310#define MITE_IOWBSR1 0xc4
311#define MITE_IOWCR1 0xf4
312#define MITE_LCIMR1 0x08
313#define MITE_LCIMR2 0x10
314
315#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
316
317static void __devexit pci_ni8430_exit(struct pci_dev *dev)
318{
319 void __iomem *p;
320 unsigned long base, len;
321 unsigned int bar = 0;
322
323 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
324 moan_device("no memory in bar", dev);
325 return;
326 }
327
328 base = pci_resource_start(dev, bar);
329 len = pci_resource_len(dev, bar);
330 p = ioremap_nocache(base, len);
331 if (p == NULL)
332 return;
333
334 /* Disable the CPU Interrupt */
335 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
336 iounmap(p);
337}
338
1da177e4
LT		 339/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
340static int
975a1a7d 341sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 342 struct uart_port *port, int idx)
343{
344 unsigned int bar, offset = board->first_offset;
345
346 bar = 0;
347
348 if (idx < 4) {
349 /* first four channels map to 0, 0x100, 0x200, 0x300 */
350 offset += idx * board->uart_offset;
351 } else if (idx < 8) {
352 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
353 offset += idx * board->uart_offset + 0xC00;
354 } else /* we have only 8 ports on PMC-OCTALPRO */
355 return 1;
356
70db3d91 357 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 358}
359
360/*
361* This does initialization for PMC OCTALPRO cards:
362* maps the device memory, resets the UARTs (needed, bc
363* if the module is removed and inserted again, the card
364* is in the sleep mode) and enables global interrupt.
365*/
366
367/* global control register offset for SBS PMC-OctalPro */
368#define OCT_REG_CR_OFF 0x500
369
61a116ef 370static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 371{
372 u8 __iomem *p;
373
6f441fe9
AC		 374 p = ioremap_nocache(pci_resource_start(dev, 0),
375 pci_resource_len(dev, 0));
1da177e4
LT		 376
377 if (p == NULL)
378 return -ENOMEM;
379 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 380 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 381 udelay(50);
5756ee99 382 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 383
384 /* Set bit-2 (INTENABLE) of Control Register */
385 writeb(0x4, p + OCT_REG_CR_OFF);
386 iounmap(p);
387
388 return 0;
389}
390
391/*
392 * Disables the global interrupt of PMC-OctalPro
393 */
394
395static void __devexit sbs_exit(struct pci_dev *dev)
396{
397 u8 __iomem *p;
398
6f441fe9
AC		 399 p = ioremap_nocache(pci_resource_start(dev, 0),
400 pci_resource_len(dev, 0));
5756ee99
AC		 401 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
402 if (p != NULL)
1da177e4 403 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 404 iounmap(p);
405}
406
407/*
408 * SIIG serial cards have an PCI interface chip which also controls
409 * the UART clocking frequency. Each UART can be clocked independently
410 * (except cards equiped with 4 UARTs) and initial clocking settings
411 * are stored in the EEPROM chip. It can cause problems because this
412 * version of serial driver doesn't support differently clocked UART's
413 * on single PCI card. To prevent this, initialization functions set
414 * high frequency clocking for all UART's on given card. It is safe (I
415 * hope) because it doesn't touch EEPROM settings to prevent conflicts
416 * with other OSes (like M$ DOS).
417 *
418 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 419 *
1da177e4
LT		 420 * There is two family of SIIG serial cards with different PCI
421 * interface chip and different configuration methods:
422 * - 10x cards have control registers in IO and/or memory space;
423 * - 20x cards have control registers in standard PCI configuration space.
424 *
67d74b87
RK		 425 * Note: all 10x cards have PCI device ids 0x10..
426 * all 20x cards have PCI device ids 0x20..
427 *
fbc0dc0d
AP		 428 * There are also Quartet Serial cards which use Oxford Semiconductor
429 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
430 *
1da177e4
LT		 431 * Note: some SIIG cards are probed by the parport_serial object.
432 */
433
434#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
435#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
436
437static int pci_siig10x_init(struct pci_dev *dev)
438{
439 u16 data;
440 void __iomem *p;
441
442 switch (dev->device & 0xfff8) {
443 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
444 data = 0xffdf;
445 break;
446 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
447 data = 0xf7ff;
448 break;
449 default: /* 1S1P, 4S */
450 data = 0xfffb;
451 break;
452 }
453
6f441fe9 454 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 455 if (p == NULL)
456 return -ENOMEM;
457
458 writew(readw(p + 0x28) & data, p + 0x28);
459 readw(p + 0x28);
460 iounmap(p);
461 return 0;
462}
463
464#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
465#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
466
467static int pci_siig20x_init(struct pci_dev *dev)
468{
469 u8 data;
470
471 /* Change clock frequency for the first UART. */
472 pci_read_config_byte(dev, 0x6f, &data);
473 pci_write_config_byte(dev, 0x6f, data & 0xef);
474
475 /* If this card has 2 UART, we have to do the same with second UART. */
476 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
477 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
478 pci_read_config_byte(dev, 0x73, &data);
479 pci_write_config_byte(dev, 0x73, data & 0xef);
480 }
481 return 0;
482}
483
67d74b87
RK		 484static int pci_siig_init(struct pci_dev *dev)
485{
486 unsigned int type = dev->device & 0xff00;
487
488 if (type == 0x1000)
489 return pci_siig10x_init(dev);
490 else if (type == 0x2000)
491 return pci_siig20x_init(dev);
492
493 moan_device("Unknown SIIG card", dev);
494 return -ENODEV;
495}
496
3ec9c594 497static int pci_siig_setup(struct serial_private *priv,
975a1a7d 498 const struct pciserial_board *board,
3ec9c594
AP		 499 struct uart_port *port, int idx)
500{
501 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
502
503 if (idx > 3) {
504 bar = 4;
505 offset = (idx - 4) * 8;
506 }
507
508 return setup_port(priv, port, bar, offset, 0);
509}
510
1da177e4
LT		 511/*
512 * Timedia has an explosion of boards, and to avoid the PCI table from
513 * growing *huge*, we use this function to collapse some 70 entries
514 * in the PCI table into one, for sanity's and compactness's sake.
515 */
e9422e09 516static const unsigned short timedia_single_port[] = {
1da177e4
LT		 517 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
518};
519
e9422e09 520static const unsigned short timedia_dual_port[] = {
1da177e4 521 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 522 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
523 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 524 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
525 0xD079, 0
526};
527
e9422e09 528static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 529 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
530 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 531 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
532 0xB157, 0
533};
534
e9422e09 535static const unsigned short timedia_eight_port[] = {
5756ee99 536 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 537 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
538};
539
cb3592be 540static const struct timedia_struct {
1da177e4 541 int num;
e9422e09 542 const unsigned short *ids;
1da177e4
LT		 543} timedia_data[] = {
544 { 1, timedia_single_port },
545 { 2, timedia_dual_port },
546 { 4, timedia_quad_port },
e9422e09 547 { 8, timedia_eight_port }
1da177e4
LT		 548};
549
61a116ef 550static int pci_timedia_init(struct pci_dev *dev)
1da177e4 551{
e9422e09 552 const unsigned short *ids;
1da177e4
LT		 553 int i, j;
554
e9422e09 555 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 556 ids = timedia_data[i].ids;
557 for (j = 0; ids[j]; j++)
558 if (dev->subsystem_device == ids[j])
559 return timedia_data[i].num;
560 }
561 return 0;
562}
563
564/*
565 * Timedia/SUNIX uses a mixture of BARs and offsets
566 * Ugh, this is ugly as all hell --- TYT
567 */
568static int
975a1a7d
RK		 569pci_timedia_setup(struct serial_private *priv,
570 const struct pciserial_board *board,
1da177e4
LT		 571 struct uart_port *port, int idx)
572{
573 unsigned int bar = 0, offset = board->first_offset;
574
575 switch (idx) {
576 case 0:
577 bar = 0;
578 break;
579 case 1:
580 offset = board->uart_offset;
581 bar = 0;
582 break;
583 case 2:
584 bar = 1;
585 break;
586 case 3:
587 offset = board->uart_offset;
c2cd6d3c 588 /* FALLTHROUGH */
1da177e4
LT		 589 case 4: /* BAR 2 */
590 case 5: /* BAR 3 */
591 case 6: /* BAR 4 */
592 case 7: /* BAR 5 */
593 bar = idx - 2;
594 }
595
70db3d91 596 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 597}
598
599/*
600 * Some Titan cards are also a little weird
601 */
602static int
70db3d91 603titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 604 const struct pciserial_board *board,
1da177e4
LT		 605 struct uart_port *port, int idx)
606{
607 unsigned int bar, offset = board->first_offset;
608
609 switch (idx) {
610 case 0:
611 bar = 1;
612 break;
613 case 1:
614 bar = 2;
615 break;
616 default:
617 bar = 4;
618 offset = (idx - 2) * board->uart_offset;
619 }
620
70db3d91 621 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 622}
623
61a116ef 624static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 625{
626 msleep(100);
627 return 0;
628}
629
46a0fac9
SB		 630#define MITE_IOWBSR1_WSIZE 0xa
631#define MITE_IOWBSR1_WIN_OFFSET 0x800
632#define MITE_IOWBSR1_WENAB (1 << 7)
633#define MITE_LCIMR1_IO_IE_0 (1 << 24)
634#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
635#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
636
637static int pci_ni8430_init(struct pci_dev *dev)
638{
639 void __iomem *p;
640 unsigned long base, len;
641 u32 device_window;
642 unsigned int bar = 0;
643
644 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
645 moan_device("no memory in bar", dev);
646 return 0;
647 }
648
649 base = pci_resource_start(dev, bar);
650 len = pci_resource_len(dev, bar);
651 p = ioremap_nocache(base, len);
652 if (p == NULL)
653 return -ENOMEM;
654
655 /* Set device window address and size in BAR0 */
656 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
657 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
658 writel(device_window, p + MITE_IOWBSR1);
659
660 /* Set window access to go to RAMSEL IO address space */
661 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
662 p + MITE_IOWCR1);
663
664 /* Enable IO Bus Interrupt 0 */
665 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
666
667 /* Enable CPU Interrupt */
668 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
669
670 iounmap(p);
671 return 0;
672}
673
674/* UART Port Control Register */
675#define NI8430_PORTCON 0x0f
676#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
677
678static int
679pci_ni8430_setup(struct serial_private *priv, struct pciserial_board *board,
680 struct uart_port *port, int idx)
681{
682 void __iomem *p;
683 unsigned long base, len;
684 unsigned int bar, offset = board->first_offset;
685
686 if (idx >= board->num_ports)
687 return 1;
688
689 bar = FL_GET_BASE(board->flags);
690 offset += idx * board->uart_offset;
691
692 base = pci_resource_start(priv->dev, bar);
693 len = pci_resource_len(priv->dev, bar);
694 p = ioremap_nocache(base, len);
695
696 /* enable the transciever */
697 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
698 p + offset + NI8430_PORTCON);
699
700 iounmap(p);
701
702 return setup_port(priv, port, bar, offset, board->reg_shift);
703}
704
705
61a116ef 706static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 707{
708 /* subdevice 0x00PS means <P> parallel, <S> serial */
709 unsigned int num_serial = dev->subsystem_device & 0xf;
710
25cf9bc1
JS		 711 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
712 dev->subsystem_device == 0x0299)
713 return 0;
714
1da177e4
LT		 715 if (num_serial == 0)
716 return -ENODEV;
717 return num_serial;
718}
719
84f8c6fc
NV		 720/*
721 * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
722 *
723 * These chips are available with optionally one parallel port and up to
724 * two serial ports. Unfortunately they all have the same product id.
725 *
726 * Basic configuration is done over a region of 32 I/O ports. The base
727 * ioport is called INTA or INTC, depending on docs/other drivers.
728 *
729 * The region of the 32 I/O ports is configured in POSIO0R...
730 */
731
732/* registers */
733#define ITE_887x_MISCR 0x9c
734#define ITE_887x_INTCBAR 0x78
735#define ITE_887x_UARTBAR 0x7c
736#define ITE_887x_PS0BAR 0x10
737#define ITE_887x_POSIO0 0x60
738
739/* I/O space size */
740#define ITE_887x_IOSIZE 32
741/* I/O space size (bits 26-24; 8 bytes = 011b) */
742#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
743/* I/O space size (bits 26-24; 32 bytes = 101b) */
744#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
745/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
746#define ITE_887x_POSIO_SPEED (3 << 29)
747/* enable IO_Space bit */
748#define ITE_887x_POSIO_ENABLE (1 << 31)
749
f79abb82 750static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 751{
752 /* inta_addr are the configuration addresses of the ITE */
753 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
754 0x200, 0x280, 0 };
755 int ret, i, type;
756 struct resource *iobase = NULL;
757 u32 miscr, uartbar, ioport;
758
759 /* search for the base-ioport */
760 i = 0;
761 while (inta_addr[i] && iobase == NULL) {
762 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
763 "ite887x");
764 if (iobase != NULL) {
765 /* write POSIO0R - speed | size | ioport */
766 pci_write_config_dword(dev, ITE_887x_POSIO0,
767 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
768 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
769 /* write INTCBAR - ioport */
5756ee99
AC		 770 pci_write_config_dword(dev, ITE_887x_INTCBAR,
771 inta_addr[i]);
84f8c6fc
NV		 772 ret = inb(inta_addr[i]);
773 if (ret != 0xff) {
774 /* ioport connected */
775 break;
776 }
777 release_region(iobase->start, ITE_887x_IOSIZE);
778 iobase = NULL;
779 }
780 i++;
781 }
782
783 if (!inta_addr[i]) {
784 printk(KERN_ERR "ite887x: could not find iobase\n");
785 return -ENODEV;
786 }
787
788 /* start of undocumented type checking (see parport_pc.c) */
789 type = inb(iobase->start + 0x18) & 0x0f;
790
791 switch (type) {
792 case 0x2: /* ITE8871 (1P) */
793 case 0xa: /* ITE8875 (1P) */
794 ret = 0;
795 break;
796 case 0xe: /* ITE8872 (2S1P) */
797 ret = 2;
798 break;
799 case 0x6: /* ITE8873 (1S) */
800 ret = 1;
801 break;
802 case 0x8: /* ITE8874 (2S) */
803 ret = 2;
804 break;
805 default:
806 moan_device("Unknown ITE887x", dev);
807 ret = -ENODEV;
808 }
809
810 /* configure all serial ports */
811 for (i = 0; i < ret; i++) {
812 /* read the I/O port from the device */
813 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
814 &ioport);
815 ioport &= 0x0000FF00; /* the actual base address */
816 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
817 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
818 ITE_887x_POSIO_IOSIZE_8 | ioport);
819
820 /* write the ioport to the UARTBAR */
821 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
822 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
823 uartbar |= (ioport << (16 * i)); /* set the ioport */
824 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
825
826 /* get current config */
827 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
828 /* disable interrupts (UARTx_Routing[3:0]) */
829 miscr &= ~(0xf << (12 - 4 * i));
830 /* activate the UART (UARTx_En) */
831 miscr |= 1 << (23 - i);
832 /* write new config with activated UART */
833 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
834 }
835
836 if (ret <= 0) {
837 /* the device has no UARTs if we get here */
838 release_region(iobase->start, ITE_887x_IOSIZE);
839 }
840
841 return ret;
842}
843
844static void __devexit pci_ite887x_exit(struct pci_dev *dev)
845{
846 u32 ioport;
847 /* the ioport is bit 0-15 in POSIO0R */
848 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
849 ioport &= 0xffff;
850 release_region(ioport, ITE_887x_IOSIZE);
851}
852
9f2a036a
RK		 853/*
854 * Oxford Semiconductor Inc.
855 * Check that device is part of the Tornado range of devices, then determine
856 * the number of ports available on the device.
857 */
858static int pci_oxsemi_tornado_init(struct pci_dev *dev)
859{
860 u8 __iomem *p;
861 unsigned long deviceID;
862 unsigned int number_uarts = 0;
863
864 /* OxSemi Tornado devices are all 0xCxxx */
865 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
866 (dev->device & 0xF000) != 0xC000)
867 return 0;
868
869 p = pci_iomap(dev, 0, 5);
870 if (p == NULL)
871 return -ENOMEM;
872
873 deviceID = ioread32(p);
874 /* Tornado device */
875 if (deviceID == 0x07000200) {
876 number_uarts = ioread8(p + 4);
877 printk(KERN_DEBUG
878 "%d ports detected on Oxford PCI Express device\n",
879 number_uarts);
880 }
881 pci_iounmap(dev, p);
882 return number_uarts;
883}
884
1da177e4 885static int
975a1a7d
RK		 886pci_default_setup(struct serial_private *priv,
887 const struct pciserial_board *board,
1da177e4
LT		 888 struct uart_port *port, int idx)
889{
890 unsigned int bar, offset = board->first_offset, maxnr;
891
892 bar = FL_GET_BASE(board->flags);
893 if (board->flags & FL_BASE_BARS)
894 bar += idx;
895 else
896 offset += idx * board->uart_offset;
897
2427ddd8
GKH		 898 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
899 (board->reg_shift + 3);
1da177e4
LT		 900
901 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
902 return 1;
5756ee99 903
70db3d91 904 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 905}
906
b6adea33
MCC		 907static int skip_tx_en_setup(struct serial_private *priv,
908 const struct pciserial_board *board,
909 struct uart_port *port, int idx)
910{
911 port->flags |= UPF_NO_TXEN_TEST;
912 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
913 "[%04x:%04x] subsystem [%04x:%04x]\n",
914 priv->dev->vendor,
915 priv->dev->device,
916 priv->dev->subsystem_vendor,
917 priv->dev->subsystem_device);
918
919 return pci_default_setup(priv, board, port, idx);
920}
921
1da177e4
LT		 922/* This should be in linux/pci_ids.h */
923#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
924#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
925#define PCI_DEVICE_ID_OCTPRO 0x0001
926#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
927#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
928#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
929#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
78d70d48
MB		 930#define PCI_VENDOR_ID_ADVANTECH 0x13fe
931#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1da177e4 932
b76c5a07
CB		 933/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
934#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
935
1da177e4
LT		 936/*
937 * Master list of serial port init/setup/exit quirks.
938 * This does not describe the general nature of the port.
939 * (ie, baud base, number and location of ports, etc)
940 *
941 * This list is ordered alphabetically by vendor then device.
942 * Specific entries must come before more generic entries.
943 */
7a63ce5a 944static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 945 /*
946 * ADDI-DATA GmbH communication cards <info@addi-data.com>
947 */
948 {
949 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
950 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
951 .subvendor = PCI_ANY_ID,
952 .subdevice = PCI_ANY_ID,
953 .setup = addidata_apci7800_setup,
954 },
1da177e4 955 /*
61a116ef 956 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 957 * It is not clear whether this applies to all products.
958 */
959 {
960 .vendor = PCI_VENDOR_ID_AFAVLAB,
961 .device = PCI_ANY_ID,
962 .subvendor = PCI_ANY_ID,
963 .subdevice = PCI_ANY_ID,
964 .setup = afavlab_setup,
965 },
966 /*
967 * HP Diva
968 */
969 {
970 .vendor = PCI_VENDOR_ID_HP,
971 .device = PCI_DEVICE_ID_HP_DIVA,
972 .subvendor = PCI_ANY_ID,
973 .subdevice = PCI_ANY_ID,
974 .init = pci_hp_diva_init,
975 .setup = pci_hp_diva_setup,
976 },
977 /*
978 * Intel
979 */
980 {
981 .vendor = PCI_VENDOR_ID_INTEL,
982 .device = PCI_DEVICE_ID_INTEL_80960_RP,
983 .subvendor = 0xe4bf,
984 .subdevice = PCI_ANY_ID,
985 .init = pci_inteli960ni_init,
986 .setup = pci_default_setup,
987 },
b6adea33
MCC		 988 {
989 .vendor = PCI_VENDOR_ID_INTEL,
990 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
991 .subvendor = PCI_ANY_ID,
992 .subdevice = PCI_ANY_ID,
993 .setup = skip_tx_en_setup,
994 },
995 {
996 .vendor = PCI_VENDOR_ID_INTEL,
997 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
998 .subvendor = PCI_ANY_ID,
999 .subdevice = PCI_ANY_ID,
1000 .setup = skip_tx_en_setup,
1001 },
1002 {
1003 .vendor = PCI_VENDOR_ID_INTEL,
1004 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1005 .subvendor = PCI_ANY_ID,
1006 .subdevice = PCI_ANY_ID,
1007 .setup = skip_tx_en_setup,
1008 },
84f8c6fc
NV		 1009 /*
1010 * ITE
1011 */
1012 {
1013 .vendor = PCI_VENDOR_ID_ITE,
1014 .device = PCI_DEVICE_ID_ITE_8872,
1015 .subvendor = PCI_ANY_ID,
1016 .subdevice = PCI_ANY_ID,
1017 .init = pci_ite887x_init,
1018 .setup = pci_default_setup,
1019 .exit = __devexit_p(pci_ite887x_exit),
1020 },
46a0fac9
SB		 1021 /*
1022 * National Instruments
1023 */
1024 {
1025 .vendor = PCI_VENDOR_ID_NI,
1026 .device = PCI_ANY_ID,
1027 .subvendor = PCI_ANY_ID,
1028 .subdevice = PCI_ANY_ID,
1029 .init = pci_ni8430_init,
1030 .setup = pci_ni8430_setup,
1031 .exit = __devexit_p(pci_ni8430_exit),
1032 },
1da177e4
LT		 1033 /*
1034 * Panacom
1035 */
1036 {
1037 .vendor = PCI_VENDOR_ID_PANACOM,
1038 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1039 .subvendor = PCI_ANY_ID,
1040 .subdevice = PCI_ANY_ID,
1041 .init = pci_plx9050_init,
1042 .setup = pci_default_setup,
1043 .exit = __devexit_p(pci_plx9050_exit),
5756ee99 1044 },
1da177e4
LT		 1045 {
1046 .vendor = PCI_VENDOR_ID_PANACOM,
1047 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1048 .subvendor = PCI_ANY_ID,
1049 .subdevice = PCI_ANY_ID,
1050 .init = pci_plx9050_init,
1051 .setup = pci_default_setup,
1052 .exit = __devexit_p(pci_plx9050_exit),
1053 },
1054 /*
1055 * PLX
1056 */
48212008
TH		 1057 {
1058 .vendor = PCI_VENDOR_ID_PLX,
1059 .device = PCI_DEVICE_ID_PLX_9030,
1060 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1061 .subdevice = PCI_ANY_ID,
1062 .setup = pci_default_setup,
1063 },
add7b58e
BH		 1064 {
1065 .vendor = PCI_VENDOR_ID_PLX,
1066 .device = PCI_DEVICE_ID_PLX_9050,
1067 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1068 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1069 .init = pci_plx9050_init,
1070 .setup = pci_default_setup,
1071 .exit = __devexit_p(pci_plx9050_exit),
1072 },
1da177e4
LT		 1073 {
1074 .vendor = PCI_VENDOR_ID_PLX,
1075 .device = PCI_DEVICE_ID_PLX_9050,
1076 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1077 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1078 .init = pci_plx9050_init,
1079 .setup = pci_default_setup,
1080 .exit = __devexit_p(pci_plx9050_exit),
1081 },
b76c5a07
CB		 1082 {
1083 .vendor = PCI_VENDOR_ID_PLX,
1084 .device = PCI_DEVICE_ID_PLX_9050,
1085 .subvendor = PCI_VENDOR_ID_PLX,
1086 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1087 .init = pci_plx9050_init,
1088 .setup = pci_default_setup,
1089 .exit = __devexit_p(pci_plx9050_exit),
1090 },
1da177e4
LT		 1091 {
1092 .vendor = PCI_VENDOR_ID_PLX,
1093 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1094 .subvendor = PCI_VENDOR_ID_PLX,
1095 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1096 .init = pci_plx9050_init,
1097 .setup = pci_default_setup,
1098 .exit = __devexit_p(pci_plx9050_exit),
1099 },
1100 /*
1101 * SBS Technologies, Inc., PMC-OCTALPRO 232
1102 */
1103 {
1104 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1105 .device = PCI_DEVICE_ID_OCTPRO,
1106 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1107 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1108 .init = sbs_init,
1109 .setup = sbs_setup,
1110 .exit = __devexit_p(sbs_exit),
1111 },
1112 /*
1113 * SBS Technologies, Inc., PMC-OCTALPRO 422
1114 */
1115 {
1116 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1117 .device = PCI_DEVICE_ID_OCTPRO,
1118 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1119 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1120 .init = sbs_init,
1121 .setup = sbs_setup,
1122 .exit = __devexit_p(sbs_exit),
1123 },
1124 /*
1125 * SBS Technologies, Inc., P-Octal 232
1126 */
1127 {
1128 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1129 .device = PCI_DEVICE_ID_OCTPRO,
1130 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1131 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1132 .init = sbs_init,
1133 .setup = sbs_setup,
1134 .exit = __devexit_p(sbs_exit),
1135 },
1136 /*
1137 * SBS Technologies, Inc., P-Octal 422
1138 */
1139 {
1140 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1141 .device = PCI_DEVICE_ID_OCTPRO,
1142 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1143 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1144 .init = sbs_init,
1145 .setup = sbs_setup,
1146 .exit = __devexit_p(sbs_exit),
1147 },
1da177e4 1148 /*
61a116ef 1149 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 1150 */
1151 {
1152 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 1153 .device = PCI_ANY_ID,
1da177e4
LT		 1154 .subvendor = PCI_ANY_ID,
1155 .subdevice = PCI_ANY_ID,
67d74b87 1156 .init = pci_siig_init,
3ec9c594 1157 .setup = pci_siig_setup,
1da177e4
LT		 1158 },
1159 /*
1160 * Titan cards
1161 */
1162 {
1163 .vendor = PCI_VENDOR_ID_TITAN,
1164 .device = PCI_DEVICE_ID_TITAN_400L,
1165 .subvendor = PCI_ANY_ID,
1166 .subdevice = PCI_ANY_ID,
1167 .setup = titan_400l_800l_setup,
1168 },
1169 {
1170 .vendor = PCI_VENDOR_ID_TITAN,
1171 .device = PCI_DEVICE_ID_TITAN_800L,
1172 .subvendor = PCI_ANY_ID,
1173 .subdevice = PCI_ANY_ID,
1174 .setup = titan_400l_800l_setup,
1175 },
1176 /*
1177 * Timedia cards
1178 */
1179 {
1180 .vendor = PCI_VENDOR_ID_TIMEDIA,
1181 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1182 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1183 .subdevice = PCI_ANY_ID,
1184 .init = pci_timedia_init,
1185 .setup = pci_timedia_setup,
1186 },
1187 {
1188 .vendor = PCI_VENDOR_ID_TIMEDIA,
1189 .device = PCI_ANY_ID,
1190 .subvendor = PCI_ANY_ID,
1191 .subdevice = PCI_ANY_ID,
1192 .setup = pci_timedia_setup,
1193 },
1194 /*
1195 * Xircom cards
1196 */
1197 {
1198 .vendor = PCI_VENDOR_ID_XIRCOM,
1199 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1200 .subvendor = PCI_ANY_ID,
1201 .subdevice = PCI_ANY_ID,
1202 .init = pci_xircom_init,
1203 .setup = pci_default_setup,
1204 },
1205 /*
61a116ef 1206 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 1207 */
1208 {
1209 .vendor = PCI_VENDOR_ID_NETMOS,
1210 .device = PCI_ANY_ID,
1211 .subvendor = PCI_ANY_ID,
1212 .subdevice = PCI_ANY_ID,
1213 .init = pci_netmos_init,
1214 .setup = pci_default_setup,
1215 },
9f2a036a
RK		 1216 /*
1217 * For Oxford Semiconductor and Mainpine
1218 */
1219 {
1220 .vendor = PCI_VENDOR_ID_OXSEMI,
1221 .device = PCI_ANY_ID,
1222 .subvendor = PCI_ANY_ID,
1223 .subdevice = PCI_ANY_ID,
1224 .init = pci_oxsemi_tornado_init,
1225 .setup = pci_default_setup,
1226 },
1227 {
1228 .vendor = PCI_VENDOR_ID_MAINPINE,
1229 .device = PCI_ANY_ID,
1230 .subvendor = PCI_ANY_ID,
1231 .subdevice = PCI_ANY_ID,
1232 .init = pci_oxsemi_tornado_init,
1233 .setup = pci_default_setup,
1234 },
1da177e4
LT		 1235 /*
1236 * Default "match everything" terminator entry
1237 */
1238 {
1239 .vendor = PCI_ANY_ID,
1240 .device = PCI_ANY_ID,
1241 .subvendor = PCI_ANY_ID,
1242 .subdevice = PCI_ANY_ID,
1243 .setup = pci_default_setup,
1244 }
1245};
1246
1247static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1248{
1249 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1250}
1251
1252static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1253{
1254 struct pci_serial_quirk *quirk;
1255
1256 for (quirk = pci_serial_quirks; ; quirk++)
1257 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1258 quirk_id_matches(quirk->device, dev->device) &&
1259 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1260 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 1261 break;
1da177e4
LT		 1262 return quirk;
1263}
1264
dd68e88c 1265static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 1266 const struct pciserial_board *board)
1da177e4
LT		 1267{
1268 if (board->flags & FL_NOIRQ)
1269 return 0;
1270 else
1271 return dev->irq;
1272}
1273
1274/*
1275 * This is the configuration table for all of the PCI serial boards
1276 * which we support. It is directly indexed by the pci_board_num_t enum
1277 * value, which is encoded in the pci_device_id PCI probe table's
1278 * driver_data member.
1279 *
1280 * The makeup of these names are:
26e92861 1281 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 1282 *
26e92861
GH		 1283 * bn = PCI BAR number
1284 * bt = Index using PCI BARs
1285 * n = number of serial ports
1286 * baud = baud rate
1287 * offsetinhex = offset for each sequential port (in hex)
1da177e4 1288 *
26e92861 1289 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 1290 *
1da177e4
LT		 1291 * Please note: in theory if n = 1, _bt infix should make no difference.
1292 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1293 */
1294enum pci_board_num_t {
1295 pbn_default = 0,
1296
1297 pbn_b0_1_115200,
1298 pbn_b0_2_115200,
1299 pbn_b0_4_115200,
1300 pbn_b0_5_115200,
bf0df636 1301 pbn_b0_8_115200,
1da177e4
LT		 1302
1303 pbn_b0_1_921600,
1304 pbn_b0_2_921600,
1305 pbn_b0_4_921600,
1306
db1de159
DR		 1307 pbn_b0_2_1130000,
1308
fbc0dc0d
AP		 1309 pbn_b0_4_1152000,
1310
26e92861
GH		 1311 pbn_b0_2_1843200,
1312 pbn_b0_4_1843200,
1313
1314 pbn_b0_2_1843200_200,
1315 pbn_b0_4_1843200_200,
1316 pbn_b0_8_1843200_200,
1317
7106b4e3
LH		 1318 pbn_b0_1_4000000,
1319
1da177e4
LT		 1320 pbn_b0_bt_1_115200,
1321 pbn_b0_bt_2_115200,
1322 pbn_b0_bt_8_115200,
1323
1324 pbn_b0_bt_1_460800,
1325 pbn_b0_bt_2_460800,
1326 pbn_b0_bt_4_460800,
1327
1328 pbn_b0_bt_1_921600,
1329 pbn_b0_bt_2_921600,
1330 pbn_b0_bt_4_921600,
1331 pbn_b0_bt_8_921600,
1332
1333 pbn_b1_1_115200,
1334 pbn_b1_2_115200,
1335 pbn_b1_4_115200,
1336 pbn_b1_8_115200,
1337
1338 pbn_b1_1_921600,
1339 pbn_b1_2_921600,
1340 pbn_b1_4_921600,
1341 pbn_b1_8_921600,
1342
26e92861
GH		 1343 pbn_b1_2_1250000,
1344
84f8c6fc 1345 pbn_b1_bt_1_115200,
1da177e4
LT		 1346 pbn_b1_bt_2_921600,
1347
1348 pbn_b1_1_1382400,
1349 pbn_b1_2_1382400,
1350 pbn_b1_4_1382400,
1351 pbn_b1_8_1382400,
1352
1353 pbn_b2_1_115200,
737c1756 1354 pbn_b2_2_115200,
a9cccd34 1355 pbn_b2_4_115200,
1da177e4
LT		 1356 pbn_b2_8_115200,
1357
1358 pbn_b2_1_460800,
1359 pbn_b2_4_460800,
1360 pbn_b2_8_460800,
1361 pbn_b2_16_460800,
1362
1363 pbn_b2_1_921600,
1364 pbn_b2_4_921600,
1365 pbn_b2_8_921600,
1366
1367 pbn_b2_bt_1_115200,
1368 pbn_b2_bt_2_115200,
1369 pbn_b2_bt_4_115200,
1370
1371 pbn_b2_bt_2_921600,
1372 pbn_b2_bt_4_921600,
1373
d9004eb4 1374 pbn_b3_2_115200,
1da177e4
LT		 1375 pbn_b3_4_115200,
1376 pbn_b3_8_115200,
1377
1378 /*
1379 * Board-specific versions.
1380 */
1381 pbn_panacom,
1382 pbn_panacom2,
1383 pbn_panacom4,
add7b58e 1384 pbn_exsys_4055,
1da177e4
LT		 1385 pbn_plx_romulus,
1386 pbn_oxsemi,
7106b4e3
LH		 1387 pbn_oxsemi_1_4000000,
1388 pbn_oxsemi_2_4000000,
1389 pbn_oxsemi_4_4000000,
1390 pbn_oxsemi_8_4000000,
1da177e4
LT		 1391 pbn_intel_i960,
1392 pbn_sgi_ioc3,
1da177e4
LT		 1393 pbn_computone_4,
1394 pbn_computone_6,
1395 pbn_computone_8,
1396 pbn_sbsxrsio,
1397 pbn_exar_XR17C152,
1398 pbn_exar_XR17C154,
1399 pbn_exar_XR17C158,
aa798505 1400 pbn_pasemi_1682M,
46a0fac9
SB		 1401 pbn_ni8430_2,
1402 pbn_ni8430_4,
1403 pbn_ni8430_8,
1404 pbn_ni8430_16,
1da177e4
LT		 1405};
1406
1407/*
1408 * uart_offset - the space between channels
1409 * reg_shift - describes how the UART registers are mapped
1410 * to PCI memory by the card.
1411 * For example IER register on SBS, Inc. PMC-OctPro is located at
1412 * offset 0x10 from the UART base, while UART_IER is defined as 1
1413 * in include/linux/serial_reg.h,
1414 * see first lines of serial_in() and serial_out() in 8250.c
1415*/
1416
1c7c1fe5 1417static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 1418 [pbn_default] = {
1419 .flags = FL_BASE0,
1420 .num_ports = 1,
1421 .base_baud = 115200,
1422 .uart_offset = 8,
1423 },
1424 [pbn_b0_1_115200] = {
1425 .flags = FL_BASE0,
1426 .num_ports = 1,
1427 .base_baud = 115200,
1428 .uart_offset = 8,
1429 },
1430 [pbn_b0_2_115200] = {
1431 .flags = FL_BASE0,
1432 .num_ports = 2,
1433 .base_baud = 115200,
1434 .uart_offset = 8,
1435 },
1436 [pbn_b0_4_115200] = {
1437 .flags = FL_BASE0,
1438 .num_ports = 4,
1439 .base_baud = 115200,
1440 .uart_offset = 8,
1441 },
1442 [pbn_b0_5_115200] = {
1443 .flags = FL_BASE0,
1444 .num_ports = 5,
1445 .base_baud = 115200,
1446 .uart_offset = 8,
1447 },
bf0df636
AC		 1448 [pbn_b0_8_115200] = {
1449 .flags = FL_BASE0,
1450 .num_ports = 8,
1451 .base_baud = 115200,
1452 .uart_offset = 8,
1453 },
1da177e4
LT		 1454 [pbn_b0_1_921600] = {
1455 .flags = FL_BASE0,
1456 .num_ports = 1,
1457 .base_baud = 921600,
1458 .uart_offset = 8,
1459 },
1460 [pbn_b0_2_921600] = {
1461 .flags = FL_BASE0,
1462 .num_ports = 2,
1463 .base_baud = 921600,
1464 .uart_offset = 8,
1465 },
1466 [pbn_b0_4_921600] = {
1467 .flags = FL_BASE0,
1468 .num_ports = 4,
1469 .base_baud = 921600,
1470 .uart_offset = 8,
1471 },
db1de159
DR		 1472
1473 [pbn_b0_2_1130000] = {
1474 .flags = FL_BASE0,
1475 .num_ports = 2,
1476 .base_baud = 1130000,
1477 .uart_offset = 8,
1478 },
1479
fbc0dc0d
AP		 1480 [pbn_b0_4_1152000] = {
1481 .flags = FL_BASE0,
1482 .num_ports = 4,
1483 .base_baud = 1152000,
1484 .uart_offset = 8,
1485 },
1da177e4 1486
26e92861
GH		 1487 [pbn_b0_2_1843200] = {
1488 .flags = FL_BASE0,
1489 .num_ports = 2,
1490 .base_baud = 1843200,
1491 .uart_offset = 8,
1492 },
1493 [pbn_b0_4_1843200] = {
1494 .flags = FL_BASE0,
1495 .num_ports = 4,
1496 .base_baud = 1843200,
1497 .uart_offset = 8,
1498 },
1499
1500 [pbn_b0_2_1843200_200] = {
1501 .flags = FL_BASE0,
1502 .num_ports = 2,
1503 .base_baud = 1843200,
1504 .uart_offset = 0x200,
1505 },
1506 [pbn_b0_4_1843200_200] = {
1507 .flags = FL_BASE0,
1508 .num_ports = 4,
1509 .base_baud = 1843200,
1510 .uart_offset = 0x200,
1511 },
1512 [pbn_b0_8_1843200_200] = {
1513 .flags = FL_BASE0,
1514 .num_ports = 8,
1515 .base_baud = 1843200,
1516 .uart_offset = 0x200,
1517 },
7106b4e3
LH		 1518 [pbn_b0_1_4000000] = {
1519 .flags = FL_BASE0,
1520 .num_ports = 1,
1521 .base_baud = 4000000,
1522 .uart_offset = 8,
1523 },
26e92861 1524
1da177e4
LT		 1525 [pbn_b0_bt_1_115200] = {
1526 .flags = FL_BASE0|FL_BASE_BARS,
1527 .num_ports = 1,
1528 .base_baud = 115200,
1529 .uart_offset = 8,
1530 },
1531 [pbn_b0_bt_2_115200] = {
1532 .flags = FL_BASE0|FL_BASE_BARS,
1533 .num_ports = 2,
1534 .base_baud = 115200,
1535 .uart_offset = 8,
1536 },
1537 [pbn_b0_bt_8_115200] = {
1538 .flags = FL_BASE0|FL_BASE_BARS,
1539 .num_ports = 8,
1540 .base_baud = 115200,
1541 .uart_offset = 8,
1542 },
1543
1544 [pbn_b0_bt_1_460800] = {
1545 .flags = FL_BASE0|FL_BASE_BARS,
1546 .num_ports = 1,
1547 .base_baud = 460800,
1548 .uart_offset = 8,
1549 },
1550 [pbn_b0_bt_2_460800] = {
1551 .flags = FL_BASE0|FL_BASE_BARS,
1552 .num_ports = 2,
1553 .base_baud = 460800,
1554 .uart_offset = 8,
1555 },
1556 [pbn_b0_bt_4_460800] = {
1557 .flags = FL_BASE0|FL_BASE_BARS,
1558 .num_ports = 4,
1559 .base_baud = 460800,
1560 .uart_offset = 8,
1561 },
1562
1563 [pbn_b0_bt_1_921600] = {
1564 .flags = FL_BASE0|FL_BASE_BARS,
1565 .num_ports = 1,
1566 .base_baud = 921600,
1567 .uart_offset = 8,
1568 },
1569 [pbn_b0_bt_2_921600] = {
1570 .flags = FL_BASE0|FL_BASE_BARS,
1571 .num_ports = 2,
1572 .base_baud = 921600,
1573 .uart_offset = 8,
1574 },
1575 [pbn_b0_bt_4_921600] = {
1576 .flags = FL_BASE0|FL_BASE_BARS,
1577 .num_ports = 4,
1578 .base_baud = 921600,
1579 .uart_offset = 8,
1580 },
1581 [pbn_b0_bt_8_921600] = {
1582 .flags = FL_BASE0|FL_BASE_BARS,
1583 .num_ports = 8,
1584 .base_baud = 921600,
1585 .uart_offset = 8,
1586 },
1587
1588 [pbn_b1_1_115200] = {
1589 .flags = FL_BASE1,
1590 .num_ports = 1,
1591 .base_baud = 115200,
1592 .uart_offset = 8,
1593 },
1594 [pbn_b1_2_115200] = {
1595 .flags = FL_BASE1,
1596 .num_ports = 2,
1597 .base_baud = 115200,
1598 .uart_offset = 8,
1599 },
1600 [pbn_b1_4_115200] = {
1601 .flags = FL_BASE1,
1602 .num_ports = 4,
1603 .base_baud = 115200,
1604 .uart_offset = 8,
1605 },
1606 [pbn_b1_8_115200] = {
1607 .flags = FL_BASE1,
1608 .num_ports = 8,
1609 .base_baud = 115200,
1610 .uart_offset = 8,
1611 },
1612
1613 [pbn_b1_1_921600] = {
1614 .flags = FL_BASE1,
1615 .num_ports = 1,
1616 .base_baud = 921600,
1617 .uart_offset = 8,
1618 },
1619 [pbn_b1_2_921600] = {
1620 .flags = FL_BASE1,
1621 .num_ports = 2,
1622 .base_baud = 921600,
1623 .uart_offset = 8,
1624 },
1625 [pbn_b1_4_921600] = {
1626 .flags = FL_BASE1,
1627 .num_ports = 4,
1628 .base_baud = 921600,
1629 .uart_offset = 8,
1630 },
1631 [pbn_b1_8_921600] = {
1632 .flags = FL_BASE1,
1633 .num_ports = 8,
1634 .base_baud = 921600,
1635 .uart_offset = 8,
1636 },
26e92861
GH		 1637 [pbn_b1_2_1250000] = {
1638 .flags = FL_BASE1,
1639 .num_ports = 2,
1640 .base_baud = 1250000,
1641 .uart_offset = 8,
1642 },
1da177e4 1643
84f8c6fc
NV		 1644 [pbn_b1_bt_1_115200] = {
1645 .flags = FL_BASE1|FL_BASE_BARS,
1646 .num_ports = 1,
1647 .base_baud = 115200,
1648 .uart_offset = 8,
1649 },
1650
1da177e4
LT		 1651 [pbn_b1_bt_2_921600] = {
1652 .flags = FL_BASE1|FL_BASE_BARS,
1653 .num_ports = 2,
1654 .base_baud = 921600,
1655 .uart_offset = 8,
1656 },
1657
1658 [pbn_b1_1_1382400] = {
1659 .flags = FL_BASE1,
1660 .num_ports = 1,
1661 .base_baud = 1382400,
1662 .uart_offset = 8,
1663 },
1664 [pbn_b1_2_1382400] = {
1665 .flags = FL_BASE1,
1666 .num_ports = 2,
1667 .base_baud = 1382400,
1668 .uart_offset = 8,
1669 },
1670 [pbn_b1_4_1382400] = {
1671 .flags = FL_BASE1,
1672 .num_ports = 4,
1673 .base_baud = 1382400,
1674 .uart_offset = 8,
1675 },
1676 [pbn_b1_8_1382400] = {
1677 .flags = FL_BASE1,
1678 .num_ports = 8,
1679 .base_baud = 1382400,
1680 .uart_offset = 8,
1681 },
1682
1683 [pbn_b2_1_115200] = {
1684 .flags = FL_BASE2,
1685 .num_ports = 1,
1686 .base_baud = 115200,
1687 .uart_offset = 8,
1688 },
737c1756
PH		 1689 [pbn_b2_2_115200] = {
1690 .flags = FL_BASE2,
1691 .num_ports = 2,
1692 .base_baud = 115200,
1693 .uart_offset = 8,
1694 },
a9cccd34
MF		 1695 [pbn_b2_4_115200] = {
1696 .flags = FL_BASE2,
1697 .num_ports = 4,
1698 .base_baud = 115200,
1699 .uart_offset = 8,
1700 },
1da177e4
LT		 1701 [pbn_b2_8_115200] = {
1702 .flags = FL_BASE2,
1703 .num_ports = 8,
1704 .base_baud = 115200,
1705 .uart_offset = 8,
1706 },
1707
1708 [pbn_b2_1_460800] = {
1709 .flags = FL_BASE2,
1710 .num_ports = 1,
1711 .base_baud = 460800,
1712 .uart_offset = 8,
1713 },
1714 [pbn_b2_4_460800] = {
1715 .flags = FL_BASE2,
1716 .num_ports = 4,
1717 .base_baud = 460800,
1718 .uart_offset = 8,
1719 },
1720 [pbn_b2_8_460800] = {
1721 .flags = FL_BASE2,
1722 .num_ports = 8,
1723 .base_baud = 460800,
1724 .uart_offset = 8,
1725 },
1726 [pbn_b2_16_460800] = {
1727 .flags = FL_BASE2,
1728 .num_ports = 16,
1729 .base_baud = 460800,
1730 .uart_offset = 8,
1731 },
1732
1733 [pbn_b2_1_921600] = {
1734 .flags = FL_BASE2,
1735 .num_ports = 1,
1736 .base_baud = 921600,
1737 .uart_offset = 8,
1738 },
1739 [pbn_b2_4_921600] = {
1740 .flags = FL_BASE2,
1741 .num_ports = 4,
1742 .base_baud = 921600,
1743 .uart_offset = 8,
1744 },
1745 [pbn_b2_8_921600] = {
1746 .flags = FL_BASE2,
1747 .num_ports = 8,
1748 .base_baud = 921600,
1749 .uart_offset = 8,
1750 },
1751
1752 [pbn_b2_bt_1_115200] = {
1753 .flags = FL_BASE2|FL_BASE_BARS,
1754 .num_ports = 1,
1755 .base_baud = 115200,
1756 .uart_offset = 8,
1757 },
1758 [pbn_b2_bt_2_115200] = {
1759 .flags = FL_BASE2|FL_BASE_BARS,
1760 .num_ports = 2,
1761 .base_baud = 115200,
1762 .uart_offset = 8,
1763 },
1764 [pbn_b2_bt_4_115200] = {
1765 .flags = FL_BASE2|FL_BASE_BARS,
1766 .num_ports = 4,
1767 .base_baud = 115200,
1768 .uart_offset = 8,
1769 },
1770
1771 [pbn_b2_bt_2_921600] = {
1772 .flags = FL_BASE2|FL_BASE_BARS,
1773 .num_ports = 2,
1774 .base_baud = 921600,
1775 .uart_offset = 8,
1776 },
1777 [pbn_b2_bt_4_921600] = {
1778 .flags = FL_BASE2|FL_BASE_BARS,
1779 .num_ports = 4,
1780 .base_baud = 921600,
1781 .uart_offset = 8,
1782 },
1783
d9004eb4
ABL		 1784 [pbn_b3_2_115200] = {
1785 .flags = FL_BASE3,
1786 .num_ports = 2,
1787 .base_baud = 115200,
1788 .uart_offset = 8,
1789 },
1da177e4
LT		 1790 [pbn_b3_4_115200] = {
1791 .flags = FL_BASE3,
1792 .num_ports = 4,
1793 .base_baud = 115200,
1794 .uart_offset = 8,
1795 },
1796 [pbn_b3_8_115200] = {
1797 .flags = FL_BASE3,
1798 .num_ports = 8,
1799 .base_baud = 115200,
1800 .uart_offset = 8,
1801 },
1802
1803 /*
1804 * Entries following this are board-specific.
1805 */
1806
1807 /*
1808 * Panacom - IOMEM
1809 */
1810 [pbn_panacom] = {
1811 .flags = FL_BASE2,
1812 .num_ports = 2,
1813 .base_baud = 921600,
1814 .uart_offset = 0x400,
1815 .reg_shift = 7,
1816 },
1817 [pbn_panacom2] = {
1818 .flags = FL_BASE2|FL_BASE_BARS,
1819 .num_ports = 2,
1820 .base_baud = 921600,
1821 .uart_offset = 0x400,
1822 .reg_shift = 7,
1823 },
1824 [pbn_panacom4] = {
1825 .flags = FL_BASE2|FL_BASE_BARS,
1826 .num_ports = 4,
1827 .base_baud = 921600,
1828 .uart_offset = 0x400,
1829 .reg_shift = 7,
1830 },
1831
add7b58e
BH		 1832 [pbn_exsys_4055] = {
1833 .flags = FL_BASE2,
1834 .num_ports = 4,
1835 .base_baud = 115200,
1836 .uart_offset = 8,
1837 },
1838
1da177e4
LT		 1839 /* I think this entry is broken - the first_offset looks wrong --rmk */
1840 [pbn_plx_romulus] = {
1841 .flags = FL_BASE2,
1842 .num_ports = 4,
1843 .base_baud = 921600,
1844 .uart_offset = 8 << 2,
1845 .reg_shift = 2,
1846 .first_offset = 0x03,
1847 },
1848
1849 /*
1850 * This board uses the size of PCI Base region 0 to
1851 * signal now many ports are available
1852 */
1853 [pbn_oxsemi] = {
1854 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1855 .num_ports = 32,
1856 .base_baud = 115200,
1857 .uart_offset = 8,
1858 },
7106b4e3
LH		 1859 [pbn_oxsemi_1_4000000] = {
1860 .flags = FL_BASE0,
1861 .num_ports = 1,
1862 .base_baud = 4000000,
1863 .uart_offset = 0x200,
1864 .first_offset = 0x1000,
1865 },
1866 [pbn_oxsemi_2_4000000] = {
1867 .flags = FL_BASE0,
1868 .num_ports = 2,
1869 .base_baud = 4000000,
1870 .uart_offset = 0x200,
1871 .first_offset = 0x1000,
1872 },
1873 [pbn_oxsemi_4_4000000] = {
1874 .flags = FL_BASE0,
1875 .num_ports = 4,
1876 .base_baud = 4000000,
1877 .uart_offset = 0x200,
1878 .first_offset = 0x1000,
1879 },
1880 [pbn_oxsemi_8_4000000] = {
1881 .flags = FL_BASE0,
1882 .num_ports = 8,
1883 .base_baud = 4000000,
1884 .uart_offset = 0x200,
1885 .first_offset = 0x1000,
1886 },
1887
1da177e4
LT		 1888
1889 /*
1890 * EKF addition for i960 Boards form EKF with serial port.
1891 * Max 256 ports.
1892 */
1893 [pbn_intel_i960] = {
1894 .flags = FL_BASE0,
1895 .num_ports = 32,
1896 .base_baud = 921600,
1897 .uart_offset = 8 << 2,
1898 .reg_shift = 2,
1899 .first_offset = 0x10000,
1900 },
1901 [pbn_sgi_ioc3] = {
1902 .flags = FL_BASE0|FL_NOIRQ,
1903 .num_ports = 1,
1904 .base_baud = 458333,
1905 .uart_offset = 8,
1906 .reg_shift = 0,
1907 .first_offset = 0x20178,
1908 },
1909
1da177e4
LT		 1910 /*
1911 * Computone - uses IOMEM.
1912 */
1913 [pbn_computone_4] = {
1914 .flags = FL_BASE0,
1915 .num_ports = 4,
1916 .base_baud = 921600,
1917 .uart_offset = 0x40,
1918 .reg_shift = 2,
1919 .first_offset = 0x200,
1920 },
1921 [pbn_computone_6] = {
1922 .flags = FL_BASE0,
1923 .num_ports = 6,
1924 .base_baud = 921600,
1925 .uart_offset = 0x40,
1926 .reg_shift = 2,
1927 .first_offset = 0x200,
1928 },
1929 [pbn_computone_8] = {
1930 .flags = FL_BASE0,
1931 .num_ports = 8,
1932 .base_baud = 921600,
1933 .uart_offset = 0x40,
1934 .reg_shift = 2,
1935 .first_offset = 0x200,
1936 },
1937 [pbn_sbsxrsio] = {
1938 .flags = FL_BASE0,
1939 .num_ports = 8,
1940 .base_baud = 460800,
1941 .uart_offset = 256,
1942 .reg_shift = 4,
1943 },
1944 /*
1945 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1946 * Only basic 16550A support.
1947 * XR17C15[24] are not tested, but they should work.
1948 */
1949 [pbn_exar_XR17C152] = {
1950 .flags = FL_BASE0,
1951 .num_ports = 2,
1952 .base_baud = 921600,
1953 .uart_offset = 0x200,
1954 },
1955 [pbn_exar_XR17C154] = {
1956 .flags = FL_BASE0,
1957 .num_ports = 4,
1958 .base_baud = 921600,
1959 .uart_offset = 0x200,
1960 },
1961 [pbn_exar_XR17C158] = {
1962 .flags = FL_BASE0,
1963 .num_ports = 8,
1964 .base_baud = 921600,
1965 .uart_offset = 0x200,
1966 },
aa798505
OJ		 1967 /*
1968 * PA Semi PWRficient PA6T-1682M on-chip UART
1969 */
1970 [pbn_pasemi_1682M] = {
1971 .flags = FL_BASE0,
1972 .num_ports = 1,
1973 .base_baud = 8333333,
1974 },
46a0fac9
SB		 1975 /*
1976 * National Instruments 843x
1977 */
1978 [pbn_ni8430_16] = {
1979 .flags = FL_BASE0,
1980 .num_ports = 16,
1981 .base_baud = 3686400,
1982 .uart_offset = 0x10,
1983 .first_offset = 0x800,
1984 },
1985 [pbn_ni8430_8] = {
1986 .flags = FL_BASE0,
1987 .num_ports = 8,
1988 .base_baud = 3686400,
1989 .uart_offset = 0x10,
1990 .first_offset = 0x800,
1991 },
1992 [pbn_ni8430_4] = {
1993 .flags = FL_BASE0,
1994 .num_ports = 4,
1995 .base_baud = 3686400,
1996 .uart_offset = 0x10,
1997 .first_offset = 0x800,
1998 },
1999 [pbn_ni8430_2] = {
2000 .flags = FL_BASE0,
2001 .num_ports = 2,
2002 .base_baud = 3686400,
2003 .uart_offset = 0x10,
2004 .first_offset = 0x800,
2005 },
1da177e4
LT		 2006};
2007
436bbd43 2008static const struct pci_device_id softmodem_blacklist[] = {
5756ee99 2009 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
436bbd43
CS		 2010};
2011
1da177e4
LT		 2012/*
2013 * Given a complete unknown PCI device, try to use some heuristics to
2014 * guess what the configuration might be, based on the pitiful PCI
2015 * serial specs. Returns 0 on success, 1 on failure.
2016 */
2017static int __devinit
1c7c1fe5 2018serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 2019{
436bbd43 2020 const struct pci_device_id *blacklist;
1da177e4 2021 int num_iomem, num_port, first_port = -1, i;
5756ee99 2022
1da177e4
LT		 2023 /*
2024 * If it is not a communications device or the programming
2025 * interface is greater than 6, give up.
2026 *
2027 * (Should we try to make guesses for multiport serial devices
5756ee99 2028 * later?)
1da177e4
LT		 2029 */
2030 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2031 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2032 (dev->class & 0xff) > 6)
2033 return -ENODEV;
2034
436bbd43
CS		 2035 /*
2036 * Do not access blacklisted devices that are known not to
2037 * feature serial ports.
2038 */
2039 for (blacklist = softmodem_blacklist;
2040 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2041 blacklist++) {
2042 if (dev->vendor == blacklist->vendor &&
2043 dev->device == blacklist->device)
2044 return -ENODEV;
2045 }
2046
1da177e4
LT		 2047 num_iomem = num_port = 0;
2048 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2049 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2050 num_port++;
2051 if (first_port == -1)
2052 first_port = i;
2053 }
2054 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2055 num_iomem++;
2056 }
2057
2058 /*
2059 * If there is 1 or 0 iomem regions, and exactly one port,
2060 * use it. We guess the number of ports based on the IO
2061 * region size.
2062 */
2063 if (num_iomem <= 1 && num_port == 1) {
2064 board->flags = first_port;
2065 board->num_ports = pci_resource_len(dev, first_port) / 8;
2066 return 0;
2067 }
2068
2069 /*
2070 * Now guess if we've got a board which indexes by BARs.
2071 * Each IO BAR should be 8 bytes, and they should follow
2072 * consecutively.
2073 */
2074 first_port = -1;
2075 num_port = 0;
2076 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2077 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2078 pci_resource_len(dev, i) == 8 &&
2079 (first_port == -1 || (first_port + num_port) == i)) {
2080 num_port++;
2081 if (first_port == -1)
2082 first_port = i;
2083 }
2084 }
2085
2086 if (num_port > 1) {
2087 board->flags = first_port | FL_BASE_BARS;
2088 board->num_ports = num_port;
2089 return 0;
2090 }
2091
2092 return -ENODEV;
2093}
2094
2095static inline int
975a1a7d
RK		 2096serial_pci_matches(const struct pciserial_board *board,
2097 const struct pciserial_board *guessed)
1da177e4
LT		 2098{
2099 return
2100 board->num_ports == guessed->num_ports &&
2101 board->base_baud == guessed->base_baud &&
2102 board->uart_offset == guessed->uart_offset &&
2103 board->reg_shift == guessed->reg_shift &&
2104 board->first_offset == guessed->first_offset;
2105}
2106
241fc436 2107struct serial_private *
975a1a7d 2108pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 2109{
72ce9a83 2110 struct uart_port serial_port;
1da177e4 2111 struct serial_private *priv;
1da177e4
LT		 2112 struct pci_serial_quirk *quirk;
2113 int rc, nr_ports, i;
2114
1da177e4
LT		 2115 nr_ports = board->num_ports;
2116
2117 /*
2118 * Find an init and setup quirks.
2119 */
2120 quirk = find_quirk(dev);
2121
2122 /*
2123 * Run the new-style initialization function.
2124 * The initialization function returns:
2125 * <0 - error
2126 * 0 - use board->num_ports
2127 * >0 - number of ports
2128 */
2129 if (quirk->init) {
2130 rc = quirk->init(dev);
241fc436
RK		 2131 if (rc < 0) {
2132 priv = ERR_PTR(rc);
2133 goto err_out;
2134 }
1da177e4
LT		 2135 if (rc)
2136 nr_ports = rc;
2137 }
2138
8f31bb39 2139 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 2140 sizeof(unsigned int) * nr_ports,
2141 GFP_KERNEL);
2142 if (!priv) {
241fc436
RK		 2143 priv = ERR_PTR(-ENOMEM);
2144 goto err_deinit;
1da177e4
LT		 2145 }
2146
70db3d91 2147 priv->dev = dev;
1da177e4 2148 priv->quirk = quirk;
1da177e4 2149
72ce9a83
RK		 2150 memset(&serial_port, 0, sizeof(struct uart_port));
2151 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2152 serial_port.uartclk = board->base_baud * 16;
2153 serial_port.irq = get_pci_irq(dev, board);
2154 serial_port.dev = &dev->dev;
2155
1da177e4 2156 for (i = 0; i < nr_ports; i++) {
70db3d91 2157 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 2158 break;
72ce9a83 2159
1da177e4 2160#ifdef SERIAL_DEBUG_PCI
5756ee99 2161 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
1da177e4
LT		 2162 serial_port.iobase, serial_port.irq, serial_port.iotype);
2163#endif
5756ee99 2164
1da177e4
LT		 2165 priv->line[i] = serial8250_register_port(&serial_port);
2166 if (priv->line[i] < 0) {
2167 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2168 break;
2169 }
2170 }
1da177e4 2171 priv->nr = i;
241fc436 2172 return priv;
1da177e4 2173
5756ee99 2174err_deinit:
1da177e4
LT		 2175 if (quirk->exit)
2176 quirk->exit(dev);
5756ee99 2177err_out:
241fc436 2178 return priv;
1da177e4 2179}
241fc436 2180EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 2181
241fc436 2182void pciserial_remove_ports(struct serial_private *priv)
1da177e4 2183{
056a8763
RK		 2184 struct pci_serial_quirk *quirk;
2185 int i;
1da177e4 2186
056a8763
RK		 2187 for (i = 0; i < priv->nr; i++)
2188 serial8250_unregister_port(priv->line[i]);
1da177e4 2189
056a8763
RK		 2190 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2191 if (priv->remapped_bar[i])
2192 iounmap(priv->remapped_bar[i]);
2193 priv->remapped_bar[i] = NULL;
2194 }
1da177e4 2195
056a8763
RK		 2196 /*
2197 * Find the exit quirks.
2198 */
241fc436 2199 quirk = find_quirk(priv->dev);
056a8763 2200 if (quirk->exit)
241fc436
RK		 2201 quirk->exit(priv->dev);
2202
2203 kfree(priv);
2204}
2205EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2206
2207void pciserial_suspend_ports(struct serial_private *priv)
2208{
2209 int i;
2210
2211 for (i = 0; i < priv->nr; i++)
2212 if (priv->line[i] >= 0)
2213 serial8250_suspend_port(priv->line[i]);
2214}
2215EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2216
2217void pciserial_resume_ports(struct serial_private *priv)
2218{
2219 int i;
2220
2221 /*
2222 * Ensure that the board is correctly configured.
2223 */
2224 if (priv->quirk->init)
2225 priv->quirk->init(priv->dev);
2226
2227 for (i = 0; i < priv->nr; i++)
2228 if (priv->line[i] >= 0)
2229 serial8250_resume_port(priv->line[i]);
2230}
2231EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2232
2233/*
2234 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2235 * to the arrangement of serial ports on a PCI card.
2236 */
2237static int __devinit
2238pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2239{
2240 struct serial_private *priv;
975a1a7d
RK		 2241 const struct pciserial_board *board;
2242 struct pciserial_board tmp;
241fc436
RK		 2243 int rc;
2244
2245 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2246 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2247 ent->driver_data);
2248 return -EINVAL;
2249 }
2250
2251 board = &pci_boards[ent->driver_data];
2252
2253 rc = pci_enable_device(dev);
2254 if (rc)
2255 return rc;
2256
2257 if (ent->driver_data == pbn_default) {
2258 /*
2259 * Use a copy of the pci_board entry for this;
2260 * avoid changing entries in the table.
2261 */
2262 memcpy(&tmp, board, sizeof(struct pciserial_board));
2263 board = &tmp;
2264
2265 /*
2266 * We matched one of our class entries. Try to
2267 * determine the parameters of this board.
2268 */
975a1a7d 2269 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 2270 if (rc)
2271 goto disable;
2272 } else {
2273 /*
2274 * We matched an explicit entry. If we are able to
2275 * detect this boards settings with our heuristic,
2276 * then we no longer need this entry.
2277 */
2278 memcpy(&tmp, &pci_boards[pbn_default],
2279 sizeof(struct pciserial_board));
2280 rc = serial_pci_guess_board(dev, &tmp);
2281 if (rc == 0 && serial_pci_matches(board, &tmp))
2282 moan_device("Redundant entry in serial pci_table.",
2283 dev);
2284 }
2285
2286 priv = pciserial_init_ports(dev, board);
2287 if (!IS_ERR(priv)) {
2288 pci_set_drvdata(dev, priv);
2289 return 0;
2290 }
2291
2292 rc = PTR_ERR(priv);
1da177e4 2293
241fc436 2294 disable:
056a8763 2295 pci_disable_device(dev);
241fc436
RK		 2296 return rc;
2297}
1da177e4 2298
241fc436
RK		 2299static void __devexit pciserial_remove_one(struct pci_dev *dev)
2300{
2301 struct serial_private *priv = pci_get_drvdata(dev);
2302
2303 pci_set_drvdata(dev, NULL);
2304
2305 pciserial_remove_ports(priv);
2306
2307 pci_disable_device(dev);
1da177e4
LT		 2308}
2309
1d5e7996 2310#ifdef CONFIG_PM
1da177e4
LT		 2311static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2312{
2313 struct serial_private *priv = pci_get_drvdata(dev);
2314
241fc436
RK		 2315 if (priv)
2316 pciserial_suspend_ports(priv);
1da177e4 2317
1da177e4
LT		 2318 pci_save_state(dev);
2319 pci_set_power_state(dev, pci_choose_state(dev, state));
2320 return 0;
2321}
2322
2323static int pciserial_resume_one(struct pci_dev *dev)
2324{
ccb9d59e 2325 int err;
1da177e4
LT		 2326 struct serial_private *priv = pci_get_drvdata(dev);
2327
2328 pci_set_power_state(dev, PCI_D0);
2329 pci_restore_state(dev);
2330
2331 if (priv) {
1da177e4
LT		 2332 /*
2333 * The device may have been disabled. Re-enable it.
2334 */
ccb9d59e 2335 err = pci_enable_device(dev);
40836c48 2336 /* FIXME: We cannot simply error out here */
ccb9d59e 2337 if (err)
40836c48 2338 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
241fc436 2339 pciserial_resume_ports(priv);
1da177e4
LT		 2340 }
2341 return 0;
2342}
1d5e7996 2343#endif
1da177e4
LT		 2344
2345static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 2346 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2347 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2348 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2349 pbn_b2_8_921600 },
1da177e4
LT		 2350 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2351 PCI_SUBVENDOR_ID_CONNECT_TECH,
2352 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2353 pbn_b1_8_1382400 },
2354 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2355 PCI_SUBVENDOR_ID_CONNECT_TECH,
2356 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2357 pbn_b1_4_1382400 },
2358 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2359 PCI_SUBVENDOR_ID_CONNECT_TECH,
2360 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2361 pbn_b1_2_1382400 },
2362 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2363 PCI_SUBVENDOR_ID_CONNECT_TECH,
2364 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2365 pbn_b1_8_1382400 },
2366 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2367 PCI_SUBVENDOR_ID_CONNECT_TECH,
2368 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2369 pbn_b1_4_1382400 },
2370 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2371 PCI_SUBVENDOR_ID_CONNECT_TECH,
2372 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2373 pbn_b1_2_1382400 },
2374 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2375 PCI_SUBVENDOR_ID_CONNECT_TECH,
2376 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2377 pbn_b1_8_921600 },
2378 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2379 PCI_SUBVENDOR_ID_CONNECT_TECH,
2380 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2381 pbn_b1_8_921600 },
2382 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2383 PCI_SUBVENDOR_ID_CONNECT_TECH,
2384 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2385 pbn_b1_4_921600 },
2386 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2387 PCI_SUBVENDOR_ID_CONNECT_TECH,
2388 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2389 pbn_b1_4_921600 },
2390 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2391 PCI_SUBVENDOR_ID_CONNECT_TECH,
2392 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2393 pbn_b1_2_921600 },
2394 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2395 PCI_SUBVENDOR_ID_CONNECT_TECH,
2396 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2397 pbn_b1_8_921600 },
2398 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2399 PCI_SUBVENDOR_ID_CONNECT_TECH,
2400 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2401 pbn_b1_8_921600 },
2402 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2403 PCI_SUBVENDOR_ID_CONNECT_TECH,
2404 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2405 pbn_b1_4_921600 },
26e92861
GH		 2406 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2407 PCI_SUBVENDOR_ID_CONNECT_TECH,
2408 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2409 pbn_b1_2_1250000 },
2410 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2411 PCI_SUBVENDOR_ID_CONNECT_TECH,
2412 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2413 pbn_b0_2_1843200 },
2414 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2415 PCI_SUBVENDOR_ID_CONNECT_TECH,
2416 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2417 pbn_b0_4_1843200 },
85d1494e
YY		 2418 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2419 PCI_VENDOR_ID_AFAVLAB,
2420 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2421 pbn_b0_4_1152000 },
26e92861
GH		 2422 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2423 PCI_SUBVENDOR_ID_CONNECT_TECH,
2424 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2425 pbn_b0_2_1843200_200 },
2426 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2427 PCI_SUBVENDOR_ID_CONNECT_TECH,
2428 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2429 pbn_b0_4_1843200_200 },
2430 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2431 PCI_SUBVENDOR_ID_CONNECT_TECH,
2432 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2433 pbn_b0_8_1843200_200 },
2434 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2435 PCI_SUBVENDOR_ID_CONNECT_TECH,
2436 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2437 pbn_b0_2_1843200_200 },
2438 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2439 PCI_SUBVENDOR_ID_CONNECT_TECH,
2440 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2441 pbn_b0_4_1843200_200 },
2442 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2443 PCI_SUBVENDOR_ID_CONNECT_TECH,
2444 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2445 pbn_b0_8_1843200_200 },
2446 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2447 PCI_SUBVENDOR_ID_CONNECT_TECH,
2448 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2449 pbn_b0_2_1843200_200 },
2450 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2451 PCI_SUBVENDOR_ID_CONNECT_TECH,
2452 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2453 pbn_b0_4_1843200_200 },
2454 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2455 PCI_SUBVENDOR_ID_CONNECT_TECH,
2456 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2457 pbn_b0_8_1843200_200 },
2458 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2459 PCI_SUBVENDOR_ID_CONNECT_TECH,
2460 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2461 pbn_b0_2_1843200_200 },
2462 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2463 PCI_SUBVENDOR_ID_CONNECT_TECH,
2464 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2465 pbn_b0_4_1843200_200 },
2466 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2467 PCI_SUBVENDOR_ID_CONNECT_TECH,
2468 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2469 pbn_b0_8_1843200_200 },
1da177e4
LT		 2470
2471 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 2472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2473 pbn_b2_bt_1_115200 },
2474 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 2475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2476 pbn_b2_bt_2_115200 },
2477 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 2478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2479 pbn_b2_bt_4_115200 },
2480 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 2481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2482 pbn_b2_bt_2_115200 },
2483 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 2484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2485 pbn_b2_bt_4_115200 },
2486 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 2487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 2488 pbn_b2_8_115200 },
e65f0f82
FL		 2489 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2491 pbn_b2_8_460800 },
1da177e4
LT		 2492 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2494 pbn_b2_8_115200 },
2495
2496 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2498 pbn_b2_bt_2_115200 },
2499 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2501 pbn_b2_bt_2_921600 },
2502 /*
2503 * VScom SPCOM800, from sl@s.pl
2504 */
5756ee99
AC		 2505 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2507 pbn_b2_8_921600 },
2508 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 2509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 2510 pbn_b2_4_921600 },
b76c5a07
CB		 2511 /* Unknown card - subdevice 0x1584 */
2512 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2513 PCI_VENDOR_ID_PLX,
2514 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2515 pbn_b0_4_115200 },
1da177e4
LT		 2516 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2517 PCI_SUBVENDOR_ID_KEYSPAN,
2518 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2519 pbn_panacom },
2520 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2522 pbn_panacom4 },
2523 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2525 pbn_panacom2 },
a9cccd34
MF		 2526 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2527 PCI_VENDOR_ID_ESDGMBH,
2528 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2529 pbn_b2_4_115200 },
1da177e4
LT		 2530 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2531 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2532 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 2533 pbn_b2_4_460800 },
2534 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2535 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2536 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 2537 pbn_b2_8_460800 },
2538 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2539 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2540 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 2541 pbn_b2_16_460800 },
2542 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2543 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2544 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 2545 pbn_b2_16_460800 },
2546 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2547 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 2548 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 2549 pbn_b2_4_460800 },
2550 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2551 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 2552 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 2553 pbn_b2_8_460800 },
add7b58e
BH		 2554 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2555 PCI_SUBVENDOR_ID_EXSYS,
2556 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2557 pbn_exsys_4055 },
1da177e4
LT		 2558 /*
2559 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2560 * (Exoray@isys.ca)
2561 */
2562 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2563 0x10b5, 0x106a, 0, 0,
2564 pbn_plx_romulus },
2565 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2566 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2567 pbn_b1_4_115200 },
2568 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2570 pbn_b1_2_115200 },
2571 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2572 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2573 pbn_b1_8_115200 },
2574 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2575 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2576 pbn_b1_8_115200 },
2577 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 2578 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2579 0, 0,
1da177e4 2580 pbn_b0_4_921600 },
fbc0dc0d 2581 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 2582 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2583 0, 0,
fbc0dc0d 2584 pbn_b0_4_1152000 },
db1de159
DR		 2585
2586 /*
2587 * The below card is a little controversial since it is the
2588 * subject of a PCI vendor/device ID clash. (See
2589 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2590 * For now just used the hex ID 0x950a.
2591 */
39aced68
NV		 2592 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2593 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2594 pbn_b0_2_115200 },
db1de159
DR		 2595 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2596 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2597 pbn_b0_2_1130000 },
1da177e4
LT		 2598 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2600 pbn_b0_4_115200 },
2601 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2603 pbn_b0_bt_2_921600 },
2604
7106b4e3
LH		 2605 /*
2606 * Oxford Semiconductor Inc. Tornado PCI express device range.
2607 */
2608 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2610 pbn_b0_1_4000000 },
2611 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2613 pbn_b0_1_4000000 },
2614 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2616 pbn_oxsemi_1_4000000 },
2617 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2619 pbn_oxsemi_1_4000000 },
2620 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2622 pbn_b0_1_4000000 },
2623 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2625 pbn_b0_1_4000000 },
2626 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2628 pbn_oxsemi_1_4000000 },
2629 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2631 pbn_oxsemi_1_4000000 },
2632 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2634 pbn_b0_1_4000000 },
2635 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2637 pbn_b0_1_4000000 },
2638 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2640 pbn_b0_1_4000000 },
2641 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2643 pbn_b0_1_4000000 },
2644 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2646 pbn_oxsemi_2_4000000 },
2647 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2649 pbn_oxsemi_2_4000000 },
2650 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2652 pbn_oxsemi_4_4000000 },
2653 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2655 pbn_oxsemi_4_4000000 },
2656 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2658 pbn_oxsemi_8_4000000 },
2659 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2661 pbn_oxsemi_8_4000000 },
2662 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2664 pbn_oxsemi_1_4000000 },
2665 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2666 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2667 pbn_oxsemi_1_4000000 },
2668 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2669 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2670 pbn_oxsemi_1_4000000 },
2671 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2673 pbn_oxsemi_1_4000000 },
2674 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2675 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2676 pbn_oxsemi_1_4000000 },
2677 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2678 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2679 pbn_oxsemi_1_4000000 },
2680 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
2681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2682 pbn_oxsemi_1_4000000 },
2683 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
2684 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2685 pbn_oxsemi_1_4000000 },
2686 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
2687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2688 pbn_oxsemi_1_4000000 },
2689 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
2690 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2691 pbn_oxsemi_1_4000000 },
2692 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
2693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2694 pbn_oxsemi_1_4000000 },
2695 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
2696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2697 pbn_oxsemi_1_4000000 },
2698 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
2699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2700 pbn_oxsemi_1_4000000 },
2701 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
2702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2703 pbn_oxsemi_1_4000000 },
2704 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
2705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2706 pbn_oxsemi_1_4000000 },
2707 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
2708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2709 pbn_oxsemi_1_4000000 },
2710 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
2711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2712 pbn_oxsemi_1_4000000 },
2713 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
2714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2715 pbn_oxsemi_1_4000000 },
2716 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
2717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2718 pbn_oxsemi_1_4000000 },
2719 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
2720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2721 pbn_oxsemi_1_4000000 },
2722 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
2723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2724 pbn_oxsemi_1_4000000 },
2725 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
2726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2727 pbn_oxsemi_1_4000000 },
2728 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
2729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2730 pbn_oxsemi_1_4000000 },
2731 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
2732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2733 pbn_oxsemi_1_4000000 },
2734 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
2735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2736 pbn_oxsemi_1_4000000 },
2737 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
2738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2739 pbn_oxsemi_1_4000000 },
b80de369
LH		 2740 /*
2741 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2742 */
2743 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2744 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
2745 pbn_oxsemi_1_4000000 },
2746 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2747 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
2748 pbn_oxsemi_2_4000000 },
2749 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2750 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
2751 pbn_oxsemi_4_4000000 },
2752 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2753 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
2754 pbn_oxsemi_8_4000000 },
1da177e4
LT		 2755 /*
2756 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2757 * from skokodyn@yahoo.com
2758 */
2759 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2760 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2761 pbn_sbsxrsio },
2762 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2763 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2764 pbn_sbsxrsio },
2765 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2766 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2767 pbn_sbsxrsio },
2768 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2769 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2770 pbn_sbsxrsio },
2771
2772 /*
2773 * Digitan DS560-558, from jimd@esoft.com
2774 */
2775 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 2776 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2777 pbn_b1_1_115200 },
2778
2779 /*
2780 * Titan Electronic cards
2781 * The 400L and 800L have a custom setup quirk.
2782 */
2783 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 2784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2785 pbn_b0_1_921600 },
2786 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 2787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2788 pbn_b0_2_921600 },
2789 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 2790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2791 pbn_b0_4_921600 },
2792 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 2793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2794 pbn_b0_4_921600 },
2795 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2797 pbn_b1_1_921600 },
2798 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2800 pbn_b1_bt_2_921600 },
2801 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2803 pbn_b0_bt_4_921600 },
2804 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2806 pbn_b0_bt_8_921600 },
2807
2808 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2810 pbn_b2_1_460800 },
2811 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2813 pbn_b2_1_460800 },
2814 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2816 pbn_b2_1_460800 },
2817 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2819 pbn_b2_bt_2_921600 },
2820 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2822 pbn_b2_bt_2_921600 },
2823 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2825 pbn_b2_bt_2_921600 },
2826 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2828 pbn_b2_bt_4_921600 },
2829 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2831 pbn_b2_bt_4_921600 },
2832 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2834 pbn_b2_bt_4_921600 },
2835 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2837 pbn_b0_1_921600 },
2838 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2840 pbn_b0_1_921600 },
2841 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2843 pbn_b0_1_921600 },
2844 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2846 pbn_b0_bt_2_921600 },
2847 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2849 pbn_b0_bt_2_921600 },
2850 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2852 pbn_b0_bt_2_921600 },
2853 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2855 pbn_b0_bt_4_921600 },
2856 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2857 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2858 pbn_b0_bt_4_921600 },
2859 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2861 pbn_b0_bt_4_921600 },
3ec9c594
AP		 2862 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2864 pbn_b0_bt_8_921600 },
2865 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2867 pbn_b0_bt_8_921600 },
2868 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2869 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2870 pbn_b0_bt_8_921600 },
1da177e4
LT		 2871
2872 /*
2873 * Computone devices submitted by Doug McNash dmcnash@computone.com
2874 */
2875 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2876 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2877 0, 0, pbn_computone_4 },
2878 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2879 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2880 0, 0, pbn_computone_8 },
2881 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2882 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2883 0, 0, pbn_computone_6 },
2884
2885 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2887 pbn_oxsemi },
2888 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2889 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2890 pbn_b0_bt_1_921600 },
2891
2892 /*
2893 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2894 */
2895 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2897 pbn_b0_bt_8_115200 },
2898 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2900 pbn_b0_bt_8_115200 },
2901
2902 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2904 pbn_b0_bt_2_115200 },
2905 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2907 pbn_b0_bt_2_115200 },
2908 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2910 pbn_b0_bt_2_115200 },
2911 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2913 pbn_b0_bt_4_460800 },
2914 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2916 pbn_b0_bt_4_460800 },
2917 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2919 pbn_b0_bt_2_460800 },
2920 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2922 pbn_b0_bt_2_460800 },
2923 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2925 pbn_b0_bt_2_460800 },
2926 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2928 pbn_b0_bt_1_115200 },
2929 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2931 pbn_b0_bt_1_460800 },
2932
1fb8cacc
RK		 2933 /*
2934 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2935 * Cards are identified by their subsystem vendor IDs, which
2936 * (in hex) match the model number.
2937 *
2938 * Note that JC140x are RS422/485 cards which require ox950
2939 * ACR = 0x10, and as such are not currently fully supported.
2940 */
2941 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2942 0x1204, 0x0004, 0, 0,
2943 pbn_b0_4_921600 },
2944 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2945 0x1208, 0x0004, 0, 0,
2946 pbn_b0_4_921600 },
2947/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2948 0x1402, 0x0002, 0, 0,
2949 pbn_b0_2_921600 }, */
2950/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2951 0x1404, 0x0004, 0, 0,
2952 pbn_b0_4_921600 }, */
2953 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2954 0x1208, 0x0004, 0, 0,
2955 pbn_b0_4_921600 },
2956
1da177e4
LT		 2957 /*
2958 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2959 */
2960 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2962 pbn_b1_1_1382400 },
2963
2964 /*
2965 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2966 */
2967 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2969 pbn_b1_1_1382400 },
2970
2971 /*
2972 * RAStel 2 port modem, gerg@moreton.com.au
2973 */
2974 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2976 pbn_b2_bt_2_115200 },
2977
2978 /*
2979 * EKF addition for i960 Boards form EKF with serial port
2980 */
2981 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2982 0xE4BF, PCI_ANY_ID, 0, 0,
2983 pbn_intel_i960 },
2984
2985 /*
2986 * Xircom Cardbus/Ethernet combos
2987 */
2988 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2990 pbn_b0_1_115200 },
2991 /*
2992 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2993 */
2994 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2996 pbn_b0_1_115200 },
2997
2998 /*
2999 * Untested PCI modems, sent in from various folks...
3000 */
3001
3002 /*
3003 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3004 */
3005 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3006 0x1048, 0x1500, 0, 0,
3007 pbn_b1_1_115200 },
3008
3009 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3010 0xFF00, 0, 0, 0,
3011 pbn_sgi_ioc3 },
3012
3013 /*
3014 * HP Diva card
3015 */
3016 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3017 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3018 pbn_b1_1_115200 },
3019 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3021 pbn_b0_5_115200 },
3022 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3024 pbn_b2_1_115200 },
3025
d9004eb4
ABL		 3026 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3028 pbn_b3_2_115200 },
1da177e4
LT		 3029 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3031 pbn_b3_4_115200 },
3032 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3034 pbn_b3_8_115200 },
3035
3036 /*
3037 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3038 */
3039 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3040 PCI_ANY_ID, PCI_ANY_ID,
3041 0,
3042 0, pbn_exar_XR17C152 },
3043 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3044 PCI_ANY_ID, PCI_ANY_ID,
3045 0,
3046 0, pbn_exar_XR17C154 },
3047 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3048 PCI_ANY_ID, PCI_ANY_ID,
3049 0,
3050 0, pbn_exar_XR17C158 },
3051
3052 /*
3053 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3054 */
3055 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3056 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3057 pbn_b0_1_115200 },
84f8c6fc
NV		 3058 /*
3059 * ITE
3060 */
3061 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3062 PCI_ANY_ID, PCI_ANY_ID,
3063 0, 0,
3064 pbn_b1_bt_1_115200 },
1da177e4 3065
737c1756
PH		 3066 /*
3067 * IntaShield IS-200
3068 */
3069 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3070 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3071 pbn_b2_2_115200 },
4b6f6ce9
IGP		 3072 /*
3073 * IntaShield IS-400
3074 */
3075 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3076 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3077 pbn_b2_4_115200 },
48212008
TH		 3078 /*
3079 * Perle PCI-RAS cards
3080 */
3081 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3082 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3083 0, 0, pbn_b2_4_921600 },
3084 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3085 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3086 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 3087
3088 /*
3089 * Mainpine series cards: Fairly standard layout but fools
3090 * parts of the autodetect in some cases and uses otherwise
3091 * unmatched communications subclasses in the PCI Express case
3092 */
3093
3094 { /* RockForceDUO */
3095 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3096 PCI_VENDOR_ID_MAINPINE, 0x0200,
3097 0, 0, pbn_b0_2_115200 },
3098 { /* RockForceQUATRO */
3099 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3100 PCI_VENDOR_ID_MAINPINE, 0x0300,
3101 0, 0, pbn_b0_4_115200 },
3102 { /* RockForceDUO+ */
3103 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3104 PCI_VENDOR_ID_MAINPINE, 0x0400,
3105 0, 0, pbn_b0_2_115200 },
3106 { /* RockForceQUATRO+ */
3107 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3108 PCI_VENDOR_ID_MAINPINE, 0x0500,
3109 0, 0, pbn_b0_4_115200 },
3110 { /* RockForce+ */
3111 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3112 PCI_VENDOR_ID_MAINPINE, 0x0600,
3113 0, 0, pbn_b0_2_115200 },
3114 { /* RockForce+ */
3115 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3116 PCI_VENDOR_ID_MAINPINE, 0x0700,
3117 0, 0, pbn_b0_4_115200 },
3118 { /* RockForceOCTO+ */
3119 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3120 PCI_VENDOR_ID_MAINPINE, 0x0800,
3121 0, 0, pbn_b0_8_115200 },
3122 { /* RockForceDUO+ */
3123 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3124 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3125 0, 0, pbn_b0_2_115200 },
3126 { /* RockForceQUARTRO+ */
3127 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3128 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3129 0, 0, pbn_b0_4_115200 },
3130 { /* RockForceOCTO+ */
3131 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3132 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3133 0, 0, pbn_b0_8_115200 },
3134 { /* RockForceD1 */
3135 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3136 PCI_VENDOR_ID_MAINPINE, 0x2000,
3137 0, 0, pbn_b0_1_115200 },
3138 { /* RockForceF1 */
3139 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3140 PCI_VENDOR_ID_MAINPINE, 0x2100,
3141 0, 0, pbn_b0_1_115200 },
3142 { /* RockForceD2 */
3143 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3144 PCI_VENDOR_ID_MAINPINE, 0x2200,
3145 0, 0, pbn_b0_2_115200 },
3146 { /* RockForceF2 */
3147 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3148 PCI_VENDOR_ID_MAINPINE, 0x2300,
3149 0, 0, pbn_b0_2_115200 },
3150 { /* RockForceD4 */
3151 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3152 PCI_VENDOR_ID_MAINPINE, 0x2400,
3153 0, 0, pbn_b0_4_115200 },
3154 { /* RockForceF4 */
3155 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3156 PCI_VENDOR_ID_MAINPINE, 0x2500,
3157 0, 0, pbn_b0_4_115200 },
3158 { /* RockForceD8 */
3159 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3160 PCI_VENDOR_ID_MAINPINE, 0x2600,
3161 0, 0, pbn_b0_8_115200 },
3162 { /* RockForceF8 */
3163 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3164 PCI_VENDOR_ID_MAINPINE, 0x2700,
3165 0, 0, pbn_b0_8_115200 },
3166 { /* IQ Express D1 */
3167 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3168 PCI_VENDOR_ID_MAINPINE, 0x3000,
3169 0, 0, pbn_b0_1_115200 },
3170 { /* IQ Express F1 */
3171 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3172 PCI_VENDOR_ID_MAINPINE, 0x3100,
3173 0, 0, pbn_b0_1_115200 },
3174 { /* IQ Express D2 */
3175 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3176 PCI_VENDOR_ID_MAINPINE, 0x3200,
3177 0, 0, pbn_b0_2_115200 },
3178 { /* IQ Express F2 */
3179 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3180 PCI_VENDOR_ID_MAINPINE, 0x3300,
3181 0, 0, pbn_b0_2_115200 },
3182 { /* IQ Express D4 */
3183 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3184 PCI_VENDOR_ID_MAINPINE, 0x3400,
3185 0, 0, pbn_b0_4_115200 },
3186 { /* IQ Express F4 */
3187 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3188 PCI_VENDOR_ID_MAINPINE, 0x3500,
3189 0, 0, pbn_b0_4_115200 },
3190 { /* IQ Express D8 */
3191 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3192 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3193 0, 0, pbn_b0_8_115200 },
3194 { /* IQ Express F8 */
3195 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3196 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3197 0, 0, pbn_b0_8_115200 },
3198
3199
aa798505
OJ		 3200 /*
3201 * PA Semi PA6T-1682M on-chip UART
3202 */
3203 { PCI_VENDOR_ID_PASEMI, 0xa004,
3204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3205 pbn_pasemi_1682M },
3206
46a0fac9
SB		 3207 /*
3208 * National Instruments
3209 */
3210 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3212 pbn_ni8430_2 },
3213 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3215 pbn_ni8430_2 },
3216 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3218 pbn_ni8430_4 },
3219 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3221 pbn_ni8430_4 },
3222 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3224 pbn_ni8430_8 },
3225 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3227 pbn_ni8430_8 },
3228 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3230 pbn_ni8430_16 },
3231 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3233 pbn_ni8430_16 },
3234 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3236 pbn_ni8430_2 },
3237 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3239 pbn_ni8430_2 },
3240 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3242 pbn_ni8430_4 },
3243 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3245 pbn_ni8430_4 },
3246
02c9b5cf
KJ		 3247 /*
3248 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3249 */
3250 { PCI_VENDOR_ID_ADDIDATA,
3251 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3252 PCI_ANY_ID,
3253 PCI_ANY_ID,
3254 0,
3255 0,
3256 pbn_b0_4_115200 },
3257
3258 { PCI_VENDOR_ID_ADDIDATA,
3259 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3260 PCI_ANY_ID,
3261 PCI_ANY_ID,
3262 0,
3263 0,
3264 pbn_b0_2_115200 },
3265
3266 { PCI_VENDOR_ID_ADDIDATA,
3267 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3268 PCI_ANY_ID,
3269 PCI_ANY_ID,
3270 0,
3271 0,
3272 pbn_b0_1_115200 },
3273
3274 { PCI_VENDOR_ID_ADDIDATA_OLD,
3275 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3276 PCI_ANY_ID,
3277 PCI_ANY_ID,
3278 0,
3279 0,
3280 pbn_b1_8_115200 },
3281
3282 { PCI_VENDOR_ID_ADDIDATA,
3283 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3284 PCI_ANY_ID,
3285 PCI_ANY_ID,
3286 0,
3287 0,
3288 pbn_b0_4_115200 },
3289
3290 { PCI_VENDOR_ID_ADDIDATA,
3291 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3292 PCI_ANY_ID,
3293 PCI_ANY_ID,
3294 0,
3295 0,
3296 pbn_b0_2_115200 },
3297
3298 { PCI_VENDOR_ID_ADDIDATA,
3299 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3300 PCI_ANY_ID,
3301 PCI_ANY_ID,
3302 0,
3303 0,
3304 pbn_b0_1_115200 },
3305
3306 { PCI_VENDOR_ID_ADDIDATA,
3307 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3308 PCI_ANY_ID,
3309 PCI_ANY_ID,
3310 0,
3311 0,
3312 pbn_b0_4_115200 },
3313
3314 { PCI_VENDOR_ID_ADDIDATA,
3315 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3316 PCI_ANY_ID,
3317 PCI_ANY_ID,
3318 0,
3319 0,
3320 pbn_b0_2_115200 },
3321
3322 { PCI_VENDOR_ID_ADDIDATA,
3323 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3324 PCI_ANY_ID,
3325 PCI_ANY_ID,
3326 0,
3327 0,
3328 pbn_b0_1_115200 },
3329
3330 { PCI_VENDOR_ID_ADDIDATA,
3331 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3332 PCI_ANY_ID,
3333 PCI_ANY_ID,
3334 0,
3335 0,
3336 pbn_b0_8_115200 },
3337
25cf9bc1
JS		 3338 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3339 PCI_VENDOR_ID_IBM, 0x0299,
3340 0, 0, pbn_b0_bt_2_115200 },
3341
1da177e4
LT		 3342 /*
3343 * These entries match devices with class COMMUNICATION_SERIAL,
3344 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3345 */
3346 { PCI_ANY_ID, PCI_ANY_ID,
3347 PCI_ANY_ID, PCI_ANY_ID,
3348 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3349 0xffff00, pbn_default },
3350 { PCI_ANY_ID, PCI_ANY_ID,
3351 PCI_ANY_ID, PCI_ANY_ID,
3352 PCI_CLASS_COMMUNICATION_MODEM << 8,
3353 0xffff00, pbn_default },
3354 { PCI_ANY_ID, PCI_ANY_ID,
3355 PCI_ANY_ID, PCI_ANY_ID,
3356 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3357 0xffff00, pbn_default },
3358 { 0, }
3359};
3360
3361static struct pci_driver serial_pci_driver = {
3362 .name = "serial",
3363 .probe = pciserial_init_one,
3364 .remove = __devexit_p(pciserial_remove_one),
1d5e7996 3365#ifdef CONFIG_PM
1da177e4
LT		 3366 .suspend = pciserial_suspend_one,
3367 .resume = pciserial_resume_one,
1d5e7996 3368#endif
1da177e4
LT		 3369 .id_table = serial_pci_tbl,
3370};
3371
3372static int __init serial8250_pci_init(void)
3373{
3374 return pci_register_driver(&serial_pci_driver);
3375}
3376
3377static void __exit serial8250_pci_exit(void)
3378{
3379 pci_unregister_driver(&serial_pci_driver);
3380}
3381
3382module_init(serial8250_pci_init);
3383module_exit(serial8250_pci_exit);
3384
3385MODULE_LICENSE("GPL");
3386MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3387MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Clone of davem's net-next-2.6 tree