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serial: don't optimise away baud rate changes when BOTHER is used
[net-next-2.6.git] / drivers / serial / 8250_pci.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/pci.h>
1da177e4
LT		 19#include <linux/string.h>
20#include <linux/kernel.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/tty.h>
24#include <linux/serial_core.h>
25#include <linux/8250_pci.h>
26#include <linux/bitops.h>
27
28#include <asm/byteorder.h>
29#include <asm/io.h>
30
31#include "8250.h"
32
33#undef SERIAL_DEBUG_PCI
34
1da177e4
LT		 35/*
36 * init function returns:
37 * > 0 - number of ports
38 * = 0 - use board->num_ports
39 * < 0 - error
40 */
41struct pci_serial_quirk {
42 u32 vendor;
43 u32 device;
44 u32 subvendor;
45 u32 subdevice;
46 int (*init)(struct pci_dev *dev);
70db3d91 47 int (*setup)(struct serial_private *, struct pciserial_board *,
05caac58 48 struct uart_port *, int);
1da177e4
LT		 49 void (*exit)(struct pci_dev *dev);
50};
51
52#define PCI_NUM_BAR_RESOURCES 6
53
54struct serial_private {
70db3d91 55 struct pci_dev *dev;
1da177e4
LT		 56 unsigned int nr;
57 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
58 struct pci_serial_quirk *quirk;
59 int line[0];
60};
61
62static void moan_device(const char *str, struct pci_dev *dev)
63{
64 printk(KERN_WARNING "%s: %s\n"
65 KERN_WARNING "Please send the output of lspci -vv, this\n"
66 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
67 KERN_WARNING "manufacturer and name of serial board or\n"
68 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
69 pci_name(dev), str, dev->vendor, dev->device,
70 dev->subsystem_vendor, dev->subsystem_device);
71}
72
73static int
70db3d91 74setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 75 int bar, int offset, int regshift)
76{
70db3d91 77 struct pci_dev *dev = priv->dev;
1da177e4
LT		 78 unsigned long base, len;
79
80 if (bar >= PCI_NUM_BAR_RESOURCES)
81 return -EINVAL;
82
72ce9a83
RK		 83 base = pci_resource_start(dev, bar);
84
1da177e4 85 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 86 len = pci_resource_len(dev, bar);
87
88 if (!priv->remapped_bar[bar])
89 priv->remapped_bar[bar] = ioremap(base, len);
90 if (!priv->remapped_bar[bar])
91 return -ENOMEM;
92
93 port->iotype = UPIO_MEM;
72ce9a83 94 port->iobase = 0;
1da177e4
LT		 95 port->mapbase = base + offset;
96 port->membase = priv->remapped_bar[bar] + offset;
97 port->regshift = regshift;
98 } else {
1da177e4 99 port->iotype = UPIO_PORT;
72ce9a83
RK		 100 port->iobase = base + offset;
101 port->mapbase = 0;
102 port->membase = NULL;
103 port->regshift = 0;
1da177e4
LT		 104 }
105 return 0;
106}
107
108/*
109 * AFAVLAB uses a different mixture of BARs and offsets
110 * Not that ugly ;) -- HW
111 */
112static int
70db3d91 113afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 114 struct uart_port *port, int idx)
115{
116 unsigned int bar, offset = board->first_offset;
117
118 bar = FL_GET_BASE(board->flags);
119 if (idx < 4)
120 bar += idx;
121 else {
122 bar = 4;
123 offset += (idx - 4) * board->uart_offset;
124 }
125
70db3d91 126 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 127}
128
129/*
130 * HP's Remote Management Console. The Diva chip came in several
131 * different versions. N-class, L2000 and A500 have two Diva chips, each
132 * with 3 UARTs (the third UART on the second chip is unused). Superdome
133 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
134 * one Diva chip, but it has been expanded to 5 UARTs.
135 */
61a116ef 136static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 137{
138 int rc = 0;
139
140 switch (dev->subsystem_device) {
141 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
142 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
143 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
144 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
145 rc = 3;
146 break;
147 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
148 rc = 2;
149 break;
150 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
151 rc = 4;
152 break;
153 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 154 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 155 rc = 1;
156 break;
157 }
158
159 return rc;
160}
161
162/*
163 * HP's Diva chip puts the 4th/5th serial port further out, and
164 * some serial ports are supposed to be hidden on certain models.
165 */
166static int
70db3d91 167pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 168 struct uart_port *port, int idx)
169{
170 unsigned int offset = board->first_offset;
171 unsigned int bar = FL_GET_BASE(board->flags);
172
70db3d91 173 switch (priv->dev->subsystem_device) {
1da177e4
LT		 174 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
175 if (idx == 3)
176 idx++;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
179 if (idx > 0)
180 idx++;
181 if (idx > 2)
182 idx++;
183 break;
184 }
185 if (idx > 2)
186 offset = 0x18;
187
188 offset += idx * board->uart_offset;
189
70db3d91 190 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 191}
192
193/*
194 * Added for EKF Intel i960 serial boards
195 */
61a116ef 196static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 197{
198 unsigned long oldval;
199
200 if (!(dev->subsystem_device & 0x1000))
201 return -ENODEV;
202
203 /* is firmware started? */
204 pci_read_config_dword(dev, 0x44, (void*) &oldval);
205 if (oldval == 0x00001000L) { /* RESET value */
206 printk(KERN_DEBUG "Local i960 firmware missing");
207 return -ENODEV;
208 }
209 return 0;
210}
211
212/*
213 * Some PCI serial cards using the PLX 9050 PCI interface chip require
214 * that the card interrupt be explicitly enabled or disabled. This
215 * seems to be mainly needed on card using the PLX which also use I/O
216 * mapped memory.
217 */
61a116ef 218static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 219{
220 u8 irq_config;
221 void __iomem *p;
222
223 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
224 moan_device("no memory in bar 0", dev);
225 return 0;
226 }
227
228 irq_config = 0x41;
add7b58e
BH		 229 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
230 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
1da177e4 231 irq_config = 0x43;
add7b58e 232 }
1da177e4
LT		 233 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
234 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
235 /*
236 * As the megawolf cards have the int pins active
237 * high, and have 2 UART chips, both ints must be
238 * enabled on the 9050. Also, the UARTS are set in
239 * 16450 mode by default, so we have to enable the
240 * 16C950 'enhanced' mode so that we can use the
241 * deep FIFOs
242 */
243 irq_config = 0x5b;
244 }
245
246 /*
247 * enable/disable interrupts
248 */
249 p = ioremap(pci_resource_start(dev, 0), 0x80);
250 if (p == NULL)
251 return -ENOMEM;
252 writel(irq_config, p + 0x4c);
253
254 /*
255 * Read the register back to ensure that it took effect.
256 */
257 readl(p + 0x4c);
258 iounmap(p);
259
260 return 0;
261}
262
263static void __devexit pci_plx9050_exit(struct pci_dev *dev)
264{
265 u8 __iomem *p;
266
267 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
268 return;
269
270 /*
271 * disable interrupts
272 */
273 p = ioremap(pci_resource_start(dev, 0), 0x80);
274 if (p != NULL) {
275 writel(0, p + 0x4c);
276
277 /*
278 * Read the register back to ensure that it took effect.
279 */
280 readl(p + 0x4c);
281 iounmap(p);
282 }
283}
284
285/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
286static int
70db3d91 287sbs_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 288 struct uart_port *port, int idx)
289{
290 unsigned int bar, offset = board->first_offset;
291
292 bar = 0;
293
294 if (idx < 4) {
295 /* first four channels map to 0, 0x100, 0x200, 0x300 */
296 offset += idx * board->uart_offset;
297 } else if (idx < 8) {
298 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
299 offset += idx * board->uart_offset + 0xC00;
300 } else /* we have only 8 ports on PMC-OCTALPRO */
301 return 1;
302
70db3d91 303 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 304}
305
306/*
307* This does initialization for PMC OCTALPRO cards:
308* maps the device memory, resets the UARTs (needed, bc
309* if the module is removed and inserted again, the card
310* is in the sleep mode) and enables global interrupt.
311*/
312
313/* global control register offset for SBS PMC-OctalPro */
314#define OCT_REG_CR_OFF 0x500
315
61a116ef 316static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 317{
318 u8 __iomem *p;
319
320 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
321
322 if (p == NULL)
323 return -ENOMEM;
324 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
325 writeb(0x10,p + OCT_REG_CR_OFF);
326 udelay(50);
327 writeb(0x0,p + OCT_REG_CR_OFF);
328
329 /* Set bit-2 (INTENABLE) of Control Register */
330 writeb(0x4, p + OCT_REG_CR_OFF);
331 iounmap(p);
332
333 return 0;
334}
335
336/*
337 * Disables the global interrupt of PMC-OctalPro
338 */
339
340static void __devexit sbs_exit(struct pci_dev *dev)
341{
342 u8 __iomem *p;
343
344 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
345 if (p != NULL) {
346 writeb(0, p + OCT_REG_CR_OFF);
347 }
348 iounmap(p);
349}
350
351/*
352 * SIIG serial cards have an PCI interface chip which also controls
353 * the UART clocking frequency. Each UART can be clocked independently
354 * (except cards equiped with 4 UARTs) and initial clocking settings
355 * are stored in the EEPROM chip. It can cause problems because this
356 * version of serial driver doesn't support differently clocked UART's
357 * on single PCI card. To prevent this, initialization functions set
358 * high frequency clocking for all UART's on given card. It is safe (I
359 * hope) because it doesn't touch EEPROM settings to prevent conflicts
360 * with other OSes (like M$ DOS).
361 *
362 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
363 *
364 * There is two family of SIIG serial cards with different PCI
365 * interface chip and different configuration methods:
366 * - 10x cards have control registers in IO and/or memory space;
367 * - 20x cards have control registers in standard PCI configuration space.
368 *
67d74b87
RK		 369 * Note: all 10x cards have PCI device ids 0x10..
370 * all 20x cards have PCI device ids 0x20..
371 *
fbc0dc0d
AP		 372 * There are also Quartet Serial cards which use Oxford Semiconductor
373 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
374 *
1da177e4
LT		 375 * Note: some SIIG cards are probed by the parport_serial object.
376 */
377
378#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
379#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
380
381static int pci_siig10x_init(struct pci_dev *dev)
382{
383 u16 data;
384 void __iomem *p;
385
386 switch (dev->device & 0xfff8) {
387 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
388 data = 0xffdf;
389 break;
390 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
391 data = 0xf7ff;
392 break;
393 default: /* 1S1P, 4S */
394 data = 0xfffb;
395 break;
396 }
397
398 p = ioremap(pci_resource_start(dev, 0), 0x80);
399 if (p == NULL)
400 return -ENOMEM;
401
402 writew(readw(p + 0x28) & data, p + 0x28);
403 readw(p + 0x28);
404 iounmap(p);
405 return 0;
406}
407
408#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
409#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
410
411static int pci_siig20x_init(struct pci_dev *dev)
412{
413 u8 data;
414
415 /* Change clock frequency for the first UART. */
416 pci_read_config_byte(dev, 0x6f, &data);
417 pci_write_config_byte(dev, 0x6f, data & 0xef);
418
419 /* If this card has 2 UART, we have to do the same with second UART. */
420 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
421 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
422 pci_read_config_byte(dev, 0x73, &data);
423 pci_write_config_byte(dev, 0x73, data & 0xef);
424 }
425 return 0;
426}
427
67d74b87
RK		 428static int pci_siig_init(struct pci_dev *dev)
429{
430 unsigned int type = dev->device & 0xff00;
431
432 if (type == 0x1000)
433 return pci_siig10x_init(dev);
434 else if (type == 0x2000)
435 return pci_siig20x_init(dev);
436
437 moan_device("Unknown SIIG card", dev);
438 return -ENODEV;
439}
440
3ec9c594
AP		 441static int pci_siig_setup(struct serial_private *priv,
442 struct pciserial_board *board,
443 struct uart_port *port, int idx)
444{
445 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
446
447 if (idx > 3) {
448 bar = 4;
449 offset = (idx - 4) * 8;
450 }
451
452 return setup_port(priv, port, bar, offset, 0);
453}
454
1da177e4
LT		 455/*
456 * Timedia has an explosion of boards, and to avoid the PCI table from
457 * growing *huge*, we use this function to collapse some 70 entries
458 * in the PCI table into one, for sanity's and compactness's sake.
459 */
e9422e09 460static const unsigned short timedia_single_port[] = {
1da177e4
LT		 461 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
462};
463
e9422e09 464static const unsigned short timedia_dual_port[] = {
1da177e4
LT		 465 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
466 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
467 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
468 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
469 0xD079, 0
470};
471
e9422e09 472static const unsigned short timedia_quad_port[] = {
1da177e4
LT		 473 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
474 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
475 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
476 0xB157, 0
477};
478
e9422e09 479static const unsigned short timedia_eight_port[] = {
1da177e4
LT		 480 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
481 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
482};
483
cb3592be 484static const struct timedia_struct {
1da177e4 485 int num;
e9422e09 486 const unsigned short *ids;
1da177e4
LT		 487} timedia_data[] = {
488 { 1, timedia_single_port },
489 { 2, timedia_dual_port },
490 { 4, timedia_quad_port },
e9422e09 491 { 8, timedia_eight_port }
1da177e4
LT		 492};
493
61a116ef 494static int pci_timedia_init(struct pci_dev *dev)
1da177e4 495{
e9422e09 496 const unsigned short *ids;
1da177e4
LT		 497 int i, j;
498
e9422e09 499 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 500 ids = timedia_data[i].ids;
501 for (j = 0; ids[j]; j++)
502 if (dev->subsystem_device == ids[j])
503 return timedia_data[i].num;
504 }
505 return 0;
506}
507
508/*
509 * Timedia/SUNIX uses a mixture of BARs and offsets
510 * Ugh, this is ugly as all hell --- TYT
511 */
512static int
70db3d91 513pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 514 struct uart_port *port, int idx)
515{
516 unsigned int bar = 0, offset = board->first_offset;
517
518 switch (idx) {
519 case 0:
520 bar = 0;
521 break;
522 case 1:
523 offset = board->uart_offset;
524 bar = 0;
525 break;
526 case 2:
527 bar = 1;
528 break;
529 case 3:
530 offset = board->uart_offset;
c2cd6d3c 531 /* FALLTHROUGH */
1da177e4
LT		 532 case 4: /* BAR 2 */
533 case 5: /* BAR 3 */
534 case 6: /* BAR 4 */
535 case 7: /* BAR 5 */
536 bar = idx - 2;
537 }
538
70db3d91 539 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 540}
541
542/*
543 * Some Titan cards are also a little weird
544 */
545static int
70db3d91 546titan_400l_800l_setup(struct serial_private *priv,
1c7c1fe5 547 struct pciserial_board *board,
1da177e4
LT		 548 struct uart_port *port, int idx)
549{
550 unsigned int bar, offset = board->first_offset;
551
552 switch (idx) {
553 case 0:
554 bar = 1;
555 break;
556 case 1:
557 bar = 2;
558 break;
559 default:
560 bar = 4;
561 offset = (idx - 2) * board->uart_offset;
562 }
563
70db3d91 564 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 565}
566
61a116ef 567static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 568{
569 msleep(100);
570 return 0;
571}
572
61a116ef 573static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 574{
575 /* subdevice 0x00PS means <P> parallel, <S> serial */
576 unsigned int num_serial = dev->subsystem_device & 0xf;
577
578 if (num_serial == 0)
579 return -ENODEV;
580 return num_serial;
581}
582
583static int
70db3d91 584pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 585 struct uart_port *port, int idx)
586{
587 unsigned int bar, offset = board->first_offset, maxnr;
588
589 bar = FL_GET_BASE(board->flags);
590 if (board->flags & FL_BASE_BARS)
591 bar += idx;
592 else
593 offset += idx * board->uart_offset;
594
2427ddd8
GKH		 595 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
596 (board->reg_shift + 3);
1da177e4
LT		 597
598 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
599 return 1;
600
70db3d91 601 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 602}
603
604/* This should be in linux/pci_ids.h */
605#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
606#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
607#define PCI_DEVICE_ID_OCTPRO 0x0001
608#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
609#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
610#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
611#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
612
613/*
614 * Master list of serial port init/setup/exit quirks.
615 * This does not describe the general nature of the port.
616 * (ie, baud base, number and location of ports, etc)
617 *
618 * This list is ordered alphabetically by vendor then device.
619 * Specific entries must come before more generic entries.
620 */
621static struct pci_serial_quirk pci_serial_quirks[] = {
622 /*
61a116ef 623 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 624 * It is not clear whether this applies to all products.
625 */
626 {
627 .vendor = PCI_VENDOR_ID_AFAVLAB,
628 .device = PCI_ANY_ID,
629 .subvendor = PCI_ANY_ID,
630 .subdevice = PCI_ANY_ID,
631 .setup = afavlab_setup,
632 },
633 /*
634 * HP Diva
635 */
636 {
637 .vendor = PCI_VENDOR_ID_HP,
638 .device = PCI_DEVICE_ID_HP_DIVA,
639 .subvendor = PCI_ANY_ID,
640 .subdevice = PCI_ANY_ID,
641 .init = pci_hp_diva_init,
642 .setup = pci_hp_diva_setup,
643 },
644 /*
645 * Intel
646 */
647 {
648 .vendor = PCI_VENDOR_ID_INTEL,
649 .device = PCI_DEVICE_ID_INTEL_80960_RP,
650 .subvendor = 0xe4bf,
651 .subdevice = PCI_ANY_ID,
652 .init = pci_inteli960ni_init,
653 .setup = pci_default_setup,
654 },
655 /*
656 * Panacom
657 */
658 {
659 .vendor = PCI_VENDOR_ID_PANACOM,
660 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
661 .subvendor = PCI_ANY_ID,
662 .subdevice = PCI_ANY_ID,
663 .init = pci_plx9050_init,
664 .setup = pci_default_setup,
665 .exit = __devexit_p(pci_plx9050_exit),
666 },
667 {
668 .vendor = PCI_VENDOR_ID_PANACOM,
669 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
670 .subvendor = PCI_ANY_ID,
671 .subdevice = PCI_ANY_ID,
672 .init = pci_plx9050_init,
673 .setup = pci_default_setup,
674 .exit = __devexit_p(pci_plx9050_exit),
675 },
676 /*
677 * PLX
678 */
48212008
TH		 679 {
680 .vendor = PCI_VENDOR_ID_PLX,
681 .device = PCI_DEVICE_ID_PLX_9030,
682 .subvendor = PCI_SUBVENDOR_ID_PERLE,
683 .subdevice = PCI_ANY_ID,
684 .setup = pci_default_setup,
685 },
add7b58e
BH		 686 {
687 .vendor = PCI_VENDOR_ID_PLX,
688 .device = PCI_DEVICE_ID_PLX_9050,
689 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
690 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
691 .init = pci_plx9050_init,
692 .setup = pci_default_setup,
693 .exit = __devexit_p(pci_plx9050_exit),
694 },
1da177e4
LT		 695 {
696 .vendor = PCI_VENDOR_ID_PLX,
697 .device = PCI_DEVICE_ID_PLX_9050,
698 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
699 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
700 .init = pci_plx9050_init,
701 .setup = pci_default_setup,
702 .exit = __devexit_p(pci_plx9050_exit),
703 },
704 {
705 .vendor = PCI_VENDOR_ID_PLX,
706 .device = PCI_DEVICE_ID_PLX_ROMULUS,
707 .subvendor = PCI_VENDOR_ID_PLX,
708 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
709 .init = pci_plx9050_init,
710 .setup = pci_default_setup,
711 .exit = __devexit_p(pci_plx9050_exit),
712 },
713 /*
714 * SBS Technologies, Inc., PMC-OCTALPRO 232
715 */
716 {
717 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
718 .device = PCI_DEVICE_ID_OCTPRO,
719 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
720 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
721 .init = sbs_init,
722 .setup = sbs_setup,
723 .exit = __devexit_p(sbs_exit),
724 },
725 /*
726 * SBS Technologies, Inc., PMC-OCTALPRO 422
727 */
728 {
729 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
730 .device = PCI_DEVICE_ID_OCTPRO,
731 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
732 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
733 .init = sbs_init,
734 .setup = sbs_setup,
735 .exit = __devexit_p(sbs_exit),
736 },
737 /*
738 * SBS Technologies, Inc., P-Octal 232
739 */
740 {
741 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
742 .device = PCI_DEVICE_ID_OCTPRO,
743 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
744 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
745 .init = sbs_init,
746 .setup = sbs_setup,
747 .exit = __devexit_p(sbs_exit),
748 },
749 /*
750 * SBS Technologies, Inc., P-Octal 422
751 */
752 {
753 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
754 .device = PCI_DEVICE_ID_OCTPRO,
755 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
756 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
757 .init = sbs_init,
758 .setup = sbs_setup,
759 .exit = __devexit_p(sbs_exit),
760 },
1da177e4 761 /*
61a116ef 762 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 763 */
764 {
765 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 766 .device = PCI_ANY_ID,
1da177e4
LT		 767 .subvendor = PCI_ANY_ID,
768 .subdevice = PCI_ANY_ID,
67d74b87 769 .init = pci_siig_init,
3ec9c594 770 .setup = pci_siig_setup,
1da177e4
LT		 771 },
772 /*
773 * Titan cards
774 */
775 {
776 .vendor = PCI_VENDOR_ID_TITAN,
777 .device = PCI_DEVICE_ID_TITAN_400L,
778 .subvendor = PCI_ANY_ID,
779 .subdevice = PCI_ANY_ID,
780 .setup = titan_400l_800l_setup,
781 },
782 {
783 .vendor = PCI_VENDOR_ID_TITAN,
784 .device = PCI_DEVICE_ID_TITAN_800L,
785 .subvendor = PCI_ANY_ID,
786 .subdevice = PCI_ANY_ID,
787 .setup = titan_400l_800l_setup,
788 },
789 /*
790 * Timedia cards
791 */
792 {
793 .vendor = PCI_VENDOR_ID_TIMEDIA,
794 .device = PCI_DEVICE_ID_TIMEDIA_1889,
795 .subvendor = PCI_VENDOR_ID_TIMEDIA,
796 .subdevice = PCI_ANY_ID,
797 .init = pci_timedia_init,
798 .setup = pci_timedia_setup,
799 },
800 {
801 .vendor = PCI_VENDOR_ID_TIMEDIA,
802 .device = PCI_ANY_ID,
803 .subvendor = PCI_ANY_ID,
804 .subdevice = PCI_ANY_ID,
805 .setup = pci_timedia_setup,
806 },
807 /*
808 * Xircom cards
809 */
810 {
811 .vendor = PCI_VENDOR_ID_XIRCOM,
812 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
813 .subvendor = PCI_ANY_ID,
814 .subdevice = PCI_ANY_ID,
815 .init = pci_xircom_init,
816 .setup = pci_default_setup,
817 },
818 /*
61a116ef 819 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 820 */
821 {
822 .vendor = PCI_VENDOR_ID_NETMOS,
823 .device = PCI_ANY_ID,
824 .subvendor = PCI_ANY_ID,
825 .subdevice = PCI_ANY_ID,
826 .init = pci_netmos_init,
827 .setup = pci_default_setup,
828 },
829 /*
830 * Default "match everything" terminator entry
831 */
832 {
833 .vendor = PCI_ANY_ID,
834 .device = PCI_ANY_ID,
835 .subvendor = PCI_ANY_ID,
836 .subdevice = PCI_ANY_ID,
837 .setup = pci_default_setup,
838 }
839};
840
841static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
842{
843 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
844}
845
846static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
847{
848 struct pci_serial_quirk *quirk;
849
850 for (quirk = pci_serial_quirks; ; quirk++)
851 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
852 quirk_id_matches(quirk->device, dev->device) &&
853 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
854 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
855 break;
856 return quirk;
857}
858
dd68e88c
AM		 859static inline int get_pci_irq(struct pci_dev *dev,
860 struct pciserial_board *board)
1da177e4
LT		 861{
862 if (board->flags & FL_NOIRQ)
863 return 0;
864 else
865 return dev->irq;
866}
867
868/*
869 * This is the configuration table for all of the PCI serial boards
870 * which we support. It is directly indexed by the pci_board_num_t enum
871 * value, which is encoded in the pci_device_id PCI probe table's
872 * driver_data member.
873 *
874 * The makeup of these names are:
26e92861 875 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 876 *
26e92861
GH		 877 * bn = PCI BAR number
878 * bt = Index using PCI BARs
879 * n = number of serial ports
880 * baud = baud rate
881 * offsetinhex = offset for each sequential port (in hex)
1da177e4 882 *
26e92861 883 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 884 *
1da177e4
LT		 885 * Please note: in theory if n = 1, _bt infix should make no difference.
886 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
887 */
888enum pci_board_num_t {
889 pbn_default = 0,
890
891 pbn_b0_1_115200,
892 pbn_b0_2_115200,
893 pbn_b0_4_115200,
894 pbn_b0_5_115200,
895
896 pbn_b0_1_921600,
897 pbn_b0_2_921600,
898 pbn_b0_4_921600,
899
db1de159
DR		 900 pbn_b0_2_1130000,
901
fbc0dc0d
AP		 902 pbn_b0_4_1152000,
903
26e92861
GH		 904 pbn_b0_2_1843200,
905 pbn_b0_4_1843200,
906
907 pbn_b0_2_1843200_200,
908 pbn_b0_4_1843200_200,
909 pbn_b0_8_1843200_200,
910
1da177e4
LT		 911 pbn_b0_bt_1_115200,
912 pbn_b0_bt_2_115200,
913 pbn_b0_bt_8_115200,
914
915 pbn_b0_bt_1_460800,
916 pbn_b0_bt_2_460800,
917 pbn_b0_bt_4_460800,
918
919 pbn_b0_bt_1_921600,
920 pbn_b0_bt_2_921600,
921 pbn_b0_bt_4_921600,
922 pbn_b0_bt_8_921600,
923
924 pbn_b1_1_115200,
925 pbn_b1_2_115200,
926 pbn_b1_4_115200,
927 pbn_b1_8_115200,
928
929 pbn_b1_1_921600,
930 pbn_b1_2_921600,
931 pbn_b1_4_921600,
932 pbn_b1_8_921600,
933
26e92861
GH		 934 pbn_b1_2_1250000,
935
1da177e4
LT		 936 pbn_b1_bt_2_921600,
937
938 pbn_b1_1_1382400,
939 pbn_b1_2_1382400,
940 pbn_b1_4_1382400,
941 pbn_b1_8_1382400,
942
943 pbn_b2_1_115200,
737c1756 944 pbn_b2_2_115200,
a9cccd34 945 pbn_b2_4_115200,
1da177e4
LT		 946 pbn_b2_8_115200,
947
948 pbn_b2_1_460800,
949 pbn_b2_4_460800,
950 pbn_b2_8_460800,
951 pbn_b2_16_460800,
952
953 pbn_b2_1_921600,
954 pbn_b2_4_921600,
955 pbn_b2_8_921600,
956
957 pbn_b2_bt_1_115200,
958 pbn_b2_bt_2_115200,
959 pbn_b2_bt_4_115200,
960
961 pbn_b2_bt_2_921600,
962 pbn_b2_bt_4_921600,
963
d9004eb4 964 pbn_b3_2_115200,
1da177e4
LT		 965 pbn_b3_4_115200,
966 pbn_b3_8_115200,
967
968 /*
969 * Board-specific versions.
970 */
971 pbn_panacom,
972 pbn_panacom2,
973 pbn_panacom4,
add7b58e 974 pbn_exsys_4055,
1da177e4
LT		 975 pbn_plx_romulus,
976 pbn_oxsemi,
977 pbn_intel_i960,
978 pbn_sgi_ioc3,
1da177e4
LT		 979 pbn_computone_4,
980 pbn_computone_6,
981 pbn_computone_8,
982 pbn_sbsxrsio,
983 pbn_exar_XR17C152,
984 pbn_exar_XR17C154,
985 pbn_exar_XR17C158,
986};
987
988/*
989 * uart_offset - the space between channels
990 * reg_shift - describes how the UART registers are mapped
991 * to PCI memory by the card.
992 * For example IER register on SBS, Inc. PMC-OctPro is located at
993 * offset 0x10 from the UART base, while UART_IER is defined as 1
994 * in include/linux/serial_reg.h,
995 * see first lines of serial_in() and serial_out() in 8250.c
996*/
997
1c7c1fe5 998static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 999 [pbn_default] = {
1000 .flags = FL_BASE0,
1001 .num_ports = 1,
1002 .base_baud = 115200,
1003 .uart_offset = 8,
1004 },
1005 [pbn_b0_1_115200] = {
1006 .flags = FL_BASE0,
1007 .num_ports = 1,
1008 .base_baud = 115200,
1009 .uart_offset = 8,
1010 },
1011 [pbn_b0_2_115200] = {
1012 .flags = FL_BASE0,
1013 .num_ports = 2,
1014 .base_baud = 115200,
1015 .uart_offset = 8,
1016 },
1017 [pbn_b0_4_115200] = {
1018 .flags = FL_BASE0,
1019 .num_ports = 4,
1020 .base_baud = 115200,
1021 .uart_offset = 8,
1022 },
1023 [pbn_b0_5_115200] = {
1024 .flags = FL_BASE0,
1025 .num_ports = 5,
1026 .base_baud = 115200,
1027 .uart_offset = 8,
1028 },
1029
1030 [pbn_b0_1_921600] = {
1031 .flags = FL_BASE0,
1032 .num_ports = 1,
1033 .base_baud = 921600,
1034 .uart_offset = 8,
1035 },
1036 [pbn_b0_2_921600] = {
1037 .flags = FL_BASE0,
1038 .num_ports = 2,
1039 .base_baud = 921600,
1040 .uart_offset = 8,
1041 },
1042 [pbn_b0_4_921600] = {
1043 .flags = FL_BASE0,
1044 .num_ports = 4,
1045 .base_baud = 921600,
1046 .uart_offset = 8,
1047 },
db1de159
DR		 1048
1049 [pbn_b0_2_1130000] = {
1050 .flags = FL_BASE0,
1051 .num_ports = 2,
1052 .base_baud = 1130000,
1053 .uart_offset = 8,
1054 },
1055
fbc0dc0d
AP		 1056 [pbn_b0_4_1152000] = {
1057 .flags = FL_BASE0,
1058 .num_ports = 4,
1059 .base_baud = 1152000,
1060 .uart_offset = 8,
1061 },
1da177e4 1062
26e92861
GH		 1063 [pbn_b0_2_1843200] = {
1064 .flags = FL_BASE0,
1065 .num_ports = 2,
1066 .base_baud = 1843200,
1067 .uart_offset = 8,
1068 },
1069 [pbn_b0_4_1843200] = {
1070 .flags = FL_BASE0,
1071 .num_ports = 4,
1072 .base_baud = 1843200,
1073 .uart_offset = 8,
1074 },
1075
1076 [pbn_b0_2_1843200_200] = {
1077 .flags = FL_BASE0,
1078 .num_ports = 2,
1079 .base_baud = 1843200,
1080 .uart_offset = 0x200,
1081 },
1082 [pbn_b0_4_1843200_200] = {
1083 .flags = FL_BASE0,
1084 .num_ports = 4,
1085 .base_baud = 1843200,
1086 .uart_offset = 0x200,
1087 },
1088 [pbn_b0_8_1843200_200] = {
1089 .flags = FL_BASE0,
1090 .num_ports = 8,
1091 .base_baud = 1843200,
1092 .uart_offset = 0x200,
1093 },
1094
1da177e4
LT		 1095 [pbn_b0_bt_1_115200] = {
1096 .flags = FL_BASE0|FL_BASE_BARS,
1097 .num_ports = 1,
1098 .base_baud = 115200,
1099 .uart_offset = 8,
1100 },
1101 [pbn_b0_bt_2_115200] = {
1102 .flags = FL_BASE0|FL_BASE_BARS,
1103 .num_ports = 2,
1104 .base_baud = 115200,
1105 .uart_offset = 8,
1106 },
1107 [pbn_b0_bt_8_115200] = {
1108 .flags = FL_BASE0|FL_BASE_BARS,
1109 .num_ports = 8,
1110 .base_baud = 115200,
1111 .uart_offset = 8,
1112 },
1113
1114 [pbn_b0_bt_1_460800] = {
1115 .flags = FL_BASE0|FL_BASE_BARS,
1116 .num_ports = 1,
1117 .base_baud = 460800,
1118 .uart_offset = 8,
1119 },
1120 [pbn_b0_bt_2_460800] = {
1121 .flags = FL_BASE0|FL_BASE_BARS,
1122 .num_ports = 2,
1123 .base_baud = 460800,
1124 .uart_offset = 8,
1125 },
1126 [pbn_b0_bt_4_460800] = {
1127 .flags = FL_BASE0|FL_BASE_BARS,
1128 .num_ports = 4,
1129 .base_baud = 460800,
1130 .uart_offset = 8,
1131 },
1132
1133 [pbn_b0_bt_1_921600] = {
1134 .flags = FL_BASE0|FL_BASE_BARS,
1135 .num_ports = 1,
1136 .base_baud = 921600,
1137 .uart_offset = 8,
1138 },
1139 [pbn_b0_bt_2_921600] = {
1140 .flags = FL_BASE0|FL_BASE_BARS,
1141 .num_ports = 2,
1142 .base_baud = 921600,
1143 .uart_offset = 8,
1144 },
1145 [pbn_b0_bt_4_921600] = {
1146 .flags = FL_BASE0|FL_BASE_BARS,
1147 .num_ports = 4,
1148 .base_baud = 921600,
1149 .uart_offset = 8,
1150 },
1151 [pbn_b0_bt_8_921600] = {
1152 .flags = FL_BASE0|FL_BASE_BARS,
1153 .num_ports = 8,
1154 .base_baud = 921600,
1155 .uart_offset = 8,
1156 },
1157
1158 [pbn_b1_1_115200] = {
1159 .flags = FL_BASE1,
1160 .num_ports = 1,
1161 .base_baud = 115200,
1162 .uart_offset = 8,
1163 },
1164 [pbn_b1_2_115200] = {
1165 .flags = FL_BASE1,
1166 .num_ports = 2,
1167 .base_baud = 115200,
1168 .uart_offset = 8,
1169 },
1170 [pbn_b1_4_115200] = {
1171 .flags = FL_BASE1,
1172 .num_ports = 4,
1173 .base_baud = 115200,
1174 .uart_offset = 8,
1175 },
1176 [pbn_b1_8_115200] = {
1177 .flags = FL_BASE1,
1178 .num_ports = 8,
1179 .base_baud = 115200,
1180 .uart_offset = 8,
1181 },
1182
1183 [pbn_b1_1_921600] = {
1184 .flags = FL_BASE1,
1185 .num_ports = 1,
1186 .base_baud = 921600,
1187 .uart_offset = 8,
1188 },
1189 [pbn_b1_2_921600] = {
1190 .flags = FL_BASE1,
1191 .num_ports = 2,
1192 .base_baud = 921600,
1193 .uart_offset = 8,
1194 },
1195 [pbn_b1_4_921600] = {
1196 .flags = FL_BASE1,
1197 .num_ports = 4,
1198 .base_baud = 921600,
1199 .uart_offset = 8,
1200 },
1201 [pbn_b1_8_921600] = {
1202 .flags = FL_BASE1,
1203 .num_ports = 8,
1204 .base_baud = 921600,
1205 .uart_offset = 8,
1206 },
26e92861
GH		 1207 [pbn_b1_2_1250000] = {
1208 .flags = FL_BASE1,
1209 .num_ports = 2,
1210 .base_baud = 1250000,
1211 .uart_offset = 8,
1212 },
1da177e4
LT		 1213
1214 [pbn_b1_bt_2_921600] = {
1215 .flags = FL_BASE1|FL_BASE_BARS,
1216 .num_ports = 2,
1217 .base_baud = 921600,
1218 .uart_offset = 8,
1219 },
1220
1221 [pbn_b1_1_1382400] = {
1222 .flags = FL_BASE1,
1223 .num_ports = 1,
1224 .base_baud = 1382400,
1225 .uart_offset = 8,
1226 },
1227 [pbn_b1_2_1382400] = {
1228 .flags = FL_BASE1,
1229 .num_ports = 2,
1230 .base_baud = 1382400,
1231 .uart_offset = 8,
1232 },
1233 [pbn_b1_4_1382400] = {
1234 .flags = FL_BASE1,
1235 .num_ports = 4,
1236 .base_baud = 1382400,
1237 .uart_offset = 8,
1238 },
1239 [pbn_b1_8_1382400] = {
1240 .flags = FL_BASE1,
1241 .num_ports = 8,
1242 .base_baud = 1382400,
1243 .uart_offset = 8,
1244 },
1245
1246 [pbn_b2_1_115200] = {
1247 .flags = FL_BASE2,
1248 .num_ports = 1,
1249 .base_baud = 115200,
1250 .uart_offset = 8,
1251 },
737c1756
PH		 1252 [pbn_b2_2_115200] = {
1253 .flags = FL_BASE2,
1254 .num_ports = 2,
1255 .base_baud = 115200,
1256 .uart_offset = 8,
1257 },
a9cccd34
MF		 1258 [pbn_b2_4_115200] = {
1259 .flags = FL_BASE2,
1260 .num_ports = 4,
1261 .base_baud = 115200,
1262 .uart_offset = 8,
1263 },
1da177e4
LT		 1264 [pbn_b2_8_115200] = {
1265 .flags = FL_BASE2,
1266 .num_ports = 8,
1267 .base_baud = 115200,
1268 .uart_offset = 8,
1269 },
1270
1271 [pbn_b2_1_460800] = {
1272 .flags = FL_BASE2,
1273 .num_ports = 1,
1274 .base_baud = 460800,
1275 .uart_offset = 8,
1276 },
1277 [pbn_b2_4_460800] = {
1278 .flags = FL_BASE2,
1279 .num_ports = 4,
1280 .base_baud = 460800,
1281 .uart_offset = 8,
1282 },
1283 [pbn_b2_8_460800] = {
1284 .flags = FL_BASE2,
1285 .num_ports = 8,
1286 .base_baud = 460800,
1287 .uart_offset = 8,
1288 },
1289 [pbn_b2_16_460800] = {
1290 .flags = FL_BASE2,
1291 .num_ports = 16,
1292 .base_baud = 460800,
1293 .uart_offset = 8,
1294 },
1295
1296 [pbn_b2_1_921600] = {
1297 .flags = FL_BASE2,
1298 .num_ports = 1,
1299 .base_baud = 921600,
1300 .uart_offset = 8,
1301 },
1302 [pbn_b2_4_921600] = {
1303 .flags = FL_BASE2,
1304 .num_ports = 4,
1305 .base_baud = 921600,
1306 .uart_offset = 8,
1307 },
1308 [pbn_b2_8_921600] = {
1309 .flags = FL_BASE2,
1310 .num_ports = 8,
1311 .base_baud = 921600,
1312 .uart_offset = 8,
1313 },
1314
1315 [pbn_b2_bt_1_115200] = {
1316 .flags = FL_BASE2|FL_BASE_BARS,
1317 .num_ports = 1,
1318 .base_baud = 115200,
1319 .uart_offset = 8,
1320 },
1321 [pbn_b2_bt_2_115200] = {
1322 .flags = FL_BASE2|FL_BASE_BARS,
1323 .num_ports = 2,
1324 .base_baud = 115200,
1325 .uart_offset = 8,
1326 },
1327 [pbn_b2_bt_4_115200] = {
1328 .flags = FL_BASE2|FL_BASE_BARS,
1329 .num_ports = 4,
1330 .base_baud = 115200,
1331 .uart_offset = 8,
1332 },
1333
1334 [pbn_b2_bt_2_921600] = {
1335 .flags = FL_BASE2|FL_BASE_BARS,
1336 .num_ports = 2,
1337 .base_baud = 921600,
1338 .uart_offset = 8,
1339 },
1340 [pbn_b2_bt_4_921600] = {
1341 .flags = FL_BASE2|FL_BASE_BARS,
1342 .num_ports = 4,
1343 .base_baud = 921600,
1344 .uart_offset = 8,
1345 },
1346
d9004eb4
ABL		 1347 [pbn_b3_2_115200] = {
1348 .flags = FL_BASE3,
1349 .num_ports = 2,
1350 .base_baud = 115200,
1351 .uart_offset = 8,
1352 },
1da177e4
LT		 1353 [pbn_b3_4_115200] = {
1354 .flags = FL_BASE3,
1355 .num_ports = 4,
1356 .base_baud = 115200,
1357 .uart_offset = 8,
1358 },
1359 [pbn_b3_8_115200] = {
1360 .flags = FL_BASE3,
1361 .num_ports = 8,
1362 .base_baud = 115200,
1363 .uart_offset = 8,
1364 },
1365
1366 /*
1367 * Entries following this are board-specific.
1368 */
1369
1370 /*
1371 * Panacom - IOMEM
1372 */
1373 [pbn_panacom] = {
1374 .flags = FL_BASE2,
1375 .num_ports = 2,
1376 .base_baud = 921600,
1377 .uart_offset = 0x400,
1378 .reg_shift = 7,
1379 },
1380 [pbn_panacom2] = {
1381 .flags = FL_BASE2|FL_BASE_BARS,
1382 .num_ports = 2,
1383 .base_baud = 921600,
1384 .uart_offset = 0x400,
1385 .reg_shift = 7,
1386 },
1387 [pbn_panacom4] = {
1388 .flags = FL_BASE2|FL_BASE_BARS,
1389 .num_ports = 4,
1390 .base_baud = 921600,
1391 .uart_offset = 0x400,
1392 .reg_shift = 7,
1393 },
1394
add7b58e
BH		 1395 [pbn_exsys_4055] = {
1396 .flags = FL_BASE2,
1397 .num_ports = 4,
1398 .base_baud = 115200,
1399 .uart_offset = 8,
1400 },
1401
1da177e4
LT		 1402 /* I think this entry is broken - the first_offset looks wrong --rmk */
1403 [pbn_plx_romulus] = {
1404 .flags = FL_BASE2,
1405 .num_ports = 4,
1406 .base_baud = 921600,
1407 .uart_offset = 8 << 2,
1408 .reg_shift = 2,
1409 .first_offset = 0x03,
1410 },
1411
1412 /*
1413 * This board uses the size of PCI Base region 0 to
1414 * signal now many ports are available
1415 */
1416 [pbn_oxsemi] = {
1417 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1418 .num_ports = 32,
1419 .base_baud = 115200,
1420 .uart_offset = 8,
1421 },
1422
1423 /*
1424 * EKF addition for i960 Boards form EKF with serial port.
1425 * Max 256 ports.
1426 */
1427 [pbn_intel_i960] = {
1428 .flags = FL_BASE0,
1429 .num_ports = 32,
1430 .base_baud = 921600,
1431 .uart_offset = 8 << 2,
1432 .reg_shift = 2,
1433 .first_offset = 0x10000,
1434 },
1435 [pbn_sgi_ioc3] = {
1436 .flags = FL_BASE0|FL_NOIRQ,
1437 .num_ports = 1,
1438 .base_baud = 458333,
1439 .uart_offset = 8,
1440 .reg_shift = 0,
1441 .first_offset = 0x20178,
1442 },
1443
1da177e4
LT		 1444 /*
1445 * Computone - uses IOMEM.
1446 */
1447 [pbn_computone_4] = {
1448 .flags = FL_BASE0,
1449 .num_ports = 4,
1450 .base_baud = 921600,
1451 .uart_offset = 0x40,
1452 .reg_shift = 2,
1453 .first_offset = 0x200,
1454 },
1455 [pbn_computone_6] = {
1456 .flags = FL_BASE0,
1457 .num_ports = 6,
1458 .base_baud = 921600,
1459 .uart_offset = 0x40,
1460 .reg_shift = 2,
1461 .first_offset = 0x200,
1462 },
1463 [pbn_computone_8] = {
1464 .flags = FL_BASE0,
1465 .num_ports = 8,
1466 .base_baud = 921600,
1467 .uart_offset = 0x40,
1468 .reg_shift = 2,
1469 .first_offset = 0x200,
1470 },
1471 [pbn_sbsxrsio] = {
1472 .flags = FL_BASE0,
1473 .num_ports = 8,
1474 .base_baud = 460800,
1475 .uart_offset = 256,
1476 .reg_shift = 4,
1477 },
1478 /*
1479 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1480 * Only basic 16550A support.
1481 * XR17C15[24] are not tested, but they should work.
1482 */
1483 [pbn_exar_XR17C152] = {
1484 .flags = FL_BASE0,
1485 .num_ports = 2,
1486 .base_baud = 921600,
1487 .uart_offset = 0x200,
1488 },
1489 [pbn_exar_XR17C154] = {
1490 .flags = FL_BASE0,
1491 .num_ports = 4,
1492 .base_baud = 921600,
1493 .uart_offset = 0x200,
1494 },
1495 [pbn_exar_XR17C158] = {
1496 .flags = FL_BASE0,
1497 .num_ports = 8,
1498 .base_baud = 921600,
1499 .uart_offset = 0x200,
1500 },
1501};
1502
1503/*
1504 * Given a complete unknown PCI device, try to use some heuristics to
1505 * guess what the configuration might be, based on the pitiful PCI
1506 * serial specs. Returns 0 on success, 1 on failure.
1507 */
1508static int __devinit
1c7c1fe5 1509serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4
LT		 1510{
1511 int num_iomem, num_port, first_port = -1, i;
1512
1513 /*
1514 * If it is not a communications device or the programming
1515 * interface is greater than 6, give up.
1516 *
1517 * (Should we try to make guesses for multiport serial devices
1518 * later?)
1519 */
1520 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1521 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1522 (dev->class & 0xff) > 6)
1523 return -ENODEV;
1524
1525 num_iomem = num_port = 0;
1526 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1527 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1528 num_port++;
1529 if (first_port == -1)
1530 first_port = i;
1531 }
1532 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1533 num_iomem++;
1534 }
1535
1536 /*
1537 * If there is 1 or 0 iomem regions, and exactly one port,
1538 * use it. We guess the number of ports based on the IO
1539 * region size.
1540 */
1541 if (num_iomem <= 1 && num_port == 1) {
1542 board->flags = first_port;
1543 board->num_ports = pci_resource_len(dev, first_port) / 8;
1544 return 0;
1545 }
1546
1547 /*
1548 * Now guess if we've got a board which indexes by BARs.
1549 * Each IO BAR should be 8 bytes, and they should follow
1550 * consecutively.
1551 */
1552 first_port = -1;
1553 num_port = 0;
1554 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1555 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1556 pci_resource_len(dev, i) == 8 &&
1557 (first_port == -1 || (first_port + num_port) == i)) {
1558 num_port++;
1559 if (first_port == -1)
1560 first_port = i;
1561 }
1562 }
1563
1564 if (num_port > 1) {
1565 board->flags = first_port | FL_BASE_BARS;
1566 board->num_ports = num_port;
1567 return 0;
1568 }
1569
1570 return -ENODEV;
1571}
1572
1573static inline int
1c7c1fe5
RK		 1574serial_pci_matches(struct pciserial_board *board,
1575 struct pciserial_board *guessed)
1da177e4
LT		 1576{
1577 return
1578 board->num_ports == guessed->num_ports &&
1579 board->base_baud == guessed->base_baud &&
1580 board->uart_offset == guessed->uart_offset &&
1581 board->reg_shift == guessed->reg_shift &&
1582 board->first_offset == guessed->first_offset;
1583}
1584
241fc436
RK		 1585struct serial_private *
1586pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 1587{
72ce9a83 1588 struct uart_port serial_port;
1da177e4 1589 struct serial_private *priv;
1da177e4
LT		 1590 struct pci_serial_quirk *quirk;
1591 int rc, nr_ports, i;
1592
1da177e4
LT		 1593 nr_ports = board->num_ports;
1594
1595 /*
1596 * Find an init and setup quirks.
1597 */
1598 quirk = find_quirk(dev);
1599
1600 /*
1601 * Run the new-style initialization function.
1602 * The initialization function returns:
1603 * <0 - error
1604 * 0 - use board->num_ports
1605 * >0 - number of ports
1606 */
1607 if (quirk->init) {
1608 rc = quirk->init(dev);
241fc436
RK		 1609 if (rc < 0) {
1610 priv = ERR_PTR(rc);
1611 goto err_out;
1612 }
1da177e4
LT		 1613 if (rc)
1614 nr_ports = rc;
1615 }
1616
8f31bb39 1617 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 1618 sizeof(unsigned int) * nr_ports,
1619 GFP_KERNEL);
1620 if (!priv) {
241fc436
RK		 1621 priv = ERR_PTR(-ENOMEM);
1622 goto err_deinit;
1da177e4
LT		 1623 }
1624
70db3d91 1625 priv->dev = dev;
1da177e4 1626 priv->quirk = quirk;
1da177e4 1627
72ce9a83
RK		 1628 memset(&serial_port, 0, sizeof(struct uart_port));
1629 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1630 serial_port.uartclk = board->base_baud * 16;
1631 serial_port.irq = get_pci_irq(dev, board);
1632 serial_port.dev = &dev->dev;
1633
1da177e4 1634 for (i = 0; i < nr_ports; i++) {
70db3d91 1635 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 1636 break;
72ce9a83 1637
1da177e4
LT		 1638#ifdef SERIAL_DEBUG_PCI
1639 printk("Setup PCI port: port %x, irq %d, type %d\n",
1640 serial_port.iobase, serial_port.irq, serial_port.iotype);
1641#endif
1642
1643 priv->line[i] = serial8250_register_port(&serial_port);
1644 if (priv->line[i] < 0) {
1645 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1646 break;
1647 }
1648 }
1649
1650 priv->nr = i;
1651
241fc436 1652 return priv;
1da177e4 1653
241fc436 1654 err_deinit:
1da177e4
LT		 1655 if (quirk->exit)
1656 quirk->exit(dev);
241fc436
RK		 1657 err_out:
1658 return priv;
1da177e4 1659}
241fc436 1660EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 1661
241fc436 1662void pciserial_remove_ports(struct serial_private *priv)
1da177e4 1663{
056a8763
RK		 1664 struct pci_serial_quirk *quirk;
1665 int i;
1da177e4 1666
056a8763
RK		 1667 for (i = 0; i < priv->nr; i++)
1668 serial8250_unregister_port(priv->line[i]);
1da177e4 1669
056a8763
RK		 1670 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1671 if (priv->remapped_bar[i])
1672 iounmap(priv->remapped_bar[i]);
1673 priv->remapped_bar[i] = NULL;
1674 }
1da177e4 1675
056a8763
RK		 1676 /*
1677 * Find the exit quirks.
1678 */
241fc436 1679 quirk = find_quirk(priv->dev);
056a8763 1680 if (quirk->exit)
241fc436
RK		 1681 quirk->exit(priv->dev);
1682
1683 kfree(priv);
1684}
1685EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1686
1687void pciserial_suspend_ports(struct serial_private *priv)
1688{
1689 int i;
1690
1691 for (i = 0; i < priv->nr; i++)
1692 if (priv->line[i] >= 0)
1693 serial8250_suspend_port(priv->line[i]);
1694}
1695EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1696
1697void pciserial_resume_ports(struct serial_private *priv)
1698{
1699 int i;
1700
1701 /*
1702 * Ensure that the board is correctly configured.
1703 */
1704 if (priv->quirk->init)
1705 priv->quirk->init(priv->dev);
1706
1707 for (i = 0; i < priv->nr; i++)
1708 if (priv->line[i] >= 0)
1709 serial8250_resume_port(priv->line[i]);
1710}
1711EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1712
1713/*
1714 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1715 * to the arrangement of serial ports on a PCI card.
1716 */
1717static int __devinit
1718pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1719{
1720 struct serial_private *priv;
1721 struct pciserial_board *board, tmp;
1722 int rc;
1723
1724 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1725 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1726 ent->driver_data);
1727 return -EINVAL;
1728 }
1729
1730 board = &pci_boards[ent->driver_data];
1731
1732 rc = pci_enable_device(dev);
1733 if (rc)
1734 return rc;
1735
1736 if (ent->driver_data == pbn_default) {
1737 /*
1738 * Use a copy of the pci_board entry for this;
1739 * avoid changing entries in the table.
1740 */
1741 memcpy(&tmp, board, sizeof(struct pciserial_board));
1742 board = &tmp;
1743
1744 /*
1745 * We matched one of our class entries. Try to
1746 * determine the parameters of this board.
1747 */
1748 rc = serial_pci_guess_board(dev, board);
1749 if (rc)
1750 goto disable;
1751 } else {
1752 /*
1753 * We matched an explicit entry. If we are able to
1754 * detect this boards settings with our heuristic,
1755 * then we no longer need this entry.
1756 */
1757 memcpy(&tmp, &pci_boards[pbn_default],
1758 sizeof(struct pciserial_board));
1759 rc = serial_pci_guess_board(dev, &tmp);
1760 if (rc == 0 && serial_pci_matches(board, &tmp))
1761 moan_device("Redundant entry in serial pci_table.",
1762 dev);
1763 }
1764
1765 priv = pciserial_init_ports(dev, board);
1766 if (!IS_ERR(priv)) {
1767 pci_set_drvdata(dev, priv);
1768 return 0;
1769 }
1770
1771 rc = PTR_ERR(priv);
1da177e4 1772
241fc436 1773 disable:
056a8763 1774 pci_disable_device(dev);
241fc436
RK		 1775 return rc;
1776}
1da177e4 1777
241fc436
RK		 1778static void __devexit pciserial_remove_one(struct pci_dev *dev)
1779{
1780 struct serial_private *priv = pci_get_drvdata(dev);
1781
1782 pci_set_drvdata(dev, NULL);
1783
1784 pciserial_remove_ports(priv);
1785
1786 pci_disable_device(dev);
1da177e4
LT		 1787}
1788
1d5e7996 1789#ifdef CONFIG_PM
1da177e4
LT		 1790static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1791{
1792 struct serial_private *priv = pci_get_drvdata(dev);
1793
241fc436
RK		 1794 if (priv)
1795 pciserial_suspend_ports(priv);
1da177e4 1796
1da177e4
LT		 1797 pci_save_state(dev);
1798 pci_set_power_state(dev, pci_choose_state(dev, state));
1799 return 0;
1800}
1801
1802static int pciserial_resume_one(struct pci_dev *dev)
1803{
1804 struct serial_private *priv = pci_get_drvdata(dev);
1805
1806 pci_set_power_state(dev, PCI_D0);
1807 pci_restore_state(dev);
1808
1809 if (priv) {
1da177e4
LT		 1810 /*
1811 * The device may have been disabled. Re-enable it.
1812 */
1813 pci_enable_device(dev);
1814
241fc436 1815 pciserial_resume_ports(priv);
1da177e4
LT		 1816 }
1817 return 0;
1818}
1d5e7996 1819#endif
1da177e4
LT		 1820
1821static struct pci_device_id serial_pci_tbl[] = {
1822 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1823 PCI_SUBVENDOR_ID_CONNECT_TECH,
1824 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1825 pbn_b1_8_1382400 },
1826 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1827 PCI_SUBVENDOR_ID_CONNECT_TECH,
1828 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1829 pbn_b1_4_1382400 },
1830 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1831 PCI_SUBVENDOR_ID_CONNECT_TECH,
1832 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1833 pbn_b1_2_1382400 },
1834 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1835 PCI_SUBVENDOR_ID_CONNECT_TECH,
1836 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1837 pbn_b1_8_1382400 },
1838 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1839 PCI_SUBVENDOR_ID_CONNECT_TECH,
1840 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1841 pbn_b1_4_1382400 },
1842 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1843 PCI_SUBVENDOR_ID_CONNECT_TECH,
1844 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1845 pbn_b1_2_1382400 },
1846 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1847 PCI_SUBVENDOR_ID_CONNECT_TECH,
1848 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1849 pbn_b1_8_921600 },
1850 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1851 PCI_SUBVENDOR_ID_CONNECT_TECH,
1852 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1853 pbn_b1_8_921600 },
1854 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1855 PCI_SUBVENDOR_ID_CONNECT_TECH,
1856 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1857 pbn_b1_4_921600 },
1858 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1859 PCI_SUBVENDOR_ID_CONNECT_TECH,
1860 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1861 pbn_b1_4_921600 },
1862 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1863 PCI_SUBVENDOR_ID_CONNECT_TECH,
1864 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1865 pbn_b1_2_921600 },
1866 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1867 PCI_SUBVENDOR_ID_CONNECT_TECH,
1868 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1869 pbn_b1_8_921600 },
1870 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1871 PCI_SUBVENDOR_ID_CONNECT_TECH,
1872 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1873 pbn_b1_8_921600 },
1874 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1875 PCI_SUBVENDOR_ID_CONNECT_TECH,
1876 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1877 pbn_b1_4_921600 },
26e92861
GH		 1878 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1879 PCI_SUBVENDOR_ID_CONNECT_TECH,
1880 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
1881 pbn_b1_2_1250000 },
1882 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1883 PCI_SUBVENDOR_ID_CONNECT_TECH,
1884 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
1885 pbn_b0_2_1843200 },
1886 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1887 PCI_SUBVENDOR_ID_CONNECT_TECH,
1888 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
1889 pbn_b0_4_1843200 },
85d1494e
YY		 1890 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1891 PCI_VENDOR_ID_AFAVLAB,
1892 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
1893 pbn_b0_4_1152000 },
26e92861
GH		 1894 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1895 PCI_SUBVENDOR_ID_CONNECT_TECH,
1896 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
1897 pbn_b0_2_1843200_200 },
1898 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1899 PCI_SUBVENDOR_ID_CONNECT_TECH,
1900 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
1901 pbn_b0_4_1843200_200 },
1902 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1903 PCI_SUBVENDOR_ID_CONNECT_TECH,
1904 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
1905 pbn_b0_8_1843200_200 },
1906 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1907 PCI_SUBVENDOR_ID_CONNECT_TECH,
1908 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
1909 pbn_b0_2_1843200_200 },
1910 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1911 PCI_SUBVENDOR_ID_CONNECT_TECH,
1912 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
1913 pbn_b0_4_1843200_200 },
1914 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1915 PCI_SUBVENDOR_ID_CONNECT_TECH,
1916 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
1917 pbn_b0_8_1843200_200 },
1918 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1919 PCI_SUBVENDOR_ID_CONNECT_TECH,
1920 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
1921 pbn_b0_2_1843200_200 },
1922 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1923 PCI_SUBVENDOR_ID_CONNECT_TECH,
1924 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
1925 pbn_b0_4_1843200_200 },
1926 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1927 PCI_SUBVENDOR_ID_CONNECT_TECH,
1928 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
1929 pbn_b0_8_1843200_200 },
1930 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1931 PCI_SUBVENDOR_ID_CONNECT_TECH,
1932 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
1933 pbn_b0_2_1843200_200 },
1934 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1935 PCI_SUBVENDOR_ID_CONNECT_TECH,
1936 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
1937 pbn_b0_4_1843200_200 },
1938 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1939 PCI_SUBVENDOR_ID_CONNECT_TECH,
1940 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
1941 pbn_b0_8_1843200_200 },
1da177e4
LT		 1942
1943 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1945 pbn_b2_bt_1_115200 },
1946 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1948 pbn_b2_bt_2_115200 },
1949 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1951 pbn_b2_bt_4_115200 },
1952 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1954 pbn_b2_bt_2_115200 },
1955 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1957 pbn_b2_bt_4_115200 },
1958 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1960 pbn_b2_8_115200 },
1961 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1963 pbn_b2_8_115200 },
1964
1965 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1967 pbn_b2_bt_2_115200 },
1968 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1970 pbn_b2_bt_2_921600 },
1971 /*
1972 * VScom SPCOM800, from sl@s.pl
1973 */
1974 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1976 pbn_b2_8_921600 },
1977 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1979 pbn_b2_4_921600 },
1980 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1981 PCI_SUBVENDOR_ID_KEYSPAN,
1982 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1983 pbn_panacom },
1984 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1986 pbn_panacom4 },
1987 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1989 pbn_panacom2 },
a9cccd34
MF		 1990 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
1991 PCI_VENDOR_ID_ESDGMBH,
1992 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
1993 pbn_b2_4_115200 },
1da177e4
LT		 1994 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1995 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1996 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1997 pbn_b2_4_460800 },
1998 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1999 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2000 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2001 pbn_b2_8_460800 },
2002 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2003 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2004 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2005 pbn_b2_16_460800 },
2006 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2007 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2008 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2009 pbn_b2_16_460800 },
2010 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2011 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2012 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2013 pbn_b2_4_460800 },
2014 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2015 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2016 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2017 pbn_b2_8_460800 },
add7b58e
BH		 2018 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2019 PCI_SUBVENDOR_ID_EXSYS,
2020 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2021 pbn_exsys_4055 },
1da177e4
LT		 2022 /*
2023 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2024 * (Exoray@isys.ca)
2025 */
2026 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2027 0x10b5, 0x106a, 0, 0,
2028 pbn_plx_romulus },
2029 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2031 pbn_b1_4_115200 },
2032 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2034 pbn_b1_2_115200 },
2035 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2037 pbn_b1_8_115200 },
2038 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2040 pbn_b1_8_115200 },
2041 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2042 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2043 pbn_b0_4_921600 },
fbc0dc0d
AP		 2044 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2045 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2046 pbn_b0_4_1152000 },
db1de159
DR		 2047
2048 /*
2049 * The below card is a little controversial since it is the
2050 * subject of a PCI vendor/device ID clash. (See
2051 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2052 * For now just used the hex ID 0x950a.
2053 */
2054 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2056 pbn_b0_2_1130000 },
1da177e4
LT		 2057 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2059 pbn_b0_4_115200 },
2060 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2062 pbn_b0_bt_2_921600 },
2063
2064 /*
2065 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2066 * from skokodyn@yahoo.com
2067 */
2068 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2069 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2070 pbn_sbsxrsio },
2071 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2072 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2073 pbn_sbsxrsio },
2074 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2075 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2076 pbn_sbsxrsio },
2077 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2078 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2079 pbn_sbsxrsio },
2080
2081 /*
2082 * Digitan DS560-558, from jimd@esoft.com
2083 */
2084 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2086 pbn_b1_1_115200 },
2087
2088 /*
2089 * Titan Electronic cards
2090 * The 400L and 800L have a custom setup quirk.
2091 */
2092 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2094 pbn_b0_1_921600 },
2095 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2097 pbn_b0_2_921600 },
2098 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2100 pbn_b0_4_921600 },
2101 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2103 pbn_b0_4_921600 },
2104 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2106 pbn_b1_1_921600 },
2107 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2109 pbn_b1_bt_2_921600 },
2110 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2112 pbn_b0_bt_4_921600 },
2113 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2115 pbn_b0_bt_8_921600 },
2116
2117 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2119 pbn_b2_1_460800 },
2120 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2122 pbn_b2_1_460800 },
2123 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2125 pbn_b2_1_460800 },
2126 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2128 pbn_b2_bt_2_921600 },
2129 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2131 pbn_b2_bt_2_921600 },
2132 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2134 pbn_b2_bt_2_921600 },
2135 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2137 pbn_b2_bt_4_921600 },
2138 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2140 pbn_b2_bt_4_921600 },
2141 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2143 pbn_b2_bt_4_921600 },
2144 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2146 pbn_b0_1_921600 },
2147 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2149 pbn_b0_1_921600 },
2150 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2152 pbn_b0_1_921600 },
2153 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2155 pbn_b0_bt_2_921600 },
2156 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2158 pbn_b0_bt_2_921600 },
2159 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2161 pbn_b0_bt_2_921600 },
2162 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2164 pbn_b0_bt_4_921600 },
2165 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2167 pbn_b0_bt_4_921600 },
2168 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2170 pbn_b0_bt_4_921600 },
3ec9c594
AP		 2171 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2173 pbn_b0_bt_8_921600 },
2174 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2176 pbn_b0_bt_8_921600 },
2177 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2179 pbn_b0_bt_8_921600 },
1da177e4
LT		 2180
2181 /*
2182 * Computone devices submitted by Doug McNash dmcnash@computone.com
2183 */
2184 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2185 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2186 0, 0, pbn_computone_4 },
2187 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2188 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2189 0, 0, pbn_computone_8 },
2190 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2191 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2192 0, 0, pbn_computone_6 },
2193
2194 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2196 pbn_oxsemi },
2197 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2198 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2199 pbn_b0_bt_1_921600 },
2200
2201 /*
2202 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2203 */
2204 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2206 pbn_b0_bt_8_115200 },
2207 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2209 pbn_b0_bt_8_115200 },
2210
2211 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2213 pbn_b0_bt_2_115200 },
2214 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2216 pbn_b0_bt_2_115200 },
2217 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2219 pbn_b0_bt_2_115200 },
2220 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2221 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2222 pbn_b0_bt_4_460800 },
2223 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2225 pbn_b0_bt_4_460800 },
2226 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2228 pbn_b0_bt_2_460800 },
2229 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2231 pbn_b0_bt_2_460800 },
2232 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2234 pbn_b0_bt_2_460800 },
2235 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2237 pbn_b0_bt_1_115200 },
2238 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2240 pbn_b0_bt_1_460800 },
2241
1fb8cacc
RK		 2242 /*
2243 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2244 * Cards are identified by their subsystem vendor IDs, which
2245 * (in hex) match the model number.
2246 *
2247 * Note that JC140x are RS422/485 cards which require ox950
2248 * ACR = 0x10, and as such are not currently fully supported.
2249 */
2250 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2251 0x1204, 0x0004, 0, 0,
2252 pbn_b0_4_921600 },
2253 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2254 0x1208, 0x0004, 0, 0,
2255 pbn_b0_4_921600 },
2256/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2257 0x1402, 0x0002, 0, 0,
2258 pbn_b0_2_921600 }, */
2259/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2260 0x1404, 0x0004, 0, 0,
2261 pbn_b0_4_921600 }, */
2262 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2263 0x1208, 0x0004, 0, 0,
2264 pbn_b0_4_921600 },
2265
1da177e4
LT		 2266 /*
2267 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2268 */
2269 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2271 pbn_b1_1_1382400 },
2272
2273 /*
2274 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2275 */
2276 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2278 pbn_b1_1_1382400 },
2279
2280 /*
2281 * RAStel 2 port modem, gerg@moreton.com.au
2282 */
2283 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2285 pbn_b2_bt_2_115200 },
2286
2287 /*
2288 * EKF addition for i960 Boards form EKF with serial port
2289 */
2290 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2291 0xE4BF, PCI_ANY_ID, 0, 0,
2292 pbn_intel_i960 },
2293
2294 /*
2295 * Xircom Cardbus/Ethernet combos
2296 */
2297 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2299 pbn_b0_1_115200 },
2300 /*
2301 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2302 */
2303 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2305 pbn_b0_1_115200 },
2306
2307 /*
2308 * Untested PCI modems, sent in from various folks...
2309 */
2310
2311 /*
2312 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2313 */
2314 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2315 0x1048, 0x1500, 0, 0,
2316 pbn_b1_1_115200 },
2317
2318 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2319 0xFF00, 0, 0, 0,
2320 pbn_sgi_ioc3 },
2321
2322 /*
2323 * HP Diva card
2324 */
2325 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2326 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2327 pbn_b1_1_115200 },
2328 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2330 pbn_b0_5_115200 },
2331 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2333 pbn_b2_1_115200 },
2334
d9004eb4
ABL		 2335 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2336 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2337 pbn_b3_2_115200 },
1da177e4
LT		 2338 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2339 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2340 pbn_b3_4_115200 },
2341 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2343 pbn_b3_8_115200 },
2344
2345 /*
2346 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2347 */
2348 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2349 PCI_ANY_ID, PCI_ANY_ID,
2350 0,
2351 0, pbn_exar_XR17C152 },
2352 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2353 PCI_ANY_ID, PCI_ANY_ID,
2354 0,
2355 0, pbn_exar_XR17C154 },
2356 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2357 PCI_ANY_ID, PCI_ANY_ID,
2358 0,
2359 0, pbn_exar_XR17C158 },
2360
2361 /*
2362 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2363 */
2364 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2366 pbn_b0_1_115200 },
2367
737c1756
PH		 2368 /*
2369 * IntaShield IS-200
2370 */
2371 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
2373 pbn_b2_2_115200 },
2374
48212008
TH		 2375 /*
2376 * Perle PCI-RAS cards
2377 */
2378 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2379 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2380 0, 0, pbn_b2_4_921600 },
2381 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2382 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2383 0, 0, pbn_b2_8_921600 },
1da177e4
LT		 2384 /*
2385 * These entries match devices with class COMMUNICATION_SERIAL,
2386 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2387 */
2388 { PCI_ANY_ID, PCI_ANY_ID,
2389 PCI_ANY_ID, PCI_ANY_ID,
2390 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2391 0xffff00, pbn_default },
2392 { PCI_ANY_ID, PCI_ANY_ID,
2393 PCI_ANY_ID, PCI_ANY_ID,
2394 PCI_CLASS_COMMUNICATION_MODEM << 8,
2395 0xffff00, pbn_default },
2396 { PCI_ANY_ID, PCI_ANY_ID,
2397 PCI_ANY_ID, PCI_ANY_ID,
2398 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2399 0xffff00, pbn_default },
2400 { 0, }
2401};
2402
2403static struct pci_driver serial_pci_driver = {
2404 .name = "serial",
2405 .probe = pciserial_init_one,
2406 .remove = __devexit_p(pciserial_remove_one),
1d5e7996 2407#ifdef CONFIG_PM
1da177e4
LT		 2408 .suspend = pciserial_suspend_one,
2409 .resume = pciserial_resume_one,
1d5e7996 2410#endif
1da177e4
LT		 2411 .id_table = serial_pci_tbl,
2412};
2413
2414static int __init serial8250_pci_init(void)
2415{
2416 return pci_register_driver(&serial_pci_driver);
2417}
2418
2419static void __exit serial8250_pci_exit(void)
2420{
2421 pci_unregister_driver(&serial_pci_driver);
2422}
2423
2424module_init(serial8250_pci_init);
2425module_exit(serial8250_pci_exit);
2426
2427MODULE_LICENSE("GPL");
2428MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2429MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Clone of davem's net-next-2.6 tree