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[SERIAL] Remove unconditional enable of TX irq for console
[net-next-2.6.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22#include <linux/config.h>
23
24#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/ioport.h>
31#include <linux/init.h>
32#include <linux/console.h>
33#include <linux/sysrq.h>
1da177e4 34#include <linux/delay.h>
d052d1be 35#include <linux/platform_device.h>
1da177e4
LT		 36#include <linux/tty.h>
37#include <linux/tty_flip.h>
38#include <linux/serial_reg.h>
39#include <linux/serial_core.h>
40#include <linux/serial.h>
41#include <linux/serial_8250.h>
78512ece 42#include <linux/nmi.h>
f392ecfa 43#include <linux/mutex.h>
1da177e4
LT		 44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50/*
51 * Configuration:
52 * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
54 */
408b664a 55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 56
a61c2d78
DJ		 57static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
1da177e4
LT		 59/*
60 * Debugging.
61 */
62#if 0
63#define DEBUG_AUTOCONF(fmt...) printk(fmt)
64#else
65#define DEBUG_AUTOCONF(fmt...) do { } while (0)
66#endif
67
68#if 0
69#define DEBUG_INTR(fmt...) printk(fmt)
70#else
71#define DEBUG_INTR(fmt...) do { } while (0)
72#endif
73
74#define PASS_LIMIT 256
75
76/*
77 * We default to IRQ0 for the "no irq" hack. Some
78 * machine types want others as well - they're free
79 * to redefine this in their header file.
80 */
81#define is_real_interrupt(irq) ((irq) != 0)
82
1da177e4
LT		 83#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
84#define CONFIG_SERIAL_DETECT_IRQ 1
85#endif
1da177e4
LT		 86#ifdef CONFIG_SERIAL_8250_MANY_PORTS
87#define CONFIG_SERIAL_MANY_PORTS 1
88#endif
89
90/*
91 * HUB6 is always on. This will be removed once the header
92 * files have been cleaned.
93 */
94#define CONFIG_HUB6 1
95
96#include <asm/serial.h>
97
98/*
99 * SERIAL_PORT_DFNS tells us about built-in ports that have no
100 * standard enumeration mechanism. Platforms that can find all
101 * serial ports via mechanisms like ACPI or PCI need not supply it.
102 */
103#ifndef SERIAL_PORT_DFNS
104#define SERIAL_PORT_DFNS
105#endif
106
cb3592be 107static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 108 SERIAL_PORT_DFNS /* defined in asm/serial.h */
109};
110
026d02a2 111#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 112
113#ifdef CONFIG_SERIAL_8250_RSA
114
115#define PORT_RSA_MAX 4
116static unsigned long probe_rsa[PORT_RSA_MAX];
117static unsigned int probe_rsa_count;
118#endif /* CONFIG_SERIAL_8250_RSA */
119
120struct uart_8250_port {
121 struct uart_port port;
122 struct timer_list timer; /* "no irq" timer */
123 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 124 unsigned short capabilities; /* port capabilities */
125 unsigned short bugs; /* port bugs */
1da177e4 126 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 127 unsigned char acr;
128 unsigned char ier;
129 unsigned char lcr;
130 unsigned char mcr;
131 unsigned char mcr_mask; /* mask of user bits */
132 unsigned char mcr_force; /* mask of forced bits */
133 unsigned char lsr_break_flag;
134
135 /*
136 * We provide a per-port pm hook.
137 */
138 void (*pm)(struct uart_port *port,
139 unsigned int state, unsigned int old);
140};
141
142struct irq_info {
143 spinlock_t lock;
144 struct list_head *head;
145};
146
147static struct irq_info irq_lists[NR_IRQS];
148
149/*
150 * Here we define the default xmit fifo size used for each type of UART.
151 */
152static const struct serial8250_config uart_config[] = {
153 [PORT_UNKNOWN] = {
154 .name = "unknown",
155 .fifo_size = 1,
156 .tx_loadsz = 1,
157 },
158 [PORT_8250] = {
159 .name = "8250",
160 .fifo_size = 1,
161 .tx_loadsz = 1,
162 },
163 [PORT_16450] = {
164 .name = "16450",
165 .fifo_size = 1,
166 .tx_loadsz = 1,
167 },
168 [PORT_16550] = {
169 .name = "16550",
170 .fifo_size = 1,
171 .tx_loadsz = 1,
172 },
173 [PORT_16550A] = {
174 .name = "16550A",
175 .fifo_size = 16,
176 .tx_loadsz = 16,
177 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
178 .flags = UART_CAP_FIFO,
179 },
180 [PORT_CIRRUS] = {
181 .name = "Cirrus",
182 .fifo_size = 1,
183 .tx_loadsz = 1,
184 },
185 [PORT_16650] = {
186 .name = "ST16650",
187 .fifo_size = 1,
188 .tx_loadsz = 1,
189 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
190 },
191 [PORT_16650V2] = {
192 .name = "ST16650V2",
193 .fifo_size = 32,
194 .tx_loadsz = 16,
195 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
196 UART_FCR_T_TRIG_00,
197 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
198 },
199 [PORT_16750] = {
200 .name = "TI16750",
201 .fifo_size = 64,
202 .tx_loadsz = 64,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
204 UART_FCR7_64BYTE,
205 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
206 },
207 [PORT_STARTECH] = {
208 .name = "Startech",
209 .fifo_size = 1,
210 .tx_loadsz = 1,
211 },
212 [PORT_16C950] = {
213 .name = "16C950/954",
214 .fifo_size = 128,
215 .tx_loadsz = 128,
216 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
217 .flags = UART_CAP_FIFO,
218 },
219 [PORT_16654] = {
220 .name = "ST16654",
221 .fifo_size = 64,
222 .tx_loadsz = 32,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
224 UART_FCR_T_TRIG_10,
225 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
226 },
227 [PORT_16850] = {
228 .name = "XR16850",
229 .fifo_size = 128,
230 .tx_loadsz = 128,
231 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
232 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
233 },
234 [PORT_RSA] = {
235 .name = "RSA",
236 .fifo_size = 2048,
237 .tx_loadsz = 2048,
238 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
239 .flags = UART_CAP_FIFO,
240 },
241 [PORT_NS16550A] = {
242 .name = "NS16550A",
243 .fifo_size = 16,
244 .tx_loadsz = 16,
245 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_NATSEMI,
247 },
248 [PORT_XSCALE] = {
249 .name = "XScale",
250 .fifo_size = 32,
251 .tx_loadsz = 32,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_UUE,
254 },
255};
256
21c614a7
PA		 257#ifdef CONFIG_SERIAL_8250_AU1X00
258
259/* Au1x00 UART hardware has a weird register layout */
260static const u8 au_io_in_map[] = {
261 [UART_RX] = 0,
262 [UART_IER] = 2,
263 [UART_IIR] = 3,
264 [UART_LCR] = 5,
265 [UART_MCR] = 6,
266 [UART_LSR] = 7,
267 [UART_MSR] = 8,
268};
269
270static const u8 au_io_out_map[] = {
271 [UART_TX] = 1,
272 [UART_IER] = 2,
273 [UART_FCR] = 4,
274 [UART_LCR] = 5,
275 [UART_MCR] = 6,
276};
277
278/* sane hardware needs no mapping */
279static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
280{
281 if (up->port.iotype != UPIO_AU)
282 return offset;
283 return au_io_in_map[offset];
284}
285
286static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
287{
288 if (up->port.iotype != UPIO_AU)
289 return offset;
290 return au_io_out_map[offset];
291}
292
293#else
294
295/* sane hardware needs no mapping */
296#define map_8250_in_reg(up, offset) (offset)
297#define map_8250_out_reg(up, offset) (offset)
298
299#endif
300
ea8874dc 301static unsigned int serial_in(struct uart_8250_port *up, int offset)
1da177e4 302{
21c614a7 303 offset = map_8250_in_reg(up, offset) << up->port.regshift;
1da177e4
LT		 304
305 switch (up->port.iotype) {
306 case UPIO_HUB6:
307 outb(up->port.hub6 - 1 + offset, up->port.iobase);
308 return inb(up->port.iobase + 1);
309
310 case UPIO_MEM:
311 return readb(up->port.membase + offset);
312
313 case UPIO_MEM32:
314 return readl(up->port.membase + offset);
315
21c614a7
PA		 316#ifdef CONFIG_SERIAL_8250_AU1X00
317 case UPIO_AU:
318 return __raw_readl(up->port.membase + offset);
319#endif
320
1da177e4
LT		 321 default:
322 return inb(up->port.iobase + offset);
323 }
324}
325
ea8874dc 326static void
1da177e4
LT		 327serial_out(struct uart_8250_port *up, int offset, int value)
328{
21c614a7 329 offset = map_8250_out_reg(up, offset) << up->port.regshift;
1da177e4
LT		 330
331 switch (up->port.iotype) {
332 case UPIO_HUB6:
333 outb(up->port.hub6 - 1 + offset, up->port.iobase);
334 outb(value, up->port.iobase + 1);
335 break;
336
337 case UPIO_MEM:
338 writeb(value, up->port.membase + offset);
339 break;
340
341 case UPIO_MEM32:
342 writel(value, up->port.membase + offset);
343 break;
344
21c614a7
PA		 345#ifdef CONFIG_SERIAL_8250_AU1X00
346 case UPIO_AU:
347 __raw_writel(value, up->port.membase + offset);
348 break;
349#endif
350
1da177e4
LT		 351 default:
352 outb(value, up->port.iobase + offset);
353 }
354}
355
356/*
357 * We used to support using pause I/O for certain machines. We
358 * haven't supported this for a while, but just in case it's badly
359 * needed for certain old 386 machines, I've left these #define's
360 * in....
361 */
362#define serial_inp(up, offset) serial_in(up, offset)
363#define serial_outp(up, offset, value) serial_out(up, offset, value)
364
b32b19b8
JAH		 365/* Uart divisor latch read */
366static inline int _serial_dl_read(struct uart_8250_port *up)
367{
368 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
369}
370
371/* Uart divisor latch write */
372static inline void _serial_dl_write(struct uart_8250_port *up, int value)
373{
374 serial_outp(up, UART_DLL, value & 0xff);
375 serial_outp(up, UART_DLM, value >> 8 & 0xff);
376}
377
378#ifdef CONFIG_SERIAL_8250_AU1X00
379/* Au1x00 haven't got a standard divisor latch */
380static int serial_dl_read(struct uart_8250_port *up)
381{
382 if (up->port.iotype == UPIO_AU)
383 return __raw_readl(up->port.membase + 0x28);
384 else
385 return _serial_dl_read(up);
386}
387
388static void serial_dl_write(struct uart_8250_port *up, int value)
389{
390 if (up->port.iotype == UPIO_AU)
391 __raw_writel(value, up->port.membase + 0x28);
392 else
393 _serial_dl_write(up, value);
394}
395#else
396#define serial_dl_read(up) _serial_dl_read(up)
397#define serial_dl_write(up, value) _serial_dl_write(up, value)
398#endif
1da177e4
LT		 399
400/*
401 * For the 16C950
402 */
403static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
404{
405 serial_out(up, UART_SCR, offset);
406 serial_out(up, UART_ICR, value);
407}
408
409static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
410{
411 unsigned int value;
412
413 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
414 serial_out(up, UART_SCR, offset);
415 value = serial_in(up, UART_ICR);
416 serial_icr_write(up, UART_ACR, up->acr);
417
418 return value;
419}
420
421/*
422 * FIFO support.
423 */
424static inline void serial8250_clear_fifos(struct uart_8250_port *p)
425{
426 if (p->capabilities & UART_CAP_FIFO) {
427 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
428 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
429 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
430 serial_outp(p, UART_FCR, 0);
431 }
432}
433
434/*
435 * IER sleep support. UARTs which have EFRs need the "extended
436 * capability" bit enabled. Note that on XR16C850s, we need to
437 * reset LCR to write to IER.
438 */
439static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
440{
441 if (p->capabilities & UART_CAP_SLEEP) {
442 if (p->capabilities & UART_CAP_EFR) {
443 serial_outp(p, UART_LCR, 0xBF);
444 serial_outp(p, UART_EFR, UART_EFR_ECB);
445 serial_outp(p, UART_LCR, 0);
446 }
447 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
448 if (p->capabilities & UART_CAP_EFR) {
449 serial_outp(p, UART_LCR, 0xBF);
450 serial_outp(p, UART_EFR, 0);
451 serial_outp(p, UART_LCR, 0);
452 }
453 }
454}
455
456#ifdef CONFIG_SERIAL_8250_RSA
457/*
458 * Attempts to turn on the RSA FIFO. Returns zero on failure.
459 * We set the port uart clock rate if we succeed.
460 */
461static int __enable_rsa(struct uart_8250_port *up)
462{
463 unsigned char mode;
464 int result;
465
466 mode = serial_inp(up, UART_RSA_MSR);
467 result = mode & UART_RSA_MSR_FIFO;
468
469 if (!result) {
470 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
471 mode = serial_inp(up, UART_RSA_MSR);
472 result = mode & UART_RSA_MSR_FIFO;
473 }
474
475 if (result)
476 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
477
478 return result;
479}
480
481static void enable_rsa(struct uart_8250_port *up)
482{
483 if (up->port.type == PORT_RSA) {
484 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
485 spin_lock_irq(&up->port.lock);
486 __enable_rsa(up);
487 spin_unlock_irq(&up->port.lock);
488 }
489 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
490 serial_outp(up, UART_RSA_FRR, 0);
491 }
492}
493
494/*
495 * Attempts to turn off the RSA FIFO. Returns zero on failure.
496 * It is unknown why interrupts were disabled in here. However,
497 * the caller is expected to preserve this behaviour by grabbing
498 * the spinlock before calling this function.
499 */
500static void disable_rsa(struct uart_8250_port *up)
501{
502 unsigned char mode;
503 int result;
504
505 if (up->port.type == PORT_RSA &&
506 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
507 spin_lock_irq(&up->port.lock);
508
509 mode = serial_inp(up, UART_RSA_MSR);
510 result = !(mode & UART_RSA_MSR_FIFO);
511
512 if (!result) {
513 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
514 mode = serial_inp(up, UART_RSA_MSR);
515 result = !(mode & UART_RSA_MSR_FIFO);
516 }
517
518 if (result)
519 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
520 spin_unlock_irq(&up->port.lock);
521 }
522}
523#endif /* CONFIG_SERIAL_8250_RSA */
524
525/*
526 * This is a quickie test to see how big the FIFO is.
527 * It doesn't work at all the time, more's the pity.
528 */
529static int size_fifo(struct uart_8250_port *up)
530{
b32b19b8
JAH		 531 unsigned char old_fcr, old_mcr, old_lcr;
532 unsigned short old_dl;
1da177e4
LT		 533 int count;
534
535 old_lcr = serial_inp(up, UART_LCR);
536 serial_outp(up, UART_LCR, 0);
537 old_fcr = serial_inp(up, UART_FCR);
538 old_mcr = serial_inp(up, UART_MCR);
539 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
540 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
541 serial_outp(up, UART_MCR, UART_MCR_LOOP);
542 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8
JAH		 543 old_dl = serial_dl_read(up);
544 serial_dl_write(up, 0x0001);
1da177e4
LT		 545 serial_outp(up, UART_LCR, 0x03);
546 for (count = 0; count < 256; count++)
547 serial_outp(up, UART_TX, count);
548 mdelay(20);/* FIXME - schedule_timeout */
549 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
550 (count < 256); count++)
551 serial_inp(up, UART_RX);
552 serial_outp(up, UART_FCR, old_fcr);
553 serial_outp(up, UART_MCR, old_mcr);
554 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8 555 serial_dl_write(up, old_dl);
1da177e4
LT		 556 serial_outp(up, UART_LCR, old_lcr);
557
558 return count;
559}
560
561/*
562 * Read UART ID using the divisor method - set DLL and DLM to zero
563 * and the revision will be in DLL and device type in DLM. We
564 * preserve the device state across this.
565 */
566static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
567{
568 unsigned char old_dll, old_dlm, old_lcr;
569 unsigned int id;
570
571 old_lcr = serial_inp(p, UART_LCR);
572 serial_outp(p, UART_LCR, UART_LCR_DLAB);
573
574 old_dll = serial_inp(p, UART_DLL);
575 old_dlm = serial_inp(p, UART_DLM);
576
577 serial_outp(p, UART_DLL, 0);
578 serial_outp(p, UART_DLM, 0);
579
580 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
581
582 serial_outp(p, UART_DLL, old_dll);
583 serial_outp(p, UART_DLM, old_dlm);
584 serial_outp(p, UART_LCR, old_lcr);
585
586 return id;
587}
588
589/*
590 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
591 * When this function is called we know it is at least a StarTech
592 * 16650 V2, but it might be one of several StarTech UARTs, or one of
593 * its clones. (We treat the broken original StarTech 16650 V1 as a
594 * 16550, and why not? Startech doesn't seem to even acknowledge its
595 * existence.)
596 *
597 * What evil have men's minds wrought...
598 */
599static void autoconfig_has_efr(struct uart_8250_port *up)
600{
601 unsigned int id1, id2, id3, rev;
602
603 /*
604 * Everything with an EFR has SLEEP
605 */
606 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
607
608 /*
609 * First we check to see if it's an Oxford Semiconductor UART.
610 *
611 * If we have to do this here because some non-National
612 * Semiconductor clone chips lock up if you try writing to the
613 * LSR register (which serial_icr_read does)
614 */
615
616 /*
617 * Check for Oxford Semiconductor 16C950.
618 *
619 * EFR [4] must be set else this test fails.
620 *
621 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
622 * claims that it's needed for 952 dual UART's (which are not
623 * recommended for new designs).
624 */
625 up->acr = 0;
626 serial_out(up, UART_LCR, 0xBF);
627 serial_out(up, UART_EFR, UART_EFR_ECB);
628 serial_out(up, UART_LCR, 0x00);
629 id1 = serial_icr_read(up, UART_ID1);
630 id2 = serial_icr_read(up, UART_ID2);
631 id3 = serial_icr_read(up, UART_ID3);
632 rev = serial_icr_read(up, UART_REV);
633
634 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
635
636 if (id1 == 0x16 && id2 == 0xC9 &&
637 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
638 up->port.type = PORT_16C950;
4ba5e35d
RK		 639
640 /*
641 * Enable work around for the Oxford Semiconductor 952 rev B
642 * chip which causes it to seriously miscalculate baud rates
643 * when DLL is 0.
644 */
645 if (id3 == 0x52 && rev == 0x01)
646 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 647 return;
648 }
649
650 /*
651 * We check for a XR16C850 by setting DLL and DLM to 0, and then
652 * reading back DLL and DLM. The chip type depends on the DLM
653 * value read back:
654 * 0x10 - XR16C850 and the DLL contains the chip revision.
655 * 0x12 - XR16C2850.
656 * 0x14 - XR16C854.
657 */
658 id1 = autoconfig_read_divisor_id(up);
659 DEBUG_AUTOCONF("850id=%04x ", id1);
660
661 id2 = id1 >> 8;
662 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 663 up->port.type = PORT_16850;
664 return;
665 }
666
667 /*
668 * It wasn't an XR16C850.
669 *
670 * We distinguish between the '654 and the '650 by counting
671 * how many bytes are in the FIFO. I'm using this for now,
672 * since that's the technique that was sent to me in the
673 * serial driver update, but I'm not convinced this works.
674 * I've had problems doing this in the past. -TYT
675 */
676 if (size_fifo(up) == 64)
677 up->port.type = PORT_16654;
678 else
679 up->port.type = PORT_16650V2;
680}
681
682/*
683 * We detected a chip without a FIFO. Only two fall into
684 * this category - the original 8250 and the 16450. The
685 * 16450 has a scratch register (accessible with LCR=0)
686 */
687static void autoconfig_8250(struct uart_8250_port *up)
688{
689 unsigned char scratch, status1, status2;
690
691 up->port.type = PORT_8250;
692
693 scratch = serial_in(up, UART_SCR);
694 serial_outp(up, UART_SCR, 0xa5);
695 status1 = serial_in(up, UART_SCR);
696 serial_outp(up, UART_SCR, 0x5a);
697 status2 = serial_in(up, UART_SCR);
698 serial_outp(up, UART_SCR, scratch);
699
700 if (status1 == 0xa5 && status2 == 0x5a)
701 up->port.type = PORT_16450;
702}
703
704static int broken_efr(struct uart_8250_port *up)
705{
706 /*
707 * Exar ST16C2550 "A2" devices incorrectly detect as
708 * having an EFR, and report an ID of 0x0201. See
709 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
710 */
711 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
712 return 1;
713
714 return 0;
715}
716
717/*
718 * We know that the chip has FIFOs. Does it have an EFR? The
719 * EFR is located in the same register position as the IIR and
720 * we know the top two bits of the IIR are currently set. The
721 * EFR should contain zero. Try to read the EFR.
722 */
723static void autoconfig_16550a(struct uart_8250_port *up)
724{
725 unsigned char status1, status2;
726 unsigned int iersave;
727
728 up->port.type = PORT_16550A;
729 up->capabilities |= UART_CAP_FIFO;
730
731 /*
732 * Check for presence of the EFR when DLAB is set.
733 * Only ST16C650V1 UARTs pass this test.
734 */
735 serial_outp(up, UART_LCR, UART_LCR_DLAB);
736 if (serial_in(up, UART_EFR) == 0) {
737 serial_outp(up, UART_EFR, 0xA8);
738 if (serial_in(up, UART_EFR) != 0) {
739 DEBUG_AUTOCONF("EFRv1 ");
740 up->port.type = PORT_16650;
741 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
742 } else {
743 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
744 }
745 serial_outp(up, UART_EFR, 0);
746 return;
747 }
748
749 /*
750 * Maybe it requires 0xbf to be written to the LCR.
751 * (other ST16C650V2 UARTs, TI16C752A, etc)
752 */
753 serial_outp(up, UART_LCR, 0xBF);
754 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
755 DEBUG_AUTOCONF("EFRv2 ");
756 autoconfig_has_efr(up);
757 return;
758 }
759
760 /*
761 * Check for a National Semiconductor SuperIO chip.
762 * Attempt to switch to bank 2, read the value of the LOOP bit
763 * from EXCR1. Switch back to bank 0, change it in MCR. Then
764 * switch back to bank 2, read it from EXCR1 again and check
765 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 766 */
767 serial_outp(up, UART_LCR, 0);
768 status1 = serial_in(up, UART_MCR);
769 serial_outp(up, UART_LCR, 0xE0);
770 status2 = serial_in(up, 0x02); /* EXCR1 */
771
772 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
773 serial_outp(up, UART_LCR, 0);
774 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
775 serial_outp(up, UART_LCR, 0xE0);
776 status2 = serial_in(up, 0x02); /* EXCR1 */
777 serial_outp(up, UART_LCR, 0);
778 serial_outp(up, UART_MCR, status1);
779
780 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 781 unsigned short quot;
782
1da177e4 783 serial_outp(up, UART_LCR, 0xE0);
857dde2e 784
b32b19b8 785 quot = serial_dl_read(up);
857dde2e
DW		 786 quot <<= 3;
787
1da177e4
LT		 788 status1 = serial_in(up, 0x04); /* EXCR1 */
789 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
790 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
791 serial_outp(up, 0x04, status1);
857dde2e 792
b32b19b8 793 serial_dl_write(up, quot);
857dde2e 794
1da177e4 795 serial_outp(up, UART_LCR, 0);
1da177e4 796
857dde2e 797 up->port.uartclk = 921600*16;
1da177e4
LT		 798 up->port.type = PORT_NS16550A;
799 up->capabilities |= UART_NATSEMI;
800 return;
801 }
802 }
803
804 /*
805 * No EFR. Try to detect a TI16750, which only sets bit 5 of
806 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
807 * Try setting it with and without DLAB set. Cheap clones
808 * set bit 5 without DLAB set.
809 */
810 serial_outp(up, UART_LCR, 0);
811 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
812 status1 = serial_in(up, UART_IIR) >> 5;
813 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
814 serial_outp(up, UART_LCR, UART_LCR_DLAB);
815 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
816 status2 = serial_in(up, UART_IIR) >> 5;
817 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
818 serial_outp(up, UART_LCR, 0);
819
820 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
821
822 if (status1 == 6 && status2 == 7) {
823 up->port.type = PORT_16750;
824 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
825 return;
826 }
827
828 /*
829 * Try writing and reading the UART_IER_UUE bit (b6).
830 * If it works, this is probably one of the Xscale platform's
831 * internal UARTs.
832 * We're going to explicitly set the UUE bit to 0 before
833 * trying to write and read a 1 just to make sure it's not
834 * already a 1 and maybe locked there before we even start start.
835 */
836 iersave = serial_in(up, UART_IER);
837 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
838 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
839 /*
840 * OK it's in a known zero state, try writing and reading
841 * without disturbing the current state of the other bits.
842 */
843 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
844 if (serial_in(up, UART_IER) & UART_IER_UUE) {
845 /*
846 * It's an Xscale.
847 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
848 */
849 DEBUG_AUTOCONF("Xscale ");
850 up->port.type = PORT_XSCALE;
851 up->capabilities |= UART_CAP_UUE;
852 return;
853 }
854 } else {
855 /*
856 * If we got here we couldn't force the IER_UUE bit to 0.
857 * Log it and continue.
858 */
859 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
860 }
861 serial_outp(up, UART_IER, iersave);
862}
863
864/*
865 * This routine is called by rs_init() to initialize a specific serial
866 * port. It determines what type of UART chip this serial port is
867 * using: 8250, 16450, 16550, 16550A. The important question is
868 * whether or not this UART is a 16550A or not, since this will
869 * determine whether or not we can use its FIFO features or not.
870 */
871static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
872{
873 unsigned char status1, scratch, scratch2, scratch3;
874 unsigned char save_lcr, save_mcr;
875 unsigned long flags;
876
877 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
878 return;
879
880 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
881 up->port.line, up->port.iobase, up->port.membase);
882
883 /*
884 * We really do need global IRQs disabled here - we're going to
885 * be frobbing the chips IRQ enable register to see if it exists.
886 */
887 spin_lock_irqsave(&up->port.lock, flags);
888// save_flags(flags); cli();
889
890 up->capabilities = 0;
4ba5e35d 891 up->bugs = 0;
1da177e4
LT		 892
893 if (!(up->port.flags & UPF_BUGGY_UART)) {
894 /*
895 * Do a simple existence test first; if we fail this,
896 * there's no point trying anything else.
897 *
898 * 0x80 is used as a nonsense port to prevent against
899 * false positives due to ISA bus float. The
900 * assumption is that 0x80 is a non-existent port;
901 * which should be safe since include/asm/io.h also
902 * makes this assumption.
903 *
904 * Note: this is safe as long as MCR bit 4 is clear
905 * and the device is in "PC" mode.
906 */
907 scratch = serial_inp(up, UART_IER);
908 serial_outp(up, UART_IER, 0);
909#ifdef __i386__
910 outb(0xff, 0x080);
911#endif
912 scratch2 = serial_inp(up, UART_IER);
913 serial_outp(up, UART_IER, 0x0F);
914#ifdef __i386__
915 outb(0, 0x080);
916#endif
917 scratch3 = serial_inp(up, UART_IER);
918 serial_outp(up, UART_IER, scratch);
919 if (scratch2 != 0 || scratch3 != 0x0F) {
920 /*
921 * We failed; there's nothing here
922 */
923 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
924 scratch2, scratch3);
925 goto out;
926 }
927 }
928
929 save_mcr = serial_in(up, UART_MCR);
930 save_lcr = serial_in(up, UART_LCR);
931
932 /*
933 * Check to see if a UART is really there. Certain broken
934 * internal modems based on the Rockwell chipset fail this
935 * test, because they apparently don't implement the loopback
936 * test mode. So this test is skipped on the COM 1 through
937 * COM 4 ports. This *should* be safe, since no board
938 * manufacturer would be stupid enough to design a board
939 * that conflicts with COM 1-4 --- we hope!
940 */
941 if (!(up->port.flags & UPF_SKIP_TEST)) {
942 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
943 status1 = serial_inp(up, UART_MSR) & 0xF0;
944 serial_outp(up, UART_MCR, save_mcr);
945 if (status1 != 0x90) {
946 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
947 status1);
948 goto out;
949 }
950 }
951
952 /*
953 * We're pretty sure there's a port here. Lets find out what
954 * type of port it is. The IIR top two bits allows us to find
6f0d618f 955 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 956 * determines what we test for next.
957 *
958 * We also initialise the EFR (if any) to zero for later. The
959 * EFR occupies the same register location as the FCR and IIR.
960 */
961 serial_outp(up, UART_LCR, 0xBF);
962 serial_outp(up, UART_EFR, 0);
963 serial_outp(up, UART_LCR, 0);
964
965 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
966 scratch = serial_in(up, UART_IIR) >> 6;
967
968 DEBUG_AUTOCONF("iir=%d ", scratch);
969
970 switch (scratch) {
971 case 0:
972 autoconfig_8250(up);
973 break;
974 case 1:
975 up->port.type = PORT_UNKNOWN;
976 break;
977 case 2:
978 up->port.type = PORT_16550;
979 break;
980 case 3:
981 autoconfig_16550a(up);
982 break;
983 }
984
985#ifdef CONFIG_SERIAL_8250_RSA
986 /*
987 * Only probe for RSA ports if we got the region.
988 */
989 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
990 int i;
991
992 for (i = 0 ; i < probe_rsa_count; ++i) {
993 if (probe_rsa[i] == up->port.iobase &&
994 __enable_rsa(up)) {
995 up->port.type = PORT_RSA;
996 break;
997 }
998 }
999 }
1000#endif
21c614a7
PA		 1001
1002#ifdef CONFIG_SERIAL_8250_AU1X00
1003 /* if access method is AU, it is a 16550 with a quirk */
1004 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1005 up->bugs |= UART_BUG_NOMSR;
1006#endif
1007
1da177e4
LT		 1008 serial_outp(up, UART_LCR, save_lcr);
1009
1010 if (up->capabilities != uart_config[up->port.type].flags) {
1011 printk(KERN_WARNING
1012 "ttyS%d: detected caps %08x should be %08x\n",
1013 up->port.line, up->capabilities,
1014 uart_config[up->port.type].flags);
1015 }
1016
1017 up->port.fifosize = uart_config[up->port.type].fifo_size;
1018 up->capabilities = uart_config[up->port.type].flags;
1019 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1020
1021 if (up->port.type == PORT_UNKNOWN)
1022 goto out;
1023
1024 /*
1025 * Reset the UART.
1026 */
1027#ifdef CONFIG_SERIAL_8250_RSA
1028 if (up->port.type == PORT_RSA)
1029 serial_outp(up, UART_RSA_FRR, 0);
1030#endif
1031 serial_outp(up, UART_MCR, save_mcr);
1032 serial8250_clear_fifos(up);
1033 (void)serial_in(up, UART_RX);
5c8c755c
LB		 1034 if (up->capabilities & UART_CAP_UUE)
1035 serial_outp(up, UART_IER, UART_IER_UUE);
1036 else
1037 serial_outp(up, UART_IER, 0);
1da177e4
LT		 1038
1039 out:
1040 spin_unlock_irqrestore(&up->port.lock, flags);
1041// restore_flags(flags);
1042 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1043}
1044
1045static void autoconfig_irq(struct uart_8250_port *up)
1046{
1047 unsigned char save_mcr, save_ier;
1048 unsigned char save_ICP = 0;
1049 unsigned int ICP = 0;
1050 unsigned long irqs;
1051 int irq;
1052
1053 if (up->port.flags & UPF_FOURPORT) {
1054 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1055 save_ICP = inb_p(ICP);
1056 outb_p(0x80, ICP);
1057 (void) inb_p(ICP);
1058 }
1059
1060 /* forget possible initially masked and pending IRQ */
1061 probe_irq_off(probe_irq_on());
1062 save_mcr = serial_inp(up, UART_MCR);
1063 save_ier = serial_inp(up, UART_IER);
1064 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1065
1066 irqs = probe_irq_on();
1067 serial_outp(up, UART_MCR, 0);
1068 udelay (10);
1069 if (up->port.flags & UPF_FOURPORT) {
1070 serial_outp(up, UART_MCR,
1071 UART_MCR_DTR | UART_MCR_RTS);
1072 } else {
1073 serial_outp(up, UART_MCR,
1074 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1075 }
1076 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1077 (void)serial_inp(up, UART_LSR);
1078 (void)serial_inp(up, UART_RX);
1079 (void)serial_inp(up, UART_IIR);
1080 (void)serial_inp(up, UART_MSR);
1081 serial_outp(up, UART_TX, 0xFF);
1082 udelay (20);
1083 irq = probe_irq_off(irqs);
1084
1085 serial_outp(up, UART_MCR, save_mcr);
1086 serial_outp(up, UART_IER, save_ier);
1087
1088 if (up->port.flags & UPF_FOURPORT)
1089 outb_p(save_ICP, ICP);
1090
1091 up->port.irq = (irq > 0) ? irq : 0;
1092}
1093
e763b90c
RK		 1094static inline void __stop_tx(struct uart_8250_port *p)
1095{
1096 if (p->ier & UART_IER_THRI) {
1097 p->ier &= ~UART_IER_THRI;
1098 serial_out(p, UART_IER, p->ier);
1099 }
1100}
1101
b129a8cc 1102static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1103{
1104 struct uart_8250_port *up = (struct uart_8250_port *)port;
1105
e763b90c 1106 __stop_tx(up);
1da177e4
LT		 1107
1108 /*
e763b90c 1109 * We really want to stop the transmitter from sending.
1da177e4 1110 */
e763b90c 1111 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1112 up->acr |= UART_ACR_TXDIS;
1113 serial_icr_write(up, UART_ACR, up->acr);
1114 }
1115}
1116
55d3b282
RK		 1117static void transmit_chars(struct uart_8250_port *up);
1118
b129a8cc 1119static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1120{
1121 struct uart_8250_port *up = (struct uart_8250_port *)port;
1122
1123 if (!(up->ier & UART_IER_THRI)) {
1124 up->ier |= UART_IER_THRI;
1125 serial_out(up, UART_IER, up->ier);
55d3b282 1126
67f7654e 1127 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1128 unsigned char lsr, iir;
1129 lsr = serial_in(up, UART_LSR);
1130 iir = serial_in(up, UART_IIR);
1131 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1132 transmit_chars(up);
1133 }
1da177e4 1134 }
e763b90c 1135
1da177e4 1136 /*
e763b90c 1137 * Re-enable the transmitter if we disabled it.
1da177e4 1138 */
e763b90c 1139 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1140 up->acr &= ~UART_ACR_TXDIS;
1141 serial_icr_write(up, UART_ACR, up->acr);
1142 }
1143}
1144
1145static void serial8250_stop_rx(struct uart_port *port)
1146{
1147 struct uart_8250_port *up = (struct uart_8250_port *)port;
1148
1149 up->ier &= ~UART_IER_RLSI;
1150 up->port.read_status_mask &= ~UART_LSR_DR;
1151 serial_out(up, UART_IER, up->ier);
1152}
1153
1154static void serial8250_enable_ms(struct uart_port *port)
1155{
1156 struct uart_8250_port *up = (struct uart_8250_port *)port;
1157
21c614a7
PA		 1158 /* no MSR capabilities */
1159 if (up->bugs & UART_BUG_NOMSR)
1160 return;
1161
1da177e4
LT		 1162 up->ier |= UART_IER_MSI;
1163 serial_out(up, UART_IER, up->ier);
1164}
1165
ea8874dc 1166static void
1da177e4
LT		 1167receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1168{
1169 struct tty_struct *tty = up->port.info->tty;
1170 unsigned char ch, lsr = *status;
1171 int max_count = 256;
1172 char flag;
1173
1174 do {
1da177e4
LT		 1175 ch = serial_inp(up, UART_RX);
1176 flag = TTY_NORMAL;
1177 up->port.icount.rx++;
1178
1179#ifdef CONFIG_SERIAL_8250_CONSOLE
1180 /*
1181 * Recover the break flag from console xmit
1182 */
1183 if (up->port.line == up->port.cons->index) {
1184 lsr |= up->lsr_break_flag;
1185 up->lsr_break_flag = 0;
1186 }
1187#endif
1188
1189 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1190 UART_LSR_FE | UART_LSR_OE))) {
1191 /*
1192 * For statistics only
1193 */
1194 if (lsr & UART_LSR_BI) {
1195 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1196 up->port.icount.brk++;
1197 /*
1198 * We do the SysRQ and SAK checking
1199 * here because otherwise the break
1200 * may get masked by ignore_status_mask
1201 * or read_status_mask.
1202 */
1203 if (uart_handle_break(&up->port))
1204 goto ignore_char;
1205 } else if (lsr & UART_LSR_PE)
1206 up->port.icount.parity++;
1207 else if (lsr & UART_LSR_FE)
1208 up->port.icount.frame++;
1209 if (lsr & UART_LSR_OE)
1210 up->port.icount.overrun++;
1211
1212 /*
23907eb8 1213 * Mask off conditions which should be ignored.
1da177e4
LT		 1214 */
1215 lsr &= up->port.read_status_mask;
1216
1217 if (lsr & UART_LSR_BI) {
1218 DEBUG_INTR("handling break....");
1219 flag = TTY_BREAK;
1220 } else if (lsr & UART_LSR_PE)
1221 flag = TTY_PARITY;
1222 else if (lsr & UART_LSR_FE)
1223 flag = TTY_FRAME;
1224 }
1225 if (uart_handle_sysrq_char(&up->port, ch, regs))
1226 goto ignore_char;
05ab3014
RK		 1227
1228 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1229
1da177e4
LT		 1230 ignore_char:
1231 lsr = serial_inp(up, UART_LSR);
1232 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1233 spin_unlock(&up->port.lock);
1234 tty_flip_buffer_push(tty);
1235 spin_lock(&up->port.lock);
1236 *status = lsr;
1237}
1238
ea8874dc 1239static void transmit_chars(struct uart_8250_port *up)
1da177e4
LT		 1240{
1241 struct circ_buf *xmit = &up->port.info->xmit;
1242 int count;
1243
1244 if (up->port.x_char) {
1245 serial_outp(up, UART_TX, up->port.x_char);
1246 up->port.icount.tx++;
1247 up->port.x_char = 0;
1248 return;
1249 }
b129a8cc
RK		 1250 if (uart_tx_stopped(&up->port)) {
1251 serial8250_stop_tx(&up->port);
1252 return;
1253 }
1254 if (uart_circ_empty(xmit)) {
e763b90c 1255 __stop_tx(up);
1da177e4
LT		 1256 return;
1257 }
1258
1259 count = up->tx_loadsz;
1260 do {
1261 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1262 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1263 up->port.icount.tx++;
1264 if (uart_circ_empty(xmit))
1265 break;
1266 } while (--count > 0);
1267
1268 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1269 uart_write_wakeup(&up->port);
1270
1271 DEBUG_INTR("THRE...");
1272
1273 if (uart_circ_empty(xmit))
e763b90c 1274 __stop_tx(up);
1da177e4
LT		 1275}
1276
2af7cd68 1277static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1278{
2af7cd68
RK		 1279 unsigned int status = serial_in(up, UART_MSR);
1280
1281 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI) {
1282 if (status & UART_MSR_TERI)
1283 up->port.icount.rng++;
1284 if (status & UART_MSR_DDSR)
1285 up->port.icount.dsr++;
1286 if (status & UART_MSR_DDCD)
1287 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1288 if (status & UART_MSR_DCTS)
1289 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1290
1291 wake_up_interruptible(&up->port.info->delta_msr_wait);
1292 }
1da177e4 1293
2af7cd68 1294 return status;
1da177e4
LT		 1295}
1296
1297/*
1298 * This handles the interrupt from one port.
1299 */
1300static inline void
1301serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1302{
45e24601
RK		 1303 unsigned int status;
1304
1305 spin_lock(&up->port.lock);
1306
1307 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1308
1309 DEBUG_INTR("status = %x...", status);
1310
1311 if (status & UART_LSR_DR)
1312 receive_chars(up, &status, regs);
1313 check_modem_status(up);
1314 if (status & UART_LSR_THRE)
1315 transmit_chars(up);
45e24601
RK		 1316
1317 spin_unlock(&up->port.lock);
1da177e4
LT		 1318}
1319
1320/*
1321 * This is the serial driver's interrupt routine.
1322 *
1323 * Arjan thinks the old way was overly complex, so it got simplified.
1324 * Alan disagrees, saying that need the complexity to handle the weird
1325 * nature of ISA shared interrupts. (This is a special exception.)
1326 *
1327 * In order to handle ISA shared interrupts properly, we need to check
1328 * that all ports have been serviced, and therefore the ISA interrupt
1329 * line has been de-asserted.
1330 *
1331 * This means we need to loop through all ports. checking that they
1332 * don't have an interrupt pending.
1333 */
1334static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1335{
1336 struct irq_info *i = dev_id;
1337 struct list_head *l, *end = NULL;
1338 int pass_counter = 0, handled = 0;
1339
1340 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1341
1342 spin_lock(&i->lock);
1343
1344 l = i->head;
1345 do {
1346 struct uart_8250_port *up;
1347 unsigned int iir;
1348
1349 up = list_entry(l, struct uart_8250_port, list);
1350
1351 iir = serial_in(up, UART_IIR);
1352 if (!(iir & UART_IIR_NO_INT)) {
1da177e4 1353 serial8250_handle_port(up, regs);
1da177e4
LT		 1354
1355 handled = 1;
1356
1357 end = NULL;
1358 } else if (end == NULL)
1359 end = l;
1360
1361 l = l->next;
1362
1363 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1364 /* If we hit this, we're dead. */
1365 printk(KERN_ERR "serial8250: too much work for "
1366 "irq%d\n", irq);
1367 break;
1368 }
1369 } while (l != end);
1370
1371 spin_unlock(&i->lock);
1372
1373 DEBUG_INTR("end.\n");
1374
1375 return IRQ_RETVAL(handled);
1376}
1377
1378/*
1379 * To support ISA shared interrupts, we need to have one interrupt
1380 * handler that ensures that the IRQ line has been deasserted
1381 * before returning. Failing to do this will result in the IRQ
1382 * line being stuck active, and, since ISA irqs are edge triggered,
1383 * no more IRQs will be seen.
1384 */
1385static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1386{
1387 spin_lock_irq(&i->lock);
1388
1389 if (!list_empty(i->head)) {
1390 if (i->head == &up->list)
1391 i->head = i->head->next;
1392 list_del(&up->list);
1393 } else {
1394 BUG_ON(i->head != &up->list);
1395 i->head = NULL;
1396 }
1397
1398 spin_unlock_irq(&i->lock);
1399}
1400
1401static int serial_link_irq_chain(struct uart_8250_port *up)
1402{
1403 struct irq_info *i = irq_lists + up->port.irq;
1404 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
1405
1406 spin_lock_irq(&i->lock);
1407
1408 if (i->head) {
1409 list_add(&up->list, i->head);
1410 spin_unlock_irq(&i->lock);
1411
1412 ret = 0;
1413 } else {
1414 INIT_LIST_HEAD(&up->list);
1415 i->head = &up->list;
1416 spin_unlock_irq(&i->lock);
1417
1418 ret = request_irq(up->port.irq, serial8250_interrupt,
1419 irq_flags, "serial", i);
1420 if (ret < 0)
1421 serial_do_unlink(i, up);
1422 }
1423
1424 return ret;
1425}
1426
1427static void serial_unlink_irq_chain(struct uart_8250_port *up)
1428{
1429 struct irq_info *i = irq_lists + up->port.irq;
1430
1431 BUG_ON(i->head == NULL);
1432
1433 if (list_empty(i->head))
1434 free_irq(up->port.irq, i);
1435
1436 serial_do_unlink(i, up);
1437}
1438
1439/*
1440 * This function is used to handle ports that do not have an
1441 * interrupt. This doesn't work very well for 16450's, but gives
1442 * barely passable results for a 16550A. (Although at the expense
1443 * of much CPU overhead).
1444 */
1445static void serial8250_timeout(unsigned long data)
1446{
1447 struct uart_8250_port *up = (struct uart_8250_port *)data;
1448 unsigned int timeout;
1449 unsigned int iir;
1450
1451 iir = serial_in(up, UART_IIR);
45e24601 1452 if (!(iir & UART_IIR_NO_INT))
1da177e4 1453 serial8250_handle_port(up, NULL);
1da177e4
LT		 1454
1455 timeout = up->port.timeout;
1456 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1457 mod_timer(&up->timer, jiffies + timeout);
1458}
1459
1460static unsigned int serial8250_tx_empty(struct uart_port *port)
1461{
1462 struct uart_8250_port *up = (struct uart_8250_port *)port;
1463 unsigned long flags;
1464 unsigned int ret;
1465
1466 spin_lock_irqsave(&up->port.lock, flags);
1467 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1468 spin_unlock_irqrestore(&up->port.lock, flags);
1469
1470 return ret;
1471}
1472
1473static unsigned int serial8250_get_mctrl(struct uart_port *port)
1474{
1475 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1476 unsigned int status;
1da177e4
LT		 1477 unsigned int ret;
1478
2af7cd68 1479 status = check_modem_status(up);
1da177e4
LT		 1480
1481 ret = 0;
1482 if (status & UART_MSR_DCD)
1483 ret |= TIOCM_CAR;
1484 if (status & UART_MSR_RI)
1485 ret |= TIOCM_RNG;
1486 if (status & UART_MSR_DSR)
1487 ret |= TIOCM_DSR;
1488 if (status & UART_MSR_CTS)
1489 ret |= TIOCM_CTS;
1490 return ret;
1491}
1492
1493static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1494{
1495 struct uart_8250_port *up = (struct uart_8250_port *)port;
1496 unsigned char mcr = 0;
1497
1498 if (mctrl & TIOCM_RTS)
1499 mcr |= UART_MCR_RTS;
1500 if (mctrl & TIOCM_DTR)
1501 mcr |= UART_MCR_DTR;
1502 if (mctrl & TIOCM_OUT1)
1503 mcr |= UART_MCR_OUT1;
1504 if (mctrl & TIOCM_OUT2)
1505 mcr |= UART_MCR_OUT2;
1506 if (mctrl & TIOCM_LOOP)
1507 mcr |= UART_MCR_LOOP;
1508
1509 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1510
1511 serial_out(up, UART_MCR, mcr);
1512}
1513
1514static void serial8250_break_ctl(struct uart_port *port, int break_state)
1515{
1516 struct uart_8250_port *up = (struct uart_8250_port *)port;
1517 unsigned long flags;
1518
1519 spin_lock_irqsave(&up->port.lock, flags);
1520 if (break_state == -1)
1521 up->lcr |= UART_LCR_SBC;
1522 else
1523 up->lcr &= ~UART_LCR_SBC;
1524 serial_out(up, UART_LCR, up->lcr);
1525 spin_unlock_irqrestore(&up->port.lock, flags);
1526}
1527
1528static int serial8250_startup(struct uart_port *port)
1529{
1530 struct uart_8250_port *up = (struct uart_8250_port *)port;
1531 unsigned long flags;
55d3b282 1532 unsigned char lsr, iir;
1da177e4
LT		 1533 int retval;
1534
1535 up->capabilities = uart_config[up->port.type].flags;
1536 up->mcr = 0;
1537
1538 if (up->port.type == PORT_16C950) {
1539 /* Wake up and initialize UART */
1540 up->acr = 0;
1541 serial_outp(up, UART_LCR, 0xBF);
1542 serial_outp(up, UART_EFR, UART_EFR_ECB);
1543 serial_outp(up, UART_IER, 0);
1544 serial_outp(up, UART_LCR, 0);
1545 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1546 serial_outp(up, UART_LCR, 0xBF);
1547 serial_outp(up, UART_EFR, UART_EFR_ECB);
1548 serial_outp(up, UART_LCR, 0);
1549 }
1550
1551#ifdef CONFIG_SERIAL_8250_RSA
1552 /*
1553 * If this is an RSA port, see if we can kick it up to the
1554 * higher speed clock.
1555 */
1556 enable_rsa(up);
1557#endif
1558
1559 /*
1560 * Clear the FIFO buffers and disable them.
7f927fcc 1561 * (they will be reenabled in set_termios())
1da177e4
LT		 1562 */
1563 serial8250_clear_fifos(up);
1564
1565 /*
1566 * Clear the interrupt registers.
1567 */
1568 (void) serial_inp(up, UART_LSR);
1569 (void) serial_inp(up, UART_RX);
1570 (void) serial_inp(up, UART_IIR);
1571 (void) serial_inp(up, UART_MSR);
1572
1573 /*
1574 * At this point, there's no way the LSR could still be 0xff;
1575 * if it is, then bail out, because there's likely no UART
1576 * here.
1577 */
1578 if (!(up->port.flags & UPF_BUGGY_UART) &&
1579 (serial_inp(up, UART_LSR) == 0xff)) {
1580 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1581 return -ENODEV;
1582 }
1583
1584 /*
1585 * For a XR16C850, we need to set the trigger levels
1586 */
1587 if (up->port.type == PORT_16850) {
1588 unsigned char fctr;
1589
1590 serial_outp(up, UART_LCR, 0xbf);
1591
1592 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1593 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1594 serial_outp(up, UART_TRG, UART_TRG_96);
1595 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1596 serial_outp(up, UART_TRG, UART_TRG_96);
1597
1598 serial_outp(up, UART_LCR, 0);
1599 }
1600
1601 /*
1602 * If the "interrupt" for this port doesn't correspond with any
1603 * hardware interrupt, we use a timer-based system. The original
1604 * driver used to do this with IRQ0.
1605 */
1606 if (!is_real_interrupt(up->port.irq)) {
1607 unsigned int timeout = up->port.timeout;
1608
1609 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1610
1611 up->timer.data = (unsigned long)up;
1612 mod_timer(&up->timer, jiffies + timeout);
1613 } else {
1614 retval = serial_link_irq_chain(up);
1615 if (retval)
1616 return retval;
1617 }
1618
1619 /*
1620 * Now, initialize the UART
1621 */
1622 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1623
1624 spin_lock_irqsave(&up->port.lock, flags);
1625 if (up->port.flags & UPF_FOURPORT) {
1626 if (!is_real_interrupt(up->port.irq))
1627 up->port.mctrl |= TIOCM_OUT1;
1628 } else
1629 /*
1630 * Most PC uarts need OUT2 raised to enable interrupts.
1631 */
1632 if (is_real_interrupt(up->port.irq))
1633 up->port.mctrl |= TIOCM_OUT2;
1634
1635 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1636
1637 /*
1638 * Do a quick test to see if we receive an
1639 * interrupt when we enable the TX irq.
1640 */
1641 serial_outp(up, UART_IER, UART_IER_THRI);
1642 lsr = serial_in(up, UART_LSR);
1643 iir = serial_in(up, UART_IIR);
1644 serial_outp(up, UART_IER, 0);
1645
1646 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1647 if (!(up->bugs & UART_BUG_TXEN)) {
1648 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1649 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1650 port->line);
1651 }
1652 } else {
67f7654e 1653 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1654 }
1655
1da177e4
LT		 1656 spin_unlock_irqrestore(&up->port.lock, flags);
1657
1658 /*
1659 * Finally, enable interrupts. Note: Modem status interrupts
1660 * are set via set_termios(), which will be occurring imminently
1661 * anyway, so we don't enable them here.
1662 */
1663 up->ier = UART_IER_RLSI | UART_IER_RDI;
1664 serial_outp(up, UART_IER, up->ier);
1665
1666 if (up->port.flags & UPF_FOURPORT) {
1667 unsigned int icp;
1668 /*
1669 * Enable interrupts on the AST Fourport board
1670 */
1671 icp = (up->port.iobase & 0xfe0) | 0x01f;
1672 outb_p(0x80, icp);
1673 (void) inb_p(icp);
1674 }
1675
1676 /*
1677 * And clear the interrupt registers again for luck.
1678 */
1679 (void) serial_inp(up, UART_LSR);
1680 (void) serial_inp(up, UART_RX);
1681 (void) serial_inp(up, UART_IIR);
1682 (void) serial_inp(up, UART_MSR);
1683
1684 return 0;
1685}
1686
1687static void serial8250_shutdown(struct uart_port *port)
1688{
1689 struct uart_8250_port *up = (struct uart_8250_port *)port;
1690 unsigned long flags;
1691
1692 /*
1693 * Disable interrupts from this port
1694 */
1695 up->ier = 0;
1696 serial_outp(up, UART_IER, 0);
1697
1698 spin_lock_irqsave(&up->port.lock, flags);
1699 if (up->port.flags & UPF_FOURPORT) {
1700 /* reset interrupts on the AST Fourport board */
1701 inb((up->port.iobase & 0xfe0) | 0x1f);
1702 up->port.mctrl |= TIOCM_OUT1;
1703 } else
1704 up->port.mctrl &= ~TIOCM_OUT2;
1705
1706 serial8250_set_mctrl(&up->port, up->port.mctrl);
1707 spin_unlock_irqrestore(&up->port.lock, flags);
1708
1709 /*
1710 * Disable break condition and FIFOs
1711 */
1712 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1713 serial8250_clear_fifos(up);
1714
1715#ifdef CONFIG_SERIAL_8250_RSA
1716 /*
1717 * Reset the RSA board back to 115kbps compat mode.
1718 */
1719 disable_rsa(up);
1720#endif
1721
1722 /*
1723 * Read data port to reset things, and then unlink from
1724 * the IRQ chain.
1725 */
1726 (void) serial_in(up, UART_RX);
1727
1728 if (!is_real_interrupt(up->port.irq))
1729 del_timer_sync(&up->timer);
1730 else
1731 serial_unlink_irq_chain(up);
1732}
1733
1734static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1735{
1736 unsigned int quot;
1737
1738 /*
1739 * Handle magic divisors for baud rates above baud_base on
1740 * SMSC SuperIO chips.
1741 */
1742 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1743 baud == (port->uartclk/4))
1744 quot = 0x8001;
1745 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1746 baud == (port->uartclk/8))
1747 quot = 0x8002;
1748 else
1749 quot = uart_get_divisor(port, baud);
1750
1751 return quot;
1752}
1753
1754static void
1755serial8250_set_termios(struct uart_port *port, struct termios *termios,
1756 struct termios *old)
1757{
1758 struct uart_8250_port *up = (struct uart_8250_port *)port;
1759 unsigned char cval, fcr = 0;
1760 unsigned long flags;
1761 unsigned int baud, quot;
1762
1763 switch (termios->c_cflag & CSIZE) {
1764 case CS5:
0a8b80c5 1765 cval = UART_LCR_WLEN5;
1da177e4
LT		 1766 break;
1767 case CS6:
0a8b80c5 1768 cval = UART_LCR_WLEN6;
1da177e4
LT		 1769 break;
1770 case CS7:
0a8b80c5 1771 cval = UART_LCR_WLEN7;
1da177e4
LT		 1772 break;
1773 default:
1774 case CS8:
0a8b80c5 1775 cval = UART_LCR_WLEN8;
1da177e4
LT		 1776 break;
1777 }
1778
1779 if (termios->c_cflag & CSTOPB)
0a8b80c5 1780 cval |= UART_LCR_STOP;
1da177e4
LT		 1781 if (termios->c_cflag & PARENB)
1782 cval |= UART_LCR_PARITY;
1783 if (!(termios->c_cflag & PARODD))
1784 cval |= UART_LCR_EPAR;
1785#ifdef CMSPAR
1786 if (termios->c_cflag & CMSPAR)
1787 cval |= UART_LCR_SPAR;
1788#endif
1789
1790 /*
1791 * Ask the core to calculate the divisor for us.
1792 */
1793 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1794 quot = serial8250_get_divisor(port, baud);
1795
1796 /*
4ba5e35d 1797 * Oxford Semi 952 rev B workaround
1da177e4 1798 */
4ba5e35d 1799 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1da177e4
LT		 1800 quot ++;
1801
1802 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1803 if (baud < 2400)
1804 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1805 else
1806 fcr = uart_config[up->port.type].fcr;
1807 }
1808
1809 /*
1810 * MCR-based auto flow control. When AFE is enabled, RTS will be
1811 * deasserted when the receive FIFO contains more characters than
1812 * the trigger, or the MCR RTS bit is cleared. In the case where
1813 * the remote UART is not using CTS auto flow control, we must
1814 * have sufficient FIFO entries for the latency of the remote
1815 * UART to respond. IOW, at least 32 bytes of FIFO.
1816 */
1817 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1818 up->mcr &= ~UART_MCR_AFE;
1819 if (termios->c_cflag & CRTSCTS)
1820 up->mcr |= UART_MCR_AFE;
1821 }
1822
1823 /*
1824 * Ok, we're now changing the port state. Do it with
1825 * interrupts disabled.
1826 */
1827 spin_lock_irqsave(&up->port.lock, flags);
1828
1829 /*
1830 * Update the per-port timeout.
1831 */
1832 uart_update_timeout(port, termios->c_cflag, baud);
1833
1834 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1835 if (termios->c_iflag & INPCK)
1836 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1837 if (termios->c_iflag & (BRKINT | PARMRK))
1838 up->port.read_status_mask |= UART_LSR_BI;
1839
1840 /*
1841 * Characteres to ignore
1842 */
1843 up->port.ignore_status_mask = 0;
1844 if (termios->c_iflag & IGNPAR)
1845 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1846 if (termios->c_iflag & IGNBRK) {
1847 up->port.ignore_status_mask |= UART_LSR_BI;
1848 /*
1849 * If we're ignoring parity and break indicators,
1850 * ignore overruns too (for real raw support).
1851 */
1852 if (termios->c_iflag & IGNPAR)
1853 up->port.ignore_status_mask |= UART_LSR_OE;
1854 }
1855
1856 /*
1857 * ignore all characters if CREAD is not set
1858 */
1859 if ((termios->c_cflag & CREAD) == 0)
1860 up->port.ignore_status_mask |= UART_LSR_DR;
1861
1862 /*
1863 * CTS flow control flag and modem status interrupts
1864 */
1865 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 1866 if (!(up->bugs & UART_BUG_NOMSR) &&
1867 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 1868 up->ier |= UART_IER_MSI;
1869 if (up->capabilities & UART_CAP_UUE)
1870 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1871
1872 serial_out(up, UART_IER, up->ier);
1873
1874 if (up->capabilities & UART_CAP_EFR) {
1875 unsigned char efr = 0;
1876 /*
1877 * TI16C752/Startech hardware flow control. FIXME:
1878 * - TI16C752 requires control thresholds to be set.
1879 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1880 */
1881 if (termios->c_cflag & CRTSCTS)
1882 efr |= UART_EFR_CTS;
1883
1884 serial_outp(up, UART_LCR, 0xBF);
1885 serial_outp(up, UART_EFR, efr);
1886 }
1887
1888 if (up->capabilities & UART_NATSEMI) {
1889 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1890 serial_outp(up, UART_LCR, 0xe0);
1891 } else {
1892 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1893 }
1894
b32b19b8 1895 serial_dl_write(up, quot);
1da177e4
LT		 1896
1897 /*
1898 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1899 * is written without DLAB set, this mode will be disabled.
1900 */
1901 if (up->port.type == PORT_16750)
1902 serial_outp(up, UART_FCR, fcr);
1903
1904 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1905 up->lcr = cval; /* Save LCR */
1906 if (up->port.type != PORT_16750) {
1907 if (fcr & UART_FCR_ENABLE_FIFO) {
1908 /* emulated UARTs (Lucent Venus 167x) need two steps */
1909 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1910 }
1911 serial_outp(up, UART_FCR, fcr); /* set fcr */
1912 }
1913 serial8250_set_mctrl(&up->port, up->port.mctrl);
1914 spin_unlock_irqrestore(&up->port.lock, flags);
1915}
1916
1917static void
1918serial8250_pm(struct uart_port *port, unsigned int state,
1919 unsigned int oldstate)
1920{
1921 struct uart_8250_port *p = (struct uart_8250_port *)port;
1922
1923 serial8250_set_sleep(p, state != 0);
1924
1925 if (p->pm)
1926 p->pm(port, state, oldstate);
1927}
1928
1929/*
1930 * Resource handling.
1931 */
1932static int serial8250_request_std_resource(struct uart_8250_port *up)
1933{
1934 unsigned int size = 8 << up->port.regshift;
1935 int ret = 0;
1936
1937 switch (up->port.iotype) {
85835f44
SS		 1938 case UPIO_AU:
1939 size = 0x100000;
1940 /* fall thru */
1da177e4
LT		 1941 case UPIO_MEM:
1942 if (!up->port.mapbase)
1943 break;
1944
1945 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1946 ret = -EBUSY;
1947 break;
1948 }
1949
1950 if (up->port.flags & UPF_IOREMAP) {
1951 up->port.membase = ioremap(up->port.mapbase, size);
1952 if (!up->port.membase) {
1953 release_mem_region(up->port.mapbase, size);
1954 ret = -ENOMEM;
1955 }
1956 }
1957 break;
1958
1959 case UPIO_HUB6:
1960 case UPIO_PORT:
1961 if (!request_region(up->port.iobase, size, "serial"))
1962 ret = -EBUSY;
1963 break;
1964 }
1965 return ret;
1966}
1967
1968static void serial8250_release_std_resource(struct uart_8250_port *up)
1969{
1970 unsigned int size = 8 << up->port.regshift;
1971
1972 switch (up->port.iotype) {
85835f44
SS		 1973 case UPIO_AU:
1974 size = 0x100000;
1975 /* fall thru */
1da177e4
LT		 1976 case UPIO_MEM:
1977 if (!up->port.mapbase)
1978 break;
1979
1980 if (up->port.flags & UPF_IOREMAP) {
1981 iounmap(up->port.membase);
1982 up->port.membase = NULL;
1983 }
1984
1985 release_mem_region(up->port.mapbase, size);
1986 break;
1987
1988 case UPIO_HUB6:
1989 case UPIO_PORT:
1990 release_region(up->port.iobase, size);
1991 break;
1992 }
1993}
1994
1995static int serial8250_request_rsa_resource(struct uart_8250_port *up)
1996{
1997 unsigned long start = UART_RSA_BASE << up->port.regshift;
1998 unsigned int size = 8 << up->port.regshift;
1999 int ret = 0;
2000
2001 switch (up->port.iotype) {
2002 case UPIO_MEM:
2003 ret = -EINVAL;
2004 break;
2005
2006 case UPIO_HUB6:
2007 case UPIO_PORT:
2008 start += up->port.iobase;
2009 if (!request_region(start, size, "serial-rsa"))
2010 ret = -EBUSY;
2011 break;
2012 }
2013
2014 return ret;
2015}
2016
2017static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2018{
2019 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2020 unsigned int size = 8 << up->port.regshift;
2021
2022 switch (up->port.iotype) {
2023 case UPIO_MEM:
2024 break;
2025
2026 case UPIO_HUB6:
2027 case UPIO_PORT:
2028 release_region(up->port.iobase + offset, size);
2029 break;
2030 }
2031}
2032
2033static void serial8250_release_port(struct uart_port *port)
2034{
2035 struct uart_8250_port *up = (struct uart_8250_port *)port;
2036
2037 serial8250_release_std_resource(up);
2038 if (up->port.type == PORT_RSA)
2039 serial8250_release_rsa_resource(up);
2040}
2041
2042static int serial8250_request_port(struct uart_port *port)
2043{
2044 struct uart_8250_port *up = (struct uart_8250_port *)port;
2045 int ret = 0;
2046
2047 ret = serial8250_request_std_resource(up);
2048 if (ret == 0 && up->port.type == PORT_RSA) {
2049 ret = serial8250_request_rsa_resource(up);
2050 if (ret < 0)
2051 serial8250_release_std_resource(up);
2052 }
2053
2054 return ret;
2055}
2056
2057static void serial8250_config_port(struct uart_port *port, int flags)
2058{
2059 struct uart_8250_port *up = (struct uart_8250_port *)port;
2060 int probeflags = PROBE_ANY;
2061 int ret;
2062
1da177e4
LT		 2063 /*
2064 * Find the region that we can probe for. This in turn
2065 * tells us whether we can probe for the type of port.
2066 */
2067 ret = serial8250_request_std_resource(up);
2068 if (ret < 0)
2069 return;
2070
2071 ret = serial8250_request_rsa_resource(up);
2072 if (ret < 0)
2073 probeflags &= ~PROBE_RSA;
2074
2075 if (flags & UART_CONFIG_TYPE)
2076 autoconfig(up, probeflags);
2077 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2078 autoconfig_irq(up);
2079
2080 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2081 serial8250_release_rsa_resource(up);
2082 if (up->port.type == PORT_UNKNOWN)
2083 serial8250_release_std_resource(up);
2084}
2085
2086static int
2087serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2088{
2089 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2090 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2091 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2092 ser->type == PORT_STARTECH)
2093 return -EINVAL;
2094 return 0;
2095}
2096
2097static const char *
2098serial8250_type(struct uart_port *port)
2099{
2100 int type = port->type;
2101
2102 if (type >= ARRAY_SIZE(uart_config))
2103 type = 0;
2104 return uart_config[type].name;
2105}
2106
2107static struct uart_ops serial8250_pops = {
2108 .tx_empty = serial8250_tx_empty,
2109 .set_mctrl = serial8250_set_mctrl,
2110 .get_mctrl = serial8250_get_mctrl,
2111 .stop_tx = serial8250_stop_tx,
2112 .start_tx = serial8250_start_tx,
2113 .stop_rx = serial8250_stop_rx,
2114 .enable_ms = serial8250_enable_ms,
2115 .break_ctl = serial8250_break_ctl,
2116 .startup = serial8250_startup,
2117 .shutdown = serial8250_shutdown,
2118 .set_termios = serial8250_set_termios,
2119 .pm = serial8250_pm,
2120 .type = serial8250_type,
2121 .release_port = serial8250_release_port,
2122 .request_port = serial8250_request_port,
2123 .config_port = serial8250_config_port,
2124 .verify_port = serial8250_verify_port,
2125};
2126
2127static struct uart_8250_port serial8250_ports[UART_NR];
2128
2129static void __init serial8250_isa_init_ports(void)
2130{
2131 struct uart_8250_port *up;
2132 static int first = 1;
2133 int i;
2134
2135 if (!first)
2136 return;
2137 first = 0;
2138
a61c2d78 2139 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2140 struct uart_8250_port *up = &serial8250_ports[i];
2141
2142 up->port.line = i;
2143 spin_lock_init(&up->port.lock);
2144
2145 init_timer(&up->timer);
2146 up->timer.function = serial8250_timeout;
2147
2148 /*
2149 * ALPHA_KLUDGE_MCR needs to be killed.
2150 */
2151 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2152 up->mcr_force = ALPHA_KLUDGE_MCR;
2153
2154 up->port.ops = &serial8250_pops;
2155 }
2156
44454bcd 2157 for (i = 0, up = serial8250_ports;
a61c2d78 2158 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2159 i++, up++) {
2160 up->port.iobase = old_serial_port[i].port;
2161 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2162 up->port.uartclk = old_serial_port[i].baud_base * 16;
2163 up->port.flags = old_serial_port[i].flags;
2164 up->port.hub6 = old_serial_port[i].hub6;
2165 up->port.membase = old_serial_port[i].iomem_base;
2166 up->port.iotype = old_serial_port[i].io_type;
2167 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2168 if (share_irqs)
2169 up->port.flags |= UPF_SHARE_IRQ;
2170 }
2171}
2172
2173static void __init
2174serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2175{
2176 int i;
2177
2178 serial8250_isa_init_ports();
2179
a61c2d78 2180 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2181 struct uart_8250_port *up = &serial8250_ports[i];
2182
2183 up->port.dev = dev;
2184 uart_add_one_port(drv, &up->port);
2185 }
2186}
2187
2188#ifdef CONFIG_SERIAL_8250_CONSOLE
2189
2190#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2191
2192/*
2193 * Wait for transmitter & holding register to empty
2194 */
f91a3715 2195static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1da177e4
LT		 2196{
2197 unsigned int status, tmout = 10000;
2198
2199 /* Wait up to 10ms for the character(s) to be sent. */
2200 do {
2201 status = serial_in(up, UART_LSR);
2202
2203 if (status & UART_LSR_BI)
2204 up->lsr_break_flag = UART_LSR_BI;
2205
2206 if (--tmout == 0)
2207 break;
2208 udelay(1);
f91a3715 2209 } while ((status & bits) != bits);
1da177e4
LT		 2210
2211 /* Wait up to 1s for flow control if necessary */
2212 if (up->port.flags & UPF_CONS_FLOW) {
2213 tmout = 1000000;
2214 while (--tmout &&
2215 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2216 udelay(1);
2217 }
2218}
2219
d358788f
RK		 2220static void serial8250_console_putchar(struct uart_port *port, int ch)
2221{
2222 struct uart_8250_port *up = (struct uart_8250_port *)port;
2223
2224 wait_for_xmitr(up, UART_LSR_THRE);
2225 serial_out(up, UART_TX, ch);
2226}
2227
1da177e4
LT		 2228/*
2229 * Print a string to the serial port trying not to disturb
2230 * any possible real use of the port...
2231 *
2232 * The console_lock must be held when we get here.
2233 */
2234static void
2235serial8250_console_write(struct console *co, const char *s, unsigned int count)
2236{
2237 struct uart_8250_port *up = &serial8250_ports[co->index];
2238 unsigned int ier;
1da177e4 2239
78512ece
AM		 2240 touch_nmi_watchdog();
2241
1da177e4 2242 /*
dc7bf130 2243 * First save the IER then disable the interrupts
1da177e4
LT		 2244 */
2245 ier = serial_in(up, UART_IER);
2246
2247 if (up->capabilities & UART_CAP_UUE)
2248 serial_out(up, UART_IER, UART_IER_UUE);
2249 else
2250 serial_out(up, UART_IER, 0);
2251
d358788f 2252 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2253
2254 /*
2255 * Finally, wait for transmitter to become empty
2256 * and restore the IER
2257 */
f91a3715 2258 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2259 serial_out(up, UART_IER, ier);
1da177e4
LT		 2260}
2261
2262static int serial8250_console_setup(struct console *co, char *options)
2263{
2264 struct uart_port *port;
2265 int baud = 9600;
2266 int bits = 8;
2267 int parity = 'n';
2268 int flow = 'n';
2269
2270 /*
2271 * Check whether an invalid uart number has been specified, and
2272 * if so, search for the first available port that does have
2273 * console support.
2274 */
a61c2d78 2275 if (co->index >= nr_uarts)
1da177e4
LT		 2276 co->index = 0;
2277 port = &serial8250_ports[co->index].port;
2278 if (!port->iobase && !port->membase)
2279 return -ENODEV;
2280
2281 if (options)
2282 uart_parse_options(options, &baud, &parity, &bits, &flow);
2283
2284 return uart_set_options(port, co, baud, parity, bits, flow);
2285}
2286
2287static struct uart_driver serial8250_reg;
2288static struct console serial8250_console = {
2289 .name = "ttyS",
2290 .write = serial8250_console_write,
2291 .device = uart_console_device,
2292 .setup = serial8250_console_setup,
2293 .flags = CON_PRINTBUFFER,
2294 .index = -1,
2295 .data = &serial8250_reg,
2296};
2297
2298static int __init serial8250_console_init(void)
2299{
2300 serial8250_isa_init_ports();
2301 register_console(&serial8250_console);
2302 return 0;
2303}
2304console_initcall(serial8250_console_init);
2305
2306static int __init find_port(struct uart_port *p)
2307{
2308 int line;
2309 struct uart_port *port;
2310
a61c2d78 2311 for (line = 0; line < nr_uarts; line++) {
1da177e4 2312 port = &serial8250_ports[line].port;
50aec3b5 2313 if (uart_match_port(p, port))
1da177e4
LT		 2314 return line;
2315 }
2316 return -ENODEV;
2317}
2318
2319int __init serial8250_start_console(struct uart_port *port, char *options)
2320{
2321 int line;
2322
2323 line = find_port(port);
2324 if (line < 0)
2325 return -ENODEV;
2326
2327 add_preferred_console("ttyS", line, options);
2328 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2329 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2330 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2331 (unsigned long) port->iobase, options);
2332 if (!(serial8250_console.flags & CON_ENABLED)) {
2333 serial8250_console.flags &= ~CON_PRINTBUFFER;
2334 register_console(&serial8250_console);
2335 }
2336 return line;
2337}
2338
2339#define SERIAL8250_CONSOLE &serial8250_console
2340#else
2341#define SERIAL8250_CONSOLE NULL
2342#endif
2343
2344static struct uart_driver serial8250_reg = {
2345 .owner = THIS_MODULE,
2346 .driver_name = "serial",
2347 .devfs_name = "tts/",
2348 .dev_name = "ttyS",
2349 .major = TTY_MAJOR,
2350 .minor = 64,
2351 .nr = UART_NR,
2352 .cons = SERIAL8250_CONSOLE,
2353};
2354
d856c666
RK		 2355/*
2356 * early_serial_setup - early registration for 8250 ports
2357 *
2358 * Setup an 8250 port structure prior to console initialisation. Use
2359 * after console initialisation will cause undefined behaviour.
2360 */
1da177e4
LT		 2361int __init early_serial_setup(struct uart_port *port)
2362{
2363 if (port->line >= ARRAY_SIZE(serial8250_ports))
2364 return -ENODEV;
2365
2366 serial8250_isa_init_ports();
2367 serial8250_ports[port->line].port = *port;
2368 serial8250_ports[port->line].port.ops = &serial8250_pops;
2369 return 0;
2370}
2371
2372/**
2373 * serial8250_suspend_port - suspend one serial port
2374 * @line: serial line number
2375 * @level: the level of port suspension, as per uart_suspend_port
2376 *
2377 * Suspend one serial port.
2378 */
2379void serial8250_suspend_port(int line)
2380{
2381 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2382}
2383
2384/**
2385 * serial8250_resume_port - resume one serial port
2386 * @line: serial line number
2387 * @level: the level of port resumption, as per uart_resume_port
2388 *
2389 * Resume one serial port.
2390 */
2391void serial8250_resume_port(int line)
2392{
2393 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2394}
2395
2396/*
2397 * Register a set of serial devices attached to a platform device. The
2398 * list is terminated with a zero flags entry, which means we expect
2399 * all entries to have at least UPF_BOOT_AUTOCONF set.
2400 */
3ae5eaec 2401static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2402{
3ae5eaec 2403 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2404 struct uart_port port;
ec9f47cd 2405 int ret, i;
1da177e4
LT		 2406
2407 memset(&port, 0, sizeof(struct uart_port));
2408
ec9f47cd 2409 for (i = 0; p && p->flags != 0; p++, i++) {
1da177e4
LT		 2410 port.iobase = p->iobase;
2411 port.membase = p->membase;
2412 port.irq = p->irq;
2413 port.uartclk = p->uartclk;
2414 port.regshift = p->regshift;
2415 port.iotype = p->iotype;
2416 port.flags = p->flags;
2417 port.mapbase = p->mapbase;
ec9f47cd 2418 port.hub6 = p->hub6;
3ae5eaec 2419 port.dev = &dev->dev;
1da177e4
LT		 2420 if (share_irqs)
2421 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2422 ret = serial8250_register_port(&port);
2423 if (ret < 0) {
3ae5eaec 2424 dev_err(&dev->dev, "unable to register port at index %d "
ec9f47cd
RK		 2425 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2426 p->iobase, p->mapbase, p->irq, ret);
2427 }
1da177e4
LT		 2428 }
2429 return 0;
2430}
2431
2432/*
2433 * Remove serial ports registered against a platform device.
2434 */
3ae5eaec 2435static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2436{
2437 int i;
2438
a61c2d78 2439 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2440 struct uart_8250_port *up = &serial8250_ports[i];
2441
3ae5eaec 2442 if (up->port.dev == &dev->dev)
1da177e4
LT		 2443 serial8250_unregister_port(i);
2444 }
2445 return 0;
2446}
2447
3ae5eaec 2448static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2449{
2450 int i;
2451
1da177e4
LT		 2452 for (i = 0; i < UART_NR; i++) {
2453 struct uart_8250_port *up = &serial8250_ports[i];
2454
3ae5eaec 2455 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2456 uart_suspend_port(&serial8250_reg, &up->port);
2457 }
2458
2459 return 0;
2460}
2461
3ae5eaec 2462static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 2463{
2464 int i;
2465
1da177e4
LT		 2466 for (i = 0; i < UART_NR; i++) {
2467 struct uart_8250_port *up = &serial8250_ports[i];
2468
3ae5eaec 2469 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2470 uart_resume_port(&serial8250_reg, &up->port);
2471 }
2472
2473 return 0;
2474}
2475
3ae5eaec 2476static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 2477 .probe = serial8250_probe,
2478 .remove = __devexit_p(serial8250_remove),
2479 .suspend = serial8250_suspend,
2480 .resume = serial8250_resume,
3ae5eaec
RK		 2481 .driver = {
2482 .name = "serial8250",
7493a314 2483 .owner = THIS_MODULE,
3ae5eaec 2484 },
1da177e4
LT		 2485};
2486
2487/*
2488 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2489 * in the table in include/asm/serial.h
2490 */
2491static struct platform_device *serial8250_isa_devs;
2492
2493/*
2494 * serial8250_register_port and serial8250_unregister_port allows for
2495 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2496 * modems and PCI multiport cards.
2497 */
f392ecfa 2498static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 2499
2500static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2501{
2502 int i;
2503
2504 /*
2505 * First, find a port entry which matches.
2506 */
a61c2d78 2507 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2508 if (uart_match_port(&serial8250_ports[i].port, port))
2509 return &serial8250_ports[i];
2510
2511 /*
2512 * We didn't find a matching entry, so look for the first
2513 * free entry. We look for one which hasn't been previously
2514 * used (indicated by zero iobase).
2515 */
a61c2d78 2516 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2517 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2518 serial8250_ports[i].port.iobase == 0)
2519 return &serial8250_ports[i];
2520
2521 /*
2522 * That also failed. Last resort is to find any entry which
2523 * doesn't have a real port associated with it.
2524 */
a61c2d78 2525 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2526 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2527 return &serial8250_ports[i];
2528
2529 return NULL;
2530}
2531
2532/**
2533 * serial8250_register_port - register a serial port
2534 * @port: serial port template
2535 *
2536 * Configure the serial port specified by the request. If the
2537 * port exists and is in use, it is hung up and unregistered
2538 * first.
2539 *
2540 * The port is then probed and if necessary the IRQ is autodetected
2541 * If this fails an error is returned.
2542 *
2543 * On success the port is ready to use and the line number is returned.
2544 */
2545int serial8250_register_port(struct uart_port *port)
2546{
2547 struct uart_8250_port *uart;
2548 int ret = -ENOSPC;
2549
2550 if (port->uartclk == 0)
2551 return -EINVAL;
2552
f392ecfa 2553 mutex_lock(&serial_mutex);
1da177e4
LT		 2554
2555 uart = serial8250_find_match_or_unused(port);
2556 if (uart) {
2557 uart_remove_one_port(&serial8250_reg, &uart->port);
2558
2559 uart->port.iobase = port->iobase;
2560 uart->port.membase = port->membase;
2561 uart->port.irq = port->irq;
2562 uart->port.uartclk = port->uartclk;
2563 uart->port.fifosize = port->fifosize;
2564 uart->port.regshift = port->regshift;
2565 uart->port.iotype = port->iotype;
2566 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2567 uart->port.mapbase = port->mapbase;
2568 if (port->dev)
2569 uart->port.dev = port->dev;
2570
2571 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2572 if (ret == 0)
2573 ret = uart->port.line;
2574 }
f392ecfa 2575 mutex_unlock(&serial_mutex);
1da177e4
LT		 2576
2577 return ret;
2578}
2579EXPORT_SYMBOL(serial8250_register_port);
2580
2581/**
2582 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2583 * @line: serial line number
2584 *
2585 * Remove one serial port. This may not be called from interrupt
2586 * context. We hand the port back to the our control.
2587 */
2588void serial8250_unregister_port(int line)
2589{
2590 struct uart_8250_port *uart = &serial8250_ports[line];
2591
f392ecfa 2592 mutex_lock(&serial_mutex);
1da177e4
LT		 2593 uart_remove_one_port(&serial8250_reg, &uart->port);
2594 if (serial8250_isa_devs) {
2595 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2596 uart->port.type = PORT_UNKNOWN;
2597 uart->port.dev = &serial8250_isa_devs->dev;
2598 uart_add_one_port(&serial8250_reg, &uart->port);
2599 } else {
2600 uart->port.dev = NULL;
2601 }
f392ecfa 2602 mutex_unlock(&serial_mutex);
1da177e4
LT		 2603}
2604EXPORT_SYMBOL(serial8250_unregister_port);
2605
2606static int __init serial8250_init(void)
2607{
2608 int ret, i;
2609
a61c2d78
DJ		 2610 if (nr_uarts > UART_NR)
2611 nr_uarts = UART_NR;
2612
1da177e4 2613 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
a61c2d78 2614 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 2615 share_irqs ? "en" : "dis");
2616
2617 for (i = 0; i < NR_IRQS; i++)
2618 spin_lock_init(&irq_lists[i].lock);
2619
2620 ret = uart_register_driver(&serial8250_reg);
2621 if (ret)
2622 goto out;
2623
7493a314
DT		 2624 serial8250_isa_devs = platform_device_alloc("serial8250",
2625 PLAT8250_DEV_LEGACY);
2626 if (!serial8250_isa_devs) {
2627 ret = -ENOMEM;
bc965a7f 2628 goto unreg_uart_drv;
1da177e4
LT		 2629 }
2630
7493a314
DT		 2631 ret = platform_device_add(serial8250_isa_devs);
2632 if (ret)
2633 goto put_dev;
2634
1da177e4
LT		 2635 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2636
bc965a7f
RK		 2637 ret = platform_driver_register(&serial8250_isa_driver);
2638 if (ret == 0)
2639 goto out;
1da177e4 2640
bc965a7f 2641 platform_device_del(serial8250_isa_devs);
7493a314
DT		 2642 put_dev:
2643 platform_device_put(serial8250_isa_devs);
7493a314 2644 unreg_uart_drv:
1da177e4
LT		 2645 uart_unregister_driver(&serial8250_reg);
2646 out:
2647 return ret;
2648}
2649
2650static void __exit serial8250_exit(void)
2651{
2652 struct platform_device *isa_dev = serial8250_isa_devs;
2653
2654 /*
2655 * This tells serial8250_unregister_port() not to re-register
2656 * the ports (thereby making serial8250_isa_driver permanently
2657 * in use.)
2658 */
2659 serial8250_isa_devs = NULL;
2660
3ae5eaec 2661 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 2662 platform_device_unregister(isa_dev);
2663
2664 uart_unregister_driver(&serial8250_reg);
2665}
2666
2667module_init(serial8250_init);
2668module_exit(serial8250_exit);
2669
2670EXPORT_SYMBOL(serial8250_suspend_port);
2671EXPORT_SYMBOL(serial8250_resume_port);
2672
2673MODULE_LICENSE("GPL");
2674MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2675
2676module_param(share_irqs, uint, 0644);
2677MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2678 " (unsafe)");
2679
a61c2d78
DJ		 2680module_param(nr_uarts, uint, 0644);
2681MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2682
1da177e4
LT		 2683#ifdef CONFIG_SERIAL_8250_RSA
2684module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2685MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2686#endif
2687MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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