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[SCSI] mvsas: fix potential NULL dereference
[net-next-2.6.git] / drivers / scsi / mvsas / mv_sas.c
CommitLineData
b5762948 1/*
20b09c29
AY		 2 * Marvell 88SE64xx/88SE94xx main function
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 *
7 * This file is licensed under GPLv2.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23*/
b5762948 24
dd4969a8 25#include "mv_sas.h"
b5762948 26
dd4969a8
JG		 27static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
28{
29 if (task->lldd_task) {
30 struct mvs_slot_info *slot;
f9da3be5 31 slot = task->lldd_task;
20b09c29 32 *tag = slot->slot_tag;
dd4969a8
JG		 33 return 1;
34 }
35 return 0;
36}
8f261aaf 37
20b09c29 38void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
dd4969a8 39{
f9da3be5 40 void *bitmap = &mvi->tags;
dd4969a8
JG		 41 clear_bit(tag, bitmap);
42}
8f261aaf 43
20b09c29 44void mvs_tag_free(struct mvs_info *mvi, u32 tag)
dd4969a8
JG		 45{
46 mvs_tag_clear(mvi, tag);
47}
8f261aaf 48
20b09c29 49void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
dd4969a8 50{
f9da3be5 51 void *bitmap = &mvi->tags;
dd4969a8
JG		 52 set_bit(tag, bitmap);
53}
8f261aaf 54
20b09c29 55inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
dd4969a8
JG		 56{
57 unsigned int index, tag;
f9da3be5 58 void *bitmap = &mvi->tags;
b5762948 59
20b09c29 60 index = find_first_zero_bit(bitmap, mvi->tags_num);
dd4969a8 61 tag = index;
20b09c29 62 if (tag >= mvi->tags_num)
dd4969a8
JG		 63 return -SAS_QUEUE_FULL;
64 mvs_tag_set(mvi, tag);
65 *tag_out = tag;
66 return 0;
67}
b5762948 68
dd4969a8
JG		 69void mvs_tag_init(struct mvs_info *mvi)
70{
71 int i;
20b09c29 72 for (i = 0; i < mvi->tags_num; ++i)
dd4969a8
JG		 73 mvs_tag_clear(mvi, i);
74}
b5762948 75
20b09c29 76void mvs_hexdump(u32 size, u8 *data, u32 baseaddr)
8f261aaf
KW		 77{
78 u32 i;
79 u32 run;
80 u32 offset;
81
82 offset = 0;
83 while (size) {
20b09c29 84 printk(KERN_DEBUG"%08X : ", baseaddr + offset);
8f261aaf
KW		 85 if (size >= 16)
86 run = 16;
87 else
88 run = size;
89 size -= run;
90 for (i = 0; i < 16; i++) {
91 if (i < run)
20b09c29 92 printk(KERN_DEBUG"%02X ", (u32)data[i]);
8f261aaf 93 else
20b09c29 94 printk(KERN_DEBUG" ");
8f261aaf 95 }
20b09c29 96 printk(KERN_DEBUG": ");
8f261aaf 97 for (i = 0; i < run; i++)
20b09c29
AY		 98 printk(KERN_DEBUG"%c",
99 isalnum(data[i]) ? data[i] : '.');
100 printk(KERN_DEBUG"\n");
8f261aaf
KW		 101 data = &data[16];
102 offset += run;
103 }
20b09c29 104 printk(KERN_DEBUG"\n");
8f261aaf
KW		 105}
106
20b09c29 107#if (_MV_DUMP > 1)
8f261aaf
KW		 108static void mvs_hba_sb_dump(struct mvs_info *mvi, u32 tag,
109 enum sas_protocol proto)
110{
8f261aaf 111 u32 offset;
8f261aaf
KW		 112 struct mvs_slot_info *slot = &mvi->slot_info[tag];
113
114 offset = slot->cmd_size + MVS_OAF_SZ +
20b09c29
AY		 115 MVS_CHIP_DISP->prd_size() * slot->n_elem;
116 dev_printk(KERN_DEBUG, mvi->dev, "+---->Status buffer[%d] :\n",
8f261aaf
KW		 117 tag);
118 mvs_hexdump(32, (u8 *) slot->response,
119 (u32) slot->buf_dma + offset);
8f261aaf 120}
ee1f1c2e 121#endif
8f261aaf
KW		 122
123static void mvs_hba_memory_dump(struct mvs_info *mvi, u32 tag,
124 enum sas_protocol proto)
125{
20b09c29 126#if (_MV_DUMP > 1)
ee1f1c2e 127 u32 sz, w_ptr;
8f261aaf 128 u64 addr;
8f261aaf
KW		 129 struct mvs_slot_info *slot = &mvi->slot_info[tag];
130
131 /*Delivery Queue */
20b09c29 132 sz = MVS_CHIP_SLOT_SZ;
ee1f1c2e 133 w_ptr = slot->tx;
20b09c29
AY		 134 addr = mvi->tx_dma;
135 dev_printk(KERN_DEBUG, mvi->dev,
ee1f1c2e 136 "Delivery Queue Size=%04d , WRT_PTR=%04X\n", sz, w_ptr);
20b09c29 137 dev_printk(KERN_DEBUG, mvi->dev,
8f261aaf
KW		 138 "Delivery Queue Base Address=0x%llX (PA)"
139 "(tx_dma=0x%llX), Entry=%04d\n",
20b09c29 140 addr, (unsigned long long)mvi->tx_dma, w_ptr);
8f261aaf
KW		 141 mvs_hexdump(sizeof(u32), (u8 *)(&mvi->tx[mvi->tx_prod]),
142 (u32) mvi->tx_dma + sizeof(u32) * w_ptr);
143 /*Command List */
ee1f1c2e 144 addr = mvi->slot_dma;
20b09c29 145 dev_printk(KERN_DEBUG, mvi->dev,
8f261aaf
KW		 146 "Command List Base Address=0x%llX (PA)"
147 "(slot_dma=0x%llX), Header=%03d\n",
20b09c29
AY		 148 addr, (unsigned long long)slot->buf_dma, tag);
149 dev_printk(KERN_DEBUG, mvi->dev, "Command Header[%03d]:\n", tag);
8f261aaf
KW		 150 /*mvs_cmd_hdr */
151 mvs_hexdump(sizeof(struct mvs_cmd_hdr), (u8 *)(&mvi->slot[tag]),
152 (u32) mvi->slot_dma + tag * sizeof(struct mvs_cmd_hdr));
153 /*1.command table area */
20b09c29 154 dev_printk(KERN_DEBUG, mvi->dev, "+---->Command Table :\n");
8f261aaf
KW		 155 mvs_hexdump(slot->cmd_size, (u8 *) slot->buf, (u32) slot->buf_dma);
156 /*2.open address frame area */
20b09c29 157 dev_printk(KERN_DEBUG, mvi->dev, "+---->Open Address Frame :\n");
8f261aaf
KW		 158 mvs_hexdump(MVS_OAF_SZ, (u8 *) slot->buf + slot->cmd_size,
159 (u32) slot->buf_dma + slot->cmd_size);
160 /*3.status buffer */
161 mvs_hba_sb_dump(mvi, tag, proto);
162 /*4.PRD table */
20b09c29
AY		 163 dev_printk(KERN_DEBUG, mvi->dev, "+---->PRD table :\n");
164 mvs_hexdump(MVS_CHIP_DISP->prd_size() * slot->n_elem,
8f261aaf
KW		 165 (u8 *) slot->buf + slot->cmd_size + MVS_OAF_SZ,
166 (u32) slot->buf_dma + slot->cmd_size + MVS_OAF_SZ);
167#endif
168}
169
170static void mvs_hba_cq_dump(struct mvs_info *mvi)
171{
ee1f1c2e 172#if (_MV_DUMP > 2)
8f261aaf
KW		 173 u64 addr;
174 void __iomem *regs = mvi->regs;
8f261aaf
KW		 175 u32 entry = mvi->rx_cons + 1;
176 u32 rx_desc = le32_to_cpu(mvi->rx[entry]);
177
178 /*Completion Queue */
179 addr = mr32(RX_HI) << 16 << 16 | mr32(RX_LO);
20b09c29 180 dev_printk(KERN_DEBUG, mvi->dev, "Completion Task = 0x%p\n",
ee1f1c2e 181 mvi->slot_info[rx_desc & RXQ_SLOT_MASK].task);
20b09c29 182 dev_printk(KERN_DEBUG, mvi->dev,
8f261aaf
KW		 183 "Completion List Base Address=0x%llX (PA), "
184 "CQ_Entry=%04d, CQ_WP=0x%08X\n",
185 addr, entry - 1, mvi->rx[0]);
186 mvs_hexdump(sizeof(u32), (u8 *)(&rx_desc),
187 mvi->rx_dma + sizeof(u32) * entry);
188#endif
189}
190
20b09c29 191void mvs_get_sas_addr(void *buf, u32 buflen)
8f261aaf 192{
20b09c29
AY		 193 /*memcpy(buf, "\x50\x05\x04\x30\x11\xab\x64\x40", 8);*/
194}
8f261aaf 195
20b09c29
AY		 196struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
197{
198 unsigned long i = 0, j = 0, hi = 0;
199 struct sas_ha_struct *sha = dev->port->ha;
200 struct mvs_info *mvi = NULL;
201 struct asd_sas_phy *phy;
202
203 while (sha->sas_port[i]) {
204 if (sha->sas_port[i] == dev->port) {
205 phy = container_of(sha->sas_port[i]->phy_list.next,
206 struct asd_sas_phy, port_phy_el);
207 j = 0;
208 while (sha->sas_phy[j]) {
209 if (sha->sas_phy[j] == phy)
210 break;
211 j++;
212 }
213 break;
214 }
215 i++;
216 }
217 hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
218 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
8f261aaf 219
20b09c29 220 return mvi;
8f261aaf 221
20b09c29 222}
8f261aaf 223
20b09c29
AY		 224/* FIXME */
225int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
226{
227 unsigned long i = 0, j = 0, n = 0, num = 0;
9870d9a2
AY		 228 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
229 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 230 struct sas_ha_struct *sha = dev->port->ha;
231
232 while (sha->sas_port[i]) {
233 if (sha->sas_port[i] == dev->port) {
234 struct asd_sas_phy *phy;
235 list_for_each_entry(phy,
236 &sha->sas_port[i]->phy_list, port_phy_el) {
237 j = 0;
238 while (sha->sas_phy[j]) {
239 if (sha->sas_phy[j] == phy)
240 break;
241 j++;
242 }
243 phyno[n] = (j >= mvi->chip->n_phy) ?
244 (j - mvi->chip->n_phy) : j;
245 num++;
246 n++;
dd4969a8 247 }
dd4969a8
JG		 248 break;
249 }
20b09c29
AY		 250 i++;
251 }
252 return num;
253}
254
255static inline void mvs_free_reg_set(struct mvs_info *mvi,
256 struct mvs_device *dev)
257{
258 if (!dev) {
259 mv_printk("device has been free.\n");
260 return;
261 }
20b09c29
AY		 262 if (dev->taskfileset == MVS_ID_NOT_MAPPED)
263 return;
264 MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
265}
266
267static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
268 struct mvs_device *dev)
269{
270 if (dev->taskfileset != MVS_ID_NOT_MAPPED)
271 return 0;
272 return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
273}
274
275void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
276{
277 u32 no;
278 for_each_phy(phy_mask, phy_mask, no) {
279 if (!(phy_mask & 1))
280 continue;
281 MVS_CHIP_DISP->phy_reset(mvi, no, hard);
282 }
283}
284
285/* FIXME: locking? */
286int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
287 void *funcdata)
288{
289 int rc = 0, phy_id = sas_phy->id;
290 u32 tmp, i = 0, hi;
291 struct sas_ha_struct *sha = sas_phy->ha;
292 struct mvs_info *mvi = NULL;
293
294 while (sha->sas_phy[i]) {
295 if (sha->sas_phy[i] == sas_phy)
296 break;
297 i++;
298 }
299 hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
300 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
301
302 switch (func) {
303 case PHY_FUNC_SET_LINK_RATE:
304 MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
305 break;
8f261aaf 306
dd4969a8 307 case PHY_FUNC_HARD_RESET:
20b09c29 308 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
dd4969a8
JG		 309 if (tmp & PHY_RST_HARD)
310 break;
20b09c29 311 MVS_CHIP_DISP->phy_reset(mvi, phy_id, 1);
dd4969a8 312 break;
b5762948 313
dd4969a8 314 case PHY_FUNC_LINK_RESET:
20b09c29
AY		 315 MVS_CHIP_DISP->phy_enable(mvi, phy_id);
316 MVS_CHIP_DISP->phy_reset(mvi, phy_id, 0);
dd4969a8 317 break;
b5762948 318
dd4969a8 319 case PHY_FUNC_DISABLE:
20b09c29
AY		 320 MVS_CHIP_DISP->phy_disable(mvi, phy_id);
321 break;
dd4969a8
JG		 322 case PHY_FUNC_RELEASE_SPINUP_HOLD:
323 default:
324 rc = -EOPNOTSUPP;
b5762948 325 }
20b09c29 326 msleep(200);
b5762948
JG		 327 return rc;
328}
329
20b09c29
AY		 330void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
331 u32 off_lo, u32 off_hi, u64 sas_addr)
332{
333 u32 lo = (u32)sas_addr;
334 u32 hi = (u32)(sas_addr>>32);
335
336 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
337 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
338 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
339 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
340}
341
dd4969a8 342static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
ee1f1c2e 343{
dd4969a8 344 struct mvs_phy *phy = &mvi->phy[i];
20b09c29
AY		 345 struct asd_sas_phy *sas_phy = &phy->sas_phy;
346 struct sas_ha_struct *sas_ha;
dd4969a8
JG		 347 if (!phy->phy_attached)
348 return;
349
20b09c29
AY		 350 if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
351 && phy->phy_type & PORT_TYPE_SAS) {
352 return;
353 }
354
355 sas_ha = mvi->sas;
356 sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
357
dd4969a8
JG		 358 if (sas_phy->phy) {
359 struct sas_phy *sphy = sas_phy->phy;
360
361 sphy->negotiated_linkrate = sas_phy->linkrate;
362 sphy->minimum_linkrate = phy->minimum_linkrate;
363 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
364 sphy->maximum_linkrate = phy->maximum_linkrate;
20b09c29 365 sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
ee1f1c2e 366 }
ee1f1c2e 367
dd4969a8
JG		 368 if (phy->phy_type & PORT_TYPE_SAS) {
369 struct sas_identify_frame *id;
b5762948 370
dd4969a8
JG		 371 id = (struct sas_identify_frame *)phy->frame_rcvd;
372 id->dev_type = phy->identify.device_type;
373 id->initiator_bits = SAS_PROTOCOL_ALL;
374 id->target_bits = phy->identify.target_port_protocols;
375 } else if (phy->phy_type & PORT_TYPE_SATA) {
20b09c29 376 /*Nothing*/
dd4969a8 377 }
20b09c29
AY		 378 mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
379
380 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
381
382 mvi->sas->notify_port_event(sas_phy,
dd4969a8 383 PORTE_BYTES_DMAED);
ee1f1c2e
KW		 384}
385
20b09c29
AY		 386int mvs_slave_alloc(struct scsi_device *scsi_dev)
387{
388 struct domain_device *dev = sdev_to_domain_dev(scsi_dev);
389 if (dev_is_sata(dev)) {
390 /* We don't need to rescan targets
391 * if REPORT_LUNS request is failed
392 */
393 if (scsi_dev->lun > 0)
394 return -ENXIO;
395 scsi_dev->tagged_supported = 1;
396 }
397
398 return sas_slave_alloc(scsi_dev);
399}
400
dd4969a8 401int mvs_slave_configure(struct scsi_device *sdev)
ee1f1c2e 402{
dd4969a8
JG		 403 struct domain_device *dev = sdev_to_domain_dev(sdev);
404 int ret = sas_slave_configure(sdev);
b5762948 405
dd4969a8
JG		 406 if (ret)
407 return ret;
dd4969a8 408 if (dev_is_sata(dev)) {
20b09c29
AY		 409 /* may set PIO mode */
410 #if MV_DISABLE_NCQ
411 struct ata_port *ap = dev->sata_dev.ap;
412 struct ata_device *adev = ap->link.device;
413 adev->flags |= ATA_DFLAG_NCQ_OFF;
dd4969a8 414 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, 1);
20b09c29 415 #endif
dd4969a8 416 }
ee1f1c2e 417 return 0;
b5762948
JG		 418}
419
dd4969a8 420void mvs_scan_start(struct Scsi_Host *shost)
b5762948 421{
20b09c29
AY		 422 int i, j;
423 unsigned short core_nr;
424 struct mvs_info *mvi;
425 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
426
427 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
dd4969a8 428
20b09c29
AY		 429 for (j = 0; j < core_nr; j++) {
430 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
431 for (i = 0; i < mvi->chip->n_phy; ++i)
432 mvs_bytes_dmaed(mvi, i);
dd4969a8 433 }
b5762948
JG		 434}
435
dd4969a8 436int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
b5762948 437{
dd4969a8
JG		 438 /* give the phy enabling interrupt event time to come in (1s
439 * is empirically about all it takes) */
440 if (time < HZ)
441 return 0;
442 /* Wait for discovery to finish */
443 scsi_flush_work(shost);
444 return 1;
b5762948
JG		 445}
446
dd4969a8
JG		 447static int mvs_task_prep_smp(struct mvs_info *mvi,
448 struct mvs_task_exec_info *tei)
b5762948 449{
dd4969a8
JG		 450 int elem, rc, i;
451 struct sas_task *task = tei->task;
452 struct mvs_cmd_hdr *hdr = tei->hdr;
20b09c29
AY		 453 struct domain_device *dev = task->dev;
454 struct asd_sas_port *sas_port = dev->port;
dd4969a8
JG		 455 struct scatterlist *sg_req, *sg_resp;
456 u32 req_len, resp_len, tag = tei->tag;
457 void *buf_tmp;
458 u8 *buf_oaf;
459 dma_addr_t buf_tmp_dma;
20b09c29 460 void *buf_prd;
dd4969a8 461 struct mvs_slot_info *slot = &mvi->slot_info[tag];
dd4969a8
JG		 462 u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
463#if _MV_DUMP
464 u8 *buf_cmd;
465 void *from;
466#endif
467 /*
468 * DMA-map SMP request, response buffers
469 */
470 sg_req = &task->smp_task.smp_req;
20b09c29 471 elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
dd4969a8
JG		 472 if (!elem)
473 return -ENOMEM;
474 req_len = sg_dma_len(sg_req);
b5762948 475
dd4969a8 476 sg_resp = &task->smp_task.smp_resp;
20b09c29 477 elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
dd4969a8
JG		 478 if (!elem) {
479 rc = -ENOMEM;
480 goto err_out;
481 }
20b09c29 482 resp_len = SB_RFB_MAX;
b5762948 483
dd4969a8
JG		 484 /* must be in dwords */
485 if ((req_len & 0x3) || (resp_len & 0x3)) {
486 rc = -EINVAL;
487 goto err_out_2;
b5762948
JG		 488 }
489
dd4969a8
JG		 490 /*
491 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
492 */
b5762948 493
20b09c29 494 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
dd4969a8
JG		 495 buf_tmp = slot->buf;
496 buf_tmp_dma = slot->buf_dma;
b5762948 497
dd4969a8
JG		 498#if _MV_DUMP
499 buf_cmd = buf_tmp;
500 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
501 buf_tmp += req_len;
502 buf_tmp_dma += req_len;
503 slot->cmd_size = req_len;
504#else
505 hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
506#endif
b5762948 507
dd4969a8
JG		 508 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
509 buf_oaf = buf_tmp;
510 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
b5762948 511
dd4969a8
JG		 512 buf_tmp += MVS_OAF_SZ;
513 buf_tmp_dma += MVS_OAF_SZ;
b5762948 514
20b09c29 515 /* region 3: PRD table *********************************** */
dd4969a8
JG		 516 buf_prd = buf_tmp;
517 if (tei->n_elem)
518 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
519 else
520 hdr->prd_tbl = 0;
b5762948 521
20b09c29 522 i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
dd4969a8
JG		 523 buf_tmp += i;
524 buf_tmp_dma += i;
b5762948 525
dd4969a8
JG		 526 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
527 slot->response = buf_tmp;
528 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 529 if (mvi->flags & MVF_FLAG_SOC)
530 hdr->reserved[0] = 0;
b5762948 531
dd4969a8
JG		 532 /*
533 * Fill in TX ring and command slot header
534 */
535 slot->tx = mvi->tx_prod;
536 mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
537 TXQ_MODE_I | tag |
538 (sas_port->phy_mask << TXQ_PHY_SHIFT));
b5762948 539
dd4969a8
JG		 540 hdr->flags |= flags;
541 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
542 hdr->tags = cpu_to_le32(tag);
543 hdr->data_len = 0;
b5762948 544
dd4969a8 545 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 546 /* initiator, SMP, ftype 1h */
547 buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
548 buf_oaf[1] = dev->linkrate & 0xf;
dd4969a8 549 *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
20b09c29 550 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
dd4969a8
JG		 551
552 /* fill in PRD (scatter/gather) table, if any */
20b09c29 553 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
b5762948 554
dd4969a8
JG		 555#if _MV_DUMP
556 /* copy cmd table */
557 from = kmap_atomic(sg_page(sg_req), KM_IRQ0);
558 memcpy(buf_cmd, from + sg_req->offset, req_len);
559 kunmap_atomic(from, KM_IRQ0);
560#endif
b5762948
JG		 561 return 0;
562
dd4969a8 563err_out_2:
20b09c29 564 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
dd4969a8 565 PCI_DMA_FROMDEVICE);
b5762948 566err_out:
20b09c29 567 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
dd4969a8 568 PCI_DMA_TODEVICE);
8f261aaf 569 return rc;
8f261aaf
KW		 570}
571
dd4969a8 572static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
8f261aaf 573{
dd4969a8 574 struct ata_queued_cmd *qc = task->uldd_task;
8f261aaf 575
dd4969a8
JG		 576 if (qc) {
577 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
578 qc->tf.command == ATA_CMD_FPDMA_READ) {
579 *tag = qc->tag;
580 return 1;
581 }
8f261aaf 582 }
8f261aaf 583
dd4969a8 584 return 0;
8f261aaf
KW		 585}
586
dd4969a8
JG		 587static int mvs_task_prep_ata(struct mvs_info *mvi,
588 struct mvs_task_exec_info *tei)
b5762948
JG		 589{
590 struct sas_task *task = tei->task;
591 struct domain_device *dev = task->dev;
f9da3be5 592 struct mvs_device *mvi_dev = dev->lldd_dev;
b5762948
JG		 593 struct mvs_cmd_hdr *hdr = tei->hdr;
594 struct asd_sas_port *sas_port = dev->port;
8f261aaf 595 struct mvs_slot_info *slot;
20b09c29
AY		 596 void *buf_prd;
597 u32 tag = tei->tag, hdr_tag;
598 u32 flags, del_q;
b5762948
JG		 599 void *buf_tmp;
600 u8 *buf_cmd, *buf_oaf;
601 dma_addr_t buf_tmp_dma;
8f261aaf
KW		 602 u32 i, req_len, resp_len;
603 const u32 max_resp_len = SB_RFB_MAX;
604
20b09c29
AY		 605 if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
606 mv_dprintk("Have not enough regiset for dev %d.\n",
607 mvi_dev->device_id);
8f261aaf 608 return -EBUSY;
20b09c29 609 }
8f261aaf
KW		 610 slot = &mvi->slot_info[tag];
611 slot->tx = mvi->tx_prod;
20b09c29
AY		 612 del_q = TXQ_MODE_I | tag |
613 (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
614 (sas_port->phy_mask << TXQ_PHY_SHIFT) |
615 (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
616 mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
617
618#ifndef DISABLE_HOTPLUG_DMA_FIX
619 if (task->data_dir == DMA_FROM_DEVICE)
620 flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
621 else
622 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
623#else
624 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
625#endif
b5762948
JG		 626 if (task->ata_task.use_ncq)
627 flags |= MCH_FPDMA;
8f261aaf
KW		 628 if (dev->sata_dev.command_set == ATAPI_COMMAND_SET) {
629 if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
630 flags |= MCH_ATAPI;
631 }
632
b5762948
JG		 633 /* FIXME: fill in port multiplier number */
634
635 hdr->flags = cpu_to_le32(flags);
8f261aaf
KW		 636
637 /* FIXME: the low order order 5 bits for the TAG if enable NCQ */
20b09c29
AY		 638 if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
639 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4e52fc0a 640 else
20b09c29
AY		 641 hdr_tag = tag;
642
643 hdr->tags = cpu_to_le32(hdr_tag);
644
b5762948
JG		 645 hdr->data_len = cpu_to_le32(task->total_xfer_len);
646
647 /*
648 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
649 */
b5762948 650
8f261aaf
KW		 651 /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
652 buf_cmd = buf_tmp = slot->buf;
b5762948
JG		 653 buf_tmp_dma = slot->buf_dma;
654
655 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
656
657 buf_tmp += MVS_ATA_CMD_SZ;
658 buf_tmp_dma += MVS_ATA_CMD_SZ;
8f261aaf
KW		 659#if _MV_DUMP
660 slot->cmd_size = MVS_ATA_CMD_SZ;
661#endif
b5762948 662
8f261aaf 663 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
b5762948
JG		 664 /* used for STP. unused for SATA? */
665 buf_oaf = buf_tmp;
666 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
667
668 buf_tmp += MVS_OAF_SZ;
669 buf_tmp_dma += MVS_OAF_SZ;
670
8f261aaf 671 /* region 3: PRD table ********************************************* */
b5762948 672 buf_prd = buf_tmp;
20b09c29 673
8f261aaf
KW		 674 if (tei->n_elem)
675 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
676 else
677 hdr->prd_tbl = 0;
20b09c29 678 i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
b5762948 679
b5762948
JG		 680 buf_tmp += i;
681 buf_tmp_dma += i;
682
8f261aaf 683 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
b5762948
JG		 684 /* FIXME: probably unused, for SATA. kept here just in case
685 * we get a STP/SATA error information record
686 */
687 slot->response = buf_tmp;
688 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 689 if (mvi->flags & MVF_FLAG_SOC)
690 hdr->reserved[0] = 0;
b5762948 691
8f261aaf 692 req_len = sizeof(struct host_to_dev_fis);
b5762948 693 resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
8f261aaf 694 sizeof(struct mvs_err_info) - i;
b5762948
JG		 695
696 /* request, response lengths */
8f261aaf 697 resp_len = min(resp_len, max_resp_len);
b5762948
JG		 698 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
699
20b09c29
AY		 700 if (likely(!task->ata_task.device_control_reg_update))
701 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
b5762948 702 /* fill in command FIS and ATAPI CDB */
8f261aaf
KW		 703 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
704 if (dev->sata_dev.command_set == ATAPI_COMMAND_SET)
705 memcpy(buf_cmd + STP_ATAPI_CMD,
706 task->ata_task.atapi_packet, 16);
707
708 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 709 /* initiator, STP, ftype 1h */
710 buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
711 buf_oaf[1] = dev->linkrate & 0xf;
712 *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
713 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
b5762948
JG		 714
715 /* fill in PRD (scatter/gather) table, if any */
20b09c29
AY		 716 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
717#ifndef DISABLE_HOTPLUG_DMA_FIX
718 if (task->data_dir == DMA_FROM_DEVICE)
719 MVS_CHIP_DISP->dma_fix(mvi->bulk_buffer_dma,
720 TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
721#endif
b5762948
JG		 722 return 0;
723}
724
725static int mvs_task_prep_ssp(struct mvs_info *mvi,
20b09c29
AY		 726 struct mvs_task_exec_info *tei, int is_tmf,
727 struct mvs_tmf_task *tmf)
b5762948
JG		 728{
729 struct sas_task *task = tei->task;
b5762948 730 struct mvs_cmd_hdr *hdr = tei->hdr;
8f261aaf 731 struct mvs_port *port = tei->port;
20b09c29 732 struct domain_device *dev = task->dev;
f9da3be5 733 struct mvs_device *mvi_dev = dev->lldd_dev;
20b09c29 734 struct asd_sas_port *sas_port = dev->port;
b5762948 735 struct mvs_slot_info *slot;
20b09c29 736 void *buf_prd;
b5762948
JG		 737 struct ssp_frame_hdr *ssp_hdr;
738 void *buf_tmp;
739 u8 *buf_cmd, *buf_oaf, fburst = 0;
740 dma_addr_t buf_tmp_dma;
741 u32 flags;
8f261aaf
KW		 742 u32 resp_len, req_len, i, tag = tei->tag;
743 const u32 max_resp_len = SB_RFB_MAX;
20b09c29 744 u32 phy_mask;
b5762948
JG		 745
746 slot = &mvi->slot_info[tag];
747
20b09c29
AY		 748 phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
749 sas_port->phy_mask) & TXQ_PHY_MASK;
750
8f261aaf
KW		 751 slot->tx = mvi->tx_prod;
752 mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
753 (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
4e52fc0a 754 (phy_mask << TXQ_PHY_SHIFT));
b5762948
JG		 755
756 flags = MCH_RETRY;
757 if (task->ssp_task.enable_first_burst) {
758 flags |= MCH_FBURST;
759 fburst = (1 << 7);
760 }
2b288133
AY		 761 if (is_tmf)
762 flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
2b288133 763 hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
b5762948
JG		 764 hdr->tags = cpu_to_le32(tag);
765 hdr->data_len = cpu_to_le32(task->total_xfer_len);
766
767 /*
768 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
769 */
b5762948 770
8f261aaf
KW		 771 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
772 buf_cmd = buf_tmp = slot->buf;
b5762948
JG		 773 buf_tmp_dma = slot->buf_dma;
774
775 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
776
777 buf_tmp += MVS_SSP_CMD_SZ;
778 buf_tmp_dma += MVS_SSP_CMD_SZ;
8f261aaf
KW		 779#if _MV_DUMP
780 slot->cmd_size = MVS_SSP_CMD_SZ;
781#endif
b5762948 782
8f261aaf 783 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
b5762948
JG		 784 buf_oaf = buf_tmp;
785 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
786
787 buf_tmp += MVS_OAF_SZ;
788 buf_tmp_dma += MVS_OAF_SZ;
789
8f261aaf 790 /* region 3: PRD table ********************************************* */
b5762948 791 buf_prd = buf_tmp;
8f261aaf
KW		 792 if (tei->n_elem)
793 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
794 else
795 hdr->prd_tbl = 0;
b5762948 796
20b09c29 797 i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
b5762948
JG		 798 buf_tmp += i;
799 buf_tmp_dma += i;
800
8f261aaf 801 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
b5762948
JG		 802 slot->response = buf_tmp;
803 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
20b09c29
AY		 804 if (mvi->flags & MVF_FLAG_SOC)
805 hdr->reserved[0] = 0;
b5762948 806
b5762948 807 resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
8f261aaf
KW		 808 sizeof(struct mvs_err_info) - i;
809 resp_len = min(resp_len, max_resp_len);
810
811 req_len = sizeof(struct ssp_frame_hdr) + 28;
b5762948
JG		 812
813 /* request, response lengths */
814 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
815
816 /* generate open address frame hdr (first 12 bytes) */
20b09c29
AY		 817 /* initiator, SSP, ftype 1h */
818 buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
819 buf_oaf[1] = dev->linkrate & 0xf;
820 *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
821 memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
b5762948 822
8f261aaf
KW		 823 /* fill in SSP frame header (Command Table.SSP frame header) */
824 ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
20b09c29
AY		 825
826 if (is_tmf)
827 ssp_hdr->frame_type = SSP_TASK;
828 else
829 ssp_hdr->frame_type = SSP_COMMAND;
830
831 memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
b5762948
JG		 832 HASHED_SAS_ADDR_SIZE);
833 memcpy(ssp_hdr->hashed_src_addr,
20b09c29 834 dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
b5762948
JG		 835 ssp_hdr->tag = cpu_to_be16(tag);
836
20b09c29 837 /* fill in IU for TASK and Command Frame */
b5762948
JG		 838 buf_cmd += sizeof(*ssp_hdr);
839 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
b5762948 840
20b09c29
AY		 841 if (ssp_hdr->frame_type != SSP_TASK) {
842 buf_cmd[9] = fburst | task->ssp_task.task_attr |
843 (task->ssp_task.task_prio << 3);
844 memcpy(buf_cmd + 12, &task->ssp_task.cdb, 16);
845 } else{
846 buf_cmd[10] = tmf->tmf;
847 switch (tmf->tmf) {
848 case TMF_ABORT_TASK:
849 case TMF_QUERY_TASK:
850 buf_cmd[12] =
851 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
852 buf_cmd[13] =
853 tmf->tag_of_task_to_be_managed & 0xff;
854 break;
855 default:
856 break;
857 }
b5762948 858 }
20b09c29
AY		 859 /* fill in PRD (scatter/gather) table, if any */
860 MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
b5762948
JG		 861 return 0;
862}
863
20b09c29
AY		 864#define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == NO_DEVICE)))
865static int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
0b84b709
AY		 866 struct completion *completion,int is_tmf,
867 struct mvs_tmf_task *tmf)
b5762948 868{
8f261aaf 869 struct domain_device *dev = task->dev;
9870d9a2
AY		 870 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
871 struct mvs_info *mvi = mvi_dev->mvi_info;
b5762948 872 struct mvs_task_exec_info tei;
8f261aaf 873 struct sas_task *t = task;
4e52fc0a 874 struct mvs_slot_info *slot;
8f261aaf 875 u32 tag = 0xdeadbeef, rc, n_elem = 0;
8f261aaf 876 u32 n = num, pass = 0;
9dc9fd94 877 unsigned long flags = 0, flags_libsas = 0;
b5762948 878
20b09c29
AY		 879 if (!dev->port) {
880 struct task_status_struct *tsm = &t->task_status;
881
882 tsm->resp = SAS_TASK_UNDELIVERED;
883 tsm->stat = SAS_PHY_DOWN;
9dc9fd94
S		 884 if (dev->dev_type != SATA_DEV)
885 t->task_done(t);
20b09c29
AY		 886 return 0;
887 }
888
0b84b709 889 spin_lock_irqsave(&mvi->lock, flags);
8f261aaf 890 do {
4e52fc0a 891 dev = t->dev;
f9da3be5 892 mvi_dev = dev->lldd_dev;
20b09c29
AY		 893 if (DEV_IS_GONE(mvi_dev)) {
894 if (mvi_dev)
895 mv_dprintk("device %d not ready.\n",
896 mvi_dev->device_id);
897 else
898 mv_dprintk("device %016llx not ready.\n",
899 SAS_ADDR(dev->sas_addr));
900
901 rc = SAS_PHY_DOWN;
902 goto out_done;
903 }
904
905 if (dev->port->id >= mvi->chip->n_phy)
906 tei.port = &mvi->port[dev->port->id - mvi->chip->n_phy];
907 else
908 tei.port = &mvi->port[dev->port->id];
b5762948 909
9dc9fd94 910 if (tei.port && !tei.port->port_attached) {
dd4969a8 911 if (sas_protocol_ata(t->task_proto)) {
9dc9fd94
S		 912 struct task_status_struct *ts = &t->task_status;
913
20b09c29
AY		 914 mv_dprintk("port %d does not"
915 "attached device.\n", dev->port->id);
9dc9fd94
S		 916 ts->stat = SAS_PROTO_RESPONSE;
917 ts->stat = SAS_PHY_DOWN;
918 spin_unlock_irqrestore(dev->sata_dev.ap->lock,
919 flags_libsas);
920 spin_unlock_irqrestore(&mvi->lock, flags);
921 t->task_done(t);
922 spin_lock_irqsave(&mvi->lock, flags);
923 spin_lock_irqsave(dev->sata_dev.ap->lock,
924 flags_libsas);
925 if (n > 1)
926 t = list_entry(t->list.next,
927 struct sas_task, list);
928 continue;
dd4969a8
JG		 929 } else {
930 struct task_status_struct *ts = &t->task_status;
931 ts->resp = SAS_TASK_UNDELIVERED;
932 ts->stat = SAS_PHY_DOWN;
933 t->task_done(t);
934 if (n > 1)
935 t = list_entry(t->list.next,
936 struct sas_task, list);
937 continue;
938 }
939 }
940
941 if (!sas_protocol_ata(t->task_proto)) {
942 if (t->num_scatter) {
20b09c29
AY		 943 n_elem = dma_map_sg(mvi->dev,
944 t->scatter,
dd4969a8
JG		 945 t->num_scatter,
946 t->data_dir);
947 if (!n_elem) {
948 rc = -ENOMEM;
949 goto err_out;
950 }
951 }
952 } else {
953 n_elem = t->num_scatter;
954 }
955
956 rc = mvs_tag_alloc(mvi, &tag);
957 if (rc)
958 goto err_out;
959
960 slot = &mvi->slot_info[tag];
20b09c29
AY		 961
962
dd4969a8
JG		 963 t->lldd_task = NULL;
964 slot->n_elem = n_elem;
20b09c29 965 slot->slot_tag = tag;
dd4969a8 966 memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
20b09c29 967
dd4969a8
JG		 968 tei.task = t;
969 tei.hdr = &mvi->slot[tag];
970 tei.tag = tag;
971 tei.n_elem = n_elem;
dd4969a8
JG		 972 switch (t->task_proto) {
973 case SAS_PROTOCOL_SMP:
974 rc = mvs_task_prep_smp(mvi, &tei);
975 break;
976 case SAS_PROTOCOL_SSP:
20b09c29 977 rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
dd4969a8
JG		 978 break;
979 case SAS_PROTOCOL_SATA:
980 case SAS_PROTOCOL_STP:
981 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
982 rc = mvs_task_prep_ata(mvi, &tei);
983 break;
984 default:
20b09c29 985 dev_printk(KERN_ERR, mvi->dev,
9dc9fd94
S		 986 "unknown sas_task proto: 0x%x\n",
987 t->task_proto);
dd4969a8
JG		 988 rc = -EINVAL;
989 break;
990 }
991
20b09c29
AY		 992 if (rc) {
993 mv_dprintk("rc is %x\n", rc);
dd4969a8 994 goto err_out_tag;
20b09c29 995 }
dd4969a8
JG		 996 slot->task = t;
997 slot->port = tei.port;
f9da3be5 998 t->lldd_task = slot;
20b09c29 999 list_add_tail(&slot->entry, &tei.port->list);
dd4969a8 1000 /* TODO: select normal or high priority */
dd4969a8
JG		 1001 spin_lock(&t->task_state_lock);
1002 t->task_state_flags |= SAS_TASK_AT_INITIATOR;
1003 spin_unlock(&t->task_state_lock);
1004
1005 mvs_hba_memory_dump(mvi, tag, t->task_proto);
9dc9fd94 1006 mvi_dev->running_req++;
dd4969a8
JG		 1007 ++pass;
1008 mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
1009 if (n > 1)
1010 t = list_entry(t->list.next, struct sas_task, list);
9dc9fd94
S		 1011 if (likely(pass))
1012 MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
1013 (MVS_CHIP_SLOT_SZ - 1));
1014
dd4969a8 1015 } while (--n);
dd4969a8
JG		 1016 rc = 0;
1017 goto out_done;
1018
1019err_out_tag:
1020 mvs_tag_free(mvi, tag);
1021err_out:
20b09c29
AY		 1022
1023 dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
dd4969a8
JG		 1024 if (!sas_protocol_ata(t->task_proto))
1025 if (n_elem)
20b09c29 1026 dma_unmap_sg(mvi->dev, t->scatter, n_elem,
dd4969a8
JG		 1027 t->data_dir);
1028out_done:
0b84b709 1029 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8
JG		 1030 return rc;
1031}
1032
20b09c29
AY		 1033int mvs_queue_command(struct sas_task *task, const int num,
1034 gfp_t gfp_flags)
1035{
0b84b709 1036 return mvs_task_exec(task, num, gfp_flags, NULL, 0, NULL);
20b09c29
AY		 1037}
1038
dd4969a8
JG		 1039static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
1040{
1041 u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
1042 mvs_tag_clear(mvi, slot_idx);
1043}
1044
1045static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
1046 struct mvs_slot_info *slot, u32 slot_idx)
1047{
20b09c29
AY		 1048 if (!slot->task)
1049 return;
dd4969a8
JG		 1050 if (!sas_protocol_ata(task->task_proto))
1051 if (slot->n_elem)
20b09c29 1052 dma_unmap_sg(mvi->dev, task->scatter,
dd4969a8
JG		 1053 slot->n_elem, task->data_dir);
1054
1055 switch (task->task_proto) {
1056 case SAS_PROTOCOL_SMP:
20b09c29 1057 dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
dd4969a8 1058 PCI_DMA_FROMDEVICE);
20b09c29 1059 dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
dd4969a8
JG		 1060 PCI_DMA_TODEVICE);
1061 break;
1062
1063 case SAS_PROTOCOL_SATA:
1064 case SAS_PROTOCOL_STP:
1065 case SAS_PROTOCOL_SSP:
1066 default:
1067 /* do nothing */
1068 break;
1069 }
20b09c29 1070 list_del_init(&slot->entry);
dd4969a8
JG		 1071 task->lldd_task = NULL;
1072 slot->task = NULL;
1073 slot->port = NULL;
20b09c29
AY		 1074 slot->slot_tag = 0xFFFFFFFF;
1075 mvs_slot_free(mvi, slot_idx);
dd4969a8
JG		 1076}
1077
1078static void mvs_update_wideport(struct mvs_info *mvi, int i)
1079{
1080 struct mvs_phy *phy = &mvi->phy[i];
1081 struct mvs_port *port = phy->port;
1082 int j, no;
1083
20b09c29
AY		 1084 for_each_phy(port->wide_port_phymap, j, no) {
1085 if (j & 1) {
1086 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
1087 PHYR_WIDE_PORT);
1088 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
dd4969a8
JG		 1089 port->wide_port_phymap);
1090 } else {
20b09c29
AY		 1091 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
1092 PHYR_WIDE_PORT);
1093 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
1094 0);
dd4969a8 1095 }
20b09c29 1096 }
dd4969a8
JG		 1097}
1098
1099static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
1100{
1101 u32 tmp;
1102 struct mvs_phy *phy = &mvi->phy[i];
20b09c29 1103 struct mvs_port *port = phy->port;
dd4969a8 1104
20b09c29 1105 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
dd4969a8
JG		 1106 if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
1107 if (!port)
1108 phy->phy_attached = 1;
1109 return tmp;
1110 }
1111
1112 if (port) {
1113 if (phy->phy_type & PORT_TYPE_SAS) {
1114 port->wide_port_phymap &= ~(1U << i);
1115 if (!port->wide_port_phymap)
1116 port->port_attached = 0;
1117 mvs_update_wideport(mvi, i);
1118 } else if (phy->phy_type & PORT_TYPE_SATA)
1119 port->port_attached = 0;
dd4969a8
JG		 1120 phy->port = NULL;
1121 phy->phy_attached = 0;
1122 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1123 }
1124 return 0;
1125}
1126
1127static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
1128{
1129 u32 *s = (u32 *) buf;
1130
1131 if (!s)
1132 return NULL;
1133
20b09c29
AY		 1134 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
1135 s[3] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
dd4969a8 1136
20b09c29
AY		 1137 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
1138 s[2] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
dd4969a8 1139
20b09c29
AY		 1140 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
1141 s[1] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
dd4969a8 1142
20b09c29
AY		 1143 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
1144 s[0] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
1145
1146 /* Workaround: take some ATAPI devices for ATA */
1147 if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
1148 s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
dd4969a8 1149
f9da3be5 1150 return s;
dd4969a8
JG		 1151}
1152
1153static u32 mvs_is_sig_fis_received(u32 irq_status)
1154{
1155 return irq_status & PHYEV_SIG_FIS;
1156}
1157
20b09c29 1158void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
dd4969a8
JG		 1159{
1160 struct mvs_phy *phy = &mvi->phy[i];
20b09c29 1161 struct sas_identify_frame *id;
b5762948 1162
20b09c29 1163 id = (struct sas_identify_frame *)phy->frame_rcvd;
b5762948 1164
dd4969a8 1165 if (get_st) {
20b09c29 1166 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
dd4969a8
JG		 1167 phy->phy_status = mvs_is_phy_ready(mvi, i);
1168 }
8f261aaf 1169
dd4969a8 1170 if (phy->phy_status) {
20b09c29
AY		 1171 int oob_done = 0;
1172 struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
b5762948 1173
20b09c29
AY		 1174 oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
1175
1176 MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
1177 if (phy->phy_type & PORT_TYPE_SATA) {
1178 phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
1179 if (mvs_is_sig_fis_received(phy->irq_status)) {
1180 phy->phy_attached = 1;
1181 phy->att_dev_sas_addr =
1182 i + mvi->id * mvi->chip->n_phy;
1183 if (oob_done)
1184 sas_phy->oob_mode = SATA_OOB_MODE;
1185 phy->frame_rcvd_size =
1186 sizeof(struct dev_to_host_fis);
f9da3be5 1187 mvs_get_d2h_reg(mvi, i, id);
20b09c29
AY		 1188 } else {
1189 u32 tmp;
1190 dev_printk(KERN_DEBUG, mvi->dev,
1191 "Phy%d : No sig fis\n", i);
1192 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
1193 MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
1194 tmp | PHYEV_SIG_FIS);
1195 phy->phy_attached = 0;
1196 phy->phy_type &= ~PORT_TYPE_SATA;
1197 MVS_CHIP_DISP->phy_reset(mvi, i, 0);
1198 goto out_done;
1199 }
9dc9fd94 1200 } else if (phy->phy_type & PORT_TYPE_SAS
20b09c29
AY		 1201 || phy->att_dev_info & PORT_SSP_INIT_MASK) {
1202 phy->phy_attached = 1;
dd4969a8 1203 phy->identify.device_type =
20b09c29 1204 phy->att_dev_info & PORT_DEV_TYPE_MASK;
b5762948 1205
dd4969a8
JG		 1206 if (phy->identify.device_type == SAS_END_DEV)
1207 phy->identify.target_port_protocols =
1208 SAS_PROTOCOL_SSP;
1209 else if (phy->identify.device_type != NO_DEVICE)
1210 phy->identify.target_port_protocols =
1211 SAS_PROTOCOL_SMP;
20b09c29 1212 if (oob_done)
dd4969a8
JG		 1213 sas_phy->oob_mode = SAS_OOB_MODE;
1214 phy->frame_rcvd_size =
1215 sizeof(struct sas_identify_frame);
dd4969a8 1216 }
20b09c29
AY		 1217 memcpy(sas_phy->attached_sas_addr,
1218 &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
b5762948 1219
20b09c29
AY		 1220 if (MVS_CHIP_DISP->phy_work_around)
1221 MVS_CHIP_DISP->phy_work_around(mvi, i);
dd4969a8 1222 }
20b09c29
AY		 1223 mv_dprintk("port %d attach dev info is %x\n",
1224 i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
1225 mv_dprintk("port %d attach sas addr is %llx\n",
1226 i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
4e52fc0a 1227out_done:
dd4969a8 1228 if (get_st)
20b09c29 1229 MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
b5762948
JG		 1230}
1231
20b09c29 1232static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
8f261aaf 1233{
dd4969a8 1234 struct sas_ha_struct *sas_ha = sas_phy->ha;
20b09c29 1235 struct mvs_info *mvi = NULL; int i = 0, hi;
dd4969a8 1236 struct mvs_phy *phy = sas_phy->lldd_phy;
20b09c29
AY		 1237 struct asd_sas_port *sas_port = sas_phy->port;
1238 struct mvs_port *port;
1239 unsigned long flags = 0;
1240 if (!sas_port)
1241 return;
8f261aaf 1242
20b09c29
AY		 1243 while (sas_ha->sas_phy[i]) {
1244 if (sas_ha->sas_phy[i] == sas_phy)
1245 break;
1246 i++;
1247 }
1248 hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
1249 mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
1250 if (sas_port->id >= mvi->chip->n_phy)
1251 port = &mvi->port[sas_port->id - mvi->chip->n_phy];
1252 else
1253 port = &mvi->port[sas_port->id];
1254 if (lock)
1255 spin_lock_irqsave(&mvi->lock, flags);
dd4969a8
JG		 1256 port->port_attached = 1;
1257 phy->port = port;
dd4969a8
JG		 1258 if (phy->phy_type & PORT_TYPE_SAS) {
1259 port->wide_port_phymap = sas_port->phy_mask;
20b09c29 1260 mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
dd4969a8 1261 mvs_update_wideport(mvi, sas_phy->id);
8f261aaf 1262 }
20b09c29
AY		 1263 if (lock)
1264 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8
JG		 1265}
1266
20b09c29 1267static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
dd4969a8 1268{
9dc9fd94
S		 1269 struct domain_device *dev;
1270 struct mvs_phy *phy = sas_phy->lldd_phy;
1271 struct mvs_info *mvi = phy->mvi;
1272 struct asd_sas_port *port = sas_phy->port;
1273 int phy_no = 0;
1274
1275 while (phy != &mvi->phy[phy_no]) {
1276 phy_no++;
1277 if (phy_no >= MVS_MAX_PHYS)
1278 return;
1279 }
1280 list_for_each_entry(dev, &port->dev_list, dev_list_node)
1281 mvs_do_release_task(phy->mvi, phy_no, NULL);
1282
dd4969a8
JG		 1283}
1284
dd4969a8 1285
20b09c29
AY		 1286void mvs_port_formed(struct asd_sas_phy *sas_phy)
1287{
1288 mvs_port_notify_formed(sas_phy, 1);
dd4969a8
JG		 1289}
1290
20b09c29 1291void mvs_port_deformed(struct asd_sas_phy *sas_phy)
dd4969a8 1292{
20b09c29
AY		 1293 mvs_port_notify_deformed(sas_phy, 1);
1294}
8f261aaf 1295
20b09c29
AY		 1296struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
1297{
1298 u32 dev;
1299 for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
1300 if (mvi->devices[dev].dev_type == NO_DEVICE) {
1301 mvi->devices[dev].device_id = dev;
1302 return &mvi->devices[dev];
1303 }
8f261aaf 1304 }
8121ed42 1305
20b09c29
AY		 1306 if (dev == MVS_MAX_DEVICES)
1307 mv_printk("max support %d devices, ignore ..\n",
1308 MVS_MAX_DEVICES);
1309
1310 return NULL;
8f261aaf
KW		 1311}
1312
20b09c29 1313void mvs_free_dev(struct mvs_device *mvi_dev)
b5762948 1314{
20b09c29
AY		 1315 u32 id = mvi_dev->device_id;
1316 memset(mvi_dev, 0, sizeof(*mvi_dev));
1317 mvi_dev->device_id = id;
1318 mvi_dev->dev_type = NO_DEVICE;
1319 mvi_dev->dev_status = MVS_DEV_NORMAL;
1320 mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
1321}
b5762948 1322
20b09c29
AY		 1323int mvs_dev_found_notify(struct domain_device *dev, int lock)
1324{
1325 unsigned long flags = 0;
1326 int res = 0;
1327 struct mvs_info *mvi = NULL;
1328 struct domain_device *parent_dev = dev->parent;
1329 struct mvs_device *mvi_device;
b5762948 1330
20b09c29 1331 mvi = mvs_find_dev_mvi(dev);
b5762948 1332
20b09c29
AY		 1333 if (lock)
1334 spin_lock_irqsave(&mvi->lock, flags);
1335
1336 mvi_device = mvs_alloc_dev(mvi);
1337 if (!mvi_device) {
1338 res = -1;
1339 goto found_out;
b5762948 1340 }
f9da3be5 1341 dev->lldd_dev = mvi_device;
9dc9fd94 1342 mvi_device->dev_status = MVS_DEV_NORMAL;
20b09c29 1343 mvi_device->dev_type = dev->dev_type;
9870d9a2 1344 mvi_device->mvi_info = mvi;
20b09c29
AY		 1345 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
1346 int phy_id;
1347 u8 phy_num = parent_dev->ex_dev.num_phys;
1348 struct ex_phy *phy;
1349 for (phy_id = 0; phy_id < phy_num; phy_id++) {
1350 phy = &parent_dev->ex_dev.ex_phy[phy_id];
1351 if (SAS_ADDR(phy->attached_sas_addr) ==
1352 SAS_ADDR(dev->sas_addr)) {
1353 mvi_device->attached_phy = phy_id;
1354 break;
1355 }
1356 }
b5762948 1357
20b09c29
AY		 1358 if (phy_id == phy_num) {
1359 mv_printk("Error: no attached dev:%016llx"
1360 "at ex:%016llx.\n",
1361 SAS_ADDR(dev->sas_addr),
1362 SAS_ADDR(parent_dev->sas_addr));
1363 res = -1;
1364 }
dd4969a8 1365 }
b5762948 1366
20b09c29
AY		 1367found_out:
1368 if (lock)
1369 spin_unlock_irqrestore(&mvi->lock, flags);
1370 return res;
1371}
b5762948 1372
20b09c29
AY		 1373int mvs_dev_found(struct domain_device *dev)
1374{
1375 return mvs_dev_found_notify(dev, 1);
1376}
b5762948 1377
9dc9fd94 1378void mvs_dev_gone_notify(struct domain_device *dev)
20b09c29
AY		 1379{
1380 unsigned long flags = 0;
f9da3be5 1381 struct mvs_device *mvi_dev = dev->lldd_dev;
9870d9a2 1382 struct mvs_info *mvi = mvi_dev->mvi_info;
b5762948 1383
9dc9fd94 1384 spin_lock_irqsave(&mvi->lock, flags);
b5762948 1385
20b09c29
AY		 1386 if (mvi_dev) {
1387 mv_dprintk("found dev[%d:%x] is gone.\n",
1388 mvi_dev->device_id, mvi_dev->dev_type);
9dc9fd94 1389 mvs_release_task(mvi, dev);
20b09c29
AY		 1390 mvs_free_reg_set(mvi, mvi_dev);
1391 mvs_free_dev(mvi_dev);
1392 } else {
1393 mv_dprintk("found dev has gone.\n");
b5762948 1394 }
20b09c29 1395 dev->lldd_dev = NULL;
b5762948 1396
9dc9fd94 1397 spin_unlock_irqrestore(&mvi->lock, flags);
b5762948
JG		 1398}
1399
b5762948 1400
20b09c29
AY		 1401void mvs_dev_gone(struct domain_device *dev)
1402{
9dc9fd94 1403 mvs_dev_gone_notify(dev);
20b09c29 1404}
b5762948 1405
20b09c29
AY		 1406static struct sas_task *mvs_alloc_task(void)
1407{
1408 struct sas_task *task = kzalloc(sizeof(struct sas_task), GFP_KERNEL);
1409
1410 if (task) {
1411 INIT_LIST_HEAD(&task->list);
1412 spin_lock_init(&task->task_state_lock);
1413 task->task_state_flags = SAS_TASK_STATE_PENDING;
1414 init_timer(&task->timer);
1415 init_completion(&task->completion);
b5762948 1416 }
20b09c29 1417 return task;
dd4969a8 1418}
b5762948 1419
20b09c29 1420static void mvs_free_task(struct sas_task *task)
dd4969a8 1421{
20b09c29
AY		 1422 if (task) {
1423 BUG_ON(!list_empty(&task->list));
1424 kfree(task);
b5762948 1425 }
20b09c29 1426}
b5762948 1427
20b09c29
AY		 1428static void mvs_task_done(struct sas_task *task)
1429{
1430 if (!del_timer(&task->timer))
1431 return;
1432 complete(&task->completion);
b5762948 1433}
b5762948 1434
20b09c29 1435static void mvs_tmf_timedout(unsigned long data)
b5762948 1436{
20b09c29 1437 struct sas_task *task = (struct sas_task *)data;
8f261aaf 1438
20b09c29
AY		 1439 task->task_state_flags |= SAS_TASK_STATE_ABORTED;
1440 complete(&task->completion);
1441}
8f261aaf 1442
20b09c29
AY		 1443/* XXX */
1444#define MVS_TASK_TIMEOUT 20
1445static int mvs_exec_internal_tmf_task(struct domain_device *dev,
1446 void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
1447{
1448 int res, retry;
1449 struct sas_task *task = NULL;
8f261aaf 1450
20b09c29
AY		 1451 for (retry = 0; retry < 3; retry++) {
1452 task = mvs_alloc_task();
1453 if (!task)
1454 return -ENOMEM;
8f261aaf 1455
20b09c29
AY		 1456 task->dev = dev;
1457 task->task_proto = dev->tproto;
8f261aaf 1458
20b09c29
AY		 1459 memcpy(&task->ssp_task, parameter, para_len);
1460 task->task_done = mvs_task_done;
8f261aaf 1461
20b09c29
AY		 1462 task->timer.data = (unsigned long) task;
1463 task->timer.function = mvs_tmf_timedout;
1464 task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
1465 add_timer(&task->timer);
8f261aaf 1466
0b84b709 1467 res = mvs_task_exec(task, 1, GFP_KERNEL, NULL, 1, tmf);
8f261aaf 1468
20b09c29
AY		 1469 if (res) {
1470 del_timer(&task->timer);
1471 mv_printk("executing internel task failed:%d\n", res);
1472 goto ex_err;
1473 }
8f261aaf 1474
20b09c29
AY		 1475 wait_for_completion(&task->completion);
1476 res = -TMF_RESP_FUNC_FAILED;
1477 /* Even TMF timed out, return direct. */
1478 if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1479 if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
1480 mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
1481 goto ex_err;
1482 }
1483 }
8f261aaf 1484
20b09c29
AY		 1485 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1486 task->task_status.stat == SAM_GOOD) {
1487 res = TMF_RESP_FUNC_COMPLETE;
1488 break;
1489 }
b5762948 1490
20b09c29
AY		 1491 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1492 task->task_status.stat == SAS_DATA_UNDERRUN) {
1493 /* no error, but return the number of bytes of
1494 * underrun */
1495 res = task->task_status.residual;
1496 break;
1497 }
b5762948 1498
20b09c29
AY		 1499 if (task->task_status.resp == SAS_TASK_COMPLETE &&
1500 task->task_status.stat == SAS_DATA_OVERRUN) {
1501 mv_dprintk("blocked task error.\n");
1502 res = -EMSGSIZE;
1503 break;
1504 } else {
1505 mv_dprintk(" task to dev %016llx response: 0x%x "
1506 "status 0x%x\n",
1507 SAS_ADDR(dev->sas_addr),
1508 task->task_status.resp,
1509 task->task_status.stat);
1510 mvs_free_task(task);
1511 task = NULL;
b5762948 1512
dd4969a8 1513 }
dd4969a8 1514 }
20b09c29
AY		 1515ex_err:
1516 BUG_ON(retry == 3 && task != NULL);
1517 if (task != NULL)
1518 mvs_free_task(task);
1519 return res;
dd4969a8 1520}
b5762948 1521
20b09c29
AY		 1522static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
1523 u8 *lun, struct mvs_tmf_task *tmf)
dd4969a8 1524{
20b09c29
AY		 1525 struct sas_ssp_task ssp_task;
1526 DECLARE_COMPLETION_ONSTACK(completion);
1527 if (!(dev->tproto & SAS_PROTOCOL_SSP))
1528 return TMF_RESP_FUNC_ESUPP;
b5762948 1529
20b09c29 1530 strncpy((u8 *)&ssp_task.LUN, lun, 8);
b5762948 1531
20b09c29
AY		 1532 return mvs_exec_internal_tmf_task(dev, &ssp_task,
1533 sizeof(ssp_task), tmf);
1534}
8f261aaf 1535
8f261aaf 1536
20b09c29
AY		 1537/* Standard mandates link reset for ATA (type 0)
1538 and hard reset for SSP (type 1) , only for RECOVERY */
1539static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
1540{
1541 int rc;
1542 struct sas_phy *phy = sas_find_local_phy(dev);
1543 int reset_type = (dev->dev_type == SATA_DEV ||
1544 (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
1545 rc = sas_phy_reset(phy, reset_type);
1546 msleep(2000);
1547 return rc;
1548}
8f261aaf 1549
20b09c29
AY		 1550/* mandatory SAM-3 */
1551int mvs_lu_reset(struct domain_device *dev, u8 *lun)
1552{
1553 unsigned long flags;
1554 int i, phyno[WIDE_PORT_MAX_PHY], num , rc = TMF_RESP_FUNC_FAILED;
1555 struct mvs_tmf_task tmf_task;
f9da3be5 1556 struct mvs_device * mvi_dev = dev->lldd_dev;
9870d9a2 1557 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 1558
1559 tmf_task.tmf = TMF_LU_RESET;
1560 mvi_dev->dev_status = MVS_DEV_EH;
1561 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
1562 if (rc == TMF_RESP_FUNC_COMPLETE) {
1563 num = mvs_find_dev_phyno(dev, phyno);
1564 spin_lock_irqsave(&mvi->lock, flags);
1565 for (i = 0; i < num; i++)
9dc9fd94 1566 mvs_release_task(mvi, dev);
20b09c29 1567 spin_unlock_irqrestore(&mvi->lock, flags);
dd4969a8 1568 }
20b09c29
AY		 1569 /* If failed, fall-through I_T_Nexus reset */
1570 mv_printk("%s for device[%x]:rc= %d\n", __func__,
1571 mvi_dev->device_id, rc);
1572 return rc;
1573}
8f261aaf 1574
20b09c29
AY		 1575int mvs_I_T_nexus_reset(struct domain_device *dev)
1576{
1577 unsigned long flags;
9dc9fd94
S		 1578 int rc = TMF_RESP_FUNC_FAILED;
1579 struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
9870d9a2 1580 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 1581
1582 if (mvi_dev->dev_status != MVS_DEV_EH)
1583 return TMF_RESP_FUNC_COMPLETE;
1584 rc = mvs_debug_I_T_nexus_reset(dev);
1585 mv_printk("%s for device[%x]:rc= %d\n",
1586 __func__, mvi_dev->device_id, rc);
1587
1588 /* housekeeper */
20b09c29 1589 spin_lock_irqsave(&mvi->lock, flags);
9dc9fd94 1590 mvs_release_task(mvi, dev);
20b09c29
AY		 1591 spin_unlock_irqrestore(&mvi->lock, flags);
1592
1593 return rc;
1594}
1595/* optional SAM-3 */
1596int mvs_query_task(struct sas_task *task)
1597{
1598 u32 tag;
1599 struct scsi_lun lun;
1600 struct mvs_tmf_task tmf_task;
1601 int rc = TMF_RESP_FUNC_FAILED;
1602
1603 if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
1604 struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
1605 struct domain_device *dev = task->dev;
9870d9a2
AY		 1606 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
1607 struct mvs_info *mvi = mvi_dev->mvi_info;
20b09c29
AY		 1608
1609 int_to_scsilun(cmnd->device->lun, &lun);
1610 rc = mvs_find_tag(mvi, task, &tag);
1611 if (rc == 0) {
1612 rc = TMF_RESP_FUNC_FAILED;
dd4969a8 1613 return rc;
20b09c29 1614 }
8f261aaf 1615
20b09c29
AY		 1616 tmf_task.tmf = TMF_QUERY_TASK;
1617 tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
8f261aaf 1618
20b09c29
AY		 1619 rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
1620 switch (rc) {
1621 /* The task is still in Lun, release it then */
1622 case TMF_RESP_FUNC_SUCC:
1623 /* The task is not in Lun or failed, reset the phy */
1624 case TMF_RESP_FUNC_FAILED:
1625 case TMF_RESP_FUNC_COMPLETE:
1626 break;
9dc9fd94
S		 1627 default:
1628 rc = TMF_RESP_FUNC_COMPLETE;
1629 break;
20b09c29 1630 }
dd4969a8 1631 }
20b09c29
AY		 1632 mv_printk("%s:rc= %d\n", __func__, rc);
1633 return rc;
8f261aaf
KW		 1634}
1635
20b09c29
AY		 1636/* mandatory SAM-3, still need free task/slot info */
1637int mvs_abort_task(struct sas_task *task)
8f261aaf 1638{
20b09c29
AY		 1639 struct scsi_lun lun;
1640 struct mvs_tmf_task tmf_task;
1641 struct domain_device *dev = task->dev;
9870d9a2 1642 struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
24ae163e 1643 struct mvs_info *mvi;
20b09c29
AY		 1644 int rc = TMF_RESP_FUNC_FAILED;
1645 unsigned long flags;
1646 u32 tag;
9870d9a2 1647
9dc9fd94
S		 1648 if (!mvi_dev) {
1649 mv_printk("%s:%d TMF_RESP_FUNC_FAILED\n", __func__, __LINE__);
1650 rc = TMF_RESP_FUNC_FAILED;
1651 }
1652
24ae163e
JS		 1653 mvi = mvi_dev->mvi_info;
1654
20b09c29
AY		 1655 spin_lock_irqsave(&task->task_state_lock, flags);
1656 if (task->task_state_flags & SAS_TASK_STATE_DONE) {
1657 spin_unlock_irqrestore(&task->task_state_lock, flags);
1658 rc = TMF_RESP_FUNC_COMPLETE;
1659 goto out;
dd4969a8 1660 }
20b09c29 1661 spin_unlock_irqrestore(&task->task_state_lock, flags);
9dc9fd94 1662 mvi_dev->dev_status = MVS_DEV_EH;
20b09c29
AY		 1663 if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
1664 struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
1665
1666 int_to_scsilun(cmnd->device->lun, &lun);
1667 rc = mvs_find_tag(mvi, task, &tag);
1668 if (rc == 0) {
1669 mv_printk("No such tag in %s\n", __func__);
1670 rc = TMF_RESP_FUNC_FAILED;
1671 return rc;
1672 }
8f261aaf 1673
20b09c29
AY		 1674 tmf_task.tmf = TMF_ABORT_TASK;
1675 tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
8f261aaf 1676
20b09c29 1677 rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
8f261aaf 1678
20b09c29
AY		 1679 /* if successful, clear the task and callback forwards.*/
1680 if (rc == TMF_RESP_FUNC_COMPLETE) {
1681 u32 slot_no;
1682 struct mvs_slot_info *slot;
8f261aaf 1683
20b09c29 1684 if (task->lldd_task) {
f9da3be5 1685 slot = task->lldd_task;
20b09c29 1686 slot_no = (u32) (slot - mvi->slot_info);
9dc9fd94 1687 spin_lock_irqsave(&mvi->lock, flags);
20b09c29 1688 mvs_slot_complete(mvi, slot_no, 1);
9dc9fd94 1689 spin_unlock_irqrestore(&mvi->lock, flags);
20b09c29
AY		 1690 }
1691 }
9dc9fd94 1692
20b09c29
AY		 1693 } else if (task->task_proto & SAS_PROTOCOL_SATA ||
1694 task->task_proto & SAS_PROTOCOL_STP) {
1695 /* to do free register_set */
9dc9fd94
S		 1696 if (SATA_DEV == dev->dev_type) {
1697 struct mvs_slot_info *slot = task->lldd_task;
1698 struct task_status_struct *tstat;
1699 u32 slot_idx = (u32)(slot - mvi->slot_info);
1700 tstat = &task->task_status;
1701 mv_dprintk(KERN_DEBUG "mv_abort_task() mvi=%p task=%p "
1702 "slot=%p slot_idx=x%x\n",
1703 mvi, task, slot, slot_idx);
1704 tstat->stat = SAS_ABORTED_TASK;
1705 if (mvi_dev && mvi_dev->running_req)
1706 mvi_dev->running_req--;
1707 if (sas_protocol_ata(task->task_proto))
1708 mvs_free_reg_set(mvi, mvi_dev);
1709 mvs_slot_task_free(mvi, task, slot, slot_idx);
1710 return -1;
1711 }
20b09c29
AY		 1712 } else {
1713 /* SMP */
8f261aaf 1714
20b09c29
AY		 1715 }
1716out:
1717 if (rc != TMF_RESP_FUNC_COMPLETE)
1718 mv_printk("%s:rc= %d\n", __func__, rc);
dd4969a8 1719 return rc;
8f261aaf
KW		 1720}
1721
20b09c29 1722int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
8f261aaf 1723{
20b09c29
AY		 1724 int rc = TMF_RESP_FUNC_FAILED;
1725 struct mvs_tmf_task tmf_task;
8f261aaf 1726
20b09c29
AY		 1727 tmf_task.tmf = TMF_ABORT_TASK_SET;
1728 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
dd4969a8 1729
20b09c29 1730 return rc;
8f261aaf
KW		 1731}
1732
20b09c29 1733int mvs_clear_aca(struct domain_device *dev, u8 *lun)
8f261aaf 1734{
20b09c29
AY		 1735 int rc = TMF_RESP_FUNC_FAILED;
1736 struct mvs_tmf_task tmf_task;
8f261aaf 1737
20b09c29
AY		 1738 tmf_task.tmf = TMF_CLEAR_ACA;
1739 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
8f261aaf 1740
20b09c29
AY		 1741 return rc;
1742}
8f261aaf 1743
20b09c29
AY		 1744int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
1745{
1746 int rc = TMF_RESP_FUNC_FAILED;
1747 struct mvs_tmf_task tmf_task;
8f261aaf 1748
20b09c29
AY		 1749 tmf_task.tmf = TMF_CLEAR_TASK_SET;
1750 rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
8f261aaf 1751
20b09c29 1752 return rc;
dd4969a8 1753}
8f261aaf 1754
20b09c29
AY		 1755static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
1756 u32 slot_idx, int err)
dd4969a8 1757{
f9da3be5 1758 struct mvs_device *mvi_dev = task->dev->lldd_dev;
20b09c29
AY		 1759 struct task_status_struct *tstat = &task->task_status;
1760 struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
1761 int stat = SAM_GOOD;
e9ff91b6 1762
8f261aaf 1763
20b09c29
AY		 1764 resp->frame_len = sizeof(struct dev_to_host_fis);
1765 memcpy(&resp->ending_fis[0],
1766 SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
1767 sizeof(struct dev_to_host_fis));
1768 tstat->buf_valid_size = sizeof(*resp);
9dc9fd94
S		 1769 if (unlikely(err)) {
1770 if (unlikely(err & CMD_ISS_STPD))
1771 stat = SAS_OPEN_REJECT;
1772 else
1773 stat = SAS_PROTO_RESPONSE;
1774 }
1775
20b09c29 1776 return stat;
8f261aaf
KW		 1777}
1778
20b09c29
AY		 1779static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
1780 u32 slot_idx)
8f261aaf 1781{
20b09c29
AY		 1782 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1783 int stat;
1784 u32 err_dw0 = le32_to_cpu(*(u32 *) (slot->response));
1785 u32 tfs = 0;
1786 enum mvs_port_type type = PORT_TYPE_SAS;
8f261aaf 1787
20b09c29
AY		 1788 if (err_dw0 & CMD_ISS_STPD)
1789 MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
1790
1791 MVS_CHIP_DISP->command_active(mvi, slot_idx);
b5762948 1792
20b09c29 1793 stat = SAM_CHECK_COND;
dd4969a8 1794 switch (task->task_proto) {
dd4969a8 1795 case SAS_PROTOCOL_SSP:
20b09c29
AY		 1796 stat = SAS_ABORTED_TASK;
1797 break;
1798 case SAS_PROTOCOL_SMP:
1799 stat = SAM_CHECK_COND;
dd4969a8 1800 break;
20b09c29 1801
dd4969a8
JG		 1802 case SAS_PROTOCOL_SATA:
1803 case SAS_PROTOCOL_STP:
20b09c29
AY		 1804 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1805 {
1806 if (err_dw0 == 0x80400002)
1807 mv_printk("find reserved error, why?\n");
1808
1809 task->ata_task.use_ncq = 0;
9dc9fd94 1810 mvs_sata_done(mvi, task, slot_idx, err_dw0);
dd4969a8 1811 }
20b09c29 1812 break;
dd4969a8
JG		 1813 default:
1814 break;
1815 }
1816
20b09c29 1817 return stat;
e9ff91b6
KW		 1818}
1819
20b09c29 1820int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
b5762948 1821{
20b09c29
AY		 1822 u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
1823 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1824 struct sas_task *task = slot->task;
1825 struct mvs_device *mvi_dev = NULL;
1826 struct task_status_struct *tstat;
9dc9fd94
S		 1827 struct domain_device *dev;
1828 u32 aborted;
20b09c29 1829
20b09c29
AY		 1830 void *to;
1831 enum exec_status sts;
1832
1833 if (mvi->exp_req)
1834 mvi->exp_req--;
9dc9fd94 1835 if (unlikely(!task || !task->lldd_task || !task->dev))
20b09c29
AY		 1836 return -1;
1837
1838 tstat = &task->task_status;
9dc9fd94
S		 1839 dev = task->dev;
1840 mvi_dev = dev->lldd_dev;
b5762948 1841
20b09c29
AY		 1842 mvs_hba_cq_dump(mvi);
1843
1844 spin_lock(&task->task_state_lock);
1845 task->task_state_flags &=
1846 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1847 task->task_state_flags |= SAS_TASK_STATE_DONE;
1848 /* race condition*/
1849 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1850 spin_unlock(&task->task_state_lock);
1851
1852 memset(tstat, 0, sizeof(*tstat));
1853 tstat->resp = SAS_TASK_COMPLETE;
1854
1855 if (unlikely(aborted)) {
1856 tstat->stat = SAS_ABORTED_TASK;
9dc9fd94
S		 1857 if (mvi_dev && mvi_dev->running_req)
1858 mvi_dev->running_req--;
20b09c29
AY		 1859 if (sas_protocol_ata(task->task_proto))
1860 mvs_free_reg_set(mvi, mvi_dev);
1861
1862 mvs_slot_task_free(mvi, task, slot, slot_idx);
1863 return -1;
b5762948
JG		 1864 }
1865
9dc9fd94
S		 1866 if (unlikely(!mvi_dev || flags)) {
1867 if (!mvi_dev)
1868 mv_dprintk("port has not device.\n");
20b09c29
AY		 1869 tstat->stat = SAS_PHY_DOWN;
1870 goto out;
1871 }
b5762948 1872
20b09c29
AY		 1873 /* error info record present */
1874 if (unlikely((rx_desc & RXQ_ERR) && (*(u64 *) slot->response))) {
1875 tstat->stat = mvs_slot_err(mvi, task, slot_idx);
9dc9fd94 1876 tstat->resp = SAS_TASK_COMPLETE;
20b09c29 1877 goto out;
b5762948
JG		 1878 }
1879
20b09c29
AY		 1880 switch (task->task_proto) {
1881 case SAS_PROTOCOL_SSP:
1882 /* hw says status == 0, datapres == 0 */
1883 if (rx_desc & RXQ_GOOD) {
1884 tstat->stat = SAM_GOOD;
1885 tstat->resp = SAS_TASK_COMPLETE;
1886 }
1887 /* response frame present */
1888 else if (rx_desc & RXQ_RSP) {
1889 struct ssp_response_iu *iu = slot->response +
1890 sizeof(struct mvs_err_info);
1891 sas_ssp_task_response(mvi->dev, task, iu);
1892 } else
1893 tstat->stat = SAM_CHECK_COND;
1894 break;
b5762948 1895
20b09c29
AY		 1896 case SAS_PROTOCOL_SMP: {
1897 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1898 tstat->stat = SAM_GOOD;
1899 to = kmap_atomic(sg_page(sg_resp), KM_IRQ0);
1900 memcpy(to + sg_resp->offset,
1901 slot->response + sizeof(struct mvs_err_info),
1902 sg_dma_len(sg_resp));
1903 kunmap_atomic(to, KM_IRQ0);
1904 break;
1905 }
8f261aaf 1906
20b09c29
AY		 1907 case SAS_PROTOCOL_SATA:
1908 case SAS_PROTOCOL_STP:
1909 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
1910 tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
1911 break;
1912 }
b5762948 1913
20b09c29
AY		 1914 default:
1915 tstat->stat = SAM_CHECK_COND;
1916 break;
1917 }
9dc9fd94
S		 1918 if (!slot->port->port_attached) {
1919 mv_dprintk("port %d has removed.\n", slot->port->sas_port.id);
1920 tstat->stat = SAS_PHY_DOWN;
1921 }
1922
b5762948 1923
20b09c29 1924out:
9dc9fd94
S		 1925 if (mvi_dev && mvi_dev->running_req) {
1926 mvi_dev->running_req--;
1927 if (sas_protocol_ata(task->task_proto) && !mvi_dev->running_req)
0f980a87
AY		 1928 mvs_free_reg_set(mvi, mvi_dev);
1929 }
20b09c29
AY		 1930 mvs_slot_task_free(mvi, task, slot, slot_idx);
1931 sts = tstat->stat;
8f261aaf 1932
20b09c29
AY		 1933 spin_unlock(&mvi->lock);
1934 if (task->task_done)
1935 task->task_done(task);
1936 else
1937 mv_dprintk("why has not task_done.\n");
1938 spin_lock(&mvi->lock);
b5762948 1939
20b09c29
AY		 1940 return sts;
1941}
b5762948 1942
9dc9fd94 1943void mvs_do_release_task(struct mvs_info *mvi,
20b09c29
AY		 1944 int phy_no, struct domain_device *dev)
1945{
9dc9fd94 1946 u32 slot_idx;
20b09c29
AY		 1947 struct mvs_phy *phy;
1948 struct mvs_port *port;
1949 struct mvs_slot_info *slot, *slot2;
b5762948 1950
20b09c29
AY		 1951 phy = &mvi->phy[phy_no];
1952 port = phy->port;
1953 if (!port)
1954 return;
9dc9fd94
S		 1955 /* clean cmpl queue in case request is already finished */
1956 mvs_int_rx(mvi, false);
1957
1958
b5762948 1959
20b09c29
AY		 1960 list_for_each_entry_safe(slot, slot2, &port->list, entry) {
1961 struct sas_task *task;
1962 slot_idx = (u32) (slot - mvi->slot_info);
1963 task = slot->task;
b5762948 1964
20b09c29
AY		 1965 if (dev && task->dev != dev)
1966 continue;
8f261aaf 1967
20b09c29
AY		 1968 mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
1969 slot_idx, slot->slot_tag, task);
9dc9fd94 1970 MVS_CHIP_DISP->command_active(mvi, slot_idx);
b5762948 1971
20b09c29 1972 mvs_slot_complete(mvi, slot_idx, 1);
b5762948 1973 }
20b09c29 1974}
b5762948 1975
9dc9fd94
S		 1976void mvs_release_task(struct mvs_info *mvi,
1977 struct domain_device *dev)
1978{
1979 int i, phyno[WIDE_PORT_MAX_PHY], num;
1980 /* housekeeper */
1981 num = mvs_find_dev_phyno(dev, phyno);
1982 for (i = 0; i < num; i++)
1983 mvs_do_release_task(mvi, phyno[i], dev);
1984}
1985
20b09c29
AY		 1986static void mvs_phy_disconnected(struct mvs_phy *phy)
1987{
1988 phy->phy_attached = 0;
1989 phy->att_dev_info = 0;
1990 phy->att_dev_sas_addr = 0;
1991}
1992
1993static void mvs_work_queue(struct work_struct *work)
1994{
1995 struct delayed_work *dw = container_of(work, struct delayed_work, work);
1996 struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
1997 struct mvs_info *mvi = mwq->mvi;
1998 unsigned long flags;
b5762948 1999
20b09c29
AY		 2000 spin_lock_irqsave(&mvi->lock, flags);
2001 if (mwq->handler & PHY_PLUG_EVENT) {
2002 u32 phy_no = (unsigned long) mwq->data;
2003 struct sas_ha_struct *sas_ha = mvi->sas;
2004 struct mvs_phy *phy = &mvi->phy[phy_no];
2005 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2006
2007 if (phy->phy_event & PHY_PLUG_OUT) {
2008 u32 tmp;
2009 struct sas_identify_frame *id;
2010 id = (struct sas_identify_frame *)phy->frame_rcvd;
2011 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
2012 phy->phy_event &= ~PHY_PLUG_OUT;
2013 if (!(tmp & PHY_READY_MASK)) {
2014 sas_phy_disconnected(sas_phy);
2015 mvs_phy_disconnected(phy);
2016 sas_ha->notify_phy_event(sas_phy,
2017 PHYE_LOSS_OF_SIGNAL);
2018 mv_dprintk("phy%d Removed Device\n", phy_no);
2019 } else {
2020 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
2021 mvs_update_phyinfo(mvi, phy_no, 1);
2022 mvs_bytes_dmaed(mvi, phy_no);
2023 mvs_port_notify_formed(sas_phy, 0);
2024 mv_dprintk("phy%d Attached Device\n", phy_no);
2025 }
2026 }
2027 }
2028 list_del(&mwq->entry);
2029 spin_unlock_irqrestore(&mvi->lock, flags);
2030 kfree(mwq);
2031}
8f261aaf 2032
20b09c29
AY		 2033static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
2034{
2035 struct mvs_wq *mwq;
2036 int ret = 0;
2037
2038 mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
2039 if (mwq) {
2040 mwq->mvi = mvi;
2041 mwq->data = data;
2042 mwq->handler = handler;
2043 MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
2044 list_add_tail(&mwq->entry, &mvi->wq_list);
2045 schedule_delayed_work(&mwq->work_q, HZ * 2);
2046 } else
2047 ret = -ENOMEM;
2048
2049 return ret;
2050}
b5762948 2051
20b09c29
AY		 2052static void mvs_sig_time_out(unsigned long tphy)
2053{
2054 struct mvs_phy *phy = (struct mvs_phy *)tphy;
2055 struct mvs_info *mvi = phy->mvi;
2056 u8 phy_no;
2057
2058 for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
2059 if (&mvi->phy[phy_no] == phy) {
2060 mv_dprintk("Get signature time out, reset phy %d\n",
2061 phy_no+mvi->id*mvi->chip->n_phy);
2062 MVS_CHIP_DISP->phy_reset(mvi, phy_no, 1);
2063 }
b5762948 2064 }
20b09c29 2065}
b5762948 2066
20b09c29
AY		 2067static void mvs_sig_remove_timer(struct mvs_phy *phy)
2068{
2069 if (phy->timer.function)
2070 del_timer(&phy->timer);
2071 phy->timer.function = NULL;
2072}
b5762948 2073
20b09c29
AY		 2074void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
2075{
2076 u32 tmp;
2077 struct sas_ha_struct *sas_ha = mvi->sas;
2078 struct mvs_phy *phy = &mvi->phy[phy_no];
2079 struct asd_sas_phy *sas_phy = &phy->sas_phy;
8f261aaf 2080
20b09c29
AY		 2081 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
2082 mv_dprintk("port %d ctrl sts=0x%X.\n", phy_no+mvi->id*mvi->chip->n_phy,
2083 MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
2084 mv_dprintk("Port %d irq sts = 0x%X\n", phy_no+mvi->id*mvi->chip->n_phy,
2085 phy->irq_status);
8f261aaf 2086
20b09c29
AY		 2087 /*
2088 * events is port event now ,
2089 * we need check the interrupt status which belongs to per port.
2090 */
b5762948 2091
9dc9fd94 2092 if (phy->irq_status & PHYEV_DCDR_ERR) {
20b09c29 2093 mv_dprintk("port %d STP decoding error.\n",
9dc9fd94
S		 2094 phy_no + mvi->id*mvi->chip->n_phy);
2095 }
20b09c29
AY		 2096
2097 if (phy->irq_status & PHYEV_POOF) {
2098 if (!(phy->phy_event & PHY_PLUG_OUT)) {
2099 int dev_sata = phy->phy_type & PORT_TYPE_SATA;
2100 int ready;
9dc9fd94 2101 mvs_do_release_task(mvi, phy_no, NULL);
20b09c29 2102 phy->phy_event |= PHY_PLUG_OUT;
9dc9fd94 2103 MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
20b09c29
AY		 2104 mvs_handle_event(mvi,
2105 (void *)(unsigned long)phy_no,
2106 PHY_PLUG_EVENT);
2107 ready = mvs_is_phy_ready(mvi, phy_no);
2108 if (!ready)
2109 mv_dprintk("phy%d Unplug Notice\n",
2110 phy_no +
2111 mvi->id * mvi->chip->n_phy);
2112 if (ready || dev_sata) {
2113 if (MVS_CHIP_DISP->stp_reset)
2114 MVS_CHIP_DISP->stp_reset(mvi,
2115 phy_no);
2116 else
2117 MVS_CHIP_DISP->phy_reset(mvi,
2118 phy_no, 0);
2119 return;
2120 }
2121 }
2122 }
b5762948 2123
20b09c29
AY		 2124 if (phy->irq_status & PHYEV_COMWAKE) {
2125 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
2126 MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
2127 tmp | PHYEV_SIG_FIS);
2128 if (phy->timer.function == NULL) {
2129 phy->timer.data = (unsigned long)phy;
2130 phy->timer.function = mvs_sig_time_out;
2131 phy->timer.expires = jiffies + 10*HZ;
2132 add_timer(&phy->timer);
2133 }
2134 }
2135 if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
2136 phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
2137 mvs_sig_remove_timer(phy);
2138 mv_dprintk("notify plug in on phy[%d]\n", phy_no);
2139 if (phy->phy_status) {
2140 mdelay(10);
2141 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
2142 if (phy->phy_type & PORT_TYPE_SATA) {
2143 tmp = MVS_CHIP_DISP->read_port_irq_mask(
2144 mvi, phy_no);
2145 tmp &= ~PHYEV_SIG_FIS;
2146 MVS_CHIP_DISP->write_port_irq_mask(mvi,
2147 phy_no, tmp);
2148 }
2149 mvs_update_phyinfo(mvi, phy_no, 0);
9dc9fd94
S		 2150 if (phy->phy_type & PORT_TYPE_SAS) {
2151 MVS_CHIP_DISP->phy_reset(mvi, phy_no, 2);
2152 mdelay(10);
2153 }
2154
20b09c29
AY		 2155 mvs_bytes_dmaed(mvi, phy_no);
2156 /* whether driver is going to handle hot plug */
2157 if (phy->phy_event & PHY_PLUG_OUT) {
2158 mvs_port_notify_formed(sas_phy, 0);
2159 phy->phy_event &= ~PHY_PLUG_OUT;
2160 }
2161 } else {
2162 mv_dprintk("plugin interrupt but phy%d is gone\n",
2163 phy_no + mvi->id*mvi->chip->n_phy);
2164 }
2165 } else if (phy->irq_status & PHYEV_BROAD_CH) {
2166 mv_dprintk("port %d broadcast change.\n",
2167 phy_no + mvi->id*mvi->chip->n_phy);
2168 /* exception for Samsung disk drive*/
2169 mdelay(1000);
2170 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2171 }
2172 MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
b5762948
JG		 2173}
2174
20b09c29 2175int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
b5762948 2176{
20b09c29
AY		 2177 u32 rx_prod_idx, rx_desc;
2178 bool attn = false;
b5762948 2179
20b09c29
AY		 2180 /* the first dword in the RX ring is special: it contains
2181 * a mirror of the hardware's RX producer index, so that
2182 * we don't have to stall the CPU reading that register.
2183 * The actual RX ring is offset by one dword, due to this.
2184 */
2185 rx_prod_idx = mvi->rx_cons;
2186 mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
2187 if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
2188 return 0;
b5762948 2189
20b09c29
AY		 2190 /* The CMPL_Q may come late, read from register and try again
2191 * note: if coalescing is enabled,
2192 * it will need to read from register every time for sure
2193 */
2194 if (unlikely(mvi->rx_cons == rx_prod_idx))
2195 mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
2196
2197 if (mvi->rx_cons == rx_prod_idx)
2198 return 0;
2199
2200 while (mvi->rx_cons != rx_prod_idx) {
2201 /* increment our internal RX consumer pointer */
2202 rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
2203 rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
2204
2205 if (likely(rx_desc & RXQ_DONE))
2206 mvs_slot_complete(mvi, rx_desc, 0);
2207 if (rx_desc & RXQ_ATTN) {
2208 attn = true;
2209 } else if (rx_desc & RXQ_ERR) {
2210 if (!(rx_desc & RXQ_DONE))
2211 mvs_slot_complete(mvi, rx_desc, 0);
2212 } else if (rx_desc & RXQ_SLOT_RESET) {
2213 mvs_slot_free(mvi, rx_desc);
2214 }
2215 }
2216
2217 if (attn && self_clear)
2218 MVS_CHIP_DISP->int_full(mvi);
2219 return 0;
b5762948
JG		 2220}
2221
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