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[SCSI] lpfc 8.3.13: SCSI specific changes
[net-next-2.6.git] / drivers / scsi / lpfc / lpfc_hw.h
CommitLineData
dea3101e
JB		 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
4fede78f 4 * Copyright (C) 2004-2010 Emulex. All rights reserved. *
c44ce173 5 * EMULEX and SLI are trademarks of Emulex. *
dea3101e
JB		 6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC		 9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
dea3101e
JB		 19 *******************************************************************/
20
dea3101e
JB		 21#define FDMI_DID 0xfffffaU
22#define NameServer_DID 0xfffffcU
23#define SCR_DID 0xfffffdU
24#define Fabric_DID 0xfffffeU
25#define Bcast_DID 0xffffffU
26#define Mask_DID 0xffffffU
27#define CT_DID_MASK 0xffff00U
28#define Fabric_DID_MASK 0xfff000U
29#define WELL_KNOWN_DID_MASK 0xfffff0U
30
31#define PT2PT_LocalID 1
32#define PT2PT_RemoteID 2
33
34#define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35#define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36#define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
37#define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
38
39#define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
40 0 */
41
42#define FCELSSIZE 1024 /* maximum ELS transfer size */
43
44#define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
a4bc3379 45#define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
dea3101e
JB		 46#define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47#define LPFC_FCP_NEXT_RING 3
48
49#define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
50#define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
a4bc3379
JS		 51#define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
52#define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
dea3101e
JB		 53#define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
54#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
55#define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
56#define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
57#define SLI2_IOCB_CMD_R3_ENTRIES 0
58#define SLI2_IOCB_RSP_R3_ENTRIES 0
59#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
61
ed957684
JS		 62#define SLI2_IOCB_CMD_SIZE 32
63#define SLI2_IOCB_RSP_SIZE 32
64#define SLI3_IOCB_CMD_SIZE 128
65#define SLI3_IOCB_RSP_SIZE 64
66
92d7f7b0 67
ddcc50f0
JS		 68/* vendor ID used in SCSI netlink calls */
69#define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
70
dea3101e
JB		 71/* Common Transport structures and definitions */
72
73union CtRevisionId {
74 /* Structure is in Big Endian format */
75 struct {
76 uint32_t Revision:8;
77 uint32_t InId:24;
78 } bits;
79 uint32_t word;
80};
81
82union CtCommandResponse {
83 /* Structure is in Big Endian format */
84 struct {
85 uint32_t CmdRsp:16;
86 uint32_t Size:16;
87 } bits;
88 uint32_t word;
89};
90
92d7f7b0
JS		 91#define FC4_FEATURE_INIT 0x2
92#define FC4_FEATURE_TARGET 0x1
93
dea3101e
JB		 94struct lpfc_sli_ct_request {
95 /* Structure is in Big Endian format */
96 union CtRevisionId RevisionId;
97 uint8_t FsType;
98 uint8_t FsSubType;
99 uint8_t Options;
100 uint8_t Rsrvd1;
101 union CtCommandResponse CommandResponse;
102 uint8_t Rsrvd2;
103 uint8_t ReasonCode;
104 uint8_t Explanation;
105 uint8_t VendorUnique;
106
107 union {
108 uint32_t PortID;
109 struct gid {
110 uint8_t PortType; /* for GID_PT requests */
111 uint8_t DomainScope;
112 uint8_t AreaScope;
113 uint8_t Fc4Type; /* for GID_FT requests */
114 } gid;
115 struct rft {
116 uint32_t PortId; /* For RFT_ID requests */
117
118#ifdef __BIG_ENDIAN_BITFIELD
119 uint32_t rsvd0:16;
120 uint32_t rsvd1:7;
121 uint32_t fcpReg:1; /* Type 8 */
122 uint32_t rsvd2:2;
123 uint32_t ipReg:1; /* Type 5 */
124 uint32_t rsvd3:5;
125#else /* __LITTLE_ENDIAN_BITFIELD */
126 uint32_t rsvd0:16;
127 uint32_t fcpReg:1; /* Type 8 */
128 uint32_t rsvd1:7;
129 uint32_t rsvd3:5;
130 uint32_t ipReg:1; /* Type 5 */
131 uint32_t rsvd2:2;
132#endif
133
134 uint32_t rsvd[7];
135 } rft;
136 struct rnn {
137 uint32_t PortId; /* For RNN_ID requests */
138 uint8_t wwnn[8];
139 } rnn;
140 struct rsnn { /* For RSNN_ID requests */
141 uint8_t wwnn[8];
142 uint8_t len;
143 uint8_t symbname[255];
144 } rsnn;
7ee5d43e
JS		 145 struct da_id { /* For DA_ID requests */
146 uint32_t port_id;
147 } da_id;
92d7f7b0
JS		 148 struct rspn { /* For RSPN_ID requests */
149 uint32_t PortId;
150 uint8_t len;
151 uint8_t symbname[255];
152 } rspn;
153 struct gff {
154 uint32_t PortId;
155 } gff;
156 struct gff_acc {
157 uint8_t fbits[128];
158 } gff_acc;
51ef4c26 159#define FCP_TYPE_FEATURE_OFFSET 7
92d7f7b0
JS		 160 struct rff {
161 uint32_t PortId;
162 uint8_t reserved[2];
163 uint8_t fbits;
164 uint8_t type_code; /* type=8 for FCP */
165 } rff;
dea3101e
JB		 166 } un;
167};
168
169#define SLI_CT_REVISION 1
92d7f7b0
JS		 170#define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
171 sizeof(struct gid))
172#define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
173 sizeof(struct gff))
174#define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
175 sizeof(struct rft))
176#define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
177 sizeof(struct rff))
178#define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
179 sizeof(struct rnn))
180#define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
181 sizeof(struct rsnn))
7ee5d43e
JS		 182#define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
183 sizeof(struct da_id))
92d7f7b0
JS		 184#define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
185 sizeof(struct rspn))
dea3101e
JB		 186
187/*
188 * FsType Definitions
189 */
190
191#define SLI_CT_MANAGEMENT_SERVICE 0xFA
192#define SLI_CT_TIME_SERVICE 0xFB
193#define SLI_CT_DIRECTORY_SERVICE 0xFC
194#define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
195
196/*
197 * Directory Service Subtypes
198 */
199
200#define SLI_CT_DIRECTORY_NAME_SERVER 0x02
201
202/*
203 * Response Codes
204 */
205
206#define SLI_CT_RESPONSE_FS_RJT 0x8001
207#define SLI_CT_RESPONSE_FS_ACC 0x8002
208
209/*
210 * Reason Codes
211 */
212
213#define SLI_CT_NO_ADDITIONAL_EXPL 0x0
214#define SLI_CT_INVALID_COMMAND 0x01
215#define SLI_CT_INVALID_VERSION 0x02
216#define SLI_CT_LOGICAL_ERROR 0x03
217#define SLI_CT_INVALID_IU_SIZE 0x04
218#define SLI_CT_LOGICAL_BUSY 0x05
219#define SLI_CT_PROTOCOL_ERROR 0x07
220#define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
221#define SLI_CT_REQ_NOT_SUPPORTED 0x0b
222#define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
223#define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
224#define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
225#define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
226#define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
227#define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
228#define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
229#define SLI_CT_VENDOR_UNIQUE 0xff
230
231/*
232 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
233 */
234
235#define SLI_CT_NO_PORT_ID 0x01
236#define SLI_CT_NO_PORT_NAME 0x02
237#define SLI_CT_NO_NODE_NAME 0x03
238#define SLI_CT_NO_CLASS_OF_SERVICE 0x04
239#define SLI_CT_NO_IP_ADDRESS 0x05
240#define SLI_CT_NO_IPA 0x06
241#define SLI_CT_NO_FC4_TYPES 0x07
242#define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
243#define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
244#define SLI_CT_NO_PORT_TYPE 0x0A
245#define SLI_CT_ACCESS_DENIED 0x10
246#define SLI_CT_INVALID_PORT_ID 0x11
247#define SLI_CT_DATABASE_EMPTY 0x12
248
249/*
250 * Name Server Command Codes
251 */
252
253#define SLI_CTNS_GA_NXT 0x0100
254#define SLI_CTNS_GPN_ID 0x0112
255#define SLI_CTNS_GNN_ID 0x0113
256#define SLI_CTNS_GCS_ID 0x0114
257#define SLI_CTNS_GFT_ID 0x0117
258#define SLI_CTNS_GSPN_ID 0x0118
259#define SLI_CTNS_GPT_ID 0x011A
92d7f7b0 260#define SLI_CTNS_GFF_ID 0x011F
dea3101e
JB		 261#define SLI_CTNS_GID_PN 0x0121
262#define SLI_CTNS_GID_NN 0x0131
263#define SLI_CTNS_GIP_NN 0x0135
264#define SLI_CTNS_GIPA_NN 0x0136
265#define SLI_CTNS_GSNN_NN 0x0139
266#define SLI_CTNS_GNN_IP 0x0153
267#define SLI_CTNS_GIPA_IP 0x0156
268#define SLI_CTNS_GID_FT 0x0171
269#define SLI_CTNS_GID_PT 0x01A1
270#define SLI_CTNS_RPN_ID 0x0212
271#define SLI_CTNS_RNN_ID 0x0213
272#define SLI_CTNS_RCS_ID 0x0214
273#define SLI_CTNS_RFT_ID 0x0217
274#define SLI_CTNS_RSPN_ID 0x0218
275#define SLI_CTNS_RPT_ID 0x021A
92d7f7b0 276#define SLI_CTNS_RFF_ID 0x021F
dea3101e
JB		 277#define SLI_CTNS_RIP_NN 0x0235
278#define SLI_CTNS_RIPA_NN 0x0236
279#define SLI_CTNS_RSNN_NN 0x0239
280#define SLI_CTNS_DA_ID 0x0300
281
282/*
283 * Port Types
284 */
285
286#define SLI_CTPT_N_PORT 0x01
287#define SLI_CTPT_NL_PORT 0x02
288#define SLI_CTPT_FNL_PORT 0x03
289#define SLI_CTPT_IP 0x04
290#define SLI_CTPT_FCP 0x08
291#define SLI_CTPT_NX_PORT 0x7F
292#define SLI_CTPT_F_PORT 0x81
293#define SLI_CTPT_FL_PORT 0x82
294#define SLI_CTPT_E_PORT 0x84
295
296#define SLI_CT_LAST_ENTRY 0x80000000
297
298/* Fibre Channel Service Parameter definitions */
299
300#define FC_PH_4_0 6 /* FC-PH version 4.0 */
301#define FC_PH_4_1 7 /* FC-PH version 4.1 */
302#define FC_PH_4_2 8 /* FC-PH version 4.2 */
303#define FC_PH_4_3 9 /* FC-PH version 4.3 */
304
305#define FC_PH_LOW 8 /* Lowest supported FC-PH version */
306#define FC_PH_HIGH 9 /* Highest supported FC-PH version */
307#define FC_PH3 0x20 /* FC-PH-3 version */
308
309#define FF_FRAME_SIZE 2048
310
311struct lpfc_name {
f631b4be
AV		 312 union {
313 struct {
dea3101e 314#ifdef __BIG_ENDIAN_BITFIELD
f631b4be 315 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
1de933f3
JSEC		 316 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
317 8:11 of IEEE ext */
dea3101e 318#else /* __LITTLE_ENDIAN_BITFIELD */
1de933f3
JSEC		 319 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
320 8:11 of IEEE ext */
f631b4be 321 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
dea3101e
JB		 322#endif
323
324#define NAME_IEEE 0x1 /* IEEE name - nameType */
325#define NAME_IEEE_EXT 0x2 /* IEEE extended name */
326#define NAME_FC_TYPE 0x3 /* FC native name type */
327#define NAME_IP_TYPE 0x4 /* IP address */
328#define NAME_CCITT_TYPE 0xC
329#define NAME_CCITT_GR_TYPE 0xE
1de933f3
JSEC		 330 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
331 extended Lsb */
f631b4be 332 uint8_t IEEE[6]; /* FC IEEE address */
68ce1eb5 333 } s;
f631b4be 334 uint8_t wwn[8];
68ce1eb5 335 } u;
dea3101e
JB		 336};
337
338struct csp {
339 uint8_t fcphHigh; /* FC Word 0, byte 0 */
340 uint8_t fcphLow;
341 uint8_t bbCreditMsb;
342 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
343
344#ifdef __BIG_ENDIAN_BITFIELD
92d7f7b0
JS		 345 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
346 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
347 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
dea3101e
JB		 348 uint16_t fPort:1; /* FC Word 1, bit 28 */
349 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
350 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
351 uint16_t multicast:1; /* FC Word 1, bit 25 */
352 uint16_t broadcast:1; /* FC Word 1, bit 24 */
353
354 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
355 uint16_t simplex:1; /* FC Word 1, bit 22 */
356 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
357 uint16_t dhd:1; /* FC Word 1, bit 18 */
358 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
359 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
360#else /* __LITTLE_ENDIAN_BITFIELD */
361 uint16_t broadcast:1; /* FC Word 1, bit 24 */
362 uint16_t multicast:1; /* FC Word 1, bit 25 */
363 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
364 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
365 uint16_t fPort:1; /* FC Word 1, bit 28 */
92d7f7b0 366 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
dea3101e 367 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
92d7f7b0 368 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
dea3101e
JB		 369
370 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
371 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
372 uint16_t dhd:1; /* FC Word 1, bit 18 */
373 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
374 uint16_t simplex:1; /* FC Word 1, bit 22 */
375 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
376#endif
377
378 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
379 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
380 union {
381 struct {
382 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
383
384 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
385 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
386
387 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
388 } nPort;
389 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
390 } w2;
391
392 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
393};
394
395struct class_parms {
396#ifdef __BIG_ENDIAN_BITFIELD
397 uint8_t classValid:1; /* FC Word 0, bit 31 */
398 uint8_t intermix:1; /* FC Word 0, bit 30 */
399 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
400 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
401 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
402 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
403#else /* __LITTLE_ENDIAN_BITFIELD */
404 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
405 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
406 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
407 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
408 uint8_t intermix:1; /* FC Word 0, bit 30 */
409 uint8_t classValid:1; /* FC Word 0, bit 31 */
410
411#endif
412
413 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
414
415#ifdef __BIG_ENDIAN_BITFIELD
416 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
417 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
418 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
419 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
420 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
421#else /* __LITTLE_ENDIAN_BITFIELD */
422 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
423 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
424 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
425 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
426 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
427#endif
428
429 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
430
431#ifdef __BIG_ENDIAN_BITFIELD
432 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
433 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
434 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
435 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
436 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
437 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
438#else /* __LITTLE_ENDIAN_BITFIELD */
439 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
440 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
441 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
442 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
443 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
444 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
445#endif
446
447 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
448 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
449 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
450
451 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
452 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
453 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
454 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
455
456 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
457 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
458 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
459 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
460};
461
462struct serv_parm { /* Structure is in Big Endian format */
463 struct csp cmn;
464 struct lpfc_name portName;
465 struct lpfc_name nodeName;
466 struct class_parms cls1;
467 struct class_parms cls2;
468 struct class_parms cls3;
469 struct class_parms cls4;
470 uint8_t vendorVersion[16];
471};
472
da0436e9
JS		 473/*
474 * Virtual Fabric Tagging Header
475 */
476struct fc_vft_header {
477 uint32_t word0;
478#define fc_vft_hdr_r_ctl_SHIFT 24
479#define fc_vft_hdr_r_ctl_MASK 0xFF
480#define fc_vft_hdr_r_ctl_WORD word0
481#define fc_vft_hdr_ver_SHIFT 22
482#define fc_vft_hdr_ver_MASK 0x3
483#define fc_vft_hdr_ver_WORD word0
484#define fc_vft_hdr_type_SHIFT 18
485#define fc_vft_hdr_type_MASK 0xF
486#define fc_vft_hdr_type_WORD word0
487#define fc_vft_hdr_e_SHIFT 16
488#define fc_vft_hdr_e_MASK 0x1
489#define fc_vft_hdr_e_WORD word0
490#define fc_vft_hdr_priority_SHIFT 13
491#define fc_vft_hdr_priority_MASK 0x7
492#define fc_vft_hdr_priority_WORD word0
493#define fc_vft_hdr_vf_id_SHIFT 1
494#define fc_vft_hdr_vf_id_MASK 0xFFF
495#define fc_vft_hdr_vf_id_WORD word0
496 uint32_t word1;
497#define fc_vft_hdr_hopct_SHIFT 24
498#define fc_vft_hdr_hopct_MASK 0xFF
499#define fc_vft_hdr_hopct_WORD word1
500};
501
dea3101e
JB		 502/*
503 * Extended Link Service LS_COMMAND codes (Payload Word 0)
504 */
505#ifdef __BIG_ENDIAN_BITFIELD
506#define ELS_CMD_MASK 0xffff0000
507#define ELS_RSP_MASK 0xff000000
508#define ELS_CMD_LS_RJT 0x01000000
509#define ELS_CMD_ACC 0x02000000
510#define ELS_CMD_PLOGI 0x03000000
511#define ELS_CMD_FLOGI 0x04000000
512#define ELS_CMD_LOGO 0x05000000
513#define ELS_CMD_ABTX 0x06000000
514#define ELS_CMD_RCS 0x07000000
515#define ELS_CMD_RES 0x08000000
516#define ELS_CMD_RSS 0x09000000
517#define ELS_CMD_RSI 0x0A000000
518#define ELS_CMD_ESTS 0x0B000000
519#define ELS_CMD_ESTC 0x0C000000
520#define ELS_CMD_ADVC 0x0D000000
521#define ELS_CMD_RTV 0x0E000000
522#define ELS_CMD_RLS 0x0F000000
523#define ELS_CMD_ECHO 0x10000000
524#define ELS_CMD_TEST 0x11000000
525#define ELS_CMD_RRQ 0x12000000
526#define ELS_CMD_PRLI 0x20100014
527#define ELS_CMD_PRLO 0x21100014
82d9a2a2 528#define ELS_CMD_PRLO_ACC 0x02100014
dea3101e
JB		 529#define ELS_CMD_PDISC 0x50000000
530#define ELS_CMD_FDISC 0x51000000
531#define ELS_CMD_ADISC 0x52000000
532#define ELS_CMD_FARP 0x54000000
533#define ELS_CMD_FARPR 0x55000000
7bb3b137
JW		 534#define ELS_CMD_RPS 0x56000000
535#define ELS_CMD_RPL 0x57000000
dea3101e
JB		 536#define ELS_CMD_FAN 0x60000000
537#define ELS_CMD_RSCN 0x61040000
538#define ELS_CMD_SCR 0x62000000
539#define ELS_CMD_RNID 0x78000000
7bb3b137 540#define ELS_CMD_LIRR 0x7A000000
dea3101e
JB		 541#else /* __LITTLE_ENDIAN_BITFIELD */
542#define ELS_CMD_MASK 0xffff
543#define ELS_RSP_MASK 0xff
544#define ELS_CMD_LS_RJT 0x01
545#define ELS_CMD_ACC 0x02
546#define ELS_CMD_PLOGI 0x03
547#define ELS_CMD_FLOGI 0x04
548#define ELS_CMD_LOGO 0x05
549#define ELS_CMD_ABTX 0x06
550#define ELS_CMD_RCS 0x07
551#define ELS_CMD_RES 0x08
552#define ELS_CMD_RSS 0x09
553#define ELS_CMD_RSI 0x0A
554#define ELS_CMD_ESTS 0x0B
555#define ELS_CMD_ESTC 0x0C
556#define ELS_CMD_ADVC 0x0D
557#define ELS_CMD_RTV 0x0E
558#define ELS_CMD_RLS 0x0F
559#define ELS_CMD_ECHO 0x10
560#define ELS_CMD_TEST 0x11
561#define ELS_CMD_RRQ 0x12
562#define ELS_CMD_PRLI 0x14001020
563#define ELS_CMD_PRLO 0x14001021
82d9a2a2 564#define ELS_CMD_PRLO_ACC 0x14001002
dea3101e
JB		 565#define ELS_CMD_PDISC 0x50
566#define ELS_CMD_FDISC 0x51
567#define ELS_CMD_ADISC 0x52
568#define ELS_CMD_FARP 0x54
569#define ELS_CMD_FARPR 0x55
7bb3b137
JW		 570#define ELS_CMD_RPS 0x56
571#define ELS_CMD_RPL 0x57
dea3101e
JB		 572#define ELS_CMD_FAN 0x60
573#define ELS_CMD_RSCN 0x0461
574#define ELS_CMD_SCR 0x62
575#define ELS_CMD_RNID 0x78
7bb3b137 576#define ELS_CMD_LIRR 0x7A
dea3101e
JB		 577#endif
578
579/*
580 * LS_RJT Payload Definition
581 */
582
583struct ls_rjt { /* Structure is in Big Endian format */
584 union {
585 uint32_t lsRjtError;
586 struct {
587 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
588
589 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
590 /* LS_RJT reason codes */
591#define LSRJT_INVALID_CMD 0x01
592#define LSRJT_LOGICAL_ERR 0x03
593#define LSRJT_LOGICAL_BSY 0x05
594#define LSRJT_PROTOCOL_ERR 0x07
595#define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
596#define LSRJT_CMD_UNSUPPORTED 0x0B
597#define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
598
599 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
600 /* LS_RJT reason explanation */
601#define LSEXP_NOTHING_MORE 0x00
602#define LSEXP_SPARM_OPTIONS 0x01
603#define LSEXP_SPARM_ICTL 0x03
604#define LSEXP_SPARM_RCTL 0x05
605#define LSEXP_SPARM_RCV_SIZE 0x07
606#define LSEXP_SPARM_CONCUR_SEQ 0x09
607#define LSEXP_SPARM_CREDIT 0x0B
608#define LSEXP_INVALID_PNAME 0x0D
609#define LSEXP_INVALID_NNAME 0x0E
610#define LSEXP_INVALID_CSP 0x0F
611#define LSEXP_INVALID_ASSOC_HDR 0x11
612#define LSEXP_ASSOC_HDR_REQ 0x13
613#define LSEXP_INVALID_O_SID 0x15
614#define LSEXP_INVALID_OX_RX 0x17
615#define LSEXP_CMD_IN_PROGRESS 0x19
7f5f3d0d 616#define LSEXP_PORT_LOGIN_REQ 0x1E
dea3101e
JB		 617#define LSEXP_INVALID_NPORT_ID 0x1F
618#define LSEXP_INVALID_SEQ_ID 0x21
619#define LSEXP_INVALID_XCHG 0x23
620#define LSEXP_INACTIVE_XCHG 0x25
621#define LSEXP_RQ_REQUIRED 0x27
622#define LSEXP_OUT_OF_RESOURCE 0x29
623#define LSEXP_CANT_GIVE_DATA 0x2A
624#define LSEXP_REQ_UNSUPPORTED 0x2C
625 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
626 } b;
627 } un;
628};
629
630/*
631 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
632 */
633
634typedef struct _LOGO { /* Structure is in Big Endian format */
635 union {
636 uint32_t nPortId32; /* Access nPortId as a word */
637 struct {
638 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
639 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
640 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
641 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
642 } b;
643 } un;
644 struct lpfc_name portName; /* N_port name field */
645} LOGO;
646
647/*
648 * FCP Login (PRLI Request / ACC) Payload Definition
649 */
650
651#define PRLX_PAGE_LEN 0x10
652#define TPRLO_PAGE_LEN 0x14
653
654typedef struct _PRLI { /* Structure is in Big Endian format */
655 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
656
657#define PRLI_FCP_TYPE 0x08
658 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
659
660#ifdef __BIG_ENDIAN_BITFIELD
661 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
662 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
663 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
664
665 /* ACC = imagePairEstablished */
666 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
667 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
668#else /* __LITTLE_ENDIAN_BITFIELD */
669 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
670 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
671 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
672 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
673 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
674 /* ACC = imagePairEstablished */
675#endif
676
677#define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
678#define PRLI_NO_RESOURCES 0x2
679#define PRLI_INIT_INCOMPLETE 0x3
680#define PRLI_NO_SUCH_PA 0x4
681#define PRLI_PREDEF_CONFIG 0x5
682#define PRLI_PARTIAL_SUCCESS 0x6
683#define PRLI_INVALID_PAGE_CNT 0x7
684 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
685
686 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
687
688 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
689
690 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
691 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
692
693#ifdef __BIG_ENDIAN_BITFIELD
694 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
695 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
696 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
697 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
698 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
699 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
700 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
701 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
702 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
703 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
704 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
705 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
706 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
707 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
708 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
709 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
710#else /* __LITTLE_ENDIAN_BITFIELD */
711 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
712 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
713 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
714 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
715 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
716 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
717 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
718 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
719 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
720 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
721 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
722 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
723 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
724 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
725 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
726 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
727#endif
728} PRLI;
729
730/*
731 * FCP Logout (PRLO Request / ACC) Payload Definition
732 */
733
734typedef struct _PRLO { /* Structure is in Big Endian format */
735 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
736
737#define PRLO_FCP_TYPE 0x08
738 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
739
740#ifdef __BIG_ENDIAN_BITFIELD
741 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
742 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
743 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
744 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
745#else /* __LITTLE_ENDIAN_BITFIELD */
746 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
747 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
748 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
749 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
750#endif
751
752#define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
753#define PRLO_NO_SUCH_IMAGE 0x4
754#define PRLO_INVALID_PAGE_CNT 0x7
755
756 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
757
758 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
759
760 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
761
762 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
763} PRLO;
764
765typedef struct _ADISC { /* Structure is in Big Endian format */
766 uint32_t hardAL_PA;
767 struct lpfc_name portName;
768 struct lpfc_name nodeName;
769 uint32_t DID;
770} ADISC;
771
772typedef struct _FARP { /* Structure is in Big Endian format */
773 uint32_t Mflags:8;
774 uint32_t Odid:24;
775#define FARP_NO_ACTION 0 /* FARP information enclosed, no
776 action */
777#define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
778#define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
779#define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
780#define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
781 supported */
782#define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
783 supported */
784 uint32_t Rflags:8;
785 uint32_t Rdid:24;
786#define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
787#define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
788 struct lpfc_name OportName;
789 struct lpfc_name OnodeName;
790 struct lpfc_name RportName;
791 struct lpfc_name RnodeName;
792 uint8_t Oipaddr[16];
793 uint8_t Ripaddr[16];
794} FARP;
795
796typedef struct _FAN { /* Structure is in Big Endian format */
797 uint32_t Fdid;
798 struct lpfc_name FportName;
799 struct lpfc_name FnodeName;
800} FAN;
801
802typedef struct _SCR { /* Structure is in Big Endian format */
803 uint8_t resvd1;
804 uint8_t resvd2;
805 uint8_t resvd3;
806 uint8_t Function;
807#define SCR_FUNC_FABRIC 0x01
808#define SCR_FUNC_NPORT 0x02
809#define SCR_FUNC_FULL 0x03
810#define SCR_CLEAR 0xff
811} SCR;
812
813typedef struct _RNID_TOP_DISC {
814 struct lpfc_name portName;
815 uint8_t resvd[8];
816 uint32_t unitType;
817#define RNID_HBA 0x7
818#define RNID_HOST 0xa
819#define RNID_DRIVER 0xd
820 uint32_t physPort;
821 uint32_t attachedNodes;
822 uint16_t ipVersion;
823#define RNID_IPV4 0x1
824#define RNID_IPV6 0x2
825 uint16_t UDPport;
826 uint8_t ipAddr[16];
827 uint16_t resvd1;
828 uint16_t flags;
829#define RNID_TD_SUPPORT 0x1
830#define RNID_LP_VALID 0x2
831} RNID_TOP_DISC;
832
833typedef struct _RNID { /* Structure is in Big Endian format */
834 uint8_t Format;
835#define RNID_TOPOLOGY_DISC 0xdf
836 uint8_t CommonLen;
837 uint8_t resvd1;
838 uint8_t SpecificLen;
839 struct lpfc_name portName;
840 struct lpfc_name nodeName;
841 union {
842 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
843 } un;
844} RNID;
845
311464ec 846typedef struct _RPS { /* Structure is in Big Endian format */
7bb3b137
JW		 847 union {
848 uint32_t portNum;
849 struct lpfc_name portName;
850 } un;
851} RPS;
852
853typedef struct _RPS_RSP { /* Structure is in Big Endian format */
854 uint16_t rsvd1;
855 uint16_t portStatus;
856 uint32_t linkFailureCnt;
857 uint32_t lossSyncCnt;
858 uint32_t lossSignalCnt;
859 uint32_t primSeqErrCnt;
860 uint32_t invalidXmitWord;
861 uint32_t crcCnt;
862} RPS_RSP;
863
311464ec 864typedef struct _RPL { /* Structure is in Big Endian format */
7bb3b137
JW		 865 uint32_t maxsize;
866 uint32_t index;
867} RPL;
868
869typedef struct _PORT_NUM_BLK {
870 uint32_t portNum;
871 uint32_t portID;
872 struct lpfc_name portName;
873} PORT_NUM_BLK;
874
311464ec 875typedef struct _RPL_RSP { /* Structure is in Big Endian format */
7bb3b137
JW		 876 uint32_t listLen;
877 uint32_t index;
878 PORT_NUM_BLK port_num_blk;
879} RPL_RSP;
dea3101e
JB		 880
881/* This is used for RSCN command */
882typedef struct _D_ID { /* Structure is in Big Endian format */
883 union {
884 uint32_t word;
885 struct {
886#ifdef __BIG_ENDIAN_BITFIELD
887 uint8_t resv;
888 uint8_t domain;
889 uint8_t area;
890 uint8_t id;
891#else /* __LITTLE_ENDIAN_BITFIELD */
892 uint8_t id;
893 uint8_t area;
894 uint8_t domain;
895 uint8_t resv;
896#endif
897 } b;
898 } un;
899} D_ID;
900
eaf15d5b
JS		 901#define RSCN_ADDRESS_FORMAT_PORT 0x0
902#define RSCN_ADDRESS_FORMAT_AREA 0x1
903#define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
904#define RSCN_ADDRESS_FORMAT_FABRIC 0x3
905#define RSCN_ADDRESS_FORMAT_MASK 0x3
906
dea3101e
JB		 907/*
908 * Structure to define all ELS Payload types
909 */
910
911typedef struct _ELS_PKT { /* Structure is in Big Endian format */
912 uint8_t elsCode; /* FC Word 0, bit 24:31 */
913 uint8_t elsByte1;
914 uint8_t elsByte2;
915 uint8_t elsByte3;
916 union {
917 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
918 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
919 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
920 PRLI prli; /* Payload for PRLI/ACC */
921 PRLO prlo; /* Payload for PRLO/ACC */
922 ADISC adisc; /* Payload for ADISC/ACC */
923 FARP farp; /* Payload for FARP/ACC */
924 FAN fan; /* Payload for FAN */
925 SCR scr; /* Payload for SCR/ACC */
dea3101e
JB		 926 RNID rnid; /* Payload for RNID */
927 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
928 } un;
929} ELS_PKT;
930
931/*
932 * FDMI
933 * HBA MAnagement Operations Command Codes
934 */
935#define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
936#define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
937#define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
938#define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
939#define SLI_MGMT_RHBA 0x200 /* Register HBA */
940#define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */
941#define SLI_MGMT_RPRT 0x210 /* Register Port */
942#define SLI_MGMT_RPA 0x211 /* Register Port attributes */
943#define SLI_MGMT_DHBA 0x300 /* De-register HBA */
944#define SLI_MGMT_DPRT 0x310 /* De-register Port */
945
946/*
947 * Management Service Subtypes
948 */
949#define SLI_CT_FDMI_Subtypes 0x10
950
951/*
952 * HBA Management Service Reject Code
953 */
954#define REJECT_CODE 0x9 /* Unable to perform command request */
955
956/*
957 * HBA Management Service Reject Reason Code
958 * Please refer to the Reason Codes above
959 */
960
961/*
962 * HBA Attribute Types
963 */
964#define NODE_NAME 0x1
965#define MANUFACTURER 0x2
966#define SERIAL_NUMBER 0x3
967#define MODEL 0x4
968#define MODEL_DESCRIPTION 0x5
969#define HARDWARE_VERSION 0x6
970#define DRIVER_VERSION 0x7
971#define OPTION_ROM_VERSION 0x8
972#define FIRMWARE_VERSION 0x9
973#define OS_NAME_VERSION 0xa
974#define MAX_CT_PAYLOAD_LEN 0xb
975
976/*
977 * Port Attrubute Types
978 */
979#define SUPPORTED_FC4_TYPES 0x1
980#define SUPPORTED_SPEED 0x2
981#define PORT_SPEED 0x3
982#define MAX_FRAME_SIZE 0x4
983#define OS_DEVICE_NAME 0x5
984#define HOST_NAME 0x6
985
986union AttributesDef {
987 /* Structure is in Big Endian format */
988 struct {
989 uint32_t AttrType:16;
990 uint32_t AttrLen:16;
991 } bits;
992 uint32_t word;
993};
994
995
996/*
997 * HBA Attribute Entry (8 - 260 bytes)
998 */
999typedef struct {
1000 union AttributesDef ad;
1001 union {
1002 uint32_t VendorSpecific;
1003 uint8_t Manufacturer[64];
1004 uint8_t SerialNumber[64];
1005 uint8_t Model[256];
1006 uint8_t ModelDescription[256];
1007 uint8_t HardwareVersion[256];
1008 uint8_t DriverVersion[256];
1009 uint8_t OptionROMVersion[256];
1010 uint8_t FirmwareVersion[256];
1011 struct lpfc_name NodeName;
1012 uint8_t SupportFC4Types[32];
1013 uint32_t SupportSpeed;
1014 uint32_t PortSpeed;
1015 uint32_t MaxFrameSize;
1016 uint8_t OsDeviceName[256];
1017 uint8_t OsNameVersion[256];
1018 uint32_t MaxCTPayloadLen;
1019 uint8_t HostName[256];
1020 } un;
1021} ATTRIBUTE_ENTRY;
1022
1023/*
1024 * HBA Attribute Block
1025 */
1026typedef struct {
1027 uint32_t EntryCnt; /* Number of HBA attribute entries */
1028 ATTRIBUTE_ENTRY Entry; /* Variable-length array */
1029} ATTRIBUTE_BLOCK;
1030
1031/*
1032 * Port Entry
1033 */
1034typedef struct {
1035 struct lpfc_name PortName;
1036} PORT_ENTRY;
1037
1038/*
1039 * HBA Identifier
1040 */
1041typedef struct {
1042 struct lpfc_name PortName;
1043} HBA_IDENTIFIER;
1044
1045/*
1046 * Registered Port List Format
1047 */
1048typedef struct {
1049 uint32_t EntryCnt;
1050 PORT_ENTRY pe; /* Variable-length array */
1051} REG_PORT_LIST;
1052
1053/*
1054 * Register HBA(RHBA)
1055 */
1056typedef struct {
1057 HBA_IDENTIFIER hi;
1058 REG_PORT_LIST rpl; /* variable-length array */
1059/* ATTRIBUTE_BLOCK ab; */
1060} REG_HBA;
1061
1062/*
1063 * Register HBA Attributes (RHAT)
1064 */
1065typedef struct {
1066 struct lpfc_name HBA_PortName;
1067 ATTRIBUTE_BLOCK ab;
1068} REG_HBA_ATTRIBUTE;
1069
1070/*
1071 * Register Port Attributes (RPA)
1072 */
1073typedef struct {
1074 struct lpfc_name PortName;
1075 ATTRIBUTE_BLOCK ab;
1076} REG_PORT_ATTRIBUTE;
1077
1078/*
1079 * Get Registered HBA List (GRHL) Accept Payload Format
1080 */
1081typedef struct {
1082 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1083 struct lpfc_name HBA_PortName; /* Variable-length array */
1084} GRHL_ACC_PAYLOAD;
1085
1086/*
1087 * Get Registered Port List (GRPL) Accept Payload Format
1088 */
1089typedef struct {
1090 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1091 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
1092} GRPL_ACC_PAYLOAD;
1093
1094/*
1095 * Get Port Attributes (GPAT) Accept Payload Format
1096 */
1097
1098typedef struct {
1099 ATTRIBUTE_BLOCK pab;
1100} GPAT_ACC_PAYLOAD;
1101
1102
1103/*
1104 * Begin HBA configuration parameters.
1105 * The PCI configuration register BAR assignments are:
1106 * BAR0, offset 0x10 - SLIM base memory address
1107 * BAR1, offset 0x14 - SLIM base memory high address
1108 * BAR2, offset 0x18 - REGISTER base memory address
1109 * BAR3, offset 0x1c - REGISTER base memory high address
1110 * BAR4, offset 0x20 - BIU I/O registers
1111 * BAR5, offset 0x24 - REGISTER base io high address
1112 */
1113
1114/* Number of rings currently used and available. */
1115#define MAX_CONFIGURED_RINGS 3
1116#define MAX_RINGS 4
1117
1118/* IOCB / Mailbox is owned by FireFly */
1119#define OWN_CHIP 1
1120
1121/* IOCB / Mailbox is owned by Host */
1122#define OWN_HOST 0
1123
1124/* Number of 4-byte words in an IOCB. */
1125#define IOCB_WORD_SZ 8
1126
dea3101e
JB		 1127/* network headers for Dfctl field */
1128#define FC_NET_HDR 0x20
1129
1130/* Start FireFly Register definitions */
1131#define PCI_VENDOR_ID_EMULEX 0x10df
1132#define PCI_DEVICE_ID_FIREFLY 0x1ae5
84774a4d
JS		 1133#define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1134#define PCI_DEVICE_ID_PROTEUS_PF 0xe180
b87eab38
JS		 1135#define PCI_DEVICE_ID_SAT_SMB 0xf011
1136#define PCI_DEVICE_ID_SAT_MID 0xf015
dea3101e
JB		 1137#define PCI_DEVICE_ID_RFLY 0xf095
1138#define PCI_DEVICE_ID_PFLY 0xf098
e4adb204 1139#define PCI_DEVICE_ID_LP101 0xf0a1
dea3101e 1140#define PCI_DEVICE_ID_TFLY 0xf0a5
e4adb204
JSEC		 1141#define PCI_DEVICE_ID_BSMB 0xf0d1
1142#define PCI_DEVICE_ID_BMID 0xf0d5
1143#define PCI_DEVICE_ID_ZSMB 0xf0e1
1144#define PCI_DEVICE_ID_ZMID 0xf0e5
1145#define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1146#define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1147#define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
b87eab38
JS		 1148#define PCI_DEVICE_ID_SAT 0xf100
1149#define PCI_DEVICE_ID_SAT_SCSP 0xf111
1150#define PCI_DEVICE_ID_SAT_DCSP 0xf112
e4adb204
JSEC		 1151#define PCI_DEVICE_ID_SUPERFLY 0xf700
1152#define PCI_DEVICE_ID_DRAGONFLY 0xf800
dea3101e
JB		 1153#define PCI_DEVICE_ID_CENTAUR 0xf900
1154#define PCI_DEVICE_ID_PEGASUS 0xf980
1155#define PCI_DEVICE_ID_THOR 0xfa00
1156#define PCI_DEVICE_ID_VIPER 0xfb00
e4adb204
JSEC		 1157#define PCI_DEVICE_ID_LP10000S 0xfc00
1158#define PCI_DEVICE_ID_LP11000S 0xfc10
1159#define PCI_DEVICE_ID_LPE11000S 0xfc20
b87eab38 1160#define PCI_DEVICE_ID_SAT_S 0xfc40
84774a4d 1161#define PCI_DEVICE_ID_PROTEUS_S 0xfc50
dea3101e 1162#define PCI_DEVICE_ID_HELIOS 0xfd00
e4adb204
JSEC		 1163#define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1164#define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
dea3101e 1165#define PCI_DEVICE_ID_ZEPHYR 0xfe00
84774a4d 1166#define PCI_DEVICE_ID_HORNET 0xfe05
e4adb204
JSEC		 1167#define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1168#define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
da0436e9
JS		 1169#define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1170#define PCI_DEVICE_ID_TIGERSHARK 0x0704
a747c9ce
JS		 1171#define PCI_DEVICE_ID_TOMCAT 0x0714
1172#define PCI_DEVICE_ID_FALCON 0xf180
dea3101e
JB		 1173
1174#define JEDEC_ID_ADDRESS 0x0080001c
1175#define FIREFLY_JEDEC_ID 0x1ACC
1176#define SUPERFLY_JEDEC_ID 0x0020
1177#define DRAGONFLY_JEDEC_ID 0x0021
1178#define DRAGONFLY_V2_JEDEC_ID 0x0025
1179#define CENTAUR_2G_JEDEC_ID 0x0026
1180#define CENTAUR_1G_JEDEC_ID 0x0028
1181#define PEGASUS_ORION_JEDEC_ID 0x0036
1182#define PEGASUS_JEDEC_ID 0x0038
1183#define THOR_JEDEC_ID 0x0012
1184#define HELIOS_JEDEC_ID 0x0364
1185#define ZEPHYR_JEDEC_ID 0x0577
1186#define VIPER_JEDEC_ID 0x4838
b87eab38 1187#define SATURN_JEDEC_ID 0x1004
84774a4d 1188#define HORNET_JDEC_ID 0x2057706D
dea3101e
JB		 1189
1190#define JEDEC_ID_MASK 0x0FFFF000
1191#define JEDEC_ID_SHIFT 12
1192#define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1193
1194typedef struct { /* FireFly BIU registers */
1195 uint32_t hostAtt; /* See definitions for Host Attention
1196 register */
1197 uint32_t chipAtt; /* See definitions for Chip Attention
1198 register */
1199 uint32_t hostStatus; /* See definitions for Host Status register */
1200 uint32_t hostControl; /* See definitions for Host Control register */
1201 uint32_t buiConfig; /* See definitions for BIU configuration
1202 register */
1203} FF_REGS;
1204
1205/* IO Register size in bytes */
1206#define FF_REG_AREA_SIZE 256
1207
1208/* Host Attention Register */
1209
1210#define HA_REG_OFFSET 0 /* Byte offset from register base address */
1211
1212#define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1213#define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1214#define HA_R0ATT 0x00000008 /* Bit 3 */
1215#define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1216#define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1217#define HA_R1ATT 0x00000080 /* Bit 7 */
1218#define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1219#define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1220#define HA_R2ATT 0x00000800 /* Bit 11 */
1221#define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1222#define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1223#define HA_R3ATT 0x00008000 /* Bit 15 */
1224#define HA_LATT 0x20000000 /* Bit 29 */
1225#define HA_MBATT 0x40000000 /* Bit 30 */
1226#define HA_ERATT 0x80000000 /* Bit 31 */
1227
1228#define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1229#define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1230#define HA_RXATT 0x00000008 /* Bit 3 */
1231#define HA_RXMASK 0x0000000f
1232
9399627f
JS		 1233#define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1234#define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1235#define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1236#define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1237
1238#define HA_R0_POS 3
1239#define HA_R1_POS 7
1240#define HA_R2_POS 11
1241#define HA_R3_POS 15
1242#define HA_LE_POS 29
1243#define HA_MB_POS 30
1244#define HA_ER_POS 31
dea3101e
JB		 1245/* Chip Attention Register */
1246
1247#define CA_REG_OFFSET 4 /* Byte offset from register base address */
1248
1249#define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1250#define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1251#define CA_R0ATT 0x00000008 /* Bit 3 */
1252#define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1253#define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1254#define CA_R1ATT 0x00000080 /* Bit 7 */
1255#define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1256#define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1257#define CA_R2ATT 0x00000800 /* Bit 11 */
1258#define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1259#define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1260#define CA_R3ATT 0x00008000 /* Bit 15 */
1261#define CA_MBATT 0x40000000 /* Bit 30 */
1262
1263/* Host Status Register */
1264
1265#define HS_REG_OFFSET 8 /* Byte offset from register base address */
1266
1267#define HS_MBRDY 0x00400000 /* Bit 22 */
1268#define HS_FFRDY 0x00800000 /* Bit 23 */
1269#define HS_FFER8 0x01000000 /* Bit 24 */
1270#define HS_FFER7 0x02000000 /* Bit 25 */
1271#define HS_FFER6 0x04000000 /* Bit 26 */
1272#define HS_FFER5 0x08000000 /* Bit 27 */
1273#define HS_FFER4 0x10000000 /* Bit 28 */
1274#define HS_FFER3 0x20000000 /* Bit 29 */
1275#define HS_FFER2 0x40000000 /* Bit 30 */
1276#define HS_FFER1 0x80000000 /* Bit 31 */
57127f15
JS		 1277#define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1278#define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
dea3101e
JB		 1279
1280/* Host Control Register */
1281
9399627f 1282#define HC_REG_OFFSET 12 /* Byte offset from register base address */
dea3101e
JB		 1283
1284#define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1285#define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1286#define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1287#define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1288#define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1289#define HC_INITHBI 0x02000000 /* Bit 25 */
1290#define HC_INITMB 0x04000000 /* Bit 26 */
1291#define HC_INITFF 0x08000000 /* Bit 27 */
1292#define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1293#define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1294
9399627f
JS		 1295/* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1296#define MSIX_DFLT_ID 0
1297#define MSIX_RNG0_ID 0
1298#define MSIX_RNG1_ID 1
1299#define MSIX_RNG2_ID 2
1300#define MSIX_RNG3_ID 3
1301
1302#define MSIX_LINK_ID 4
1303#define MSIX_MBOX_ID 5
1304
1305#define MSIX_SPARE0_ID 6
1306#define MSIX_SPARE1_ID 7
1307
dea3101e
JB		 1308/* Mailbox Commands */
1309#define MBX_SHUTDOWN 0x00 /* terminate testing */
1310#define MBX_LOAD_SM 0x01
1311#define MBX_READ_NV 0x02
1312#define MBX_WRITE_NV 0x03
1313#define MBX_RUN_BIU_DIAG 0x04
1314#define MBX_INIT_LINK 0x05
1315#define MBX_DOWN_LINK 0x06
1316#define MBX_CONFIG_LINK 0x07
1317#define MBX_CONFIG_RING 0x09
1318#define MBX_RESET_RING 0x0A
1319#define MBX_READ_CONFIG 0x0B
1320#define MBX_READ_RCONFIG 0x0C
1321#define MBX_READ_SPARM 0x0D
1322#define MBX_READ_STATUS 0x0E
1323#define MBX_READ_RPI 0x0F
1324#define MBX_READ_XRI 0x10
1325#define MBX_READ_REV 0x11
1326#define MBX_READ_LNK_STAT 0x12
1327#define MBX_REG_LOGIN 0x13
1328#define MBX_UNREG_LOGIN 0x14
1329#define MBX_READ_LA 0x15
1330#define MBX_CLEAR_LA 0x16
1331#define MBX_DUMP_MEMORY 0x17
1332#define MBX_DUMP_CONTEXT 0x18
1333#define MBX_RUN_DIAGS 0x19
1334#define MBX_RESTART 0x1A
1335#define MBX_UPDATE_CFG 0x1B
1336#define MBX_DOWN_LOAD 0x1C
1337#define MBX_DEL_LD_ENTRY 0x1D
1338#define MBX_RUN_PROGRAM 0x1E
1339#define MBX_SET_MASK 0x20
09372820 1340#define MBX_SET_VARIABLE 0x21
dea3101e 1341#define MBX_UNREG_D_ID 0x23
41415862 1342#define MBX_KILL_BOARD 0x24
dea3101e 1343#define MBX_CONFIG_FARP 0x25
41415862 1344#define MBX_BEACON 0x2A
9399627f 1345#define MBX_CONFIG_MSI 0x30
858c9f6c 1346#define MBX_HEARTBEAT 0x31
a8adb832
JS		 1347#define MBX_WRITE_VPARMS 0x32
1348#define MBX_ASYNCEVT_ENABLE 0x33
4fede78f
JS		 1349#define MBX_READ_EVENT_LOG_STATUS 0x37
1350#define MBX_READ_EVENT_LOG 0x38
1351#define MBX_WRITE_EVENT_LOG 0x39
dea3101e 1352
84774a4d
JS		 1353#define MBX_PORT_CAPABILITIES 0x3B
1354#define MBX_PORT_IOV_CONTROL 0x3C
1355
ed957684 1356#define MBX_CONFIG_HBQ 0x7C
dea3101e
JB		 1357#define MBX_LOAD_AREA 0x81
1358#define MBX_RUN_BIU_DIAG64 0x84
1359#define MBX_CONFIG_PORT 0x88
1360#define MBX_READ_SPARM64 0x8D
1361#define MBX_READ_RPI64 0x8F
1362#define MBX_REG_LOGIN64 0x93
1363#define MBX_READ_LA64 0x95
92d7f7b0
JS		 1364#define MBX_REG_VPI 0x96
1365#define MBX_UNREG_VPI 0x97
dea3101e 1366
09372820 1367#define MBX_WRITE_WWN 0x98
dea3101e
JB		 1368#define MBX_SET_DEBUG 0x99
1369#define MBX_LOAD_EXP_ROM 0x9C
da0436e9
JS		 1370#define MBX_SLI4_CONFIG 0x9B
1371#define MBX_SLI4_REQ_FTRS 0x9D
1372#define MBX_MAX_CMDS 0x9E
1373#define MBX_RESUME_RPI 0x9E
dea3101e 1374#define MBX_SLI2_CMD_MASK 0x80
da0436e9
JS		 1375#define MBX_REG_VFI 0x9F
1376#define MBX_REG_FCFI 0xA0
1377#define MBX_UNREG_VFI 0xA1
1378#define MBX_UNREG_FCFI 0xA2
1379#define MBX_INIT_VFI 0xA3
1380#define MBX_INIT_VPI 0xA4
dea3101e
JB		 1381
1382/* IOCB Commands */
1383
1384#define CMD_RCV_SEQUENCE_CX 0x01
1385#define CMD_XMIT_SEQUENCE_CR 0x02
1386#define CMD_XMIT_SEQUENCE_CX 0x03
1387#define CMD_XMIT_BCAST_CN 0x04
1388#define CMD_XMIT_BCAST_CX 0x05
1389#define CMD_QUE_RING_BUF_CN 0x06
1390#define CMD_QUE_XRI_BUF_CX 0x07
1391#define CMD_IOCB_CONTINUE_CN 0x08
1392#define CMD_RET_XRI_BUF_CX 0x09
1393#define CMD_ELS_REQUEST_CR 0x0A
1394#define CMD_ELS_REQUEST_CX 0x0B
1395#define CMD_RCV_ELS_REQ_CX 0x0D
1396#define CMD_ABORT_XRI_CN 0x0E
1397#define CMD_ABORT_XRI_CX 0x0F
1398#define CMD_CLOSE_XRI_CN 0x10
1399#define CMD_CLOSE_XRI_CX 0x11
1400#define CMD_CREATE_XRI_CR 0x12
1401#define CMD_CREATE_XRI_CX 0x13
1402#define CMD_GET_RPI_CN 0x14
1403#define CMD_XMIT_ELS_RSP_CX 0x15
1404#define CMD_GET_RPI_CR 0x16
1405#define CMD_XRI_ABORTED_CX 0x17
1406#define CMD_FCP_IWRITE_CR 0x18
1407#define CMD_FCP_IWRITE_CX 0x19
1408#define CMD_FCP_IREAD_CR 0x1A
1409#define CMD_FCP_IREAD_CX 0x1B
1410#define CMD_FCP_ICMND_CR 0x1C
1411#define CMD_FCP_ICMND_CX 0x1D
f5603511
JS		 1412#define CMD_FCP_TSEND_CX 0x1F
1413#define CMD_FCP_TRECEIVE_CX 0x21
1414#define CMD_FCP_TRSP_CX 0x23
1415#define CMD_FCP_AUTO_TRSP_CX 0x29
dea3101e
JB		 1416
1417#define CMD_ADAPTER_MSG 0x20
1418#define CMD_ADAPTER_DUMP 0x22
1419
1420/* SLI_2 IOCB Command Set */
1421
57127f15 1422#define CMD_ASYNC_STATUS 0x7C
dea3101e
JB		 1423#define CMD_RCV_SEQUENCE64_CX 0x81
1424#define CMD_XMIT_SEQUENCE64_CR 0x82
1425#define CMD_XMIT_SEQUENCE64_CX 0x83
1426#define CMD_XMIT_BCAST64_CN 0x84
1427#define CMD_XMIT_BCAST64_CX 0x85
1428#define CMD_QUE_RING_BUF64_CN 0x86
1429#define CMD_QUE_XRI_BUF64_CX 0x87
1430#define CMD_IOCB_CONTINUE64_CN 0x88
1431#define CMD_RET_XRI_BUF64_CX 0x89
1432#define CMD_ELS_REQUEST64_CR 0x8A
1433#define CMD_ELS_REQUEST64_CX 0x8B
1434#define CMD_ABORT_MXRI64_CN 0x8C
1435#define CMD_RCV_ELS_REQ64_CX 0x8D
1436#define CMD_XMIT_ELS_RSP64_CX 0x95
6669f9bb 1437#define CMD_XMIT_BLS_RSP64_CX 0x97
dea3101e
JB		 1438#define CMD_FCP_IWRITE64_CR 0x98
1439#define CMD_FCP_IWRITE64_CX 0x99
1440#define CMD_FCP_IREAD64_CR 0x9A
1441#define CMD_FCP_IREAD64_CX 0x9B
1442#define CMD_FCP_ICMND64_CR 0x9C
1443#define CMD_FCP_ICMND64_CX 0x9D
f5603511
JS		 1444#define CMD_FCP_TSEND64_CX 0x9F
1445#define CMD_FCP_TRECEIVE64_CX 0xA1
1446#define CMD_FCP_TRSP64_CX 0xA3
dea3101e 1447
76bb24ef 1448#define CMD_QUE_XRI64_CX 0xB3
ed957684
JS		 1449#define CMD_IOCB_RCV_SEQ64_CX 0xB5
1450#define CMD_IOCB_RCV_ELS64_CX 0xB7
3163f725 1451#define CMD_IOCB_RET_XRI64_CX 0xB9
ed957684
JS		 1452#define CMD_IOCB_RCV_CONT64_CX 0xBB
1453
dea3101e
JB		 1454#define CMD_GEN_REQUEST64_CR 0xC2
1455#define CMD_GEN_REQUEST64_CX 0xC3
1456
3163f725
JS		 1457/* Unhandled SLI-3 Commands */
1458#define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1459#define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1460#define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1461#define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1462#define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1463#define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1464#define CMD_IOCB_RET_HBQE64_CN 0xCA
1465#define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1466#define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1467#define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1468#define CMD_IOCB_LOGENTRY_CN 0x94
1469#define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1470
341af102
JS		 1471/* Data Security SLI Commands */
1472#define DSSCMD_IWRITE64_CR 0xF8
1473#define DSSCMD_IWRITE64_CX 0xF9
1474#define DSSCMD_IREAD64_CR 0xFA
1475#define DSSCMD_IREAD64_CX 0xFB
1476
1477#define CMD_MAX_IOCB_CMD 0xFB
dea3101e
JB		 1478#define CMD_IOCB_MASK 0xff
1479
1480#define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1481 iocb */
1482#define LPFC_MAX_ADPTMSG 32 /* max msg data */
1483/*
1484 * Define Status
1485 */
1486#define MBX_SUCCESS 0
1487#define MBXERR_NUM_RINGS 1
1488#define MBXERR_NUM_IOCBS 2
1489#define MBXERR_IOCBS_EXCEEDED 3
1490#define MBXERR_BAD_RING_NUMBER 4
1491#define MBXERR_MASK_ENTRIES_RANGE 5
1492#define MBXERR_MASKS_EXCEEDED 6
1493#define MBXERR_BAD_PROFILE 7
1494#define MBXERR_BAD_DEF_CLASS 8
1495#define MBXERR_BAD_MAX_RESPONDER 9
1496#define MBXERR_BAD_MAX_ORIGINATOR 10
1497#define MBXERR_RPI_REGISTERED 11
1498#define MBXERR_RPI_FULL 12
1499#define MBXERR_NO_RESOURCES 13
1500#define MBXERR_BAD_RCV_LENGTH 14
1501#define MBXERR_DMA_ERROR 15
1502#define MBXERR_ERROR 16
da0436e9 1503#define MBXERR_LINK_DOWN 0x33
dea3101e
JB		 1504#define MBX_NOT_FINISHED 255
1505
1506#define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1507#define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1508
57127f15
JS		 1509#define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1510
dea3101e
JB		 1511/*
1512 * Begin Structure Definitions for Mailbox Commands
1513 */
1514
1515typedef struct {
1516#ifdef __BIG_ENDIAN_BITFIELD
1517 uint8_t tval;
1518 uint8_t tmask;
1519 uint8_t rval;
1520 uint8_t rmask;
1521#else /* __LITTLE_ENDIAN_BITFIELD */
1522 uint8_t rmask;
1523 uint8_t rval;
1524 uint8_t tmask;
1525 uint8_t tval;
1526#endif
1527} RR_REG;
1528
1529struct ulp_bde {
1530 uint32_t bdeAddress;
1531#ifdef __BIG_ENDIAN_BITFIELD
1532 uint32_t bdeReserved:4;
1533 uint32_t bdeAddrHigh:4;
1534 uint32_t bdeSize:24;
1535#else /* __LITTLE_ENDIAN_BITFIELD */
1536 uint32_t bdeSize:24;
1537 uint32_t bdeAddrHigh:4;
1538 uint32_t bdeReserved:4;
1539#endif
1540};
1541
dea3101e
JB		 1542typedef struct ULP_BDL { /* SLI-2 */
1543#ifdef __BIG_ENDIAN_BITFIELD
1544 uint32_t bdeFlags:8; /* BDL Flags */
1545 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1546#else /* __LITTLE_ENDIAN_BITFIELD */
1547 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1548 uint32_t bdeFlags:8; /* BDL Flags */
1549#endif
1550
1551 uint32_t addrLow; /* Address 0:31 */
1552 uint32_t addrHigh; /* Address 32:63 */
1553 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1554} ULP_BDL;
1555
81301a9b
JS		 1556/*
1557 * BlockGuard Definitions
1558 */
1559
1560enum lpfc_protgrp_type {
1561 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
1562 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
1563 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
1564 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
1565};
1566
1567/* PDE Descriptors */
6c8eea54
JS		 1568#define LPFC_PDE5_DESCRIPTOR 0x85
1569#define LPFC_PDE6_DESCRIPTOR 0x86
1570#define LPFC_PDE7_DESCRIPTOR 0x87
1571
1572/* BlockGuard Opcodes */
1573#define BG_OP_IN_NODIF_OUT_CRC 0x0
1574#define BG_OP_IN_CRC_OUT_NODIF 0x1
1575#define BG_OP_IN_NODIF_OUT_CSUM 0x2
1576#define BG_OP_IN_CSUM_OUT_NODIF 0x3
1577#define BG_OP_IN_CRC_OUT_CRC 0x4
1578#define BG_OP_IN_CSUM_OUT_CSUM 0x5
1579#define BG_OP_IN_CRC_OUT_CSUM 0x6
1580#define BG_OP_IN_CSUM_OUT_CRC 0x7
1581
1582struct lpfc_pde5 {
1583 uint32_t word0;
1584#define pde5_type_SHIFT 24
1585#define pde5_type_MASK 0x000000ff
1586#define pde5_type_WORD word0
1587#define pde5_rsvd0_SHIFT 0
1588#define pde5_rsvd0_MASK 0x00ffffff
1589#define pde5_rsvd0_WORD word0
1590 uint32_t reftag; /* Reference Tag Value */
1591 uint32_t reftagtr; /* Reference Tag Translation Value */
81301a9b
JS		 1592};
1593
6c8eea54
JS		 1594struct lpfc_pde6 {
1595 uint32_t word0;
1596#define pde6_type_SHIFT 24
1597#define pde6_type_MASK 0x000000ff
1598#define pde6_type_WORD word0
1599#define pde6_rsvd0_SHIFT 0
1600#define pde6_rsvd0_MASK 0x00ffffff
1601#define pde6_rsvd0_WORD word0
1602 uint32_t word1;
1603#define pde6_rsvd1_SHIFT 26
1604#define pde6_rsvd1_MASK 0x0000003f
1605#define pde6_rsvd1_WORD word1
1606#define pde6_na_SHIFT 25
1607#define pde6_na_MASK 0x00000001
1608#define pde6_na_WORD word1
1609#define pde6_rsvd2_SHIFT 16
1610#define pde6_rsvd2_MASK 0x000001FF
1611#define pde6_rsvd2_WORD word1
1612#define pde6_apptagtr_SHIFT 0
1613#define pde6_apptagtr_MASK 0x0000ffff
1614#define pde6_apptagtr_WORD word1
1615 uint32_t word2;
1616#define pde6_optx_SHIFT 28
1617#define pde6_optx_MASK 0x0000000f
1618#define pde6_optx_WORD word2
1619#define pde6_oprx_SHIFT 24
1620#define pde6_oprx_MASK 0x0000000f
1621#define pde6_oprx_WORD word2
1622#define pde6_nr_SHIFT 23
1623#define pde6_nr_MASK 0x00000001
1624#define pde6_nr_WORD word2
1625#define pde6_ce_SHIFT 22
1626#define pde6_ce_MASK 0x00000001
1627#define pde6_ce_WORD word2
1628#define pde6_re_SHIFT 21
1629#define pde6_re_MASK 0x00000001
1630#define pde6_re_WORD word2
1631#define pde6_ae_SHIFT 20
1632#define pde6_ae_MASK 0x00000001
1633#define pde6_ae_WORD word2
1634#define pde6_ai_SHIFT 19
1635#define pde6_ai_MASK 0x00000001
1636#define pde6_ai_WORD word2
1637#define pde6_bs_SHIFT 16
1638#define pde6_bs_MASK 0x00000007
1639#define pde6_bs_WORD word2
1640#define pde6_apptagval_SHIFT 0
1641#define pde6_apptagval_MASK 0x0000ffff
1642#define pde6_apptagval_WORD word2
81301a9b
JS		 1643};
1644
81301a9b 1645
dea3101e
JB		 1646/* Structure for MB Command LOAD_SM and DOWN_LOAD */
1647
1648typedef struct {
1649#ifdef __BIG_ENDIAN_BITFIELD
1650 uint32_t rsvd2:25;
1651 uint32_t acknowledgment:1;
1652 uint32_t version:1;
1653 uint32_t erase_or_prog:1;
1654 uint32_t update_flash:1;
1655 uint32_t update_ram:1;
1656 uint32_t method:1;
1657 uint32_t load_cmplt:1;
1658#else /* __LITTLE_ENDIAN_BITFIELD */
1659 uint32_t load_cmplt:1;
1660 uint32_t method:1;
1661 uint32_t update_ram:1;
1662 uint32_t update_flash:1;
1663 uint32_t erase_or_prog:1;
1664 uint32_t version:1;
1665 uint32_t acknowledgment:1;
1666 uint32_t rsvd2:25;
1667#endif
1668
1669 uint32_t dl_to_adr_low;
1670 uint32_t dl_to_adr_high;
1671 uint32_t dl_len;
1672 union {
1673 uint32_t dl_from_mbx_offset;
1674 struct ulp_bde dl_from_bde;
1675 struct ulp_bde64 dl_from_bde64;
1676 } un;
1677
1678} LOAD_SM_VAR;
1679
1680/* Structure for MB Command READ_NVPARM (02) */
1681
1682typedef struct {
1683 uint32_t rsvd1[3]; /* Read as all one's */
1684 uint32_t rsvd2; /* Read as all zero's */
1685 uint32_t portname[2]; /* N_PORT name */
1686 uint32_t nodename[2]; /* NODE name */
1687
1688#ifdef __BIG_ENDIAN_BITFIELD
1689 uint32_t pref_DID:24;
1690 uint32_t hardAL_PA:8;
1691#else /* __LITTLE_ENDIAN_BITFIELD */
1692 uint32_t hardAL_PA:8;
1693 uint32_t pref_DID:24;
1694#endif
1695
1696 uint32_t rsvd3[21]; /* Read as all one's */
1697} READ_NV_VAR;
1698
1699/* Structure for MB Command WRITE_NVPARMS (03) */
1700
1701typedef struct {
1702 uint32_t rsvd1[3]; /* Must be all one's */
1703 uint32_t rsvd2; /* Must be all zero's */
1704 uint32_t portname[2]; /* N_PORT name */
1705 uint32_t nodename[2]; /* NODE name */
1706
1707#ifdef __BIG_ENDIAN_BITFIELD
1708 uint32_t pref_DID:24;
1709 uint32_t hardAL_PA:8;
1710#else /* __LITTLE_ENDIAN_BITFIELD */
1711 uint32_t hardAL_PA:8;
1712 uint32_t pref_DID:24;
1713#endif
1714
1715 uint32_t rsvd3[21]; /* Must be all one's */
1716} WRITE_NV_VAR;
1717
1718/* Structure for MB Command RUN_BIU_DIAG (04) */
1719/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1720
1721typedef struct {
1722 uint32_t rsvd1;
1723 union {
1724 struct {
1725 struct ulp_bde xmit_bde;
1726 struct ulp_bde rcv_bde;
1727 } s1;
1728 struct {
1729 struct ulp_bde64 xmit_bde64;
1730 struct ulp_bde64 rcv_bde64;
1731 } s2;
1732 } un;
1733} BIU_DIAG_VAR;
1734
c7495937
JS		 1735/* Structure for MB command READ_EVENT_LOG (0x38) */
1736struct READ_EVENT_LOG_VAR {
1737 uint32_t word1;
1738#define lpfc_event_log_SHIFT 29
1739#define lpfc_event_log_MASK 0x00000001
1740#define lpfc_event_log_WORD word1
1741#define USE_MAILBOX_RESPONSE 1
1742 uint32_t offset;
1743 struct ulp_bde64 rcv_bde64;
1744};
1745
dea3101e
JB		 1746/* Structure for MB Command INIT_LINK (05) */
1747
1748typedef struct {
1749#ifdef __BIG_ENDIAN_BITFIELD
1750 uint32_t rsvd1:24;
1751 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1752#else /* __LITTLE_ENDIAN_BITFIELD */
1753 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1754 uint32_t rsvd1:24;
1755#endif
1756
1757#ifdef __BIG_ENDIAN_BITFIELD
1758 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1759 uint8_t rsvd2;
1760 uint16_t link_flags;
1761#else /* __LITTLE_ENDIAN_BITFIELD */
1762 uint16_t link_flags;
1763 uint8_t rsvd2;
1764 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1765#endif
1766
1767#define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1768#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1769#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1770#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1771#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
92d7f7b0 1772#define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
dea3101e
JB		 1773#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1774
1775#define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1776#define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
4b0b91d4 1777#define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
dea3101e
JB		 1778
1779 uint32_t link_speed;
1780#define LINK_SPEED_AUTO 0 /* Auto selection */
1781#define LINK_SPEED_1G 1 /* 1 Gigabaud */
1782#define LINK_SPEED_2G 2 /* 2 Gigabaud */
1783#define LINK_SPEED_4G 4 /* 4 Gigabaud */
b87eab38 1784#define LINK_SPEED_8G 8 /* 8 Gigabaud */
dea3101e
JB		 1785#define LINK_SPEED_10G 16 /* 10 Gigabaud */
1786
1787} INIT_LINK_VAR;
1788
1789/* Structure for MB Command DOWN_LINK (06) */
1790
1791typedef struct {
1792 uint32_t rsvd1;
1793} DOWN_LINK_VAR;
1794
1795/* Structure for MB Command CONFIG_LINK (07) */
1796
1797typedef struct {
1798#ifdef __BIG_ENDIAN_BITFIELD
1799 uint32_t cr:1;
1800 uint32_t ci:1;
1801 uint32_t cr_delay:6;
1802 uint32_t cr_count:8;
1803 uint32_t rsvd1:8;
1804 uint32_t MaxBBC:8;
1805#else /* __LITTLE_ENDIAN_BITFIELD */
1806 uint32_t MaxBBC:8;
1807 uint32_t rsvd1:8;
1808 uint32_t cr_count:8;
1809 uint32_t cr_delay:6;
1810 uint32_t ci:1;
1811 uint32_t cr:1;
1812#endif
1813
1814 uint32_t myId;
1815 uint32_t rsvd2;
1816 uint32_t edtov;
1817 uint32_t arbtov;
1818 uint32_t ratov;
1819 uint32_t rttov;
1820 uint32_t altov;
1821 uint32_t crtov;
1822 uint32_t citov;
1823#ifdef __BIG_ENDIAN_BITFIELD
1824 uint32_t rrq_enable:1;
1825 uint32_t rrq_immed:1;
1826 uint32_t rsvd4:29;
1827 uint32_t ack0_enable:1;
1828#else /* __LITTLE_ENDIAN_BITFIELD */
1829 uint32_t ack0_enable:1;
1830 uint32_t rsvd4:29;
1831 uint32_t rrq_immed:1;
1832 uint32_t rrq_enable:1;
1833#endif
1834} CONFIG_LINK;
1835
1836/* Structure for MB Command PART_SLIM (08)
1837 * will be removed since SLI1 is no longer supported!
1838 */
1839typedef struct {
1840#ifdef __BIG_ENDIAN_BITFIELD
1841 uint16_t offCiocb;
1842 uint16_t numCiocb;
1843 uint16_t offRiocb;
1844 uint16_t numRiocb;
1845#else /* __LITTLE_ENDIAN_BITFIELD */
1846 uint16_t numCiocb;
1847 uint16_t offCiocb;
1848 uint16_t numRiocb;
1849 uint16_t offRiocb;
1850#endif
1851} RING_DEF;
1852
1853typedef struct {
1854#ifdef __BIG_ENDIAN_BITFIELD
1855 uint32_t unused1:24;
1856 uint32_t numRing:8;
1857#else /* __LITTLE_ENDIAN_BITFIELD */
1858 uint32_t numRing:8;
1859 uint32_t unused1:24;
1860#endif
1861
1862 RING_DEF ringdef[4];
1863 uint32_t hbainit;
1864} PART_SLIM_VAR;
1865
1866/* Structure for MB Command CONFIG_RING (09) */
1867
1868typedef struct {
1869#ifdef __BIG_ENDIAN_BITFIELD
1870 uint32_t unused2:6;
1871 uint32_t recvSeq:1;
1872 uint32_t recvNotify:1;
1873 uint32_t numMask:8;
1874 uint32_t profile:8;
1875 uint32_t unused1:4;
1876 uint32_t ring:4;
1877#else /* __LITTLE_ENDIAN_BITFIELD */
1878 uint32_t ring:4;
1879 uint32_t unused1:4;
1880 uint32_t profile:8;
1881 uint32_t numMask:8;
1882 uint32_t recvNotify:1;
1883 uint32_t recvSeq:1;
1884 uint32_t unused2:6;
1885#endif
1886
1887#ifdef __BIG_ENDIAN_BITFIELD
1888 uint16_t maxRespXchg;
1889 uint16_t maxOrigXchg;
1890#else /* __LITTLE_ENDIAN_BITFIELD */
1891 uint16_t maxOrigXchg;
1892 uint16_t maxRespXchg;
1893#endif
1894
1895 RR_REG rrRegs[6];
1896} CONFIG_RING_VAR;
1897
1898/* Structure for MB Command RESET_RING (10) */
1899
1900typedef struct {
1901 uint32_t ring_no;
1902} RESET_RING_VAR;
1903
1904/* Structure for MB Command READ_CONFIG (11) */
1905
1906typedef struct {
1907#ifdef __BIG_ENDIAN_BITFIELD
1908 uint32_t cr:1;
1909 uint32_t ci:1;
1910 uint32_t cr_delay:6;
1911 uint32_t cr_count:8;
1912 uint32_t InitBBC:8;
1913 uint32_t MaxBBC:8;
1914#else /* __LITTLE_ENDIAN_BITFIELD */
1915 uint32_t MaxBBC:8;
1916 uint32_t InitBBC:8;
1917 uint32_t cr_count:8;
1918 uint32_t cr_delay:6;
1919 uint32_t ci:1;
1920 uint32_t cr:1;
1921#endif
1922
1923#ifdef __BIG_ENDIAN_BITFIELD
1924 uint32_t topology:8;
1925 uint32_t myDid:24;
1926#else /* __LITTLE_ENDIAN_BITFIELD */
1927 uint32_t myDid:24;
1928 uint32_t topology:8;
1929#endif
1930
1931 /* Defines for topology (defined previously) */
1932#ifdef __BIG_ENDIAN_BITFIELD
1933 uint32_t AR:1;
1934 uint32_t IR:1;
1935 uint32_t rsvd1:29;
1936 uint32_t ack0:1;
1937#else /* __LITTLE_ENDIAN_BITFIELD */
1938 uint32_t ack0:1;
1939 uint32_t rsvd1:29;
1940 uint32_t IR:1;
1941 uint32_t AR:1;
1942#endif
1943
1944 uint32_t edtov;
1945 uint32_t arbtov;
1946 uint32_t ratov;
1947 uint32_t rttov;
1948 uint32_t altov;
1949 uint32_t lmt;
74b72a59
JW		 1950#define LMT_RESERVED 0x000 /* Not used */
1951#define LMT_1Gb 0x004
1952#define LMT_2Gb 0x008
1953#define LMT_4Gb 0x040
1954#define LMT_8Gb 0x080
1955#define LMT_10Gb 0x100
dea3101e
JB		 1956 uint32_t rsvd2;
1957 uint32_t rsvd3;
1958 uint32_t max_xri;
1959 uint32_t max_iocb;
1960 uint32_t max_rpi;
1961 uint32_t avail_xri;
1962 uint32_t avail_iocb;
1963 uint32_t avail_rpi;
858c9f6c
JS		 1964 uint32_t max_vpi;
1965 uint32_t rsvd4;
1966 uint32_t rsvd5;
1967 uint32_t avail_vpi;
dea3101e
JB		 1968} READ_CONFIG_VAR;
1969
1970/* Structure for MB Command READ_RCONFIG (12) */
1971
1972typedef struct {
1973#ifdef __BIG_ENDIAN_BITFIELD
1974 uint32_t rsvd2:7;
1975 uint32_t recvNotify:1;
1976 uint32_t numMask:8;
1977 uint32_t profile:8;
1978 uint32_t rsvd1:4;
1979 uint32_t ring:4;
1980#else /* __LITTLE_ENDIAN_BITFIELD */
1981 uint32_t ring:4;
1982 uint32_t rsvd1:4;
1983 uint32_t profile:8;
1984 uint32_t numMask:8;
1985 uint32_t recvNotify:1;
1986 uint32_t rsvd2:7;
1987#endif
1988
1989#ifdef __BIG_ENDIAN_BITFIELD
1990 uint16_t maxResp;
1991 uint16_t maxOrig;
1992#else /* __LITTLE_ENDIAN_BITFIELD */
1993 uint16_t maxOrig;
1994 uint16_t maxResp;
1995#endif
1996
1997 RR_REG rrRegs[6];
1998
1999#ifdef __BIG_ENDIAN_BITFIELD
2000 uint16_t cmdRingOffset;
2001 uint16_t cmdEntryCnt;
2002 uint16_t rspRingOffset;
2003 uint16_t rspEntryCnt;
2004 uint16_t nextCmdOffset;
2005 uint16_t rsvd3;
2006 uint16_t nextRspOffset;
2007 uint16_t rsvd4;
2008#else /* __LITTLE_ENDIAN_BITFIELD */
2009 uint16_t cmdEntryCnt;
2010 uint16_t cmdRingOffset;
2011 uint16_t rspEntryCnt;
2012 uint16_t rspRingOffset;
2013 uint16_t rsvd3;
2014 uint16_t nextCmdOffset;
2015 uint16_t rsvd4;
2016 uint16_t nextRspOffset;
2017#endif
2018} READ_RCONF_VAR;
2019
2020/* Structure for MB Command READ_SPARM (13) */
2021/* Structure for MB Command READ_SPARM64 (0x8D) */
2022
2023typedef struct {
2024 uint32_t rsvd1;
2025 uint32_t rsvd2;
2026 union {
2027 struct ulp_bde sp; /* This BDE points to struct serv_parm
2028 structure */
2029 struct ulp_bde64 sp64;
2030 } un;
ed957684
JS		 2031#ifdef __BIG_ENDIAN_BITFIELD
2032 uint16_t rsvd3;
2033 uint16_t vpi;
2034#else /* __LITTLE_ENDIAN_BITFIELD */
2035 uint16_t vpi;
2036 uint16_t rsvd3;
2037#endif
dea3101e
JB		 2038} READ_SPARM_VAR;
2039
2040/* Structure for MB Command READ_STATUS (14) */
2041
2042typedef struct {
2043#ifdef __BIG_ENDIAN_BITFIELD
2044 uint32_t rsvd1:31;
2045 uint32_t clrCounters:1;
2046 uint16_t activeXriCnt;
2047 uint16_t activeRpiCnt;
2048#else /* __LITTLE_ENDIAN_BITFIELD */
2049 uint32_t clrCounters:1;
2050 uint32_t rsvd1:31;
2051 uint16_t activeRpiCnt;
2052 uint16_t activeXriCnt;
2053#endif
2054
2055 uint32_t xmitByteCnt;
2056 uint32_t rcvByteCnt;
2057 uint32_t xmitFrameCnt;
2058 uint32_t rcvFrameCnt;
2059 uint32_t xmitSeqCnt;
2060 uint32_t rcvSeqCnt;
2061 uint32_t totalOrigExchanges;
2062 uint32_t totalRespExchanges;
2063 uint32_t rcvPbsyCnt;
2064 uint32_t rcvFbsyCnt;
2065} READ_STATUS_VAR;
2066
2067/* Structure for MB Command READ_RPI (15) */
2068/* Structure for MB Command READ_RPI64 (0x8F) */
2069
2070typedef struct {
2071#ifdef __BIG_ENDIAN_BITFIELD
2072 uint16_t nextRpi;
2073 uint16_t reqRpi;
2074 uint32_t rsvd2:8;
2075 uint32_t DID:24;
2076#else /* __LITTLE_ENDIAN_BITFIELD */
2077 uint16_t reqRpi;
2078 uint16_t nextRpi;
2079 uint32_t DID:24;
2080 uint32_t rsvd2:8;
2081#endif
2082
2083 union {
2084 struct ulp_bde sp;
2085 struct ulp_bde64 sp64;
2086 } un;
2087
2088} READ_RPI_VAR;
2089
2090/* Structure for MB Command READ_XRI (16) */
2091
2092typedef struct {
2093#ifdef __BIG_ENDIAN_BITFIELD
2094 uint16_t nextXri;
2095 uint16_t reqXri;
2096 uint16_t rsvd1;
2097 uint16_t rpi;
2098 uint32_t rsvd2:8;
2099 uint32_t DID:24;
2100 uint32_t rsvd3:8;
2101 uint32_t SID:24;
2102 uint32_t rsvd4;
2103 uint8_t seqId;
2104 uint8_t rsvd5;
2105 uint16_t seqCount;
2106 uint16_t oxId;
2107 uint16_t rxId;
2108 uint32_t rsvd6:30;
2109 uint32_t si:1;
2110 uint32_t exchOrig:1;
2111#else /* __LITTLE_ENDIAN_BITFIELD */
2112 uint16_t reqXri;
2113 uint16_t nextXri;
2114 uint16_t rpi;
2115 uint16_t rsvd1;
2116 uint32_t DID:24;
2117 uint32_t rsvd2:8;
2118 uint32_t SID:24;
2119 uint32_t rsvd3:8;
2120 uint32_t rsvd4;
2121 uint16_t seqCount;
2122 uint8_t rsvd5;
2123 uint8_t seqId;
2124 uint16_t rxId;
2125 uint16_t oxId;
2126 uint32_t exchOrig:1;
2127 uint32_t si:1;
2128 uint32_t rsvd6:30;
2129#endif
2130} READ_XRI_VAR;
2131
2132/* Structure for MB Command READ_REV (17) */
2133
2134typedef struct {
2135#ifdef __BIG_ENDIAN_BITFIELD
2136 uint32_t cv:1;
2137 uint32_t rr:1;
ed957684
JS		 2138 uint32_t rsvd2:2;
2139 uint32_t v3req:1;
2140 uint32_t v3rsp:1;
2141 uint32_t rsvd1:25;
dea3101e
JB		 2142 uint32_t rv:1;
2143#else /* __LITTLE_ENDIAN_BITFIELD */
2144 uint32_t rv:1;
ed957684
JS		 2145 uint32_t rsvd1:25;
2146 uint32_t v3rsp:1;
2147 uint32_t v3req:1;
2148 uint32_t rsvd2:2;
dea3101e
JB		 2149 uint32_t rr:1;
2150 uint32_t cv:1;
2151#endif
2152
2153 uint32_t biuRev;
2154 uint32_t smRev;
2155 union {
2156 uint32_t smFwRev;
2157 struct {
2158#ifdef __BIG_ENDIAN_BITFIELD
2159 uint8_t ProgType;
2160 uint8_t ProgId;
2161 uint16_t ProgVer:4;
2162 uint16_t ProgRev:4;
2163 uint16_t ProgFixLvl:2;
2164 uint16_t ProgDistType:2;
2165 uint16_t DistCnt:4;
2166#else /* __LITTLE_ENDIAN_BITFIELD */
2167 uint16_t DistCnt:4;
2168 uint16_t ProgDistType:2;
2169 uint16_t ProgFixLvl:2;
2170 uint16_t ProgRev:4;
2171 uint16_t ProgVer:4;
2172 uint8_t ProgId;
2173 uint8_t ProgType;
2174#endif
2175
2176 } b;
2177 } un;
2178 uint32_t endecRev;
2179#ifdef __BIG_ENDIAN_BITFIELD
2180 uint8_t feaLevelHigh;
2181 uint8_t feaLevelLow;
2182 uint8_t fcphHigh;
2183 uint8_t fcphLow;
2184#else /* __LITTLE_ENDIAN_BITFIELD */
2185 uint8_t fcphLow;
2186 uint8_t fcphHigh;
2187 uint8_t feaLevelLow;
2188 uint8_t feaLevelHigh;
2189#endif
2190
2191 uint32_t postKernRev;
2192 uint32_t opFwRev;
2193 uint8_t opFwName[16];
2194 uint32_t sli1FwRev;
2195 uint8_t sli1FwName[16];
2196 uint32_t sli2FwRev;
2197 uint8_t sli2FwName[16];
ed957684
JS		 2198 uint32_t sli3Feat;
2199 uint32_t RandomData[6];
dea3101e
JB		 2200} READ_REV_VAR;
2201
2202/* Structure for MB Command READ_LINK_STAT (18) */
2203
2204typedef struct {
2205 uint32_t rsvd1;
2206 uint32_t linkFailureCnt;
2207 uint32_t lossSyncCnt;
2208
2209 uint32_t lossSignalCnt;
2210 uint32_t primSeqErrCnt;
2211 uint32_t invalidXmitWord;
2212 uint32_t crcCnt;
2213 uint32_t primSeqTimeout;
2214 uint32_t elasticOverrun;
2215 uint32_t arbTimeout;
2216} READ_LNK_VAR;
2217
2218/* Structure for MB Command REG_LOGIN (19) */
2219/* Structure for MB Command REG_LOGIN64 (0x93) */
2220
2221typedef struct {
2222#ifdef __BIG_ENDIAN_BITFIELD
2223 uint16_t rsvd1;
2224 uint16_t rpi;
2225 uint32_t rsvd2:8;
2226 uint32_t did:24;
2227#else /* __LITTLE_ENDIAN_BITFIELD */
2228 uint16_t rpi;
2229 uint16_t rsvd1;
2230 uint32_t did:24;
2231 uint32_t rsvd2:8;
2232#endif
2233
2234 union {
2235 struct ulp_bde sp;
2236 struct ulp_bde64 sp64;
2237 } un;
2238
ed957684
JS		 2239#ifdef __BIG_ENDIAN_BITFIELD
2240 uint16_t rsvd6;
2241 uint16_t vpi;
2242#else /* __LITTLE_ENDIAN_BITFIELD */
2243 uint16_t vpi;
2244 uint16_t rsvd6;
2245#endif
2246
dea3101e
JB		 2247} REG_LOGIN_VAR;
2248
2249/* Word 30 contents for REG_LOGIN */
2250typedef union {
2251 struct {
2252#ifdef __BIG_ENDIAN_BITFIELD
2253 uint16_t rsvd1:12;
2254 uint16_t wd30_class:4;
2255 uint16_t xri;
2256#else /* __LITTLE_ENDIAN_BITFIELD */
2257 uint16_t xri;
2258 uint16_t wd30_class:4;
2259 uint16_t rsvd1:12;
2260#endif
2261 } f;
2262 uint32_t word;
2263} REG_WD30;
2264
2265/* Structure for MB Command UNREG_LOGIN (20) */
2266
2267typedef struct {
2268#ifdef __BIG_ENDIAN_BITFIELD
2269 uint16_t rsvd1;
2270 uint16_t rpi;
ed957684
JS		 2271 uint32_t rsvd2;
2272 uint32_t rsvd3;
2273 uint32_t rsvd4;
2274 uint32_t rsvd5;
2275 uint16_t rsvd6;
2276 uint16_t vpi;
dea3101e
JB		 2277#else /* __LITTLE_ENDIAN_BITFIELD */
2278 uint16_t rpi;
2279 uint16_t rsvd1;
ed957684
JS		 2280 uint32_t rsvd2;
2281 uint32_t rsvd3;
2282 uint32_t rsvd4;
2283 uint32_t rsvd5;
2284 uint16_t vpi;
2285 uint16_t rsvd6;
dea3101e
JB		 2286#endif
2287} UNREG_LOGIN_VAR;
2288
92d7f7b0
JS		 2289/* Structure for MB Command REG_VPI (0x96) */
2290typedef struct {
2291#ifdef __BIG_ENDIAN_BITFIELD
2292 uint32_t rsvd1;
2293 uint32_t rsvd2:8;
2294 uint32_t sid:24;
c868595d 2295 uint32_t wwn[2];
92d7f7b0 2296 uint32_t rsvd5;
da0436e9 2297 uint16_t vfi;
92d7f7b0
JS		 2298 uint16_t vpi;
2299#else /* __LITTLE_ENDIAN */
2300 uint32_t rsvd1;
2301 uint32_t sid:24;
2302 uint32_t rsvd2:8;
c868595d 2303 uint32_t wwn[2];
92d7f7b0
JS		 2304 uint32_t rsvd5;
2305 uint16_t vpi;
da0436e9 2306 uint16_t vfi;
92d7f7b0
JS		 2307#endif
2308} REG_VPI_VAR;
2309
2310/* Structure for MB Command UNREG_VPI (0x97) */
2311typedef struct {
2312 uint32_t rsvd1;
6669f9bb
JS		 2313#ifdef __BIG_ENDIAN_BITFIELD
2314 uint16_t rsvd2;
2315 uint16_t sli4_vpi;
2316#else /* __LITTLE_ENDIAN */
2317 uint16_t sli4_vpi;
2318 uint16_t rsvd2;
2319#endif
92d7f7b0
JS		 2320 uint32_t rsvd3;
2321 uint32_t rsvd4;
2322 uint32_t rsvd5;
2323#ifdef __BIG_ENDIAN_BITFIELD
2324 uint16_t rsvd6;
2325 uint16_t vpi;
2326#else /* __LITTLE_ENDIAN */
2327 uint16_t vpi;
2328 uint16_t rsvd6;
2329#endif
2330} UNREG_VPI_VAR;
2331
dea3101e
JB		 2332/* Structure for MB Command UNREG_D_ID (0x23) */
2333
2334typedef struct {
2335 uint32_t did;
ed957684
JS		 2336 uint32_t rsvd2;
2337 uint32_t rsvd3;
2338 uint32_t rsvd4;
2339 uint32_t rsvd5;
2340#ifdef __BIG_ENDIAN_BITFIELD
2341 uint16_t rsvd6;
2342 uint16_t vpi;
2343#else
2344 uint16_t vpi;
2345 uint16_t rsvd6;
2346#endif
dea3101e
JB		 2347} UNREG_D_ID_VAR;
2348
2349/* Structure for MB Command READ_LA (21) */
2350/* Structure for MB Command READ_LA64 (0x95) */
2351
2352typedef struct {
2353 uint32_t eventTag; /* Event tag */
2354#ifdef __BIG_ENDIAN_BITFIELD
84774a4d
JS		 2355 uint32_t rsvd1:19;
2356 uint32_t fa:1;
2357 uint32_t mm:1; /* Menlo Maintenance mode enabled */
2358 uint32_t rx:1;
dea3101e
JB		 2359 uint32_t pb:1;
2360 uint32_t il:1;
2361 uint32_t attType:8;
2362#else /* __LITTLE_ENDIAN_BITFIELD */
2363 uint32_t attType:8;
2364 uint32_t il:1;
2365 uint32_t pb:1;
84774a4d
JS		 2366 uint32_t rx:1;
2367 uint32_t mm:1;
2368 uint32_t fa:1;
2369 uint32_t rsvd1:19;
dea3101e
JB		 2370#endif
2371
2372#define AT_RESERVED 0x00 /* Reserved - attType */
2373#define AT_LINK_UP 0x01 /* Link is up */
2374#define AT_LINK_DOWN 0x02 /* Link is down */
2375
2376#ifdef __BIG_ENDIAN_BITFIELD
2377 uint8_t granted_AL_PA;
2378 uint8_t lipAlPs;
2379 uint8_t lipType;
2380 uint8_t topology;
2381#else /* __LITTLE_ENDIAN_BITFIELD */
2382 uint8_t topology;
2383 uint8_t lipType;
2384 uint8_t lipAlPs;
2385 uint8_t granted_AL_PA;
2386#endif
2387
2388#define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2389#define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
84774a4d 2390#define TOPOLOGY_LNK_MENLO_MAINTENANCE 0x05 /* maint mode zephtr to menlo */
dea3101e
JB		 2391
2392 union {
2393 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer
2394 to */
2395 /* store the LILP AL_PA position map into */
2396 struct ulp_bde64 lilpBde64;
2397 } un;
2398
2399#ifdef __BIG_ENDIAN_BITFIELD
2400 uint32_t Dlu:1;
2401 uint32_t Dtf:1;
2402 uint32_t Drsvd2:14;
2403 uint32_t DlnkSpeed:8;
2404 uint32_t DnlPort:4;
2405 uint32_t Dtx:2;
2406 uint32_t Drx:2;
2407#else /* __LITTLE_ENDIAN_BITFIELD */
2408 uint32_t Drx:2;
2409 uint32_t Dtx:2;
2410 uint32_t DnlPort:4;
2411 uint32_t DlnkSpeed:8;
2412 uint32_t Drsvd2:14;
2413 uint32_t Dtf:1;
2414 uint32_t Dlu:1;
2415#endif
2416
2417#ifdef __BIG_ENDIAN_BITFIELD
2418 uint32_t Ulu:1;
2419 uint32_t Utf:1;
2420 uint32_t Ursvd2:14;
2421 uint32_t UlnkSpeed:8;
2422 uint32_t UnlPort:4;
2423 uint32_t Utx:2;
2424 uint32_t Urx:2;
2425#else /* __LITTLE_ENDIAN_BITFIELD */
2426 uint32_t Urx:2;
2427 uint32_t Utx:2;
2428 uint32_t UnlPort:4;
2429 uint32_t UlnkSpeed:8;
2430 uint32_t Ursvd2:14;
2431 uint32_t Utf:1;
2432 uint32_t Ulu:1;
2433#endif
2434
2435#define LA_UNKNW_LINK 0x0 /* lnkSpeed */
2436#define LA_1GHZ_LINK 0x04 /* lnkSpeed */
2437#define LA_2GHZ_LINK 0x08 /* lnkSpeed */
2438#define LA_4GHZ_LINK 0x10 /* lnkSpeed */
2439#define LA_8GHZ_LINK 0x20 /* lnkSpeed */
2440#define LA_10GHZ_LINK 0x40 /* lnkSpeed */
2441
2442} READ_LA_VAR;
2443
2444/* Structure for MB Command CLEAR_LA (22) */
2445
2446typedef struct {
2447 uint32_t eventTag; /* Event tag */
2448 uint32_t rsvd1;
2449} CLEAR_LA_VAR;
2450
2451/* Structure for MB Command DUMP */
2452
2453typedef struct {
2454#ifdef __BIG_ENDIAN_BITFIELD
2455 uint32_t rsvd:25;
2456 uint32_t ra:1;
2457 uint32_t co:1;
2458 uint32_t cv:1;
2459 uint32_t type:4;
2460 uint32_t entry_index:16;
2461 uint32_t region_id:16;
2462#else /* __LITTLE_ENDIAN_BITFIELD */
2463 uint32_t type:4;
2464 uint32_t cv:1;
2465 uint32_t co:1;
2466 uint32_t ra:1;
2467 uint32_t rsvd:25;
2468 uint32_t region_id:16;
2469 uint32_t entry_index:16;
2470#endif
2471
da0436e9 2472 uint32_t sli4_length;
dea3101e
JB		 2473 uint32_t word_cnt;
2474 uint32_t resp_offset;
2475} DUMP_VAR;
2476
2477#define DMP_MEM_REG 0x1
2478#define DMP_NV_PARAMS 0x2
2479
2480#define DMP_REGION_VPD 0xe
2481#define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2482#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2483#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2484
da0436e9
JS		 2485#define DMP_REGION_VPORT 0x16 /* VPort info region */
2486#define DMP_VPORT_REGION_SIZE 0x200
2487#define DMP_MBOX_OFFSET_WORD 0x5
2488
6c8eea54
JS		 2489#define DMP_REGION_23 0x17 /* fcoe param and port state region */
2490#define DMP_RGN23_SIZE 0x400
da0436e9 2491
97207482
JS		 2492#define WAKE_UP_PARMS_REGION_ID 4
2493#define WAKE_UP_PARMS_WORD_SIZE 15
2494
da0436e9
JS		 2495struct vport_rec {
2496 uint8_t wwpn[8];
2497 uint8_t wwnn[8];
2498};
2499
2500#define VPORT_INFO_SIG 0x32324752
2501#define VPORT_INFO_REV_MASK 0xff
2502#define VPORT_INFO_REV 0x1
2503#define MAX_STATIC_VPORT_COUNT 16
2504struct static_vport_info {
6c8eea54 2505 uint32_t signature;
da0436e9 2506 uint32_t rev;
6c8eea54 2507 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
da0436e9
JS		 2508 uint32_t resvd[66];
2509};
2510
97207482
JS		 2511/* Option rom version structure */
2512struct prog_id {
2513#ifdef __BIG_ENDIAN_BITFIELD
2514 uint8_t type;
2515 uint8_t id;
2516 uint32_t ver:4; /* Major Version */
2517 uint32_t rev:4; /* Revision */
2518 uint32_t lev:2; /* Level */
2519 uint32_t dist:2; /* Dist Type */
2520 uint32_t num:4; /* number after dist type */
2521#else /* __LITTLE_ENDIAN_BITFIELD */
2522 uint32_t num:4; /* number after dist type */
2523 uint32_t dist:2; /* Dist Type */
2524 uint32_t lev:2; /* Level */
2525 uint32_t rev:4; /* Revision */
2526 uint32_t ver:4; /* Major Version */
2527 uint8_t id;
2528 uint8_t type;
2529#endif
2530};
2531
d7c255b2
JS		 2532/* Structure for MB Command UPDATE_CFG (0x1B) */
2533
2534struct update_cfg_var {
2535#ifdef __BIG_ENDIAN_BITFIELD
2536 uint32_t rsvd2:16;
2537 uint32_t type:8;
2538 uint32_t rsvd:1;
2539 uint32_t ra:1;
2540 uint32_t co:1;
2541 uint32_t cv:1;
2542 uint32_t req:4;
2543 uint32_t entry_length:16;
2544 uint32_t region_id:16;
2545#else /* __LITTLE_ENDIAN_BITFIELD */
2546 uint32_t req:4;
2547 uint32_t cv:1;
2548 uint32_t co:1;
2549 uint32_t ra:1;
2550 uint32_t rsvd:1;
2551 uint32_t type:8;
2552 uint32_t rsvd2:16;
2553 uint32_t region_id:16;
2554 uint32_t entry_length:16;
2555#endif
2556
2557 uint32_t resp_info;
2558 uint32_t byte_cnt;
2559 uint32_t data_offset;
2560};
2561
ed957684
JS		 2562struct hbq_mask {
2563#ifdef __BIG_ENDIAN_BITFIELD
2564 uint8_t tmatch;
2565 uint8_t tmask;
2566 uint8_t rctlmatch;
2567 uint8_t rctlmask;
2568#else /* __LITTLE_ENDIAN */
2569 uint8_t rctlmask;
2570 uint8_t rctlmatch;
2571 uint8_t tmask;
2572 uint8_t tmatch;
2573#endif
2574};
2575
2576
2577/* Structure for MB Command CONFIG_HBQ (7c) */
2578
2579struct config_hbq_var {
2580#ifdef __BIG_ENDIAN_BITFIELD
2581 uint32_t rsvd1 :7;
2582 uint32_t recvNotify :1; /* Receive Notification */
2583 uint32_t numMask :8; /* # Mask Entries */
2584 uint32_t profile :8; /* Selection Profile */
2585 uint32_t rsvd2 :8;
2586#else /* __LITTLE_ENDIAN */
2587 uint32_t rsvd2 :8;
2588 uint32_t profile :8; /* Selection Profile */
2589 uint32_t numMask :8; /* # Mask Entries */
2590 uint32_t recvNotify :1; /* Receive Notification */
2591 uint32_t rsvd1 :7;
2592#endif
2593
2594#ifdef __BIG_ENDIAN_BITFIELD
2595 uint32_t hbqId :16;
2596 uint32_t rsvd3 :12;
2597 uint32_t ringMask :4;
2598#else /* __LITTLE_ENDIAN */
2599 uint32_t ringMask :4;
2600 uint32_t rsvd3 :12;
2601 uint32_t hbqId :16;
2602#endif
2603
2604#ifdef __BIG_ENDIAN_BITFIELD
2605 uint32_t entry_count :16;
2606 uint32_t rsvd4 :8;
2607 uint32_t headerLen :8;
2608#else /* __LITTLE_ENDIAN */
2609 uint32_t headerLen :8;
2610 uint32_t rsvd4 :8;
2611 uint32_t entry_count :16;
2612#endif
2613
2614 uint32_t hbqaddrLow;
2615 uint32_t hbqaddrHigh;
2616
2617#ifdef __BIG_ENDIAN_BITFIELD
2618 uint32_t rsvd5 :31;
2619 uint32_t logEntry :1;
2620#else /* __LITTLE_ENDIAN */
2621 uint32_t logEntry :1;
2622 uint32_t rsvd5 :31;
2623#endif
2624
2625 uint32_t rsvd6; /* w7 */
2626 uint32_t rsvd7; /* w8 */
2627 uint32_t rsvd8; /* w9 */
2628
2629 struct hbq_mask hbqMasks[6];
2630
2631
2632 union {
2633 uint32_t allprofiles[12];
2634
2635 struct {
2636 #ifdef __BIG_ENDIAN_BITFIELD
2637 uint32_t seqlenoff :16;
2638 uint32_t maxlen :16;
2639 #else /* __LITTLE_ENDIAN */
2640 uint32_t maxlen :16;
2641 uint32_t seqlenoff :16;
2642 #endif
2643 #ifdef __BIG_ENDIAN_BITFIELD
2644 uint32_t rsvd1 :28;
2645 uint32_t seqlenbcnt :4;
2646 #else /* __LITTLE_ENDIAN */
2647 uint32_t seqlenbcnt :4;
2648 uint32_t rsvd1 :28;
2649 #endif
2650 uint32_t rsvd[10];
2651 } profile2;
2652
2653 struct {
2654 #ifdef __BIG_ENDIAN_BITFIELD
2655 uint32_t seqlenoff :16;
2656 uint32_t maxlen :16;
2657 #else /* __LITTLE_ENDIAN */
2658 uint32_t maxlen :16;
2659 uint32_t seqlenoff :16;
2660 #endif
2661 #ifdef __BIG_ENDIAN_BITFIELD
2662 uint32_t cmdcodeoff :28;
2663 uint32_t rsvd1 :12;
2664 uint32_t seqlenbcnt :4;
2665 #else /* __LITTLE_ENDIAN */
2666 uint32_t seqlenbcnt :4;
2667 uint32_t rsvd1 :12;
2668 uint32_t cmdcodeoff :28;
2669 #endif
2670 uint32_t cmdmatch[8];
2671
2672 uint32_t rsvd[2];
2673 } profile3;
2674
2675 struct {
2676 #ifdef __BIG_ENDIAN_BITFIELD
2677 uint32_t seqlenoff :16;
2678 uint32_t maxlen :16;
2679 #else /* __LITTLE_ENDIAN */
2680 uint32_t maxlen :16;
2681 uint32_t seqlenoff :16;
2682 #endif
2683 #ifdef __BIG_ENDIAN_BITFIELD
2684 uint32_t cmdcodeoff :28;
2685 uint32_t rsvd1 :12;
2686 uint32_t seqlenbcnt :4;
2687 #else /* __LITTLE_ENDIAN */
2688 uint32_t seqlenbcnt :4;
2689 uint32_t rsvd1 :12;
2690 uint32_t cmdcodeoff :28;
2691 #endif
2692 uint32_t cmdmatch[8];
2693
2694 uint32_t rsvd[2];
2695 } profile5;
2696
2697 } profiles;
2698
2699};
2700
2701
dea3101e 2702
2e0fef85 2703/* Structure for MB Command CONFIG_PORT (0x88) */
dea3101e 2704typedef struct {
ed957684
JS		 2705#ifdef __BIG_ENDIAN_BITFIELD
2706 uint32_t cBE : 1;
2707 uint32_t cET : 1;
2708 uint32_t cHpcb : 1;
2709 uint32_t cMA : 1;
2710 uint32_t sli_mode : 4;
2711 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2712 * config block */
2713#else /* __LITTLE_ENDIAN */
2714 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2715 * config block */
2716 uint32_t sli_mode : 4;
2717 uint32_t cMA : 1;
2718 uint32_t cHpcb : 1;
2719 uint32_t cET : 1;
2720 uint32_t cBE : 1;
2721#endif
2722
dea3101e
JB		 2723 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2724 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
97207482
JS		 2725 uint32_t hbainit[5];
2726#ifdef __BIG_ENDIAN_BITFIELD
2727 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
2728 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
2729#else /* __LITTLE_ENDIAN */
2730 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
2731 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
2732#endif
ed957684
JS		 2733
2734#ifdef __BIG_ENDIAN_BITFIELD
da0436e9
JS		 2735 uint32_t rsvd1 : 19; /* Reserved */
2736 uint32_t cdss : 1; /* Configure Data Security SLI */
2737 uint32_t rsvd2 : 3; /* Reserved */
81301a9b
JS		 2738 uint32_t cbg : 1; /* Configure BlockGuard */
2739 uint32_t cmv : 1; /* Configure Max VPIs */
ed957684
JS		 2740 uint32_t ccrp : 1; /* Config Command Ring Polling */
2741 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2742 uint32_t chbs : 1; /* Cofigure Host Backing store */
2743 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2744 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2745 uint32_t cmx : 1; /* Configure Max XRIs */
2746 uint32_t cmr : 1; /* Configure Max RPIs */
2747#else /* __LITTLE_ENDIAN */
2748 uint32_t cmr : 1; /* Configure Max RPIs */
2749 uint32_t cmx : 1; /* Configure Max XRIs */
2750 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2751 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2752 uint32_t chbs : 1; /* Cofigure Host Backing store */
2753 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2754 uint32_t ccrp : 1; /* Config Command Ring Polling */
2755 uint32_t cmv : 1; /* Configure Max VPIs */
81301a9b 2756 uint32_t cbg : 1; /* Configure BlockGuard */
da0436e9
JS		 2757 uint32_t rsvd2 : 3; /* Reserved */
2758 uint32_t cdss : 1; /* Configure Data Security SLI */
2759 uint32_t rsvd1 : 19; /* Reserved */
ed957684
JS		 2760#endif
2761#ifdef __BIG_ENDIAN_BITFIELD
da0436e9
JS		 2762 uint32_t rsvd3 : 19; /* Reserved */
2763 uint32_t gdss : 1; /* Configure Data Security SLI */
2764 uint32_t rsvd4 : 3; /* Reserved */
81301a9b 2765 uint32_t gbg : 1; /* Grant BlockGuard */
ed957684
JS		 2766 uint32_t gmv : 1; /* Grant Max VPIs */
2767 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2768 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2769 uint32_t ghbs : 1; /* Grant Host Backing Store */
2770 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2771 uint32_t gerbm : 1; /* Grant ERBM Request */
2772 uint32_t gmx : 1; /* Grant Max XRIs */
2773 uint32_t gmr : 1; /* Grant Max RPIs */
2774#else /* __LITTLE_ENDIAN */
2775 uint32_t gmr : 1; /* Grant Max RPIs */
2776 uint32_t gmx : 1; /* Grant Max XRIs */
2777 uint32_t gerbm : 1; /* Grant ERBM Request */
2778 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2779 uint32_t ghbs : 1; /* Grant Host Backing Store */
2780 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2781 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2782 uint32_t gmv : 1; /* Grant Max VPIs */
81301a9b 2783 uint32_t gbg : 1; /* Grant BlockGuard */
da0436e9
JS		 2784 uint32_t rsvd4 : 3; /* Reserved */
2785 uint32_t gdss : 1; /* Configure Data Security SLI */
2786 uint32_t rsvd3 : 19; /* Reserved */
ed957684
JS		 2787#endif
2788
2789#ifdef __BIG_ENDIAN_BITFIELD
2790 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2791 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2792#else /* __LITTLE_ENDIAN */
2793 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2794 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2795#endif
2796
2797#ifdef __BIG_ENDIAN_BITFIELD
2798 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
da0436e9 2799 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
ed957684 2800#else /* __LITTLE_ENDIAN */
da0436e9 2801 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
ed957684
JS		 2802 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2803#endif
2804
da0436e9 2805 uint32_t rsvd6; /* Reserved */
ed957684
JS		 2806
2807#ifdef __BIG_ENDIAN_BITFIELD
da0436e9 2808 uint32_t rsvd7 : 16; /* Reserved */
ed957684
JS		 2809 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2810#else /* __LITTLE_ENDIAN */
2811 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
da0436e9 2812 uint32_t rsvd7 : 16; /* Reserved */
ed957684
JS		 2813#endif
2814
dea3101e
JB		 2815} CONFIG_PORT_VAR;
2816
9399627f
JS		 2817/* Structure for MB Command CONFIG_MSI (0x30) */
2818struct config_msi_var {
2819#ifdef __BIG_ENDIAN_BITFIELD
2820 uint32_t dfltMsgNum:8; /* Default message number */
2821 uint32_t rsvd1:11; /* Reserved */
2822 uint32_t NID:5; /* Number of secondary attention IDs */
2823 uint32_t rsvd2:5; /* Reserved */
2824 uint32_t dfltPresent:1; /* Default message number present */
2825 uint32_t addFlag:1; /* Add association flag */
2826 uint32_t reportFlag:1; /* Report association flag */
2827#else /* __LITTLE_ENDIAN_BITFIELD */
2828 uint32_t reportFlag:1; /* Report association flag */
2829 uint32_t addFlag:1; /* Add association flag */
2830 uint32_t dfltPresent:1; /* Default message number present */
2831 uint32_t rsvd2:5; /* Reserved */
2832 uint32_t NID:5; /* Number of secondary attention IDs */
2833 uint32_t rsvd1:11; /* Reserved */
2834 uint32_t dfltMsgNum:8; /* Default message number */
2835#endif
2836 uint32_t attentionConditions[2];
2837 uint8_t attentionId[16];
2838 uint8_t messageNumberByHA[64];
2839 uint8_t messageNumberByID[16];
2840 uint32_t autoClearHA[2];
2841#ifdef __BIG_ENDIAN_BITFIELD
2842 uint32_t rsvd3:16;
2843 uint32_t autoClearID:16;
2844#else /* __LITTLE_ENDIAN_BITFIELD */
2845 uint32_t autoClearID:16;
2846 uint32_t rsvd3:16;
2847#endif
2848 uint32_t rsvd4;
2849};
2850
dea3101e
JB		 2851/* SLI-2 Port Control Block */
2852
2853/* SLIM POINTER */
2854#define SLIMOFF 0x30 /* WORD */
2855
2856typedef struct _SLI2_RDSC {
2857 uint32_t cmdEntries;
2858 uint32_t cmdAddrLow;
2859 uint32_t cmdAddrHigh;
2860
2861 uint32_t rspEntries;
2862 uint32_t rspAddrLow;
2863 uint32_t rspAddrHigh;
2864} SLI2_RDSC;
2865
2866typedef struct _PCB {
2867#ifdef __BIG_ENDIAN_BITFIELD
2868 uint32_t type:8;
2869#define TYPE_NATIVE_SLI2 0x01;
2870 uint32_t feature:8;
2871#define FEATURE_INITIAL_SLI2 0x01;
2872 uint32_t rsvd:12;
2873 uint32_t maxRing:4;
2874#else /* __LITTLE_ENDIAN_BITFIELD */
2875 uint32_t maxRing:4;
2876 uint32_t rsvd:12;
2877 uint32_t feature:8;
2878#define FEATURE_INITIAL_SLI2 0x01;
2879 uint32_t type:8;
2880#define TYPE_NATIVE_SLI2 0x01;
2881#endif
2882
2883 uint32_t mailBoxSize;
2884 uint32_t mbAddrLow;
2885 uint32_t mbAddrHigh;
2886
2887 uint32_t hgpAddrLow;
2888 uint32_t hgpAddrHigh;
2889
2890 uint32_t pgpAddrLow;
2891 uint32_t pgpAddrHigh;
2892 SLI2_RDSC rdsc[MAX_RINGS];
2893} PCB_t;
2894
2895/* NEW_FEATURE */
2896typedef struct {
2897#ifdef __BIG_ENDIAN_BITFIELD
2898 uint32_t rsvd0:27;
2899 uint32_t discardFarp:1;
2900 uint32_t IPEnable:1;
2901 uint32_t nodeName:1;
2902 uint32_t portName:1;
2903 uint32_t filterEnable:1;
2904#else /* __LITTLE_ENDIAN_BITFIELD */
2905 uint32_t filterEnable:1;
2906 uint32_t portName:1;
2907 uint32_t nodeName:1;
2908 uint32_t IPEnable:1;
2909 uint32_t discardFarp:1;
2910 uint32_t rsvd:27;
2911#endif
2912
2913 uint8_t portname[8]; /* Used to be struct lpfc_name */
2914 uint8_t nodename[8];
2915 uint32_t rsvd1;
2916 uint32_t rsvd2;
2917 uint32_t rsvd3;
2918 uint32_t IPAddress;
2919} CONFIG_FARP_VAR;
2920
57127f15
JS		 2921/* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
2922
2923typedef struct {
2924#ifdef __BIG_ENDIAN_BITFIELD
2925 uint32_t rsvd:30;
2926 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
2927#else /* __LITTLE_ENDIAN */
2928 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
2929 uint32_t rsvd:30;
2930#endif
2931} ASYNCEVT_ENABLE_VAR;
2932
dea3101e
JB		 2933/* Union of all Mailbox Command types */
2934#define MAILBOX_CMD_WSIZE 32
2935#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
7a470277
JS		 2936/* ext_wsize times 4 bytes should not be greater than max xmit size */
2937#define MAILBOX_EXT_WSIZE 512
2938#define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
2939#define MAILBOX_HBA_EXT_OFFSET 0x100
2940/* max mbox xmit size is a page size for sysfs IO operations */
2941#define MAILBOX_MAX_XMIT_SIZE PAGE_SIZE
dea3101e
JB		 2942
2943typedef union {
ed957684
JS		 2944 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
2945 * feature/max ring number
2946 */
2947 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2948 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2949 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
311464ec
JS		 2950 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2951 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
dea3101e 2952 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
ed957684
JS		 2953 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2954 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
dea3101e
JB		 2955 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2956 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2957 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2958 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2959 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2960 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
ed957684
JS		 2961 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2962 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2963 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2964 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
dea3101e
JB		 2965 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2966 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
ed957684 2967 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
dea3101e 2968 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
ed957684
JS		 2969 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2970 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2971 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
2972 * NEW_FEATURE
2973 */
2974 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
d7c255b2 2975 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
ed957684 2976 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
92d7f7b0
JS		 2977 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
2978 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
57127f15 2979 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
c7495937
JS		 2980 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
2981 * (READ_EVENT_LOG)
2982 */
9399627f 2983 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
dea3101e
JB		 2984} MAILVARIANTS;
2985
2986/*
2987 * SLI-2 specific structures
2988 */
2989
4cc2da1d
JSEC		 2990struct lpfc_hgp {
2991 __le32 cmdPutInx;
2992 __le32 rspGetInx;
2993};
dea3101e 2994
4cc2da1d
JSEC		 2995struct lpfc_pgp {
2996 __le32 cmdGetInx;
2997 __le32 rspPutInx;
2998};
dea3101e 2999
ed957684 3000struct sli2_desc {
dea3101e 3001 uint32_t unused1[16];
ed957684
JS		 3002 struct lpfc_hgp host[MAX_RINGS];
3003 struct lpfc_pgp port[MAX_RINGS];
3004};
3005
3006struct sli3_desc {
3007 struct lpfc_hgp host[MAX_RINGS];
3008 uint32_t reserved[8];
3009 uint32_t hbq_put[16];
3010};
3011
3012struct sli3_pgp {
4cc2da1d 3013 struct lpfc_pgp port[MAX_RINGS];
ed957684
JS		 3014 uint32_t hbq_get[16];
3015};
dea3101e 3016
34b02dcd
JS		 3017union sli_var {
3018 struct sli2_desc s2;
3019 struct sli3_desc s3;
3020 struct sli3_pgp s3_pgp;
34b02dcd 3021};
dea3101e
JB		 3022
3023typedef struct {
3024#ifdef __BIG_ENDIAN_BITFIELD
3025 uint16_t mbxStatus;
3026 uint8_t mbxCommand;
3027 uint8_t mbxReserved:6;
3028 uint8_t mbxHc:1;
3029 uint8_t mbxOwner:1; /* Low order bit first word */
3030#else /* __LITTLE_ENDIAN_BITFIELD */
3031 uint8_t mbxOwner:1; /* Low order bit first word */
3032 uint8_t mbxHc:1;
3033 uint8_t mbxReserved:6;
3034 uint8_t mbxCommand;
3035 uint16_t mbxStatus;
3036#endif
3037
3038 MAILVARIANTS un;
34b02dcd 3039 union sli_var us;
dea3101e
JB		 3040} MAILBOX_t;
3041
3042/*
3043 * Begin Structure Definitions for IOCB Commands
3044 */
3045
3046typedef struct {
3047#ifdef __BIG_ENDIAN_BITFIELD
3048 uint8_t statAction;
3049 uint8_t statRsn;
3050 uint8_t statBaExp;
3051 uint8_t statLocalError;
3052#else /* __LITTLE_ENDIAN_BITFIELD */
3053 uint8_t statLocalError;
3054 uint8_t statBaExp;
3055 uint8_t statRsn;
3056 uint8_t statAction;
3057#endif
3058 /* statRsn P/F_RJT reason codes */
3059#define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3060#define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3061#define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3062#define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3063#define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3064#define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3065#define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3066#define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3067#define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3068#define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3069#define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3070#define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3071#define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3072#define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3073#define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3074#define RJT_BAD_PARM 0x10 /* Param. field invalid */
3075#define RJT_XCHG_ERR 0x11 /* Exchange error */
3076#define RJT_PROT_ERR 0x12 /* Protocol error */
3077#define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3078#define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3079#define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3080#define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3081#define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3082#define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3083#define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3084#define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3085
3086#define IOERR_SUCCESS 0x00 /* statLocalError */
3087#define IOERR_MISSING_CONTINUE 0x01
3088#define IOERR_SEQUENCE_TIMEOUT 0x02
3089#define IOERR_INTERNAL_ERROR 0x03
3090#define IOERR_INVALID_RPI 0x04
3091#define IOERR_NO_XRI 0x05
3092#define IOERR_ILLEGAL_COMMAND 0x06
3093#define IOERR_XCHG_DROPPED 0x07
3094#define IOERR_ILLEGAL_FIELD 0x08
3095#define IOERR_BAD_CONTINUE 0x09
3096#define IOERR_TOO_MANY_BUFFERS 0x0A
3097#define IOERR_RCV_BUFFER_WAITING 0x0B
3098#define IOERR_NO_CONNECTION 0x0C
3099#define IOERR_TX_DMA_FAILED 0x0D
3100#define IOERR_RX_DMA_FAILED 0x0E
3101#define IOERR_ILLEGAL_FRAME 0x0F
3102#define IOERR_EXTRA_DATA 0x10
3103#define IOERR_NO_RESOURCES 0x11
3104#define IOERR_RESERVED 0x12
3105#define IOERR_ILLEGAL_LENGTH 0x13
3106#define IOERR_UNSUPPORTED_FEATURE 0x14
3107#define IOERR_ABORT_IN_PROGRESS 0x15
3108#define IOERR_ABORT_REQUESTED 0x16
3109#define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3110#define IOERR_LOOP_OPEN_FAILURE 0x18
3111#define IOERR_RING_RESET 0x19
3112#define IOERR_LINK_DOWN 0x1A
3113#define IOERR_CORRUPTED_DATA 0x1B
3114#define IOERR_CORRUPTED_RPI 0x1C
3115#define IOERR_OUT_OF_ORDER_DATA 0x1D
3116#define IOERR_OUT_OF_ORDER_ACK 0x1E
3117#define IOERR_DUP_FRAME 0x1F
3118#define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3119#define IOERR_BAD_HOST_ADDRESS 0x21
3120#define IOERR_RCV_HDRBUF_WAITING 0x22
3121#define IOERR_MISSING_HDR_BUFFER 0x23
3122#define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3123#define IOERR_ABORTMULT_REQUESTED 0x25
3124#define IOERR_BUFFER_SHORTAGE 0x28
3125#define IOERR_DEFAULT 0x29
3126#define IOERR_CNT 0x2A
b92938b4
JS		 3127#define IOERR_SLER_FAILURE 0x46
3128#define IOERR_SLER_CMD_RCV_FAILURE 0x47
3129#define IOERR_SLER_REC_RJT_ERR 0x48
3130#define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3131#define IOERR_SLER_SRR_RJT_ERR 0x4A
3132#define IOERR_SLER_RRQ_RJT_ERR 0x4C
3133#define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3134#define IOERR_SLER_ABTS_ERR 0x4E
dea3101e
JB		 3135
3136#define IOERR_DRVR_MASK 0x100
3137#define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3138#define IOERR_SLI_BRESET 0x102
3139#define IOERR_SLI_ABORTED 0x103
3140} PARM_ERR;
3141
3142typedef union {
3143 struct {
3144#ifdef __BIG_ENDIAN_BITFIELD
3145 uint8_t Rctl; /* R_CTL field */
3146 uint8_t Type; /* TYPE field */
3147 uint8_t Dfctl; /* DF_CTL field */
3148 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3149#else /* __LITTLE_ENDIAN_BITFIELD */
3150 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3151 uint8_t Dfctl; /* DF_CTL field */
3152 uint8_t Type; /* TYPE field */
3153 uint8_t Rctl; /* R_CTL field */
3154#endif
3155
3156#define BC 0x02 /* Broadcast Received - Fctl */
3157#define SI 0x04 /* Sequence Initiative */
3158#define LA 0x08 /* Ignore Link Attention state */
3159#define LS 0x80 /* Last Sequence */
3160 } hcsw;
3161 uint32_t reserved;
3162} WORD5;
3163
3164/* IOCB Command template for a generic response */
3165typedef struct {
3166 uint32_t reserved[4];
3167 PARM_ERR perr;
3168} GENERIC_RSP;
3169
3170/* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3171typedef struct {
3172 struct ulp_bde xrsqbde[2];
3173 uint32_t xrsqRo; /* Starting Relative Offset */
3174 WORD5 w5; /* Header control/status word */
3175} XR_SEQ_FIELDS;
3176
3177/* IOCB Command template for ELS_REQUEST */
3178typedef struct {
3179 struct ulp_bde elsReq;
3180 struct ulp_bde elsRsp;
3181
3182#ifdef __BIG_ENDIAN_BITFIELD
3183 uint32_t word4Rsvd:7;
3184 uint32_t fl:1;
3185 uint32_t myID:24;
3186 uint32_t word5Rsvd:8;
3187 uint32_t remoteID:24;
3188#else /* __LITTLE_ENDIAN_BITFIELD */
3189 uint32_t myID:24;
3190 uint32_t fl:1;
3191 uint32_t word4Rsvd:7;
3192 uint32_t remoteID:24;
3193 uint32_t word5Rsvd:8;
3194#endif
3195} ELS_REQUEST;
3196
3197/* IOCB Command template for RCV_ELS_REQ */
3198typedef struct {
3199 struct ulp_bde elsReq[2];
3200 uint32_t parmRo;
3201
3202#ifdef __BIG_ENDIAN_BITFIELD
3203 uint32_t word5Rsvd:8;
3204 uint32_t remoteID:24;
3205#else /* __LITTLE_ENDIAN_BITFIELD */
3206 uint32_t remoteID:24;
3207 uint32_t word5Rsvd:8;
3208#endif
3209} RCV_ELS_REQ;
3210
3211/* IOCB Command template for ABORT / CLOSE_XRI */
3212typedef struct {
3213 uint32_t rsvd[3];
3214 uint32_t abortType;
3215#define ABORT_TYPE_ABTX 0x00000000
3216#define ABORT_TYPE_ABTS 0x00000001
3217 uint32_t parm;
3218#ifdef __BIG_ENDIAN_BITFIELD
3219 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3220 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3221#else /* __LITTLE_ENDIAN_BITFIELD */
3222 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3223 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3224#endif
3225} AC_XRI;
3226
3227/* IOCB Command template for ABORT_MXRI64 */
3228typedef struct {
3229 uint32_t rsvd[3];
3230 uint32_t abortType;
3231 uint32_t parm;
3232 uint32_t iotag32;
3233} A_MXRI64;
3234
3235/* IOCB Command template for GET_RPI */
3236typedef struct {
3237 uint32_t rsvd[4];
3238 uint32_t parmRo;
3239#ifdef __BIG_ENDIAN_BITFIELD
3240 uint32_t word5Rsvd:8;
3241 uint32_t remoteID:24;
3242#else /* __LITTLE_ENDIAN_BITFIELD */
3243 uint32_t remoteID:24;
3244 uint32_t word5Rsvd:8;
3245#endif
3246} GET_RPI;
3247
3248/* IOCB Command template for all FCP Initiator commands */
3249typedef struct {
3250 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3251 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3252 uint32_t fcpi_parm;
3253 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3254} FCPI_FIELDS;
3255
3256/* IOCB Command template for all FCP Target commands */
3257typedef struct {
3258 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3259 uint32_t fcpt_Offset;
3260 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3261} FCPT_FIELDS;
3262
3263/* SLI-2 IOCB structure definitions */
3264
3265/* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3266typedef struct {
3267 ULP_BDL bdl;
3268 uint32_t xrsqRo; /* Starting Relative Offset */
3269 WORD5 w5; /* Header control/status word */
3270} XMT_SEQ_FIELDS64;
3271
3272/* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3273typedef struct {
3274 struct ulp_bde64 rcvBde;
3275 uint32_t rsvd1;
3276 uint32_t xrsqRo; /* Starting Relative Offset */
3277 WORD5 w5; /* Header control/status word */
3278} RCV_SEQ_FIELDS64;
3279
3280/* IOCB Command template for ELS_REQUEST64 */
3281typedef struct {
3282 ULP_BDL bdl;
3283#ifdef __BIG_ENDIAN_BITFIELD
3284 uint32_t word4Rsvd:7;
3285 uint32_t fl:1;
3286 uint32_t myID:24;
3287 uint32_t word5Rsvd:8;
3288 uint32_t remoteID:24;
3289#else /* __LITTLE_ENDIAN_BITFIELD */
3290 uint32_t myID:24;
3291 uint32_t fl:1;
3292 uint32_t word4Rsvd:7;
3293 uint32_t remoteID:24;
3294 uint32_t word5Rsvd:8;
3295#endif
3296} ELS_REQUEST64;
3297
3298/* IOCB Command template for GEN_REQUEST64 */
3299typedef struct {
3300 ULP_BDL bdl;
3301 uint32_t xrsqRo; /* Starting Relative Offset */
3302 WORD5 w5; /* Header control/status word */
3303} GEN_REQUEST64;
3304
3305/* IOCB Command template for RCV_ELS_REQ64 */
3306typedef struct {
3307 struct ulp_bde64 elsReq;
3308 uint32_t rcvd1;
3309 uint32_t parmRo;
3310
3311#ifdef __BIG_ENDIAN_BITFIELD
3312 uint32_t word5Rsvd:8;
3313 uint32_t remoteID:24;
3314#else /* __LITTLE_ENDIAN_BITFIELD */
3315 uint32_t remoteID:24;
3316 uint32_t word5Rsvd:8;
3317#endif
3318} RCV_ELS_REQ64;
3319
9c2face6
JS		 3320/* IOCB Command template for RCV_SEQ64 */
3321struct rcv_seq64 {
3322 struct ulp_bde64 elsReq;
3323 uint32_t hbq_1;
3324 uint32_t parmRo;
3325#ifdef __BIG_ENDIAN_BITFIELD
3326 uint32_t rctl:8;
3327 uint32_t type:8;
3328 uint32_t dfctl:8;
3329 uint32_t ls:1;
3330 uint32_t fs:1;
3331 uint32_t rsvd2:3;
3332 uint32_t si:1;
3333 uint32_t bc:1;
3334 uint32_t rsvd3:1;
3335#else /* __LITTLE_ENDIAN_BITFIELD */
3336 uint32_t rsvd3:1;
3337 uint32_t bc:1;
3338 uint32_t si:1;
3339 uint32_t rsvd2:3;
3340 uint32_t fs:1;
3341 uint32_t ls:1;
3342 uint32_t dfctl:8;
3343 uint32_t type:8;
3344 uint32_t rctl:8;
3345#endif
3346};
3347
dea3101e
JB		 3348/* IOCB Command template for all 64 bit FCP Initiator commands */
3349typedef struct {
3350 ULP_BDL bdl;
3351 uint32_t fcpi_parm;
3352 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3353} FCPI_FIELDS64;
3354
3355/* IOCB Command template for all 64 bit FCP Target commands */
3356typedef struct {
3357 ULP_BDL bdl;
3358 uint32_t fcpt_Offset;
3359 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3360} FCPT_FIELDS64;
3361
57127f15
JS		 3362/* IOCB Command template for Async Status iocb commands */
3363typedef struct {
3364 uint32_t rsvd[4];
3365 uint32_t param;
3366#ifdef __BIG_ENDIAN_BITFIELD
3367 uint16_t evt_code; /* High order bits word 5 */
3368 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3369#else /* __LITTLE_ENDIAN_BITFIELD */
3370 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3371 uint16_t evt_code; /* Low order bits word 5 */
3372#endif
3373} ASYNCSTAT_FIELDS;
3374#define ASYNC_TEMP_WARN 0x100
3375#define ASYNC_TEMP_SAFE 0x101
3376
ed957684
JS		 3377/* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3378 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3379
3380struct rcv_sli3 {
3381 uint32_t word8Rsvd;
3382#ifdef __BIG_ENDIAN_BITFIELD
3383 uint16_t vpi;
3384 uint16_t word9Rsvd;
3385#else /* __LITTLE_ENDIAN */
3386 uint16_t word9Rsvd;
3387 uint16_t vpi;
3388#endif
3389 uint32_t word10Rsvd;
3390 uint32_t acc_len; /* accumulated length */
3391 struct ulp_bde64 bde2;
3392};
3393
76bb24ef
JS		 3394/* Structure used for a single HBQ entry */
3395struct lpfc_hbq_entry {
3396 struct ulp_bde64 bde;
3397 uint32_t buffer_tag;
3398};
92d7f7b0 3399
76bb24ef
JS		 3400/* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3401typedef struct {
3402 struct lpfc_hbq_entry buff;
3403 uint32_t rsvd;
3404 uint32_t rsvd1;
3405} QUE_XRI64_CX_FIELDS;
3406
3407struct que_xri64cx_ext_fields {
3408 uint32_t iotag64_low;
3409 uint32_t iotag64_high;
3410 uint32_t ebde_count;
3411 uint32_t rsvd;
3412 struct lpfc_hbq_entry buff[5];
3413};
92d7f7b0 3414
81301a9b
JS		 3415struct sli3_bg_fields {
3416 uint32_t filler[6]; /* word 8-13 in IOCB */
3417 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3418/* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3419#define BGS_BIDIR_BG_PROF_MASK 0xff000000
3420#define BGS_BIDIR_BG_PROF_SHIFT 24
3421#define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3422#define BGS_BIDIR_ERR_COND_SHIFT 16
3423#define BGS_BG_PROFILE_MASK 0x0000ff00
3424#define BGS_BG_PROFILE_SHIFT 8
3425#define BGS_INVALID_PROF_MASK 0x00000020
3426#define BGS_INVALID_PROF_SHIFT 5
3427#define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3428#define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3429#define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3430#define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3431#define BGS_REFTAG_ERR_MASK 0x00000004
3432#define BGS_REFTAG_ERR_SHIFT 2
3433#define BGS_APPTAG_ERR_MASK 0x00000002
3434#define BGS_APPTAG_ERR_SHIFT 1
3435#define BGS_GUARD_ERR_MASK 0x00000001
3436#define BGS_GUARD_ERR_SHIFT 0
3437 uint32_t bgstat; /* word 15 - BlockGuard Status */
3438};
3439
3440static inline uint32_t
3441lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3442{
3443 return (le32_to_cpu(bgstat) & BGS_BIDIR_BG_PROF_MASK) >>
3444 BGS_BIDIR_BG_PROF_SHIFT;
3445}
3446
3447static inline uint32_t
3448lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3449{
3450 return (le32_to_cpu(bgstat) & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3451 BGS_BIDIR_ERR_COND_SHIFT;
3452}
3453
3454static inline uint32_t
3455lpfc_bgs_get_bg_prof(uint32_t bgstat)
3456{
3457 return (le32_to_cpu(bgstat) & BGS_BG_PROFILE_MASK) >>
3458 BGS_BG_PROFILE_SHIFT;
3459}
3460
3461static inline uint32_t
3462lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3463{
3464 return (le32_to_cpu(bgstat) & BGS_INVALID_PROF_MASK) >>
3465 BGS_INVALID_PROF_SHIFT;
3466}
3467
3468static inline uint32_t
3469lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
3470{
3471 return (le32_to_cpu(bgstat) & BGS_UNINIT_DIF_BLOCK_MASK) >>
3472 BGS_UNINIT_DIF_BLOCK_SHIFT;
3473}
3474
3475static inline uint32_t
3476lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
3477{
3478 return (le32_to_cpu(bgstat) & BGS_HI_WATER_MARK_PRESENT_MASK) >>
3479 BGS_HI_WATER_MARK_PRESENT_SHIFT;
3480}
3481
3482static inline uint32_t
3483lpfc_bgs_get_reftag_err(uint32_t bgstat)
3484{
3485 return (le32_to_cpu(bgstat) & BGS_REFTAG_ERR_MASK) >>
3486 BGS_REFTAG_ERR_SHIFT;
3487}
3488
3489static inline uint32_t
3490lpfc_bgs_get_apptag_err(uint32_t bgstat)
3491{
3492 return (le32_to_cpu(bgstat) & BGS_APPTAG_ERR_MASK) >>
3493 BGS_APPTAG_ERR_SHIFT;
3494}
3495
3496static inline uint32_t
3497lpfc_bgs_get_guard_err(uint32_t bgstat)
3498{
3499 return (le32_to_cpu(bgstat) & BGS_GUARD_ERR_MASK) >>
3500 BGS_GUARD_ERR_SHIFT;
3501}
3502
34b02dcd
JS		 3503#define LPFC_EXT_DATA_BDE_COUNT 3
3504struct fcp_irw_ext {
3505 uint32_t io_tag64_low;
3506 uint32_t io_tag64_high;
3507#ifdef __BIG_ENDIAN_BITFIELD
3508 uint8_t reserved1;
3509 uint8_t reserved2;
3510 uint8_t reserved3;
3511 uint8_t ebde_count;
3512#else /* __LITTLE_ENDIAN */
3513 uint8_t ebde_count;
3514 uint8_t reserved3;
3515 uint8_t reserved2;
3516 uint8_t reserved1;
3517#endif
3518 uint32_t reserved4;
3519 struct ulp_bde64 rbde; /* response bde */
3520 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
3521 uint8_t icd[32]; /* immediate command data (32 bytes) */
3522};
3523
dea3101e
JB		 3524typedef struct _IOCB { /* IOCB structure */
3525 union {
3526 GENERIC_RSP grsp; /* Generic response */
3527 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
3528 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3529 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
3530 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
3531 A_MXRI64 amxri; /* abort multiple xri command overlay */
3532 GET_RPI getrpi; /* GET_RPI template */
3533 FCPI_FIELDS fcpi; /* FCP Initiator template */
3534 FCPT_FIELDS fcpt; /* FCP target template */
3535
3536 /* SLI-2 structures */
3537
ed957684
JS		 3538 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
3539 * bde_64s */
dea3101e
JB		 3540 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3541 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3542 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3543 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
3544 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
3545 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
57127f15 3546 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
76bb24ef 3547 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
9c2face6 3548 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
5ffc266e 3549 struct sli4_bls_acc bls_acc; /* UNSOL ABTS BLS_ACC params */
dea3101e
JB		 3550 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
3551 } un;
3552 union {
3553 struct {
3554#ifdef __BIG_ENDIAN_BITFIELD
3555 uint16_t ulpContext; /* High order bits word 6 */
3556 uint16_t ulpIoTag; /* Low order bits word 6 */
3557#else /* __LITTLE_ENDIAN_BITFIELD */
3558 uint16_t ulpIoTag; /* Low order bits word 6 */
3559 uint16_t ulpContext; /* High order bits word 6 */
3560#endif
3561 } t1;
3562 struct {
3563#ifdef __BIG_ENDIAN_BITFIELD
3564 uint16_t ulpContext; /* High order bits word 6 */
3565 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3566 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3567#else /* __LITTLE_ENDIAN_BITFIELD */
3568 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3569 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3570 uint16_t ulpContext; /* High order bits word 6 */
3571#endif
3572 } t2;
3573 } un1;
3574#define ulpContext un1.t1.ulpContext
3575#define ulpIoTag un1.t1.ulpIoTag
3576#define ulpIoTag0 un1.t2.ulpIoTag0
3577
3578#ifdef __BIG_ENDIAN_BITFIELD
3579 uint32_t ulpTimeout:8;
3580 uint32_t ulpXS:1;
3581 uint32_t ulpFCP2Rcvy:1;
3582 uint32_t ulpPU:2;
3583 uint32_t ulpIr:1;
3584 uint32_t ulpClass:3;
3585 uint32_t ulpCommand:8;
3586 uint32_t ulpStatus:4;
3587 uint32_t ulpBdeCount:2;
3588 uint32_t ulpLe:1;
3589 uint32_t ulpOwner:1; /* Low order bit word 7 */
3590#else /* __LITTLE_ENDIAN_BITFIELD */
3591 uint32_t ulpOwner:1; /* Low order bit word 7 */
3592 uint32_t ulpLe:1;
3593 uint32_t ulpBdeCount:2;
3594 uint32_t ulpStatus:4;
3595 uint32_t ulpCommand:8;
3596 uint32_t ulpClass:3;
3597 uint32_t ulpIr:1;
3598 uint32_t ulpPU:2;
3599 uint32_t ulpFCP2Rcvy:1;
3600 uint32_t ulpXS:1;
3601 uint32_t ulpTimeout:8;
3602#endif
92d7f7b0 3603
ed957684
JS		 3604 union {
3605 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
76bb24ef
JS		 3606
3607 /* words 8-31 used for que_xri_cx iocb */
3608 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
34b02dcd 3609 struct fcp_irw_ext fcp_ext;
ed957684 3610 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
81301a9b
JS		 3611
3612 /* words 8-15 for BlockGuard */
3613 struct sli3_bg_fields sli3_bg;
ed957684
JS		 3614 } unsli3;
3615
3616#define ulpCt_h ulpXS
3617#define ulpCt_l ulpFCP2Rcvy
dea3101e 3618
ed957684
JS		 3619#define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3620#define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
dea3101e
JB		 3621#define PARM_UNUSED 0 /* PU field (Word 4) not used */
3622#define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
3623#define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
92d7f7b0 3624#define PARM_NPIV_DID 3
dea3101e
JB		 3625#define CLASS1 0 /* Class 1 */
3626#define CLASS2 1 /* Class 2 */
3627#define CLASS3 2 /* Class 3 */
3628#define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
3629
3630#define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
3631#define IOSTAT_FCP_RSP_ERROR 0x1
3632#define IOSTAT_REMOTE_STOP 0x2
3633#define IOSTAT_LOCAL_REJECT 0x3
3634#define IOSTAT_NPORT_RJT 0x4
3635#define IOSTAT_FABRIC_RJT 0x5
3636#define IOSTAT_NPORT_BSY 0x6
3637#define IOSTAT_FABRIC_BSY 0x7
3638#define IOSTAT_INTERMED_RSP 0x8
3639#define IOSTAT_LS_RJT 0x9
3640#define IOSTAT_BA_RJT 0xA
3641#define IOSTAT_RSVD1 0xB
3642#define IOSTAT_RSVD2 0xC
3643#define IOSTAT_RSVD3 0xD
3644#define IOSTAT_RSVD4 0xE
92d7f7b0 3645#define IOSTAT_NEED_BUFFER 0xF
dea3101e
JB		 3646#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
3647#define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
3648#define IOSTAT_CNT 0x11
3649
3650} IOCB_t;
3651
3652
3653#define SLI1_SLIM_SIZE (4 * 1024)
3654
3655/* Up to 498 IOCBs will fit into 16k
3656 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3657 */
ed957684 3658#define SLI2_SLIM_SIZE (64 * 1024)
dea3101e
JB		 3659
3660/* Maximum IOCBs that will fit in SLI2 slim */
3661#define MAX_SLI2_IOCB 498
ed957684 3662#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
7a470277
JS		 3663 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
3664 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
ed957684
JS		 3665
3666/* HBQ entries are 4 words each = 4k */
3667#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3668 lpfc_sli_hbq_count())
dea3101e
JB		 3669
3670struct lpfc_sli2_slim {
3671 MAILBOX_t mbx;
7a470277 3672 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
dea3101e 3673 PCB_t pcb;
ed957684 3674 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
dea3101e
JB		 3675};
3676
2e0fef85
JS		 3677/*
3678 * This function checks PCI device to allow special handling for LC HBAs.
3679 *
3680 * Parameters:
3681 * device : struct pci_dev 's device field
3682 *
3683 * return 1 => TRUE
3684 * 0 => FALSE
3685 */
dea3101e
JB		 3686static inline int
3687lpfc_is_LC_HBA(unsigned short device)
3688{
3689 if ((device == PCI_DEVICE_ID_TFLY) ||
3690 (device == PCI_DEVICE_ID_PFLY) ||
3691 (device == PCI_DEVICE_ID_LP101) ||
3692 (device == PCI_DEVICE_ID_BMID) ||
3693 (device == PCI_DEVICE_ID_BSMB) ||
3694 (device == PCI_DEVICE_ID_ZMID) ||
3695 (device == PCI_DEVICE_ID_ZSMB) ||
09372820
JS		 3696 (device == PCI_DEVICE_ID_SAT_MID) ||
3697 (device == PCI_DEVICE_ID_SAT_SMB) ||
dea3101e
JB		 3698 (device == PCI_DEVICE_ID_RFLY))
3699 return 1;
3700 else
3701 return 0;
3702}
858c9f6c
JS		 3703
3704/*
3705 * Determine if an IOCB failed because of a link event or firmware reset.
3706 */
3707
3708static inline int
3709lpfc_error_lost_link(IOCB_t *iocbp)
3710{
3711 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3712 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3713 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3714 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
3715}
84774a4d
JS		 3716
3717#define MENLO_TRANSPORT_TYPE 0xfe
3718#define MENLO_CONTEXT 0
3719#define MENLO_PU 3
3720#define MENLO_TIMEOUT 30
3721#define SETVAR_MLOMNT 0x103107
3722#define SETVAR_MLORST 0x103007
da0436e9
JS		 3723
3724#define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
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