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[SCSI] lpfc 8.1.11 : Discovery Fixes
[net-next-2.6.git] / drivers / scsi / lpfc / lpfc_hw.h
CommitLineData
dea3101e
JB		 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
41415862 4 * Copyright (C) 2004-2006 Emulex. All rights reserved. *
c44ce173 5 * EMULEX and SLI are trademarks of Emulex. *
dea3101e
JB		 6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC		 9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
dea3101e
JB		 19 *******************************************************************/
20
dea3101e
JB		 21#define FDMI_DID 0xfffffaU
22#define NameServer_DID 0xfffffcU
23#define SCR_DID 0xfffffdU
24#define Fabric_DID 0xfffffeU
25#define Bcast_DID 0xffffffU
26#define Mask_DID 0xffffffU
27#define CT_DID_MASK 0xffff00U
28#define Fabric_DID_MASK 0xfff000U
29#define WELL_KNOWN_DID_MASK 0xfffff0U
30
31#define PT2PT_LocalID 1
32#define PT2PT_RemoteID 2
33
34#define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35#define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36#define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
37#define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
38
39#define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
40 0 */
41
42#define FCELSSIZE 1024 /* maximum ELS transfer size */
43
44#define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
45#define LPFC_IP_RING 1 /* ring 1 for IP commands */
46#define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47#define LPFC_FCP_NEXT_RING 3
48
49#define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
50#define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
51#define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 IP command ring entries */
52#define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 IP response ring entries */
53#define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
54#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
55#define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
56#define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
57#define SLI2_IOCB_CMD_R3_ENTRIES 0
58#define SLI2_IOCB_RSP_R3_ENTRIES 0
59#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
61
62/* Common Transport structures and definitions */
63
64union CtRevisionId {
65 /* Structure is in Big Endian format */
66 struct {
67 uint32_t Revision:8;
68 uint32_t InId:24;
69 } bits;
70 uint32_t word;
71};
72
73union CtCommandResponse {
74 /* Structure is in Big Endian format */
75 struct {
76 uint32_t CmdRsp:16;
77 uint32_t Size:16;
78 } bits;
79 uint32_t word;
80};
81
82struct lpfc_sli_ct_request {
83 /* Structure is in Big Endian format */
84 union CtRevisionId RevisionId;
85 uint8_t FsType;
86 uint8_t FsSubType;
87 uint8_t Options;
88 uint8_t Rsrvd1;
89 union CtCommandResponse CommandResponse;
90 uint8_t Rsrvd2;
91 uint8_t ReasonCode;
92 uint8_t Explanation;
93 uint8_t VendorUnique;
94
95 union {
96 uint32_t PortID;
97 struct gid {
98 uint8_t PortType; /* for GID_PT requests */
99 uint8_t DomainScope;
100 uint8_t AreaScope;
101 uint8_t Fc4Type; /* for GID_FT requests */
102 } gid;
103 struct rft {
104 uint32_t PortId; /* For RFT_ID requests */
105
106#ifdef __BIG_ENDIAN_BITFIELD
107 uint32_t rsvd0:16;
108 uint32_t rsvd1:7;
109 uint32_t fcpReg:1; /* Type 8 */
110 uint32_t rsvd2:2;
111 uint32_t ipReg:1; /* Type 5 */
112 uint32_t rsvd3:5;
113#else /* __LITTLE_ENDIAN_BITFIELD */
114 uint32_t rsvd0:16;
115 uint32_t fcpReg:1; /* Type 8 */
116 uint32_t rsvd1:7;
117 uint32_t rsvd3:5;
118 uint32_t ipReg:1; /* Type 5 */
119 uint32_t rsvd2:2;
120#endif
121
122 uint32_t rsvd[7];
123 } rft;
2fb9bd8b
JS		 124 struct rff {
125 uint32_t PortId;
126 uint8_t reserved[2];
127#ifdef __BIG_ENDIAN_BITFIELD
128 uint8_t feature_res:6;
129 uint8_t feature_init:1;
130 uint8_t feature_tgt:1;
131#else /* __LITTLE_ENDIAN_BITFIELD */
132 uint8_t feature_tgt:1;
133 uint8_t feature_init:1;
134 uint8_t feature_res:6;
135#endif
136 uint8_t type_code; /* type=8 for FCP */
137 } rff;
dea3101e
JB		 138 struct rnn {
139 uint32_t PortId; /* For RNN_ID requests */
140 uint8_t wwnn[8];
141 } rnn;
142 struct rsnn { /* For RSNN_ID requests */
143 uint8_t wwnn[8];
144 uint8_t len;
145 uint8_t symbname[255];
146 } rsnn;
147 } un;
148};
149
150#define SLI_CT_REVISION 1
151#define GID_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 260)
152#define RFT_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 228)
2fb9bd8b 153#define RFF_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 235)
dea3101e
JB		 154#define RNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 252)
155#define RSNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request))
156
157/*
158 * FsType Definitions
159 */
160
161#define SLI_CT_MANAGEMENT_SERVICE 0xFA
162#define SLI_CT_TIME_SERVICE 0xFB
163#define SLI_CT_DIRECTORY_SERVICE 0xFC
164#define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
165
166/*
167 * Directory Service Subtypes
168 */
169
170#define SLI_CT_DIRECTORY_NAME_SERVER 0x02
171
172/*
173 * Response Codes
174 */
175
176#define SLI_CT_RESPONSE_FS_RJT 0x8001
177#define SLI_CT_RESPONSE_FS_ACC 0x8002
178
179/*
180 * Reason Codes
181 */
182
183#define SLI_CT_NO_ADDITIONAL_EXPL 0x0
184#define SLI_CT_INVALID_COMMAND 0x01
185#define SLI_CT_INVALID_VERSION 0x02
186#define SLI_CT_LOGICAL_ERROR 0x03
187#define SLI_CT_INVALID_IU_SIZE 0x04
188#define SLI_CT_LOGICAL_BUSY 0x05
189#define SLI_CT_PROTOCOL_ERROR 0x07
190#define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
191#define SLI_CT_REQ_NOT_SUPPORTED 0x0b
192#define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
193#define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
194#define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
195#define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
196#define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
197#define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
198#define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
199#define SLI_CT_VENDOR_UNIQUE 0xff
200
201/*
202 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
203 */
204
205#define SLI_CT_NO_PORT_ID 0x01
206#define SLI_CT_NO_PORT_NAME 0x02
207#define SLI_CT_NO_NODE_NAME 0x03
208#define SLI_CT_NO_CLASS_OF_SERVICE 0x04
209#define SLI_CT_NO_IP_ADDRESS 0x05
210#define SLI_CT_NO_IPA 0x06
211#define SLI_CT_NO_FC4_TYPES 0x07
212#define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
213#define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
214#define SLI_CT_NO_PORT_TYPE 0x0A
215#define SLI_CT_ACCESS_DENIED 0x10
216#define SLI_CT_INVALID_PORT_ID 0x11
217#define SLI_CT_DATABASE_EMPTY 0x12
218
219/*
220 * Name Server Command Codes
221 */
222
223#define SLI_CTNS_GA_NXT 0x0100
224#define SLI_CTNS_GPN_ID 0x0112
225#define SLI_CTNS_GNN_ID 0x0113
226#define SLI_CTNS_GCS_ID 0x0114
227#define SLI_CTNS_GFT_ID 0x0117
228#define SLI_CTNS_GSPN_ID 0x0118
229#define SLI_CTNS_GPT_ID 0x011A
230#define SLI_CTNS_GID_PN 0x0121
231#define SLI_CTNS_GID_NN 0x0131
232#define SLI_CTNS_GIP_NN 0x0135
233#define SLI_CTNS_GIPA_NN 0x0136
234#define SLI_CTNS_GSNN_NN 0x0139
235#define SLI_CTNS_GNN_IP 0x0153
236#define SLI_CTNS_GIPA_IP 0x0156
237#define SLI_CTNS_GID_FT 0x0171
238#define SLI_CTNS_GID_PT 0x01A1
239#define SLI_CTNS_RPN_ID 0x0212
240#define SLI_CTNS_RNN_ID 0x0213
241#define SLI_CTNS_RCS_ID 0x0214
242#define SLI_CTNS_RFT_ID 0x0217
2fb9bd8b 243#define SLI_CTNS_RFF_ID 0x021F
dea3101e
JB		 244#define SLI_CTNS_RSPN_ID 0x0218
245#define SLI_CTNS_RPT_ID 0x021A
246#define SLI_CTNS_RIP_NN 0x0235
247#define SLI_CTNS_RIPA_NN 0x0236
248#define SLI_CTNS_RSNN_NN 0x0239
249#define SLI_CTNS_DA_ID 0x0300
250
251/*
252 * Port Types
253 */
254
255#define SLI_CTPT_N_PORT 0x01
256#define SLI_CTPT_NL_PORT 0x02
257#define SLI_CTPT_FNL_PORT 0x03
258#define SLI_CTPT_IP 0x04
259#define SLI_CTPT_FCP 0x08
260#define SLI_CTPT_NX_PORT 0x7F
261#define SLI_CTPT_F_PORT 0x81
262#define SLI_CTPT_FL_PORT 0x82
263#define SLI_CTPT_E_PORT 0x84
264
265#define SLI_CT_LAST_ENTRY 0x80000000
266
267/* Fibre Channel Service Parameter definitions */
268
269#define FC_PH_4_0 6 /* FC-PH version 4.0 */
270#define FC_PH_4_1 7 /* FC-PH version 4.1 */
271#define FC_PH_4_2 8 /* FC-PH version 4.2 */
272#define FC_PH_4_3 9 /* FC-PH version 4.3 */
273
274#define FC_PH_LOW 8 /* Lowest supported FC-PH version */
275#define FC_PH_HIGH 9 /* Highest supported FC-PH version */
276#define FC_PH3 0x20 /* FC-PH-3 version */
277
278#define FF_FRAME_SIZE 2048
279
280struct lpfc_name {
f631b4be
AV		 281 union {
282 struct {
dea3101e 283#ifdef __BIG_ENDIAN_BITFIELD
f631b4be 284 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
1de933f3
JSEC		 285 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
286 8:11 of IEEE ext */
dea3101e 287#else /* __LITTLE_ENDIAN_BITFIELD */
1de933f3
JSEC		 288 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
289 8:11 of IEEE ext */
f631b4be 290 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
dea3101e
JB		 291#endif
292
293#define NAME_IEEE 0x1 /* IEEE name - nameType */
294#define NAME_IEEE_EXT 0x2 /* IEEE extended name */
295#define NAME_FC_TYPE 0x3 /* FC native name type */
296#define NAME_IP_TYPE 0x4 /* IP address */
297#define NAME_CCITT_TYPE 0xC
298#define NAME_CCITT_GR_TYPE 0xE
1de933f3
JSEC		 299 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
300 extended Lsb */
f631b4be 301 uint8_t IEEE[6]; /* FC IEEE address */
68ce1eb5 302 } s;
f631b4be 303 uint8_t wwn[8];
68ce1eb5 304 } u;
dea3101e
JB		 305};
306
307struct csp {
308 uint8_t fcphHigh; /* FC Word 0, byte 0 */
309 uint8_t fcphLow;
310 uint8_t bbCreditMsb;
311 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
312
313#ifdef __BIG_ENDIAN_BITFIELD
314 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */
315 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
316 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */
317 uint16_t fPort:1; /* FC Word 1, bit 28 */
318 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
319 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
320 uint16_t multicast:1; /* FC Word 1, bit 25 */
321 uint16_t broadcast:1; /* FC Word 1, bit 24 */
322
323 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
324 uint16_t simplex:1; /* FC Word 1, bit 22 */
325 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
326 uint16_t dhd:1; /* FC Word 1, bit 18 */
327 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
328 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
329#else /* __LITTLE_ENDIAN_BITFIELD */
330 uint16_t broadcast:1; /* FC Word 1, bit 24 */
331 uint16_t multicast:1; /* FC Word 1, bit 25 */
332 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
333 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
334 uint16_t fPort:1; /* FC Word 1, bit 28 */
335 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */
336 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
337 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */
338
339 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
340 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
341 uint16_t dhd:1; /* FC Word 1, bit 18 */
342 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
343 uint16_t simplex:1; /* FC Word 1, bit 22 */
344 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
345#endif
346
347 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
348 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
349 union {
350 struct {
351 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
352
353 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
354 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
355
356 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
357 } nPort;
358 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
359 } w2;
360
361 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
362};
363
364struct class_parms {
365#ifdef __BIG_ENDIAN_BITFIELD
366 uint8_t classValid:1; /* FC Word 0, bit 31 */
367 uint8_t intermix:1; /* FC Word 0, bit 30 */
368 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
369 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
370 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
371 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
372#else /* __LITTLE_ENDIAN_BITFIELD */
373 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
374 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
375 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
376 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
377 uint8_t intermix:1; /* FC Word 0, bit 30 */
378 uint8_t classValid:1; /* FC Word 0, bit 31 */
379
380#endif
381
382 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
383
384#ifdef __BIG_ENDIAN_BITFIELD
385 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
386 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
387 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
388 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
389 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
390#else /* __LITTLE_ENDIAN_BITFIELD */
391 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
392 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
393 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
394 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
395 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
396#endif
397
398 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
399
400#ifdef __BIG_ENDIAN_BITFIELD
401 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
402 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
403 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
404 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
405 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
406 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
407#else /* __LITTLE_ENDIAN_BITFIELD */
408 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
409 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
410 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
411 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
412 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
413 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
414#endif
415
416 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
417 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
418 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
419
420 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
421 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
422 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
423 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
424
425 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
426 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
427 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
428 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
429};
430
431struct serv_parm { /* Structure is in Big Endian format */
432 struct csp cmn;
433 struct lpfc_name portName;
434 struct lpfc_name nodeName;
435 struct class_parms cls1;
436 struct class_parms cls2;
437 struct class_parms cls3;
438 struct class_parms cls4;
439 uint8_t vendorVersion[16];
440};
441
442/*
443 * Extended Link Service LS_COMMAND codes (Payload Word 0)
444 */
445#ifdef __BIG_ENDIAN_BITFIELD
446#define ELS_CMD_MASK 0xffff0000
447#define ELS_RSP_MASK 0xff000000
448#define ELS_CMD_LS_RJT 0x01000000
449#define ELS_CMD_ACC 0x02000000
450#define ELS_CMD_PLOGI 0x03000000
451#define ELS_CMD_FLOGI 0x04000000
452#define ELS_CMD_LOGO 0x05000000
453#define ELS_CMD_ABTX 0x06000000
454#define ELS_CMD_RCS 0x07000000
455#define ELS_CMD_RES 0x08000000
456#define ELS_CMD_RSS 0x09000000
457#define ELS_CMD_RSI 0x0A000000
458#define ELS_CMD_ESTS 0x0B000000
459#define ELS_CMD_ESTC 0x0C000000
460#define ELS_CMD_ADVC 0x0D000000
461#define ELS_CMD_RTV 0x0E000000
462#define ELS_CMD_RLS 0x0F000000
463#define ELS_CMD_ECHO 0x10000000
464#define ELS_CMD_TEST 0x11000000
465#define ELS_CMD_RRQ 0x12000000
466#define ELS_CMD_PRLI 0x20100014
467#define ELS_CMD_PRLO 0x21100014
82d9a2a2 468#define ELS_CMD_PRLO_ACC 0x02100014
dea3101e
JB		 469#define ELS_CMD_PDISC 0x50000000
470#define ELS_CMD_FDISC 0x51000000
471#define ELS_CMD_ADISC 0x52000000
472#define ELS_CMD_FARP 0x54000000
473#define ELS_CMD_FARPR 0x55000000
7bb3b137
JW		 474#define ELS_CMD_RPS 0x56000000
475#define ELS_CMD_RPL 0x57000000
dea3101e
JB		 476#define ELS_CMD_FAN 0x60000000
477#define ELS_CMD_RSCN 0x61040000
478#define ELS_CMD_SCR 0x62000000
479#define ELS_CMD_RNID 0x78000000
7bb3b137 480#define ELS_CMD_LIRR 0x7A000000
dea3101e
JB		 481#else /* __LITTLE_ENDIAN_BITFIELD */
482#define ELS_CMD_MASK 0xffff
483#define ELS_RSP_MASK 0xff
484#define ELS_CMD_LS_RJT 0x01
485#define ELS_CMD_ACC 0x02
486#define ELS_CMD_PLOGI 0x03
487#define ELS_CMD_FLOGI 0x04
488#define ELS_CMD_LOGO 0x05
489#define ELS_CMD_ABTX 0x06
490#define ELS_CMD_RCS 0x07
491#define ELS_CMD_RES 0x08
492#define ELS_CMD_RSS 0x09
493#define ELS_CMD_RSI 0x0A
494#define ELS_CMD_ESTS 0x0B
495#define ELS_CMD_ESTC 0x0C
496#define ELS_CMD_ADVC 0x0D
497#define ELS_CMD_RTV 0x0E
498#define ELS_CMD_RLS 0x0F
499#define ELS_CMD_ECHO 0x10
500#define ELS_CMD_TEST 0x11
501#define ELS_CMD_RRQ 0x12
502#define ELS_CMD_PRLI 0x14001020
503#define ELS_CMD_PRLO 0x14001021
82d9a2a2 504#define ELS_CMD_PRLO_ACC 0x14001002
dea3101e
JB		 505#define ELS_CMD_PDISC 0x50
506#define ELS_CMD_FDISC 0x51
507#define ELS_CMD_ADISC 0x52
508#define ELS_CMD_FARP 0x54
509#define ELS_CMD_FARPR 0x55
7bb3b137
JW		 510#define ELS_CMD_RPS 0x56
511#define ELS_CMD_RPL 0x57
dea3101e
JB		 512#define ELS_CMD_FAN 0x60
513#define ELS_CMD_RSCN 0x0461
514#define ELS_CMD_SCR 0x62
515#define ELS_CMD_RNID 0x78
7bb3b137 516#define ELS_CMD_LIRR 0x7A
dea3101e
JB		 517#endif
518
519/*
520 * LS_RJT Payload Definition
521 */
522
523struct ls_rjt { /* Structure is in Big Endian format */
524 union {
525 uint32_t lsRjtError;
526 struct {
527 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
528
529 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
530 /* LS_RJT reason codes */
531#define LSRJT_INVALID_CMD 0x01
532#define LSRJT_LOGICAL_ERR 0x03
533#define LSRJT_LOGICAL_BSY 0x05
534#define LSRJT_PROTOCOL_ERR 0x07
535#define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
536#define LSRJT_CMD_UNSUPPORTED 0x0B
537#define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
538
539 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
540 /* LS_RJT reason explanation */
541#define LSEXP_NOTHING_MORE 0x00
542#define LSEXP_SPARM_OPTIONS 0x01
543#define LSEXP_SPARM_ICTL 0x03
544#define LSEXP_SPARM_RCTL 0x05
545#define LSEXP_SPARM_RCV_SIZE 0x07
546#define LSEXP_SPARM_CONCUR_SEQ 0x09
547#define LSEXP_SPARM_CREDIT 0x0B
548#define LSEXP_INVALID_PNAME 0x0D
549#define LSEXP_INVALID_NNAME 0x0E
550#define LSEXP_INVALID_CSP 0x0F
551#define LSEXP_INVALID_ASSOC_HDR 0x11
552#define LSEXP_ASSOC_HDR_REQ 0x13
553#define LSEXP_INVALID_O_SID 0x15
554#define LSEXP_INVALID_OX_RX 0x17
555#define LSEXP_CMD_IN_PROGRESS 0x19
556#define LSEXP_INVALID_NPORT_ID 0x1F
557#define LSEXP_INVALID_SEQ_ID 0x21
558#define LSEXP_INVALID_XCHG 0x23
559#define LSEXP_INACTIVE_XCHG 0x25
560#define LSEXP_RQ_REQUIRED 0x27
561#define LSEXP_OUT_OF_RESOURCE 0x29
562#define LSEXP_CANT_GIVE_DATA 0x2A
563#define LSEXP_REQ_UNSUPPORTED 0x2C
564 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
565 } b;
566 } un;
567};
568
569/*
570 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
571 */
572
573typedef struct _LOGO { /* Structure is in Big Endian format */
574 union {
575 uint32_t nPortId32; /* Access nPortId as a word */
576 struct {
577 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
578 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
579 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
580 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
581 } b;
582 } un;
583 struct lpfc_name portName; /* N_port name field */
584} LOGO;
585
586/*
587 * FCP Login (PRLI Request / ACC) Payload Definition
588 */
589
590#define PRLX_PAGE_LEN 0x10
591#define TPRLO_PAGE_LEN 0x14
592
593typedef struct _PRLI { /* Structure is in Big Endian format */
594 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
595
596#define PRLI_FCP_TYPE 0x08
597 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
598
599#ifdef __BIG_ENDIAN_BITFIELD
600 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
601 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
602 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
603
604 /* ACC = imagePairEstablished */
605 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
606 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
607#else /* __LITTLE_ENDIAN_BITFIELD */
608 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
609 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
610 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
611 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
612 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
613 /* ACC = imagePairEstablished */
614#endif
615
616#define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
617#define PRLI_NO_RESOURCES 0x2
618#define PRLI_INIT_INCOMPLETE 0x3
619#define PRLI_NO_SUCH_PA 0x4
620#define PRLI_PREDEF_CONFIG 0x5
621#define PRLI_PARTIAL_SUCCESS 0x6
622#define PRLI_INVALID_PAGE_CNT 0x7
623 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
624
625 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
626
627 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
628
629 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
630 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
631
632#ifdef __BIG_ENDIAN_BITFIELD
633 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
634 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
635 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
636 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
637 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
638 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
639 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
640 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
641 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
642 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
643 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
644 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
645 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
646 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
647 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
648 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
649#else /* __LITTLE_ENDIAN_BITFIELD */
650 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
651 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
652 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
653 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
654 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
655 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
656 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
657 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
658 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
659 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
660 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
661 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
662 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
663 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
664 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
665 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
666#endif
667} PRLI;
668
669/*
670 * FCP Logout (PRLO Request / ACC) Payload Definition
671 */
672
673typedef struct _PRLO { /* Structure is in Big Endian format */
674 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
675
676#define PRLO_FCP_TYPE 0x08
677 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
678
679#ifdef __BIG_ENDIAN_BITFIELD
680 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
681 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
682 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
683 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
684#else /* __LITTLE_ENDIAN_BITFIELD */
685 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
686 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
687 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
688 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
689#endif
690
691#define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
692#define PRLO_NO_SUCH_IMAGE 0x4
693#define PRLO_INVALID_PAGE_CNT 0x7
694
695 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
696
697 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
698
699 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
700
701 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
702} PRLO;
703
704typedef struct _ADISC { /* Structure is in Big Endian format */
705 uint32_t hardAL_PA;
706 struct lpfc_name portName;
707 struct lpfc_name nodeName;
708 uint32_t DID;
709} ADISC;
710
711typedef struct _FARP { /* Structure is in Big Endian format */
712 uint32_t Mflags:8;
713 uint32_t Odid:24;
714#define FARP_NO_ACTION 0 /* FARP information enclosed, no
715 action */
716#define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
717#define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
718#define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
719#define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
720 supported */
721#define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
722 supported */
723 uint32_t Rflags:8;
724 uint32_t Rdid:24;
725#define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
726#define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
727 struct lpfc_name OportName;
728 struct lpfc_name OnodeName;
729 struct lpfc_name RportName;
730 struct lpfc_name RnodeName;
731 uint8_t Oipaddr[16];
732 uint8_t Ripaddr[16];
733} FARP;
734
735typedef struct _FAN { /* Structure is in Big Endian format */
736 uint32_t Fdid;
737 struct lpfc_name FportName;
738 struct lpfc_name FnodeName;
739} FAN;
740
741typedef struct _SCR { /* Structure is in Big Endian format */
742 uint8_t resvd1;
743 uint8_t resvd2;
744 uint8_t resvd3;
745 uint8_t Function;
746#define SCR_FUNC_FABRIC 0x01
747#define SCR_FUNC_NPORT 0x02
748#define SCR_FUNC_FULL 0x03
749#define SCR_CLEAR 0xff
750} SCR;
751
752typedef struct _RNID_TOP_DISC {
753 struct lpfc_name portName;
754 uint8_t resvd[8];
755 uint32_t unitType;
756#define RNID_HBA 0x7
757#define RNID_HOST 0xa
758#define RNID_DRIVER 0xd
759 uint32_t physPort;
760 uint32_t attachedNodes;
761 uint16_t ipVersion;
762#define RNID_IPV4 0x1
763#define RNID_IPV6 0x2
764 uint16_t UDPport;
765 uint8_t ipAddr[16];
766 uint16_t resvd1;
767 uint16_t flags;
768#define RNID_TD_SUPPORT 0x1
769#define RNID_LP_VALID 0x2
770} RNID_TOP_DISC;
771
772typedef struct _RNID { /* Structure is in Big Endian format */
773 uint8_t Format;
774#define RNID_TOPOLOGY_DISC 0xdf
775 uint8_t CommonLen;
776 uint8_t resvd1;
777 uint8_t SpecificLen;
778 struct lpfc_name portName;
779 struct lpfc_name nodeName;
780 union {
781 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
782 } un;
783} RNID;
784
7bb3b137
JW		 785typedef struct _RPS { /* Structure is in Big Endian format */
786 union {
787 uint32_t portNum;
788 struct lpfc_name portName;
789 } un;
790} RPS;
791
792typedef struct _RPS_RSP { /* Structure is in Big Endian format */
793 uint16_t rsvd1;
794 uint16_t portStatus;
795 uint32_t linkFailureCnt;
796 uint32_t lossSyncCnt;
797 uint32_t lossSignalCnt;
798 uint32_t primSeqErrCnt;
799 uint32_t invalidXmitWord;
800 uint32_t crcCnt;
801} RPS_RSP;
802
803typedef struct _RPL { /* Structure is in Big Endian format */
804 uint32_t maxsize;
805 uint32_t index;
806} RPL;
807
808typedef struct _PORT_NUM_BLK {
809 uint32_t portNum;
810 uint32_t portID;
811 struct lpfc_name portName;
812} PORT_NUM_BLK;
813
814typedef struct _RPL_RSP { /* Structure is in Big Endian format */
815 uint32_t listLen;
816 uint32_t index;
817 PORT_NUM_BLK port_num_blk;
818} RPL_RSP;
dea3101e
JB		 819
820/* This is used for RSCN command */
821typedef struct _D_ID { /* Structure is in Big Endian format */
822 union {
823 uint32_t word;
824 struct {
825#ifdef __BIG_ENDIAN_BITFIELD
826 uint8_t resv;
827 uint8_t domain;
828 uint8_t area;
829 uint8_t id;
830#else /* __LITTLE_ENDIAN_BITFIELD */
831 uint8_t id;
832 uint8_t area;
833 uint8_t domain;
834 uint8_t resv;
835#endif
836 } b;
837 } un;
838} D_ID;
839
840/*
841 * Structure to define all ELS Payload types
842 */
843
844typedef struct _ELS_PKT { /* Structure is in Big Endian format */
845 uint8_t elsCode; /* FC Word 0, bit 24:31 */
846 uint8_t elsByte1;
847 uint8_t elsByte2;
848 uint8_t elsByte3;
849 union {
850 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
851 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
852 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
853 PRLI prli; /* Payload for PRLI/ACC */
854 PRLO prlo; /* Payload for PRLO/ACC */
855 ADISC adisc; /* Payload for ADISC/ACC */
856 FARP farp; /* Payload for FARP/ACC */
857 FAN fan; /* Payload for FAN */
858 SCR scr; /* Payload for SCR/ACC */
dea3101e
JB		 859 RNID rnid; /* Payload for RNID */
860 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
861 } un;
862} ELS_PKT;
863
864/*
865 * FDMI
866 * HBA MAnagement Operations Command Codes
867 */
868#define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
869#define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
870#define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
871#define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
872#define SLI_MGMT_RHBA 0x200 /* Register HBA */
873#define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */
874#define SLI_MGMT_RPRT 0x210 /* Register Port */
875#define SLI_MGMT_RPA 0x211 /* Register Port attributes */
876#define SLI_MGMT_DHBA 0x300 /* De-register HBA */
877#define SLI_MGMT_DPRT 0x310 /* De-register Port */
878
879/*
880 * Management Service Subtypes
881 */
882#define SLI_CT_FDMI_Subtypes 0x10
883
884/*
885 * HBA Management Service Reject Code
886 */
887#define REJECT_CODE 0x9 /* Unable to perform command request */
888
889/*
890 * HBA Management Service Reject Reason Code
891 * Please refer to the Reason Codes above
892 */
893
894/*
895 * HBA Attribute Types
896 */
897#define NODE_NAME 0x1
898#define MANUFACTURER 0x2
899#define SERIAL_NUMBER 0x3
900#define MODEL 0x4
901#define MODEL_DESCRIPTION 0x5
902#define HARDWARE_VERSION 0x6
903#define DRIVER_VERSION 0x7
904#define OPTION_ROM_VERSION 0x8
905#define FIRMWARE_VERSION 0x9
906#define OS_NAME_VERSION 0xa
907#define MAX_CT_PAYLOAD_LEN 0xb
908
909/*
910 * Port Attrubute Types
911 */
912#define SUPPORTED_FC4_TYPES 0x1
913#define SUPPORTED_SPEED 0x2
914#define PORT_SPEED 0x3
915#define MAX_FRAME_SIZE 0x4
916#define OS_DEVICE_NAME 0x5
917#define HOST_NAME 0x6
918
919union AttributesDef {
920 /* Structure is in Big Endian format */
921 struct {
922 uint32_t AttrType:16;
923 uint32_t AttrLen:16;
924 } bits;
925 uint32_t word;
926};
927
928
929/*
930 * HBA Attribute Entry (8 - 260 bytes)
931 */
932typedef struct {
933 union AttributesDef ad;
934 union {
935 uint32_t VendorSpecific;
936 uint8_t Manufacturer[64];
937 uint8_t SerialNumber[64];
938 uint8_t Model[256];
939 uint8_t ModelDescription[256];
940 uint8_t HardwareVersion[256];
941 uint8_t DriverVersion[256];
942 uint8_t OptionROMVersion[256];
943 uint8_t FirmwareVersion[256];
944 struct lpfc_name NodeName;
945 uint8_t SupportFC4Types[32];
946 uint32_t SupportSpeed;
947 uint32_t PortSpeed;
948 uint32_t MaxFrameSize;
949 uint8_t OsDeviceName[256];
950 uint8_t OsNameVersion[256];
951 uint32_t MaxCTPayloadLen;
952 uint8_t HostName[256];
953 } un;
954} ATTRIBUTE_ENTRY;
955
956/*
957 * HBA Attribute Block
958 */
959typedef struct {
960 uint32_t EntryCnt; /* Number of HBA attribute entries */
961 ATTRIBUTE_ENTRY Entry; /* Variable-length array */
962} ATTRIBUTE_BLOCK;
963
964/*
965 * Port Entry
966 */
967typedef struct {
968 struct lpfc_name PortName;
969} PORT_ENTRY;
970
971/*
972 * HBA Identifier
973 */
974typedef struct {
975 struct lpfc_name PortName;
976} HBA_IDENTIFIER;
977
978/*
979 * Registered Port List Format
980 */
981typedef struct {
982 uint32_t EntryCnt;
983 PORT_ENTRY pe; /* Variable-length array */
984} REG_PORT_LIST;
985
986/*
987 * Register HBA(RHBA)
988 */
989typedef struct {
990 HBA_IDENTIFIER hi;
991 REG_PORT_LIST rpl; /* variable-length array */
992/* ATTRIBUTE_BLOCK ab; */
993} REG_HBA;
994
995/*
996 * Register HBA Attributes (RHAT)
997 */
998typedef struct {
999 struct lpfc_name HBA_PortName;
1000 ATTRIBUTE_BLOCK ab;
1001} REG_HBA_ATTRIBUTE;
1002
1003/*
1004 * Register Port Attributes (RPA)
1005 */
1006typedef struct {
1007 struct lpfc_name PortName;
1008 ATTRIBUTE_BLOCK ab;
1009} REG_PORT_ATTRIBUTE;
1010
1011/*
1012 * Get Registered HBA List (GRHL) Accept Payload Format
1013 */
1014typedef struct {
1015 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1016 struct lpfc_name HBA_PortName; /* Variable-length array */
1017} GRHL_ACC_PAYLOAD;
1018
1019/*
1020 * Get Registered Port List (GRPL) Accept Payload Format
1021 */
1022typedef struct {
1023 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1024 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
1025} GRPL_ACC_PAYLOAD;
1026
1027/*
1028 * Get Port Attributes (GPAT) Accept Payload Format
1029 */
1030
1031typedef struct {
1032 ATTRIBUTE_BLOCK pab;
1033} GPAT_ACC_PAYLOAD;
1034
1035
1036/*
1037 * Begin HBA configuration parameters.
1038 * The PCI configuration register BAR assignments are:
1039 * BAR0, offset 0x10 - SLIM base memory address
1040 * BAR1, offset 0x14 - SLIM base memory high address
1041 * BAR2, offset 0x18 - REGISTER base memory address
1042 * BAR3, offset 0x1c - REGISTER base memory high address
1043 * BAR4, offset 0x20 - BIU I/O registers
1044 * BAR5, offset 0x24 - REGISTER base io high address
1045 */
1046
1047/* Number of rings currently used and available. */
1048#define MAX_CONFIGURED_RINGS 3
1049#define MAX_RINGS 4
1050
1051/* IOCB / Mailbox is owned by FireFly */
1052#define OWN_CHIP 1
1053
1054/* IOCB / Mailbox is owned by Host */
1055#define OWN_HOST 0
1056
1057/* Number of 4-byte words in an IOCB. */
1058#define IOCB_WORD_SZ 8
1059
1060/* defines for type field in fc header */
1061#define FC_ELS_DATA 0x1
1062#define FC_LLC_SNAP 0x5
1063#define FC_FCP_DATA 0x8
1064#define FC_COMMON_TRANSPORT_ULP 0x20
1065
1066/* defines for rctl field in fc header */
1067#define FC_DEV_DATA 0x0
1068#define FC_UNSOL_CTL 0x2
1069#define FC_SOL_CTL 0x3
1070#define FC_UNSOL_DATA 0x4
1071#define FC_FCP_CMND 0x6
1072#define FC_ELS_REQ 0x22
1073#define FC_ELS_RSP 0x23
1074
1075/* network headers for Dfctl field */
1076#define FC_NET_HDR 0x20
1077
1078/* Start FireFly Register definitions */
1079#define PCI_VENDOR_ID_EMULEX 0x10df
1080#define PCI_DEVICE_ID_FIREFLY 0x1ae5
dea3101e
JB		 1081#define PCI_DEVICE_ID_RFLY 0xf095
1082#define PCI_DEVICE_ID_PFLY 0xf098
e4adb204 1083#define PCI_DEVICE_ID_LP101 0xf0a1
dea3101e 1084#define PCI_DEVICE_ID_TFLY 0xf0a5
e4adb204
JSEC		 1085#define PCI_DEVICE_ID_BSMB 0xf0d1
1086#define PCI_DEVICE_ID_BMID 0xf0d5
1087#define PCI_DEVICE_ID_ZSMB 0xf0e1
1088#define PCI_DEVICE_ID_ZMID 0xf0e5
1089#define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1090#define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1091#define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1092#define PCI_DEVICE_ID_SUPERFLY 0xf700
1093#define PCI_DEVICE_ID_DRAGONFLY 0xf800
dea3101e
JB		 1094#define PCI_DEVICE_ID_CENTAUR 0xf900
1095#define PCI_DEVICE_ID_PEGASUS 0xf980
1096#define PCI_DEVICE_ID_THOR 0xfa00
1097#define PCI_DEVICE_ID_VIPER 0xfb00
e4adb204
JSEC		 1098#define PCI_DEVICE_ID_LP10000S 0xfc00
1099#define PCI_DEVICE_ID_LP11000S 0xfc10
1100#define PCI_DEVICE_ID_LPE11000S 0xfc20
dea3101e 1101#define PCI_DEVICE_ID_HELIOS 0xfd00
e4adb204
JSEC		 1102#define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1103#define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
dea3101e 1104#define PCI_DEVICE_ID_ZEPHYR 0xfe00
e4adb204
JSEC		 1105#define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1106#define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
dea3101e 1107
5cc36b3c
JSEC		 1108#define PCI_SUBSYSTEM_ID_LP11000S 0xfc11
1109#define PCI_SUBSYSTEM_ID_LP11002S 0xfc12
1110#define PCI_SUBSYSTEM_ID_LPE11000S 0xfc21
1111#define PCI_SUBSYSTEM_ID_LPE11002S 0xfc22
1112#define PCI_SUBSYSTEM_ID_LPE11010S 0xfc2A
1113
dea3101e
JB		 1114#define JEDEC_ID_ADDRESS 0x0080001c
1115#define FIREFLY_JEDEC_ID 0x1ACC
1116#define SUPERFLY_JEDEC_ID 0x0020
1117#define DRAGONFLY_JEDEC_ID 0x0021
1118#define DRAGONFLY_V2_JEDEC_ID 0x0025
1119#define CENTAUR_2G_JEDEC_ID 0x0026
1120#define CENTAUR_1G_JEDEC_ID 0x0028
1121#define PEGASUS_ORION_JEDEC_ID 0x0036
1122#define PEGASUS_JEDEC_ID 0x0038
1123#define THOR_JEDEC_ID 0x0012
1124#define HELIOS_JEDEC_ID 0x0364
1125#define ZEPHYR_JEDEC_ID 0x0577
1126#define VIPER_JEDEC_ID 0x4838
1127
1128#define JEDEC_ID_MASK 0x0FFFF000
1129#define JEDEC_ID_SHIFT 12
1130#define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1131
1132typedef struct { /* FireFly BIU registers */
1133 uint32_t hostAtt; /* See definitions for Host Attention
1134 register */
1135 uint32_t chipAtt; /* See definitions for Chip Attention
1136 register */
1137 uint32_t hostStatus; /* See definitions for Host Status register */
1138 uint32_t hostControl; /* See definitions for Host Control register */
1139 uint32_t buiConfig; /* See definitions for BIU configuration
1140 register */
1141} FF_REGS;
1142
1143/* IO Register size in bytes */
1144#define FF_REG_AREA_SIZE 256
1145
1146/* Host Attention Register */
1147
1148#define HA_REG_OFFSET 0 /* Byte offset from register base address */
1149
1150#define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1151#define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1152#define HA_R0ATT 0x00000008 /* Bit 3 */
1153#define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1154#define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1155#define HA_R1ATT 0x00000080 /* Bit 7 */
1156#define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1157#define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1158#define HA_R2ATT 0x00000800 /* Bit 11 */
1159#define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1160#define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1161#define HA_R3ATT 0x00008000 /* Bit 15 */
1162#define HA_LATT 0x20000000 /* Bit 29 */
1163#define HA_MBATT 0x40000000 /* Bit 30 */
1164#define HA_ERATT 0x80000000 /* Bit 31 */
1165
1166#define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1167#define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1168#define HA_RXATT 0x00000008 /* Bit 3 */
1169#define HA_RXMASK 0x0000000f
1170
1171/* Chip Attention Register */
1172
1173#define CA_REG_OFFSET 4 /* Byte offset from register base address */
1174
1175#define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1176#define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1177#define CA_R0ATT 0x00000008 /* Bit 3 */
1178#define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1179#define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1180#define CA_R1ATT 0x00000080 /* Bit 7 */
1181#define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1182#define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1183#define CA_R2ATT 0x00000800 /* Bit 11 */
1184#define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1185#define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1186#define CA_R3ATT 0x00008000 /* Bit 15 */
1187#define CA_MBATT 0x40000000 /* Bit 30 */
1188
1189/* Host Status Register */
1190
1191#define HS_REG_OFFSET 8 /* Byte offset from register base address */
1192
1193#define HS_MBRDY 0x00400000 /* Bit 22 */
1194#define HS_FFRDY 0x00800000 /* Bit 23 */
1195#define HS_FFER8 0x01000000 /* Bit 24 */
1196#define HS_FFER7 0x02000000 /* Bit 25 */
1197#define HS_FFER6 0x04000000 /* Bit 26 */
1198#define HS_FFER5 0x08000000 /* Bit 27 */
1199#define HS_FFER4 0x10000000 /* Bit 28 */
1200#define HS_FFER3 0x20000000 /* Bit 29 */
1201#define HS_FFER2 0x40000000 /* Bit 30 */
1202#define HS_FFER1 0x80000000 /* Bit 31 */
1203#define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */
1204
1205/* Host Control Register */
1206
1207#define HC_REG_OFFSET 12 /* Word offset from register base address */
1208
1209#define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1210#define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1211#define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1212#define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1213#define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1214#define HC_INITHBI 0x02000000 /* Bit 25 */
1215#define HC_INITMB 0x04000000 /* Bit 26 */
1216#define HC_INITFF 0x08000000 /* Bit 27 */
1217#define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1218#define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1219
1220/* Mailbox Commands */
1221#define MBX_SHUTDOWN 0x00 /* terminate testing */
1222#define MBX_LOAD_SM 0x01
1223#define MBX_READ_NV 0x02
1224#define MBX_WRITE_NV 0x03
1225#define MBX_RUN_BIU_DIAG 0x04
1226#define MBX_INIT_LINK 0x05
1227#define MBX_DOWN_LINK 0x06
1228#define MBX_CONFIG_LINK 0x07
1229#define MBX_CONFIG_RING 0x09
1230#define MBX_RESET_RING 0x0A
1231#define MBX_READ_CONFIG 0x0B
1232#define MBX_READ_RCONFIG 0x0C
1233#define MBX_READ_SPARM 0x0D
1234#define MBX_READ_STATUS 0x0E
1235#define MBX_READ_RPI 0x0F
1236#define MBX_READ_XRI 0x10
1237#define MBX_READ_REV 0x11
1238#define MBX_READ_LNK_STAT 0x12
1239#define MBX_REG_LOGIN 0x13
1240#define MBX_UNREG_LOGIN 0x14
1241#define MBX_READ_LA 0x15
1242#define MBX_CLEAR_LA 0x16
1243#define MBX_DUMP_MEMORY 0x17
1244#define MBX_DUMP_CONTEXT 0x18
1245#define MBX_RUN_DIAGS 0x19
1246#define MBX_RESTART 0x1A
1247#define MBX_UPDATE_CFG 0x1B
1248#define MBX_DOWN_LOAD 0x1C
1249#define MBX_DEL_LD_ENTRY 0x1D
1250#define MBX_RUN_PROGRAM 0x1E
1251#define MBX_SET_MASK 0x20
1252#define MBX_SET_SLIM 0x21
1253#define MBX_UNREG_D_ID 0x23
41415862 1254#define MBX_KILL_BOARD 0x24
dea3101e 1255#define MBX_CONFIG_FARP 0x25
41415862 1256#define MBX_BEACON 0x2A
dea3101e
JB		 1257
1258#define MBX_LOAD_AREA 0x81
1259#define MBX_RUN_BIU_DIAG64 0x84
1260#define MBX_CONFIG_PORT 0x88
1261#define MBX_READ_SPARM64 0x8D
1262#define MBX_READ_RPI64 0x8F
1263#define MBX_REG_LOGIN64 0x93
1264#define MBX_READ_LA64 0x95
1265
1266#define MBX_FLASH_WR_ULA 0x98
1267#define MBX_SET_DEBUG 0x99
1268#define MBX_LOAD_EXP_ROM 0x9C
1269
1270#define MBX_MAX_CMDS 0x9D
1271#define MBX_SLI2_CMD_MASK 0x80
1272
1273/* IOCB Commands */
1274
1275#define CMD_RCV_SEQUENCE_CX 0x01
1276#define CMD_XMIT_SEQUENCE_CR 0x02
1277#define CMD_XMIT_SEQUENCE_CX 0x03
1278#define CMD_XMIT_BCAST_CN 0x04
1279#define CMD_XMIT_BCAST_CX 0x05
1280#define CMD_QUE_RING_BUF_CN 0x06
1281#define CMD_QUE_XRI_BUF_CX 0x07
1282#define CMD_IOCB_CONTINUE_CN 0x08
1283#define CMD_RET_XRI_BUF_CX 0x09
1284#define CMD_ELS_REQUEST_CR 0x0A
1285#define CMD_ELS_REQUEST_CX 0x0B
1286#define CMD_RCV_ELS_REQ_CX 0x0D
1287#define CMD_ABORT_XRI_CN 0x0E
1288#define CMD_ABORT_XRI_CX 0x0F
1289#define CMD_CLOSE_XRI_CN 0x10
1290#define CMD_CLOSE_XRI_CX 0x11
1291#define CMD_CREATE_XRI_CR 0x12
1292#define CMD_CREATE_XRI_CX 0x13
1293#define CMD_GET_RPI_CN 0x14
1294#define CMD_XMIT_ELS_RSP_CX 0x15
1295#define CMD_GET_RPI_CR 0x16
1296#define CMD_XRI_ABORTED_CX 0x17
1297#define CMD_FCP_IWRITE_CR 0x18
1298#define CMD_FCP_IWRITE_CX 0x19
1299#define CMD_FCP_IREAD_CR 0x1A
1300#define CMD_FCP_IREAD_CX 0x1B
1301#define CMD_FCP_ICMND_CR 0x1C
1302#define CMD_FCP_ICMND_CX 0x1D
1303
1304#define CMD_ADAPTER_MSG 0x20
1305#define CMD_ADAPTER_DUMP 0x22
1306
1307/* SLI_2 IOCB Command Set */
1308
1309#define CMD_RCV_SEQUENCE64_CX 0x81
1310#define CMD_XMIT_SEQUENCE64_CR 0x82
1311#define CMD_XMIT_SEQUENCE64_CX 0x83
1312#define CMD_XMIT_BCAST64_CN 0x84
1313#define CMD_XMIT_BCAST64_CX 0x85
1314#define CMD_QUE_RING_BUF64_CN 0x86
1315#define CMD_QUE_XRI_BUF64_CX 0x87
1316#define CMD_IOCB_CONTINUE64_CN 0x88
1317#define CMD_RET_XRI_BUF64_CX 0x89
1318#define CMD_ELS_REQUEST64_CR 0x8A
1319#define CMD_ELS_REQUEST64_CX 0x8B
1320#define CMD_ABORT_MXRI64_CN 0x8C
1321#define CMD_RCV_ELS_REQ64_CX 0x8D
1322#define CMD_XMIT_ELS_RSP64_CX 0x95
1323#define CMD_FCP_IWRITE64_CR 0x98
1324#define CMD_FCP_IWRITE64_CX 0x99
1325#define CMD_FCP_IREAD64_CR 0x9A
1326#define CMD_FCP_IREAD64_CX 0x9B
1327#define CMD_FCP_ICMND64_CR 0x9C
1328#define CMD_FCP_ICMND64_CX 0x9D
1329
1330#define CMD_GEN_REQUEST64_CR 0xC2
1331#define CMD_GEN_REQUEST64_CX 0xC3
1332
1333#define CMD_MAX_IOCB_CMD 0xE6
1334#define CMD_IOCB_MASK 0xff
1335
1336#define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1337 iocb */
1338#define LPFC_MAX_ADPTMSG 32 /* max msg data */
1339/*
1340 * Define Status
1341 */
1342#define MBX_SUCCESS 0
1343#define MBXERR_NUM_RINGS 1
1344#define MBXERR_NUM_IOCBS 2
1345#define MBXERR_IOCBS_EXCEEDED 3
1346#define MBXERR_BAD_RING_NUMBER 4
1347#define MBXERR_MASK_ENTRIES_RANGE 5
1348#define MBXERR_MASKS_EXCEEDED 6
1349#define MBXERR_BAD_PROFILE 7
1350#define MBXERR_BAD_DEF_CLASS 8
1351#define MBXERR_BAD_MAX_RESPONDER 9
1352#define MBXERR_BAD_MAX_ORIGINATOR 10
1353#define MBXERR_RPI_REGISTERED 11
1354#define MBXERR_RPI_FULL 12
1355#define MBXERR_NO_RESOURCES 13
1356#define MBXERR_BAD_RCV_LENGTH 14
1357#define MBXERR_DMA_ERROR 15
1358#define MBXERR_ERROR 16
1359#define MBX_NOT_FINISHED 255
1360
1361#define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1362#define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1363
1364/*
1365 * Begin Structure Definitions for Mailbox Commands
1366 */
1367
1368typedef struct {
1369#ifdef __BIG_ENDIAN_BITFIELD
1370 uint8_t tval;
1371 uint8_t tmask;
1372 uint8_t rval;
1373 uint8_t rmask;
1374#else /* __LITTLE_ENDIAN_BITFIELD */
1375 uint8_t rmask;
1376 uint8_t rval;
1377 uint8_t tmask;
1378 uint8_t tval;
1379#endif
1380} RR_REG;
1381
1382struct ulp_bde {
1383 uint32_t bdeAddress;
1384#ifdef __BIG_ENDIAN_BITFIELD
1385 uint32_t bdeReserved:4;
1386 uint32_t bdeAddrHigh:4;
1387 uint32_t bdeSize:24;
1388#else /* __LITTLE_ENDIAN_BITFIELD */
1389 uint32_t bdeSize:24;
1390 uint32_t bdeAddrHigh:4;
1391 uint32_t bdeReserved:4;
1392#endif
1393};
1394
1395struct ulp_bde64 { /* SLI-2 */
1396 union ULP_BDE_TUS {
1397 uint32_t w;
1398 struct {
1399#ifdef __BIG_ENDIAN_BITFIELD
1400 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1401 VALUE !! */
1402 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1403#else /* __LITTLE_ENDIAN_BITFIELD */
1404 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1405 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1406 VALUE !! */
1407#endif
1408
1409#define BUFF_USE_RSVD 0x01 /* bdeFlags */
1410#define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */
1411#define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */
1412#define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit
1413 buffer */
1414#define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit
1415 addr */
1416#define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */
1417#define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */
1418#define BUFF_TYPE_INVALID 0x80 /* "" "" */
1419 } f;
1420 } tus;
1421 uint32_t addrLow;
1422 uint32_t addrHigh;
1423};
1424#define BDE64_SIZE_WORD 0
1425#define BPL64_SIZE_WORD 0x40
1426
1427typedef struct ULP_BDL { /* SLI-2 */
1428#ifdef __BIG_ENDIAN_BITFIELD
1429 uint32_t bdeFlags:8; /* BDL Flags */
1430 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1431#else /* __LITTLE_ENDIAN_BITFIELD */
1432 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1433 uint32_t bdeFlags:8; /* BDL Flags */
1434#endif
1435
1436 uint32_t addrLow; /* Address 0:31 */
1437 uint32_t addrHigh; /* Address 32:63 */
1438 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1439} ULP_BDL;
1440
1441/* Structure for MB Command LOAD_SM and DOWN_LOAD */
1442
1443typedef struct {
1444#ifdef __BIG_ENDIAN_BITFIELD
1445 uint32_t rsvd2:25;
1446 uint32_t acknowledgment:1;
1447 uint32_t version:1;
1448 uint32_t erase_or_prog:1;
1449 uint32_t update_flash:1;
1450 uint32_t update_ram:1;
1451 uint32_t method:1;
1452 uint32_t load_cmplt:1;
1453#else /* __LITTLE_ENDIAN_BITFIELD */
1454 uint32_t load_cmplt:1;
1455 uint32_t method:1;
1456 uint32_t update_ram:1;
1457 uint32_t update_flash:1;
1458 uint32_t erase_or_prog:1;
1459 uint32_t version:1;
1460 uint32_t acknowledgment:1;
1461 uint32_t rsvd2:25;
1462#endif
1463
1464 uint32_t dl_to_adr_low;
1465 uint32_t dl_to_adr_high;
1466 uint32_t dl_len;
1467 union {
1468 uint32_t dl_from_mbx_offset;
1469 struct ulp_bde dl_from_bde;
1470 struct ulp_bde64 dl_from_bde64;
1471 } un;
1472
1473} LOAD_SM_VAR;
1474
1475/* Structure for MB Command READ_NVPARM (02) */
1476
1477typedef struct {
1478 uint32_t rsvd1[3]; /* Read as all one's */
1479 uint32_t rsvd2; /* Read as all zero's */
1480 uint32_t portname[2]; /* N_PORT name */
1481 uint32_t nodename[2]; /* NODE name */
1482
1483#ifdef __BIG_ENDIAN_BITFIELD
1484 uint32_t pref_DID:24;
1485 uint32_t hardAL_PA:8;
1486#else /* __LITTLE_ENDIAN_BITFIELD */
1487 uint32_t hardAL_PA:8;
1488 uint32_t pref_DID:24;
1489#endif
1490
1491 uint32_t rsvd3[21]; /* Read as all one's */
1492} READ_NV_VAR;
1493
1494/* Structure for MB Command WRITE_NVPARMS (03) */
1495
1496typedef struct {
1497 uint32_t rsvd1[3]; /* Must be all one's */
1498 uint32_t rsvd2; /* Must be all zero's */
1499 uint32_t portname[2]; /* N_PORT name */
1500 uint32_t nodename[2]; /* NODE name */
1501
1502#ifdef __BIG_ENDIAN_BITFIELD
1503 uint32_t pref_DID:24;
1504 uint32_t hardAL_PA:8;
1505#else /* __LITTLE_ENDIAN_BITFIELD */
1506 uint32_t hardAL_PA:8;
1507 uint32_t pref_DID:24;
1508#endif
1509
1510 uint32_t rsvd3[21]; /* Must be all one's */
1511} WRITE_NV_VAR;
1512
1513/* Structure for MB Command RUN_BIU_DIAG (04) */
1514/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1515
1516typedef struct {
1517 uint32_t rsvd1;
1518 union {
1519 struct {
1520 struct ulp_bde xmit_bde;
1521 struct ulp_bde rcv_bde;
1522 } s1;
1523 struct {
1524 struct ulp_bde64 xmit_bde64;
1525 struct ulp_bde64 rcv_bde64;
1526 } s2;
1527 } un;
1528} BIU_DIAG_VAR;
1529
1530/* Structure for MB Command INIT_LINK (05) */
1531
1532typedef struct {
1533#ifdef __BIG_ENDIAN_BITFIELD
1534 uint32_t rsvd1:24;
1535 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1536#else /* __LITTLE_ENDIAN_BITFIELD */
1537 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1538 uint32_t rsvd1:24;
1539#endif
1540
1541#ifdef __BIG_ENDIAN_BITFIELD
1542 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1543 uint8_t rsvd2;
1544 uint16_t link_flags;
1545#else /* __LITTLE_ENDIAN_BITFIELD */
1546 uint16_t link_flags;
1547 uint8_t rsvd2;
1548 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1549#endif
1550
1551#define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1552#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1553#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1554#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1555#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
1556#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1557
1558#define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1559#define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
4b0b91d4 1560#define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
dea3101e
JB		 1561
1562 uint32_t link_speed;
1563#define LINK_SPEED_AUTO 0 /* Auto selection */
1564#define LINK_SPEED_1G 1 /* 1 Gigabaud */
1565#define LINK_SPEED_2G 2 /* 2 Gigabaud */
1566#define LINK_SPEED_4G 4 /* 4 Gigabaud */
1567#define LINK_SPEED_8G 8 /* 4 Gigabaud */
1568#define LINK_SPEED_10G 16 /* 10 Gigabaud */
1569
1570} INIT_LINK_VAR;
1571
1572/* Structure for MB Command DOWN_LINK (06) */
1573
1574typedef struct {
1575 uint32_t rsvd1;
1576} DOWN_LINK_VAR;
1577
1578/* Structure for MB Command CONFIG_LINK (07) */
1579
1580typedef struct {
1581#ifdef __BIG_ENDIAN_BITFIELD
1582 uint32_t cr:1;
1583 uint32_t ci:1;
1584 uint32_t cr_delay:6;
1585 uint32_t cr_count:8;
1586 uint32_t rsvd1:8;
1587 uint32_t MaxBBC:8;
1588#else /* __LITTLE_ENDIAN_BITFIELD */
1589 uint32_t MaxBBC:8;
1590 uint32_t rsvd1:8;
1591 uint32_t cr_count:8;
1592 uint32_t cr_delay:6;
1593 uint32_t ci:1;
1594 uint32_t cr:1;
1595#endif
1596
1597 uint32_t myId;
1598 uint32_t rsvd2;
1599 uint32_t edtov;
1600 uint32_t arbtov;
1601 uint32_t ratov;
1602 uint32_t rttov;
1603 uint32_t altov;
1604 uint32_t crtov;
1605 uint32_t citov;
1606#ifdef __BIG_ENDIAN_BITFIELD
1607 uint32_t rrq_enable:1;
1608 uint32_t rrq_immed:1;
1609 uint32_t rsvd4:29;
1610 uint32_t ack0_enable:1;
1611#else /* __LITTLE_ENDIAN_BITFIELD */
1612 uint32_t ack0_enable:1;
1613 uint32_t rsvd4:29;
1614 uint32_t rrq_immed:1;
1615 uint32_t rrq_enable:1;
1616#endif
1617} CONFIG_LINK;
1618
1619/* Structure for MB Command PART_SLIM (08)
1620 * will be removed since SLI1 is no longer supported!
1621 */
1622typedef struct {
1623#ifdef __BIG_ENDIAN_BITFIELD
1624 uint16_t offCiocb;
1625 uint16_t numCiocb;
1626 uint16_t offRiocb;
1627 uint16_t numRiocb;
1628#else /* __LITTLE_ENDIAN_BITFIELD */
1629 uint16_t numCiocb;
1630 uint16_t offCiocb;
1631 uint16_t numRiocb;
1632 uint16_t offRiocb;
1633#endif
1634} RING_DEF;
1635
1636typedef struct {
1637#ifdef __BIG_ENDIAN_BITFIELD
1638 uint32_t unused1:24;
1639 uint32_t numRing:8;
1640#else /* __LITTLE_ENDIAN_BITFIELD */
1641 uint32_t numRing:8;
1642 uint32_t unused1:24;
1643#endif
1644
1645 RING_DEF ringdef[4];
1646 uint32_t hbainit;
1647} PART_SLIM_VAR;
1648
1649/* Structure for MB Command CONFIG_RING (09) */
1650
1651typedef struct {
1652#ifdef __BIG_ENDIAN_BITFIELD
1653 uint32_t unused2:6;
1654 uint32_t recvSeq:1;
1655 uint32_t recvNotify:1;
1656 uint32_t numMask:8;
1657 uint32_t profile:8;
1658 uint32_t unused1:4;
1659 uint32_t ring:4;
1660#else /* __LITTLE_ENDIAN_BITFIELD */
1661 uint32_t ring:4;
1662 uint32_t unused1:4;
1663 uint32_t profile:8;
1664 uint32_t numMask:8;
1665 uint32_t recvNotify:1;
1666 uint32_t recvSeq:1;
1667 uint32_t unused2:6;
1668#endif
1669
1670#ifdef __BIG_ENDIAN_BITFIELD
1671 uint16_t maxRespXchg;
1672 uint16_t maxOrigXchg;
1673#else /* __LITTLE_ENDIAN_BITFIELD */
1674 uint16_t maxOrigXchg;
1675 uint16_t maxRespXchg;
1676#endif
1677
1678 RR_REG rrRegs[6];
1679} CONFIG_RING_VAR;
1680
1681/* Structure for MB Command RESET_RING (10) */
1682
1683typedef struct {
1684 uint32_t ring_no;
1685} RESET_RING_VAR;
1686
1687/* Structure for MB Command READ_CONFIG (11) */
1688
1689typedef struct {
1690#ifdef __BIG_ENDIAN_BITFIELD
1691 uint32_t cr:1;
1692 uint32_t ci:1;
1693 uint32_t cr_delay:6;
1694 uint32_t cr_count:8;
1695 uint32_t InitBBC:8;
1696 uint32_t MaxBBC:8;
1697#else /* __LITTLE_ENDIAN_BITFIELD */
1698 uint32_t MaxBBC:8;
1699 uint32_t InitBBC:8;
1700 uint32_t cr_count:8;
1701 uint32_t cr_delay:6;
1702 uint32_t ci:1;
1703 uint32_t cr:1;
1704#endif
1705
1706#ifdef __BIG_ENDIAN_BITFIELD
1707 uint32_t topology:8;
1708 uint32_t myDid:24;
1709#else /* __LITTLE_ENDIAN_BITFIELD */
1710 uint32_t myDid:24;
1711 uint32_t topology:8;
1712#endif
1713
1714 /* Defines for topology (defined previously) */
1715#ifdef __BIG_ENDIAN_BITFIELD
1716 uint32_t AR:1;
1717 uint32_t IR:1;
1718 uint32_t rsvd1:29;
1719 uint32_t ack0:1;
1720#else /* __LITTLE_ENDIAN_BITFIELD */
1721 uint32_t ack0:1;
1722 uint32_t rsvd1:29;
1723 uint32_t IR:1;
1724 uint32_t AR:1;
1725#endif
1726
1727 uint32_t edtov;
1728 uint32_t arbtov;
1729 uint32_t ratov;
1730 uint32_t rttov;
1731 uint32_t altov;
1732 uint32_t lmt;
74b72a59
JW		 1733#define LMT_RESERVED 0x000 /* Not used */
1734#define LMT_1Gb 0x004
1735#define LMT_2Gb 0x008
1736#define LMT_4Gb 0x040
1737#define LMT_8Gb 0x080
1738#define LMT_10Gb 0x100
1739
dea3101e
JB		 1740
1741 uint32_t rsvd2;
1742 uint32_t rsvd3;
1743 uint32_t max_xri;
1744 uint32_t max_iocb;
1745 uint32_t max_rpi;
1746 uint32_t avail_xri;
1747 uint32_t avail_iocb;
1748 uint32_t avail_rpi;
1749 uint32_t default_rpi;
1750} READ_CONFIG_VAR;
1751
1752/* Structure for MB Command READ_RCONFIG (12) */
1753
1754typedef struct {
1755#ifdef __BIG_ENDIAN_BITFIELD
1756 uint32_t rsvd2:7;
1757 uint32_t recvNotify:1;
1758 uint32_t numMask:8;
1759 uint32_t profile:8;
1760 uint32_t rsvd1:4;
1761 uint32_t ring:4;
1762#else /* __LITTLE_ENDIAN_BITFIELD */
1763 uint32_t ring:4;
1764 uint32_t rsvd1:4;
1765 uint32_t profile:8;
1766 uint32_t numMask:8;
1767 uint32_t recvNotify:1;
1768 uint32_t rsvd2:7;
1769#endif
1770
1771#ifdef __BIG_ENDIAN_BITFIELD
1772 uint16_t maxResp;
1773 uint16_t maxOrig;
1774#else /* __LITTLE_ENDIAN_BITFIELD */
1775 uint16_t maxOrig;
1776 uint16_t maxResp;
1777#endif
1778
1779 RR_REG rrRegs[6];
1780
1781#ifdef __BIG_ENDIAN_BITFIELD
1782 uint16_t cmdRingOffset;
1783 uint16_t cmdEntryCnt;
1784 uint16_t rspRingOffset;
1785 uint16_t rspEntryCnt;
1786 uint16_t nextCmdOffset;
1787 uint16_t rsvd3;
1788 uint16_t nextRspOffset;
1789 uint16_t rsvd4;
1790#else /* __LITTLE_ENDIAN_BITFIELD */
1791 uint16_t cmdEntryCnt;
1792 uint16_t cmdRingOffset;
1793 uint16_t rspEntryCnt;
1794 uint16_t rspRingOffset;
1795 uint16_t rsvd3;
1796 uint16_t nextCmdOffset;
1797 uint16_t rsvd4;
1798 uint16_t nextRspOffset;
1799#endif
1800} READ_RCONF_VAR;
1801
1802/* Structure for MB Command READ_SPARM (13) */
1803/* Structure for MB Command READ_SPARM64 (0x8D) */
1804
1805typedef struct {
1806 uint32_t rsvd1;
1807 uint32_t rsvd2;
1808 union {
1809 struct ulp_bde sp; /* This BDE points to struct serv_parm
1810 structure */
1811 struct ulp_bde64 sp64;
1812 } un;
1813} READ_SPARM_VAR;
1814
1815/* Structure for MB Command READ_STATUS (14) */
1816
1817typedef struct {
1818#ifdef __BIG_ENDIAN_BITFIELD
1819 uint32_t rsvd1:31;
1820 uint32_t clrCounters:1;
1821 uint16_t activeXriCnt;
1822 uint16_t activeRpiCnt;
1823#else /* __LITTLE_ENDIAN_BITFIELD */
1824 uint32_t clrCounters:1;
1825 uint32_t rsvd1:31;
1826 uint16_t activeRpiCnt;
1827 uint16_t activeXriCnt;
1828#endif
1829
1830 uint32_t xmitByteCnt;
1831 uint32_t rcvByteCnt;
1832 uint32_t xmitFrameCnt;
1833 uint32_t rcvFrameCnt;
1834 uint32_t xmitSeqCnt;
1835 uint32_t rcvSeqCnt;
1836 uint32_t totalOrigExchanges;
1837 uint32_t totalRespExchanges;
1838 uint32_t rcvPbsyCnt;
1839 uint32_t rcvFbsyCnt;
1840} READ_STATUS_VAR;
1841
1842/* Structure for MB Command READ_RPI (15) */
1843/* Structure for MB Command READ_RPI64 (0x8F) */
1844
1845typedef struct {
1846#ifdef __BIG_ENDIAN_BITFIELD
1847 uint16_t nextRpi;
1848 uint16_t reqRpi;
1849 uint32_t rsvd2:8;
1850 uint32_t DID:24;
1851#else /* __LITTLE_ENDIAN_BITFIELD */
1852 uint16_t reqRpi;
1853 uint16_t nextRpi;
1854 uint32_t DID:24;
1855 uint32_t rsvd2:8;
1856#endif
1857
1858 union {
1859 struct ulp_bde sp;
1860 struct ulp_bde64 sp64;
1861 } un;
1862
1863} READ_RPI_VAR;
1864
1865/* Structure for MB Command READ_XRI (16) */
1866
1867typedef struct {
1868#ifdef __BIG_ENDIAN_BITFIELD
1869 uint16_t nextXri;
1870 uint16_t reqXri;
1871 uint16_t rsvd1;
1872 uint16_t rpi;
1873 uint32_t rsvd2:8;
1874 uint32_t DID:24;
1875 uint32_t rsvd3:8;
1876 uint32_t SID:24;
1877 uint32_t rsvd4;
1878 uint8_t seqId;
1879 uint8_t rsvd5;
1880 uint16_t seqCount;
1881 uint16_t oxId;
1882 uint16_t rxId;
1883 uint32_t rsvd6:30;
1884 uint32_t si:1;
1885 uint32_t exchOrig:1;
1886#else /* __LITTLE_ENDIAN_BITFIELD */
1887 uint16_t reqXri;
1888 uint16_t nextXri;
1889 uint16_t rpi;
1890 uint16_t rsvd1;
1891 uint32_t DID:24;
1892 uint32_t rsvd2:8;
1893 uint32_t SID:24;
1894 uint32_t rsvd3:8;
1895 uint32_t rsvd4;
1896 uint16_t seqCount;
1897 uint8_t rsvd5;
1898 uint8_t seqId;
1899 uint16_t rxId;
1900 uint16_t oxId;
1901 uint32_t exchOrig:1;
1902 uint32_t si:1;
1903 uint32_t rsvd6:30;
1904#endif
1905} READ_XRI_VAR;
1906
1907/* Structure for MB Command READ_REV (17) */
1908
1909typedef struct {
1910#ifdef __BIG_ENDIAN_BITFIELD
1911 uint32_t cv:1;
1912 uint32_t rr:1;
1913 uint32_t rsvd1:29;
1914 uint32_t rv:1;
1915#else /* __LITTLE_ENDIAN_BITFIELD */
1916 uint32_t rv:1;
1917 uint32_t rsvd1:29;
1918 uint32_t rr:1;
1919 uint32_t cv:1;
1920#endif
1921
1922 uint32_t biuRev;
1923 uint32_t smRev;
1924 union {
1925 uint32_t smFwRev;
1926 struct {
1927#ifdef __BIG_ENDIAN_BITFIELD
1928 uint8_t ProgType;
1929 uint8_t ProgId;
1930 uint16_t ProgVer:4;
1931 uint16_t ProgRev:4;
1932 uint16_t ProgFixLvl:2;
1933 uint16_t ProgDistType:2;
1934 uint16_t DistCnt:4;
1935#else /* __LITTLE_ENDIAN_BITFIELD */
1936 uint16_t DistCnt:4;
1937 uint16_t ProgDistType:2;
1938 uint16_t ProgFixLvl:2;
1939 uint16_t ProgRev:4;
1940 uint16_t ProgVer:4;
1941 uint8_t ProgId;
1942 uint8_t ProgType;
1943#endif
1944
1945 } b;
1946 } un;
1947 uint32_t endecRev;
1948#ifdef __BIG_ENDIAN_BITFIELD
1949 uint8_t feaLevelHigh;
1950 uint8_t feaLevelLow;
1951 uint8_t fcphHigh;
1952 uint8_t fcphLow;
1953#else /* __LITTLE_ENDIAN_BITFIELD */
1954 uint8_t fcphLow;
1955 uint8_t fcphHigh;
1956 uint8_t feaLevelLow;
1957 uint8_t feaLevelHigh;
1958#endif
1959
1960 uint32_t postKernRev;
1961 uint32_t opFwRev;
1962 uint8_t opFwName[16];
1963 uint32_t sli1FwRev;
1964 uint8_t sli1FwName[16];
1965 uint32_t sli2FwRev;
1966 uint8_t sli2FwName[16];
1967 uint32_t rsvd2;
1968 uint32_t RandomData[7];
1969} READ_REV_VAR;
1970
1971/* Structure for MB Command READ_LINK_STAT (18) */
1972
1973typedef struct {
1974 uint32_t rsvd1;
1975 uint32_t linkFailureCnt;
1976 uint32_t lossSyncCnt;
1977
1978 uint32_t lossSignalCnt;
1979 uint32_t primSeqErrCnt;
1980 uint32_t invalidXmitWord;
1981 uint32_t crcCnt;
1982 uint32_t primSeqTimeout;
1983 uint32_t elasticOverrun;
1984 uint32_t arbTimeout;
1985} READ_LNK_VAR;
1986
1987/* Structure for MB Command REG_LOGIN (19) */
1988/* Structure for MB Command REG_LOGIN64 (0x93) */
1989
1990typedef struct {
1991#ifdef __BIG_ENDIAN_BITFIELD
1992 uint16_t rsvd1;
1993 uint16_t rpi;
1994 uint32_t rsvd2:8;
1995 uint32_t did:24;
1996#else /* __LITTLE_ENDIAN_BITFIELD */
1997 uint16_t rpi;
1998 uint16_t rsvd1;
1999 uint32_t did:24;
2000 uint32_t rsvd2:8;
2001#endif
2002
2003 union {
2004 struct ulp_bde sp;
2005 struct ulp_bde64 sp64;
2006 } un;
2007
2008} REG_LOGIN_VAR;
2009
2010/* Word 30 contents for REG_LOGIN */
2011typedef union {
2012 struct {
2013#ifdef __BIG_ENDIAN_BITFIELD
2014 uint16_t rsvd1:12;
2015 uint16_t wd30_class:4;
2016 uint16_t xri;
2017#else /* __LITTLE_ENDIAN_BITFIELD */
2018 uint16_t xri;
2019 uint16_t wd30_class:4;
2020 uint16_t rsvd1:12;
2021#endif
2022 } f;
2023 uint32_t word;
2024} REG_WD30;
2025
2026/* Structure for MB Command UNREG_LOGIN (20) */
2027
2028typedef struct {
2029#ifdef __BIG_ENDIAN_BITFIELD
2030 uint16_t rsvd1;
2031 uint16_t rpi;
2032#else /* __LITTLE_ENDIAN_BITFIELD */
2033 uint16_t rpi;
2034 uint16_t rsvd1;
2035#endif
2036} UNREG_LOGIN_VAR;
2037
2038/* Structure for MB Command UNREG_D_ID (0x23) */
2039
2040typedef struct {
2041 uint32_t did;
2042} UNREG_D_ID_VAR;
2043
2044/* Structure for MB Command READ_LA (21) */
2045/* Structure for MB Command READ_LA64 (0x95) */
2046
2047typedef struct {
2048 uint32_t eventTag; /* Event tag */
2049#ifdef __BIG_ENDIAN_BITFIELD
2050 uint32_t rsvd1:22;
2051 uint32_t pb:1;
2052 uint32_t il:1;
2053 uint32_t attType:8;
2054#else /* __LITTLE_ENDIAN_BITFIELD */
2055 uint32_t attType:8;
2056 uint32_t il:1;
2057 uint32_t pb:1;
2058 uint32_t rsvd1:22;
2059#endif
2060
2061#define AT_RESERVED 0x00 /* Reserved - attType */
2062#define AT_LINK_UP 0x01 /* Link is up */
2063#define AT_LINK_DOWN 0x02 /* Link is down */
2064
2065#ifdef __BIG_ENDIAN_BITFIELD
2066 uint8_t granted_AL_PA;
2067 uint8_t lipAlPs;
2068 uint8_t lipType;
2069 uint8_t topology;
2070#else /* __LITTLE_ENDIAN_BITFIELD */
2071 uint8_t topology;
2072 uint8_t lipType;
2073 uint8_t lipAlPs;
2074 uint8_t granted_AL_PA;
2075#endif
2076
2077#define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2078#define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2079
2080 union {
2081 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer
2082 to */
2083 /* store the LILP AL_PA position map into */
2084 struct ulp_bde64 lilpBde64;
2085 } un;
2086
2087#ifdef __BIG_ENDIAN_BITFIELD
2088 uint32_t Dlu:1;
2089 uint32_t Dtf:1;
2090 uint32_t Drsvd2:14;
2091 uint32_t DlnkSpeed:8;
2092 uint32_t DnlPort:4;
2093 uint32_t Dtx:2;
2094 uint32_t Drx:2;
2095#else /* __LITTLE_ENDIAN_BITFIELD */
2096 uint32_t Drx:2;
2097 uint32_t Dtx:2;
2098 uint32_t DnlPort:4;
2099 uint32_t DlnkSpeed:8;
2100 uint32_t Drsvd2:14;
2101 uint32_t Dtf:1;
2102 uint32_t Dlu:1;
2103#endif
2104
2105#ifdef __BIG_ENDIAN_BITFIELD
2106 uint32_t Ulu:1;
2107 uint32_t Utf:1;
2108 uint32_t Ursvd2:14;
2109 uint32_t UlnkSpeed:8;
2110 uint32_t UnlPort:4;
2111 uint32_t Utx:2;
2112 uint32_t Urx:2;
2113#else /* __LITTLE_ENDIAN_BITFIELD */
2114 uint32_t Urx:2;
2115 uint32_t Utx:2;
2116 uint32_t UnlPort:4;
2117 uint32_t UlnkSpeed:8;
2118 uint32_t Ursvd2:14;
2119 uint32_t Utf:1;
2120 uint32_t Ulu:1;
2121#endif
2122
2123#define LA_UNKNW_LINK 0x0 /* lnkSpeed */
2124#define LA_1GHZ_LINK 0x04 /* lnkSpeed */
2125#define LA_2GHZ_LINK 0x08 /* lnkSpeed */
2126#define LA_4GHZ_LINK 0x10 /* lnkSpeed */
2127#define LA_8GHZ_LINK 0x20 /* lnkSpeed */
2128#define LA_10GHZ_LINK 0x40 /* lnkSpeed */
2129
2130} READ_LA_VAR;
2131
2132/* Structure for MB Command CLEAR_LA (22) */
2133
2134typedef struct {
2135 uint32_t eventTag; /* Event tag */
2136 uint32_t rsvd1;
2137} CLEAR_LA_VAR;
2138
2139/* Structure for MB Command DUMP */
2140
2141typedef struct {
2142#ifdef __BIG_ENDIAN_BITFIELD
2143 uint32_t rsvd:25;
2144 uint32_t ra:1;
2145 uint32_t co:1;
2146 uint32_t cv:1;
2147 uint32_t type:4;
2148 uint32_t entry_index:16;
2149 uint32_t region_id:16;
2150#else /* __LITTLE_ENDIAN_BITFIELD */
2151 uint32_t type:4;
2152 uint32_t cv:1;
2153 uint32_t co:1;
2154 uint32_t ra:1;
2155 uint32_t rsvd:25;
2156 uint32_t region_id:16;
2157 uint32_t entry_index:16;
2158#endif
2159
2160 uint32_t rsvd1;
2161 uint32_t word_cnt;
2162 uint32_t resp_offset;
2163} DUMP_VAR;
2164
2165#define DMP_MEM_REG 0x1
2166#define DMP_NV_PARAMS 0x2
2167
2168#define DMP_REGION_VPD 0xe
2169#define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2170#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2171#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2172
2173/* Structure for MB Command CONFIG_PORT (0x88) */
2174
2175typedef struct {
2176 uint32_t pcbLen;
2177 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2178 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
2179 uint32_t hbainit[5];
2180} CONFIG_PORT_VAR;
2181
2182/* SLI-2 Port Control Block */
2183
2184/* SLIM POINTER */
2185#define SLIMOFF 0x30 /* WORD */
2186
2187typedef struct _SLI2_RDSC {
2188 uint32_t cmdEntries;
2189 uint32_t cmdAddrLow;
2190 uint32_t cmdAddrHigh;
2191
2192 uint32_t rspEntries;
2193 uint32_t rspAddrLow;
2194 uint32_t rspAddrHigh;
2195} SLI2_RDSC;
2196
2197typedef struct _PCB {
2198#ifdef __BIG_ENDIAN_BITFIELD
2199 uint32_t type:8;
2200#define TYPE_NATIVE_SLI2 0x01;
2201 uint32_t feature:8;
2202#define FEATURE_INITIAL_SLI2 0x01;
2203 uint32_t rsvd:12;
2204 uint32_t maxRing:4;
2205#else /* __LITTLE_ENDIAN_BITFIELD */
2206 uint32_t maxRing:4;
2207 uint32_t rsvd:12;
2208 uint32_t feature:8;
2209#define FEATURE_INITIAL_SLI2 0x01;
2210 uint32_t type:8;
2211#define TYPE_NATIVE_SLI2 0x01;
2212#endif
2213
2214 uint32_t mailBoxSize;
2215 uint32_t mbAddrLow;
2216 uint32_t mbAddrHigh;
2217
2218 uint32_t hgpAddrLow;
2219 uint32_t hgpAddrHigh;
2220
2221 uint32_t pgpAddrLow;
2222 uint32_t pgpAddrHigh;
2223 SLI2_RDSC rdsc[MAX_RINGS];
2224} PCB_t;
2225
2226/* NEW_FEATURE */
2227typedef struct {
2228#ifdef __BIG_ENDIAN_BITFIELD
2229 uint32_t rsvd0:27;
2230 uint32_t discardFarp:1;
2231 uint32_t IPEnable:1;
2232 uint32_t nodeName:1;
2233 uint32_t portName:1;
2234 uint32_t filterEnable:1;
2235#else /* __LITTLE_ENDIAN_BITFIELD */
2236 uint32_t filterEnable:1;
2237 uint32_t portName:1;
2238 uint32_t nodeName:1;
2239 uint32_t IPEnable:1;
2240 uint32_t discardFarp:1;
2241 uint32_t rsvd:27;
2242#endif
2243
2244 uint8_t portname[8]; /* Used to be struct lpfc_name */
2245 uint8_t nodename[8];
2246 uint32_t rsvd1;
2247 uint32_t rsvd2;
2248 uint32_t rsvd3;
2249 uint32_t IPAddress;
2250} CONFIG_FARP_VAR;
2251
2252/* Union of all Mailbox Command types */
2253#define MAILBOX_CMD_WSIZE 32
2254#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2255
2256typedef union {
2257 uint32_t varWords[MAILBOX_CMD_WSIZE - 1];
2258 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2259 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2260 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
2261 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2262 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
2263 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
2264 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2265 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
2266 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2267 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2268 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2269 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2270 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2271 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
2272 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2273 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2274 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2275 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
2276 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2277 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
2278 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
2279 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
2280 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2281 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2282 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) NEW_FEATURE */
2283 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
2284} MAILVARIANTS;
2285
2286/*
2287 * SLI-2 specific structures
2288 */
2289
4cc2da1d
JSEC		 2290struct lpfc_hgp {
2291 __le32 cmdPutInx;
2292 __le32 rspGetInx;
2293};
dea3101e 2294
4cc2da1d
JSEC		 2295struct lpfc_pgp {
2296 __le32 cmdGetInx;
2297 __le32 rspPutInx;
2298};
dea3101e
JB		 2299
2300typedef struct _SLI2_DESC {
4cc2da1d 2301 struct lpfc_hgp host[MAX_RINGS];
dea3101e 2302 uint32_t unused1[16];
4cc2da1d 2303 struct lpfc_pgp port[MAX_RINGS];
dea3101e
JB		 2304} SLI2_DESC;
2305
2306typedef union {
2307 SLI2_DESC s2;
2308} SLI_VAR;
2309
2310typedef struct {
2311#ifdef __BIG_ENDIAN_BITFIELD
2312 uint16_t mbxStatus;
2313 uint8_t mbxCommand;
2314 uint8_t mbxReserved:6;
2315 uint8_t mbxHc:1;
2316 uint8_t mbxOwner:1; /* Low order bit first word */
2317#else /* __LITTLE_ENDIAN_BITFIELD */
2318 uint8_t mbxOwner:1; /* Low order bit first word */
2319 uint8_t mbxHc:1;
2320 uint8_t mbxReserved:6;
2321 uint8_t mbxCommand;
2322 uint16_t mbxStatus;
2323#endif
2324
2325 MAILVARIANTS un;
2326 SLI_VAR us;
2327} MAILBOX_t;
2328
2329/*
2330 * Begin Structure Definitions for IOCB Commands
2331 */
2332
2333typedef struct {
2334#ifdef __BIG_ENDIAN_BITFIELD
2335 uint8_t statAction;
2336 uint8_t statRsn;
2337 uint8_t statBaExp;
2338 uint8_t statLocalError;
2339#else /* __LITTLE_ENDIAN_BITFIELD */
2340 uint8_t statLocalError;
2341 uint8_t statBaExp;
2342 uint8_t statRsn;
2343 uint8_t statAction;
2344#endif
2345 /* statRsn P/F_RJT reason codes */
2346#define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
2347#define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
2348#define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
2349#define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
2350#define RJT_UNSUP_CLASS 0x05 /* Class not supported */
2351#define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
2352#define RJT_UNSUP_TYPE 0x07 /* Type not supported */
2353#define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
2354#define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
2355#define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
2356#define RJT_BAD_OXID 0x0B /* OX_ID invalid */
2357#define RJT_BAD_RXID 0x0C /* RX_ID invalid */
2358#define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
2359#define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
2360#define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
2361#define RJT_BAD_PARM 0x10 /* Param. field invalid */
2362#define RJT_XCHG_ERR 0x11 /* Exchange error */
2363#define RJT_PROT_ERR 0x12 /* Protocol error */
2364#define RJT_BAD_LENGTH 0x13 /* Invalid Length */
2365#define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
2366#define RJT_LOGIN_REQUIRED 0x16 /* Login required */
2367#define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
2368#define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
2369#define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
2370#define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
2371#define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
2372
2373#define IOERR_SUCCESS 0x00 /* statLocalError */
2374#define IOERR_MISSING_CONTINUE 0x01
2375#define IOERR_SEQUENCE_TIMEOUT 0x02
2376#define IOERR_INTERNAL_ERROR 0x03
2377#define IOERR_INVALID_RPI 0x04
2378#define IOERR_NO_XRI 0x05
2379#define IOERR_ILLEGAL_COMMAND 0x06
2380#define IOERR_XCHG_DROPPED 0x07
2381#define IOERR_ILLEGAL_FIELD 0x08
2382#define IOERR_BAD_CONTINUE 0x09
2383#define IOERR_TOO_MANY_BUFFERS 0x0A
2384#define IOERR_RCV_BUFFER_WAITING 0x0B
2385#define IOERR_NO_CONNECTION 0x0C
2386#define IOERR_TX_DMA_FAILED 0x0D
2387#define IOERR_RX_DMA_FAILED 0x0E
2388#define IOERR_ILLEGAL_FRAME 0x0F
2389#define IOERR_EXTRA_DATA 0x10
2390#define IOERR_NO_RESOURCES 0x11
2391#define IOERR_RESERVED 0x12
2392#define IOERR_ILLEGAL_LENGTH 0x13
2393#define IOERR_UNSUPPORTED_FEATURE 0x14
2394#define IOERR_ABORT_IN_PROGRESS 0x15
2395#define IOERR_ABORT_REQUESTED 0x16
2396#define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
2397#define IOERR_LOOP_OPEN_FAILURE 0x18
2398#define IOERR_RING_RESET 0x19
2399#define IOERR_LINK_DOWN 0x1A
2400#define IOERR_CORRUPTED_DATA 0x1B
2401#define IOERR_CORRUPTED_RPI 0x1C
2402#define IOERR_OUT_OF_ORDER_DATA 0x1D
2403#define IOERR_OUT_OF_ORDER_ACK 0x1E
2404#define IOERR_DUP_FRAME 0x1F
2405#define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
2406#define IOERR_BAD_HOST_ADDRESS 0x21
2407#define IOERR_RCV_HDRBUF_WAITING 0x22
2408#define IOERR_MISSING_HDR_BUFFER 0x23
2409#define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
2410#define IOERR_ABORTMULT_REQUESTED 0x25
2411#define IOERR_BUFFER_SHORTAGE 0x28
2412#define IOERR_DEFAULT 0x29
2413#define IOERR_CNT 0x2A
2414
2415#define IOERR_DRVR_MASK 0x100
2416#define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
2417#define IOERR_SLI_BRESET 0x102
2418#define IOERR_SLI_ABORTED 0x103
2419} PARM_ERR;
2420
2421typedef union {
2422 struct {
2423#ifdef __BIG_ENDIAN_BITFIELD
2424 uint8_t Rctl; /* R_CTL field */
2425 uint8_t Type; /* TYPE field */
2426 uint8_t Dfctl; /* DF_CTL field */
2427 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2428#else /* __LITTLE_ENDIAN_BITFIELD */
2429 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2430 uint8_t Dfctl; /* DF_CTL field */
2431 uint8_t Type; /* TYPE field */
2432 uint8_t Rctl; /* R_CTL field */
2433#endif
2434
2435#define BC 0x02 /* Broadcast Received - Fctl */
2436#define SI 0x04 /* Sequence Initiative */
2437#define LA 0x08 /* Ignore Link Attention state */
2438#define LS 0x80 /* Last Sequence */
2439 } hcsw;
2440 uint32_t reserved;
2441} WORD5;
2442
2443/* IOCB Command template for a generic response */
2444typedef struct {
2445 uint32_t reserved[4];
2446 PARM_ERR perr;
2447} GENERIC_RSP;
2448
2449/* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
2450typedef struct {
2451 struct ulp_bde xrsqbde[2];
2452 uint32_t xrsqRo; /* Starting Relative Offset */
2453 WORD5 w5; /* Header control/status word */
2454} XR_SEQ_FIELDS;
2455
2456/* IOCB Command template for ELS_REQUEST */
2457typedef struct {
2458 struct ulp_bde elsReq;
2459 struct ulp_bde elsRsp;
2460
2461#ifdef __BIG_ENDIAN_BITFIELD
2462 uint32_t word4Rsvd:7;
2463 uint32_t fl:1;
2464 uint32_t myID:24;
2465 uint32_t word5Rsvd:8;
2466 uint32_t remoteID:24;
2467#else /* __LITTLE_ENDIAN_BITFIELD */
2468 uint32_t myID:24;
2469 uint32_t fl:1;
2470 uint32_t word4Rsvd:7;
2471 uint32_t remoteID:24;
2472 uint32_t word5Rsvd:8;
2473#endif
2474} ELS_REQUEST;
2475
2476/* IOCB Command template for RCV_ELS_REQ */
2477typedef struct {
2478 struct ulp_bde elsReq[2];
2479 uint32_t parmRo;
2480
2481#ifdef __BIG_ENDIAN_BITFIELD
2482 uint32_t word5Rsvd:8;
2483 uint32_t remoteID:24;
2484#else /* __LITTLE_ENDIAN_BITFIELD */
2485 uint32_t remoteID:24;
2486 uint32_t word5Rsvd:8;
2487#endif
2488} RCV_ELS_REQ;
2489
2490/* IOCB Command template for ABORT / CLOSE_XRI */
2491typedef struct {
2492 uint32_t rsvd[3];
2493 uint32_t abortType;
2494#define ABORT_TYPE_ABTX 0x00000000
2495#define ABORT_TYPE_ABTS 0x00000001
2496 uint32_t parm;
2497#ifdef __BIG_ENDIAN_BITFIELD
2498 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2499 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2500#else /* __LITTLE_ENDIAN_BITFIELD */
2501 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2502 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2503#endif
2504} AC_XRI;
2505
2506/* IOCB Command template for ABORT_MXRI64 */
2507typedef struct {
2508 uint32_t rsvd[3];
2509 uint32_t abortType;
2510 uint32_t parm;
2511 uint32_t iotag32;
2512} A_MXRI64;
2513
2514/* IOCB Command template for GET_RPI */
2515typedef struct {
2516 uint32_t rsvd[4];
2517 uint32_t parmRo;
2518#ifdef __BIG_ENDIAN_BITFIELD
2519 uint32_t word5Rsvd:8;
2520 uint32_t remoteID:24;
2521#else /* __LITTLE_ENDIAN_BITFIELD */
2522 uint32_t remoteID:24;
2523 uint32_t word5Rsvd:8;
2524#endif
2525} GET_RPI;
2526
2527/* IOCB Command template for all FCP Initiator commands */
2528typedef struct {
2529 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
2530 struct ulp_bde fcpi_rsp; /* Rcv buffer */
2531 uint32_t fcpi_parm;
2532 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
2533} FCPI_FIELDS;
2534
2535/* IOCB Command template for all FCP Target commands */
2536typedef struct {
2537 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
2538 uint32_t fcpt_Offset;
2539 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2540} FCPT_FIELDS;
2541
2542/* SLI-2 IOCB structure definitions */
2543
2544/* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
2545typedef struct {
2546 ULP_BDL bdl;
2547 uint32_t xrsqRo; /* Starting Relative Offset */
2548 WORD5 w5; /* Header control/status word */
2549} XMT_SEQ_FIELDS64;
2550
2551/* IOCB Command template for 64 bit RCV_SEQUENCE64 */
2552typedef struct {
2553 struct ulp_bde64 rcvBde;
2554 uint32_t rsvd1;
2555 uint32_t xrsqRo; /* Starting Relative Offset */
2556 WORD5 w5; /* Header control/status word */
2557} RCV_SEQ_FIELDS64;
2558
2559/* IOCB Command template for ELS_REQUEST64 */
2560typedef struct {
2561 ULP_BDL bdl;
2562#ifdef __BIG_ENDIAN_BITFIELD
2563 uint32_t word4Rsvd:7;
2564 uint32_t fl:1;
2565 uint32_t myID:24;
2566 uint32_t word5Rsvd:8;
2567 uint32_t remoteID:24;
2568#else /* __LITTLE_ENDIAN_BITFIELD */
2569 uint32_t myID:24;
2570 uint32_t fl:1;
2571 uint32_t word4Rsvd:7;
2572 uint32_t remoteID:24;
2573 uint32_t word5Rsvd:8;
2574#endif
2575} ELS_REQUEST64;
2576
2577/* IOCB Command template for GEN_REQUEST64 */
2578typedef struct {
2579 ULP_BDL bdl;
2580 uint32_t xrsqRo; /* Starting Relative Offset */
2581 WORD5 w5; /* Header control/status word */
2582} GEN_REQUEST64;
2583
2584/* IOCB Command template for RCV_ELS_REQ64 */
2585typedef struct {
2586 struct ulp_bde64 elsReq;
2587 uint32_t rcvd1;
2588 uint32_t parmRo;
2589
2590#ifdef __BIG_ENDIAN_BITFIELD
2591 uint32_t word5Rsvd:8;
2592 uint32_t remoteID:24;
2593#else /* __LITTLE_ENDIAN_BITFIELD */
2594 uint32_t remoteID:24;
2595 uint32_t word5Rsvd:8;
2596#endif
2597} RCV_ELS_REQ64;
2598
2599/* IOCB Command template for all 64 bit FCP Initiator commands */
2600typedef struct {
2601 ULP_BDL bdl;
2602 uint32_t fcpi_parm;
2603 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
2604} FCPI_FIELDS64;
2605
2606/* IOCB Command template for all 64 bit FCP Target commands */
2607typedef struct {
2608 ULP_BDL bdl;
2609 uint32_t fcpt_Offset;
2610 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2611} FCPT_FIELDS64;
2612
2613typedef struct _IOCB { /* IOCB structure */
2614 union {
2615 GENERIC_RSP grsp; /* Generic response */
2616 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
2617 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
2618 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
2619 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
2620 A_MXRI64 amxri; /* abort multiple xri command overlay */
2621 GET_RPI getrpi; /* GET_RPI template */
2622 FCPI_FIELDS fcpi; /* FCP Initiator template */
2623 FCPT_FIELDS fcpt; /* FCP target template */
2624
2625 /* SLI-2 structures */
2626
2627 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
2628 bde_64s */
2629 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
2630 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
2631 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
2632 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
2633 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
2634 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
2635
2636 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
2637 } un;
2638 union {
2639 struct {
2640#ifdef __BIG_ENDIAN_BITFIELD
2641 uint16_t ulpContext; /* High order bits word 6 */
2642 uint16_t ulpIoTag; /* Low order bits word 6 */
2643#else /* __LITTLE_ENDIAN_BITFIELD */
2644 uint16_t ulpIoTag; /* Low order bits word 6 */
2645 uint16_t ulpContext; /* High order bits word 6 */
2646#endif
2647 } t1;
2648 struct {
2649#ifdef __BIG_ENDIAN_BITFIELD
2650 uint16_t ulpContext; /* High order bits word 6 */
2651 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
2652 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
2653#else /* __LITTLE_ENDIAN_BITFIELD */
2654 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
2655 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
2656 uint16_t ulpContext; /* High order bits word 6 */
2657#endif
2658 } t2;
2659 } un1;
2660#define ulpContext un1.t1.ulpContext
2661#define ulpIoTag un1.t1.ulpIoTag
2662#define ulpIoTag0 un1.t2.ulpIoTag0
2663
2664#ifdef __BIG_ENDIAN_BITFIELD
2665 uint32_t ulpTimeout:8;
2666 uint32_t ulpXS:1;
2667 uint32_t ulpFCP2Rcvy:1;
2668 uint32_t ulpPU:2;
2669 uint32_t ulpIr:1;
2670 uint32_t ulpClass:3;
2671 uint32_t ulpCommand:8;
2672 uint32_t ulpStatus:4;
2673 uint32_t ulpBdeCount:2;
2674 uint32_t ulpLe:1;
2675 uint32_t ulpOwner:1; /* Low order bit word 7 */
2676#else /* __LITTLE_ENDIAN_BITFIELD */
2677 uint32_t ulpOwner:1; /* Low order bit word 7 */
2678 uint32_t ulpLe:1;
2679 uint32_t ulpBdeCount:2;
2680 uint32_t ulpStatus:4;
2681 uint32_t ulpCommand:8;
2682 uint32_t ulpClass:3;
2683 uint32_t ulpIr:1;
2684 uint32_t ulpPU:2;
2685 uint32_t ulpFCP2Rcvy:1;
2686 uint32_t ulpXS:1;
2687 uint32_t ulpTimeout:8;
2688#endif
2689
2690#define PARM_UNUSED 0 /* PU field (Word 4) not used */
2691#define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
2692#define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
2693#define CLASS1 0 /* Class 1 */
2694#define CLASS2 1 /* Class 2 */
2695#define CLASS3 2 /* Class 3 */
2696#define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
2697
2698#define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
2699#define IOSTAT_FCP_RSP_ERROR 0x1
2700#define IOSTAT_REMOTE_STOP 0x2
2701#define IOSTAT_LOCAL_REJECT 0x3
2702#define IOSTAT_NPORT_RJT 0x4
2703#define IOSTAT_FABRIC_RJT 0x5
2704#define IOSTAT_NPORT_BSY 0x6
2705#define IOSTAT_FABRIC_BSY 0x7
2706#define IOSTAT_INTERMED_RSP 0x8
2707#define IOSTAT_LS_RJT 0x9
2708#define IOSTAT_BA_RJT 0xA
2709#define IOSTAT_RSVD1 0xB
2710#define IOSTAT_RSVD2 0xC
2711#define IOSTAT_RSVD3 0xD
2712#define IOSTAT_RSVD4 0xE
2713#define IOSTAT_RSVD5 0xF
2714#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
2715#define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
2716#define IOSTAT_CNT 0x11
2717
2718} IOCB_t;
2719
2720
2721#define SLI1_SLIM_SIZE (4 * 1024)
2722
2723/* Up to 498 IOCBs will fit into 16k
2724 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
2725 */
2726#define SLI2_SLIM_SIZE (16 * 1024)
2727
2728/* Maximum IOCBs that will fit in SLI2 slim */
2729#define MAX_SLI2_IOCB 498
2730
2731struct lpfc_sli2_slim {
2732 MAILBOX_t mbx;
2733 PCB_t pcb;
2734 IOCB_t IOCBs[MAX_SLI2_IOCB];
2735};
2736
2737/*******************************************************************
2738This macro check PCI device to allow special handling for LC HBAs.
2739
2740Parameters:
2741device : struct pci_dev 's device field
2742
2743return 1 => TRUE
2744 0 => FALSE
2745 *******************************************************************/
2746static inline int
2747lpfc_is_LC_HBA(unsigned short device)
2748{
2749 if ((device == PCI_DEVICE_ID_TFLY) ||
2750 (device == PCI_DEVICE_ID_PFLY) ||
2751 (device == PCI_DEVICE_ID_LP101) ||
2752 (device == PCI_DEVICE_ID_BMID) ||
2753 (device == PCI_DEVICE_ID_BSMB) ||
2754 (device == PCI_DEVICE_ID_ZMID) ||
2755 (device == PCI_DEVICE_ID_ZSMB) ||
2756 (device == PCI_DEVICE_ID_RFLY))
2757 return 1;
2758 else
2759 return 0;
2760}
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