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[libata ahci] error handling fixes
[net-next-2.6.git] / drivers / scsi / libata-core.c
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1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
35#include <linux/config.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/list.h>
41#include <linux/mm.h>
42#include <linux/highmem.h>
43#include <linux/spinlock.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/timer.h>
47#include <linux/interrupt.h>
48#include <linux/completion.h>
49#include <linux/suspend.h>
50#include <linux/workqueue.h>
67846b30 51#include <linux/jiffies.h>
378f058c 52#include <linux/scatterlist.h>
1da177e4 53#include <scsi/scsi.h>
1da177e4 54#include "scsi_priv.h"
193515d5 55#include <scsi/scsi_cmnd.h>
1da177e4
LT		 56#include <scsi/scsi_host.h>
57#include <linux/libata.h>
58#include <asm/io.h>
59#include <asm/semaphore.h>
60#include <asm/byteorder.h>
61
62#include "libata.h"
63
64static unsigned int ata_busy_sleep (struct ata_port *ap,
65 unsigned long tmout_pat,
66 unsigned long tmout);
59a10b17 67static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev);
8bf62ece 68static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev);
1da177e4
LT		 69static void ata_set_mode(struct ata_port *ap);
70static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev);
057ace5e 71static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift);
1da177e4 72static int fgb(u32 bitmap);
057ace5e 73static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 74 u8 *xfer_mode_out,
75 unsigned int *xfer_shift_out);
1da177e4
LT		 76static void __ata_qc_complete(struct ata_queued_cmd *qc);
77
78static unsigned int ata_unique_id = 1;
79static struct workqueue_struct *ata_wq;
80
1623c81e
JG		 81int atapi_enabled = 0;
82module_param(atapi_enabled, int, 0444);
83MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
84
1da177e4
LT		 85MODULE_AUTHOR("Jeff Garzik");
86MODULE_DESCRIPTION("Library module for ATA devices");
87MODULE_LICENSE("GPL");
88MODULE_VERSION(DRV_VERSION);
89
90/**
6f0ef4fa 91 * ata_tf_load_pio - send taskfile registers to host controller
1da177e4
LT		 92 * @ap: Port to which output is sent
93 * @tf: ATA taskfile register set
94 *
95 * Outputs ATA taskfile to standard ATA host controller.
96 *
97 * LOCKING:
98 * Inherited from caller.
99 */
100
057ace5e 101static void ata_tf_load_pio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 102{
103 struct ata_ioports *ioaddr = &ap->ioaddr;
104 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
105
106 if (tf->ctl != ap->last_ctl) {
107 outb(tf->ctl, ioaddr->ctl_addr);
108 ap->last_ctl = tf->ctl;
109 ata_wait_idle(ap);
110 }
111
112 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
113 outb(tf->hob_feature, ioaddr->feature_addr);
114 outb(tf->hob_nsect, ioaddr->nsect_addr);
115 outb(tf->hob_lbal, ioaddr->lbal_addr);
116 outb(tf->hob_lbam, ioaddr->lbam_addr);
117 outb(tf->hob_lbah, ioaddr->lbah_addr);
118 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
119 tf->hob_feature,
120 tf->hob_nsect,
121 tf->hob_lbal,
122 tf->hob_lbam,
123 tf->hob_lbah);
124 }
125
126 if (is_addr) {
127 outb(tf->feature, ioaddr->feature_addr);
128 outb(tf->nsect, ioaddr->nsect_addr);
129 outb(tf->lbal, ioaddr->lbal_addr);
130 outb(tf->lbam, ioaddr->lbam_addr);
131 outb(tf->lbah, ioaddr->lbah_addr);
132 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
133 tf->feature,
134 tf->nsect,
135 tf->lbal,
136 tf->lbam,
137 tf->lbah);
138 }
139
140 if (tf->flags & ATA_TFLAG_DEVICE) {
141 outb(tf->device, ioaddr->device_addr);
142 VPRINTK("device 0x%X\n", tf->device);
143 }
144
145 ata_wait_idle(ap);
146}
147
148/**
149 * ata_tf_load_mmio - send taskfile registers to host controller
150 * @ap: Port to which output is sent
151 * @tf: ATA taskfile register set
152 *
153 * Outputs ATA taskfile to standard ATA host controller using MMIO.
154 *
155 * LOCKING:
156 * Inherited from caller.
157 */
158
057ace5e 159static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 160{
161 struct ata_ioports *ioaddr = &ap->ioaddr;
162 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
163
164 if (tf->ctl != ap->last_ctl) {
165 writeb(tf->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
166 ap->last_ctl = tf->ctl;
167 ata_wait_idle(ap);
168 }
169
170 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
171 writeb(tf->hob_feature, (void __iomem *) ioaddr->feature_addr);
172 writeb(tf->hob_nsect, (void __iomem *) ioaddr->nsect_addr);
173 writeb(tf->hob_lbal, (void __iomem *) ioaddr->lbal_addr);
174 writeb(tf->hob_lbam, (void __iomem *) ioaddr->lbam_addr);
175 writeb(tf->hob_lbah, (void __iomem *) ioaddr->lbah_addr);
176 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
177 tf->hob_feature,
178 tf->hob_nsect,
179 tf->hob_lbal,
180 tf->hob_lbam,
181 tf->hob_lbah);
182 }
183
184 if (is_addr) {
185 writeb(tf->feature, (void __iomem *) ioaddr->feature_addr);
186 writeb(tf->nsect, (void __iomem *) ioaddr->nsect_addr);
187 writeb(tf->lbal, (void __iomem *) ioaddr->lbal_addr);
188 writeb(tf->lbam, (void __iomem *) ioaddr->lbam_addr);
189 writeb(tf->lbah, (void __iomem *) ioaddr->lbah_addr);
190 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
191 tf->feature,
192 tf->nsect,
193 tf->lbal,
194 tf->lbam,
195 tf->lbah);
196 }
197
198 if (tf->flags & ATA_TFLAG_DEVICE) {
199 writeb(tf->device, (void __iomem *) ioaddr->device_addr);
200 VPRINTK("device 0x%X\n", tf->device);
201 }
202
203 ata_wait_idle(ap);
204}
205
0baab86b
EF		 206
207/**
208 * ata_tf_load - send taskfile registers to host controller
209 * @ap: Port to which output is sent
210 * @tf: ATA taskfile register set
211 *
212 * Outputs ATA taskfile to standard ATA host controller using MMIO
213 * or PIO as indicated by the ATA_FLAG_MMIO flag.
214 * Writes the control, feature, nsect, lbal, lbam, and lbah registers.
215 * Optionally (ATA_TFLAG_LBA48) writes hob_feature, hob_nsect,
216 * hob_lbal, hob_lbam, and hob_lbah.
217 *
218 * This function waits for idle (!BUSY and !DRQ) after writing
219 * registers. If the control register has a new value, this
220 * function also waits for idle after writing control and before
221 * writing the remaining registers.
222 *
223 * May be used as the tf_load() entry in ata_port_operations.
224 *
225 * LOCKING:
226 * Inherited from caller.
227 */
057ace5e 228void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 229{
230 if (ap->flags & ATA_FLAG_MMIO)
231 ata_tf_load_mmio(ap, tf);
232 else
233 ata_tf_load_pio(ap, tf);
234}
235
236/**
0baab86b 237 * ata_exec_command_pio - issue ATA command to host controller
1da177e4
LT		 238 * @ap: port to which command is being issued
239 * @tf: ATA taskfile register set
240 *
0baab86b 241 * Issues PIO write to ATA command register, with proper
1da177e4
LT		 242 * synchronization with interrupt handler / other threads.
243 *
244 * LOCKING:
245 * spin_lock_irqsave(host_set lock)
246 */
247
057ace5e 248static void ata_exec_command_pio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 249{
250 DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
251
252 outb(tf->command, ap->ioaddr.command_addr);
253 ata_pause(ap);
254}
255
256
257/**
258 * ata_exec_command_mmio - issue ATA command to host controller
259 * @ap: port to which command is being issued
260 * @tf: ATA taskfile register set
261 *
262 * Issues MMIO write to ATA command register, with proper
263 * synchronization with interrupt handler / other threads.
264 *
265 * LOCKING:
266 * spin_lock_irqsave(host_set lock)
267 */
268
057ace5e 269static void ata_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 270{
271 DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
272
273 writeb(tf->command, (void __iomem *) ap->ioaddr.command_addr);
274 ata_pause(ap);
275}
276
0baab86b
EF		 277
278/**
279 * ata_exec_command - issue ATA command to host controller
280 * @ap: port to which command is being issued
281 * @tf: ATA taskfile register set
282 *
283 * Issues PIO/MMIO write to ATA command register, with proper
284 * synchronization with interrupt handler / other threads.
285 *
286 * LOCKING:
287 * spin_lock_irqsave(host_set lock)
288 */
057ace5e 289void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 290{
291 if (ap->flags & ATA_FLAG_MMIO)
292 ata_exec_command_mmio(ap, tf);
293 else
294 ata_exec_command_pio(ap, tf);
295}
296
1da177e4
LT		 297/**
298 * ata_tf_to_host - issue ATA taskfile to host controller
299 * @ap: port to which command is being issued
300 * @tf: ATA taskfile register set
301 *
302 * Issues ATA taskfile register set to ATA host controller,
303 * with proper synchronization with interrupt handler and
304 * other threads.
305 *
306 * LOCKING:
1da177e4
LT		 307 * spin_lock_irqsave(host_set lock)
308 */
309
e5338254
JG		 310static inline void ata_tf_to_host(struct ata_port *ap,
311 const struct ata_taskfile *tf)
1da177e4
LT		 312{
313 ap->ops->tf_load(ap, tf);
314 ap->ops->exec_command(ap, tf);
315}
316
317/**
0baab86b 318 * ata_tf_read_pio - input device's ATA taskfile shadow registers
1da177e4
LT		 319 * @ap: Port from which input is read
320 * @tf: ATA taskfile register set for storing input
321 *
322 * Reads ATA taskfile registers for currently-selected device
323 * into @tf.
324 *
325 * LOCKING:
326 * Inherited from caller.
327 */
328
329static void ata_tf_read_pio(struct ata_port *ap, struct ata_taskfile *tf)
330{
331 struct ata_ioports *ioaddr = &ap->ioaddr;
332
ac19bff2 333 tf->command = ata_check_status(ap);
0169e284 334 tf->feature = inb(ioaddr->error_addr);
1da177e4
LT		 335 tf->nsect = inb(ioaddr->nsect_addr);
336 tf->lbal = inb(ioaddr->lbal_addr);
337 tf->lbam = inb(ioaddr->lbam_addr);
338 tf->lbah = inb(ioaddr->lbah_addr);
339 tf->device = inb(ioaddr->device_addr);
340
341 if (tf->flags & ATA_TFLAG_LBA48) {
342 outb(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
343 tf->hob_feature = inb(ioaddr->error_addr);
344 tf->hob_nsect = inb(ioaddr->nsect_addr);
345 tf->hob_lbal = inb(ioaddr->lbal_addr);
346 tf->hob_lbam = inb(ioaddr->lbam_addr);
347 tf->hob_lbah = inb(ioaddr->lbah_addr);
348 }
349}
350
351/**
352 * ata_tf_read_mmio - input device's ATA taskfile shadow registers
353 * @ap: Port from which input is read
354 * @tf: ATA taskfile register set for storing input
355 *
356 * Reads ATA taskfile registers for currently-selected device
357 * into @tf via MMIO.
358 *
359 * LOCKING:
360 * Inherited from caller.
361 */
362
363static void ata_tf_read_mmio(struct ata_port *ap, struct ata_taskfile *tf)
364{
365 struct ata_ioports *ioaddr = &ap->ioaddr;
366
ac19bff2 367 tf->command = ata_check_status(ap);
0169e284 368 tf->feature = readb((void __iomem *)ioaddr->error_addr);
1da177e4
LT		 369 tf->nsect = readb((void __iomem *)ioaddr->nsect_addr);
370 tf->lbal = readb((void __iomem *)ioaddr->lbal_addr);
371 tf->lbam = readb((void __iomem *)ioaddr->lbam_addr);
372 tf->lbah = readb((void __iomem *)ioaddr->lbah_addr);
373 tf->device = readb((void __iomem *)ioaddr->device_addr);
374
375 if (tf->flags & ATA_TFLAG_LBA48) {
376 writeb(tf->ctl | ATA_HOB, (void __iomem *) ap->ioaddr.ctl_addr);
377 tf->hob_feature = readb((void __iomem *)ioaddr->error_addr);
378 tf->hob_nsect = readb((void __iomem *)ioaddr->nsect_addr);
379 tf->hob_lbal = readb((void __iomem *)ioaddr->lbal_addr);
380 tf->hob_lbam = readb((void __iomem *)ioaddr->lbam_addr);
381 tf->hob_lbah = readb((void __iomem *)ioaddr->lbah_addr);
382 }
383}
384
0baab86b
EF		 385
386/**
387 * ata_tf_read - input device's ATA taskfile shadow registers
388 * @ap: Port from which input is read
389 * @tf: ATA taskfile register set for storing input
390 *
391 * Reads ATA taskfile registers for currently-selected device
392 * into @tf.
393 *
394 * Reads nsect, lbal, lbam, lbah, and device. If ATA_TFLAG_LBA48
395 * is set, also reads the hob registers.
396 *
397 * May be used as the tf_read() entry in ata_port_operations.
398 *
399 * LOCKING:
400 * Inherited from caller.
401 */
1da177e4
LT		 402void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
403{
404 if (ap->flags & ATA_FLAG_MMIO)
405 ata_tf_read_mmio(ap, tf);
406 else
407 ata_tf_read_pio(ap, tf);
408}
409
410/**
411 * ata_check_status_pio - Read device status reg & clear interrupt
412 * @ap: port where the device is
413 *
414 * Reads ATA taskfile status register for currently-selected device
0baab86b 415 * and return its value. This also clears pending interrupts
1da177e4
LT		 416 * from this device
417 *
418 * LOCKING:
419 * Inherited from caller.
420 */
421static u8 ata_check_status_pio(struct ata_port *ap)
422{
423 return inb(ap->ioaddr.status_addr);
424}
425
426/**
427 * ata_check_status_mmio - Read device status reg & clear interrupt
428 * @ap: port where the device is
429 *
430 * Reads ATA taskfile status register for currently-selected device
0baab86b 431 * via MMIO and return its value. This also clears pending interrupts
1da177e4
LT		 432 * from this device
433 *
434 * LOCKING:
435 * Inherited from caller.
436 */
437static u8 ata_check_status_mmio(struct ata_port *ap)
438{
439 return readb((void __iomem *) ap->ioaddr.status_addr);
440}
441
0baab86b
EF		 442
443/**
444 * ata_check_status - Read device status reg & clear interrupt
445 * @ap: port where the device is
446 *
447 * Reads ATA taskfile status register for currently-selected device
448 * and return its value. This also clears pending interrupts
449 * from this device
450 *
451 * May be used as the check_status() entry in ata_port_operations.
452 *
453 * LOCKING:
454 * Inherited from caller.
455 */
1da177e4
LT		 456u8 ata_check_status(struct ata_port *ap)
457{
458 if (ap->flags & ATA_FLAG_MMIO)
459 return ata_check_status_mmio(ap);
460 return ata_check_status_pio(ap);
461}
462
0baab86b
EF		 463
464/**
465 * ata_altstatus - Read device alternate status reg
466 * @ap: port where the device is
467 *
468 * Reads ATA taskfile alternate status register for
469 * currently-selected device and return its value.
470 *
471 * Note: may NOT be used as the check_altstatus() entry in
472 * ata_port_operations.
473 *
474 * LOCKING:
475 * Inherited from caller.
476 */
1da177e4
LT		 477u8 ata_altstatus(struct ata_port *ap)
478{
479 if (ap->ops->check_altstatus)
480 return ap->ops->check_altstatus(ap);
481
482 if (ap->flags & ATA_FLAG_MMIO)
483 return readb((void __iomem *)ap->ioaddr.altstatus_addr);
484 return inb(ap->ioaddr.altstatus_addr);
485}
486
0baab86b 487
1da177e4
LT		 488/**
489 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
490 * @tf: Taskfile to convert
491 * @fis: Buffer into which data will output
492 * @pmp: Port multiplier port
493 *
494 * Converts a standard ATA taskfile to a Serial ATA
495 * FIS structure (Register - Host to Device).
496 *
497 * LOCKING:
498 * Inherited from caller.
499 */
500
057ace5e 501void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 502{
503 fis[0] = 0x27; /* Register - Host to Device FIS */
504 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
505 bit 7 indicates Command FIS */
506 fis[2] = tf->command;
507 fis[3] = tf->feature;
508
509 fis[4] = tf->lbal;
510 fis[5] = tf->lbam;
511 fis[6] = tf->lbah;
512 fis[7] = tf->device;
513
514 fis[8] = tf->hob_lbal;
515 fis[9] = tf->hob_lbam;
516 fis[10] = tf->hob_lbah;
517 fis[11] = tf->hob_feature;
518
519 fis[12] = tf->nsect;
520 fis[13] = tf->hob_nsect;
521 fis[14] = 0;
522 fis[15] = tf->ctl;
523
524 fis[16] = 0;
525 fis[17] = 0;
526 fis[18] = 0;
527 fis[19] = 0;
528}
529
530/**
531 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
532 * @fis: Buffer from which data will be input
533 * @tf: Taskfile to output
534 *
e12a1be6 535 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT		 536 *
537 * LOCKING:
538 * Inherited from caller.
539 */
540
057ace5e 541void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 542{
543 tf->command = fis[2]; /* status */
544 tf->feature = fis[3]; /* error */
545
546 tf->lbal = fis[4];
547 tf->lbam = fis[5];
548 tf->lbah = fis[6];
549 tf->device = fis[7];
550
551 tf->hob_lbal = fis[8];
552 tf->hob_lbam = fis[9];
553 tf->hob_lbah = fis[10];
554
555 tf->nsect = fis[12];
556 tf->hob_nsect = fis[13];
557}
558
8cbd6df1
AL		 559static const u8 ata_rw_cmds[] = {
560 /* pio multi */
561 ATA_CMD_READ_MULTI,
562 ATA_CMD_WRITE_MULTI,
563 ATA_CMD_READ_MULTI_EXT,
564 ATA_CMD_WRITE_MULTI_EXT,
565 /* pio */
566 ATA_CMD_PIO_READ,
567 ATA_CMD_PIO_WRITE,
568 ATA_CMD_PIO_READ_EXT,
569 ATA_CMD_PIO_WRITE_EXT,
570 /* dma */
571 ATA_CMD_READ,
572 ATA_CMD_WRITE,
573 ATA_CMD_READ_EXT,
574 ATA_CMD_WRITE_EXT
575};
1da177e4
LT		 576
577/**
8cbd6df1
AL		 578 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
579 * @qc: command to examine and configure
1da177e4 580 *
8cbd6df1
AL		 581 * Examine the device configuration and tf->flags to calculate
582 * the proper read/write commands and protocol to use.
1da177e4
LT		 583 *
584 * LOCKING:
585 * caller.
586 */
8cbd6df1 587void ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 588{
8cbd6df1
AL		 589 struct ata_taskfile *tf = &qc->tf;
590 struct ata_device *dev = qc->dev;
1da177e4 591
8cbd6df1
AL		 592 int index, lba48, write;
593
594 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
595 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 596
8cbd6df1
AL		 597 if (dev->flags & ATA_DFLAG_PIO) {
598 tf->protocol = ATA_PROT_PIO;
599 index = dev->multi_count ? 0 : 4;
600 } else {
601 tf->protocol = ATA_PROT_DMA;
602 index = 8;
603 }
1da177e4 604
8cbd6df1 605 tf->command = ata_rw_cmds[index + lba48 + write];
1da177e4
LT		 606}
607
608static const char * xfer_mode_str[] = {
609 "UDMA/16",
610 "UDMA/25",
611 "UDMA/33",
612 "UDMA/44",
613 "UDMA/66",
614 "UDMA/100",
615 "UDMA/133",
616 "UDMA7",
617 "MWDMA0",
618 "MWDMA1",
619 "MWDMA2",
620 "PIO0",
621 "PIO1",
622 "PIO2",
623 "PIO3",
624 "PIO4",
625};
626
627/**
628 * ata_udma_string - convert UDMA bit offset to string
629 * @mask: mask of bits supported; only highest bit counts.
630 *
631 * Determine string which represents the highest speed
632 * (highest bit in @udma_mask).
633 *
634 * LOCKING:
635 * None.
636 *
637 * RETURNS:
638 * Constant C string representing highest speed listed in
639 * @udma_mask, or the constant C string "<n/a>".
640 */
641
642static const char *ata_mode_string(unsigned int mask)
643{
644 int i;
645
646 for (i = 7; i >= 0; i--)
647 if (mask & (1 << i))
648 goto out;
649 for (i = ATA_SHIFT_MWDMA + 2; i >= ATA_SHIFT_MWDMA; i--)
650 if (mask & (1 << i))
651 goto out;
652 for (i = ATA_SHIFT_PIO + 4; i >= ATA_SHIFT_PIO; i--)
653 if (mask & (1 << i))
654 goto out;
655
656 return "<n/a>";
657
658out:
659 return xfer_mode_str[i];
660}
661
662/**
663 * ata_pio_devchk - PATA device presence detection
664 * @ap: ATA channel to examine
665 * @device: Device to examine (starting at zero)
666 *
667 * This technique was originally described in
668 * Hale Landis's ATADRVR (www.ata-atapi.com), and
669 * later found its way into the ATA/ATAPI spec.
670 *
671 * Write a pattern to the ATA shadow registers,
672 * and if a device is present, it will respond by
673 * correctly storing and echoing back the
674 * ATA shadow register contents.
675 *
676 * LOCKING:
677 * caller.
678 */
679
680static unsigned int ata_pio_devchk(struct ata_port *ap,
681 unsigned int device)
682{
683 struct ata_ioports *ioaddr = &ap->ioaddr;
684 u8 nsect, lbal;
685
686 ap->ops->dev_select(ap, device);
687
688 outb(0x55, ioaddr->nsect_addr);
689 outb(0xaa, ioaddr->lbal_addr);
690
691 outb(0xaa, ioaddr->nsect_addr);
692 outb(0x55, ioaddr->lbal_addr);
693
694 outb(0x55, ioaddr->nsect_addr);
695 outb(0xaa, ioaddr->lbal_addr);
696
697 nsect = inb(ioaddr->nsect_addr);
698 lbal = inb(ioaddr->lbal_addr);
699
700 if ((nsect == 0x55) && (lbal == 0xaa))
701 return 1; /* we found a device */
702
703 return 0; /* nothing found */
704}
705
706/**
707 * ata_mmio_devchk - PATA device presence detection
708 * @ap: ATA channel to examine
709 * @device: Device to examine (starting at zero)
710 *
711 * This technique was originally described in
712 * Hale Landis's ATADRVR (www.ata-atapi.com), and
713 * later found its way into the ATA/ATAPI spec.
714 *
715 * Write a pattern to the ATA shadow registers,
716 * and if a device is present, it will respond by
717 * correctly storing and echoing back the
718 * ATA shadow register contents.
719 *
720 * LOCKING:
721 * caller.
722 */
723
724static unsigned int ata_mmio_devchk(struct ata_port *ap,
725 unsigned int device)
726{
727 struct ata_ioports *ioaddr = &ap->ioaddr;
728 u8 nsect, lbal;
729
730 ap->ops->dev_select(ap, device);
731
732 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
733 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
734
735 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
736 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
737
738 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
739 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
740
741 nsect = readb((void __iomem *) ioaddr->nsect_addr);
742 lbal = readb((void __iomem *) ioaddr->lbal_addr);
743
744 if ((nsect == 0x55) && (lbal == 0xaa))
745 return 1; /* we found a device */
746
747 return 0; /* nothing found */
748}
749
750/**
751 * ata_devchk - PATA device presence detection
752 * @ap: ATA channel to examine
753 * @device: Device to examine (starting at zero)
754 *
755 * Dispatch ATA device presence detection, depending
756 * on whether we are using PIO or MMIO to talk to the
757 * ATA shadow registers.
758 *
759 * LOCKING:
760 * caller.
761 */
762
763static unsigned int ata_devchk(struct ata_port *ap,
764 unsigned int device)
765{
766 if (ap->flags & ATA_FLAG_MMIO)
767 return ata_mmio_devchk(ap, device);
768 return ata_pio_devchk(ap, device);
769}
770
771/**
772 * ata_dev_classify - determine device type based on ATA-spec signature
773 * @tf: ATA taskfile register set for device to be identified
774 *
775 * Determine from taskfile register contents whether a device is
776 * ATA or ATAPI, as per "Signature and persistence" section
777 * of ATA/PI spec (volume 1, sect 5.14).
778 *
779 * LOCKING:
780 * None.
781 *
782 * RETURNS:
783 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
784 * the event of failure.
785 */
786
057ace5e 787unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 788{
789 /* Apple's open source Darwin code hints that some devices only
790 * put a proper signature into the LBA mid/high registers,
791 * So, we only check those. It's sufficient for uniqueness.
792 */
793
794 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
795 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
796 DPRINTK("found ATA device by sig\n");
797 return ATA_DEV_ATA;
798 }
799
800 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
801 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
802 DPRINTK("found ATAPI device by sig\n");
803 return ATA_DEV_ATAPI;
804 }
805
806 DPRINTK("unknown device\n");
807 return ATA_DEV_UNKNOWN;
808}
809
810/**
811 * ata_dev_try_classify - Parse returned ATA device signature
812 * @ap: ATA channel to examine
813 * @device: Device to examine (starting at zero)
814 *
815 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
816 * an ATA/ATAPI-defined set of values is placed in the ATA
817 * shadow registers, indicating the results of device detection
818 * and diagnostics.
819 *
820 * Select the ATA device, and read the values from the ATA shadow
821 * registers. Then parse according to the Error register value,
822 * and the spec-defined values examined by ata_dev_classify().
823 *
824 * LOCKING:
825 * caller.
826 */
827
828static u8 ata_dev_try_classify(struct ata_port *ap, unsigned int device)
829{
830 struct ata_device *dev = &ap->device[device];
831 struct ata_taskfile tf;
832 unsigned int class;
833 u8 err;
834
835 ap->ops->dev_select(ap, device);
836
837 memset(&tf, 0, sizeof(tf));
838
1da177e4 839 ap->ops->tf_read(ap, &tf);
0169e284 840 err = tf.feature;
1da177e4
LT		 841
842 dev->class = ATA_DEV_NONE;
843
844 /* see if device passed diags */
845 if (err == 1)
846 /* do nothing */ ;
847 else if ((device == 0) && (err == 0x81))
848 /* do nothing */ ;
849 else
850 return err;
851
852 /* determine if device if ATA or ATAPI */
853 class = ata_dev_classify(&tf);
854 if (class == ATA_DEV_UNKNOWN)
855 return err;
856 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
857 return err;
858
859 dev->class = class;
860
861 return err;
862}
863
864/**
865 * ata_dev_id_string - Convert IDENTIFY DEVICE page into string
866 * @id: IDENTIFY DEVICE results we will examine
867 * @s: string into which data is output
868 * @ofs: offset into identify device page
869 * @len: length of string to return. must be an even number.
870 *
871 * The strings in the IDENTIFY DEVICE page are broken up into
872 * 16-bit chunks. Run through the string, and output each
873 * 8-bit chunk linearly, regardless of platform.
874 *
875 * LOCKING:
876 * caller.
877 */
878
057ace5e 879void ata_dev_id_string(const u16 *id, unsigned char *s,
1da177e4
LT		 880 unsigned int ofs, unsigned int len)
881{
882 unsigned int c;
883
884 while (len > 0) {
885 c = id[ofs] >> 8;
886 *s = c;
887 s++;
888
889 c = id[ofs] & 0xff;
890 *s = c;
891 s++;
892
893 ofs++;
894 len -= 2;
895 }
896}
897
0baab86b
EF		 898
899/**
900 * ata_noop_dev_select - Select device 0/1 on ATA bus
901 * @ap: ATA channel to manipulate
902 * @device: ATA device (numbered from zero) to select
903 *
904 * This function performs no actual function.
905 *
906 * May be used as the dev_select() entry in ata_port_operations.
907 *
908 * LOCKING:
909 * caller.
910 */
1da177e4
LT		 911void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
912{
913}
914
0baab86b 915
1da177e4
LT		 916/**
917 * ata_std_dev_select - Select device 0/1 on ATA bus
918 * @ap: ATA channel to manipulate
919 * @device: ATA device (numbered from zero) to select
920 *
921 * Use the method defined in the ATA specification to
922 * make either device 0, or device 1, active on the
0baab86b
EF		 923 * ATA channel. Works with both PIO and MMIO.
924 *
925 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 926 *
927 * LOCKING:
928 * caller.
929 */
930
931void ata_std_dev_select (struct ata_port *ap, unsigned int device)
932{
933 u8 tmp;
934
935 if (device == 0)
936 tmp = ATA_DEVICE_OBS;
937 else
938 tmp = ATA_DEVICE_OBS | ATA_DEV1;
939
940 if (ap->flags & ATA_FLAG_MMIO) {
941 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
942 } else {
943 outb(tmp, ap->ioaddr.device_addr);
944 }
945 ata_pause(ap); /* needed; also flushes, for mmio */
946}
947
948/**
949 * ata_dev_select - Select device 0/1 on ATA bus
950 * @ap: ATA channel to manipulate
951 * @device: ATA device (numbered from zero) to select
952 * @wait: non-zero to wait for Status register BSY bit to clear
953 * @can_sleep: non-zero if context allows sleeping
954 *
955 * Use the method defined in the ATA specification to
956 * make either device 0, or device 1, active on the
957 * ATA channel.
958 *
959 * This is a high-level version of ata_std_dev_select(),
960 * which additionally provides the services of inserting
961 * the proper pauses and status polling, where needed.
962 *
963 * LOCKING:
964 * caller.
965 */
966
967void ata_dev_select(struct ata_port *ap, unsigned int device,
968 unsigned int wait, unsigned int can_sleep)
969{
970 VPRINTK("ENTER, ata%u: device %u, wait %u\n",
971 ap->id, device, wait);
972
973 if (wait)
974 ata_wait_idle(ap);
975
976 ap->ops->dev_select(ap, device);
977
978 if (wait) {
979 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
980 msleep(150);
981 ata_wait_idle(ap);
982 }
983}
984
985/**
986 * ata_dump_id - IDENTIFY DEVICE info debugging output
987 * @dev: Device whose IDENTIFY DEVICE page we will dump
988 *
989 * Dump selected 16-bit words from a detected device's
990 * IDENTIFY PAGE page.
991 *
992 * LOCKING:
993 * caller.
994 */
995
057ace5e 996static inline void ata_dump_id(const struct ata_device *dev)
1da177e4
LT		 997{
998 DPRINTK("49==0x%04x "
999 "53==0x%04x "
1000 "63==0x%04x "
1001 "64==0x%04x "
1002 "75==0x%04x \n",
1003 dev->id[49],
1004 dev->id[53],
1005 dev->id[63],
1006 dev->id[64],
1007 dev->id[75]);
1008 DPRINTK("80==0x%04x "
1009 "81==0x%04x "
1010 "82==0x%04x "
1011 "83==0x%04x "
1012 "84==0x%04x \n",
1013 dev->id[80],
1014 dev->id[81],
1015 dev->id[82],
1016 dev->id[83],
1017 dev->id[84]);
1018 DPRINTK("88==0x%04x "
1019 "93==0x%04x\n",
1020 dev->id[88],
1021 dev->id[93]);
1022}
1023
11e29e21
AC		 1024/*
1025 * Compute the PIO modes available for this device. This is not as
1026 * trivial as it seems if we must consider early devices correctly.
1027 *
1028 * FIXME: pre IDE drive timing (do we care ?).
1029 */
1030
057ace5e 1031static unsigned int ata_pio_modes(const struct ata_device *adev)
11e29e21
AC		 1032{
1033 u16 modes;
1034
1035 /* Usual case. Word 53 indicates word 88 is valid */
1036 if (adev->id[ATA_ID_FIELD_VALID] & (1 << 2)) {
1037 modes = adev->id[ATA_ID_PIO_MODES] & 0x03;
1038 modes <<= 3;
1039 modes |= 0x7;
1040 return modes;
1041 }
1042
1043 /* If word 88 isn't valid then Word 51 holds the PIO timing number
1044 for the maximum. Turn it into a mask and return it */
1045 modes = (2 << (adev->id[ATA_ID_OLD_PIO_MODES] & 0xFF)) - 1 ;
1046 return modes;
1047}
1048
1da177e4
LT		 1049/**
1050 * ata_dev_identify - obtain IDENTIFY x DEVICE page
1051 * @ap: port on which device we wish to probe resides
1052 * @device: device bus address, starting at zero
1053 *
1054 * Following bus reset, we issue the IDENTIFY [PACKET] DEVICE
1055 * command, and read back the 512-byte device information page.
1056 * The device information page is fed to us via the standard
1057 * PIO-IN protocol, but we hand-code it here. (TODO: investigate
1058 * using standard PIO-IN paths)
1059 *
1060 * After reading the device information page, we use several
1061 * bits of information from it to initialize data structures
1062 * that will be used during the lifetime of the ata_device.
1063 * Other data from the info page is used to disqualify certain
1064 * older ATA devices we do not wish to support.
1065 *
1066 * LOCKING:
1067 * Inherited from caller. Some functions called by this function
1068 * obtain the host_set lock.
1069 */
1070
1071static void ata_dev_identify(struct ata_port *ap, unsigned int device)
1072{
1073 struct ata_device *dev = &ap->device[device];
8bf62ece 1074 unsigned int major_version;
1da177e4
LT		 1075 u16 tmp;
1076 unsigned long xfer_modes;
1da177e4
LT		 1077 unsigned int using_edd;
1078 DECLARE_COMPLETION(wait);
1079 struct ata_queued_cmd *qc;
1080 unsigned long flags;
1081 int rc;
1082
1083 if (!ata_dev_present(dev)) {
1084 DPRINTK("ENTER/EXIT (host %u, dev %u) -- nodev\n",
1085 ap->id, device);
1086 return;
1087 }
1088
1089 if (ap->flags & (ATA_FLAG_SRST | ATA_FLAG_SATA_RESET))
1090 using_edd = 0;
1091 else
1092 using_edd = 1;
1093
1094 DPRINTK("ENTER, host %u, dev %u\n", ap->id, device);
1095
1096 assert (dev->class == ATA_DEV_ATA || dev->class == ATA_DEV_ATAPI ||
1097 dev->class == ATA_DEV_NONE);
1098
1099 ata_dev_select(ap, device, 1, 1); /* select device 0/1 */
1100
1101 qc = ata_qc_new_init(ap, dev);
1102 BUG_ON(qc == NULL);
1103
1104 ata_sg_init_one(qc, dev->id, sizeof(dev->id));
1105 qc->dma_dir = DMA_FROM_DEVICE;
1106 qc->tf.protocol = ATA_PROT_PIO;
1107 qc->nsect = 1;
1108
1109retry:
1110 if (dev->class == ATA_DEV_ATA) {
1111 qc->tf.command = ATA_CMD_ID_ATA;
1112 DPRINTK("do ATA identify\n");
1113 } else {
1114 qc->tf.command = ATA_CMD_ID_ATAPI;
1115 DPRINTK("do ATAPI identify\n");
1116 }
1117
1118 qc->waiting = &wait;
1119 qc->complete_fn = ata_qc_complete_noop;
1120
1121 spin_lock_irqsave(&ap->host_set->lock, flags);
1122 rc = ata_qc_issue(qc);
1123 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1124
1125 if (rc)
1126 goto err_out;
1127 else
1128 wait_for_completion(&wait);
1129
0169e284
JG		 1130 spin_lock_irqsave(&ap->host_set->lock, flags);
1131 ap->ops->tf_read(ap, &qc->tf);
1132 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1133
1134 if (qc->tf.command & ATA_ERR) {
1da177e4
LT		 1135 /*
1136 * arg! EDD works for all test cases, but seems to return
1137 * the ATA signature for some ATAPI devices. Until the
1138 * reason for this is found and fixed, we fix up the mess
1139 * here. If IDENTIFY DEVICE returns command aborted
1140 * (as ATAPI devices do), then we issue an
1141 * IDENTIFY PACKET DEVICE.
1142 *
1143 * ATA software reset (SRST, the default) does not appear
1144 * to have this problem.
1145 */
7c398335 1146 if ((using_edd) && (dev->class == ATA_DEV_ATA)) {
0169e284 1147 u8 err = qc->tf.feature;
1da177e4
LT		 1148 if (err & ATA_ABORTED) {
1149 dev->class = ATA_DEV_ATAPI;
1150 qc->cursg = 0;
1151 qc->cursg_ofs = 0;
1152 qc->cursect = 0;
1153 qc->nsect = 1;
1154 goto retry;
1155 }
1156 }
1157 goto err_out;
1158 }
1159
1160 swap_buf_le16(dev->id, ATA_ID_WORDS);
1161
1162 /* print device capabilities */
1163 printk(KERN_DEBUG "ata%u: dev %u cfg "
1164 "49:%04x 82:%04x 83:%04x 84:%04x 85:%04x 86:%04x 87:%04x 88:%04x\n",
1165 ap->id, device, dev->id[49],
1166 dev->id[82], dev->id[83], dev->id[84],
1167 dev->id[85], dev->id[86], dev->id[87],
1168 dev->id[88]);
1169
1170 /*
1171 * common ATA, ATAPI feature tests
1172 */
1173
8bf62ece
AL		 1174 /* we require DMA support (bits 8 of word 49) */
1175 if (!ata_id_has_dma(dev->id)) {
1176 printk(KERN_DEBUG "ata%u: no dma\n", ap->id);
1da177e4
LT		 1177 goto err_out_nosup;
1178 }
1179
1180 /* quick-n-dirty find max transfer mode; for printk only */
1181 xfer_modes = dev->id[ATA_ID_UDMA_MODES];
1182 if (!xfer_modes)
1183 xfer_modes = (dev->id[ATA_ID_MWDMA_MODES]) << ATA_SHIFT_MWDMA;
11e29e21
AC		 1184 if (!xfer_modes)
1185 xfer_modes = ata_pio_modes(dev);
1da177e4
LT		 1186
1187 ata_dump_id(dev);
1188
1189 /* ATA-specific feature tests */
1190 if (dev->class == ATA_DEV_ATA) {
1191 if (!ata_id_is_ata(dev->id)) /* sanity check */
1192 goto err_out_nosup;
1193
8bf62ece 1194 /* get major version */
1da177e4 1195 tmp = dev->id[ATA_ID_MAJOR_VER];
8bf62ece
AL		 1196 for (major_version = 14; major_version >= 1; major_version--)
1197 if (tmp & (1 << major_version))
1da177e4
LT		 1198 break;
1199
8bf62ece
AL		 1200 /*
1201 * The exact sequence expected by certain pre-ATA4 drives is:
1202 * SRST RESET
1203 * IDENTIFY
1204 * INITIALIZE DEVICE PARAMETERS
1205 * anything else..
1206 * Some drives were very specific about that exact sequence.
1207 */
59a10b17 1208 if (major_version < 4 || (!ata_id_has_lba(dev->id))) {
8bf62ece
AL		 1209 ata_dev_init_params(ap, dev);
1210
59a10b17
AL		 1211 /* current CHS translation info (id[53-58]) might be
1212 * changed. reread the identify device info.
1213 */
1214 ata_dev_reread_id(ap, dev);
1215 }
1216
8bf62ece
AL		 1217 if (ata_id_has_lba(dev->id)) {
1218 dev->flags |= ATA_DFLAG_LBA;
1219
1220 if (ata_id_has_lba48(dev->id)) {
1221 dev->flags |= ATA_DFLAG_LBA48;
1222 dev->n_sectors = ata_id_u64(dev->id, 100);
1223 } else {
1224 dev->n_sectors = ata_id_u32(dev->id, 60);
1225 }
1226
1227 /* print device info to dmesg */
1228 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors:%s\n",
1229 ap->id, device,
1230 major_version,
1231 ata_mode_string(xfer_modes),
1232 (unsigned long long)dev->n_sectors,
1233 dev->flags & ATA_DFLAG_LBA48 ? " LBA48" : " LBA");
1234 } else {
1235 /* CHS */
1236
1237 /* Default translation */
1238 dev->cylinders = dev->id[1];
1239 dev->heads = dev->id[3];
1240 dev->sectors = dev->id[6];
1241 dev->n_sectors = dev->cylinders * dev->heads * dev->sectors;
1242
1243 if (ata_id_current_chs_valid(dev->id)) {
1244 /* Current CHS translation is valid. */
1245 dev->cylinders = dev->id[54];
1246 dev->heads = dev->id[55];
1247 dev->sectors = dev->id[56];
1248
1249 dev->n_sectors = ata_id_u32(dev->id, 57);
1250 }
1251
1252 /* print device info to dmesg */
1253 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors: CHS %d/%d/%d\n",
1254 ap->id, device,
1255 major_version,
1256 ata_mode_string(xfer_modes),
1257 (unsigned long long)dev->n_sectors,
1258 (int)dev->cylinders, (int)dev->heads, (int)dev->sectors);
1da177e4 1259
1da177e4
LT		 1260 }
1261
1262 ap->host->max_cmd_len = 16;
1da177e4
LT		 1263 }
1264
1265 /* ATAPI-specific feature tests */
1266 else {
1267 if (ata_id_is_ata(dev->id)) /* sanity check */
1268 goto err_out_nosup;
1269
1270 rc = atapi_cdb_len(dev->id);
1271 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
1272 printk(KERN_WARNING "ata%u: unsupported CDB len\n", ap->id);
1273 goto err_out_nosup;
1274 }
1275 ap->cdb_len = (unsigned int) rc;
1276 ap->host->max_cmd_len = (unsigned char) ap->cdb_len;
1277
1278 /* print device info to dmesg */
1279 printk(KERN_INFO "ata%u: dev %u ATAPI, max %s\n",
1280 ap->id, device,
1281 ata_mode_string(xfer_modes));
1282 }
1283
1284 DPRINTK("EXIT, drv_stat = 0x%x\n", ata_chk_status(ap));
1285 return;
1286
1287err_out_nosup:
1288 printk(KERN_WARNING "ata%u: dev %u not supported, ignoring\n",
1289 ap->id, device);
1290err_out:
1291 dev->class++; /* converts ATA_DEV_xxx into ATA_DEV_xxx_UNSUP */
1292 DPRINTK("EXIT, err\n");
1293}
1294
6f2f3812 1295
057ace5e 1296static inline u8 ata_dev_knobble(const struct ata_port *ap)
6f2f3812
BC		 1297{
1298 return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ap->device->id)));
1299}
1300
1301/**
1302 * ata_dev_config - Run device specific handlers and check for
1303 * SATA->PATA bridges
8a60a071 1304 * @ap: Bus
6f2f3812
BC		 1305 * @i: Device
1306 *
1307 * LOCKING:
1308 */
8a60a071 1309
6f2f3812
BC		 1310void ata_dev_config(struct ata_port *ap, unsigned int i)
1311{
1312 /* limit bridge transfers to udma5, 200 sectors */
1313 if (ata_dev_knobble(ap)) {
1314 printk(KERN_INFO "ata%u(%u): applying bridge limits\n",
1315 ap->id, ap->device->devno);
1316 ap->udma_mask &= ATA_UDMA5;
1317 ap->host->max_sectors = ATA_MAX_SECTORS;
1318 ap->host->hostt->max_sectors = ATA_MAX_SECTORS;
1319 ap->device->flags |= ATA_DFLAG_LOCK_SECTORS;
1320 }
1321
1322 if (ap->ops->dev_config)
1323 ap->ops->dev_config(ap, &ap->device[i]);
1324}
1325
1da177e4
LT		 1326/**
1327 * ata_bus_probe - Reset and probe ATA bus
1328 * @ap: Bus to probe
1329 *
0cba632b
JG		 1330 * Master ATA bus probing function. Initiates a hardware-dependent
1331 * bus reset, then attempts to identify any devices found on
1332 * the bus.
1333 *
1da177e4 1334 * LOCKING:
0cba632b 1335 * PCI/etc. bus probe sem.
1da177e4
LT		 1336 *
1337 * RETURNS:
1338 * Zero on success, non-zero on error.
1339 */
1340
1341static int ata_bus_probe(struct ata_port *ap)
1342{
1343 unsigned int i, found = 0;
1344
1345 ap->ops->phy_reset(ap);
1346 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1347 goto err_out;
1348
1349 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1350 ata_dev_identify(ap, i);
1351 if (ata_dev_present(&ap->device[i])) {
1352 found = 1;
6f2f3812 1353 ata_dev_config(ap,i);
1da177e4
LT		 1354 }
1355 }
1356
1357 if ((!found) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1358 goto err_out_disable;
1359
1360 ata_set_mode(ap);
1361 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1362 goto err_out_disable;
1363
1364 return 0;
1365
1366err_out_disable:
1367 ap->ops->port_disable(ap);
1368err_out:
1369 return -1;
1370}
1371
1372/**
0cba632b
JG		 1373 * ata_port_probe - Mark port as enabled
1374 * @ap: Port for which we indicate enablement
1da177e4 1375 *
0cba632b
JG		 1376 * Modify @ap data structure such that the system
1377 * thinks that the entire port is enabled.
1378 *
1379 * LOCKING: host_set lock, or some other form of
1380 * serialization.
1da177e4
LT		 1381 */
1382
1383void ata_port_probe(struct ata_port *ap)
1384{
1385 ap->flags &= ~ATA_FLAG_PORT_DISABLED;
1386}
1387
1388/**
780a87f7
JG		 1389 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1390 * @ap: SATA port associated with target SATA PHY.
1da177e4 1391 *
780a87f7
JG		 1392 * This function issues commands to standard SATA Sxxx
1393 * PHY registers, to wake up the phy (and device), and
1394 * clear any reset condition.
1da177e4
LT		 1395 *
1396 * LOCKING:
0cba632b 1397 * PCI/etc. bus probe sem.
1da177e4
LT		 1398 *
1399 */
1400void __sata_phy_reset(struct ata_port *ap)
1401{
1402 u32 sstatus;
1403 unsigned long timeout = jiffies + (HZ * 5);
1404
1405 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e
BR		 1406 /* issue phy wake/reset */
1407 scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1408 /* Couldn't find anything in SATA I/II specs, but
1409 * AHCI-1.1 10.4.2 says at least 1 ms. */
1410 mdelay(1);
1da177e4 1411 }
cdcca89e 1412 scr_write_flush(ap, SCR_CONTROL, 0x300); /* phy wake/clear reset */
1da177e4
LT		 1413
1414 /* wait for phy to become ready, if necessary */
1415 do {
1416 msleep(200);
1417 sstatus = scr_read(ap, SCR_STATUS);
1418 if ((sstatus & 0xf) != 1)
1419 break;
1420 } while (time_before(jiffies, timeout));
1421
1422 /* TODO: phy layer with polling, timeouts, etc. */
1423 if (sata_dev_present(ap))
1424 ata_port_probe(ap);
1425 else {
1426 sstatus = scr_read(ap, SCR_STATUS);
1427 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1428 ap->id, sstatus);
1429 ata_port_disable(ap);
1430 }
1431
1432 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1433 return;
1434
1435 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1436 ata_port_disable(ap);
1437 return;
1438 }
1439
1440 ap->cbl = ATA_CBL_SATA;
1441}
1442
1443/**
780a87f7
JG		 1444 * sata_phy_reset - Reset SATA bus.
1445 * @ap: SATA port associated with target SATA PHY.
1da177e4 1446 *
780a87f7
JG		 1447 * This function resets the SATA bus, and then probes
1448 * the bus for devices.
1da177e4
LT		 1449 *
1450 * LOCKING:
0cba632b 1451 * PCI/etc. bus probe sem.
1da177e4
LT		 1452 *
1453 */
1454void sata_phy_reset(struct ata_port *ap)
1455{
1456 __sata_phy_reset(ap);
1457 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1458 return;
1459 ata_bus_reset(ap);
1460}
1461
1462/**
780a87f7
JG		 1463 * ata_port_disable - Disable port.
1464 * @ap: Port to be disabled.
1da177e4 1465 *
780a87f7
JG		 1466 * Modify @ap data structure such that the system
1467 * thinks that the entire port is disabled, and should
1468 * never attempt to probe or communicate with devices
1469 * on this port.
1470 *
1471 * LOCKING: host_set lock, or some other form of
1472 * serialization.
1da177e4
LT		 1473 */
1474
1475void ata_port_disable(struct ata_port *ap)
1476{
1477 ap->device[0].class = ATA_DEV_NONE;
1478 ap->device[1].class = ATA_DEV_NONE;
1479 ap->flags |= ATA_FLAG_PORT_DISABLED;
1480}
1481
452503f9
AC		 1482/*
1483 * This mode timing computation functionality is ported over from
1484 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1485 */
1486/*
1487 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
1488 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
1489 * for PIO 5, which is a nonstandard extension and UDMA6, which
1490 * is currently supported only by Maxtor drives.
1491 */
1492
1493static const struct ata_timing ata_timing[] = {
1494
1495 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1496 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1497 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1498 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1499
1500 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1501 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1502 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1503
1504/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
1505
1506 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1507 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1508 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
1509
1510 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1511 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1512 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1513
1514/* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */
1515 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1516 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1517
1518 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1519 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1520 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1521
1522/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1523
1524 { 0xFF }
1525};
1526
1527#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
1528#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1529
1530static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
1531{
1532 q->setup = EZ(t->setup * 1000, T);
1533 q->act8b = EZ(t->act8b * 1000, T);
1534 q->rec8b = EZ(t->rec8b * 1000, T);
1535 q->cyc8b = EZ(t->cyc8b * 1000, T);
1536 q->active = EZ(t->active * 1000, T);
1537 q->recover = EZ(t->recover * 1000, T);
1538 q->cycle = EZ(t->cycle * 1000, T);
1539 q->udma = EZ(t->udma * 1000, UT);
1540}
1541
1542void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
1543 struct ata_timing *m, unsigned int what)
1544{
1545 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
1546 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
1547 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
1548 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
1549 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
1550 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
1551 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
1552 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
1553}
1554
1555static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
1556{
1557 const struct ata_timing *t;
1558
1559 for (t = ata_timing; t->mode != speed; t++)
91190758 1560 if (t->mode == 0xFF)
452503f9
AC		 1561 return NULL;
1562 return t;
1563}
1564
1565int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1566 struct ata_timing *t, int T, int UT)
1567{
1568 const struct ata_timing *s;
1569 struct ata_timing p;
1570
1571 /*
1572 * Find the mode.
1573 */
1574
1575 if (!(s = ata_timing_find_mode(speed)))
1576 return -EINVAL;
1577
1578 /*
1579 * If the drive is an EIDE drive, it can tell us it needs extended
1580 * PIO/MW_DMA cycle timing.
1581 */
1582
1583 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
1584 memset(&p, 0, sizeof(p));
1585 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
1586 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
1587 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
1588 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
1589 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
1590 }
1591 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
1592 }
1593
1594 /*
1595 * Convert the timing to bus clock counts.
1596 */
1597
1598 ata_timing_quantize(s, t, T, UT);
1599
1600 /*
1601 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T
1602 * and some other commands. We have to ensure that the DMA cycle timing is
1603 * slower/equal than the fastest PIO timing.
1604 */
1605
1606 if (speed > XFER_PIO_4) {
1607 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
1608 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
1609 }
1610
1611 /*
1612 * Lenghten active & recovery time so that cycle time is correct.
1613 */
1614
1615 if (t->act8b + t->rec8b < t->cyc8b) {
1616 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
1617 t->rec8b = t->cyc8b - t->act8b;
1618 }
1619
1620 if (t->active + t->recover < t->cycle) {
1621 t->active += (t->cycle - (t->active + t->recover)) / 2;
1622 t->recover = t->cycle - t->active;
1623 }
1624
1625 return 0;
1626}
1627
057ace5e 1628static const struct {
1da177e4
LT		 1629 unsigned int shift;
1630 u8 base;
1631} xfer_mode_classes[] = {
1632 { ATA_SHIFT_UDMA, XFER_UDMA_0 },
1633 { ATA_SHIFT_MWDMA, XFER_MW_DMA_0 },
1634 { ATA_SHIFT_PIO, XFER_PIO_0 },
1635};
1636
1637static inline u8 base_from_shift(unsigned int shift)
1638{
1639 int i;
1640
1641 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++)
1642 if (xfer_mode_classes[i].shift == shift)
1643 return xfer_mode_classes[i].base;
1644
1645 return 0xff;
1646}
1647
1648static void ata_dev_set_mode(struct ata_port *ap, struct ata_device *dev)
1649{
1650 int ofs, idx;
1651 u8 base;
1652
1653 if (!ata_dev_present(dev) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1654 return;
1655
1656 if (dev->xfer_shift == ATA_SHIFT_PIO)
1657 dev->flags |= ATA_DFLAG_PIO;
1658
1659 ata_dev_set_xfermode(ap, dev);
1660
1661 base = base_from_shift(dev->xfer_shift);
1662 ofs = dev->xfer_mode - base;
1663 idx = ofs + dev->xfer_shift;
1664 WARN_ON(idx >= ARRAY_SIZE(xfer_mode_str));
1665
1666 DPRINTK("idx=%d xfer_shift=%u, xfer_mode=0x%x, base=0x%x, offset=%d\n",
1667 idx, dev->xfer_shift, (int)dev->xfer_mode, (int)base, ofs);
1668
1669 printk(KERN_INFO "ata%u: dev %u configured for %s\n",
1670 ap->id, dev->devno, xfer_mode_str[idx]);
1671}
1672
1673static int ata_host_set_pio(struct ata_port *ap)
1674{
1675 unsigned int mask;
1676 int x, i;
1677 u8 base, xfer_mode;
1678
1679 mask = ata_get_mode_mask(ap, ATA_SHIFT_PIO);
1680 x = fgb(mask);
1681 if (x < 0) {
1682 printk(KERN_WARNING "ata%u: no PIO support\n", ap->id);
1683 return -1;
1684 }
1685
1686 base = base_from_shift(ATA_SHIFT_PIO);
1687 xfer_mode = base + x;
1688
1689 DPRINTK("base 0x%x xfer_mode 0x%x mask 0x%x x %d\n",
1690 (int)base, (int)xfer_mode, mask, x);
1691
1692 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1693 struct ata_device *dev = &ap->device[i];
1694 if (ata_dev_present(dev)) {
1695 dev->pio_mode = xfer_mode;
1696 dev->xfer_mode = xfer_mode;
1697 dev->xfer_shift = ATA_SHIFT_PIO;
1698 if (ap->ops->set_piomode)
1699 ap->ops->set_piomode(ap, dev);
1700 }
1701 }
1702
1703 return 0;
1704}
1705
1706static void ata_host_set_dma(struct ata_port *ap, u8 xfer_mode,
1707 unsigned int xfer_shift)
1708{
1709 int i;
1710
1711 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1712 struct ata_device *dev = &ap->device[i];
1713 if (ata_dev_present(dev)) {
1714 dev->dma_mode = xfer_mode;
1715 dev->xfer_mode = xfer_mode;
1716 dev->xfer_shift = xfer_shift;
1717 if (ap->ops->set_dmamode)
1718 ap->ops->set_dmamode(ap, dev);
1719 }
1720 }
1721}
1722
1723/**
1724 * ata_set_mode - Program timings and issue SET FEATURES - XFER
1725 * @ap: port on which timings will be programmed
1726 *
780a87f7
JG		 1727 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.).
1728 *
1da177e4 1729 * LOCKING:
0cba632b 1730 * PCI/etc. bus probe sem.
1da177e4
LT		 1731 *
1732 */
1733static void ata_set_mode(struct ata_port *ap)
1734{
8cbd6df1 1735 unsigned int xfer_shift;
1da177e4
LT		 1736 u8 xfer_mode;
1737 int rc;
1738
1739 /* step 1: always set host PIO timings */
1740 rc = ata_host_set_pio(ap);
1741 if (rc)
1742 goto err_out;
1743
1744 /* step 2: choose the best data xfer mode */
1745 xfer_mode = xfer_shift = 0;
1746 rc = ata_choose_xfer_mode(ap, &xfer_mode, &xfer_shift);
1747 if (rc)
1748 goto err_out;
1749
1750 /* step 3: if that xfer mode isn't PIO, set host DMA timings */
1751 if (xfer_shift != ATA_SHIFT_PIO)
1752 ata_host_set_dma(ap, xfer_mode, xfer_shift);
1753
1754 /* step 4: update devices' xfer mode */
1755 ata_dev_set_mode(ap, &ap->device[0]);
1756 ata_dev_set_mode(ap, &ap->device[1]);
1757
1758 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1759 return;
1760
1761 if (ap->ops->post_set_mode)
1762 ap->ops->post_set_mode(ap);
1763
1da177e4
LT		 1764 return;
1765
1766err_out:
1767 ata_port_disable(ap);
1768}
1769
1770/**
1771 * ata_busy_sleep - sleep until BSY clears, or timeout
1772 * @ap: port containing status register to be polled
1773 * @tmout_pat: impatience timeout
1774 * @tmout: overall timeout
1775 *
780a87f7
JG		 1776 * Sleep until ATA Status register bit BSY clears,
1777 * or a timeout occurs.
1778 *
1779 * LOCKING: None.
1da177e4
LT		 1780 *
1781 */
1782
1783static unsigned int ata_busy_sleep (struct ata_port *ap,
1784 unsigned long tmout_pat,
1785 unsigned long tmout)
1786{
1787 unsigned long timer_start, timeout;
1788 u8 status;
1789
1790 status = ata_busy_wait(ap, ATA_BUSY, 300);
1791 timer_start = jiffies;
1792 timeout = timer_start + tmout_pat;
1793 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1794 msleep(50);
1795 status = ata_busy_wait(ap, ATA_BUSY, 3);
1796 }
1797
1798 if (status & ATA_BUSY)
1799 printk(KERN_WARNING "ata%u is slow to respond, "
1800 "please be patient\n", ap->id);
1801
1802 timeout = timer_start + tmout;
1803 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1804 msleep(50);
1805 status = ata_chk_status(ap);
1806 }
1807
1808 if (status & ATA_BUSY) {
1809 printk(KERN_ERR "ata%u failed to respond (%lu secs)\n",
1810 ap->id, tmout / HZ);
1811 return 1;
1812 }
1813
1814 return 0;
1815}
1816
1817static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
1818{
1819 struct ata_ioports *ioaddr = &ap->ioaddr;
1820 unsigned int dev0 = devmask & (1 << 0);
1821 unsigned int dev1 = devmask & (1 << 1);
1822 unsigned long timeout;
1823
1824 /* if device 0 was found in ata_devchk, wait for its
1825 * BSY bit to clear
1826 */
1827 if (dev0)
1828 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1829
1830 /* if device 1 was found in ata_devchk, wait for
1831 * register access, then wait for BSY to clear
1832 */
1833 timeout = jiffies + ATA_TMOUT_BOOT;
1834 while (dev1) {
1835 u8 nsect, lbal;
1836
1837 ap->ops->dev_select(ap, 1);
1838 if (ap->flags & ATA_FLAG_MMIO) {
1839 nsect = readb((void __iomem *) ioaddr->nsect_addr);
1840 lbal = readb((void __iomem *) ioaddr->lbal_addr);
1841 } else {
1842 nsect = inb(ioaddr->nsect_addr);
1843 lbal = inb(ioaddr->lbal_addr);
1844 }
1845 if ((nsect == 1) && (lbal == 1))
1846 break;
1847 if (time_after(jiffies, timeout)) {
1848 dev1 = 0;
1849 break;
1850 }
1851 msleep(50); /* give drive a breather */
1852 }
1853 if (dev1)
1854 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1855
1856 /* is all this really necessary? */
1857 ap->ops->dev_select(ap, 0);
1858 if (dev1)
1859 ap->ops->dev_select(ap, 1);
1860 if (dev0)
1861 ap->ops->dev_select(ap, 0);
1862}
1863
1864/**
0cba632b
JG		 1865 * ata_bus_edd - Issue EXECUTE DEVICE DIAGNOSTIC command.
1866 * @ap: Port to reset and probe
1867 *
1868 * Use the EXECUTE DEVICE DIAGNOSTIC command to reset and
1869 * probe the bus. Not often used these days.
1da177e4
LT		 1870 *
1871 * LOCKING:
0cba632b 1872 * PCI/etc. bus probe sem.
e5338254 1873 * Obtains host_set lock.
1da177e4
LT		 1874 *
1875 */
1876
1877static unsigned int ata_bus_edd(struct ata_port *ap)
1878{
1879 struct ata_taskfile tf;
e5338254 1880 unsigned long flags;
1da177e4
LT		 1881
1882 /* set up execute-device-diag (bus reset) taskfile */
1883 /* also, take interrupts to a known state (disabled) */
1884 DPRINTK("execute-device-diag\n");
1885 ata_tf_init(ap, &tf, 0);
1886 tf.ctl |= ATA_NIEN;
1887 tf.command = ATA_CMD_EDD;
1888 tf.protocol = ATA_PROT_NODATA;
1889
1890 /* do bus reset */
e5338254 1891 spin_lock_irqsave(&ap->host_set->lock, flags);
1da177e4 1892 ata_tf_to_host(ap, &tf);
e5338254 1893 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1da177e4
LT		 1894
1895 /* spec says at least 2ms. but who knows with those
1896 * crazy ATAPI devices...
1897 */
1898 msleep(150);
1899
1900 return ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1901}
1902
1903static unsigned int ata_bus_softreset(struct ata_port *ap,
1904 unsigned int devmask)
1905{
1906 struct ata_ioports *ioaddr = &ap->ioaddr;
1907
1908 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
1909
1910 /* software reset. causes dev0 to be selected */
1911 if (ap->flags & ATA_FLAG_MMIO) {
1912 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1913 udelay(20); /* FIXME: flush */
1914 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
1915 udelay(20); /* FIXME: flush */
1916 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1917 } else {
1918 outb(ap->ctl, ioaddr->ctl_addr);
1919 udelay(10);
1920 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1921 udelay(10);
1922 outb(ap->ctl, ioaddr->ctl_addr);
1923 }
1924
1925 /* spec mandates ">= 2ms" before checking status.
1926 * We wait 150ms, because that was the magic delay used for
1927 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1928 * between when the ATA command register is written, and then
1929 * status is checked. Because waiting for "a while" before
1930 * checking status is fine, post SRST, we perform this magic
1931 * delay here as well.
1932 */
1933 msleep(150);
1934
1935 ata_bus_post_reset(ap, devmask);
1936
1937 return 0;
1938}
1939
1940/**
1941 * ata_bus_reset - reset host port and associated ATA channel
1942 * @ap: port to reset
1943 *
1944 * This is typically the first time we actually start issuing
1945 * commands to the ATA channel. We wait for BSY to clear, then
1946 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
1947 * result. Determine what devices, if any, are on the channel
1948 * by looking at the device 0/1 error register. Look at the signature
1949 * stored in each device's taskfile registers, to determine if
1950 * the device is ATA or ATAPI.
1951 *
1952 * LOCKING:
0cba632b
JG		 1953 * PCI/etc. bus probe sem.
1954 * Obtains host_set lock.
1da177e4
LT		 1955 *
1956 * SIDE EFFECTS:
1957 * Sets ATA_FLAG_PORT_DISABLED if bus reset fails.
1958 */
1959
1960void ata_bus_reset(struct ata_port *ap)
1961{
1962 struct ata_ioports *ioaddr = &ap->ioaddr;
1963 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1964 u8 err;
1965 unsigned int dev0, dev1 = 0, rc = 0, devmask = 0;
1966
1967 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
1968
1969 /* determine if device 0/1 are present */
1970 if (ap->flags & ATA_FLAG_SATA_RESET)
1971 dev0 = 1;
1972 else {
1973 dev0 = ata_devchk(ap, 0);
1974 if (slave_possible)
1975 dev1 = ata_devchk(ap, 1);
1976 }
1977
1978 if (dev0)
1979 devmask |= (1 << 0);
1980 if (dev1)
1981 devmask |= (1 << 1);
1982
1983 /* select device 0 again */
1984 ap->ops->dev_select(ap, 0);
1985
1986 /* issue bus reset */
1987 if (ap->flags & ATA_FLAG_SRST)
1988 rc = ata_bus_softreset(ap, devmask);
1989 else if ((ap->flags & ATA_FLAG_SATA_RESET) == 0) {
1990 /* set up device control */
1991 if (ap->flags & ATA_FLAG_MMIO)
1992 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1993 else
1994 outb(ap->ctl, ioaddr->ctl_addr);
1995 rc = ata_bus_edd(ap);
1996 }
1997
1998 if (rc)
1999 goto err_out;
2000
2001 /*
2002 * determine by signature whether we have ATA or ATAPI devices
2003 */
2004 err = ata_dev_try_classify(ap, 0);
2005 if ((slave_possible) && (err != 0x81))
2006 ata_dev_try_classify(ap, 1);
2007
2008 /* re-enable interrupts */
2009 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2010 ata_irq_on(ap);
2011
2012 /* is double-select really necessary? */
2013 if (ap->device[1].class != ATA_DEV_NONE)
2014 ap->ops->dev_select(ap, 1);
2015 if (ap->device[0].class != ATA_DEV_NONE)
2016 ap->ops->dev_select(ap, 0);
2017
2018 /* if no devices were detected, disable this port */
2019 if ((ap->device[0].class == ATA_DEV_NONE) &&
2020 (ap->device[1].class == ATA_DEV_NONE))
2021 goto err_out;
2022
2023 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2024 /* set up device control for ATA_FLAG_SATA_RESET */
2025 if (ap->flags & ATA_FLAG_MMIO)
2026 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2027 else
2028 outb(ap->ctl, ioaddr->ctl_addr);
2029 }
2030
2031 DPRINTK("EXIT\n");
2032 return;
2033
2034err_out:
2035 printk(KERN_ERR "ata%u: disabling port\n", ap->id);
2036 ap->ops->port_disable(ap);
2037
2038 DPRINTK("EXIT\n");
2039}
2040
057ace5e
JG		 2041static void ata_pr_blacklisted(const struct ata_port *ap,
2042 const struct ata_device *dev)
1da177e4
LT		 2043{
2044 printk(KERN_WARNING "ata%u: dev %u is on DMA blacklist, disabling DMA\n",
2045 ap->id, dev->devno);
2046}
2047
2048static const char * ata_dma_blacklist [] = {
2049 "WDC AC11000H",
2050 "WDC AC22100H",
2051 "WDC AC32500H",
2052 "WDC AC33100H",
2053 "WDC AC31600H",
2054 "WDC AC32100H",
2055 "WDC AC23200L",
2056 "Compaq CRD-8241B",
2057 "CRD-8400B",
2058 "CRD-8480B",
2059 "CRD-8482B",
2060 "CRD-84",
2061 "SanDisk SDP3B",
2062 "SanDisk SDP3B-64",
2063 "SANYO CD-ROM CRD",
2064 "HITACHI CDR-8",
2065 "HITACHI CDR-8335",
2066 "HITACHI CDR-8435",
2067 "Toshiba CD-ROM XM-6202B",
e922256a 2068 "TOSHIBA CD-ROM XM-1702BC",
1da177e4
LT		 2069 "CD-532E-A",
2070 "E-IDE CD-ROM CR-840",
2071 "CD-ROM Drive/F5A",
2072 "WPI CDD-820",
2073 "SAMSUNG CD-ROM SC-148C",
2074 "SAMSUNG CD-ROM SC",
2075 "SanDisk SDP3B-64",
1da177e4
LT		 2076 "ATAPI CD-ROM DRIVE 40X MAXIMUM",
2077 "_NEC DV5800A",
2078};
2079
057ace5e 2080static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4
LT		 2081{
2082 unsigned char model_num[40];
2083 char *s;
2084 unsigned int len;
2085 int i;
2086
2087 ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
2088 sizeof(model_num));
2089 s = &model_num[0];
2090 len = strnlen(s, sizeof(model_num));
2091
2092 /* ATAPI specifies that empty space is blank-filled; remove blanks */
2093 while ((len > 0) && (s[len - 1] == ' ')) {
2094 len--;
2095 s[len] = 0;
2096 }
2097
2098 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i++)
2099 if (!strncmp(ata_dma_blacklist[i], s, len))
2100 return 1;
2101
2102 return 0;
2103}
2104
057ace5e 2105static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift)
1da177e4 2106{
057ace5e 2107 const struct ata_device *master, *slave;
1da177e4
LT		 2108 unsigned int mask;
2109
2110 master = &ap->device[0];
2111 slave = &ap->device[1];
2112
2113 assert (ata_dev_present(master) || ata_dev_present(slave));
2114
2115 if (shift == ATA_SHIFT_UDMA) {
2116 mask = ap->udma_mask;
2117 if (ata_dev_present(master)) {
2118 mask &= (master->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2119 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2120 mask = 0;
2121 ata_pr_blacklisted(ap, master);
2122 }
2123 }
2124 if (ata_dev_present(slave)) {
2125 mask &= (slave->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2126 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2127 mask = 0;
2128 ata_pr_blacklisted(ap, slave);
2129 }
2130 }
2131 }
2132 else if (shift == ATA_SHIFT_MWDMA) {
2133 mask = ap->mwdma_mask;
2134 if (ata_dev_present(master)) {
2135 mask &= (master->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2136 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2137 mask = 0;
2138 ata_pr_blacklisted(ap, master);
2139 }
2140 }
2141 if (ata_dev_present(slave)) {
2142 mask &= (slave->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2143 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2144 mask = 0;
2145 ata_pr_blacklisted(ap, slave);
2146 }
2147 }
2148 }
2149 else if (shift == ATA_SHIFT_PIO) {
2150 mask = ap->pio_mask;
2151 if (ata_dev_present(master)) {
2152 /* spec doesn't return explicit support for
2153 * PIO0-2, so we fake it
2154 */
2155 u16 tmp_mode = master->id[ATA_ID_PIO_MODES] & 0x03;
2156 tmp_mode <<= 3;
2157 tmp_mode |= 0x7;
2158 mask &= tmp_mode;
2159 }
2160 if (ata_dev_present(slave)) {
2161 /* spec doesn't return explicit support for
2162 * PIO0-2, so we fake it
2163 */
2164 u16 tmp_mode = slave->id[ATA_ID_PIO_MODES] & 0x03;
2165 tmp_mode <<= 3;
2166 tmp_mode |= 0x7;
2167 mask &= tmp_mode;
2168 }
2169 }
2170 else {
2171 mask = 0xffffffff; /* shut up compiler warning */
2172 BUG();
2173 }
2174
2175 return mask;
2176}
2177
2178/* find greatest bit */
2179static int fgb(u32 bitmap)
2180{
2181 unsigned int i;
2182 int x = -1;
2183
2184 for (i = 0; i < 32; i++)
2185 if (bitmap & (1 << i))
2186 x = i;
2187
2188 return x;
2189}
2190
2191/**
2192 * ata_choose_xfer_mode - attempt to find best transfer mode
2193 * @ap: Port for which an xfer mode will be selected
2194 * @xfer_mode_out: (output) SET FEATURES - XFER MODE code
2195 * @xfer_shift_out: (output) bit shift that selects this mode
2196 *
0cba632b
JG		 2197 * Based on host and device capabilities, determine the
2198 * maximum transfer mode that is amenable to all.
2199 *
1da177e4 2200 * LOCKING:
0cba632b 2201 * PCI/etc. bus probe sem.
1da177e4
LT		 2202 *
2203 * RETURNS:
2204 * Zero on success, negative on error.
2205 */
2206
057ace5e 2207static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 2208 u8 *xfer_mode_out,
2209 unsigned int *xfer_shift_out)
2210{
2211 unsigned int mask, shift;
2212 int x, i;
2213
2214 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++) {
2215 shift = xfer_mode_classes[i].shift;
2216 mask = ata_get_mode_mask(ap, shift);
2217
2218 x = fgb(mask);
2219 if (x >= 0) {
2220 *xfer_mode_out = xfer_mode_classes[i].base + x;
2221 *xfer_shift_out = shift;
2222 return 0;
2223 }
2224 }
2225
2226 return -1;
2227}
2228
2229/**
2230 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
2231 * @ap: Port associated with device @dev
2232 * @dev: Device to which command will be sent
2233 *
780a87f7
JG		 2234 * Issue SET FEATURES - XFER MODE command to device @dev
2235 * on port @ap.
2236 *
1da177e4 2237 * LOCKING:
0cba632b 2238 * PCI/etc. bus probe sem.
1da177e4
LT		 2239 */
2240
2241static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
2242{
2243 DECLARE_COMPLETION(wait);
2244 struct ata_queued_cmd *qc;
2245 int rc;
2246 unsigned long flags;
2247
2248 /* set up set-features taskfile */
2249 DPRINTK("set features - xfer mode\n");
2250
2251 qc = ata_qc_new_init(ap, dev);
2252 BUG_ON(qc == NULL);
2253
2254 qc->tf.command = ATA_CMD_SET_FEATURES;
2255 qc->tf.feature = SETFEATURES_XFER;
2256 qc->tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2257 qc->tf.protocol = ATA_PROT_NODATA;
2258 qc->tf.nsect = dev->xfer_mode;
2259
2260 qc->waiting = &wait;
2261 qc->complete_fn = ata_qc_complete_noop;
2262
2263 spin_lock_irqsave(&ap->host_set->lock, flags);
2264 rc = ata_qc_issue(qc);
2265 spin_unlock_irqrestore(&ap->host_set->lock, flags);
2266
2267 if (rc)
2268 ata_port_disable(ap);
2269 else
2270 wait_for_completion(&wait);
2271
2272 DPRINTK("EXIT\n");
2273}
2274
59a10b17
AL		 2275/**
2276 * ata_dev_reread_id - Reread the device identify device info
2277 * @ap: port where the device is
2278 * @dev: device to reread the identify device info
2279 *
2280 * LOCKING:
2281 */
2282
2283static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev)
2284{
2285 DECLARE_COMPLETION(wait);
2286 struct ata_queued_cmd *qc;
2287 unsigned long flags;
2288 int rc;
2289
2290 qc = ata_qc_new_init(ap, dev);
2291 BUG_ON(qc == NULL);
2292
2293 ata_sg_init_one(qc, dev->id, sizeof(dev->id));
2294 qc->dma_dir = DMA_FROM_DEVICE;
2295
2296 if (dev->class == ATA_DEV_ATA) {
2297 qc->tf.command = ATA_CMD_ID_ATA;
2298 DPRINTK("do ATA identify\n");
2299 } else {
2300 qc->tf.command = ATA_CMD_ID_ATAPI;
2301 DPRINTK("do ATAPI identify\n");
2302 }
2303
2304 qc->tf.flags |= ATA_TFLAG_DEVICE;
2305 qc->tf.protocol = ATA_PROT_PIO;
2306 qc->nsect = 1;
2307
2308 qc->waiting = &wait;
2309 qc->complete_fn = ata_qc_complete_noop;
2310
2311 spin_lock_irqsave(&ap->host_set->lock, flags);
2312 rc = ata_qc_issue(qc);
2313 spin_unlock_irqrestore(&ap->host_set->lock, flags);
2314
2315 if (rc)
2316 goto err_out;
2317
2318 wait_for_completion(&wait);
2319
2320 swap_buf_le16(dev->id, ATA_ID_WORDS);
2321
2322 ata_dump_id(dev);
2323
2324 DPRINTK("EXIT\n");
2325
2326 return;
2327err_out:
2328 ata_port_disable(ap);
2329}
2330
8bf62ece
AL		 2331/**
2332 * ata_dev_init_params - Issue INIT DEV PARAMS command
2333 * @ap: Port associated with device @dev
2334 * @dev: Device to which command will be sent
2335 *
2336 * LOCKING:
2337 */
2338
2339static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev)
2340{
2341 DECLARE_COMPLETION(wait);
2342 struct ata_queued_cmd *qc;
2343 int rc;
2344 unsigned long flags;
2345 u16 sectors = dev->id[6];
2346 u16 heads = dev->id[3];
2347
2348 /* Number of sectors per track 1-255. Number of heads 1-16 */
2349 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
2350 return;
2351
2352 /* set up init dev params taskfile */
2353 DPRINTK("init dev params \n");
2354
2355 qc = ata_qc_new_init(ap, dev);
2356 BUG_ON(qc == NULL);
2357
2358 qc->tf.command = ATA_CMD_INIT_DEV_PARAMS;
2359 qc->tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2360 qc->tf.protocol = ATA_PROT_NODATA;
2361 qc->tf.nsect = sectors;
2362 qc->tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
2363
2364 qc->waiting = &wait;
2365 qc->complete_fn = ata_qc_complete_noop;
2366
2367 spin_lock_irqsave(&ap->host_set->lock, flags);
2368 rc = ata_qc_issue(qc);
2369 spin_unlock_irqrestore(&ap->host_set->lock, flags);
2370
2371 if (rc)
2372 ata_port_disable(ap);
2373 else
2374 wait_for_completion(&wait);
2375
2376 DPRINTK("EXIT\n");
2377}
2378
1da177e4 2379/**
0cba632b
JG		 2380 * ata_sg_clean - Unmap DMA memory associated with command
2381 * @qc: Command containing DMA memory to be released
2382 *
2383 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 2384 *
2385 * LOCKING:
0cba632b 2386 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2387 */
2388
2389static void ata_sg_clean(struct ata_queued_cmd *qc)
2390{
2391 struct ata_port *ap = qc->ap;
cedc9a47 2392 struct scatterlist *sg = qc->__sg;
1da177e4 2393 int dir = qc->dma_dir;
cedc9a47 2394 void *pad_buf = NULL;
1da177e4
LT		 2395
2396 assert(qc->flags & ATA_QCFLAG_DMAMAP);
2397 assert(sg != NULL);
2398
2399 if (qc->flags & ATA_QCFLAG_SINGLE)
2400 assert(qc->n_elem == 1);
2401
2402 DPRINTK("unmapping %u sg elements\n", qc->n_elem);
2403
cedc9a47
JG		 2404 /* if we padded the buffer out to 32-bit bound, and data
2405 * xfer direction is from-device, we must copy from the
2406 * pad buffer back into the supplied buffer
2407 */
2408 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
2409 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2410
2411 if (qc->flags & ATA_QCFLAG_SG) {
1da177e4 2412 dma_unmap_sg(ap->host_set->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 2413 /* restore last sg */
2414 sg[qc->orig_n_elem - 1].length += qc->pad_len;
2415 if (pad_buf) {
2416 struct scatterlist *psg = &qc->pad_sgent;
2417 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2418 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
2419 kunmap_atomic(psg->page, KM_IRQ0);
2420 }
2421 } else {
1da177e4
LT		 2422 dma_unmap_single(ap->host_set->dev, sg_dma_address(&sg[0]),
2423 sg_dma_len(&sg[0]), dir);
cedc9a47
JG		 2424 /* restore sg */
2425 sg->length += qc->pad_len;
2426 if (pad_buf)
2427 memcpy(qc->buf_virt + sg->length - qc->pad_len,
2428 pad_buf, qc->pad_len);
2429 }
1da177e4
LT		 2430
2431 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 2432 qc->__sg = NULL;
1da177e4
LT		 2433}
2434
2435/**
2436 * ata_fill_sg - Fill PCI IDE PRD table
2437 * @qc: Metadata associated with taskfile to be transferred
2438 *
780a87f7
JG		 2439 * Fill PCI IDE PRD (scatter-gather) table with segments
2440 * associated with the current disk command.
2441 *
1da177e4 2442 * LOCKING:
780a87f7 2443 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2444 *
2445 */
2446static void ata_fill_sg(struct ata_queued_cmd *qc)
2447{
1da177e4 2448 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2449 struct scatterlist *sg;
2450 unsigned int idx;
1da177e4 2451
cedc9a47 2452 assert(qc->__sg != NULL);
1da177e4
LT		 2453 assert(qc->n_elem > 0);
2454
2455 idx = 0;
cedc9a47 2456 ata_for_each_sg(sg, qc) {
1da177e4
LT		 2457 u32 addr, offset;
2458 u32 sg_len, len;
2459
2460 /* determine if physical DMA addr spans 64K boundary.
2461 * Note h/w doesn't support 64-bit, so we unconditionally
2462 * truncate dma_addr_t to u32.
2463 */
2464 addr = (u32) sg_dma_address(sg);
2465 sg_len = sg_dma_len(sg);
2466
2467 while (sg_len) {
2468 offset = addr & 0xffff;
2469 len = sg_len;
2470 if ((offset + sg_len) > 0x10000)
2471 len = 0x10000 - offset;
2472
2473 ap->prd[idx].addr = cpu_to_le32(addr);
2474 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2475 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
2476
2477 idx++;
2478 sg_len -= len;
2479 addr += len;
2480 }
2481 }
2482
2483 if (idx)
2484 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2485}
2486/**
2487 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
2488 * @qc: Metadata associated with taskfile to check
2489 *
780a87f7
JG		 2490 * Allow low-level driver to filter ATA PACKET commands, returning
2491 * a status indicating whether or not it is OK to use DMA for the
2492 * supplied PACKET command.
2493 *
1da177e4 2494 * LOCKING:
0cba632b
JG		 2495 * spin_lock_irqsave(host_set lock)
2496 *
1da177e4
LT		 2497 * RETURNS: 0 when ATAPI DMA can be used
2498 * nonzero otherwise
2499 */
2500int ata_check_atapi_dma(struct ata_queued_cmd *qc)
2501{
2502 struct ata_port *ap = qc->ap;
2503 int rc = 0; /* Assume ATAPI DMA is OK by default */
2504
2505 if (ap->ops->check_atapi_dma)
2506 rc = ap->ops->check_atapi_dma(qc);
2507
2508 return rc;
2509}
2510/**
2511 * ata_qc_prep - Prepare taskfile for submission
2512 * @qc: Metadata associated with taskfile to be prepared
2513 *
780a87f7
JG		 2514 * Prepare ATA taskfile for submission.
2515 *
1da177e4
LT		 2516 * LOCKING:
2517 * spin_lock_irqsave(host_set lock)
2518 */
2519void ata_qc_prep(struct ata_queued_cmd *qc)
2520{
2521 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2522 return;
2523
2524 ata_fill_sg(qc);
2525}
2526
0cba632b
JG		 2527/**
2528 * ata_sg_init_one - Associate command with memory buffer
2529 * @qc: Command to be associated
2530 * @buf: Memory buffer
2531 * @buflen: Length of memory buffer, in bytes.
2532 *
2533 * Initialize the data-related elements of queued_cmd @qc
2534 * to point to a single memory buffer, @buf of byte length @buflen.
2535 *
2536 * LOCKING:
2537 * spin_lock_irqsave(host_set lock)
2538 */
2539
1da177e4
LT		 2540void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
2541{
2542 struct scatterlist *sg;
2543
2544 qc->flags |= ATA_QCFLAG_SINGLE;
2545
2546 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 2547 qc->__sg = &qc->sgent;
1da177e4 2548 qc->n_elem = 1;
cedc9a47 2549 qc->orig_n_elem = 1;
1da177e4
LT		 2550 qc->buf_virt = buf;
2551
cedc9a47 2552 sg = qc->__sg;
f0612bbc 2553 sg_init_one(sg, buf, buflen);
1da177e4
LT		 2554}
2555
0cba632b
JG		 2556/**
2557 * ata_sg_init - Associate command with scatter-gather table.
2558 * @qc: Command to be associated
2559 * @sg: Scatter-gather table.
2560 * @n_elem: Number of elements in s/g table.
2561 *
2562 * Initialize the data-related elements of queued_cmd @qc
2563 * to point to a scatter-gather table @sg, containing @n_elem
2564 * elements.
2565 *
2566 * LOCKING:
2567 * spin_lock_irqsave(host_set lock)
2568 */
2569
1da177e4
LT		 2570void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
2571 unsigned int n_elem)
2572{
2573 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 2574 qc->__sg = sg;
1da177e4 2575 qc->n_elem = n_elem;
cedc9a47 2576 qc->orig_n_elem = n_elem;
1da177e4
LT		 2577}
2578
2579/**
0cba632b
JG		 2580 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
2581 * @qc: Command with memory buffer to be mapped.
2582 *
2583 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 2584 *
2585 * LOCKING:
2586 * spin_lock_irqsave(host_set lock)
2587 *
2588 * RETURNS:
0cba632b 2589 * Zero on success, negative on error.
1da177e4
LT		 2590 */
2591
2592static int ata_sg_setup_one(struct ata_queued_cmd *qc)
2593{
2594 struct ata_port *ap = qc->ap;
2595 int dir = qc->dma_dir;
cedc9a47 2596 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 2597 dma_addr_t dma_address;
2598
cedc9a47
JG		 2599 /* we must lengthen transfers to end on a 32-bit boundary */
2600 qc->pad_len = sg->length & 3;
2601 if (qc->pad_len) {
2602 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2603 struct scatterlist *psg = &qc->pad_sgent;
2604
2605 assert(qc->dev->class == ATA_DEV_ATAPI);
2606
2607 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2608
2609 if (qc->tf.flags & ATA_TFLAG_WRITE)
2610 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
2611 qc->pad_len);
2612
2613 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2614 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2615 /* trim sg */
2616 sg->length -= qc->pad_len;
2617
2618 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
2619 sg->length, qc->pad_len);
2620 }
2621
1da177e4 2622 dma_address = dma_map_single(ap->host_set->dev, qc->buf_virt,
32529e01 2623 sg->length, dir);
537a95d9
TH		 2624 if (dma_mapping_error(dma_address)) {
2625 /* restore sg */
2626 sg->length += qc->pad_len;
1da177e4 2627 return -1;
537a95d9 2628 }
1da177e4
LT		 2629
2630 sg_dma_address(sg) = dma_address;
32529e01 2631 sg_dma_len(sg) = sg->length;
1da177e4
LT		 2632
2633 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
2634 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
2635
2636 return 0;
2637}
2638
2639/**
0cba632b
JG		 2640 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
2641 * @qc: Command with scatter-gather table to be mapped.
2642 *
2643 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 2644 *
2645 * LOCKING:
2646 * spin_lock_irqsave(host_set lock)
2647 *
2648 * RETURNS:
0cba632b 2649 * Zero on success, negative on error.
1da177e4
LT		 2650 *
2651 */
2652
2653static int ata_sg_setup(struct ata_queued_cmd *qc)
2654{
2655 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2656 struct scatterlist *sg = qc->__sg;
2657 struct scatterlist *lsg = &sg[qc->n_elem - 1];
1da177e4
LT		 2658 int n_elem, dir;
2659
2660 VPRINTK("ENTER, ata%u\n", ap->id);
2661 assert(qc->flags & ATA_QCFLAG_SG);
2662
cedc9a47
JG		 2663 /* we must lengthen transfers to end on a 32-bit boundary */
2664 qc->pad_len = lsg->length & 3;
2665 if (qc->pad_len) {
2666 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2667 struct scatterlist *psg = &qc->pad_sgent;
2668 unsigned int offset;
2669
2670 assert(qc->dev->class == ATA_DEV_ATAPI);
2671
2672 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2673
2674 /*
2675 * psg->page/offset are used to copy to-be-written
2676 * data in this function or read data in ata_sg_clean.
2677 */
2678 offset = lsg->offset + lsg->length - qc->pad_len;
2679 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
2680 psg->offset = offset_in_page(offset);
2681
2682 if (qc->tf.flags & ATA_TFLAG_WRITE) {
2683 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2684 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
2685 kunmap_atomic(psg->page, KM_IRQ0);
2686 }
2687
2688 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2689 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2690 /* trim last sg */
2691 lsg->length -= qc->pad_len;
2692
2693 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
2694 qc->n_elem - 1, lsg->length, qc->pad_len);
2695 }
2696
1da177e4
LT		 2697 dir = qc->dma_dir;
2698 n_elem = dma_map_sg(ap->host_set->dev, sg, qc->n_elem, dir);
537a95d9
TH		 2699 if (n_elem < 1) {
2700 /* restore last sg */
2701 lsg->length += qc->pad_len;
1da177e4 2702 return -1;
537a95d9 2703 }
1da177e4
LT		 2704
2705 DPRINTK("%d sg elements mapped\n", n_elem);
2706
2707 qc->n_elem = n_elem;
2708
2709 return 0;
2710}
2711
40e8c82c
TH		 2712/**
2713 * ata_poll_qc_complete - turn irq back on and finish qc
2714 * @qc: Command to complete
8e8b77dd 2715 * @err_mask: ATA status register content
40e8c82c
TH		 2716 *
2717 * LOCKING:
2718 * None. (grabs host lock)
2719 */
2720
a7dac447 2721void ata_poll_qc_complete(struct ata_queued_cmd *qc, unsigned int err_mask)
40e8c82c
TH		 2722{
2723 struct ata_port *ap = qc->ap;
b8f6153e 2724 unsigned long flags;
40e8c82c 2725
b8f6153e 2726 spin_lock_irqsave(&ap->host_set->lock, flags);
40e8c82c
TH		 2727 ap->flags &= ~ATA_FLAG_NOINTR;
2728 ata_irq_on(ap);
a7dac447 2729 ata_qc_complete(qc, err_mask);
b8f6153e 2730 spin_unlock_irqrestore(&ap->host_set->lock, flags);
40e8c82c
TH		 2731}
2732
1da177e4
LT		 2733/**
2734 * ata_pio_poll -
6f0ef4fa 2735 * @ap: the target ata_port
1da177e4
LT		 2736 *
2737 * LOCKING:
0cba632b 2738 * None. (executing in kernel thread context)
1da177e4
LT		 2739 *
2740 * RETURNS:
6f0ef4fa 2741 * timeout value to use
1da177e4
LT		 2742 */
2743
2744static unsigned long ata_pio_poll(struct ata_port *ap)
2745{
2746 u8 status;
14be71f4
AL		 2747 unsigned int poll_state = HSM_ST_UNKNOWN;
2748 unsigned int reg_state = HSM_ST_UNKNOWN;
14be71f4
AL		 2749
2750 switch (ap->hsm_task_state) {
2751 case HSM_ST:
2752 case HSM_ST_POLL:
2753 poll_state = HSM_ST_POLL;
2754 reg_state = HSM_ST;
1da177e4 2755 break;
14be71f4
AL		 2756 case HSM_ST_LAST:
2757 case HSM_ST_LAST_POLL:
2758 poll_state = HSM_ST_LAST_POLL;
2759 reg_state = HSM_ST_LAST;
1da177e4
LT		 2760 break;
2761 default:
2762 BUG();
2763 break;
2764 }
2765
2766 status = ata_chk_status(ap);
2767 if (status & ATA_BUSY) {
2768 if (time_after(jiffies, ap->pio_task_timeout)) {
7c398335 2769 ap->hsm_task_state = HSM_ST_TMOUT;
1da177e4
LT		 2770 return 0;
2771 }
14be71f4 2772 ap->hsm_task_state = poll_state;
1da177e4
LT		 2773 return ATA_SHORT_PAUSE;
2774 }
2775
14be71f4 2776 ap->hsm_task_state = reg_state;
1da177e4
LT		 2777 return 0;
2778}
2779
2780/**
6f0ef4fa
RD		 2781 * ata_pio_complete - check if drive is busy or idle
2782 * @ap: the target ata_port
1da177e4
LT		 2783 *
2784 * LOCKING:
0cba632b 2785 * None. (executing in kernel thread context)
7fb6ec28
JG		 2786 *
2787 * RETURNS:
2788 * Non-zero if qc completed, zero otherwise.
1da177e4
LT		 2789 */
2790
7fb6ec28 2791static int ata_pio_complete (struct ata_port *ap)
1da177e4
LT		 2792{
2793 struct ata_queued_cmd *qc;
2794 u8 drv_stat;
2795
2796 /*
31433ea3
AC		 2797 * This is purely heuristic. This is a fast path. Sometimes when
2798 * we enter, BSY will be cleared in a chk-status or two. If not,
2799 * the drive is probably seeking or something. Snooze for a couple
2800 * msecs, then chk-status again. If still busy, fall back to
14be71f4 2801 * HSM_ST_POLL state.
1da177e4
LT		 2802 */
2803 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 10);
2804 if (drv_stat & (ATA_BUSY | ATA_DRQ)) {
2805 msleep(2);
2806 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 10);
2807 if (drv_stat & (ATA_BUSY | ATA_DRQ)) {
14be71f4 2808 ap->hsm_task_state = HSM_ST_LAST_POLL;
1da177e4 2809 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
7fb6ec28 2810 return 0;
1da177e4
LT		 2811 }
2812 }
2813
2814 drv_stat = ata_wait_idle(ap);
2815 if (!ata_ok(drv_stat)) {
14be71f4 2816 ap->hsm_task_state = HSM_ST_ERR;
7fb6ec28 2817 return 0;
1da177e4
LT		 2818 }
2819
2820 qc = ata_qc_from_tag(ap, ap->active_tag);
2821 assert(qc != NULL);
2822
14be71f4 2823 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 2824
a7dac447 2825 ata_poll_qc_complete(qc, 0);
7fb6ec28
JG		 2826
2827 /* another command may start at this point */
2828
2829 return 1;
1da177e4
LT		 2830}
2831
0baab86b
EF		 2832
2833/**
6f0ef4fa 2834 * swap_buf_le16 - swap halves of 16-words in place
0baab86b
EF		 2835 * @buf: Buffer to swap
2836 * @buf_words: Number of 16-bit words in buffer.
2837 *
2838 * Swap halves of 16-bit words if needed to convert from
2839 * little-endian byte order to native cpu byte order, or
2840 * vice-versa.
2841 *
2842 * LOCKING:
6f0ef4fa 2843 * Inherited from caller.
0baab86b 2844 */
1da177e4
LT		 2845void swap_buf_le16(u16 *buf, unsigned int buf_words)
2846{
2847#ifdef __BIG_ENDIAN
2848 unsigned int i;
2849
2850 for (i = 0; i < buf_words; i++)
2851 buf[i] = le16_to_cpu(buf[i]);
2852#endif /* __BIG_ENDIAN */
2853}
2854
6ae4cfb5
AL		 2855/**
2856 * ata_mmio_data_xfer - Transfer data by MMIO
2857 * @ap: port to read/write
2858 * @buf: data buffer
2859 * @buflen: buffer length
344babaa 2860 * @write_data: read/write
6ae4cfb5
AL		 2861 *
2862 * Transfer data from/to the device data register by MMIO.
2863 *
2864 * LOCKING:
2865 * Inherited from caller.
6ae4cfb5
AL		 2866 */
2867
1da177e4
LT		 2868static void ata_mmio_data_xfer(struct ata_port *ap, unsigned char *buf,
2869 unsigned int buflen, int write_data)
2870{
2871 unsigned int i;
2872 unsigned int words = buflen >> 1;
2873 u16 *buf16 = (u16 *) buf;
2874 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
2875
6ae4cfb5 2876 /* Transfer multiple of 2 bytes */
1da177e4
LT		 2877 if (write_data) {
2878 for (i = 0; i < words; i++)
2879 writew(le16_to_cpu(buf16[i]), mmio);
2880 } else {
2881 for (i = 0; i < words; i++)
2882 buf16[i] = cpu_to_le16(readw(mmio));
2883 }
6ae4cfb5
AL		 2884
2885 /* Transfer trailing 1 byte, if any. */
2886 if (unlikely(buflen & 0x01)) {
2887 u16 align_buf[1] = { 0 };
2888 unsigned char *trailing_buf = buf + buflen - 1;
2889
2890 if (write_data) {
2891 memcpy(align_buf, trailing_buf, 1);
2892 writew(le16_to_cpu(align_buf[0]), mmio);
2893 } else {
2894 align_buf[0] = cpu_to_le16(readw(mmio));
2895 memcpy(trailing_buf, align_buf, 1);
2896 }
2897 }
1da177e4
LT		 2898}
2899
6ae4cfb5
AL		 2900/**
2901 * ata_pio_data_xfer - Transfer data by PIO
2902 * @ap: port to read/write
2903 * @buf: data buffer
2904 * @buflen: buffer length
344babaa 2905 * @write_data: read/write
6ae4cfb5
AL		 2906 *
2907 * Transfer data from/to the device data register by PIO.
2908 *
2909 * LOCKING:
2910 * Inherited from caller.
6ae4cfb5
AL		 2911 */
2912
1da177e4
LT		 2913static void ata_pio_data_xfer(struct ata_port *ap, unsigned char *buf,
2914 unsigned int buflen, int write_data)
2915{
6ae4cfb5 2916 unsigned int words = buflen >> 1;
1da177e4 2917
6ae4cfb5 2918 /* Transfer multiple of 2 bytes */
1da177e4 2919 if (write_data)
6ae4cfb5 2920 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 2921 else
6ae4cfb5
AL		 2922 insw(ap->ioaddr.data_addr, buf, words);
2923
2924 /* Transfer trailing 1 byte, if any. */
2925 if (unlikely(buflen & 0x01)) {
2926 u16 align_buf[1] = { 0 };
2927 unsigned char *trailing_buf = buf + buflen - 1;
2928
2929 if (write_data) {
2930 memcpy(align_buf, trailing_buf, 1);
2931 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
2932 } else {
2933 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
2934 memcpy(trailing_buf, align_buf, 1);
2935 }
2936 }
1da177e4
LT		 2937}
2938
6ae4cfb5
AL		 2939/**
2940 * ata_data_xfer - Transfer data from/to the data register.
2941 * @ap: port to read/write
2942 * @buf: data buffer
2943 * @buflen: buffer length
2944 * @do_write: read/write
2945 *
2946 * Transfer data from/to the device data register.
2947 *
2948 * LOCKING:
2949 * Inherited from caller.
6ae4cfb5
AL		 2950 */
2951
1da177e4
LT		 2952static void ata_data_xfer(struct ata_port *ap, unsigned char *buf,
2953 unsigned int buflen, int do_write)
2954{
2955 if (ap->flags & ATA_FLAG_MMIO)
2956 ata_mmio_data_xfer(ap, buf, buflen, do_write);
2957 else
2958 ata_pio_data_xfer(ap, buf, buflen, do_write);
2959}
2960
6ae4cfb5
AL		 2961/**
2962 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
2963 * @qc: Command on going
2964 *
2965 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
2966 *
2967 * LOCKING:
2968 * Inherited from caller.
2969 */
2970
1da177e4
LT		 2971static void ata_pio_sector(struct ata_queued_cmd *qc)
2972{
2973 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 2974 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 2975 struct ata_port *ap = qc->ap;
2976 struct page *page;
2977 unsigned int offset;
2978 unsigned char *buf;
2979
2980 if (qc->cursect == (qc->nsect - 1))
14be71f4 2981 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 2982
2983 page = sg[qc->cursg].page;
2984 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
2985
2986 /* get the current page and offset */
2987 page = nth_page(page, (offset >> PAGE_SHIFT));
2988 offset %= PAGE_SIZE;
2989
2990 buf = kmap(page) + offset;
2991
2992 qc->cursect++;
2993 qc->cursg_ofs++;
2994
32529e01 2995 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT		 2996 qc->cursg++;
2997 qc->cursg_ofs = 0;
2998 }
2999
3000 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3001
3002 /* do the actual data transfer */
3003 do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
3004 ata_data_xfer(ap, buf, ATA_SECT_SIZE, do_write);
3005
3006 kunmap(page);
3007}
3008
6ae4cfb5
AL		 3009/**
3010 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3011 * @qc: Command on going
3012 * @bytes: number of bytes
3013 *
3014 * Transfer Transfer data from/to the ATAPI device.
3015 *
3016 * LOCKING:
3017 * Inherited from caller.
3018 *
3019 */
3020
1da177e4
LT		 3021static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3022{
3023 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3024 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3025 struct ata_port *ap = qc->ap;
3026 struct page *page;
3027 unsigned char *buf;
3028 unsigned int offset, count;
3029
563a6e1f 3030 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3031 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3032
3033next_sg:
563a6e1f 3034 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3035 /*
563a6e1f
AL		 3036 * The end of qc->sg is reached and the device expects
3037 * more data to transfer. In order not to overrun qc->sg
3038 * and fulfill length specified in the byte count register,
3039 * - for read case, discard trailing data from the device
3040 * - for write case, padding zero data to the device
3041 */
3042 u16 pad_buf[1] = { 0 };
3043 unsigned int words = bytes >> 1;
3044 unsigned int i;
3045
3046 if (words) /* warning if bytes > 1 */
7fb6ec28 3047 printk(KERN_WARNING "ata%u: %u bytes trailing data\n",
563a6e1f
AL		 3048 ap->id, bytes);
3049
3050 for (i = 0; i < words; i++)
3051 ata_data_xfer(ap, (unsigned char*)pad_buf, 2, do_write);
3052
14be71f4 3053 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3054 return;
3055 }
3056
cedc9a47 3057 sg = &qc->__sg[qc->cursg];
1da177e4 3058
1da177e4
LT		 3059 page = sg->page;
3060 offset = sg->offset + qc->cursg_ofs;
3061
3062 /* get the current page and offset */
3063 page = nth_page(page, (offset >> PAGE_SHIFT));
3064 offset %= PAGE_SIZE;
3065
6952df03 3066 /* don't overrun current sg */
32529e01 3067 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3068
3069 /* don't cross page boundaries */
3070 count = min(count, (unsigned int)PAGE_SIZE - offset);
3071
3072 buf = kmap(page) + offset;
3073
3074 bytes -= count;
3075 qc->curbytes += count;
3076 qc->cursg_ofs += count;
3077
32529e01 3078 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 3079 qc->cursg++;
3080 qc->cursg_ofs = 0;
3081 }
3082
3083 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3084
3085 /* do the actual data transfer */
3086 ata_data_xfer(ap, buf, count, do_write);
3087
3088 kunmap(page);
3089
563a6e1f 3090 if (bytes)
1da177e4 3091 goto next_sg;
1da177e4
LT		 3092}
3093
6ae4cfb5
AL		 3094/**
3095 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3096 * @qc: Command on going
3097 *
3098 * Transfer Transfer data from/to the ATAPI device.
3099 *
3100 * LOCKING:
3101 * Inherited from caller.
6ae4cfb5
AL		 3102 */
3103
1da177e4
LT		 3104static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3105{
3106 struct ata_port *ap = qc->ap;
3107 struct ata_device *dev = qc->dev;
3108 unsigned int ireason, bc_lo, bc_hi, bytes;
3109 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3110
3111 ap->ops->tf_read(ap, &qc->tf);
3112 ireason = qc->tf.nsect;
3113 bc_lo = qc->tf.lbam;
3114 bc_hi = qc->tf.lbah;
3115 bytes = (bc_hi << 8) | bc_lo;
3116
3117 /* shall be cleared to zero, indicating xfer of data */
3118 if (ireason & (1 << 0))
3119 goto err_out;
3120
3121 /* make sure transfer direction matches expected */
3122 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3123 if (do_write != i_write)
3124 goto err_out;
3125
3126 __atapi_pio_bytes(qc, bytes);
3127
3128 return;
3129
3130err_out:
3131 printk(KERN_INFO "ata%u: dev %u: ATAPI check failed\n",
3132 ap->id, dev->devno);
14be71f4 3133 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3134}
3135
3136/**
6f0ef4fa
RD		 3137 * ata_pio_block - start PIO on a block
3138 * @ap: the target ata_port
1da177e4
LT		 3139 *
3140 * LOCKING:
0cba632b 3141 * None. (executing in kernel thread context)
1da177e4
LT		 3142 */
3143
3144static void ata_pio_block(struct ata_port *ap)
3145{
3146 struct ata_queued_cmd *qc;
3147 u8 status;
3148
3149 /*
6f0ef4fa 3150 * This is purely heuristic. This is a fast path.
1da177e4
LT		 3151 * Sometimes when we enter, BSY will be cleared in
3152 * a chk-status or two. If not, the drive is probably seeking
3153 * or something. Snooze for a couple msecs, then
3154 * chk-status again. If still busy, fall back to
14be71f4 3155 * HSM_ST_POLL state.
1da177e4
LT		 3156 */
3157 status = ata_busy_wait(ap, ATA_BUSY, 5);
3158 if (status & ATA_BUSY) {
3159 msleep(2);
3160 status = ata_busy_wait(ap, ATA_BUSY, 10);
3161 if (status & ATA_BUSY) {
14be71f4 3162 ap->hsm_task_state = HSM_ST_POLL;
1da177e4
LT		 3163 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
3164 return;
3165 }
3166 }
3167
3168 qc = ata_qc_from_tag(ap, ap->active_tag);
3169 assert(qc != NULL);
3170
3171 if (is_atapi_taskfile(&qc->tf)) {
3172 /* no more data to transfer or unsupported ATAPI command */
3173 if ((status & ATA_DRQ) == 0) {
14be71f4 3174 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3175 return;
3176 }
3177
3178 atapi_pio_bytes(qc);
3179 } else {
3180 /* handle BSY=0, DRQ=0 as error */
3181 if ((status & ATA_DRQ) == 0) {
14be71f4 3182 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3183 return;
3184 }
3185
3186 ata_pio_sector(qc);
3187 }
3188}
3189
3190static void ata_pio_error(struct ata_port *ap)
3191{
3192 struct ata_queued_cmd *qc;
a7dac447
JG		 3193
3194 printk(KERN_WARNING "ata%u: PIO error\n", ap->id);
1da177e4
LT		 3195
3196 qc = ata_qc_from_tag(ap, ap->active_tag);
3197 assert(qc != NULL);
3198
14be71f4 3199 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3200
a7dac447 3201 ata_poll_qc_complete(qc, AC_ERR_ATA_BUS);
1da177e4
LT		 3202}
3203
3204static void ata_pio_task(void *_data)
3205{
3206 struct ata_port *ap = _data;
7fb6ec28
JG		 3207 unsigned long timeout;
3208 int qc_completed;
3209
3210fsm_start:
3211 timeout = 0;
3212 qc_completed = 0;
1da177e4 3213
14be71f4
AL		 3214 switch (ap->hsm_task_state) {
3215 case HSM_ST_IDLE:
1da177e4
LT		 3216 return;
3217
14be71f4 3218 case HSM_ST:
1da177e4
LT		 3219 ata_pio_block(ap);
3220 break;
3221
14be71f4 3222 case HSM_ST_LAST:
7fb6ec28 3223 qc_completed = ata_pio_complete(ap);
1da177e4
LT		 3224 break;
3225
14be71f4
AL		 3226 case HSM_ST_POLL:
3227 case HSM_ST_LAST_POLL:
1da177e4
LT		 3228 timeout = ata_pio_poll(ap);
3229 break;
3230
14be71f4
AL		 3231 case HSM_ST_TMOUT:
3232 case HSM_ST_ERR:
1da177e4
LT		 3233 ata_pio_error(ap);
3234 return;
3235 }
3236
3237 if (timeout)
7fb6ec28
JG		 3238 queue_delayed_work(ata_wq, &ap->pio_task, timeout);
3239 else if (!qc_completed)
3240 goto fsm_start;
1da177e4
LT		 3241}
3242
1da177e4
LT		 3243/**
3244 * ata_qc_timeout - Handle timeout of queued command
3245 * @qc: Command that timed out
3246 *
3247 * Some part of the kernel (currently, only the SCSI layer)
3248 * has noticed that the active command on port @ap has not
3249 * completed after a specified length of time. Handle this
3250 * condition by disabling DMA (if necessary) and completing
3251 * transactions, with error if necessary.
3252 *
3253 * This also handles the case of the "lost interrupt", where
3254 * for some reason (possibly hardware bug, possibly driver bug)
3255 * an interrupt was not delivered to the driver, even though the
3256 * transaction completed successfully.
3257 *
3258 * LOCKING:
0cba632b 3259 * Inherited from SCSI layer (none, can sleep)
1da177e4
LT		 3260 */
3261
3262static void ata_qc_timeout(struct ata_queued_cmd *qc)
3263{
3264 struct ata_port *ap = qc->ap;
b8f6153e 3265 struct ata_host_set *host_set = ap->host_set;
1da177e4
LT		 3266 struct ata_device *dev = qc->dev;
3267 u8 host_stat = 0, drv_stat;
b8f6153e 3268 unsigned long flags;
1da177e4
LT		 3269
3270 DPRINTK("ENTER\n");
3271
3272 /* FIXME: doesn't this conflict with timeout handling? */
3273 if (qc->dev->class == ATA_DEV_ATAPI && qc->scsicmd) {
3274 struct scsi_cmnd *cmd = qc->scsicmd;
3275
3111b0d1 3276 if (!(cmd->eh_eflags & SCSI_EH_CANCEL_CMD)) {
1da177e4
LT		 3277
3278 /* finish completing original command */
b8f6153e 3279 spin_lock_irqsave(&host_set->lock, flags);
1da177e4 3280 __ata_qc_complete(qc);
b8f6153e 3281 spin_unlock_irqrestore(&host_set->lock, flags);
1da177e4
LT		 3282
3283 atapi_request_sense(ap, dev, cmd);
3284
3285 cmd->result = (CHECK_CONDITION << 1) | (DID_OK << 16);
3286 scsi_finish_command(cmd);
3287
3288 goto out;
3289 }
3290 }
3291
b8f6153e
JG		 3292 spin_lock_irqsave(&host_set->lock, flags);
3293
1da177e4
LT		 3294 /* hack alert! We cannot use the supplied completion
3295 * function from inside the ->eh_strategy_handler() thread.
3296 * libata is the only user of ->eh_strategy_handler() in
3297 * any kernel, so the default scsi_done() assumes it is
3298 * not being called from the SCSI EH.
3299 */
3300 qc->scsidone = scsi_finish_command;
3301
3302 switch (qc->tf.protocol) {
3303
3304 case ATA_PROT_DMA:
3305 case ATA_PROT_ATAPI_DMA:
3306 host_stat = ap->ops->bmdma_status(ap);
3307
3308 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3309 ap->ops->bmdma_stop(qc);
1da177e4
LT		 3310
3311 /* fall through */
3312
3313 default:
3314 ata_altstatus(ap);
3315 drv_stat = ata_chk_status(ap);
3316
3317 /* ack bmdma irq events */
3318 ap->ops->irq_clear(ap);
3319
3320 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x host_stat 0x%x\n",
3321 ap->id, qc->tf.command, drv_stat, host_stat);
3322
3323 /* complete taskfile transaction */
a7dac447 3324 ata_qc_complete(qc, ac_err_mask(drv_stat));
1da177e4
LT		 3325 break;
3326 }
b8f6153e
JG		 3327
3328 spin_unlock_irqrestore(&host_set->lock, flags);
3329
1da177e4
LT		 3330out:
3331 DPRINTK("EXIT\n");
3332}
3333
3334/**
3335 * ata_eng_timeout - Handle timeout of queued command
3336 * @ap: Port on which timed-out command is active
3337 *
3338 * Some part of the kernel (currently, only the SCSI layer)
3339 * has noticed that the active command on port @ap has not
3340 * completed after a specified length of time. Handle this
3341 * condition by disabling DMA (if necessary) and completing
3342 * transactions, with error if necessary.
3343 *
3344 * This also handles the case of the "lost interrupt", where
3345 * for some reason (possibly hardware bug, possibly driver bug)
3346 * an interrupt was not delivered to the driver, even though the
3347 * transaction completed successfully.
3348 *
3349 * LOCKING:
3350 * Inherited from SCSI layer (none, can sleep)
3351 */
3352
3353void ata_eng_timeout(struct ata_port *ap)
3354{
3355 struct ata_queued_cmd *qc;
3356
3357 DPRINTK("ENTER\n");
3358
3359 qc = ata_qc_from_tag(ap, ap->active_tag);
e12669e7
JG		 3360 if (qc)
3361 ata_qc_timeout(qc);
3362 else {
1da177e4
LT		 3363 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
3364 ap->id);
3365 goto out;
3366 }
3367
1da177e4
LT		 3368out:
3369 DPRINTK("EXIT\n");
3370}
3371
3372/**
3373 * ata_qc_new - Request an available ATA command, for queueing
3374 * @ap: Port associated with device @dev
3375 * @dev: Device from whom we request an available command structure
3376 *
3377 * LOCKING:
0cba632b 3378 * None.
1da177e4
LT		 3379 */
3380
3381static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
3382{
3383 struct ata_queued_cmd *qc = NULL;
3384 unsigned int i;
3385
3386 for (i = 0; i < ATA_MAX_QUEUE; i++)
3387 if (!test_and_set_bit(i, &ap->qactive)) {
3388 qc = ata_qc_from_tag(ap, i);
3389 break;
3390 }
3391
3392 if (qc)
3393 qc->tag = i;
3394
3395 return qc;
3396}
3397
3398/**
3399 * ata_qc_new_init - Request an available ATA command, and initialize it
3400 * @ap: Port associated with device @dev
3401 * @dev: Device from whom we request an available command structure
3402 *
3403 * LOCKING:
0cba632b 3404 * None.
1da177e4
LT		 3405 */
3406
3407struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap,
3408 struct ata_device *dev)
3409{
3410 struct ata_queued_cmd *qc;
3411
3412 qc = ata_qc_new(ap);
3413 if (qc) {
cedc9a47 3414 qc->__sg = NULL;
1da177e4
LT		 3415 qc->flags = 0;
3416 qc->scsicmd = NULL;
3417 qc->ap = ap;
3418 qc->dev = dev;
3419 qc->cursect = qc->cursg = qc->cursg_ofs = 0;
3420 qc->nsect = 0;
3421 qc->nbytes = qc->curbytes = 0;
3422
3423 ata_tf_init(ap, &qc->tf, dev->devno);
1da177e4
LT		 3424 }
3425
3426 return qc;
3427}
3428
a7dac447 3429int ata_qc_complete_noop(struct ata_queued_cmd *qc, unsigned int err_mask)
1da177e4
LT		 3430{
3431 return 0;
3432}
3433
3434static void __ata_qc_complete(struct ata_queued_cmd *qc)
3435{
3436 struct ata_port *ap = qc->ap;
3437 unsigned int tag, do_clear = 0;
3438
3439 qc->flags = 0;
3440 tag = qc->tag;
3441 if (likely(ata_tag_valid(tag))) {
3442 if (tag == ap->active_tag)
3443 ap->active_tag = ATA_TAG_POISON;
3444 qc->tag = ATA_TAG_POISON;
3445 do_clear = 1;
3446 }
3447
3448 if (qc->waiting) {
3449 struct completion *waiting = qc->waiting;
3450 qc->waiting = NULL;
3451 complete(waiting);
3452 }
3453
3454 if (likely(do_clear))
3455 clear_bit(tag, &ap->qactive);
3456}
3457
3458/**
3459 * ata_qc_free - free unused ata_queued_cmd
3460 * @qc: Command to complete
3461 *
3462 * Designed to free unused ata_queued_cmd object
3463 * in case something prevents using it.
3464 *
3465 * LOCKING:
0cba632b 3466 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3467 */
3468void ata_qc_free(struct ata_queued_cmd *qc)
3469{
3470 assert(qc != NULL); /* ata_qc_from_tag _might_ return NULL */
3471 assert(qc->waiting == NULL); /* nothing should be waiting */
3472
3473 __ata_qc_complete(qc);
3474}
3475
3476/**
3477 * ata_qc_complete - Complete an active ATA command
3478 * @qc: Command to complete
8e8b77dd 3479 * @err_mask: ATA Status register contents
0cba632b
JG		 3480 *
3481 * Indicate to the mid and upper layers that an ATA
3482 * command has completed, with either an ok or not-ok status.
1da177e4
LT		 3483 *
3484 * LOCKING:
0cba632b 3485 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3486 */
3487
a7dac447 3488void ata_qc_complete(struct ata_queued_cmd *qc, unsigned int err_mask)
1da177e4
LT		 3489{
3490 int rc;
3491
3492 assert(qc != NULL); /* ata_qc_from_tag _might_ return NULL */
3493 assert(qc->flags & ATA_QCFLAG_ACTIVE);
3494
3495 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
3496 ata_sg_clean(qc);
3497
3f3791d3
AL		 3498 /* atapi: mark qc as inactive to prevent the interrupt handler
3499 * from completing the command twice later, before the error handler
3500 * is called. (when rc != 0 and atapi request sense is needed)
3501 */
3502 qc->flags &= ~ATA_QCFLAG_ACTIVE;
3503
1da177e4 3504 /* call completion callback */
a7dac447 3505 rc = qc->complete_fn(qc, err_mask);
1da177e4
LT		 3506
3507 /* if callback indicates not to complete command (non-zero),
3508 * return immediately
3509 */
3510 if (rc != 0)
3511 return;
3512
3513 __ata_qc_complete(qc);
3514
3515 VPRINTK("EXIT\n");
3516}
3517
3518static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
3519{
3520 struct ata_port *ap = qc->ap;
3521
3522 switch (qc->tf.protocol) {
3523 case ATA_PROT_DMA:
3524 case ATA_PROT_ATAPI_DMA:
3525 return 1;
3526
3527 case ATA_PROT_ATAPI:
3528 case ATA_PROT_PIO:
3529 case ATA_PROT_PIO_MULT:
3530 if (ap->flags & ATA_FLAG_PIO_DMA)
3531 return 1;
3532
3533 /* fall through */
3534
3535 default:
3536 return 0;
3537 }
3538
3539 /* never reached */
3540}
3541
3542/**
3543 * ata_qc_issue - issue taskfile to device
3544 * @qc: command to issue to device
3545 *
3546 * Prepare an ATA command to submission to device.
3547 * This includes mapping the data into a DMA-able
3548 * area, filling in the S/G table, and finally
3549 * writing the taskfile to hardware, starting the command.
3550 *
3551 * LOCKING:
3552 * spin_lock_irqsave(host_set lock)
3553 *
3554 * RETURNS:
3555 * Zero on success, negative on error.
3556 */
3557
3558int ata_qc_issue(struct ata_queued_cmd *qc)
3559{
3560 struct ata_port *ap = qc->ap;
3561
3562 if (ata_should_dma_map(qc)) {
3563 if (qc->flags & ATA_QCFLAG_SG) {
3564 if (ata_sg_setup(qc))
3565 goto err_out;
3566 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
3567 if (ata_sg_setup_one(qc))
3568 goto err_out;
3569 }
3570 } else {
3571 qc->flags &= ~ATA_QCFLAG_DMAMAP;
3572 }
3573
3574 ap->ops->qc_prep(qc);
3575
3576 qc->ap->active_tag = qc->tag;
3577 qc->flags |= ATA_QCFLAG_ACTIVE;
3578
3579 return ap->ops->qc_issue(qc);
3580
3581err_out:
3582 return -1;
3583}
3584
0baab86b 3585
1da177e4
LT		 3586/**
3587 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
3588 * @qc: command to issue to device
3589 *
3590 * Using various libata functions and hooks, this function
3591 * starts an ATA command. ATA commands are grouped into
3592 * classes called "protocols", and issuing each type of protocol
3593 * is slightly different.
3594 *
0baab86b
EF		 3595 * May be used as the qc_issue() entry in ata_port_operations.
3596 *
1da177e4
LT		 3597 * LOCKING:
3598 * spin_lock_irqsave(host_set lock)
3599 *
3600 * RETURNS:
3601 * Zero on success, negative on error.
3602 */
3603
3604int ata_qc_issue_prot(struct ata_queued_cmd *qc)
3605{
3606 struct ata_port *ap = qc->ap;
3607
3608 ata_dev_select(ap, qc->dev->devno, 1, 0);
3609
3610 switch (qc->tf.protocol) {
3611 case ATA_PROT_NODATA:
e5338254 3612 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3613 break;
3614
3615 case ATA_PROT_DMA:
3616 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3617 ap->ops->bmdma_setup(qc); /* set up bmdma */
3618 ap->ops->bmdma_start(qc); /* initiate bmdma */
3619 break;
3620
3621 case ATA_PROT_PIO: /* load tf registers, initiate polling pio */
3622 ata_qc_set_polling(qc);
e5338254 3623 ata_tf_to_host(ap, &qc->tf);
14be71f4 3624 ap->hsm_task_state = HSM_ST;
1da177e4
LT		 3625 queue_work(ata_wq, &ap->pio_task);
3626 break;
3627
3628 case ATA_PROT_ATAPI:
3629 ata_qc_set_polling(qc);
e5338254 3630 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3631 queue_work(ata_wq, &ap->packet_task);
3632 break;
3633
3634 case ATA_PROT_ATAPI_NODATA:
c1389503 3635 ap->flags |= ATA_FLAG_NOINTR;
e5338254 3636 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3637 queue_work(ata_wq, &ap->packet_task);
3638 break;
3639
3640 case ATA_PROT_ATAPI_DMA:
c1389503 3641 ap->flags |= ATA_FLAG_NOINTR;
1da177e4
LT		 3642 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3643 ap->ops->bmdma_setup(qc); /* set up bmdma */
3644 queue_work(ata_wq, &ap->packet_task);
3645 break;
3646
3647 default:
3648 WARN_ON(1);
3649 return -1;
3650 }
3651
3652 return 0;
3653}
3654
3655/**
0baab86b 3656 * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
1da177e4
LT		 3657 * @qc: Info associated with this ATA transaction.
3658 *
3659 * LOCKING:
3660 * spin_lock_irqsave(host_set lock)
3661 */
3662
3663static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
3664{
3665 struct ata_port *ap = qc->ap;
3666 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3667 u8 dmactl;
3668 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3669
3670 /* load PRD table addr. */
3671 mb(); /* make sure PRD table writes are visible to controller */
3672 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
3673
3674 /* specify data direction, triple-check start bit is clear */
3675 dmactl = readb(mmio + ATA_DMA_CMD);
3676 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3677 if (!rw)
3678 dmactl |= ATA_DMA_WR;
3679 writeb(dmactl, mmio + ATA_DMA_CMD);
3680
3681 /* issue r/w command */
3682 ap->ops->exec_command(ap, &qc->tf);
3683}
3684
3685/**
b73fc89f 3686 * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
1da177e4
LT		 3687 * @qc: Info associated with this ATA transaction.
3688 *
3689 * LOCKING:
3690 * spin_lock_irqsave(host_set lock)
3691 */
3692
3693static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
3694{
3695 struct ata_port *ap = qc->ap;
3696 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3697 u8 dmactl;
3698
3699 /* start host DMA transaction */
3700 dmactl = readb(mmio + ATA_DMA_CMD);
3701 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
3702
3703 /* Strictly, one may wish to issue a readb() here, to
3704 * flush the mmio write. However, control also passes
3705 * to the hardware at this point, and it will interrupt
3706 * us when we are to resume control. So, in effect,
3707 * we don't care when the mmio write flushes.
3708 * Further, a read of the DMA status register _immediately_
3709 * following the write may not be what certain flaky hardware
3710 * is expected, so I think it is best to not add a readb()
3711 * without first all the MMIO ATA cards/mobos.
3712 * Or maybe I'm just being paranoid.
3713 */
3714}
3715
3716/**
3717 * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
3718 * @qc: Info associated with this ATA transaction.
3719 *
3720 * LOCKING:
3721 * spin_lock_irqsave(host_set lock)
3722 */
3723
3724static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
3725{
3726 struct ata_port *ap = qc->ap;
3727 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3728 u8 dmactl;
3729
3730 /* load PRD table addr. */
3731 outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
3732
3733 /* specify data direction, triple-check start bit is clear */
3734 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3735 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3736 if (!rw)
3737 dmactl |= ATA_DMA_WR;
3738 outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3739
3740 /* issue r/w command */
3741 ap->ops->exec_command(ap, &qc->tf);
3742}
3743
3744/**
3745 * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
3746 * @qc: Info associated with this ATA transaction.
3747 *
3748 * LOCKING:
3749 * spin_lock_irqsave(host_set lock)
3750 */
3751
3752static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
3753{
3754 struct ata_port *ap = qc->ap;
3755 u8 dmactl;
3756
3757 /* start host DMA transaction */
3758 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3759 outb(dmactl | ATA_DMA_START,
3760 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3761}
3762
0baab86b
EF		 3763
3764/**
3765 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3766 * @qc: Info associated with this ATA transaction.
3767 *
3768 * Writes the ATA_DMA_START flag to the DMA command register.
3769 *
3770 * May be used as the bmdma_start() entry in ata_port_operations.
3771 *
3772 * LOCKING:
3773 * spin_lock_irqsave(host_set lock)
3774 */
1da177e4
LT		 3775void ata_bmdma_start(struct ata_queued_cmd *qc)
3776{
3777 if (qc->ap->flags & ATA_FLAG_MMIO)
3778 ata_bmdma_start_mmio(qc);
3779 else
3780 ata_bmdma_start_pio(qc);
3781}
3782
0baab86b
EF		 3783
3784/**
3785 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
3786 * @qc: Info associated with this ATA transaction.
3787 *
3788 * Writes address of PRD table to device's PRD Table Address
3789 * register, sets the DMA control register, and calls
3790 * ops->exec_command() to start the transfer.
3791 *
3792 * May be used as the bmdma_setup() entry in ata_port_operations.
3793 *
3794 * LOCKING:
3795 * spin_lock_irqsave(host_set lock)
3796 */
1da177e4
LT		 3797void ata_bmdma_setup(struct ata_queued_cmd *qc)
3798{
3799 if (qc->ap->flags & ATA_FLAG_MMIO)
3800 ata_bmdma_setup_mmio(qc);
3801 else
3802 ata_bmdma_setup_pio(qc);
3803}
3804
0baab86b
EF		 3805
3806/**
3807 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
decc6d0b 3808 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3809 *
3810 * Clear interrupt and error flags in DMA status register.
3811 *
3812 * May be used as the irq_clear() entry in ata_port_operations.
3813 *
3814 * LOCKING:
3815 * spin_lock_irqsave(host_set lock)
3816 */
3817
1da177e4
LT		 3818void ata_bmdma_irq_clear(struct ata_port *ap)
3819{
3820 if (ap->flags & ATA_FLAG_MMIO) {
3821 void __iomem *mmio = ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
3822 writeb(readb(mmio), mmio);
3823 } else {
3824 unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
3825 outb(inb(addr), addr);
3826 }
3827
3828}
3829
0baab86b
EF		 3830
3831/**
3832 * ata_bmdma_status - Read PCI IDE BMDMA status
decc6d0b 3833 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3834 *
3835 * Read and return BMDMA status register.
3836 *
3837 * May be used as the bmdma_status() entry in ata_port_operations.
3838 *
3839 * LOCKING:
3840 * spin_lock_irqsave(host_set lock)
3841 */
3842
1da177e4
LT		 3843u8 ata_bmdma_status(struct ata_port *ap)
3844{
3845 u8 host_stat;
3846 if (ap->flags & ATA_FLAG_MMIO) {
3847 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3848 host_stat = readb(mmio + ATA_DMA_STATUS);
3849 } else
ee500aab 3850 host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
1da177e4
LT		 3851 return host_stat;
3852}
3853
0baab86b
EF		 3854
3855/**
3856 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
b73fc89f 3857 * @qc: Command we are ending DMA for
0baab86b
EF		 3858 *
3859 * Clears the ATA_DMA_START flag in the dma control register
3860 *
3861 * May be used as the bmdma_stop() entry in ata_port_operations.
3862 *
3863 * LOCKING:
3864 * spin_lock_irqsave(host_set lock)
3865 */
3866
b73fc89f 3867void ata_bmdma_stop(struct ata_queued_cmd *qc)
1da177e4 3868{
b73fc89f 3869 struct ata_port *ap = qc->ap;
1da177e4
LT		 3870 if (ap->flags & ATA_FLAG_MMIO) {
3871 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3872
3873 /* clear start/stop bit */
3874 writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
3875 mmio + ATA_DMA_CMD);
3876 } else {
3877 /* clear start/stop bit */
3878 outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
3879 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3880 }
3881
3882 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
3883 ata_altstatus(ap); /* dummy read */
3884}
3885
3886/**
3887 * ata_host_intr - Handle host interrupt for given (port, task)
3888 * @ap: Port on which interrupt arrived (possibly...)
3889 * @qc: Taskfile currently active in engine
3890 *
3891 * Handle host interrupt for given queued command. Currently,
3892 * only DMA interrupts are handled. All other commands are
3893 * handled via polling with interrupts disabled (nIEN bit).
3894 *
3895 * LOCKING:
3896 * spin_lock_irqsave(host_set lock)
3897 *
3898 * RETURNS:
3899 * One if interrupt was handled, zero if not (shared irq).
3900 */
3901
3902inline unsigned int ata_host_intr (struct ata_port *ap,
3903 struct ata_queued_cmd *qc)
3904{
3905 u8 status, host_stat;
3906
3907 switch (qc->tf.protocol) {
3908
3909 case ATA_PROT_DMA:
3910 case ATA_PROT_ATAPI_DMA:
3911 case ATA_PROT_ATAPI:
3912 /* check status of DMA engine */
3913 host_stat = ap->ops->bmdma_status(ap);
3914 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
3915
3916 /* if it's not our irq... */
3917 if (!(host_stat & ATA_DMA_INTR))
3918 goto idle_irq;
3919
3920 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3921 ap->ops->bmdma_stop(qc);
1da177e4
LT		 3922
3923 /* fall through */
3924
3925 case ATA_PROT_ATAPI_NODATA:
3926 case ATA_PROT_NODATA:
3927 /* check altstatus */
3928 status = ata_altstatus(ap);
3929 if (status & ATA_BUSY)
3930 goto idle_irq;
3931
3932 /* check main status, clearing INTRQ */
3933 status = ata_chk_status(ap);
3934 if (unlikely(status & ATA_BUSY))
3935 goto idle_irq;
3936 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
3937 ap->id, qc->tf.protocol, status);
3938
3939 /* ack bmdma irq events */
3940 ap->ops->irq_clear(ap);
3941
3942 /* complete taskfile transaction */
a7dac447 3943 ata_qc_complete(qc, ac_err_mask(status));
1da177e4
LT		 3944 break;
3945
3946 default:
3947 goto idle_irq;
3948 }
3949
3950 return 1; /* irq handled */
3951
3952idle_irq:
3953 ap->stats.idle_irq++;
3954
3955#ifdef ATA_IRQ_TRAP
3956 if ((ap->stats.idle_irq % 1000) == 0) {
3957 handled = 1;
3958 ata_irq_ack(ap, 0); /* debug trap */
3959 printk(KERN_WARNING "ata%d: irq trap\n", ap->id);
3960 }
3961#endif
3962 return 0; /* irq not handled */
3963}
3964
3965/**
3966 * ata_interrupt - Default ATA host interrupt handler
0cba632b
JG		 3967 * @irq: irq line (unused)
3968 * @dev_instance: pointer to our ata_host_set information structure
1da177e4
LT		 3969 * @regs: unused
3970 *
0cba632b
JG		 3971 * Default interrupt handler for PCI IDE devices. Calls
3972 * ata_host_intr() for each port that is not disabled.
3973 *
1da177e4 3974 * LOCKING:
0cba632b 3975 * Obtains host_set lock during operation.
1da177e4
LT		 3976 *
3977 * RETURNS:
0cba632b 3978 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 3979 */
3980
3981irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
3982{
3983 struct ata_host_set *host_set = dev_instance;
3984 unsigned int i;
3985 unsigned int handled = 0;
3986 unsigned long flags;
3987
3988 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
3989 spin_lock_irqsave(&host_set->lock, flags);
3990
3991 for (i = 0; i < host_set->n_ports; i++) {
3992 struct ata_port *ap;
3993
3994 ap = host_set->ports[i];
c1389503
TH		 3995 if (ap &&
3996 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT		 3997 struct ata_queued_cmd *qc;
3998
3999 qc = ata_qc_from_tag(ap, ap->active_tag);
21b1ed74
AL		 4000 if (qc && (!(qc->tf.ctl & ATA_NIEN)) &&
4001 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 4002 handled |= ata_host_intr(ap, qc);
4003 }
4004 }
4005
4006 spin_unlock_irqrestore(&host_set->lock, flags);
4007
4008 return IRQ_RETVAL(handled);
4009}
4010
4011/**
4012 * atapi_packet_task - Write CDB bytes to hardware
4013 * @_data: Port to which ATAPI device is attached.
4014 *
4015 * When device has indicated its readiness to accept
4016 * a CDB, this function is called. Send the CDB.
4017 * If DMA is to be performed, exit immediately.
4018 * Otherwise, we are in polling mode, so poll
4019 * status under operation succeeds or fails.
4020 *
4021 * LOCKING:
4022 * Kernel thread context (may sleep)
4023 */
4024
4025static void atapi_packet_task(void *_data)
4026{
4027 struct ata_port *ap = _data;
4028 struct ata_queued_cmd *qc;
4029 u8 status;
4030
4031 qc = ata_qc_from_tag(ap, ap->active_tag);
4032 assert(qc != NULL);
4033 assert(qc->flags & ATA_QCFLAG_ACTIVE);
4034
4035 /* sleep-wait for BSY to clear */
4036 DPRINTK("busy wait\n");
4037 if (ata_busy_sleep(ap, ATA_TMOUT_CDB_QUICK, ATA_TMOUT_CDB))
a7dac447 4038 goto err_out_status;
1da177e4
LT		 4039
4040 /* make sure DRQ is set */
4041 status = ata_chk_status(ap);
4042 if ((status & (ATA_BUSY | ATA_DRQ)) != ATA_DRQ)
4043 goto err_out;
4044
4045 /* send SCSI cdb */
4046 DPRINTK("send cdb\n");
4047 assert(ap->cdb_len >= 12);
1da177e4 4048
c1389503
TH		 4049 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA ||
4050 qc->tf.protocol == ATA_PROT_ATAPI_NODATA) {
4051 unsigned long flags;
1da177e4 4052
c1389503
TH		 4053 /* Once we're done issuing command and kicking bmdma,
4054 * irq handler takes over. To not lose irq, we need
4055 * to clear NOINTR flag before sending cdb, but
4056 * interrupt handler shouldn't be invoked before we're
4057 * finished. Hence, the following locking.
4058 */
4059 spin_lock_irqsave(&ap->host_set->lock, flags);
4060 ap->flags &= ~ATA_FLAG_NOINTR;
4061 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
4062 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA)
4063 ap->ops->bmdma_start(qc); /* initiate bmdma */
4064 spin_unlock_irqrestore(&ap->host_set->lock, flags);
4065 } else {
4066 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
1da177e4 4067
c1389503 4068 /* PIO commands are handled by polling */
14be71f4 4069 ap->hsm_task_state = HSM_ST;
1da177e4
LT		 4070 queue_work(ata_wq, &ap->pio_task);
4071 }
4072
4073 return;
4074
a7dac447
JG		 4075err_out_status:
4076 status = ata_chk_status(ap);
1da177e4 4077err_out:
a7dac447 4078 ata_poll_qc_complete(qc, __ac_err_mask(status));
1da177e4
LT		 4079}
4080
0baab86b
EF		 4081
4082/**
4083 * ata_port_start - Set port up for dma.
4084 * @ap: Port to initialize
4085 *
4086 * Called just after data structures for each port are
4087 * initialized. Allocates space for PRD table.
4088 *
4089 * May be used as the port_start() entry in ata_port_operations.
4090 *
4091 * LOCKING:
6f0ef4fa 4092 * Inherited from caller.
0baab86b
EF		 4093 */
4094
1da177e4
LT		 4095int ata_port_start (struct ata_port *ap)
4096{
4097 struct device *dev = ap->host_set->dev;
6037d6bb 4098 int rc;
1da177e4
LT		 4099
4100 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
4101 if (!ap->prd)
4102 return -ENOMEM;
4103
6037d6bb
JG		 4104 rc = ata_pad_alloc(ap, dev);
4105 if (rc) {
cedc9a47 4106 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4107 return rc;
cedc9a47
JG		 4108 }
4109
1da177e4
LT		 4110 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
4111
4112 return 0;
4113}
4114
0baab86b
EF		 4115
4116/**
4117 * ata_port_stop - Undo ata_port_start()
4118 * @ap: Port to shut down
4119 *
4120 * Frees the PRD table.
4121 *
4122 * May be used as the port_stop() entry in ata_port_operations.
4123 *
4124 * LOCKING:
6f0ef4fa 4125 * Inherited from caller.
0baab86b
EF		 4126 */
4127
1da177e4
LT		 4128void ata_port_stop (struct ata_port *ap)
4129{
4130 struct device *dev = ap->host_set->dev;
4131
4132 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4133 ata_pad_free(ap, dev);
1da177e4
LT		 4134}
4135
aa8f0dc6
JG		 4136void ata_host_stop (struct ata_host_set *host_set)
4137{
4138 if (host_set->mmio_base)
4139 iounmap(host_set->mmio_base);
4140}
4141
4142
1da177e4
LT		 4143/**
4144 * ata_host_remove - Unregister SCSI host structure with upper layers
4145 * @ap: Port to unregister
4146 * @do_unregister: 1 if we fully unregister, 0 to just stop the port
4147 *
4148 * LOCKING:
6f0ef4fa 4149 * Inherited from caller.
1da177e4
LT		 4150 */
4151
4152static void ata_host_remove(struct ata_port *ap, unsigned int do_unregister)
4153{
4154 struct Scsi_Host *sh = ap->host;
4155
4156 DPRINTK("ENTER\n");
4157
4158 if (do_unregister)
4159 scsi_remove_host(sh);
4160
4161 ap->ops->port_stop(ap);
4162}
4163
4164/**
4165 * ata_host_init - Initialize an ata_port structure
4166 * @ap: Structure to initialize
4167 * @host: associated SCSI mid-layer structure
4168 * @host_set: Collection of hosts to which @ap belongs
4169 * @ent: Probe information provided by low-level driver
4170 * @port_no: Port number associated with this ata_port
4171 *
0cba632b
JG		 4172 * Initialize a new ata_port structure, and its associated
4173 * scsi_host.
4174 *
1da177e4 4175 * LOCKING:
0cba632b 4176 * Inherited from caller.
1da177e4
LT		 4177 */
4178
4179static void ata_host_init(struct ata_port *ap, struct Scsi_Host *host,
4180 struct ata_host_set *host_set,
057ace5e 4181 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 4182{
4183 unsigned int i;
4184
4185 host->max_id = 16;
4186 host->max_lun = 1;
4187 host->max_channel = 1;
4188 host->unique_id = ata_unique_id++;
4189 host->max_cmd_len = 12;
12413197 4190
1da177e4
LT		 4191 ap->flags = ATA_FLAG_PORT_DISABLED;
4192 ap->id = host->unique_id;
4193 ap->host = host;
4194 ap->ctl = ATA_DEVCTL_OBS;
4195 ap->host_set = host_set;
4196 ap->port_no = port_no;
4197 ap->hard_port_no =
4198 ent->legacy_mode ? ent->hard_port_no : port_no;
4199 ap->pio_mask = ent->pio_mask;
4200 ap->mwdma_mask = ent->mwdma_mask;
4201 ap->udma_mask = ent->udma_mask;
4202 ap->flags |= ent->host_flags;
4203 ap->ops = ent->port_ops;
4204 ap->cbl = ATA_CBL_NONE;
4205 ap->active_tag = ATA_TAG_POISON;
4206 ap->last_ctl = 0xFF;
4207
4208 INIT_WORK(&ap->packet_task, atapi_packet_task, ap);
4209 INIT_WORK(&ap->pio_task, ata_pio_task, ap);
4210
4211 for (i = 0; i < ATA_MAX_DEVICES; i++)
4212 ap->device[i].devno = i;
4213
4214#ifdef ATA_IRQ_TRAP
4215 ap->stats.unhandled_irq = 1;
4216 ap->stats.idle_irq = 1;
4217#endif
4218
4219 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
4220}
4221
4222/**
4223 * ata_host_add - Attach low-level ATA driver to system
4224 * @ent: Information provided by low-level driver
4225 * @host_set: Collections of ports to which we add
4226 * @port_no: Port number associated with this host
4227 *
0cba632b
JG		 4228 * Attach low-level ATA driver to system.
4229 *
1da177e4 4230 * LOCKING:
0cba632b 4231 * PCI/etc. bus probe sem.
1da177e4
LT		 4232 *
4233 * RETURNS:
0cba632b 4234 * New ata_port on success, for NULL on error.
1da177e4
LT		 4235 */
4236
057ace5e 4237static struct ata_port * ata_host_add(const struct ata_probe_ent *ent,
1da177e4
LT		 4238 struct ata_host_set *host_set,
4239 unsigned int port_no)
4240{
4241 struct Scsi_Host *host;
4242 struct ata_port *ap;
4243 int rc;
4244
4245 DPRINTK("ENTER\n");
4246 host = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
4247 if (!host)
4248 return NULL;
4249
4250 ap = (struct ata_port *) &host->hostdata[0];
4251
4252 ata_host_init(ap, host, host_set, ent, port_no);
4253
4254 rc = ap->ops->port_start(ap);
4255 if (rc)
4256 goto err_out;
4257
4258 return ap;
4259
4260err_out:
4261 scsi_host_put(host);
4262 return NULL;
4263}
4264
4265/**
0cba632b
JG		 4266 * ata_device_add - Register hardware device with ATA and SCSI layers
4267 * @ent: Probe information describing hardware device to be registered
4268 *
4269 * This function processes the information provided in the probe
4270 * information struct @ent, allocates the necessary ATA and SCSI
4271 * host information structures, initializes them, and registers
4272 * everything with requisite kernel subsystems.
4273 *
4274 * This function requests irqs, probes the ATA bus, and probes
4275 * the SCSI bus.
1da177e4
LT		 4276 *
4277 * LOCKING:
0cba632b 4278 * PCI/etc. bus probe sem.
1da177e4
LT		 4279 *
4280 * RETURNS:
0cba632b 4281 * Number of ports registered. Zero on error (no ports registered).
1da177e4
LT		 4282 */
4283
057ace5e 4284int ata_device_add(const struct ata_probe_ent *ent)
1da177e4
LT		 4285{
4286 unsigned int count = 0, i;
4287 struct device *dev = ent->dev;
4288 struct ata_host_set *host_set;
4289
4290 DPRINTK("ENTER\n");
4291 /* alloc a container for our list of ATA ports (buses) */
57f3bda8 4292 host_set = kzalloc(sizeof(struct ata_host_set) +
1da177e4
LT		 4293 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
4294 if (!host_set)
4295 return 0;
1da177e4
LT		 4296 spin_lock_init(&host_set->lock);
4297
4298 host_set->dev = dev;
4299 host_set->n_ports = ent->n_ports;
4300 host_set->irq = ent->irq;
4301 host_set->mmio_base = ent->mmio_base;
4302 host_set->private_data = ent->private_data;
4303 host_set->ops = ent->port_ops;
4304
4305 /* register each port bound to this device */
4306 for (i = 0; i < ent->n_ports; i++) {
4307 struct ata_port *ap;
4308 unsigned long xfer_mode_mask;
4309
4310 ap = ata_host_add(ent, host_set, i);
4311 if (!ap)
4312 goto err_out;
4313
4314 host_set->ports[i] = ap;
4315 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
4316 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
4317 (ap->pio_mask << ATA_SHIFT_PIO);
4318
4319 /* print per-port info to dmesg */
4320 printk(KERN_INFO "ata%u: %cATA max %s cmd 0x%lX ctl 0x%lX "
4321 "bmdma 0x%lX irq %lu\n",
4322 ap->id,
4323 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
4324 ata_mode_string(xfer_mode_mask),
4325 ap->ioaddr.cmd_addr,
4326 ap->ioaddr.ctl_addr,
4327 ap->ioaddr.bmdma_addr,
4328 ent->irq);
4329
4330 ata_chk_status(ap);
4331 host_set->ops->irq_clear(ap);
4332 count++;
4333 }
4334
57f3bda8
RD		 4335 if (!count)
4336 goto err_free_ret;
1da177e4
LT		 4337
4338 /* obtain irq, that is shared between channels */
4339 if (request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
4340 DRV_NAME, host_set))
4341 goto err_out;
4342
4343 /* perform each probe synchronously */
4344 DPRINTK("probe begin\n");
4345 for (i = 0; i < count; i++) {
4346 struct ata_port *ap;
4347 int rc;
4348
4349 ap = host_set->ports[i];
4350
4351 DPRINTK("ata%u: probe begin\n", ap->id);
4352 rc = ata_bus_probe(ap);
4353 DPRINTK("ata%u: probe end\n", ap->id);
4354
4355 if (rc) {
4356 /* FIXME: do something useful here?
4357 * Current libata behavior will
4358 * tear down everything when
4359 * the module is removed
4360 * or the h/w is unplugged.
4361 */
4362 }
4363
4364 rc = scsi_add_host(ap->host, dev);
4365 if (rc) {
4366 printk(KERN_ERR "ata%u: scsi_add_host failed\n",
4367 ap->id);
4368 /* FIXME: do something useful here */
4369 /* FIXME: handle unconditional calls to
4370 * scsi_scan_host and ata_host_remove, below,
4371 * at the very least
4372 */
4373 }
4374 }
4375
4376 /* probes are done, now scan each port's disk(s) */
4377 DPRINTK("probe begin\n");
4378 for (i = 0; i < count; i++) {
4379 struct ata_port *ap = host_set->ports[i];
4380
644dd0cc 4381 ata_scsi_scan_host(ap);
1da177e4
LT		 4382 }
4383
4384 dev_set_drvdata(dev, host_set);
4385
4386 VPRINTK("EXIT, returning %u\n", ent->n_ports);
4387 return ent->n_ports; /* success */
4388
4389err_out:
4390 for (i = 0; i < count; i++) {
4391 ata_host_remove(host_set->ports[i], 1);
4392 scsi_host_put(host_set->ports[i]->host);
4393 }
57f3bda8 4394err_free_ret:
1da177e4
LT		 4395 kfree(host_set);
4396 VPRINTK("EXIT, returning 0\n");
4397 return 0;
4398}
4399
17b14451
AC		 4400/**
4401 * ata_host_set_remove - PCI layer callback for device removal
4402 * @host_set: ATA host set that was removed
4403 *
4404 * Unregister all objects associated with this host set. Free those
4405 * objects.
4406 *
4407 * LOCKING:
4408 * Inherited from calling layer (may sleep).
4409 */
4410
17b14451
AC		 4411void ata_host_set_remove(struct ata_host_set *host_set)
4412{
4413 struct ata_port *ap;
4414 unsigned int i;
4415
4416 for (i = 0; i < host_set->n_ports; i++) {
4417 ap = host_set->ports[i];
4418 scsi_remove_host(ap->host);
4419 }
4420
4421 free_irq(host_set->irq, host_set);
4422
4423 for (i = 0; i < host_set->n_ports; i++) {
4424 ap = host_set->ports[i];
4425
4426 ata_scsi_release(ap->host);
4427
4428 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
4429 struct ata_ioports *ioaddr = &ap->ioaddr;
4430
4431 if (ioaddr->cmd_addr == 0x1f0)
4432 release_region(0x1f0, 8);
4433 else if (ioaddr->cmd_addr == 0x170)
4434 release_region(0x170, 8);
4435 }
4436
4437 scsi_host_put(ap->host);
4438 }
4439
4440 if (host_set->ops->host_stop)
4441 host_set->ops->host_stop(host_set);
4442
4443 kfree(host_set);
4444}
4445
1da177e4
LT		 4446/**
4447 * ata_scsi_release - SCSI layer callback hook for host unload
4448 * @host: libata host to be unloaded
4449 *
4450 * Performs all duties necessary to shut down a libata port...
4451 * Kill port kthread, disable port, and release resources.
4452 *
4453 * LOCKING:
4454 * Inherited from SCSI layer.
4455 *
4456 * RETURNS:
4457 * One.
4458 */
4459
4460int ata_scsi_release(struct Scsi_Host *host)
4461{
4462 struct ata_port *ap = (struct ata_port *) &host->hostdata[0];
4463
4464 DPRINTK("ENTER\n");
4465
4466 ap->ops->port_disable(ap);
4467 ata_host_remove(ap, 0);
4468
4469 DPRINTK("EXIT\n");
4470 return 1;
4471}
4472
4473/**
4474 * ata_std_ports - initialize ioaddr with standard port offsets.
4475 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 4476 *
4477 * Utility function which initializes data_addr, error_addr,
4478 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
4479 * device_addr, status_addr, and command_addr to standard offsets
4480 * relative to cmd_addr.
4481 *
4482 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 4483 */
0baab86b 4484
1da177e4
LT		 4485void ata_std_ports(struct ata_ioports *ioaddr)
4486{
4487 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
4488 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
4489 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
4490 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
4491 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
4492 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
4493 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
4494 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
4495 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
4496 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
4497}
4498
4499static struct ata_probe_ent *
057ace5e 4500ata_probe_ent_alloc(struct device *dev, const struct ata_port_info *port)
1da177e4
LT		 4501{
4502 struct ata_probe_ent *probe_ent;
4503
57f3bda8 4504 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
1da177e4
LT		 4505 if (!probe_ent) {
4506 printk(KERN_ERR DRV_NAME "(%s): out of memory\n",
4507 kobject_name(&(dev->kobj)));
4508 return NULL;
4509 }
4510
1da177e4
LT		 4511 INIT_LIST_HEAD(&probe_ent->node);
4512 probe_ent->dev = dev;
4513
4514 probe_ent->sht = port->sht;
4515 probe_ent->host_flags = port->host_flags;
4516 probe_ent->pio_mask = port->pio_mask;
4517 probe_ent->mwdma_mask = port->mwdma_mask;
4518 probe_ent->udma_mask = port->udma_mask;
4519 probe_ent->port_ops = port->port_ops;
4520
4521 return probe_ent;
4522}
4523
0baab86b
EF		 4524
4525
374b1873
JG		 4526#ifdef CONFIG_PCI
4527
4528void ata_pci_host_stop (struct ata_host_set *host_set)
4529{
4530 struct pci_dev *pdev = to_pci_dev(host_set->dev);
4531
4532 pci_iounmap(pdev, host_set->mmio_base);
4533}
4534
0baab86b
EF		 4535/**
4536 * ata_pci_init_native_mode - Initialize native-mode driver
4537 * @pdev: pci device to be initialized
4538 * @port: array[2] of pointers to port info structures.
47a86593 4539 * @ports: bitmap of ports present
0baab86b
EF		 4540 *
4541 * Utility function which allocates and initializes an
4542 * ata_probe_ent structure for a standard dual-port
4543 * PIO-based IDE controller. The returned ata_probe_ent
4544 * structure can be passed to ata_device_add(). The returned
4545 * ata_probe_ent structure should then be freed with kfree().
47a86593
AC		 4546 *
4547 * The caller need only pass the address of the primary port, the
4548 * secondary will be deduced automatically. If the device has non
4549 * standard secondary port mappings this function can be called twice,
4550 * once for each interface.
0baab86b
EF		 4551 */
4552
1da177e4 4553struct ata_probe_ent *
47a86593 4554ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports)
1da177e4
LT		 4555{
4556 struct ata_probe_ent *probe_ent =
4557 ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]);
47a86593
AC		 4558 int p = 0;
4559
1da177e4
LT		 4560 if (!probe_ent)
4561 return NULL;
4562
1da177e4
LT		 4563 probe_ent->irq = pdev->irq;
4564 probe_ent->irq_flags = SA_SHIRQ;
e99f8b5e 4565 probe_ent->private_data = port[0]->private_data;
1da177e4 4566
47a86593
AC		 4567 if (ports & ATA_PORT_PRIMARY) {
4568 probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 0);
4569 probe_ent->port[p].altstatus_addr =
4570 probe_ent->port[p].ctl_addr =
4571 pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS;
4572 probe_ent->port[p].bmdma_addr = pci_resource_start(pdev, 4);
4573 ata_std_ports(&probe_ent->port[p]);
4574 p++;
4575 }
1da177e4 4576
47a86593
AC		 4577 if (ports & ATA_PORT_SECONDARY) {
4578 probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 2);
4579 probe_ent->port[p].altstatus_addr =
4580 probe_ent->port[p].ctl_addr =
4581 pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS;
4582 probe_ent->port[p].bmdma_addr = pci_resource_start(pdev, 4) + 8;
4583 ata_std_ports(&probe_ent->port[p]);
4584 p++;
4585 }
1da177e4 4586
47a86593 4587 probe_ent->n_ports = p;
1da177e4
LT		 4588 return probe_ent;
4589}
4590
0f0d5192 4591static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, struct ata_port_info *port, int port_num)
1da177e4 4592{
47a86593 4593 struct ata_probe_ent *probe_ent;
1da177e4 4594
0f0d5192 4595 probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port);
1da177e4
LT		 4596 if (!probe_ent)
4597 return NULL;
1da177e4 4598
1da177e4 4599 probe_ent->legacy_mode = 1;
47a86593
AC		 4600 probe_ent->n_ports = 1;
4601 probe_ent->hard_port_no = port_num;
e99f8b5e 4602 probe_ent->private_data = port->private_data;
47a86593
AC		 4603
4604 switch(port_num)
4605 {
4606 case 0:
4607 probe_ent->irq = 14;
4608 probe_ent->port[0].cmd_addr = 0x1f0;
4609 probe_ent->port[0].altstatus_addr =
4610 probe_ent->port[0].ctl_addr = 0x3f6;
4611 break;
4612 case 1:
4613 probe_ent->irq = 15;
4614 probe_ent->port[0].cmd_addr = 0x170;
4615 probe_ent->port[0].altstatus_addr =
4616 probe_ent->port[0].ctl_addr = 0x376;
4617 break;
4618 }
4619 probe_ent->port[0].bmdma_addr = pci_resource_start(pdev, 4) + 8 * port_num;
1da177e4 4620 ata_std_ports(&probe_ent->port[0]);
1da177e4
LT		 4621 return probe_ent;
4622}
4623
4624/**
4625 * ata_pci_init_one - Initialize/register PCI IDE host controller
4626 * @pdev: Controller to be initialized
4627 * @port_info: Information from low-level host driver
4628 * @n_ports: Number of ports attached to host controller
4629 *
0baab86b
EF		 4630 * This is a helper function which can be called from a driver's
4631 * xxx_init_one() probe function if the hardware uses traditional
4632 * IDE taskfile registers.
4633 *
4634 * This function calls pci_enable_device(), reserves its register
4635 * regions, sets the dma mask, enables bus master mode, and calls
4636 * ata_device_add()
4637 *
1da177e4
LT		 4638 * LOCKING:
4639 * Inherited from PCI layer (may sleep).
4640 *
4641 * RETURNS:
0cba632b 4642 * Zero on success, negative on errno-based value on error.
1da177e4
LT		 4643 */
4644
4645int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_info,
4646 unsigned int n_ports)
4647{
47a86593 4648 struct ata_probe_ent *probe_ent = NULL, *probe_ent2 = NULL;
1da177e4
LT		 4649 struct ata_port_info *port[2];
4650 u8 tmp8, mask;
4651 unsigned int legacy_mode = 0;
4652 int disable_dev_on_err = 1;
4653 int rc;
4654
4655 DPRINTK("ENTER\n");
4656
4657 port[0] = port_info[0];
4658 if (n_ports > 1)
4659 port[1] = port_info[1];
4660 else
4661 port[1] = port[0];
4662
4663 if ((port[0]->host_flags & ATA_FLAG_NO_LEGACY) == 0
4664 && (pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
47a86593 4665 /* TODO: What if one channel is in native mode ... */
1da177e4
LT		 4666 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
4667 mask = (1 << 2) | (1 << 0);
4668 if ((tmp8 & mask) != mask)
4669 legacy_mode = (1 << 3);
4670 }
4671
4672 /* FIXME... */
47a86593
AC		 4673 if ((!legacy_mode) && (n_ports > 2)) {
4674 printk(KERN_ERR "ata: BUG: native mode, n_ports > 2\n");
4675 n_ports = 2;
4676 /* For now */
1da177e4
LT		 4677 }
4678
47a86593
AC		 4679 /* FIXME: Really for ATA it isn't safe because the device may be
4680 multi-purpose and we want to leave it alone if it was already
4681 enabled. Secondly for shared use as Arjan says we want refcounting
4682
4683 Checking dev->is_enabled is insufficient as this is not set at
4684 boot for the primary video which is BIOS enabled
4685 */
4686
1da177e4
LT		 4687 rc = pci_enable_device(pdev);
4688 if (rc)
4689 return rc;
4690
4691 rc = pci_request_regions(pdev, DRV_NAME);
4692 if (rc) {
4693 disable_dev_on_err = 0;
4694 goto err_out;
4695 }
4696
47a86593 4697 /* FIXME: Should use platform specific mappers for legacy port ranges */
1da177e4
LT		 4698 if (legacy_mode) {
4699 if (!request_region(0x1f0, 8, "libata")) {
4700 struct resource *conflict, res;
4701 res.start = 0x1f0;
4702 res.end = 0x1f0 + 8 - 1;
4703 conflict = ____request_resource(&ioport_resource, &res);
4704 if (!strcmp(conflict->name, "libata"))
4705 legacy_mode |= (1 << 0);
4706 else {
4707 disable_dev_on_err = 0;
4708 printk(KERN_WARNING "ata: 0x1f0 IDE port busy\n");
4709 }
4710 } else
4711 legacy_mode |= (1 << 0);
4712
4713 if (!request_region(0x170, 8, "libata")) {
4714 struct resource *conflict, res;
4715 res.start = 0x170;
4716 res.end = 0x170 + 8 - 1;
4717 conflict = ____request_resource(&ioport_resource, &res);
4718 if (!strcmp(conflict->name, "libata"))
4719 legacy_mode |= (1 << 1);
4720 else {
4721 disable_dev_on_err = 0;
4722 printk(KERN_WARNING "ata: 0x170 IDE port busy\n");
4723 }
4724 } else
4725 legacy_mode |= (1 << 1);
4726 }
4727
4728 /* we have legacy mode, but all ports are unavailable */
4729 if (legacy_mode == (1 << 3)) {
4730 rc = -EBUSY;
4731 goto err_out_regions;
4732 }
4733
4734 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
4735 if (rc)
4736 goto err_out_regions;
4737 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
4738 if (rc)
4739 goto err_out_regions;
4740
4741 if (legacy_mode) {
47a86593 4742 if (legacy_mode & (1 << 0))
0f0d5192 4743 probe_ent = ata_pci_init_legacy_port(pdev, port[0], 0);
47a86593 4744 if (legacy_mode & (1 << 1))
0f0d5192 4745 probe_ent2 = ata_pci_init_legacy_port(pdev, port[1], 1);
47a86593
AC		 4746 } else {
4747 if (n_ports == 2)
4748 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
4749 else
4750 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY);
4751 }
4752 if (!probe_ent && !probe_ent2) {
1da177e4
LT		 4753 rc = -ENOMEM;
4754 goto err_out_regions;
4755 }
4756
4757 pci_set_master(pdev);
4758
4759 /* FIXME: check ata_device_add return */
4760 if (legacy_mode) {
4761 if (legacy_mode & (1 << 0))
4762 ata_device_add(probe_ent);
4763 if (legacy_mode & (1 << 1))
4764 ata_device_add(probe_ent2);
4765 } else
4766 ata_device_add(probe_ent);
4767
4768 kfree(probe_ent);
4769 kfree(probe_ent2);
4770
4771 return 0;
4772
4773err_out_regions:
4774 if (legacy_mode & (1 << 0))
4775 release_region(0x1f0, 8);
4776 if (legacy_mode & (1 << 1))
4777 release_region(0x170, 8);
4778 pci_release_regions(pdev);
4779err_out:
4780 if (disable_dev_on_err)
4781 pci_disable_device(pdev);
4782 return rc;
4783}
4784
4785/**
4786 * ata_pci_remove_one - PCI layer callback for device removal
4787 * @pdev: PCI device that was removed
4788 *
4789 * PCI layer indicates to libata via this hook that
6f0ef4fa 4790 * hot-unplug or module unload event has occurred.
1da177e4
LT		 4791 * Handle this by unregistering all objects associated
4792 * with this PCI device. Free those objects. Then finally
4793 * release PCI resources and disable device.
4794 *
4795 * LOCKING:
4796 * Inherited from PCI layer (may sleep).
4797 */
4798
4799void ata_pci_remove_one (struct pci_dev *pdev)
4800{
4801 struct device *dev = pci_dev_to_dev(pdev);
4802 struct ata_host_set *host_set = dev_get_drvdata(dev);
1da177e4 4803
17b14451 4804 ata_host_set_remove(host_set);
1da177e4
LT		 4805 pci_release_regions(pdev);
4806 pci_disable_device(pdev);
4807 dev_set_drvdata(dev, NULL);
4808}
4809
4810/* move to PCI subsystem */
057ace5e 4811int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 4812{
4813 unsigned long tmp = 0;
4814
4815 switch (bits->width) {
4816 case 1: {
4817 u8 tmp8 = 0;
4818 pci_read_config_byte(pdev, bits->reg, &tmp8);
4819 tmp = tmp8;
4820 break;
4821 }
4822 case 2: {
4823 u16 tmp16 = 0;
4824 pci_read_config_word(pdev, bits->reg, &tmp16);
4825 tmp = tmp16;
4826 break;
4827 }
4828 case 4: {
4829 u32 tmp32 = 0;
4830 pci_read_config_dword(pdev, bits->reg, &tmp32);
4831 tmp = tmp32;
4832 break;
4833 }
4834
4835 default:
4836 return -EINVAL;
4837 }
4838
4839 tmp &= bits->mask;
4840
4841 return (tmp == bits->val) ? 1 : 0;
4842}
4843#endif /* CONFIG_PCI */
4844
4845
1da177e4
LT		 4846static int __init ata_init(void)
4847{
4848 ata_wq = create_workqueue("ata");
4849 if (!ata_wq)
4850 return -ENOMEM;
4851
4852 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
4853 return 0;
4854}
4855
4856static void __exit ata_exit(void)
4857{
4858 destroy_workqueue(ata_wq);
4859}
4860
4861module_init(ata_init);
4862module_exit(ata_exit);
4863
67846b30
JG		 4864static unsigned long ratelimit_time;
4865static spinlock_t ata_ratelimit_lock = SPIN_LOCK_UNLOCKED;
4866
4867int ata_ratelimit(void)
4868{
4869 int rc;
4870 unsigned long flags;
4871
4872 spin_lock_irqsave(&ata_ratelimit_lock, flags);
4873
4874 if (time_after(jiffies, ratelimit_time)) {
4875 rc = 1;
4876 ratelimit_time = jiffies + (HZ/5);
4877 } else
4878 rc = 0;
4879
4880 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
4881
4882 return rc;
4883}
4884
1da177e4
LT		 4885/*
4886 * libata is essentially a library of internal helper functions for
4887 * low-level ATA host controller drivers. As such, the API/ABI is
4888 * likely to change as new drivers are added and updated.
4889 * Do not depend on ABI/API stability.
4890 */
4891
4892EXPORT_SYMBOL_GPL(ata_std_bios_param);
4893EXPORT_SYMBOL_GPL(ata_std_ports);
4894EXPORT_SYMBOL_GPL(ata_device_add);
17b14451 4895EXPORT_SYMBOL_GPL(ata_host_set_remove);
1da177e4
LT		 4896EXPORT_SYMBOL_GPL(ata_sg_init);
4897EXPORT_SYMBOL_GPL(ata_sg_init_one);
4898EXPORT_SYMBOL_GPL(ata_qc_complete);
4899EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
4900EXPORT_SYMBOL_GPL(ata_eng_timeout);
4901EXPORT_SYMBOL_GPL(ata_tf_load);
4902EXPORT_SYMBOL_GPL(ata_tf_read);
4903EXPORT_SYMBOL_GPL(ata_noop_dev_select);
4904EXPORT_SYMBOL_GPL(ata_std_dev_select);
4905EXPORT_SYMBOL_GPL(ata_tf_to_fis);
4906EXPORT_SYMBOL_GPL(ata_tf_from_fis);
4907EXPORT_SYMBOL_GPL(ata_check_status);
4908EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 4909EXPORT_SYMBOL_GPL(ata_exec_command);
4910EXPORT_SYMBOL_GPL(ata_port_start);
4911EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 4912EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4
LT		 4913EXPORT_SYMBOL_GPL(ata_interrupt);
4914EXPORT_SYMBOL_GPL(ata_qc_prep);
4915EXPORT_SYMBOL_GPL(ata_bmdma_setup);
4916EXPORT_SYMBOL_GPL(ata_bmdma_start);
4917EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
4918EXPORT_SYMBOL_GPL(ata_bmdma_status);
4919EXPORT_SYMBOL_GPL(ata_bmdma_stop);
4920EXPORT_SYMBOL_GPL(ata_port_probe);
4921EXPORT_SYMBOL_GPL(sata_phy_reset);
4922EXPORT_SYMBOL_GPL(__sata_phy_reset);
4923EXPORT_SYMBOL_GPL(ata_bus_reset);
4924EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 4925EXPORT_SYMBOL_GPL(ata_ratelimit);
1da177e4
LT		 4926EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
4927EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
4928EXPORT_SYMBOL_GPL(ata_scsi_error);
4929EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
4930EXPORT_SYMBOL_GPL(ata_scsi_release);
4931EXPORT_SYMBOL_GPL(ata_host_intr);
4932EXPORT_SYMBOL_GPL(ata_dev_classify);
4933EXPORT_SYMBOL_GPL(ata_dev_id_string);
6f2f3812 4934EXPORT_SYMBOL_GPL(ata_dev_config);
1da177e4
LT		 4935EXPORT_SYMBOL_GPL(ata_scsi_simulate);
4936
452503f9
AC		 4937EXPORT_SYMBOL_GPL(ata_timing_compute);
4938EXPORT_SYMBOL_GPL(ata_timing_merge);
4939
1da177e4
LT		 4940#ifdef CONFIG_PCI
4941EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 4942EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 4943EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
4944EXPORT_SYMBOL_GPL(ata_pci_init_one);
4945EXPORT_SYMBOL_GPL(ata_pci_remove_one);
4946#endif /* CONFIG_PCI */
Clone of davem's net-next-2.6 tree