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[PATCH] libata: make ata_dev_knobble() per-device
[net-next-2.6.git] / drivers / scsi / libata-core.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
35#include <linux/config.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/list.h>
41#include <linux/mm.h>
42#include <linux/highmem.h>
43#include <linux/spinlock.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/timer.h>
47#include <linux/interrupt.h>
48#include <linux/completion.h>
49#include <linux/suspend.h>
50#include <linux/workqueue.h>
67846b30 51#include <linux/jiffies.h>
378f058c 52#include <linux/scatterlist.h>
1da177e4 53#include <scsi/scsi.h>
1da177e4 54#include "scsi_priv.h"
193515d5 55#include <scsi/scsi_cmnd.h>
1da177e4
LT		 56#include <scsi/scsi_host.h>
57#include <linux/libata.h>
58#include <asm/io.h>
59#include <asm/semaphore.h>
60#include <asm/byteorder.h>
61
62#include "libata.h"
63
59a10b17 64static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev);
8bf62ece 65static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev);
1da177e4
LT		 66static void ata_set_mode(struct ata_port *ap);
67static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev);
057ace5e 68static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift);
1da177e4 69static int fgb(u32 bitmap);
057ace5e 70static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 71 u8 *xfer_mode_out,
72 unsigned int *xfer_shift_out);
1da177e4
LT		 73
74static unsigned int ata_unique_id = 1;
75static struct workqueue_struct *ata_wq;
76
1623c81e
JG		 77int atapi_enabled = 0;
78module_param(atapi_enabled, int, 0444);
79MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
80
1da177e4
LT		 81MODULE_AUTHOR("Jeff Garzik");
82MODULE_DESCRIPTION("Library module for ATA devices");
83MODULE_LICENSE("GPL");
84MODULE_VERSION(DRV_VERSION);
85
0baab86b 86
1da177e4
LT		 87/**
88 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
89 * @tf: Taskfile to convert
90 * @fis: Buffer into which data will output
91 * @pmp: Port multiplier port
92 *
93 * Converts a standard ATA taskfile to a Serial ATA
94 * FIS structure (Register - Host to Device).
95 *
96 * LOCKING:
97 * Inherited from caller.
98 */
99
057ace5e 100void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 101{
102 fis[0] = 0x27; /* Register - Host to Device FIS */
103 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
104 bit 7 indicates Command FIS */
105 fis[2] = tf->command;
106 fis[3] = tf->feature;
107
108 fis[4] = tf->lbal;
109 fis[5] = tf->lbam;
110 fis[6] = tf->lbah;
111 fis[7] = tf->device;
112
113 fis[8] = tf->hob_lbal;
114 fis[9] = tf->hob_lbam;
115 fis[10] = tf->hob_lbah;
116 fis[11] = tf->hob_feature;
117
118 fis[12] = tf->nsect;
119 fis[13] = tf->hob_nsect;
120 fis[14] = 0;
121 fis[15] = tf->ctl;
122
123 fis[16] = 0;
124 fis[17] = 0;
125 fis[18] = 0;
126 fis[19] = 0;
127}
128
129/**
130 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
131 * @fis: Buffer from which data will be input
132 * @tf: Taskfile to output
133 *
e12a1be6 134 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT		 135 *
136 * LOCKING:
137 * Inherited from caller.
138 */
139
057ace5e 140void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 141{
142 tf->command = fis[2]; /* status */
143 tf->feature = fis[3]; /* error */
144
145 tf->lbal = fis[4];
146 tf->lbam = fis[5];
147 tf->lbah = fis[6];
148 tf->device = fis[7];
149
150 tf->hob_lbal = fis[8];
151 tf->hob_lbam = fis[9];
152 tf->hob_lbah = fis[10];
153
154 tf->nsect = fis[12];
155 tf->hob_nsect = fis[13];
156}
157
8cbd6df1
AL		 158static const u8 ata_rw_cmds[] = {
159 /* pio multi */
160 ATA_CMD_READ_MULTI,
161 ATA_CMD_WRITE_MULTI,
162 ATA_CMD_READ_MULTI_EXT,
163 ATA_CMD_WRITE_MULTI_EXT,
9a3dccc4
TH		 164 0,
165 0,
166 0,
167 ATA_CMD_WRITE_MULTI_FUA_EXT,
8cbd6df1
AL		 168 /* pio */
169 ATA_CMD_PIO_READ,
170 ATA_CMD_PIO_WRITE,
171 ATA_CMD_PIO_READ_EXT,
172 ATA_CMD_PIO_WRITE_EXT,
9a3dccc4
TH		 173 0,
174 0,
175 0,
176 0,
8cbd6df1
AL		 177 /* dma */
178 ATA_CMD_READ,
179 ATA_CMD_WRITE,
180 ATA_CMD_READ_EXT,
9a3dccc4
TH		 181 ATA_CMD_WRITE_EXT,
182 0,
183 0,
184 0,
185 ATA_CMD_WRITE_FUA_EXT
8cbd6df1 186};
1da177e4
LT		 187
188/**
8cbd6df1
AL		 189 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
190 * @qc: command to examine and configure
1da177e4 191 *
8cbd6df1
AL		 192 * Examine the device configuration and tf->flags to calculate
193 * the proper read/write commands and protocol to use.
1da177e4
LT		 194 *
195 * LOCKING:
196 * caller.
197 */
9a3dccc4 198int ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 199{
8cbd6df1
AL		 200 struct ata_taskfile *tf = &qc->tf;
201 struct ata_device *dev = qc->dev;
9a3dccc4 202 u8 cmd;
1da177e4 203
9a3dccc4 204 int index, fua, lba48, write;
8cbd6df1 205
9a3dccc4 206 fua = (tf->flags & ATA_TFLAG_FUA) ? 4 : 0;
8cbd6df1
AL		 207 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
208 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 209
8cbd6df1
AL		 210 if (dev->flags & ATA_DFLAG_PIO) {
211 tf->protocol = ATA_PROT_PIO;
9a3dccc4 212 index = dev->multi_count ? 0 : 8;
8d238e01
AC		 213 } else if (lba48 && (qc->ap->flags & ATA_FLAG_PIO_LBA48)) {
214 /* Unable to use DMA due to host limitation */
215 tf->protocol = ATA_PROT_PIO;
216 index = dev->multi_count ? 0 : 4;
8cbd6df1
AL		 217 } else {
218 tf->protocol = ATA_PROT_DMA;
9a3dccc4 219 index = 16;
8cbd6df1 220 }
1da177e4 221
9a3dccc4
TH		 222 cmd = ata_rw_cmds[index + fua + lba48 + write];
223 if (cmd) {
224 tf->command = cmd;
225 return 0;
226 }
227 return -1;
1da177e4
LT		 228}
229
98ac62de 230static const char * const xfer_mode_str[] = {
1da177e4
LT		 231 "UDMA/16",
232 "UDMA/25",
233 "UDMA/33",
234 "UDMA/44",
235 "UDMA/66",
236 "UDMA/100",
237 "UDMA/133",
238 "UDMA7",
239 "MWDMA0",
240 "MWDMA1",
241 "MWDMA2",
242 "PIO0",
243 "PIO1",
244 "PIO2",
245 "PIO3",
246 "PIO4",
247};
248
249/**
250 * ata_udma_string - convert UDMA bit offset to string
251 * @mask: mask of bits supported; only highest bit counts.
252 *
253 * Determine string which represents the highest speed
254 * (highest bit in @udma_mask).
255 *
256 * LOCKING:
257 * None.
258 *
259 * RETURNS:
260 * Constant C string representing highest speed listed in
261 * @udma_mask, or the constant C string "<n/a>".
262 */
263
264static const char *ata_mode_string(unsigned int mask)
265{
266 int i;
267
268 for (i = 7; i >= 0; i--)
269 if (mask & (1 << i))
270 goto out;
271 for (i = ATA_SHIFT_MWDMA + 2; i >= ATA_SHIFT_MWDMA; i--)
272 if (mask & (1 << i))
273 goto out;
274 for (i = ATA_SHIFT_PIO + 4; i >= ATA_SHIFT_PIO; i--)
275 if (mask & (1 << i))
276 goto out;
277
278 return "<n/a>";
279
280out:
281 return xfer_mode_str[i];
282}
283
284/**
285 * ata_pio_devchk - PATA device presence detection
286 * @ap: ATA channel to examine
287 * @device: Device to examine (starting at zero)
288 *
289 * This technique was originally described in
290 * Hale Landis's ATADRVR (www.ata-atapi.com), and
291 * later found its way into the ATA/ATAPI spec.
292 *
293 * Write a pattern to the ATA shadow registers,
294 * and if a device is present, it will respond by
295 * correctly storing and echoing back the
296 * ATA shadow register contents.
297 *
298 * LOCKING:
299 * caller.
300 */
301
302static unsigned int ata_pio_devchk(struct ata_port *ap,
303 unsigned int device)
304{
305 struct ata_ioports *ioaddr = &ap->ioaddr;
306 u8 nsect, lbal;
307
308 ap->ops->dev_select(ap, device);
309
310 outb(0x55, ioaddr->nsect_addr);
311 outb(0xaa, ioaddr->lbal_addr);
312
313 outb(0xaa, ioaddr->nsect_addr);
314 outb(0x55, ioaddr->lbal_addr);
315
316 outb(0x55, ioaddr->nsect_addr);
317 outb(0xaa, ioaddr->lbal_addr);
318
319 nsect = inb(ioaddr->nsect_addr);
320 lbal = inb(ioaddr->lbal_addr);
321
322 if ((nsect == 0x55) && (lbal == 0xaa))
323 return 1; /* we found a device */
324
325 return 0; /* nothing found */
326}
327
328/**
329 * ata_mmio_devchk - PATA device presence detection
330 * @ap: ATA channel to examine
331 * @device: Device to examine (starting at zero)
332 *
333 * This technique was originally described in
334 * Hale Landis's ATADRVR (www.ata-atapi.com), and
335 * later found its way into the ATA/ATAPI spec.
336 *
337 * Write a pattern to the ATA shadow registers,
338 * and if a device is present, it will respond by
339 * correctly storing and echoing back the
340 * ATA shadow register contents.
341 *
342 * LOCKING:
343 * caller.
344 */
345
346static unsigned int ata_mmio_devchk(struct ata_port *ap,
347 unsigned int device)
348{
349 struct ata_ioports *ioaddr = &ap->ioaddr;
350 u8 nsect, lbal;
351
352 ap->ops->dev_select(ap, device);
353
354 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
355 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
356
357 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
358 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
359
360 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
361 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
362
363 nsect = readb((void __iomem *) ioaddr->nsect_addr);
364 lbal = readb((void __iomem *) ioaddr->lbal_addr);
365
366 if ((nsect == 0x55) && (lbal == 0xaa))
367 return 1; /* we found a device */
368
369 return 0; /* nothing found */
370}
371
372/**
373 * ata_devchk - PATA device presence detection
374 * @ap: ATA channel to examine
375 * @device: Device to examine (starting at zero)
376 *
377 * Dispatch ATA device presence detection, depending
378 * on whether we are using PIO or MMIO to talk to the
379 * ATA shadow registers.
380 *
381 * LOCKING:
382 * caller.
383 */
384
385static unsigned int ata_devchk(struct ata_port *ap,
386 unsigned int device)
387{
388 if (ap->flags & ATA_FLAG_MMIO)
389 return ata_mmio_devchk(ap, device);
390 return ata_pio_devchk(ap, device);
391}
392
393/**
394 * ata_dev_classify - determine device type based on ATA-spec signature
395 * @tf: ATA taskfile register set for device to be identified
396 *
397 * Determine from taskfile register contents whether a device is
398 * ATA or ATAPI, as per "Signature and persistence" section
399 * of ATA/PI spec (volume 1, sect 5.14).
400 *
401 * LOCKING:
402 * None.
403 *
404 * RETURNS:
405 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
406 * the event of failure.
407 */
408
057ace5e 409unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 410{
411 /* Apple's open source Darwin code hints that some devices only
412 * put a proper signature into the LBA mid/high registers,
413 * So, we only check those. It's sufficient for uniqueness.
414 */
415
416 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
417 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
418 DPRINTK("found ATA device by sig\n");
419 return ATA_DEV_ATA;
420 }
421
422 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
423 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
424 DPRINTK("found ATAPI device by sig\n");
425 return ATA_DEV_ATAPI;
426 }
427
428 DPRINTK("unknown device\n");
429 return ATA_DEV_UNKNOWN;
430}
431
432/**
433 * ata_dev_try_classify - Parse returned ATA device signature
434 * @ap: ATA channel to examine
435 * @device: Device to examine (starting at zero)
b4dc7623 436 * @r_err: Value of error register on completion
1da177e4
LT		 437 *
438 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
439 * an ATA/ATAPI-defined set of values is placed in the ATA
440 * shadow registers, indicating the results of device detection
441 * and diagnostics.
442 *
443 * Select the ATA device, and read the values from the ATA shadow
444 * registers. Then parse according to the Error register value,
445 * and the spec-defined values examined by ata_dev_classify().
446 *
447 * LOCKING:
448 * caller.
b4dc7623
TH		 449 *
450 * RETURNS:
451 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1da177e4
LT		 452 */
453
b4dc7623
TH		 454static unsigned int
455ata_dev_try_classify(struct ata_port *ap, unsigned int device, u8 *r_err)
1da177e4 456{
1da177e4
LT		 457 struct ata_taskfile tf;
458 unsigned int class;
459 u8 err;
460
461 ap->ops->dev_select(ap, device);
462
463 memset(&tf, 0, sizeof(tf));
464
1da177e4 465 ap->ops->tf_read(ap, &tf);
0169e284 466 err = tf.feature;
b4dc7623
TH		 467 if (r_err)
468 *r_err = err;
1da177e4
LT		 469
470 /* see if device passed diags */
471 if (err == 1)
472 /* do nothing */ ;
473 else if ((device == 0) && (err == 0x81))
474 /* do nothing */ ;
475 else
b4dc7623 476 return ATA_DEV_NONE;
1da177e4 477
b4dc7623 478 /* determine if device is ATA or ATAPI */
1da177e4 479 class = ata_dev_classify(&tf);
b4dc7623 480
1da177e4 481 if (class == ATA_DEV_UNKNOWN)
b4dc7623 482 return ATA_DEV_NONE;
1da177e4 483 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
b4dc7623
TH		 484 return ATA_DEV_NONE;
485 return class;
1da177e4
LT		 486}
487
488/**
489 * ata_dev_id_string - Convert IDENTIFY DEVICE page into string
490 * @id: IDENTIFY DEVICE results we will examine
491 * @s: string into which data is output
492 * @ofs: offset into identify device page
493 * @len: length of string to return. must be an even number.
494 *
495 * The strings in the IDENTIFY DEVICE page are broken up into
496 * 16-bit chunks. Run through the string, and output each
497 * 8-bit chunk linearly, regardless of platform.
498 *
499 * LOCKING:
500 * caller.
501 */
502
057ace5e 503void ata_dev_id_string(const u16 *id, unsigned char *s,
1da177e4
LT		 504 unsigned int ofs, unsigned int len)
505{
506 unsigned int c;
507
508 while (len > 0) {
509 c = id[ofs] >> 8;
510 *s = c;
511 s++;
512
513 c = id[ofs] & 0xff;
514 *s = c;
515 s++;
516
517 ofs++;
518 len -= 2;
519 }
520}
521
0e949ff3
TH		 522/**
523 * ata_dev_id_c_string - Convert IDENTIFY DEVICE page into C string
524 * @id: IDENTIFY DEVICE results we will examine
525 * @s: string into which data is output
526 * @ofs: offset into identify device page
527 * @len: length of string to return. must be an odd number.
528 *
529 * This function is identical to ata_dev_id_string except that it
530 * trims trailing spaces and terminates the resulting string with
531 * null. @len must be actual maximum length (even number) + 1.
532 *
533 * LOCKING:
534 * caller.
535 */
536void ata_dev_id_c_string(const u16 *id, unsigned char *s,
537 unsigned int ofs, unsigned int len)
538{
539 unsigned char *p;
540
541 WARN_ON(!(len & 1));
542
543 ata_dev_id_string(id, s, ofs, len - 1);
544
545 p = s + strnlen(s, len - 1);
546 while (p > s && p[-1] == ' ')
547 p--;
548 *p = '\0';
549}
0baab86b 550
2940740b
TH		 551static u64 ata_id_n_sectors(const u16 *id)
552{
553 if (ata_id_has_lba(id)) {
554 if (ata_id_has_lba48(id))
555 return ata_id_u64(id, 100);
556 else
557 return ata_id_u32(id, 60);
558 } else {
559 if (ata_id_current_chs_valid(id))
560 return ata_id_u32(id, 57);
561 else
562 return id[1] * id[3] * id[6];
563 }
564}
565
0baab86b
EF		 566/**
567 * ata_noop_dev_select - Select device 0/1 on ATA bus
568 * @ap: ATA channel to manipulate
569 * @device: ATA device (numbered from zero) to select
570 *
571 * This function performs no actual function.
572 *
573 * May be used as the dev_select() entry in ata_port_operations.
574 *
575 * LOCKING:
576 * caller.
577 */
1da177e4
LT		 578void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
579{
580}
581
0baab86b 582
1da177e4
LT		 583/**
584 * ata_std_dev_select - Select device 0/1 on ATA bus
585 * @ap: ATA channel to manipulate
586 * @device: ATA device (numbered from zero) to select
587 *
588 * Use the method defined in the ATA specification to
589 * make either device 0, or device 1, active on the
0baab86b
EF		 590 * ATA channel. Works with both PIO and MMIO.
591 *
592 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 593 *
594 * LOCKING:
595 * caller.
596 */
597
598void ata_std_dev_select (struct ata_port *ap, unsigned int device)
599{
600 u8 tmp;
601
602 if (device == 0)
603 tmp = ATA_DEVICE_OBS;
604 else
605 tmp = ATA_DEVICE_OBS | ATA_DEV1;
606
607 if (ap->flags & ATA_FLAG_MMIO) {
608 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
609 } else {
610 outb(tmp, ap->ioaddr.device_addr);
611 }
612 ata_pause(ap); /* needed; also flushes, for mmio */
613}
614
615/**
616 * ata_dev_select - Select device 0/1 on ATA bus
617 * @ap: ATA channel to manipulate
618 * @device: ATA device (numbered from zero) to select
619 * @wait: non-zero to wait for Status register BSY bit to clear
620 * @can_sleep: non-zero if context allows sleeping
621 *
622 * Use the method defined in the ATA specification to
623 * make either device 0, or device 1, active on the
624 * ATA channel.
625 *
626 * This is a high-level version of ata_std_dev_select(),
627 * which additionally provides the services of inserting
628 * the proper pauses and status polling, where needed.
629 *
630 * LOCKING:
631 * caller.
632 */
633
634void ata_dev_select(struct ata_port *ap, unsigned int device,
635 unsigned int wait, unsigned int can_sleep)
636{
637 VPRINTK("ENTER, ata%u: device %u, wait %u\n",
638 ap->id, device, wait);
639
640 if (wait)
641 ata_wait_idle(ap);
642
643 ap->ops->dev_select(ap, device);
644
645 if (wait) {
646 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
647 msleep(150);
648 ata_wait_idle(ap);
649 }
650}
651
652/**
653 * ata_dump_id - IDENTIFY DEVICE info debugging output
0bd3300a 654 * @id: IDENTIFY DEVICE page to dump
1da177e4 655 *
0bd3300a
TH		 656 * Dump selected 16-bit words from the given IDENTIFY DEVICE
657 * page.
1da177e4
LT		 658 *
659 * LOCKING:
660 * caller.
661 */
662
0bd3300a 663static inline void ata_dump_id(const u16 *id)
1da177e4
LT		 664{
665 DPRINTK("49==0x%04x "
666 "53==0x%04x "
667 "63==0x%04x "
668 "64==0x%04x "
669 "75==0x%04x \n",
0bd3300a
TH		 670 id[49],
671 id[53],
672 id[63],
673 id[64],
674 id[75]);
1da177e4
LT		 675 DPRINTK("80==0x%04x "
676 "81==0x%04x "
677 "82==0x%04x "
678 "83==0x%04x "
679 "84==0x%04x \n",
0bd3300a
TH		 680 id[80],
681 id[81],
682 id[82],
683 id[83],
684 id[84]);
1da177e4
LT		 685 DPRINTK("88==0x%04x "
686 "93==0x%04x\n",
0bd3300a
TH		 687 id[88],
688 id[93]);
1da177e4
LT		 689}
690
11e29e21
AC		 691/*
692 * Compute the PIO modes available for this device. This is not as
693 * trivial as it seems if we must consider early devices correctly.
694 *
695 * FIXME: pre IDE drive timing (do we care ?).
696 */
697
057ace5e 698static unsigned int ata_pio_modes(const struct ata_device *adev)
11e29e21
AC		 699{
700 u16 modes;
701
ffa29456
AC		 702 /* Usual case. Word 53 indicates word 64 is valid */
703 if (adev->id[ATA_ID_FIELD_VALID] & (1 << 1)) {
11e29e21
AC		 704 modes = adev->id[ATA_ID_PIO_MODES] & 0x03;
705 modes <<= 3;
706 modes |= 0x7;
707 return modes;
708 }
709
ffa29456
AC		 710 /* If word 64 isn't valid then Word 51 high byte holds the PIO timing
711 number for the maximum. Turn it into a mask and return it */
712 modes = (2 << ((adev->id[ATA_ID_OLD_PIO_MODES] >> 8) & 0xFF)) - 1 ;
11e29e21 713 return modes;
ffa29456
AC		 714 /* But wait.. there's more. Design your standards by committee and
715 you too can get a free iordy field to process. However its the
716 speeds not the modes that are supported... Note drivers using the
717 timing API will get this right anyway */
11e29e21
AC		 718}
719
95064379
TH		 720static inline void
721ata_queue_packet_task(struct ata_port *ap)
722{
c18d06f8
TH		 723 if (!(ap->flags & ATA_FLAG_FLUSH_PIO_TASK))
724 queue_work(ata_wq, &ap->packet_task);
95064379
TH		 725}
726
727static inline void
728ata_queue_pio_task(struct ata_port *ap)
729{
c18d06f8
TH		 730 if (!(ap->flags & ATA_FLAG_FLUSH_PIO_TASK))
731 queue_work(ata_wq, &ap->pio_task);
95064379
TH		 732}
733
734static inline void
735ata_queue_delayed_pio_task(struct ata_port *ap, unsigned long delay)
736{
c18d06f8
TH		 737 if (!(ap->flags & ATA_FLAG_FLUSH_PIO_TASK))
738 queue_delayed_work(ata_wq, &ap->pio_task, delay);
739}
740
741/**
742 * ata_flush_pio_tasks - Flush pio_task and packet_task
743 * @ap: the target ata_port
744 *
745 * After this function completes, pio_task and packet_task are
746 * guranteed not to be running or scheduled.
747 *
748 * LOCKING:
749 * Kernel thread context (may sleep)
750 */
751
752static void ata_flush_pio_tasks(struct ata_port *ap)
753{
754 int tmp = 0;
755 unsigned long flags;
756
757 DPRINTK("ENTER\n");
758
759 spin_lock_irqsave(&ap->host_set->lock, flags);
760 ap->flags |= ATA_FLAG_FLUSH_PIO_TASK;
761 spin_unlock_irqrestore(&ap->host_set->lock, flags);
762
763 DPRINTK("flush #1\n");
764 flush_workqueue(ata_wq);
765
766 /*
767 * At this point, if a task is running, it's guaranteed to see
768 * the FLUSH flag; thus, it will never queue pio tasks again.
769 * Cancel and flush.
770 */
771 tmp |= cancel_delayed_work(&ap->pio_task);
772 tmp |= cancel_delayed_work(&ap->packet_task);
773 if (!tmp) {
774 DPRINTK("flush #2\n");
775 flush_workqueue(ata_wq);
776 }
777
778 spin_lock_irqsave(&ap->host_set->lock, flags);
779 ap->flags &= ~ATA_FLAG_FLUSH_PIO_TASK;
780 spin_unlock_irqrestore(&ap->host_set->lock, flags);
781
782 DPRINTK("EXIT\n");
95064379
TH		 783}
784
77853bf2 785void ata_qc_complete_internal(struct ata_queued_cmd *qc)
a2a7a662 786{
77853bf2 787 struct completion *waiting = qc->private_data;
a2a7a662 788
77853bf2 789 qc->ap->ops->tf_read(qc->ap, &qc->tf);
a2a7a662 790 complete(waiting);
a2a7a662
TH		 791}
792
793/**
794 * ata_exec_internal - execute libata internal command
795 * @ap: Port to which the command is sent
796 * @dev: Device to which the command is sent
797 * @tf: Taskfile registers for the command and the result
798 * @dma_dir: Data tranfer direction of the command
799 * @buf: Data buffer of the command
800 * @buflen: Length of data buffer
801 *
802 * Executes libata internal command with timeout. @tf contains
803 * command on entry and result on return. Timeout and error
804 * conditions are reported via return value. No recovery action
805 * is taken after a command times out. It's caller's duty to
806 * clean up after timeout.
807 *
808 * LOCKING:
809 * None. Should be called with kernel context, might sleep.
810 */
811
812static unsigned
813ata_exec_internal(struct ata_port *ap, struct ata_device *dev,
814 struct ata_taskfile *tf,
815 int dma_dir, void *buf, unsigned int buflen)
816{
817 u8 command = tf->command;
818 struct ata_queued_cmd *qc;
819 DECLARE_COMPLETION(wait);
820 unsigned long flags;
77853bf2 821 unsigned int err_mask;
a2a7a662
TH		 822
823 spin_lock_irqsave(&ap->host_set->lock, flags);
824
825 qc = ata_qc_new_init(ap, dev);
826 BUG_ON(qc == NULL);
827
828 qc->tf = *tf;
829 qc->dma_dir = dma_dir;
830 if (dma_dir != DMA_NONE) {
831 ata_sg_init_one(qc, buf, buflen);
832 qc->nsect = buflen / ATA_SECT_SIZE;
833 }
834
77853bf2 835 qc->private_data = &wait;
a2a7a662
TH		 836 qc->complete_fn = ata_qc_complete_internal;
837
9a3d9eb0
TH		 838 qc->err_mask = ata_qc_issue(qc);
839 if (qc->err_mask)
8e436af9 840 ata_qc_complete(qc);
a2a7a662
TH		 841
842 spin_unlock_irqrestore(&ap->host_set->lock, flags);
843
844 if (!wait_for_completion_timeout(&wait, ATA_TMOUT_INTERNAL)) {
845 spin_lock_irqsave(&ap->host_set->lock, flags);
846
847 /* We're racing with irq here. If we lose, the
848 * following test prevents us from completing the qc
849 * again. If completion irq occurs after here but
850 * before the caller cleans up, it will result in a
851 * spurious interrupt. We can live with that.
852 */
77853bf2 853 if (qc->flags & ATA_QCFLAG_ACTIVE) {
11a56d24 854 qc->err_mask = AC_ERR_TIMEOUT;
a2a7a662
TH		 855 ata_qc_complete(qc);
856 printk(KERN_WARNING "ata%u: qc timeout (cmd 0x%x)\n",
857 ap->id, command);
858 }
859
860 spin_unlock_irqrestore(&ap->host_set->lock, flags);
861 }
862
77853bf2
TH		 863 *tf = qc->tf;
864 err_mask = qc->err_mask;
865
866 ata_qc_free(qc);
867
868 return err_mask;
a2a7a662
TH		 869}
870
1bc4ccff
AC		 871/**
872 * ata_pio_need_iordy - check if iordy needed
873 * @adev: ATA device
874 *
875 * Check if the current speed of the device requires IORDY. Used
876 * by various controllers for chip configuration.
877 */
878
879unsigned int ata_pio_need_iordy(const struct ata_device *adev)
880{
881 int pio;
882 int speed = adev->pio_mode - XFER_PIO_0;
883
884 if (speed < 2)
885 return 0;
886 if (speed > 2)
887 return 1;
888
889 /* If we have no drive specific rule, then PIO 2 is non IORDY */
890
891 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE */
892 pio = adev->id[ATA_ID_EIDE_PIO];
893 /* Is the speed faster than the drive allows non IORDY ? */
894 if (pio) {
895 /* This is cycle times not frequency - watch the logic! */
896 if (pio > 240) /* PIO2 is 240nS per cycle */
897 return 1;
898 return 0;
899 }
900 }
901 return 0;
902}
903
1da177e4
LT		 904/**
905 * ata_dev_identify - obtain IDENTIFY x DEVICE page
906 * @ap: port on which device we wish to probe resides
907 * @device: device bus address, starting at zero
908 *
909 * Following bus reset, we issue the IDENTIFY [PACKET] DEVICE
910 * command, and read back the 512-byte device information page.
911 * The device information page is fed to us via the standard
912 * PIO-IN protocol, but we hand-code it here. (TODO: investigate
913 * using standard PIO-IN paths)
914 *
915 * After reading the device information page, we use several
916 * bits of information from it to initialize data structures
917 * that will be used during the lifetime of the ata_device.
918 * Other data from the info page is used to disqualify certain
919 * older ATA devices we do not wish to support.
920 *
921 * LOCKING:
922 * Inherited from caller. Some functions called by this function
923 * obtain the host_set lock.
924 */
925
926static void ata_dev_identify(struct ata_port *ap, unsigned int device)
927{
928 struct ata_device *dev = &ap->device[device];
8bf62ece 929 unsigned int major_version;
1da177e4 930 unsigned long xfer_modes;
1da177e4 931 unsigned int using_edd;
a0123703
TH		 932 struct ata_taskfile tf;
933 unsigned int err_mask;
1da177e4
LT		 934 int rc;
935
936 if (!ata_dev_present(dev)) {
937 DPRINTK("ENTER/EXIT (host %u, dev %u) -- nodev\n",
938 ap->id, device);
939 return;
940 }
941
61eb066a
TH		 942 if (ap->ops->probe_reset ||
943 ap->flags & (ATA_FLAG_SRST | ATA_FLAG_SATA_RESET))
1da177e4
LT		 944 using_edd = 0;
945 else
946 using_edd = 1;
947
948 DPRINTK("ENTER, host %u, dev %u\n", ap->id, device);
949
a4631474
TH		 950 WARN_ON(dev->class != ATA_DEV_ATA && dev->class != ATA_DEV_ATAPI &&
951 dev->class != ATA_DEV_NONE);
1da177e4
LT		 952
953 ata_dev_select(ap, device, 1, 1); /* select device 0/1 */
954
1da177e4 955retry:
a0123703
TH		 956 ata_tf_init(ap, &tf, device);
957
1da177e4 958 if (dev->class == ATA_DEV_ATA) {
a0123703 959 tf.command = ATA_CMD_ID_ATA;
1da177e4
LT		 960 DPRINTK("do ATA identify\n");
961 } else {
a0123703 962 tf.command = ATA_CMD_ID_ATAPI;
1da177e4
LT		 963 DPRINTK("do ATAPI identify\n");
964 }
965
a0123703 966 tf.protocol = ATA_PROT_PIO;
1da177e4 967
a0123703
TH		 968 err_mask = ata_exec_internal(ap, dev, &tf, DMA_FROM_DEVICE,
969 dev->id, sizeof(dev->id));
1da177e4 970
a0123703
TH		 971 if (err_mask) {
972 if (err_mask & ~AC_ERR_DEV)
973 goto err_out;
0169e284 974
1da177e4
LT		 975 /*
976 * arg! EDD works for all test cases, but seems to return
977 * the ATA signature for some ATAPI devices. Until the
978 * reason for this is found and fixed, we fix up the mess
979 * here. If IDENTIFY DEVICE returns command aborted
980 * (as ATAPI devices do), then we issue an
981 * IDENTIFY PACKET DEVICE.
982 *
983 * ATA software reset (SRST, the default) does not appear
984 * to have this problem.
985 */
7c398335 986 if ((using_edd) && (dev->class == ATA_DEV_ATA)) {
a0123703 987 u8 err = tf.feature;
1da177e4
LT		 988 if (err & ATA_ABORTED) {
989 dev->class = ATA_DEV_ATAPI;
1da177e4
LT		 990 goto retry;
991 }
992 }
993 goto err_out;
994 }
995
996 swap_buf_le16(dev->id, ATA_ID_WORDS);
997
998 /* print device capabilities */
999 printk(KERN_DEBUG "ata%u: dev %u cfg "
1000 "49:%04x 82:%04x 83:%04x 84:%04x 85:%04x 86:%04x 87:%04x 88:%04x\n",
1001 ap->id, device, dev->id[49],
1002 dev->id[82], dev->id[83], dev->id[84],
1003 dev->id[85], dev->id[86], dev->id[87],
1004 dev->id[88]);
1005
1006 /*
1007 * common ATA, ATAPI feature tests
1008 */
1009
8bf62ece
AL		 1010 /* we require DMA support (bits 8 of word 49) */
1011 if (!ata_id_has_dma(dev->id)) {
1012 printk(KERN_DEBUG "ata%u: no dma\n", ap->id);
1da177e4
LT		 1013 goto err_out_nosup;
1014 }
1015
1016 /* quick-n-dirty find max transfer mode; for printk only */
1017 xfer_modes = dev->id[ATA_ID_UDMA_MODES];
1018 if (!xfer_modes)
1019 xfer_modes = (dev->id[ATA_ID_MWDMA_MODES]) << ATA_SHIFT_MWDMA;
11e29e21
AC		 1020 if (!xfer_modes)
1021 xfer_modes = ata_pio_modes(dev);
1da177e4 1022
0bd3300a 1023 ata_dump_id(dev->id);
1da177e4
LT		 1024
1025 /* ATA-specific feature tests */
1026 if (dev->class == ATA_DEV_ATA) {
2940740b
TH		 1027 dev->n_sectors = ata_id_n_sectors(dev->id);
1028
1da177e4
LT		 1029 if (!ata_id_is_ata(dev->id)) /* sanity check */
1030 goto err_out_nosup;
1031
8bf62ece 1032 /* get major version */
3d2ca910 1033 major_version = ata_id_major_version(dev->id);
1da177e4 1034
8bf62ece
AL		 1035 /*
1036 * The exact sequence expected by certain pre-ATA4 drives is:
1037 * SRST RESET
1038 * IDENTIFY
1039 * INITIALIZE DEVICE PARAMETERS
1040 * anything else..
1041 * Some drives were very specific about that exact sequence.
1042 */
59a10b17 1043 if (major_version < 4 || (!ata_id_has_lba(dev->id))) {
8bf62ece
AL		 1044 ata_dev_init_params(ap, dev);
1045
59a10b17
AL		 1046 /* current CHS translation info (id[53-58]) might be
1047 * changed. reread the identify device info.
1048 */
1049 ata_dev_reread_id(ap, dev);
1050 }
1051
8bf62ece
AL		 1052 if (ata_id_has_lba(dev->id)) {
1053 dev->flags |= ATA_DFLAG_LBA;
1054
2940740b 1055 if (ata_id_has_lba48(dev->id))
8bf62ece 1056 dev->flags |= ATA_DFLAG_LBA48;
8bf62ece
AL		 1057
1058 /* print device info to dmesg */
1059 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors:%s\n",
1060 ap->id, device,
1061 major_version,
1062 ata_mode_string(xfer_modes),
1063 (unsigned long long)dev->n_sectors,
1064 dev->flags & ATA_DFLAG_LBA48 ? " LBA48" : " LBA");
1065 } else {
1066 /* CHS */
1067
1068 /* Default translation */
1069 dev->cylinders = dev->id[1];
1070 dev->heads = dev->id[3];
1071 dev->sectors = dev->id[6];
8bf62ece
AL		 1072
1073 if (ata_id_current_chs_valid(dev->id)) {
1074 /* Current CHS translation is valid. */
1075 dev->cylinders = dev->id[54];
1076 dev->heads = dev->id[55];
1077 dev->sectors = dev->id[56];
8bf62ece
AL		 1078 }
1079
1080 /* print device info to dmesg */
1081 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors: CHS %d/%d/%d\n",
1082 ap->id, device,
1083 major_version,
1084 ata_mode_string(xfer_modes),
1085 (unsigned long long)dev->n_sectors,
1086 (int)dev->cylinders, (int)dev->heads, (int)dev->sectors);
1da177e4 1087
1da177e4
LT		 1088 }
1089
1090 ap->host->max_cmd_len = 16;
1da177e4
LT		 1091 }
1092
1093 /* ATAPI-specific feature tests */
2c13b7ce 1094 else if (dev->class == ATA_DEV_ATAPI) {
1da177e4
LT		 1095 if (ata_id_is_ata(dev->id)) /* sanity check */
1096 goto err_out_nosup;
1097
1098 rc = atapi_cdb_len(dev->id);
1099 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
1100 printk(KERN_WARNING "ata%u: unsupported CDB len\n", ap->id);
1101 goto err_out_nosup;
1102 }
1103 ap->cdb_len = (unsigned int) rc;
1104 ap->host->max_cmd_len = (unsigned char) ap->cdb_len;
1105
1106 /* print device info to dmesg */
1107 printk(KERN_INFO "ata%u: dev %u ATAPI, max %s\n",
1108 ap->id, device,
1109 ata_mode_string(xfer_modes));
1110 }
1111
1112 DPRINTK("EXIT, drv_stat = 0x%x\n", ata_chk_status(ap));
1113 return;
1114
1115err_out_nosup:
1116 printk(KERN_WARNING "ata%u: dev %u not supported, ignoring\n",
1117 ap->id, device);
1118err_out:
1119 dev->class++; /* converts ATA_DEV_xxx into ATA_DEV_xxx_UNSUP */
1120 DPRINTK("EXIT, err\n");
1121}
1122
6f2f3812 1123
8eabd02c
TH		 1124static inline u8 ata_dev_knobble(const struct ata_port *ap,
1125 struct ata_device *dev)
6f2f3812 1126{
8eabd02c 1127 return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(dev->id)));
6f2f3812
BC		 1128}
1129
1130/**
c893a3ae
RD		 1131 * ata_dev_config - Run device specific handlers & check for SATA->PATA bridges
1132 * @ap: Bus
1133 * @i: Device
6f2f3812 1134 *
c893a3ae 1135 * LOCKING:
6f2f3812 1136 */
8a60a071 1137
6f2f3812
BC		 1138void ata_dev_config(struct ata_port *ap, unsigned int i)
1139{
1140 /* limit bridge transfers to udma5, 200 sectors */
8eabd02c 1141 if (ata_dev_knobble(ap, &ap->device[i])) {
6f2f3812 1142 printk(KERN_INFO "ata%u(%u): applying bridge limits\n",
8eabd02c 1143 ap->id, i);
6f2f3812
BC		 1144 ap->udma_mask &= ATA_UDMA5;
1145 ap->host->max_sectors = ATA_MAX_SECTORS;
1146 ap->host->hostt->max_sectors = ATA_MAX_SECTORS;
9d824d07 1147 ap->device[i].flags |= ATA_DFLAG_LOCK_SECTORS;
6f2f3812
BC		 1148 }
1149
1150 if (ap->ops->dev_config)
1151 ap->ops->dev_config(ap, &ap->device[i]);
1152}
1153
1da177e4
LT		 1154/**
1155 * ata_bus_probe - Reset and probe ATA bus
1156 * @ap: Bus to probe
1157 *
0cba632b
JG		 1158 * Master ATA bus probing function. Initiates a hardware-dependent
1159 * bus reset, then attempts to identify any devices found on
1160 * the bus.
1161 *
1da177e4 1162 * LOCKING:
0cba632b 1163 * PCI/etc. bus probe sem.
1da177e4
LT		 1164 *
1165 * RETURNS:
1166 * Zero on success, non-zero on error.
1167 */
1168
1169static int ata_bus_probe(struct ata_port *ap)
1170{
1171 unsigned int i, found = 0;
1172
c19ba8af
TH		 1173 if (ap->ops->probe_reset) {
1174 unsigned int classes[ATA_MAX_DEVICES];
1175 int rc;
1176
1177 ata_port_probe(ap);
1178
1179 rc = ap->ops->probe_reset(ap, classes);
1180 if (rc == 0) {
06ab7822
TH		 1181 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1182 if (classes[i] == ATA_DEV_UNKNOWN)
1183 classes[i] = ATA_DEV_NONE;
c19ba8af 1184 ap->device[i].class = classes[i];
06ab7822 1185 }
c19ba8af
TH		 1186 } else {
1187 printk(KERN_ERR "ata%u: probe reset failed, "
1188 "disabling port\n", ap->id);
1189 ata_port_disable(ap);
1190 }
1191 } else
1192 ap->ops->phy_reset(ap);
1193
1da177e4
LT		 1194 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1195 goto err_out;
1196
1197 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1198 ata_dev_identify(ap, i);
1199 if (ata_dev_present(&ap->device[i])) {
1200 found = 1;
6f2f3812 1201 ata_dev_config(ap,i);
1da177e4
LT		 1202 }
1203 }
1204
1205 if ((!found) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1206 goto err_out_disable;
1207
1208 ata_set_mode(ap);
1209 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1210 goto err_out_disable;
1211
1212 return 0;
1213
1214err_out_disable:
1215 ap->ops->port_disable(ap);
1216err_out:
1217 return -1;
1218}
1219
1220/**
0cba632b
JG		 1221 * ata_port_probe - Mark port as enabled
1222 * @ap: Port for which we indicate enablement
1da177e4 1223 *
0cba632b
JG		 1224 * Modify @ap data structure such that the system
1225 * thinks that the entire port is enabled.
1226 *
1227 * LOCKING: host_set lock, or some other form of
1228 * serialization.
1da177e4
LT		 1229 */
1230
1231void ata_port_probe(struct ata_port *ap)
1232{
1233 ap->flags &= ~ATA_FLAG_PORT_DISABLED;
1234}
1235
3be680b7
TH		 1236/**
1237 * sata_print_link_status - Print SATA link status
1238 * @ap: SATA port to printk link status about
1239 *
1240 * This function prints link speed and status of a SATA link.
1241 *
1242 * LOCKING:
1243 * None.
1244 */
1245static void sata_print_link_status(struct ata_port *ap)
1246{
1247 u32 sstatus, tmp;
1248 const char *speed;
1249
1250 if (!ap->ops->scr_read)
1251 return;
1252
1253 sstatus = scr_read(ap, SCR_STATUS);
1254
1255 if (sata_dev_present(ap)) {
1256 tmp = (sstatus >> 4) & 0xf;
1257 if (tmp & (1 << 0))
1258 speed = "1.5";
1259 else if (tmp & (1 << 1))
1260 speed = "3.0";
1261 else
1262 speed = "<unknown>";
1263 printk(KERN_INFO "ata%u: SATA link up %s Gbps (SStatus %X)\n",
1264 ap->id, speed, sstatus);
1265 } else {
1266 printk(KERN_INFO "ata%u: SATA link down (SStatus %X)\n",
1267 ap->id, sstatus);
1268 }
1269}
1270
1da177e4 1271/**
780a87f7
JG		 1272 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1273 * @ap: SATA port associated with target SATA PHY.
1da177e4 1274 *
780a87f7
JG		 1275 * This function issues commands to standard SATA Sxxx
1276 * PHY registers, to wake up the phy (and device), and
1277 * clear any reset condition.
1da177e4
LT		 1278 *
1279 * LOCKING:
0cba632b 1280 * PCI/etc. bus probe sem.
1da177e4
LT		 1281 *
1282 */
1283void __sata_phy_reset(struct ata_port *ap)
1284{
1285 u32 sstatus;
1286 unsigned long timeout = jiffies + (HZ * 5);
1287
1288 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e
BR		 1289 /* issue phy wake/reset */
1290 scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1291 /* Couldn't find anything in SATA I/II specs, but
1292 * AHCI-1.1 10.4.2 says at least 1 ms. */
1293 mdelay(1);
1da177e4 1294 }
cdcca89e 1295 scr_write_flush(ap, SCR_CONTROL, 0x300); /* phy wake/clear reset */
1da177e4
LT		 1296
1297 /* wait for phy to become ready, if necessary */
1298 do {
1299 msleep(200);
1300 sstatus = scr_read(ap, SCR_STATUS);
1301 if ((sstatus & 0xf) != 1)
1302 break;
1303 } while (time_before(jiffies, timeout));
1304
3be680b7
TH		 1305 /* print link status */
1306 sata_print_link_status(ap);
656563e3 1307
3be680b7
TH		 1308 /* TODO: phy layer with polling, timeouts, etc. */
1309 if (sata_dev_present(ap))
1da177e4 1310 ata_port_probe(ap);
3be680b7 1311 else
1da177e4 1312 ata_port_disable(ap);
1da177e4
LT		 1313
1314 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1315 return;
1316
1317 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1318 ata_port_disable(ap);
1319 return;
1320 }
1321
1322 ap->cbl = ATA_CBL_SATA;
1323}
1324
1325/**
780a87f7
JG		 1326 * sata_phy_reset - Reset SATA bus.
1327 * @ap: SATA port associated with target SATA PHY.
1da177e4 1328 *
780a87f7
JG		 1329 * This function resets the SATA bus, and then probes
1330 * the bus for devices.
1da177e4
LT		 1331 *
1332 * LOCKING:
0cba632b 1333 * PCI/etc. bus probe sem.
1da177e4
LT		 1334 *
1335 */
1336void sata_phy_reset(struct ata_port *ap)
1337{
1338 __sata_phy_reset(ap);
1339 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1340 return;
1341 ata_bus_reset(ap);
1342}
1343
1344/**
780a87f7
JG		 1345 * ata_port_disable - Disable port.
1346 * @ap: Port to be disabled.
1da177e4 1347 *
780a87f7
JG		 1348 * Modify @ap data structure such that the system
1349 * thinks that the entire port is disabled, and should
1350 * never attempt to probe or communicate with devices
1351 * on this port.
1352 *
1353 * LOCKING: host_set lock, or some other form of
1354 * serialization.
1da177e4
LT		 1355 */
1356
1357void ata_port_disable(struct ata_port *ap)
1358{
1359 ap->device[0].class = ATA_DEV_NONE;
1360 ap->device[1].class = ATA_DEV_NONE;
1361 ap->flags |= ATA_FLAG_PORT_DISABLED;
1362}
1363
452503f9
AC		 1364/*
1365 * This mode timing computation functionality is ported over from
1366 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1367 */
1368/*
1369 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
1370 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
1371 * for PIO 5, which is a nonstandard extension and UDMA6, which
1372 * is currently supported only by Maxtor drives.
1373 */
1374
1375static const struct ata_timing ata_timing[] = {
1376
1377 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1378 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1379 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1380 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1381
1382 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1383 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1384 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1385
1386/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
1387
1388 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1389 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1390 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
1391
1392 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1393 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1394 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1395
1396/* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */
1397 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1398 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1399
1400 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1401 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1402 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1403
1404/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1405
1406 { 0xFF }
1407};
1408
1409#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
1410#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1411
1412static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
1413{
1414 q->setup = EZ(t->setup * 1000, T);
1415 q->act8b = EZ(t->act8b * 1000, T);
1416 q->rec8b = EZ(t->rec8b * 1000, T);
1417 q->cyc8b = EZ(t->cyc8b * 1000, T);
1418 q->active = EZ(t->active * 1000, T);
1419 q->recover = EZ(t->recover * 1000, T);
1420 q->cycle = EZ(t->cycle * 1000, T);
1421 q->udma = EZ(t->udma * 1000, UT);
1422}
1423
1424void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
1425 struct ata_timing *m, unsigned int what)
1426{
1427 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
1428 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
1429 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
1430 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
1431 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
1432 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
1433 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
1434 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
1435}
1436
1437static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
1438{
1439 const struct ata_timing *t;
1440
1441 for (t = ata_timing; t->mode != speed; t++)
91190758 1442 if (t->mode == 0xFF)
452503f9
AC		 1443 return NULL;
1444 return t;
1445}
1446
1447int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1448 struct ata_timing *t, int T, int UT)
1449{
1450 const struct ata_timing *s;
1451 struct ata_timing p;
1452
1453 /*
1454 * Find the mode.
75b1f2f8 1455 */
452503f9
AC		 1456
1457 if (!(s = ata_timing_find_mode(speed)))
1458 return -EINVAL;
1459
75b1f2f8
AL		 1460 memcpy(t, s, sizeof(*s));
1461
452503f9
AC		 1462 /*
1463 * If the drive is an EIDE drive, it can tell us it needs extended
1464 * PIO/MW_DMA cycle timing.
1465 */
1466
1467 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
1468 memset(&p, 0, sizeof(p));
1469 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
1470 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
1471 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
1472 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
1473 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
1474 }
1475 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
1476 }
1477
1478 /*
1479 * Convert the timing to bus clock counts.
1480 */
1481
75b1f2f8 1482 ata_timing_quantize(t, t, T, UT);
452503f9
AC		 1483
1484 /*
c893a3ae
RD		 1485 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
1486 * S.M.A.R.T * and some other commands. We have to ensure that the
1487 * DMA cycle timing is slower/equal than the fastest PIO timing.
452503f9
AC		 1488 */
1489
1490 if (speed > XFER_PIO_4) {
1491 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
1492 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
1493 }
1494
1495 /*
c893a3ae 1496 * Lengthen active & recovery time so that cycle time is correct.
452503f9
AC		 1497 */
1498
1499 if (t->act8b + t->rec8b < t->cyc8b) {
1500 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
1501 t->rec8b = t->cyc8b - t->act8b;
1502 }
1503
1504 if (t->active + t->recover < t->cycle) {
1505 t->active += (t->cycle - (t->active + t->recover)) / 2;
1506 t->recover = t->cycle - t->active;
1507 }
1508
1509 return 0;
1510}
1511
057ace5e 1512static const struct {
1da177e4
LT		 1513 unsigned int shift;
1514 u8 base;
1515} xfer_mode_classes[] = {
1516 { ATA_SHIFT_UDMA, XFER_UDMA_0 },
1517 { ATA_SHIFT_MWDMA, XFER_MW_DMA_0 },
1518 { ATA_SHIFT_PIO, XFER_PIO_0 },
1519};
1520
858119e1 1521static u8 base_from_shift(unsigned int shift)
1da177e4
LT		 1522{
1523 int i;
1524
1525 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++)
1526 if (xfer_mode_classes[i].shift == shift)
1527 return xfer_mode_classes[i].base;
1528
1529 return 0xff;
1530}
1531
1532static void ata_dev_set_mode(struct ata_port *ap, struct ata_device *dev)
1533{
1534 int ofs, idx;
1535 u8 base;
1536
1537 if (!ata_dev_present(dev) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1538 return;
1539
1540 if (dev->xfer_shift == ATA_SHIFT_PIO)
1541 dev->flags |= ATA_DFLAG_PIO;
1542
1543 ata_dev_set_xfermode(ap, dev);
1544
1545 base = base_from_shift(dev->xfer_shift);
1546 ofs = dev->xfer_mode - base;
1547 idx = ofs + dev->xfer_shift;
1548 WARN_ON(idx >= ARRAY_SIZE(xfer_mode_str));
1549
1550 DPRINTK("idx=%d xfer_shift=%u, xfer_mode=0x%x, base=0x%x, offset=%d\n",
1551 idx, dev->xfer_shift, (int)dev->xfer_mode, (int)base, ofs);
1552
1553 printk(KERN_INFO "ata%u: dev %u configured for %s\n",
1554 ap->id, dev->devno, xfer_mode_str[idx]);
1555}
1556
1557static int ata_host_set_pio(struct ata_port *ap)
1558{
1559 unsigned int mask;
1560 int x, i;
1561 u8 base, xfer_mode;
1562
1563 mask = ata_get_mode_mask(ap, ATA_SHIFT_PIO);
1564 x = fgb(mask);
1565 if (x < 0) {
1566 printk(KERN_WARNING "ata%u: no PIO support\n", ap->id);
1567 return -1;
1568 }
1569
1570 base = base_from_shift(ATA_SHIFT_PIO);
1571 xfer_mode = base + x;
1572
1573 DPRINTK("base 0x%x xfer_mode 0x%x mask 0x%x x %d\n",
1574 (int)base, (int)xfer_mode, mask, x);
1575
1576 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1577 struct ata_device *dev = &ap->device[i];
1578 if (ata_dev_present(dev)) {
1579 dev->pio_mode = xfer_mode;
1580 dev->xfer_mode = xfer_mode;
1581 dev->xfer_shift = ATA_SHIFT_PIO;
1582 if (ap->ops->set_piomode)
1583 ap->ops->set_piomode(ap, dev);
1584 }
1585 }
1586
1587 return 0;
1588}
1589
1590static void ata_host_set_dma(struct ata_port *ap, u8 xfer_mode,
1591 unsigned int xfer_shift)
1592{
1593 int i;
1594
1595 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1596 struct ata_device *dev = &ap->device[i];
1597 if (ata_dev_present(dev)) {
1598 dev->dma_mode = xfer_mode;
1599 dev->xfer_mode = xfer_mode;
1600 dev->xfer_shift = xfer_shift;
1601 if (ap->ops->set_dmamode)
1602 ap->ops->set_dmamode(ap, dev);
1603 }
1604 }
1605}
1606
1607/**
1608 * ata_set_mode - Program timings and issue SET FEATURES - XFER
1609 * @ap: port on which timings will be programmed
1610 *
780a87f7
JG		 1611 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.).
1612 *
1da177e4 1613 * LOCKING:
0cba632b 1614 * PCI/etc. bus probe sem.
1da177e4
LT		 1615 */
1616static void ata_set_mode(struct ata_port *ap)
1617{
8cbd6df1 1618 unsigned int xfer_shift;
1da177e4
LT		 1619 u8 xfer_mode;
1620 int rc;
1621
1622 /* step 1: always set host PIO timings */
1623 rc = ata_host_set_pio(ap);
1624 if (rc)
1625 goto err_out;
1626
1627 /* step 2: choose the best data xfer mode */
1628 xfer_mode = xfer_shift = 0;
1629 rc = ata_choose_xfer_mode(ap, &xfer_mode, &xfer_shift);
1630 if (rc)
1631 goto err_out;
1632
1633 /* step 3: if that xfer mode isn't PIO, set host DMA timings */
1634 if (xfer_shift != ATA_SHIFT_PIO)
1635 ata_host_set_dma(ap, xfer_mode, xfer_shift);
1636
1637 /* step 4: update devices' xfer mode */
1638 ata_dev_set_mode(ap, &ap->device[0]);
1639 ata_dev_set_mode(ap, &ap->device[1]);
1640
1641 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1642 return;
1643
1644 if (ap->ops->post_set_mode)
1645 ap->ops->post_set_mode(ap);
1646
1da177e4
LT		 1647 return;
1648
1649err_out:
1650 ata_port_disable(ap);
1651}
1652
1fdffbce
JG		 1653/**
1654 * ata_tf_to_host - issue ATA taskfile to host controller
1655 * @ap: port to which command is being issued
1656 * @tf: ATA taskfile register set
1657 *
1658 * Issues ATA taskfile register set to ATA host controller,
1659 * with proper synchronization with interrupt handler and
1660 * other threads.
1661 *
1662 * LOCKING:
1663 * spin_lock_irqsave(host_set lock)
1664 */
1665
1666static inline void ata_tf_to_host(struct ata_port *ap,
1667 const struct ata_taskfile *tf)
1668{
1669 ap->ops->tf_load(ap, tf);
1670 ap->ops->exec_command(ap, tf);
1671}
1672
1da177e4
LT		 1673/**
1674 * ata_busy_sleep - sleep until BSY clears, or timeout
1675 * @ap: port containing status register to be polled
1676 * @tmout_pat: impatience timeout
1677 * @tmout: overall timeout
1678 *
780a87f7
JG		 1679 * Sleep until ATA Status register bit BSY clears,
1680 * or a timeout occurs.
1681 *
1682 * LOCKING: None.
1da177e4
LT		 1683 */
1684
6f8b9958
TH		 1685unsigned int ata_busy_sleep (struct ata_port *ap,
1686 unsigned long tmout_pat, unsigned long tmout)
1da177e4
LT		 1687{
1688 unsigned long timer_start, timeout;
1689 u8 status;
1690
1691 status = ata_busy_wait(ap, ATA_BUSY, 300);
1692 timer_start = jiffies;
1693 timeout = timer_start + tmout_pat;
1694 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1695 msleep(50);
1696 status = ata_busy_wait(ap, ATA_BUSY, 3);
1697 }
1698
1699 if (status & ATA_BUSY)
1700 printk(KERN_WARNING "ata%u is slow to respond, "
1701 "please be patient\n", ap->id);
1702
1703 timeout = timer_start + tmout;
1704 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1705 msleep(50);
1706 status = ata_chk_status(ap);
1707 }
1708
1709 if (status & ATA_BUSY) {
1710 printk(KERN_ERR "ata%u failed to respond (%lu secs)\n",
1711 ap->id, tmout / HZ);
1712 return 1;
1713 }
1714
1715 return 0;
1716}
1717
1718static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
1719{
1720 struct ata_ioports *ioaddr = &ap->ioaddr;
1721 unsigned int dev0 = devmask & (1 << 0);
1722 unsigned int dev1 = devmask & (1 << 1);
1723 unsigned long timeout;
1724
1725 /* if device 0 was found in ata_devchk, wait for its
1726 * BSY bit to clear
1727 */
1728 if (dev0)
1729 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1730
1731 /* if device 1 was found in ata_devchk, wait for
1732 * register access, then wait for BSY to clear
1733 */
1734 timeout = jiffies + ATA_TMOUT_BOOT;
1735 while (dev1) {
1736 u8 nsect, lbal;
1737
1738 ap->ops->dev_select(ap, 1);
1739 if (ap->flags & ATA_FLAG_MMIO) {
1740 nsect = readb((void __iomem *) ioaddr->nsect_addr);
1741 lbal = readb((void __iomem *) ioaddr->lbal_addr);
1742 } else {
1743 nsect = inb(ioaddr->nsect_addr);
1744 lbal = inb(ioaddr->lbal_addr);
1745 }
1746 if ((nsect == 1) && (lbal == 1))
1747 break;
1748 if (time_after(jiffies, timeout)) {
1749 dev1 = 0;
1750 break;
1751 }
1752 msleep(50); /* give drive a breather */
1753 }
1754 if (dev1)
1755 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1756
1757 /* is all this really necessary? */
1758 ap->ops->dev_select(ap, 0);
1759 if (dev1)
1760 ap->ops->dev_select(ap, 1);
1761 if (dev0)
1762 ap->ops->dev_select(ap, 0);
1763}
1764
1765/**
0cba632b
JG		 1766 * ata_bus_edd - Issue EXECUTE DEVICE DIAGNOSTIC command.
1767 * @ap: Port to reset and probe
1768 *
1769 * Use the EXECUTE DEVICE DIAGNOSTIC command to reset and
1770 * probe the bus. Not often used these days.
1da177e4
LT		 1771 *
1772 * LOCKING:
0cba632b 1773 * PCI/etc. bus probe sem.
e5338254 1774 * Obtains host_set lock.
1da177e4
LT		 1775 *
1776 */
1777
1778static unsigned int ata_bus_edd(struct ata_port *ap)
1779{
1780 struct ata_taskfile tf;
e5338254 1781 unsigned long flags;
1da177e4
LT		 1782
1783 /* set up execute-device-diag (bus reset) taskfile */
1784 /* also, take interrupts to a known state (disabled) */
1785 DPRINTK("execute-device-diag\n");
1786 ata_tf_init(ap, &tf, 0);
1787 tf.ctl |= ATA_NIEN;
1788 tf.command = ATA_CMD_EDD;
1789 tf.protocol = ATA_PROT_NODATA;
1790
1791 /* do bus reset */
e5338254 1792 spin_lock_irqsave(&ap->host_set->lock, flags);
1da177e4 1793 ata_tf_to_host(ap, &tf);
e5338254 1794 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1da177e4
LT		 1795
1796 /* spec says at least 2ms. but who knows with those
1797 * crazy ATAPI devices...
1798 */
1799 msleep(150);
1800
1801 return ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1802}
1803
1804static unsigned int ata_bus_softreset(struct ata_port *ap,
1805 unsigned int devmask)
1806{
1807 struct ata_ioports *ioaddr = &ap->ioaddr;
1808
1809 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
1810
1811 /* software reset. causes dev0 to be selected */
1812 if (ap->flags & ATA_FLAG_MMIO) {
1813 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1814 udelay(20); /* FIXME: flush */
1815 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
1816 udelay(20); /* FIXME: flush */
1817 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1818 } else {
1819 outb(ap->ctl, ioaddr->ctl_addr);
1820 udelay(10);
1821 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1822 udelay(10);
1823 outb(ap->ctl, ioaddr->ctl_addr);
1824 }
1825
1826 /* spec mandates ">= 2ms" before checking status.
1827 * We wait 150ms, because that was the magic delay used for
1828 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1829 * between when the ATA command register is written, and then
1830 * status is checked. Because waiting for "a while" before
1831 * checking status is fine, post SRST, we perform this magic
1832 * delay here as well.
1833 */
1834 msleep(150);
1835
1836 ata_bus_post_reset(ap, devmask);
1837
1838 return 0;
1839}
1840
1841/**
1842 * ata_bus_reset - reset host port and associated ATA channel
1843 * @ap: port to reset
1844 *
1845 * This is typically the first time we actually start issuing
1846 * commands to the ATA channel. We wait for BSY to clear, then
1847 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
1848 * result. Determine what devices, if any, are on the channel
1849 * by looking at the device 0/1 error register. Look at the signature
1850 * stored in each device's taskfile registers, to determine if
1851 * the device is ATA or ATAPI.
1852 *
1853 * LOCKING:
0cba632b
JG		 1854 * PCI/etc. bus probe sem.
1855 * Obtains host_set lock.
1da177e4
LT		 1856 *
1857 * SIDE EFFECTS:
1858 * Sets ATA_FLAG_PORT_DISABLED if bus reset fails.
1859 */
1860
1861void ata_bus_reset(struct ata_port *ap)
1862{
1863 struct ata_ioports *ioaddr = &ap->ioaddr;
1864 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1865 u8 err;
1866 unsigned int dev0, dev1 = 0, rc = 0, devmask = 0;
1867
1868 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
1869
1870 /* determine if device 0/1 are present */
1871 if (ap->flags & ATA_FLAG_SATA_RESET)
1872 dev0 = 1;
1873 else {
1874 dev0 = ata_devchk(ap, 0);
1875 if (slave_possible)
1876 dev1 = ata_devchk(ap, 1);
1877 }
1878
1879 if (dev0)
1880 devmask |= (1 << 0);
1881 if (dev1)
1882 devmask |= (1 << 1);
1883
1884 /* select device 0 again */
1885 ap->ops->dev_select(ap, 0);
1886
1887 /* issue bus reset */
1888 if (ap->flags & ATA_FLAG_SRST)
1889 rc = ata_bus_softreset(ap, devmask);
1890 else if ((ap->flags & ATA_FLAG_SATA_RESET) == 0) {
1891 /* set up device control */
1892 if (ap->flags & ATA_FLAG_MMIO)
1893 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1894 else
1895 outb(ap->ctl, ioaddr->ctl_addr);
1896 rc = ata_bus_edd(ap);
1897 }
1898
1899 if (rc)
1900 goto err_out;
1901
1902 /*
1903 * determine by signature whether we have ATA or ATAPI devices
1904 */
b4dc7623 1905 ap->device[0].class = ata_dev_try_classify(ap, 0, &err);
1da177e4 1906 if ((slave_possible) && (err != 0x81))
b4dc7623 1907 ap->device[1].class = ata_dev_try_classify(ap, 1, &err);
1da177e4
LT		 1908
1909 /* re-enable interrupts */
1910 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
1911 ata_irq_on(ap);
1912
1913 /* is double-select really necessary? */
1914 if (ap->device[1].class != ATA_DEV_NONE)
1915 ap->ops->dev_select(ap, 1);
1916 if (ap->device[0].class != ATA_DEV_NONE)
1917 ap->ops->dev_select(ap, 0);
1918
1919 /* if no devices were detected, disable this port */
1920 if ((ap->device[0].class == ATA_DEV_NONE) &&
1921 (ap->device[1].class == ATA_DEV_NONE))
1922 goto err_out;
1923
1924 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
1925 /* set up device control for ATA_FLAG_SATA_RESET */
1926 if (ap->flags & ATA_FLAG_MMIO)
1927 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1928 else
1929 outb(ap->ctl, ioaddr->ctl_addr);
1930 }
1931
1932 DPRINTK("EXIT\n");
1933 return;
1934
1935err_out:
1936 printk(KERN_ERR "ata%u: disabling port\n", ap->id);
1937 ap->ops->port_disable(ap);
1938
1939 DPRINTK("EXIT\n");
1940}
1941
7a7921e8
TH		 1942static int sata_phy_resume(struct ata_port *ap)
1943{
1944 unsigned long timeout = jiffies + (HZ * 5);
1945 u32 sstatus;
1946
1947 scr_write_flush(ap, SCR_CONTROL, 0x300);
1948
1949 /* Wait for phy to become ready, if necessary. */
1950 do {
1951 msleep(200);
1952 sstatus = scr_read(ap, SCR_STATUS);
1953 if ((sstatus & 0xf) != 1)
1954 return 0;
1955 } while (time_before(jiffies, timeout));
1956
1957 return -1;
1958}
1959
8a19ac89
TH		 1960/**
1961 * ata_std_probeinit - initialize probing
1962 * @ap: port to be probed
1963 *
1964 * @ap is about to be probed. Initialize it. This function is
1965 * to be used as standard callback for ata_drive_probe_reset().
3a39746a
TH		 1966 *
1967 * NOTE!!! Do not use this function as probeinit if a low level
1968 * driver implements only hardreset. Just pass NULL as probeinit
1969 * in that case. Using this function is probably okay but doing
1970 * so makes reset sequence different from the original
1971 * ->phy_reset implementation and Jeff nervous. :-P
8a19ac89
TH		 1972 */
1973extern void ata_std_probeinit(struct ata_port *ap)
1974{
3a39746a 1975 if (ap->flags & ATA_FLAG_SATA && ap->ops->scr_read) {
8a19ac89 1976 sata_phy_resume(ap);
3a39746a
TH		 1977 if (sata_dev_present(ap))
1978 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1979 }
8a19ac89
TH		 1980}
1981
c2bd5804
TH		 1982/**
1983 * ata_std_softreset - reset host port via ATA SRST
1984 * @ap: port to reset
1985 * @verbose: fail verbosely
1986 * @classes: resulting classes of attached devices
1987 *
1988 * Reset host port using ATA SRST. This function is to be used
1989 * as standard callback for ata_drive_*_reset() functions.
1990 *
1991 * LOCKING:
1992 * Kernel thread context (may sleep)
1993 *
1994 * RETURNS:
1995 * 0 on success, -errno otherwise.
1996 */
1997int ata_std_softreset(struct ata_port *ap, int verbose, unsigned int *classes)
1998{
1999 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2000 unsigned int devmask = 0, err_mask;
2001 u8 err;
2002
2003 DPRINTK("ENTER\n");
2004
3a39746a
TH		 2005 if (ap->ops->scr_read && !sata_dev_present(ap)) {
2006 classes[0] = ATA_DEV_NONE;
2007 goto out;
2008 }
2009
c2bd5804
TH		 2010 /* determine if device 0/1 are present */
2011 if (ata_devchk(ap, 0))
2012 devmask |= (1 << 0);
2013 if (slave_possible && ata_devchk(ap, 1))
2014 devmask |= (1 << 1);
2015
c2bd5804
TH		 2016 /* select device 0 again */
2017 ap->ops->dev_select(ap, 0);
2018
2019 /* issue bus reset */
2020 DPRINTK("about to softreset, devmask=%x\n", devmask);
2021 err_mask = ata_bus_softreset(ap, devmask);
2022 if (err_mask) {
2023 if (verbose)
2024 printk(KERN_ERR "ata%u: SRST failed (err_mask=0x%x)\n",
2025 ap->id, err_mask);
2026 else
2027 DPRINTK("EXIT, softreset failed (err_mask=0x%x)\n",
2028 err_mask);
2029 return -EIO;
2030 }
2031
2032 /* determine by signature whether we have ATA or ATAPI devices */
2033 classes[0] = ata_dev_try_classify(ap, 0, &err);
2034 if (slave_possible && err != 0x81)
2035 classes[1] = ata_dev_try_classify(ap, 1, &err);
2036
3a39746a 2037 out:
c2bd5804
TH		 2038 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2039 return 0;
2040}
2041
2042/**
2043 * sata_std_hardreset - reset host port via SATA phy reset
2044 * @ap: port to reset
2045 * @verbose: fail verbosely
2046 * @class: resulting class of attached device
2047 *
2048 * SATA phy-reset host port using DET bits of SControl register.
2049 * This function is to be used as standard callback for
2050 * ata_drive_*_reset().
2051 *
2052 * LOCKING:
2053 * Kernel thread context (may sleep)
2054 *
2055 * RETURNS:
2056 * 0 on success, -errno otherwise.
2057 */
2058int sata_std_hardreset(struct ata_port *ap, int verbose, unsigned int *class)
2059{
c2bd5804
TH		 2060 DPRINTK("ENTER\n");
2061
2062 /* Issue phy wake/reset */
2063 scr_write_flush(ap, SCR_CONTROL, 0x301);
2064
2065 /*
2066 * Couldn't find anything in SATA I/II specs, but AHCI-1.1
2067 * 10.4.2 says at least 1 ms.
2068 */
2069 msleep(1);
2070
7a7921e8
TH		 2071 /* Bring phy back */
2072 sata_phy_resume(ap);
c2bd5804 2073
c2bd5804
TH		 2074 /* TODO: phy layer with polling, timeouts, etc. */
2075 if (!sata_dev_present(ap)) {
2076 *class = ATA_DEV_NONE;
2077 DPRINTK("EXIT, link offline\n");
2078 return 0;
2079 }
2080
2081 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
2082 if (verbose)
2083 printk(KERN_ERR "ata%u: COMRESET failed "
2084 "(device not ready)\n", ap->id);
2085 else
2086 DPRINTK("EXIT, device not ready\n");
2087 return -EIO;
2088 }
2089
3a39746a
TH		 2090 ap->ops->dev_select(ap, 0); /* probably unnecessary */
2091
c2bd5804
TH		 2092 *class = ata_dev_try_classify(ap, 0, NULL);
2093
2094 DPRINTK("EXIT, class=%u\n", *class);
2095 return 0;
2096}
2097
2098/**
2099 * ata_std_postreset - standard postreset callback
2100 * @ap: the target ata_port
2101 * @classes: classes of attached devices
2102 *
2103 * This function is invoked after a successful reset. Note that
2104 * the device might have been reset more than once using
2105 * different reset methods before postreset is invoked.
2106 * postreset is also reponsible for setting cable type.
2107 *
2108 * This function is to be used as standard callback for
2109 * ata_drive_*_reset().
2110 *
2111 * LOCKING:
2112 * Kernel thread context (may sleep)
2113 */
2114void ata_std_postreset(struct ata_port *ap, unsigned int *classes)
2115{
2116 DPRINTK("ENTER\n");
2117
2118 /* set cable type */
2119 if (ap->cbl == ATA_CBL_NONE && ap->flags & ATA_FLAG_SATA)
2120 ap->cbl = ATA_CBL_SATA;
2121
2122 /* print link status */
2123 if (ap->cbl == ATA_CBL_SATA)
2124 sata_print_link_status(ap);
2125
3a39746a
TH		 2126 /* re-enable interrupts */
2127 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2128 ata_irq_on(ap);
c2bd5804
TH		 2129
2130 /* is double-select really necessary? */
2131 if (classes[0] != ATA_DEV_NONE)
2132 ap->ops->dev_select(ap, 1);
2133 if (classes[1] != ATA_DEV_NONE)
2134 ap->ops->dev_select(ap, 0);
2135
3a39746a
TH		 2136 /* bail out if no device is present */
2137 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2138 DPRINTK("EXIT, no device\n");
2139 return;
2140 }
2141
2142 /* set up device control */
2143 if (ap->ioaddr.ctl_addr) {
2144 if (ap->flags & ATA_FLAG_MMIO)
2145 writeb(ap->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
2146 else
2147 outb(ap->ctl, ap->ioaddr.ctl_addr);
2148 }
c2bd5804
TH		 2149
2150 DPRINTK("EXIT\n");
2151}
2152
2153/**
2154 * ata_std_probe_reset - standard probe reset method
2155 * @ap: prot to perform probe-reset
2156 * @classes: resulting classes of attached devices
2157 *
2158 * The stock off-the-shelf ->probe_reset method.
2159 *
2160 * LOCKING:
2161 * Kernel thread context (may sleep)
2162 *
2163 * RETURNS:
2164 * 0 on success, -errno otherwise.
2165 */
2166int ata_std_probe_reset(struct ata_port *ap, unsigned int *classes)
2167{
2168 ata_reset_fn_t hardreset;
2169
2170 hardreset = NULL;
b911fc3a 2171 if (ap->flags & ATA_FLAG_SATA && ap->ops->scr_read)
c2bd5804
TH		 2172 hardreset = sata_std_hardreset;
2173
8a19ac89 2174 return ata_drive_probe_reset(ap, ata_std_probeinit,
7944ea95 2175 ata_std_softreset, hardreset,
c2bd5804
TH		 2176 ata_std_postreset, classes);
2177}
2178
a62c0fc5
TH		 2179static int do_probe_reset(struct ata_port *ap, ata_reset_fn_t reset,
2180 ata_postreset_fn_t postreset,
2181 unsigned int *classes)
2182{
2183 int i, rc;
2184
2185 for (i = 0; i < ATA_MAX_DEVICES; i++)
2186 classes[i] = ATA_DEV_UNKNOWN;
2187
2188 rc = reset(ap, 0, classes);
2189 if (rc)
2190 return rc;
2191
2192 /* If any class isn't ATA_DEV_UNKNOWN, consider classification
2193 * is complete and convert all ATA_DEV_UNKNOWN to
2194 * ATA_DEV_NONE.
2195 */
2196 for (i = 0; i < ATA_MAX_DEVICES; i++)
2197 if (classes[i] != ATA_DEV_UNKNOWN)
2198 break;
2199
2200 if (i < ATA_MAX_DEVICES)
2201 for (i = 0; i < ATA_MAX_DEVICES; i++)
2202 if (classes[i] == ATA_DEV_UNKNOWN)
2203 classes[i] = ATA_DEV_NONE;
2204
2205 if (postreset)
2206 postreset(ap, classes);
2207
2208 return classes[0] != ATA_DEV_UNKNOWN ? 0 : -ENODEV;
2209}
2210
2211/**
2212 * ata_drive_probe_reset - Perform probe reset with given methods
2213 * @ap: port to reset
7944ea95 2214 * @probeinit: probeinit method (can be NULL)
a62c0fc5
TH		 2215 * @softreset: softreset method (can be NULL)
2216 * @hardreset: hardreset method (can be NULL)
2217 * @postreset: postreset method (can be NULL)
2218 * @classes: resulting classes of attached devices
2219 *
2220 * Reset the specified port and classify attached devices using
2221 * given methods. This function prefers softreset but tries all
2222 * possible reset sequences to reset and classify devices. This
2223 * function is intended to be used for constructing ->probe_reset
2224 * callback by low level drivers.
2225 *
2226 * Reset methods should follow the following rules.
2227 *
2228 * - Return 0 on sucess, -errno on failure.
2229 * - If classification is supported, fill classes[] with
2230 * recognized class codes.
2231 * - If classification is not supported, leave classes[] alone.
2232 * - If verbose is non-zero, print error message on failure;
2233 * otherwise, shut up.
2234 *
2235 * LOCKING:
2236 * Kernel thread context (may sleep)
2237 *
2238 * RETURNS:
2239 * 0 on success, -EINVAL if no reset method is avaliable, -ENODEV
2240 * if classification fails, and any error code from reset
2241 * methods.
2242 */
7944ea95 2243int ata_drive_probe_reset(struct ata_port *ap, ata_probeinit_fn_t probeinit,
a62c0fc5
TH		 2244 ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
2245 ata_postreset_fn_t postreset, unsigned int *classes)
2246{
2247 int rc = -EINVAL;
2248
7944ea95
TH		 2249 if (probeinit)
2250 probeinit(ap);
2251
a62c0fc5
TH		 2252 if (softreset) {
2253 rc = do_probe_reset(ap, softreset, postreset, classes);
2254 if (rc == 0)
2255 return 0;
2256 }
2257
2258 if (!hardreset)
2259 return rc;
2260
2261 rc = do_probe_reset(ap, hardreset, postreset, classes);
2262 if (rc == 0 || rc != -ENODEV)
2263 return rc;
2264
2265 if (softreset)
2266 rc = do_probe_reset(ap, softreset, postreset, classes);
2267
2268 return rc;
2269}
2270
057ace5e
JG		 2271static void ata_pr_blacklisted(const struct ata_port *ap,
2272 const struct ata_device *dev)
1da177e4
LT		 2273{
2274 printk(KERN_WARNING "ata%u: dev %u is on DMA blacklist, disabling DMA\n",
2275 ap->id, dev->devno);
2276}
2277
98ac62de 2278static const char * const ata_dma_blacklist [] = {
1da177e4
LT		 2279 "WDC AC11000H",
2280 "WDC AC22100H",
2281 "WDC AC32500H",
2282 "WDC AC33100H",
2283 "WDC AC31600H",
2284 "WDC AC32100H",
2285 "WDC AC23200L",
2286 "Compaq CRD-8241B",
2287 "CRD-8400B",
2288 "CRD-8480B",
2289 "CRD-8482B",
2290 "CRD-84",
2291 "SanDisk SDP3B",
2292 "SanDisk SDP3B-64",
2293 "SANYO CD-ROM CRD",
2294 "HITACHI CDR-8",
2295 "HITACHI CDR-8335",
2296 "HITACHI CDR-8435",
2297 "Toshiba CD-ROM XM-6202B",
e922256a 2298 "TOSHIBA CD-ROM XM-1702BC",
1da177e4
LT		 2299 "CD-532E-A",
2300 "E-IDE CD-ROM CR-840",
2301 "CD-ROM Drive/F5A",
2302 "WPI CDD-820",
2303 "SAMSUNG CD-ROM SC-148C",
2304 "SAMSUNG CD-ROM SC",
2305 "SanDisk SDP3B-64",
1da177e4
LT		 2306 "ATAPI CD-ROM DRIVE 40X MAXIMUM",
2307 "_NEC DV5800A",
2308};
2309
057ace5e 2310static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4 2311{
2e02671d 2312 unsigned char model_num[41];
1da177e4
LT		 2313 int i;
2314
2e02671d
TH		 2315 ata_dev_id_c_string(dev->id, model_num, ATA_ID_PROD_OFS,
2316 sizeof(model_num));
1da177e4
LT		 2317
2318 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i++)
2e02671d 2319 if (!strcmp(ata_dma_blacklist[i], model_num))
1da177e4
LT		 2320 return 1;
2321
2322 return 0;
2323}
2324
057ace5e 2325static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift)
1da177e4 2326{
057ace5e 2327 const struct ata_device *master, *slave;
1da177e4
LT		 2328 unsigned int mask;
2329
2330 master = &ap->device[0];
2331 slave = &ap->device[1];
2332
a4631474 2333 WARN_ON(!ata_dev_present(master) && !ata_dev_present(slave));
1da177e4
LT		 2334
2335 if (shift == ATA_SHIFT_UDMA) {
2336 mask = ap->udma_mask;
2337 if (ata_dev_present(master)) {
2338 mask &= (master->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2339 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2340 mask = 0;
2341 ata_pr_blacklisted(ap, master);
2342 }
2343 }
2344 if (ata_dev_present(slave)) {
2345 mask &= (slave->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2346 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2347 mask = 0;
2348 ata_pr_blacklisted(ap, slave);
2349 }
2350 }
2351 }
2352 else if (shift == ATA_SHIFT_MWDMA) {
2353 mask = ap->mwdma_mask;
2354 if (ata_dev_present(master)) {
2355 mask &= (master->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2356 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2357 mask = 0;
2358 ata_pr_blacklisted(ap, master);
2359 }
2360 }
2361 if (ata_dev_present(slave)) {
2362 mask &= (slave->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2363 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2364 mask = 0;
2365 ata_pr_blacklisted(ap, slave);
2366 }
2367 }
2368 }
2369 else if (shift == ATA_SHIFT_PIO) {
2370 mask = ap->pio_mask;
2371 if (ata_dev_present(master)) {
2372 /* spec doesn't return explicit support for
2373 * PIO0-2, so we fake it
2374 */
2375 u16 tmp_mode = master->id[ATA_ID_PIO_MODES] & 0x03;
2376 tmp_mode <<= 3;
2377 tmp_mode |= 0x7;
2378 mask &= tmp_mode;
2379 }
2380 if (ata_dev_present(slave)) {
2381 /* spec doesn't return explicit support for
2382 * PIO0-2, so we fake it
2383 */
2384 u16 tmp_mode = slave->id[ATA_ID_PIO_MODES] & 0x03;
2385 tmp_mode <<= 3;
2386 tmp_mode |= 0x7;
2387 mask &= tmp_mode;
2388 }
2389 }
2390 else {
2391 mask = 0xffffffff; /* shut up compiler warning */
2392 BUG();
2393 }
2394
2395 return mask;
2396}
2397
2398/* find greatest bit */
2399static int fgb(u32 bitmap)
2400{
2401 unsigned int i;
2402 int x = -1;
2403
2404 for (i = 0; i < 32; i++)
2405 if (bitmap & (1 << i))
2406 x = i;
2407
2408 return x;
2409}
2410
2411/**
2412 * ata_choose_xfer_mode - attempt to find best transfer mode
2413 * @ap: Port for which an xfer mode will be selected
2414 * @xfer_mode_out: (output) SET FEATURES - XFER MODE code
2415 * @xfer_shift_out: (output) bit shift that selects this mode
2416 *
0cba632b
JG		 2417 * Based on host and device capabilities, determine the
2418 * maximum transfer mode that is amenable to all.
2419 *
1da177e4 2420 * LOCKING:
0cba632b 2421 * PCI/etc. bus probe sem.
1da177e4
LT		 2422 *
2423 * RETURNS:
2424 * Zero on success, negative on error.
2425 */
2426
057ace5e 2427static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 2428 u8 *xfer_mode_out,
2429 unsigned int *xfer_shift_out)
2430{
2431 unsigned int mask, shift;
2432 int x, i;
2433
2434 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++) {
2435 shift = xfer_mode_classes[i].shift;
2436 mask = ata_get_mode_mask(ap, shift);
2437
2438 x = fgb(mask);
2439 if (x >= 0) {
2440 *xfer_mode_out = xfer_mode_classes[i].base + x;
2441 *xfer_shift_out = shift;
2442 return 0;
2443 }
2444 }
2445
2446 return -1;
2447}
2448
2449/**
2450 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
2451 * @ap: Port associated with device @dev
2452 * @dev: Device to which command will be sent
2453 *
780a87f7
JG		 2454 * Issue SET FEATURES - XFER MODE command to device @dev
2455 * on port @ap.
2456 *
1da177e4 2457 * LOCKING:
0cba632b 2458 * PCI/etc. bus probe sem.
1da177e4
LT		 2459 */
2460
2461static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
2462{
a0123703 2463 struct ata_taskfile tf;
1da177e4
LT		 2464
2465 /* set up set-features taskfile */
2466 DPRINTK("set features - xfer mode\n");
2467
a0123703
TH		 2468 ata_tf_init(ap, &tf, dev->devno);
2469 tf.command = ATA_CMD_SET_FEATURES;
2470 tf.feature = SETFEATURES_XFER;
2471 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2472 tf.protocol = ATA_PROT_NODATA;
2473 tf.nsect = dev->xfer_mode;
1da177e4 2474
a0123703
TH		 2475 if (ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0)) {
2476 printk(KERN_ERR "ata%u: failed to set xfermode, disabled\n",
2477 ap->id);
1da177e4 2478 ata_port_disable(ap);
a0123703 2479 }
1da177e4
LT		 2480
2481 DPRINTK("EXIT\n");
2482}
2483
59a10b17
AL		 2484/**
2485 * ata_dev_reread_id - Reread the device identify device info
2486 * @ap: port where the device is
2487 * @dev: device to reread the identify device info
2488 *
2489 * LOCKING:
2490 */
2491
2492static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev)
2493{
a0123703 2494 struct ata_taskfile tf;
59a10b17 2495
a0123703 2496 ata_tf_init(ap, &tf, dev->devno);
59a10b17
AL		 2497
2498 if (dev->class == ATA_DEV_ATA) {
a0123703 2499 tf.command = ATA_CMD_ID_ATA;
59a10b17
AL		 2500 DPRINTK("do ATA identify\n");
2501 } else {
a0123703 2502 tf.command = ATA_CMD_ID_ATAPI;
59a10b17
AL		 2503 DPRINTK("do ATAPI identify\n");
2504 }
2505
a0123703
TH		 2506 tf.flags |= ATA_TFLAG_DEVICE;
2507 tf.protocol = ATA_PROT_PIO;
59a10b17 2508
a0123703
TH		 2509 if (ata_exec_internal(ap, dev, &tf, DMA_FROM_DEVICE,
2510 dev->id, sizeof(dev->id)))
59a10b17
AL		 2511 goto err_out;
2512
59a10b17
AL		 2513 swap_buf_le16(dev->id, ATA_ID_WORDS);
2514
0bd3300a 2515 ata_dump_id(dev->id);
59a10b17
AL		 2516
2517 DPRINTK("EXIT\n");
2518
2519 return;
2520err_out:
a0123703 2521 printk(KERN_ERR "ata%u: failed to reread ID, disabled\n", ap->id);
59a10b17
AL		 2522 ata_port_disable(ap);
2523}
2524
8bf62ece
AL		 2525/**
2526 * ata_dev_init_params - Issue INIT DEV PARAMS command
2527 * @ap: Port associated with device @dev
2528 * @dev: Device to which command will be sent
2529 *
2530 * LOCKING:
2531 */
2532
2533static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev)
2534{
a0123703 2535 struct ata_taskfile tf;
8bf62ece
AL		 2536 u16 sectors = dev->id[6];
2537 u16 heads = dev->id[3];
2538
2539 /* Number of sectors per track 1-255. Number of heads 1-16 */
2540 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
2541 return;
2542
2543 /* set up init dev params taskfile */
2544 DPRINTK("init dev params \n");
2545
a0123703
TH		 2546 ata_tf_init(ap, &tf, dev->devno);
2547 tf.command = ATA_CMD_INIT_DEV_PARAMS;
2548 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2549 tf.protocol = ATA_PROT_NODATA;
2550 tf.nsect = sectors;
2551 tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
8bf62ece 2552
a0123703
TH		 2553 if (ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0)) {
2554 printk(KERN_ERR "ata%u: failed to init parameters, disabled\n",
2555 ap->id);
8bf62ece 2556 ata_port_disable(ap);
a0123703 2557 }
8bf62ece
AL		 2558
2559 DPRINTK("EXIT\n");
2560}
2561
1da177e4 2562/**
0cba632b
JG		 2563 * ata_sg_clean - Unmap DMA memory associated with command
2564 * @qc: Command containing DMA memory to be released
2565 *
2566 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 2567 *
2568 * LOCKING:
0cba632b 2569 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2570 */
2571
2572static void ata_sg_clean(struct ata_queued_cmd *qc)
2573{
2574 struct ata_port *ap = qc->ap;
cedc9a47 2575 struct scatterlist *sg = qc->__sg;
1da177e4 2576 int dir = qc->dma_dir;
cedc9a47 2577 void *pad_buf = NULL;
1da177e4 2578
a4631474
TH		 2579 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
2580 WARN_ON(sg == NULL);
1da177e4
LT		 2581
2582 if (qc->flags & ATA_QCFLAG_SINGLE)
a4631474 2583 WARN_ON(qc->n_elem != 1);
1da177e4 2584
2c13b7ce 2585 VPRINTK("unmapping %u sg elements\n", qc->n_elem);
1da177e4 2586
cedc9a47
JG		 2587 /* if we padded the buffer out to 32-bit bound, and data
2588 * xfer direction is from-device, we must copy from the
2589 * pad buffer back into the supplied buffer
2590 */
2591 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
2592 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2593
2594 if (qc->flags & ATA_QCFLAG_SG) {
e1410f2d
JG		 2595 if (qc->n_elem)
2596 dma_unmap_sg(ap->host_set->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 2597 /* restore last sg */
2598 sg[qc->orig_n_elem - 1].length += qc->pad_len;
2599 if (pad_buf) {
2600 struct scatterlist *psg = &qc->pad_sgent;
2601 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2602 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
dfa15988 2603 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2604 }
2605 } else {
e1410f2d
JG		 2606 if (sg_dma_len(&sg[0]) > 0)
2607 dma_unmap_single(ap->host_set->dev,
2608 sg_dma_address(&sg[0]), sg_dma_len(&sg[0]),
2609 dir);
cedc9a47
JG		 2610 /* restore sg */
2611 sg->length += qc->pad_len;
2612 if (pad_buf)
2613 memcpy(qc->buf_virt + sg->length - qc->pad_len,
2614 pad_buf, qc->pad_len);
2615 }
1da177e4
LT		 2616
2617 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 2618 qc->__sg = NULL;
1da177e4
LT		 2619}
2620
2621/**
2622 * ata_fill_sg - Fill PCI IDE PRD table
2623 * @qc: Metadata associated with taskfile to be transferred
2624 *
780a87f7
JG		 2625 * Fill PCI IDE PRD (scatter-gather) table with segments
2626 * associated with the current disk command.
2627 *
1da177e4 2628 * LOCKING:
780a87f7 2629 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2630 *
2631 */
2632static void ata_fill_sg(struct ata_queued_cmd *qc)
2633{
1da177e4 2634 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2635 struct scatterlist *sg;
2636 unsigned int idx;
1da177e4 2637
a4631474
TH		 2638 WARN_ON(qc->__sg == NULL);
2639 WARN_ON(qc->n_elem == 0);
1da177e4
LT		 2640
2641 idx = 0;
cedc9a47 2642 ata_for_each_sg(sg, qc) {
1da177e4
LT		 2643 u32 addr, offset;
2644 u32 sg_len, len;
2645
2646 /* determine if physical DMA addr spans 64K boundary.
2647 * Note h/w doesn't support 64-bit, so we unconditionally
2648 * truncate dma_addr_t to u32.
2649 */
2650 addr = (u32) sg_dma_address(sg);
2651 sg_len = sg_dma_len(sg);
2652
2653 while (sg_len) {
2654 offset = addr & 0xffff;
2655 len = sg_len;
2656 if ((offset + sg_len) > 0x10000)
2657 len = 0x10000 - offset;
2658
2659 ap->prd[idx].addr = cpu_to_le32(addr);
2660 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2661 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
2662
2663 idx++;
2664 sg_len -= len;
2665 addr += len;
2666 }
2667 }
2668
2669 if (idx)
2670 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2671}
2672/**
2673 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
2674 * @qc: Metadata associated with taskfile to check
2675 *
780a87f7
JG		 2676 * Allow low-level driver to filter ATA PACKET commands, returning
2677 * a status indicating whether or not it is OK to use DMA for the
2678 * supplied PACKET command.
2679 *
1da177e4 2680 * LOCKING:
0cba632b
JG		 2681 * spin_lock_irqsave(host_set lock)
2682 *
1da177e4
LT		 2683 * RETURNS: 0 when ATAPI DMA can be used
2684 * nonzero otherwise
2685 */
2686int ata_check_atapi_dma(struct ata_queued_cmd *qc)
2687{
2688 struct ata_port *ap = qc->ap;
2689 int rc = 0; /* Assume ATAPI DMA is OK by default */
2690
2691 if (ap->ops->check_atapi_dma)
2692 rc = ap->ops->check_atapi_dma(qc);
2693
2694 return rc;
2695}
2696/**
2697 * ata_qc_prep - Prepare taskfile for submission
2698 * @qc: Metadata associated with taskfile to be prepared
2699 *
780a87f7
JG		 2700 * Prepare ATA taskfile for submission.
2701 *
1da177e4
LT		 2702 * LOCKING:
2703 * spin_lock_irqsave(host_set lock)
2704 */
2705void ata_qc_prep(struct ata_queued_cmd *qc)
2706{
2707 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2708 return;
2709
2710 ata_fill_sg(qc);
2711}
2712
0cba632b
JG		 2713/**
2714 * ata_sg_init_one - Associate command with memory buffer
2715 * @qc: Command to be associated
2716 * @buf: Memory buffer
2717 * @buflen: Length of memory buffer, in bytes.
2718 *
2719 * Initialize the data-related elements of queued_cmd @qc
2720 * to point to a single memory buffer, @buf of byte length @buflen.
2721 *
2722 * LOCKING:
2723 * spin_lock_irqsave(host_set lock)
2724 */
2725
1da177e4
LT		 2726void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
2727{
2728 struct scatterlist *sg;
2729
2730 qc->flags |= ATA_QCFLAG_SINGLE;
2731
2732 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 2733 qc->__sg = &qc->sgent;
1da177e4 2734 qc->n_elem = 1;
cedc9a47 2735 qc->orig_n_elem = 1;
1da177e4
LT		 2736 qc->buf_virt = buf;
2737
cedc9a47 2738 sg = qc->__sg;
f0612bbc 2739 sg_init_one(sg, buf, buflen);
1da177e4
LT		 2740}
2741
0cba632b
JG		 2742/**
2743 * ata_sg_init - Associate command with scatter-gather table.
2744 * @qc: Command to be associated
2745 * @sg: Scatter-gather table.
2746 * @n_elem: Number of elements in s/g table.
2747 *
2748 * Initialize the data-related elements of queued_cmd @qc
2749 * to point to a scatter-gather table @sg, containing @n_elem
2750 * elements.
2751 *
2752 * LOCKING:
2753 * spin_lock_irqsave(host_set lock)
2754 */
2755
1da177e4
LT		 2756void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
2757 unsigned int n_elem)
2758{
2759 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 2760 qc->__sg = sg;
1da177e4 2761 qc->n_elem = n_elem;
cedc9a47 2762 qc->orig_n_elem = n_elem;
1da177e4
LT		 2763}
2764
2765/**
0cba632b
JG		 2766 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
2767 * @qc: Command with memory buffer to be mapped.
2768 *
2769 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 2770 *
2771 * LOCKING:
2772 * spin_lock_irqsave(host_set lock)
2773 *
2774 * RETURNS:
0cba632b 2775 * Zero on success, negative on error.
1da177e4
LT		 2776 */
2777
2778static int ata_sg_setup_one(struct ata_queued_cmd *qc)
2779{
2780 struct ata_port *ap = qc->ap;
2781 int dir = qc->dma_dir;
cedc9a47 2782 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 2783 dma_addr_t dma_address;
2784
cedc9a47
JG		 2785 /* we must lengthen transfers to end on a 32-bit boundary */
2786 qc->pad_len = sg->length & 3;
2787 if (qc->pad_len) {
2788 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2789 struct scatterlist *psg = &qc->pad_sgent;
2790
a4631474 2791 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 2792
2793 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2794
2795 if (qc->tf.flags & ATA_TFLAG_WRITE)
2796 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
2797 qc->pad_len);
2798
2799 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2800 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2801 /* trim sg */
2802 sg->length -= qc->pad_len;
2803
2804 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
2805 sg->length, qc->pad_len);
2806 }
2807
e1410f2d
JG		 2808 if (!sg->length) {
2809 sg_dma_address(sg) = 0;
2810 goto skip_map;
2811 }
2812
1da177e4 2813 dma_address = dma_map_single(ap->host_set->dev, qc->buf_virt,
32529e01 2814 sg->length, dir);
537a95d9
TH		 2815 if (dma_mapping_error(dma_address)) {
2816 /* restore sg */
2817 sg->length += qc->pad_len;
1da177e4 2818 return -1;
537a95d9 2819 }
1da177e4
LT		 2820
2821 sg_dma_address(sg) = dma_address;
e1410f2d 2822skip_map:
32529e01 2823 sg_dma_len(sg) = sg->length;
1da177e4
LT		 2824
2825 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
2826 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
2827
2828 return 0;
2829}
2830
2831/**
0cba632b
JG		 2832 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
2833 * @qc: Command with scatter-gather table to be mapped.
2834 *
2835 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 2836 *
2837 * LOCKING:
2838 * spin_lock_irqsave(host_set lock)
2839 *
2840 * RETURNS:
0cba632b 2841 * Zero on success, negative on error.
1da177e4
LT		 2842 *
2843 */
2844
2845static int ata_sg_setup(struct ata_queued_cmd *qc)
2846{
2847 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2848 struct scatterlist *sg = qc->__sg;
2849 struct scatterlist *lsg = &sg[qc->n_elem - 1];
e1410f2d 2850 int n_elem, pre_n_elem, dir, trim_sg = 0;
1da177e4
LT		 2851
2852 VPRINTK("ENTER, ata%u\n", ap->id);
a4631474 2853 WARN_ON(!(qc->flags & ATA_QCFLAG_SG));
1da177e4 2854
cedc9a47
JG		 2855 /* we must lengthen transfers to end on a 32-bit boundary */
2856 qc->pad_len = lsg->length & 3;
2857 if (qc->pad_len) {
2858 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2859 struct scatterlist *psg = &qc->pad_sgent;
2860 unsigned int offset;
2861
a4631474 2862 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 2863
2864 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2865
2866 /*
2867 * psg->page/offset are used to copy to-be-written
2868 * data in this function or read data in ata_sg_clean.
2869 */
2870 offset = lsg->offset + lsg->length - qc->pad_len;
2871 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
2872 psg->offset = offset_in_page(offset);
2873
2874 if (qc->tf.flags & ATA_TFLAG_WRITE) {
2875 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2876 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
dfa15988 2877 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2878 }
2879
2880 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2881 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2882 /* trim last sg */
2883 lsg->length -= qc->pad_len;
e1410f2d
JG		 2884 if (lsg->length == 0)
2885 trim_sg = 1;
cedc9a47
JG		 2886
2887 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
2888 qc->n_elem - 1, lsg->length, qc->pad_len);
2889 }
2890
e1410f2d
JG		 2891 pre_n_elem = qc->n_elem;
2892 if (trim_sg && pre_n_elem)
2893 pre_n_elem--;
2894
2895 if (!pre_n_elem) {
2896 n_elem = 0;
2897 goto skip_map;
2898 }
2899
1da177e4 2900 dir = qc->dma_dir;
e1410f2d 2901 n_elem = dma_map_sg(ap->host_set->dev, sg, pre_n_elem, dir);
537a95d9
TH		 2902 if (n_elem < 1) {
2903 /* restore last sg */
2904 lsg->length += qc->pad_len;
1da177e4 2905 return -1;
537a95d9 2906 }
1da177e4
LT		 2907
2908 DPRINTK("%d sg elements mapped\n", n_elem);
2909
e1410f2d 2910skip_map:
1da177e4
LT		 2911 qc->n_elem = n_elem;
2912
2913 return 0;
2914}
2915
40e8c82c
TH		 2916/**
2917 * ata_poll_qc_complete - turn irq back on and finish qc
2918 * @qc: Command to complete
8e8b77dd 2919 * @err_mask: ATA status register content
40e8c82c
TH		 2920 *
2921 * LOCKING:
2922 * None. (grabs host lock)
2923 */
2924
a22e2eb0 2925void ata_poll_qc_complete(struct ata_queued_cmd *qc)
40e8c82c
TH		 2926{
2927 struct ata_port *ap = qc->ap;
b8f6153e 2928 unsigned long flags;
40e8c82c 2929
b8f6153e 2930 spin_lock_irqsave(&ap->host_set->lock, flags);
40e8c82c
TH		 2931 ap->flags &= ~ATA_FLAG_NOINTR;
2932 ata_irq_on(ap);
a22e2eb0 2933 ata_qc_complete(qc);
b8f6153e 2934 spin_unlock_irqrestore(&ap->host_set->lock, flags);
40e8c82c
TH		 2935}
2936
1da177e4 2937/**
c893a3ae 2938 * ata_pio_poll - poll using PIO, depending on current state
6f0ef4fa 2939 * @ap: the target ata_port
1da177e4
LT		 2940 *
2941 * LOCKING:
0cba632b 2942 * None. (executing in kernel thread context)
1da177e4
LT		 2943 *
2944 * RETURNS:
6f0ef4fa 2945 * timeout value to use
1da177e4
LT		 2946 */
2947
2948static unsigned long ata_pio_poll(struct ata_port *ap)
2949{
c14b8331 2950 struct ata_queued_cmd *qc;
1da177e4 2951 u8 status;
14be71f4
AL		 2952 unsigned int poll_state = HSM_ST_UNKNOWN;
2953 unsigned int reg_state = HSM_ST_UNKNOWN;
14be71f4 2954
c14b8331 2955 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 2956 WARN_ON(qc == NULL);
c14b8331 2957
14be71f4
AL		 2958 switch (ap->hsm_task_state) {
2959 case HSM_ST:
2960 case HSM_ST_POLL:
2961 poll_state = HSM_ST_POLL;
2962 reg_state = HSM_ST;
1da177e4 2963 break;
14be71f4
AL		 2964 case HSM_ST_LAST:
2965 case HSM_ST_LAST_POLL:
2966 poll_state = HSM_ST_LAST_POLL;
2967 reg_state = HSM_ST_LAST;
1da177e4
LT		 2968 break;
2969 default:
2970 BUG();
2971 break;
2972 }
2973
2974 status = ata_chk_status(ap);
2975 if (status & ATA_BUSY) {
2976 if (time_after(jiffies, ap->pio_task_timeout)) {
11a56d24 2977 qc->err_mask |= AC_ERR_TIMEOUT;
7c398335 2978 ap->hsm_task_state = HSM_ST_TMOUT;
1da177e4
LT		 2979 return 0;
2980 }
14be71f4 2981 ap->hsm_task_state = poll_state;
1da177e4
LT		 2982 return ATA_SHORT_PAUSE;
2983 }
2984
14be71f4 2985 ap->hsm_task_state = reg_state;
1da177e4
LT		 2986 return 0;
2987}
2988
2989/**
6f0ef4fa
RD		 2990 * ata_pio_complete - check if drive is busy or idle
2991 * @ap: the target ata_port
1da177e4
LT		 2992 *
2993 * LOCKING:
0cba632b 2994 * None. (executing in kernel thread context)
7fb6ec28
JG		 2995 *
2996 * RETURNS:
2997 * Non-zero if qc completed, zero otherwise.
1da177e4
LT		 2998 */
2999
7fb6ec28 3000static int ata_pio_complete (struct ata_port *ap)
1da177e4
LT		 3001{
3002 struct ata_queued_cmd *qc;
3003 u8 drv_stat;
3004
3005 /*
31433ea3
AC		 3006 * This is purely heuristic. This is a fast path. Sometimes when
3007 * we enter, BSY will be cleared in a chk-status or two. If not,
3008 * the drive is probably seeking or something. Snooze for a couple
3009 * msecs, then chk-status again. If still busy, fall back to
14be71f4 3010 * HSM_ST_POLL state.
1da177e4 3011 */
fe79e683
AL		 3012 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
3013 if (drv_stat & ATA_BUSY) {
1da177e4 3014 msleep(2);
fe79e683
AL		 3015 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
3016 if (drv_stat & ATA_BUSY) {
14be71f4 3017 ap->hsm_task_state = HSM_ST_LAST_POLL;
1da177e4 3018 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
7fb6ec28 3019 return 0;
1da177e4
LT		 3020 }
3021 }
3022
c14b8331 3023 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 3024 WARN_ON(qc == NULL);
c14b8331 3025
1da177e4
LT		 3026 drv_stat = ata_wait_idle(ap);
3027 if (!ata_ok(drv_stat)) {
1c848984 3028 qc->err_mask |= __ac_err_mask(drv_stat);
14be71f4 3029 ap->hsm_task_state = HSM_ST_ERR;
7fb6ec28 3030 return 0;
1da177e4
LT		 3031 }
3032
14be71f4 3033 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3034
a4631474 3035 WARN_ON(qc->err_mask);
a22e2eb0 3036 ata_poll_qc_complete(qc);
7fb6ec28
JG		 3037
3038 /* another command may start at this point */
3039
3040 return 1;
1da177e4
LT		 3041}
3042
0baab86b
EF		 3043
3044/**
c893a3ae 3045 * swap_buf_le16 - swap halves of 16-bit words in place
0baab86b
EF		 3046 * @buf: Buffer to swap
3047 * @buf_words: Number of 16-bit words in buffer.
3048 *
3049 * Swap halves of 16-bit words if needed to convert from
3050 * little-endian byte order to native cpu byte order, or
3051 * vice-versa.
3052 *
3053 * LOCKING:
6f0ef4fa 3054 * Inherited from caller.
0baab86b 3055 */
1da177e4
LT		 3056void swap_buf_le16(u16 *buf, unsigned int buf_words)
3057{
3058#ifdef __BIG_ENDIAN
3059 unsigned int i;
3060
3061 for (i = 0; i < buf_words; i++)
3062 buf[i] = le16_to_cpu(buf[i]);
3063#endif /* __BIG_ENDIAN */
3064}
3065
6ae4cfb5
AL		 3066/**
3067 * ata_mmio_data_xfer - Transfer data by MMIO
3068 * @ap: port to read/write
3069 * @buf: data buffer
3070 * @buflen: buffer length
344babaa 3071 * @write_data: read/write
6ae4cfb5
AL		 3072 *
3073 * Transfer data from/to the device data register by MMIO.
3074 *
3075 * LOCKING:
3076 * Inherited from caller.
6ae4cfb5
AL		 3077 */
3078
1da177e4
LT		 3079static void ata_mmio_data_xfer(struct ata_port *ap, unsigned char *buf,
3080 unsigned int buflen, int write_data)
3081{
3082 unsigned int i;
3083 unsigned int words = buflen >> 1;
3084 u16 *buf16 = (u16 *) buf;
3085 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
3086
6ae4cfb5 3087 /* Transfer multiple of 2 bytes */
1da177e4
LT		 3088 if (write_data) {
3089 for (i = 0; i < words; i++)
3090 writew(le16_to_cpu(buf16[i]), mmio);
3091 } else {
3092 for (i = 0; i < words; i++)
3093 buf16[i] = cpu_to_le16(readw(mmio));
3094 }
6ae4cfb5
AL		 3095
3096 /* Transfer trailing 1 byte, if any. */
3097 if (unlikely(buflen & 0x01)) {
3098 u16 align_buf[1] = { 0 };
3099 unsigned char *trailing_buf = buf + buflen - 1;
3100
3101 if (write_data) {
3102 memcpy(align_buf, trailing_buf, 1);
3103 writew(le16_to_cpu(align_buf[0]), mmio);
3104 } else {
3105 align_buf[0] = cpu_to_le16(readw(mmio));
3106 memcpy(trailing_buf, align_buf, 1);
3107 }
3108 }
1da177e4
LT		 3109}
3110
6ae4cfb5
AL		 3111/**
3112 * ata_pio_data_xfer - Transfer data by PIO
3113 * @ap: port to read/write
3114 * @buf: data buffer
3115 * @buflen: buffer length
344babaa 3116 * @write_data: read/write
6ae4cfb5
AL		 3117 *
3118 * Transfer data from/to the device data register by PIO.
3119 *
3120 * LOCKING:
3121 * Inherited from caller.
6ae4cfb5
AL		 3122 */
3123
1da177e4
LT		 3124static void ata_pio_data_xfer(struct ata_port *ap, unsigned char *buf,
3125 unsigned int buflen, int write_data)
3126{
6ae4cfb5 3127 unsigned int words = buflen >> 1;
1da177e4 3128
6ae4cfb5 3129 /* Transfer multiple of 2 bytes */
1da177e4 3130 if (write_data)
6ae4cfb5 3131 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 3132 else
6ae4cfb5
AL		 3133 insw(ap->ioaddr.data_addr, buf, words);
3134
3135 /* Transfer trailing 1 byte, if any. */
3136 if (unlikely(buflen & 0x01)) {
3137 u16 align_buf[1] = { 0 };
3138 unsigned char *trailing_buf = buf + buflen - 1;
3139
3140 if (write_data) {
3141 memcpy(align_buf, trailing_buf, 1);
3142 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
3143 } else {
3144 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
3145 memcpy(trailing_buf, align_buf, 1);
3146 }
3147 }
1da177e4
LT		 3148}
3149
6ae4cfb5
AL		 3150/**
3151 * ata_data_xfer - Transfer data from/to the data register.
3152 * @ap: port to read/write
3153 * @buf: data buffer
3154 * @buflen: buffer length
3155 * @do_write: read/write
3156 *
3157 * Transfer data from/to the device data register.
3158 *
3159 * LOCKING:
3160 * Inherited from caller.
6ae4cfb5
AL		 3161 */
3162
1da177e4
LT		 3163static void ata_data_xfer(struct ata_port *ap, unsigned char *buf,
3164 unsigned int buflen, int do_write)
3165{
a1bd9e68
AC		 3166 /* Make the crap hardware pay the costs not the good stuff */
3167 if (unlikely(ap->flags & ATA_FLAG_IRQ_MASK)) {
3168 unsigned long flags;
3169 local_irq_save(flags);
3170 if (ap->flags & ATA_FLAG_MMIO)
3171 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3172 else
3173 ata_pio_data_xfer(ap, buf, buflen, do_write);
3174 local_irq_restore(flags);
3175 } else {
3176 if (ap->flags & ATA_FLAG_MMIO)
3177 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3178 else
3179 ata_pio_data_xfer(ap, buf, buflen, do_write);
3180 }
1da177e4
LT		 3181}
3182
6ae4cfb5
AL		 3183/**
3184 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
3185 * @qc: Command on going
3186 *
3187 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
3188 *
3189 * LOCKING:
3190 * Inherited from caller.
3191 */
3192
1da177e4
LT		 3193static void ata_pio_sector(struct ata_queued_cmd *qc)
3194{
3195 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3196 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3197 struct ata_port *ap = qc->ap;
3198 struct page *page;
3199 unsigned int offset;
3200 unsigned char *buf;
3201
3202 if (qc->cursect == (qc->nsect - 1))
14be71f4 3203 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3204
3205 page = sg[qc->cursg].page;
3206 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
3207
3208 /* get the current page and offset */
3209 page = nth_page(page, (offset >> PAGE_SHIFT));
3210 offset %= PAGE_SIZE;
3211
3212 buf = kmap(page) + offset;
3213
3214 qc->cursect++;
3215 qc->cursg_ofs++;
3216
32529e01 3217 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT		 3218 qc->cursg++;
3219 qc->cursg_ofs = 0;
3220 }
3221
3222 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3223
3224 /* do the actual data transfer */
3225 do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
3226 ata_data_xfer(ap, buf, ATA_SECT_SIZE, do_write);
3227
3228 kunmap(page);
3229}
3230
6ae4cfb5
AL		 3231/**
3232 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3233 * @qc: Command on going
3234 * @bytes: number of bytes
3235 *
3236 * Transfer Transfer data from/to the ATAPI device.
3237 *
3238 * LOCKING:
3239 * Inherited from caller.
3240 *
3241 */
3242
1da177e4
LT		 3243static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3244{
3245 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3246 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3247 struct ata_port *ap = qc->ap;
3248 struct page *page;
3249 unsigned char *buf;
3250 unsigned int offset, count;
3251
563a6e1f 3252 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3253 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3254
3255next_sg:
563a6e1f 3256 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3257 /*
563a6e1f
AL		 3258 * The end of qc->sg is reached and the device expects
3259 * more data to transfer. In order not to overrun qc->sg
3260 * and fulfill length specified in the byte count register,
3261 * - for read case, discard trailing data from the device
3262 * - for write case, padding zero data to the device
3263 */
3264 u16 pad_buf[1] = { 0 };
3265 unsigned int words = bytes >> 1;
3266 unsigned int i;
3267
3268 if (words) /* warning if bytes > 1 */
7fb6ec28 3269 printk(KERN_WARNING "ata%u: %u bytes trailing data\n",
563a6e1f
AL		 3270 ap->id, bytes);
3271
3272 for (i = 0; i < words; i++)
3273 ata_data_xfer(ap, (unsigned char*)pad_buf, 2, do_write);
3274
14be71f4 3275 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3276 return;
3277 }
3278
cedc9a47 3279 sg = &qc->__sg[qc->cursg];
1da177e4 3280
1da177e4
LT		 3281 page = sg->page;
3282 offset = sg->offset + qc->cursg_ofs;
3283
3284 /* get the current page and offset */
3285 page = nth_page(page, (offset >> PAGE_SHIFT));
3286 offset %= PAGE_SIZE;
3287
6952df03 3288 /* don't overrun current sg */
32529e01 3289 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3290
3291 /* don't cross page boundaries */
3292 count = min(count, (unsigned int)PAGE_SIZE - offset);
3293
3294 buf = kmap(page) + offset;
3295
3296 bytes -= count;
3297 qc->curbytes += count;
3298 qc->cursg_ofs += count;
3299
32529e01 3300 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 3301 qc->cursg++;
3302 qc->cursg_ofs = 0;
3303 }
3304
3305 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3306
3307 /* do the actual data transfer */
3308 ata_data_xfer(ap, buf, count, do_write);
3309
3310 kunmap(page);
3311
563a6e1f 3312 if (bytes)
1da177e4 3313 goto next_sg;
1da177e4
LT		 3314}
3315
6ae4cfb5
AL		 3316/**
3317 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3318 * @qc: Command on going
3319 *
3320 * Transfer Transfer data from/to the ATAPI device.
3321 *
3322 * LOCKING:
3323 * Inherited from caller.
6ae4cfb5
AL		 3324 */
3325
1da177e4
LT		 3326static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3327{
3328 struct ata_port *ap = qc->ap;
3329 struct ata_device *dev = qc->dev;
3330 unsigned int ireason, bc_lo, bc_hi, bytes;
3331 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3332
3333 ap->ops->tf_read(ap, &qc->tf);
3334 ireason = qc->tf.nsect;
3335 bc_lo = qc->tf.lbam;
3336 bc_hi = qc->tf.lbah;
3337 bytes = (bc_hi << 8) | bc_lo;
3338
3339 /* shall be cleared to zero, indicating xfer of data */
3340 if (ireason & (1 << 0))
3341 goto err_out;
3342
3343 /* make sure transfer direction matches expected */
3344 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3345 if (do_write != i_write)
3346 goto err_out;
3347
3348 __atapi_pio_bytes(qc, bytes);
3349
3350 return;
3351
3352err_out:
3353 printk(KERN_INFO "ata%u: dev %u: ATAPI check failed\n",
3354 ap->id, dev->devno);
11a56d24 3355 qc->err_mask |= AC_ERR_HSM;
14be71f4 3356 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3357}
3358
3359/**
6f0ef4fa
RD		 3360 * ata_pio_block - start PIO on a block
3361 * @ap: the target ata_port
1da177e4
LT		 3362 *
3363 * LOCKING:
0cba632b 3364 * None. (executing in kernel thread context)
1da177e4
LT		 3365 */
3366
3367static void ata_pio_block(struct ata_port *ap)
3368{
3369 struct ata_queued_cmd *qc;
3370 u8 status;
3371
3372 /*
6f0ef4fa 3373 * This is purely heuristic. This is a fast path.
1da177e4
LT		 3374 * Sometimes when we enter, BSY will be cleared in
3375 * a chk-status or two. If not, the drive is probably seeking
3376 * or something. Snooze for a couple msecs, then
3377 * chk-status again. If still busy, fall back to
14be71f4 3378 * HSM_ST_POLL state.
1da177e4
LT		 3379 */
3380 status = ata_busy_wait(ap, ATA_BUSY, 5);
3381 if (status & ATA_BUSY) {
3382 msleep(2);
3383 status = ata_busy_wait(ap, ATA_BUSY, 10);
3384 if (status & ATA_BUSY) {
14be71f4 3385 ap->hsm_task_state = HSM_ST_POLL;
1da177e4
LT		 3386 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
3387 return;
3388 }
3389 }
3390
3391 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 3392 WARN_ON(qc == NULL);
1da177e4 3393
fe79e683
AL		 3394 /* check error */
3395 if (status & (ATA_ERR | ATA_DF)) {
3396 qc->err_mask |= AC_ERR_DEV;
3397 ap->hsm_task_state = HSM_ST_ERR;
3398 return;
3399 }
3400
3401 /* transfer data if any */
1da177e4 3402 if (is_atapi_taskfile(&qc->tf)) {
fe79e683 3403 /* DRQ=0 means no more data to transfer */
1da177e4 3404 if ((status & ATA_DRQ) == 0) {
14be71f4 3405 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3406 return;
3407 }
3408
3409 atapi_pio_bytes(qc);
3410 } else {
3411 /* handle BSY=0, DRQ=0 as error */
3412 if ((status & ATA_DRQ) == 0) {
11a56d24 3413 qc->err_mask |= AC_ERR_HSM;
14be71f4 3414 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3415 return;
3416 }
3417
3418 ata_pio_sector(qc);
3419 }
3420}
3421
3422static void ata_pio_error(struct ata_port *ap)
3423{
3424 struct ata_queued_cmd *qc;
a7dac447
JG		 3425
3426 printk(KERN_WARNING "ata%u: PIO error\n", ap->id);
1da177e4
LT		 3427
3428 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 3429 WARN_ON(qc == NULL);
1da177e4 3430
1c848984
AL		 3431 /* make sure qc->err_mask is available to
3432 * know what's wrong and recover
3433 */
a4631474 3434 WARN_ON(qc->err_mask == 0);
1c848984 3435
14be71f4 3436 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3437
a22e2eb0 3438 ata_poll_qc_complete(qc);
1da177e4
LT		 3439}
3440
3441static void ata_pio_task(void *_data)
3442{
3443 struct ata_port *ap = _data;
7fb6ec28
JG		 3444 unsigned long timeout;
3445 int qc_completed;
3446
3447fsm_start:
3448 timeout = 0;
3449 qc_completed = 0;
1da177e4 3450
14be71f4
AL		 3451 switch (ap->hsm_task_state) {
3452 case HSM_ST_IDLE:
1da177e4
LT		 3453 return;
3454
14be71f4 3455 case HSM_ST:
1da177e4
LT		 3456 ata_pio_block(ap);
3457 break;
3458
14be71f4 3459 case HSM_ST_LAST:
7fb6ec28 3460 qc_completed = ata_pio_complete(ap);
1da177e4
LT		 3461 break;
3462
14be71f4
AL		 3463 case HSM_ST_POLL:
3464 case HSM_ST_LAST_POLL:
1da177e4
LT		 3465 timeout = ata_pio_poll(ap);
3466 break;
3467
14be71f4
AL		 3468 case HSM_ST_TMOUT:
3469 case HSM_ST_ERR:
1da177e4
LT		 3470 ata_pio_error(ap);
3471 return;
3472 }
3473
3474 if (timeout)
95064379 3475 ata_queue_delayed_pio_task(ap, timeout);
7fb6ec28
JG		 3476 else if (!qc_completed)
3477 goto fsm_start;
1da177e4
LT		 3478}
3479
1da177e4
LT		 3480/**
3481 * ata_qc_timeout - Handle timeout of queued command
3482 * @qc: Command that timed out
3483 *
3484 * Some part of the kernel (currently, only the SCSI layer)
3485 * has noticed that the active command on port @ap has not
3486 * completed after a specified length of time. Handle this
3487 * condition by disabling DMA (if necessary) and completing
3488 * transactions, with error if necessary.
3489 *
3490 * This also handles the case of the "lost interrupt", where
3491 * for some reason (possibly hardware bug, possibly driver bug)
3492 * an interrupt was not delivered to the driver, even though the
3493 * transaction completed successfully.
3494 *
3495 * LOCKING:
0cba632b 3496 * Inherited from SCSI layer (none, can sleep)
1da177e4
LT		 3497 */
3498
3499static void ata_qc_timeout(struct ata_queued_cmd *qc)
3500{
3501 struct ata_port *ap = qc->ap;
b8f6153e 3502 struct ata_host_set *host_set = ap->host_set;
1da177e4 3503 u8 host_stat = 0, drv_stat;
b8f6153e 3504 unsigned long flags;
1da177e4
LT		 3505
3506 DPRINTK("ENTER\n");
3507
c18d06f8
TH		 3508 ata_flush_pio_tasks(ap);
3509 ap->hsm_task_state = HSM_ST_IDLE;
3510
b8f6153e
JG		 3511 spin_lock_irqsave(&host_set->lock, flags);
3512
1da177e4
LT		 3513 switch (qc->tf.protocol) {
3514
3515 case ATA_PROT_DMA:
3516 case ATA_PROT_ATAPI_DMA:
3517 host_stat = ap->ops->bmdma_status(ap);
3518
3519 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3520 ap->ops->bmdma_stop(qc);
1da177e4
LT		 3521
3522 /* fall through */
3523
3524 default:
3525 ata_altstatus(ap);
3526 drv_stat = ata_chk_status(ap);
3527
3528 /* ack bmdma irq events */
3529 ap->ops->irq_clear(ap);
3530
3531 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x host_stat 0x%x\n",
3532 ap->id, qc->tf.command, drv_stat, host_stat);
3533
3534 /* complete taskfile transaction */
a22e2eb0 3535 qc->err_mask |= ac_err_mask(drv_stat);
1da177e4
LT		 3536 break;
3537 }
b8f6153e
JG		 3538
3539 spin_unlock_irqrestore(&host_set->lock, flags);
3540
a72ec4ce
TH		 3541 ata_eh_qc_complete(qc);
3542
1da177e4
LT		 3543 DPRINTK("EXIT\n");
3544}
3545
3546/**
3547 * ata_eng_timeout - Handle timeout of queued command
3548 * @ap: Port on which timed-out command is active
3549 *
3550 * Some part of the kernel (currently, only the SCSI layer)
3551 * has noticed that the active command on port @ap has not
3552 * completed after a specified length of time. Handle this
3553 * condition by disabling DMA (if necessary) and completing
3554 * transactions, with error if necessary.
3555 *
3556 * This also handles the case of the "lost interrupt", where
3557 * for some reason (possibly hardware bug, possibly driver bug)
3558 * an interrupt was not delivered to the driver, even though the
3559 * transaction completed successfully.
3560 *
3561 * LOCKING:
3562 * Inherited from SCSI layer (none, can sleep)
3563 */
3564
3565void ata_eng_timeout(struct ata_port *ap)
3566{
1da177e4
LT		 3567 DPRINTK("ENTER\n");
3568
f6379020 3569 ata_qc_timeout(ata_qc_from_tag(ap, ap->active_tag));
1da177e4 3570
1da177e4
LT		 3571 DPRINTK("EXIT\n");
3572}
3573
3574/**
3575 * ata_qc_new - Request an available ATA command, for queueing
3576 * @ap: Port associated with device @dev
3577 * @dev: Device from whom we request an available command structure
3578 *
3579 * LOCKING:
0cba632b 3580 * None.
1da177e4
LT		 3581 */
3582
3583static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
3584{
3585 struct ata_queued_cmd *qc = NULL;
3586 unsigned int i;
3587
3588 for (i = 0; i < ATA_MAX_QUEUE; i++)
3589 if (!test_and_set_bit(i, &ap->qactive)) {
3590 qc = ata_qc_from_tag(ap, i);
3591 break;
3592 }
3593
3594 if (qc)
3595 qc->tag = i;
3596
3597 return qc;
3598}
3599
3600/**
3601 * ata_qc_new_init - Request an available ATA command, and initialize it
3602 * @ap: Port associated with device @dev
3603 * @dev: Device from whom we request an available command structure
3604 *
3605 * LOCKING:
0cba632b 3606 * None.
1da177e4
LT		 3607 */
3608
3609struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap,
3610 struct ata_device *dev)
3611{
3612 struct ata_queued_cmd *qc;
3613
3614 qc = ata_qc_new(ap);
3615 if (qc) {
1da177e4
LT		 3616 qc->scsicmd = NULL;
3617 qc->ap = ap;
3618 qc->dev = dev;
1da177e4 3619
2c13b7ce 3620 ata_qc_reinit(qc);
1da177e4
LT		 3621 }
3622
3623 return qc;
3624}
3625
1da177e4
LT		 3626/**
3627 * ata_qc_free - free unused ata_queued_cmd
3628 * @qc: Command to complete
3629 *
3630 * Designed to free unused ata_queued_cmd object
3631 * in case something prevents using it.
3632 *
3633 * LOCKING:
0cba632b 3634 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3635 */
3636void ata_qc_free(struct ata_queued_cmd *qc)
3637{
4ba946e9
TH		 3638 struct ata_port *ap = qc->ap;
3639 unsigned int tag;
3640
a4631474 3641 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
1da177e4 3642
4ba946e9
TH		 3643 qc->flags = 0;
3644 tag = qc->tag;
3645 if (likely(ata_tag_valid(tag))) {
3646 if (tag == ap->active_tag)
3647 ap->active_tag = ATA_TAG_POISON;
3648 qc->tag = ATA_TAG_POISON;
3649 clear_bit(tag, &ap->qactive);
3650 }
1da177e4
LT		 3651}
3652
76014427 3653void __ata_qc_complete(struct ata_queued_cmd *qc)
1da177e4 3654{
a4631474
TH		 3655 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
3656 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
1da177e4
LT		 3657
3658 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
3659 ata_sg_clean(qc);
3660
3f3791d3
AL		 3661 /* atapi: mark qc as inactive to prevent the interrupt handler
3662 * from completing the command twice later, before the error handler
3663 * is called. (when rc != 0 and atapi request sense is needed)
3664 */
3665 qc->flags &= ~ATA_QCFLAG_ACTIVE;
3666
1da177e4 3667 /* call completion callback */
77853bf2 3668 qc->complete_fn(qc);
1da177e4
LT		 3669}
3670
3671static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
3672{
3673 struct ata_port *ap = qc->ap;
3674
3675 switch (qc->tf.protocol) {
3676 case ATA_PROT_DMA:
3677 case ATA_PROT_ATAPI_DMA:
3678 return 1;
3679
3680 case ATA_PROT_ATAPI:
3681 case ATA_PROT_PIO:
3682 case ATA_PROT_PIO_MULT:
3683 if (ap->flags & ATA_FLAG_PIO_DMA)
3684 return 1;
3685
3686 /* fall through */
3687
3688 default:
3689 return 0;
3690 }
3691
3692 /* never reached */
3693}
3694
3695/**
3696 * ata_qc_issue - issue taskfile to device
3697 * @qc: command to issue to device
3698 *
3699 * Prepare an ATA command to submission to device.
3700 * This includes mapping the data into a DMA-able
3701 * area, filling in the S/G table, and finally
3702 * writing the taskfile to hardware, starting the command.
3703 *
3704 * LOCKING:
3705 * spin_lock_irqsave(host_set lock)
3706 *
3707 * RETURNS:
9a3d9eb0 3708 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 3709 */
3710
9a3d9eb0 3711unsigned int ata_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 3712{
3713 struct ata_port *ap = qc->ap;
3714
3715 if (ata_should_dma_map(qc)) {
3716 if (qc->flags & ATA_QCFLAG_SG) {
3717 if (ata_sg_setup(qc))
8e436af9 3718 goto sg_err;
1da177e4
LT		 3719 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
3720 if (ata_sg_setup_one(qc))
8e436af9 3721 goto sg_err;
1da177e4
LT		 3722 }
3723 } else {
3724 qc->flags &= ~ATA_QCFLAG_DMAMAP;
3725 }
3726
3727 ap->ops->qc_prep(qc);
3728
3729 qc->ap->active_tag = qc->tag;
3730 qc->flags |= ATA_QCFLAG_ACTIVE;
3731
3732 return ap->ops->qc_issue(qc);
3733
8e436af9
TH		 3734sg_err:
3735 qc->flags &= ~ATA_QCFLAG_DMAMAP;
9a3d9eb0 3736 return AC_ERR_SYSTEM;
1da177e4
LT		 3737}
3738
0baab86b 3739
1da177e4
LT		 3740/**
3741 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
3742 * @qc: command to issue to device
3743 *
3744 * Using various libata functions and hooks, this function
3745 * starts an ATA command. ATA commands are grouped into
3746 * classes called "protocols", and issuing each type of protocol
3747 * is slightly different.
3748 *
0baab86b
EF		 3749 * May be used as the qc_issue() entry in ata_port_operations.
3750 *
1da177e4
LT		 3751 * LOCKING:
3752 * spin_lock_irqsave(host_set lock)
3753 *
3754 * RETURNS:
9a3d9eb0 3755 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 3756 */
3757
9a3d9eb0 3758unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
1da177e4
LT		 3759{
3760 struct ata_port *ap = qc->ap;
3761
3762 ata_dev_select(ap, qc->dev->devno, 1, 0);
3763
3764 switch (qc->tf.protocol) {
3765 case ATA_PROT_NODATA:
e5338254 3766 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3767 break;
3768
3769 case ATA_PROT_DMA:
3770 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3771 ap->ops->bmdma_setup(qc); /* set up bmdma */
3772 ap->ops->bmdma_start(qc); /* initiate bmdma */
3773 break;
3774
3775 case ATA_PROT_PIO: /* load tf registers, initiate polling pio */
3776 ata_qc_set_polling(qc);
e5338254 3777 ata_tf_to_host(ap, &qc->tf);
14be71f4 3778 ap->hsm_task_state = HSM_ST;
95064379 3779 ata_queue_pio_task(ap);
1da177e4
LT		 3780 break;
3781
3782 case ATA_PROT_ATAPI:
3783 ata_qc_set_polling(qc);
e5338254 3784 ata_tf_to_host(ap, &qc->tf);
95064379 3785 ata_queue_packet_task(ap);
1da177e4
LT		 3786 break;
3787
3788 case ATA_PROT_ATAPI_NODATA:
c1389503 3789 ap->flags |= ATA_FLAG_NOINTR;
e5338254 3790 ata_tf_to_host(ap, &qc->tf);
95064379 3791 ata_queue_packet_task(ap);
1da177e4
LT		 3792 break;
3793
3794 case ATA_PROT_ATAPI_DMA:
c1389503 3795 ap->flags |= ATA_FLAG_NOINTR;
1da177e4
LT		 3796 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3797 ap->ops->bmdma_setup(qc); /* set up bmdma */
95064379 3798 ata_queue_packet_task(ap);
1da177e4
LT		 3799 break;
3800
3801 default:
3802 WARN_ON(1);
9a3d9eb0 3803 return AC_ERR_SYSTEM;
1da177e4
LT		 3804 }
3805
3806 return 0;
3807}
3808
3809/**
0baab86b 3810 * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
1da177e4
LT		 3811 * @qc: Info associated with this ATA transaction.
3812 *
3813 * LOCKING:
3814 * spin_lock_irqsave(host_set lock)
3815 */
3816
3817static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
3818{
3819 struct ata_port *ap = qc->ap;
3820 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3821 u8 dmactl;
3822 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3823
3824 /* load PRD table addr. */
3825 mb(); /* make sure PRD table writes are visible to controller */
3826 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
3827
3828 /* specify data direction, triple-check start bit is clear */
3829 dmactl = readb(mmio + ATA_DMA_CMD);
3830 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3831 if (!rw)
3832 dmactl |= ATA_DMA_WR;
3833 writeb(dmactl, mmio + ATA_DMA_CMD);
3834
3835 /* issue r/w command */
3836 ap->ops->exec_command(ap, &qc->tf);
3837}
3838
3839/**
b73fc89f 3840 * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
1da177e4
LT		 3841 * @qc: Info associated with this ATA transaction.
3842 *
3843 * LOCKING:
3844 * spin_lock_irqsave(host_set lock)
3845 */
3846
3847static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
3848{
3849 struct ata_port *ap = qc->ap;
3850 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3851 u8 dmactl;
3852
3853 /* start host DMA transaction */
3854 dmactl = readb(mmio + ATA_DMA_CMD);
3855 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
3856
3857 /* Strictly, one may wish to issue a readb() here, to
3858 * flush the mmio write. However, control also passes
3859 * to the hardware at this point, and it will interrupt
3860 * us when we are to resume control. So, in effect,
3861 * we don't care when the mmio write flushes.
3862 * Further, a read of the DMA status register _immediately_
3863 * following the write may not be what certain flaky hardware
3864 * is expected, so I think it is best to not add a readb()
3865 * without first all the MMIO ATA cards/mobos.
3866 * Or maybe I'm just being paranoid.
3867 */
3868}
3869
3870/**
3871 * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
3872 * @qc: Info associated with this ATA transaction.
3873 *
3874 * LOCKING:
3875 * spin_lock_irqsave(host_set lock)
3876 */
3877
3878static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
3879{
3880 struct ata_port *ap = qc->ap;
3881 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3882 u8 dmactl;
3883
3884 /* load PRD table addr. */
3885 outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
3886
3887 /* specify data direction, triple-check start bit is clear */
3888 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3889 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3890 if (!rw)
3891 dmactl |= ATA_DMA_WR;
3892 outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3893
3894 /* issue r/w command */
3895 ap->ops->exec_command(ap, &qc->tf);
3896}
3897
3898/**
3899 * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
3900 * @qc: Info associated with this ATA transaction.
3901 *
3902 * LOCKING:
3903 * spin_lock_irqsave(host_set lock)
3904 */
3905
3906static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
3907{
3908 struct ata_port *ap = qc->ap;
3909 u8 dmactl;
3910
3911 /* start host DMA transaction */
3912 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3913 outb(dmactl | ATA_DMA_START,
3914 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3915}
3916
0baab86b
EF		 3917
3918/**
3919 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3920 * @qc: Info associated with this ATA transaction.
3921 *
3922 * Writes the ATA_DMA_START flag to the DMA command register.
3923 *
3924 * May be used as the bmdma_start() entry in ata_port_operations.
3925 *
3926 * LOCKING:
3927 * spin_lock_irqsave(host_set lock)
3928 */
1da177e4
LT		 3929void ata_bmdma_start(struct ata_queued_cmd *qc)
3930{
3931 if (qc->ap->flags & ATA_FLAG_MMIO)
3932 ata_bmdma_start_mmio(qc);
3933 else
3934 ata_bmdma_start_pio(qc);
3935}
3936
0baab86b
EF		 3937
3938/**
3939 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
3940 * @qc: Info associated with this ATA transaction.
3941 *
3942 * Writes address of PRD table to device's PRD Table Address
3943 * register, sets the DMA control register, and calls
3944 * ops->exec_command() to start the transfer.
3945 *
3946 * May be used as the bmdma_setup() entry in ata_port_operations.
3947 *
3948 * LOCKING:
3949 * spin_lock_irqsave(host_set lock)
3950 */
1da177e4
LT		 3951void ata_bmdma_setup(struct ata_queued_cmd *qc)
3952{
3953 if (qc->ap->flags & ATA_FLAG_MMIO)
3954 ata_bmdma_setup_mmio(qc);
3955 else
3956 ata_bmdma_setup_pio(qc);
3957}
3958
0baab86b
EF		 3959
3960/**
3961 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
decc6d0b 3962 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3963 *
3964 * Clear interrupt and error flags in DMA status register.
3965 *
3966 * May be used as the irq_clear() entry in ata_port_operations.
3967 *
3968 * LOCKING:
3969 * spin_lock_irqsave(host_set lock)
3970 */
3971
1da177e4
LT		 3972void ata_bmdma_irq_clear(struct ata_port *ap)
3973{
3974 if (ap->flags & ATA_FLAG_MMIO) {
3975 void __iomem *mmio = ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
3976 writeb(readb(mmio), mmio);
3977 } else {
3978 unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
3979 outb(inb(addr), addr);
3980 }
3981
3982}
3983
0baab86b
EF		 3984
3985/**
3986 * ata_bmdma_status - Read PCI IDE BMDMA status
decc6d0b 3987 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3988 *
3989 * Read and return BMDMA status register.
3990 *
3991 * May be used as the bmdma_status() entry in ata_port_operations.
3992 *
3993 * LOCKING:
3994 * spin_lock_irqsave(host_set lock)
3995 */
3996
1da177e4
LT		 3997u8 ata_bmdma_status(struct ata_port *ap)
3998{
3999 u8 host_stat;
4000 if (ap->flags & ATA_FLAG_MMIO) {
4001 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4002 host_stat = readb(mmio + ATA_DMA_STATUS);
4003 } else
ee500aab 4004 host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
1da177e4
LT		 4005 return host_stat;
4006}
4007
0baab86b
EF		 4008
4009/**
4010 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
b73fc89f 4011 * @qc: Command we are ending DMA for
0baab86b
EF		 4012 *
4013 * Clears the ATA_DMA_START flag in the dma control register
4014 *
4015 * May be used as the bmdma_stop() entry in ata_port_operations.
4016 *
4017 * LOCKING:
4018 * spin_lock_irqsave(host_set lock)
4019 */
4020
b73fc89f 4021void ata_bmdma_stop(struct ata_queued_cmd *qc)
1da177e4 4022{
b73fc89f 4023 struct ata_port *ap = qc->ap;
1da177e4
LT		 4024 if (ap->flags & ATA_FLAG_MMIO) {
4025 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4026
4027 /* clear start/stop bit */
4028 writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
4029 mmio + ATA_DMA_CMD);
4030 } else {
4031 /* clear start/stop bit */
4032 outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
4033 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4034 }
4035
4036 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
4037 ata_altstatus(ap); /* dummy read */
4038}
4039
4040/**
4041 * ata_host_intr - Handle host interrupt for given (port, task)
4042 * @ap: Port on which interrupt arrived (possibly...)
4043 * @qc: Taskfile currently active in engine
4044 *
4045 * Handle host interrupt for given queued command. Currently,
4046 * only DMA interrupts are handled. All other commands are
4047 * handled via polling with interrupts disabled (nIEN bit).
4048 *
4049 * LOCKING:
4050 * spin_lock_irqsave(host_set lock)
4051 *
4052 * RETURNS:
4053 * One if interrupt was handled, zero if not (shared irq).
4054 */
4055
4056inline unsigned int ata_host_intr (struct ata_port *ap,
4057 struct ata_queued_cmd *qc)
4058{
4059 u8 status, host_stat;
4060
4061 switch (qc->tf.protocol) {
4062
4063 case ATA_PROT_DMA:
4064 case ATA_PROT_ATAPI_DMA:
4065 case ATA_PROT_ATAPI:
4066 /* check status of DMA engine */
4067 host_stat = ap->ops->bmdma_status(ap);
4068 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
4069
4070 /* if it's not our irq... */
4071 if (!(host_stat & ATA_DMA_INTR))
4072 goto idle_irq;
4073
4074 /* before we do anything else, clear DMA-Start bit */
b73fc89f 4075 ap->ops->bmdma_stop(qc);
1da177e4
LT		 4076
4077 /* fall through */
4078
4079 case ATA_PROT_ATAPI_NODATA:
4080 case ATA_PROT_NODATA:
4081 /* check altstatus */
4082 status = ata_altstatus(ap);
4083 if (status & ATA_BUSY)
4084 goto idle_irq;
4085
4086 /* check main status, clearing INTRQ */
4087 status = ata_chk_status(ap);
4088 if (unlikely(status & ATA_BUSY))
4089 goto idle_irq;
4090 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
4091 ap->id, qc->tf.protocol, status);
4092
4093 /* ack bmdma irq events */
4094 ap->ops->irq_clear(ap);
4095
4096 /* complete taskfile transaction */
a22e2eb0
AL		 4097 qc->err_mask |= ac_err_mask(status);
4098 ata_qc_complete(qc);
1da177e4
LT		 4099 break;
4100
4101 default:
4102 goto idle_irq;
4103 }
4104
4105 return 1; /* irq handled */
4106
4107idle_irq:
4108 ap->stats.idle_irq++;
4109
4110#ifdef ATA_IRQ_TRAP
4111 if ((ap->stats.idle_irq % 1000) == 0) {
4112 handled = 1;
4113 ata_irq_ack(ap, 0); /* debug trap */
4114 printk(KERN_WARNING "ata%d: irq trap\n", ap->id);
4115 }
4116#endif
4117 return 0; /* irq not handled */
4118}
4119
4120/**
4121 * ata_interrupt - Default ATA host interrupt handler
0cba632b
JG		 4122 * @irq: irq line (unused)
4123 * @dev_instance: pointer to our ata_host_set information structure
1da177e4
LT		 4124 * @regs: unused
4125 *
0cba632b
JG		 4126 * Default interrupt handler for PCI IDE devices. Calls
4127 * ata_host_intr() for each port that is not disabled.
4128 *
1da177e4 4129 * LOCKING:
0cba632b 4130 * Obtains host_set lock during operation.
1da177e4
LT		 4131 *
4132 * RETURNS:
0cba632b 4133 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 4134 */
4135
4136irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
4137{
4138 struct ata_host_set *host_set = dev_instance;
4139 unsigned int i;
4140 unsigned int handled = 0;
4141 unsigned long flags;
4142
4143 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
4144 spin_lock_irqsave(&host_set->lock, flags);
4145
4146 for (i = 0; i < host_set->n_ports; i++) {
4147 struct ata_port *ap;
4148
4149 ap = host_set->ports[i];
c1389503
TH		 4150 if (ap &&
4151 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT		 4152 struct ata_queued_cmd *qc;
4153
4154 qc = ata_qc_from_tag(ap, ap->active_tag);
21b1ed74
AL		 4155 if (qc && (!(qc->tf.ctl & ATA_NIEN)) &&
4156 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 4157 handled |= ata_host_intr(ap, qc);
4158 }
4159 }
4160
4161 spin_unlock_irqrestore(&host_set->lock, flags);
4162
4163 return IRQ_RETVAL(handled);
4164}
4165
4166/**
4167 * atapi_packet_task - Write CDB bytes to hardware
4168 * @_data: Port to which ATAPI device is attached.
4169 *
4170 * When device has indicated its readiness to accept
4171 * a CDB, this function is called. Send the CDB.
4172 * If DMA is to be performed, exit immediately.
4173 * Otherwise, we are in polling mode, so poll
4174 * status under operation succeeds or fails.
4175 *
4176 * LOCKING:
4177 * Kernel thread context (may sleep)
4178 */
4179
4180static void atapi_packet_task(void *_data)
4181{
4182 struct ata_port *ap = _data;
4183 struct ata_queued_cmd *qc;
4184 u8 status;
4185
4186 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474
TH		 4187 WARN_ON(qc == NULL);
4188 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
1da177e4
LT		 4189
4190 /* sleep-wait for BSY to clear */
4191 DPRINTK("busy wait\n");
d8fe452b 4192 if (ata_busy_sleep(ap, ATA_TMOUT_CDB_QUICK, ATA_TMOUT_CDB)) {
11a56d24 4193 qc->err_mask |= AC_ERR_TIMEOUT;
d8fe452b
AL		 4194 goto err_out;
4195 }
1da177e4
LT		 4196
4197 /* make sure DRQ is set */
4198 status = ata_chk_status(ap);
d8fe452b 4199 if ((status & (ATA_BUSY | ATA_DRQ)) != ATA_DRQ) {
11a56d24 4200 qc->err_mask |= AC_ERR_HSM;
1da177e4 4201 goto err_out;
d8fe452b 4202 }
1da177e4
LT		 4203
4204 /* send SCSI cdb */
4205 DPRINTK("send cdb\n");
a4631474 4206 WARN_ON(ap->cdb_len < 12);
1da177e4 4207
c1389503
TH		 4208 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA ||
4209 qc->tf.protocol == ATA_PROT_ATAPI_NODATA) {
4210 unsigned long flags;
1da177e4 4211
c1389503
TH		 4212 /* Once we're done issuing command and kicking bmdma,
4213 * irq handler takes over. To not lose irq, we need
4214 * to clear NOINTR flag before sending cdb, but
4215 * interrupt handler shouldn't be invoked before we're
4216 * finished. Hence, the following locking.
4217 */
4218 spin_lock_irqsave(&ap->host_set->lock, flags);
4219 ap->flags &= ~ATA_FLAG_NOINTR;
4220 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
4221 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA)
4222 ap->ops->bmdma_start(qc); /* initiate bmdma */
4223 spin_unlock_irqrestore(&ap->host_set->lock, flags);
4224 } else {
4225 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
1da177e4 4226
c1389503 4227 /* PIO commands are handled by polling */
14be71f4 4228 ap->hsm_task_state = HSM_ST;
95064379 4229 ata_queue_pio_task(ap);
1da177e4
LT		 4230 }
4231
4232 return;
4233
4234err_out:
a22e2eb0 4235 ata_poll_qc_complete(qc);
1da177e4
LT		 4236}
4237
0baab86b 4238
9b847548
JA		 4239/*
4240 * Execute a 'simple' command, that only consists of the opcode 'cmd' itself,
4241 * without filling any other registers
4242 */
4243static int ata_do_simple_cmd(struct ata_port *ap, struct ata_device *dev,
4244 u8 cmd)
4245{
4246 struct ata_taskfile tf;
4247 int err;
4248
4249 ata_tf_init(ap, &tf, dev->devno);
4250
4251 tf.command = cmd;
4252 tf.flags |= ATA_TFLAG_DEVICE;
4253 tf.protocol = ATA_PROT_NODATA;
4254
4255 err = ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0);
4256 if (err)
4257 printk(KERN_ERR "%s: ata command failed: %d\n",
4258 __FUNCTION__, err);
4259
4260 return err;
4261}
4262
4263static int ata_flush_cache(struct ata_port *ap, struct ata_device *dev)
4264{
4265 u8 cmd;
4266
4267 if (!ata_try_flush_cache(dev))
4268 return 0;
4269
4270 if (ata_id_has_flush_ext(dev->id))
4271 cmd = ATA_CMD_FLUSH_EXT;
4272 else
4273 cmd = ATA_CMD_FLUSH;
4274
4275 return ata_do_simple_cmd(ap, dev, cmd);
4276}
4277
4278static int ata_standby_drive(struct ata_port *ap, struct ata_device *dev)
4279{
4280 return ata_do_simple_cmd(ap, dev, ATA_CMD_STANDBYNOW1);
4281}
4282
4283static int ata_start_drive(struct ata_port *ap, struct ata_device *dev)
4284{
4285 return ata_do_simple_cmd(ap, dev, ATA_CMD_IDLEIMMEDIATE);
4286}
4287
4288/**
4289 * ata_device_resume - wakeup a previously suspended devices
c893a3ae
RD		 4290 * @ap: port the device is connected to
4291 * @dev: the device to resume
9b847548
JA		 4292 *
4293 * Kick the drive back into action, by sending it an idle immediate
4294 * command and making sure its transfer mode matches between drive
4295 * and host.
4296 *
4297 */
4298int ata_device_resume(struct ata_port *ap, struct ata_device *dev)
4299{
4300 if (ap->flags & ATA_FLAG_SUSPENDED) {
4301 ap->flags &= ~ATA_FLAG_SUSPENDED;
4302 ata_set_mode(ap);
4303 }
4304 if (!ata_dev_present(dev))
4305 return 0;
4306 if (dev->class == ATA_DEV_ATA)
4307 ata_start_drive(ap, dev);
4308
4309 return 0;
4310}
4311
4312/**
4313 * ata_device_suspend - prepare a device for suspend
c893a3ae
RD		 4314 * @ap: port the device is connected to
4315 * @dev: the device to suspend
9b847548
JA		 4316 *
4317 * Flush the cache on the drive, if appropriate, then issue a
4318 * standbynow command.
9b847548
JA		 4319 */
4320int ata_device_suspend(struct ata_port *ap, struct ata_device *dev)
4321{
4322 if (!ata_dev_present(dev))
4323 return 0;
4324 if (dev->class == ATA_DEV_ATA)
4325 ata_flush_cache(ap, dev);
4326
4327 ata_standby_drive(ap, dev);
4328 ap->flags |= ATA_FLAG_SUSPENDED;
4329 return 0;
4330}
4331
c893a3ae
RD		 4332/**
4333 * ata_port_start - Set port up for dma.
4334 * @ap: Port to initialize
4335 *
4336 * Called just after data structures for each port are
4337 * initialized. Allocates space for PRD table.
4338 *
4339 * May be used as the port_start() entry in ata_port_operations.
4340 *
4341 * LOCKING:
4342 * Inherited from caller.
4343 */
4344
1da177e4
LT		 4345int ata_port_start (struct ata_port *ap)
4346{
4347 struct device *dev = ap->host_set->dev;
6037d6bb 4348 int rc;
1da177e4
LT		 4349
4350 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
4351 if (!ap->prd)
4352 return -ENOMEM;
4353
6037d6bb
JG		 4354 rc = ata_pad_alloc(ap, dev);
4355 if (rc) {
cedc9a47 4356 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4357 return rc;
cedc9a47
JG		 4358 }
4359
1da177e4
LT		 4360 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
4361
4362 return 0;
4363}
4364
0baab86b
EF		 4365
4366/**
4367 * ata_port_stop - Undo ata_port_start()
4368 * @ap: Port to shut down
4369 *
4370 * Frees the PRD table.
4371 *
4372 * May be used as the port_stop() entry in ata_port_operations.
4373 *
4374 * LOCKING:
6f0ef4fa 4375 * Inherited from caller.
0baab86b
EF		 4376 */
4377
1da177e4
LT		 4378void ata_port_stop (struct ata_port *ap)
4379{
4380 struct device *dev = ap->host_set->dev;
4381
4382 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4383 ata_pad_free(ap, dev);
1da177e4
LT		 4384}
4385
aa8f0dc6
JG		 4386void ata_host_stop (struct ata_host_set *host_set)
4387{
4388 if (host_set->mmio_base)
4389 iounmap(host_set->mmio_base);
4390}
4391
4392
1da177e4
LT		 4393/**
4394 * ata_host_remove - Unregister SCSI host structure with upper layers
4395 * @ap: Port to unregister
4396 * @do_unregister: 1 if we fully unregister, 0 to just stop the port
4397 *
4398 * LOCKING:
6f0ef4fa 4399 * Inherited from caller.
1da177e4
LT		 4400 */
4401
4402static void ata_host_remove(struct ata_port *ap, unsigned int do_unregister)
4403{
4404 struct Scsi_Host *sh = ap->host;
4405
4406 DPRINTK("ENTER\n");
4407
4408 if (do_unregister)
4409 scsi_remove_host(sh);
4410
4411 ap->ops->port_stop(ap);
4412}
4413
4414/**
4415 * ata_host_init - Initialize an ata_port structure
4416 * @ap: Structure to initialize
4417 * @host: associated SCSI mid-layer structure
4418 * @host_set: Collection of hosts to which @ap belongs
4419 * @ent: Probe information provided by low-level driver
4420 * @port_no: Port number associated with this ata_port
4421 *
0cba632b
JG		 4422 * Initialize a new ata_port structure, and its associated
4423 * scsi_host.
4424 *
1da177e4 4425 * LOCKING:
0cba632b 4426 * Inherited from caller.
1da177e4
LT		 4427 */
4428
4429static void ata_host_init(struct ata_port *ap, struct Scsi_Host *host,
4430 struct ata_host_set *host_set,
057ace5e 4431 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 4432{
4433 unsigned int i;
4434
4435 host->max_id = 16;
4436 host->max_lun = 1;
4437 host->max_channel = 1;
4438 host->unique_id = ata_unique_id++;
4439 host->max_cmd_len = 12;
12413197 4440
1da177e4
LT		 4441 ap->flags = ATA_FLAG_PORT_DISABLED;
4442 ap->id = host->unique_id;
4443 ap->host = host;
4444 ap->ctl = ATA_DEVCTL_OBS;
4445 ap->host_set = host_set;
4446 ap->port_no = port_no;
4447 ap->hard_port_no =
4448 ent->legacy_mode ? ent->hard_port_no : port_no;
4449 ap->pio_mask = ent->pio_mask;
4450 ap->mwdma_mask = ent->mwdma_mask;
4451 ap->udma_mask = ent->udma_mask;
4452 ap->flags |= ent->host_flags;
4453 ap->ops = ent->port_ops;
4454 ap->cbl = ATA_CBL_NONE;
4455 ap->active_tag = ATA_TAG_POISON;
4456 ap->last_ctl = 0xFF;
4457
4458 INIT_WORK(&ap->packet_task, atapi_packet_task, ap);
4459 INIT_WORK(&ap->pio_task, ata_pio_task, ap);
a72ec4ce 4460 INIT_LIST_HEAD(&ap->eh_done_q);
1da177e4
LT		 4461
4462 for (i = 0; i < ATA_MAX_DEVICES; i++)
4463 ap->device[i].devno = i;
4464
4465#ifdef ATA_IRQ_TRAP
4466 ap->stats.unhandled_irq = 1;
4467 ap->stats.idle_irq = 1;
4468#endif
4469
4470 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
4471}
4472
4473/**
4474 * ata_host_add - Attach low-level ATA driver to system
4475 * @ent: Information provided by low-level driver
4476 * @host_set: Collections of ports to which we add
4477 * @port_no: Port number associated with this host
4478 *
0cba632b
JG		 4479 * Attach low-level ATA driver to system.
4480 *
1da177e4 4481 * LOCKING:
0cba632b 4482 * PCI/etc. bus probe sem.
1da177e4
LT		 4483 *
4484 * RETURNS:
0cba632b 4485 * New ata_port on success, for NULL on error.
1da177e4
LT		 4486 */
4487
057ace5e 4488static struct ata_port * ata_host_add(const struct ata_probe_ent *ent,
1da177e4
LT		 4489 struct ata_host_set *host_set,
4490 unsigned int port_no)
4491{
4492 struct Scsi_Host *host;
4493 struct ata_port *ap;
4494 int rc;
4495
4496 DPRINTK("ENTER\n");
4497 host = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
4498 if (!host)
4499 return NULL;
4500
4501 ap = (struct ata_port *) &host->hostdata[0];
4502
4503 ata_host_init(ap, host, host_set, ent, port_no);
4504
4505 rc = ap->ops->port_start(ap);
4506 if (rc)
4507 goto err_out;
4508
4509 return ap;
4510
4511err_out:
4512 scsi_host_put(host);
4513 return NULL;
4514}
4515
4516/**
0cba632b
JG		 4517 * ata_device_add - Register hardware device with ATA and SCSI layers
4518 * @ent: Probe information describing hardware device to be registered
4519 *
4520 * This function processes the information provided in the probe
4521 * information struct @ent, allocates the necessary ATA and SCSI
4522 * host information structures, initializes them, and registers
4523 * everything with requisite kernel subsystems.
4524 *
4525 * This function requests irqs, probes the ATA bus, and probes
4526 * the SCSI bus.
1da177e4
LT		 4527 *
4528 * LOCKING:
0cba632b 4529 * PCI/etc. bus probe sem.
1da177e4
LT		 4530 *
4531 * RETURNS:
0cba632b 4532 * Number of ports registered. Zero on error (no ports registered).
1da177e4
LT		 4533 */
4534
057ace5e 4535int ata_device_add(const struct ata_probe_ent *ent)
1da177e4
LT		 4536{
4537 unsigned int count = 0, i;
4538 struct device *dev = ent->dev;
4539 struct ata_host_set *host_set;
4540
4541 DPRINTK("ENTER\n");
4542 /* alloc a container for our list of ATA ports (buses) */
57f3bda8 4543 host_set = kzalloc(sizeof(struct ata_host_set) +
1da177e4
LT		 4544 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
4545 if (!host_set)
4546 return 0;
1da177e4
LT		 4547 spin_lock_init(&host_set->lock);
4548
4549 host_set->dev = dev;
4550 host_set->n_ports = ent->n_ports;
4551 host_set->irq = ent->irq;
4552 host_set->mmio_base = ent->mmio_base;
4553 host_set->private_data = ent->private_data;
4554 host_set->ops = ent->port_ops;
4555
4556 /* register each port bound to this device */
4557 for (i = 0; i < ent->n_ports; i++) {
4558 struct ata_port *ap;
4559 unsigned long xfer_mode_mask;
4560
4561 ap = ata_host_add(ent, host_set, i);
4562 if (!ap)
4563 goto err_out;
4564
4565 host_set->ports[i] = ap;
4566 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
4567 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
4568 (ap->pio_mask << ATA_SHIFT_PIO);
4569
4570 /* print per-port info to dmesg */
4571 printk(KERN_INFO "ata%u: %cATA max %s cmd 0x%lX ctl 0x%lX "
4572 "bmdma 0x%lX irq %lu\n",
4573 ap->id,
4574 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
4575 ata_mode_string(xfer_mode_mask),
4576 ap->ioaddr.cmd_addr,
4577 ap->ioaddr.ctl_addr,
4578 ap->ioaddr.bmdma_addr,
4579 ent->irq);
4580
4581 ata_chk_status(ap);
4582 host_set->ops->irq_clear(ap);
4583 count++;
4584 }
4585
57f3bda8
RD		 4586 if (!count)
4587 goto err_free_ret;
1da177e4
LT		 4588
4589 /* obtain irq, that is shared between channels */
4590 if (request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
4591 DRV_NAME, host_set))
4592 goto err_out;
4593
4594 /* perform each probe synchronously */
4595 DPRINTK("probe begin\n");
4596 for (i = 0; i < count; i++) {
4597 struct ata_port *ap;
4598 int rc;
4599
4600 ap = host_set->ports[i];
4601
c893a3ae 4602 DPRINTK("ata%u: bus probe begin\n", ap->id);
1da177e4 4603 rc = ata_bus_probe(ap);
c893a3ae 4604 DPRINTK("ata%u: bus probe end\n", ap->id);
1da177e4
LT		 4605
4606 if (rc) {
4607 /* FIXME: do something useful here?
4608 * Current libata behavior will
4609 * tear down everything when
4610 * the module is removed
4611 * or the h/w is unplugged.
4612 */
4613 }
4614
4615 rc = scsi_add_host(ap->host, dev);
4616 if (rc) {
4617 printk(KERN_ERR "ata%u: scsi_add_host failed\n",
4618 ap->id);
4619 /* FIXME: do something useful here */
4620 /* FIXME: handle unconditional calls to
4621 * scsi_scan_host and ata_host_remove, below,
4622 * at the very least
4623 */
4624 }
4625 }
4626
4627 /* probes are done, now scan each port's disk(s) */
c893a3ae 4628 DPRINTK("host probe begin\n");
1da177e4
LT		 4629 for (i = 0; i < count; i++) {
4630 struct ata_port *ap = host_set->ports[i];
4631
644dd0cc 4632 ata_scsi_scan_host(ap);
1da177e4
LT		 4633 }
4634
4635 dev_set_drvdata(dev, host_set);
4636
4637 VPRINTK("EXIT, returning %u\n", ent->n_ports);
4638 return ent->n_ports; /* success */
4639
4640err_out:
4641 for (i = 0; i < count; i++) {
4642 ata_host_remove(host_set->ports[i], 1);
4643 scsi_host_put(host_set->ports[i]->host);
4644 }
57f3bda8 4645err_free_ret:
1da177e4
LT		 4646 kfree(host_set);
4647 VPRINTK("EXIT, returning 0\n");
4648 return 0;
4649}
4650
17b14451
AC		 4651/**
4652 * ata_host_set_remove - PCI layer callback for device removal
4653 * @host_set: ATA host set that was removed
4654 *
4655 * Unregister all objects associated with this host set. Free those
4656 * objects.
4657 *
4658 * LOCKING:
4659 * Inherited from calling layer (may sleep).
4660 */
4661
17b14451
AC		 4662void ata_host_set_remove(struct ata_host_set *host_set)
4663{
4664 struct ata_port *ap;
4665 unsigned int i;
4666
4667 for (i = 0; i < host_set->n_ports; i++) {
4668 ap = host_set->ports[i];
4669 scsi_remove_host(ap->host);
4670 }
4671
4672 free_irq(host_set->irq, host_set);
4673
4674 for (i = 0; i < host_set->n_ports; i++) {
4675 ap = host_set->ports[i];
4676
4677 ata_scsi_release(ap->host);
4678
4679 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
4680 struct ata_ioports *ioaddr = &ap->ioaddr;
4681
4682 if (ioaddr->cmd_addr == 0x1f0)
4683 release_region(0x1f0, 8);
4684 else if (ioaddr->cmd_addr == 0x170)
4685 release_region(0x170, 8);
4686 }
4687
4688 scsi_host_put(ap->host);
4689 }
4690
4691 if (host_set->ops->host_stop)
4692 host_set->ops->host_stop(host_set);
4693
4694 kfree(host_set);
4695}
4696
1da177e4
LT		 4697/**
4698 * ata_scsi_release - SCSI layer callback hook for host unload
4699 * @host: libata host to be unloaded
4700 *
4701 * Performs all duties necessary to shut down a libata port...
4702 * Kill port kthread, disable port, and release resources.
4703 *
4704 * LOCKING:
4705 * Inherited from SCSI layer.
4706 *
4707 * RETURNS:
4708 * One.
4709 */
4710
4711int ata_scsi_release(struct Scsi_Host *host)
4712{
4713 struct ata_port *ap = (struct ata_port *) &host->hostdata[0];
4714
4715 DPRINTK("ENTER\n");
4716
4717 ap->ops->port_disable(ap);
4718 ata_host_remove(ap, 0);
4719
4720 DPRINTK("EXIT\n");
4721 return 1;
4722}
4723
4724/**
4725 * ata_std_ports - initialize ioaddr with standard port offsets.
4726 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 4727 *
4728 * Utility function which initializes data_addr, error_addr,
4729 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
4730 * device_addr, status_addr, and command_addr to standard offsets
4731 * relative to cmd_addr.
4732 *
4733 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 4734 */
0baab86b 4735
1da177e4
LT		 4736void ata_std_ports(struct ata_ioports *ioaddr)
4737{
4738 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
4739 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
4740 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
4741 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
4742 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
4743 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
4744 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
4745 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
4746 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
4747 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
4748}
4749
0baab86b 4750
374b1873
JG		 4751#ifdef CONFIG_PCI
4752
4753void ata_pci_host_stop (struct ata_host_set *host_set)
4754{
4755 struct pci_dev *pdev = to_pci_dev(host_set->dev);
4756
4757 pci_iounmap(pdev, host_set->mmio_base);
4758}
4759
1da177e4
LT		 4760/**
4761 * ata_pci_remove_one - PCI layer callback for device removal
4762 * @pdev: PCI device that was removed
4763 *
4764 * PCI layer indicates to libata via this hook that
6f0ef4fa 4765 * hot-unplug or module unload event has occurred.
1da177e4
LT		 4766 * Handle this by unregistering all objects associated
4767 * with this PCI device. Free those objects. Then finally
4768 * release PCI resources and disable device.
4769 *
4770 * LOCKING:
4771 * Inherited from PCI layer (may sleep).
4772 */
4773
4774void ata_pci_remove_one (struct pci_dev *pdev)
4775{
4776 struct device *dev = pci_dev_to_dev(pdev);
4777 struct ata_host_set *host_set = dev_get_drvdata(dev);
1da177e4 4778
17b14451 4779 ata_host_set_remove(host_set);
1da177e4
LT		 4780 pci_release_regions(pdev);
4781 pci_disable_device(pdev);
4782 dev_set_drvdata(dev, NULL);
4783}
4784
4785/* move to PCI subsystem */
057ace5e 4786int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 4787{
4788 unsigned long tmp = 0;
4789
4790 switch (bits->width) {
4791 case 1: {
4792 u8 tmp8 = 0;
4793 pci_read_config_byte(pdev, bits->reg, &tmp8);
4794 tmp = tmp8;
4795 break;
4796 }
4797 case 2: {
4798 u16 tmp16 = 0;
4799 pci_read_config_word(pdev, bits->reg, &tmp16);
4800 tmp = tmp16;
4801 break;
4802 }
4803 case 4: {
4804 u32 tmp32 = 0;
4805 pci_read_config_dword(pdev, bits->reg, &tmp32);
4806 tmp = tmp32;
4807 break;
4808 }
4809
4810 default:
4811 return -EINVAL;
4812 }
4813
4814 tmp &= bits->mask;
4815
4816 return (tmp == bits->val) ? 1 : 0;
4817}
9b847548
JA		 4818
4819int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t state)
4820{
4821 pci_save_state(pdev);
4822 pci_disable_device(pdev);
4823 pci_set_power_state(pdev, PCI_D3hot);
4824 return 0;
4825}
4826
4827int ata_pci_device_resume(struct pci_dev *pdev)
4828{
4829 pci_set_power_state(pdev, PCI_D0);
4830 pci_restore_state(pdev);
4831 pci_enable_device(pdev);
4832 pci_set_master(pdev);
4833 return 0;
4834}
1da177e4
LT		 4835#endif /* CONFIG_PCI */
4836
4837
1da177e4
LT		 4838static int __init ata_init(void)
4839{
4840 ata_wq = create_workqueue("ata");
4841 if (!ata_wq)
4842 return -ENOMEM;
4843
4844 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
4845 return 0;
4846}
4847
4848static void __exit ata_exit(void)
4849{
4850 destroy_workqueue(ata_wq);
4851}
4852
4853module_init(ata_init);
4854module_exit(ata_exit);
4855
67846b30
JG		 4856static unsigned long ratelimit_time;
4857static spinlock_t ata_ratelimit_lock = SPIN_LOCK_UNLOCKED;
4858
4859int ata_ratelimit(void)
4860{
4861 int rc;
4862 unsigned long flags;
4863
4864 spin_lock_irqsave(&ata_ratelimit_lock, flags);
4865
4866 if (time_after(jiffies, ratelimit_time)) {
4867 rc = 1;
4868 ratelimit_time = jiffies + (HZ/5);
4869 } else
4870 rc = 0;
4871
4872 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
4873
4874 return rc;
4875}
4876
1da177e4
LT		 4877/*
4878 * libata is essentially a library of internal helper functions for
4879 * low-level ATA host controller drivers. As such, the API/ABI is
4880 * likely to change as new drivers are added and updated.
4881 * Do not depend on ABI/API stability.
4882 */
4883
4884EXPORT_SYMBOL_GPL(ata_std_bios_param);
4885EXPORT_SYMBOL_GPL(ata_std_ports);
4886EXPORT_SYMBOL_GPL(ata_device_add);
17b14451 4887EXPORT_SYMBOL_GPL(ata_host_set_remove);
1da177e4
LT		 4888EXPORT_SYMBOL_GPL(ata_sg_init);
4889EXPORT_SYMBOL_GPL(ata_sg_init_one);
76014427 4890EXPORT_SYMBOL_GPL(__ata_qc_complete);
1da177e4
LT		 4891EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
4892EXPORT_SYMBOL_GPL(ata_eng_timeout);
4893EXPORT_SYMBOL_GPL(ata_tf_load);
4894EXPORT_SYMBOL_GPL(ata_tf_read);
4895EXPORT_SYMBOL_GPL(ata_noop_dev_select);
4896EXPORT_SYMBOL_GPL(ata_std_dev_select);
4897EXPORT_SYMBOL_GPL(ata_tf_to_fis);
4898EXPORT_SYMBOL_GPL(ata_tf_from_fis);
4899EXPORT_SYMBOL_GPL(ata_check_status);
4900EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 4901EXPORT_SYMBOL_GPL(ata_exec_command);
4902EXPORT_SYMBOL_GPL(ata_port_start);
4903EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 4904EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4
LT		 4905EXPORT_SYMBOL_GPL(ata_interrupt);
4906EXPORT_SYMBOL_GPL(ata_qc_prep);
4907EXPORT_SYMBOL_GPL(ata_bmdma_setup);
4908EXPORT_SYMBOL_GPL(ata_bmdma_start);
4909EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
4910EXPORT_SYMBOL_GPL(ata_bmdma_status);
4911EXPORT_SYMBOL_GPL(ata_bmdma_stop);
4912EXPORT_SYMBOL_GPL(ata_port_probe);
4913EXPORT_SYMBOL_GPL(sata_phy_reset);
4914EXPORT_SYMBOL_GPL(__sata_phy_reset);
4915EXPORT_SYMBOL_GPL(ata_bus_reset);
8a19ac89 4916EXPORT_SYMBOL_GPL(ata_std_probeinit);
c2bd5804
TH		 4917EXPORT_SYMBOL_GPL(ata_std_softreset);
4918EXPORT_SYMBOL_GPL(sata_std_hardreset);
4919EXPORT_SYMBOL_GPL(ata_std_postreset);
4920EXPORT_SYMBOL_GPL(ata_std_probe_reset);
a62c0fc5 4921EXPORT_SYMBOL_GPL(ata_drive_probe_reset);
1da177e4 4922EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 4923EXPORT_SYMBOL_GPL(ata_ratelimit);
6f8b9958 4924EXPORT_SYMBOL_GPL(ata_busy_sleep);
1da177e4
LT		 4925EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
4926EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
f29841e0 4927EXPORT_SYMBOL_GPL(ata_scsi_timed_out);
1da177e4
LT		 4928EXPORT_SYMBOL_GPL(ata_scsi_error);
4929EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
4930EXPORT_SYMBOL_GPL(ata_scsi_release);
4931EXPORT_SYMBOL_GPL(ata_host_intr);
4932EXPORT_SYMBOL_GPL(ata_dev_classify);
4933EXPORT_SYMBOL_GPL(ata_dev_id_string);
0e949ff3 4934EXPORT_SYMBOL_GPL(ata_dev_id_c_string);
6f2f3812 4935EXPORT_SYMBOL_GPL(ata_dev_config);
1da177e4 4936EXPORT_SYMBOL_GPL(ata_scsi_simulate);
a72ec4ce
TH		 4937EXPORT_SYMBOL_GPL(ata_eh_qc_complete);
4938EXPORT_SYMBOL_GPL(ata_eh_qc_retry);
1da177e4 4939
1bc4ccff 4940EXPORT_SYMBOL_GPL(ata_pio_need_iordy);
452503f9
AC		 4941EXPORT_SYMBOL_GPL(ata_timing_compute);
4942EXPORT_SYMBOL_GPL(ata_timing_merge);
4943
1da177e4
LT		 4944#ifdef CONFIG_PCI
4945EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 4946EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 4947EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
4948EXPORT_SYMBOL_GPL(ata_pci_init_one);
4949EXPORT_SYMBOL_GPL(ata_pci_remove_one);
9b847548
JA		 4950EXPORT_SYMBOL_GPL(ata_pci_device_suspend);
4951EXPORT_SYMBOL_GPL(ata_pci_device_resume);
1da177e4 4952#endif /* CONFIG_PCI */
9b847548
JA		 4953
4954EXPORT_SYMBOL_GPL(ata_device_suspend);
4955EXPORT_SYMBOL_GPL(ata_device_resume);
4956EXPORT_SYMBOL_GPL(ata_scsi_device_suspend);
4957EXPORT_SYMBOL_GPL(ata_scsi_device_resume);
Clone of davem's net-next-2.6 tree