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Merge branch 'bugzilla-16422' into release
[net-next-2.6.git] / drivers / scsi / ipr.h
CommitLineData
1da177e4
LT		 1/*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
fa195afe 22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
1da177e4
LT		 23 * that broke 64bit platforms.
24 */
25
26#ifndef _IPR_H
27#define _IPR_H
28
29#include <linux/types.h>
30#include <linux/completion.h>
35a39691 31#include <linux/libata.h>
1da177e4
LT		 32#include <linux/list.h>
33#include <linux/kref.h>
34#include <scsi/scsi.h>
35#include <scsi/scsi_cmnd.h>
36
37/*
38 * Literals
39 */
d7b4627f
WB		 40#define IPR_DRIVER_VERSION "2.5.0"
41#define IPR_DRIVER_DATE "(February 11, 2010)"
1da177e4 42
1da177e4
LT		 43/*
44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
45 * ops per device for devices not running tagged command queuing.
46 * This can be adjusted at runtime through sysfs device attributes.
47 */
48#define IPR_MAX_CMD_PER_LUN 6
b5145d25 49#define IPR_MAX_CMD_PER_ATA_LUN 1
1da177e4
LT		 50
51/*
52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
53 * ops the mid-layer can send to the adapter.
54 */
55#define IPR_NUM_BASE_CMD_BLKS 100
56
60e7486b 57#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
d7b4627f
WB		 58
59#define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
60#define PCI_DEVICE_ID_IBM_CROC_ASIC_E2 0x034A
60e7486b 61
1da177e4
LT		 62#define IPR_SUBS_DEV_ID_2780 0x0264
63#define IPR_SUBS_DEV_ID_5702 0x0266
64#define IPR_SUBS_DEV_ID_5703 0x0278
65#define IPR_SUBS_DEV_ID_572E 0x028D
66#define IPR_SUBS_DEV_ID_573E 0x02D3
67#define IPR_SUBS_DEV_ID_573D 0x02D4
68#define IPR_SUBS_DEV_ID_571A 0x02C0
69#define IPR_SUBS_DEV_ID_571B 0x02BE
70#define IPR_SUBS_DEV_ID_571E 0x02BF
86f51436
BK		 71#define IPR_SUBS_DEV_ID_571F 0x02D5
72#define IPR_SUBS_DEV_ID_572A 0x02C1
73#define IPR_SUBS_DEV_ID_572B 0x02C2
60e7486b 74#define IPR_SUBS_DEV_ID_572F 0x02C3
185eb31c 75#define IPR_SUBS_DEV_ID_574E 0x030A
86f51436 76#define IPR_SUBS_DEV_ID_575B 0x030D
60e7486b 77#define IPR_SUBS_DEV_ID_575C 0x0338
185eb31c 78#define IPR_SUBS_DEV_ID_57B3 0x033A
60e7486b
BK		 79#define IPR_SUBS_DEV_ID_57B7 0x0360
80#define IPR_SUBS_DEV_ID_57B8 0x02C2
1da177e4 81
d7b4627f
WB		 82#define IPR_SUBS_DEV_ID_57B4 0x033B
83#define IPR_SUBS_DEV_ID_57B2 0x035F
84#define IPR_SUBS_DEV_ID_57C6 0x0357
85
86#define IPR_SUBS_DEV_ID_57B5 0x033C
87#define IPR_SUBS_DEV_ID_57CE 0x035E
88#define IPR_SUBS_DEV_ID_57B1 0x0355
89
90#define IPR_SUBS_DEV_ID_574D 0x0356
91#define IPR_SUBS_DEV_ID_575D 0x035D
92
1da177e4
LT		 93#define IPR_NAME "ipr"
94
95/*
96 * Return codes
97 */
98#define IPR_RC_JOB_CONTINUE 1
99#define IPR_RC_JOB_RETURN 2
100
101/*
102 * IOASCs
103 */
104#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
65f56475 105#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
1da177e4
LT		 106#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
107#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
108#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
109#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
110#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
111#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
dfed823e 112#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
1da177e4 113#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
b0df54bb
BK		 114#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
115#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
1da177e4
LT		 116#define IPR_IOASC_BUS_WAS_RESET 0x06290000
117#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
118#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
119
120#define IPR_FIRST_DRIVER_IOASC 0x10000000
121#define IPR_IOASC_IOA_WAS_RESET 0x10000001
122#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
123
5469cb5b
BK		 124/* Driver data flags */
125#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
463fc696 126#define IPR_USE_PCI_WARM_RESET 0x00000002
5469cb5b 127
ac719aba 128#define IPR_DEFAULT_MAX_ERROR_DUMP 984
1da177e4
LT		 129#define IPR_NUM_LOG_HCAMS 2
130#define IPR_NUM_CFG_CHG_HCAMS 2
131#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
3e7ebdfa
WB		 132
133#define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
134#define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
135
d71a8b0c 136#define IPR_MAX_NUM_TARGETS_PER_BUS 256
1da177e4
LT		 137#define IPR_MAX_NUM_LUNS_PER_TARGET 256
138#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
139#define IPR_VSET_BUS 0xff
140#define IPR_IOA_BUS 0xff
141#define IPR_IOA_TARGET 0xff
142#define IPR_IOA_LUN 0xff
b5145d25 143#define IPR_MAX_NUM_BUSES 16
1da177e4
LT		 144#define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
145
146#define IPR_NUM_RESET_RELOAD_RETRIES 3
147
148/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
149#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
f72919ec 150 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
1da177e4
LT		 151
152#define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
153#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
154 IPR_NUM_INTERNAL_CMD_BLKS)
155
156#define IPR_MAX_PHYSICAL_DEVS 192
3e7ebdfa
WB		 157#define IPR_DEFAULT_SIS64_DEVS 1024
158#define IPR_MAX_SIS64_DEVS 4096
1da177e4
LT		 159
160#define IPR_MAX_SGLIST 64
161#define IPR_IOA_MAX_SECTORS 32767
162#define IPR_VSET_MAX_SECTORS 512
163#define IPR_MAX_CDB_LEN 16
3feeb89d 164#define IPR_MAX_HRRQ_RETRIES 3
1da177e4
LT		 165
166#define IPR_DEFAULT_BUS_WIDTH 16
167#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
168#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
169#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
170#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
171
172#define IPR_IOA_RES_HANDLE 0xffffffff
1121b794 173#define IPR_INVALID_RES_HANDLE 0
1da177e4
LT		 174#define IPR_IOA_RES_ADDR 0x00ffffff
175
176/*
177 * Adapter Commands
178 */
179#define IPR_QUERY_RSRC_STATE 0xC2
180#define IPR_RESET_DEVICE 0xC3
181#define IPR_RESET_TYPE_SELECT 0x80
182#define IPR_LUN_RESET 0x40
183#define IPR_TARGET_RESET 0x20
184#define IPR_BUS_RESET 0x10
b5145d25 185#define IPR_ATA_PHY_RESET 0x80
1da177e4
LT		 186#define IPR_ID_HOST_RR_Q 0xC4
187#define IPR_QUERY_IOA_CONFIG 0xC5
188#define IPR_CANCEL_ALL_REQUESTS 0xCE
189#define IPR_HOST_CONTROLLED_ASYNC 0xCF
190#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
191#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
192#define IPR_SET_SUPPORTED_DEVICES 0xFB
3e7ebdfa 193#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
1da177e4
LT		 194#define IPR_IOA_SHUTDOWN 0xF7
195#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
196
197/*
198 * Timeouts
199 */
200#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
201#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
202#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
ac09c349 203#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
1da177e4
LT		 204#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
205#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
206#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
207#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
208#define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
209#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
210#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
211#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
5469cb5b 212#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
1da177e4
LT		 213#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
214#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
215#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
463fc696 216#define IPR_PCI_RESET_TIMEOUT (HZ / 2)
1da177e4
LT		 217#define IPR_DUMP_TIMEOUT (15 * HZ)
218
219/*
220 * SCSI Literals
221 */
222#define IPR_VENDOR_ID_LEN 8
223#define IPR_PROD_ID_LEN 16
224#define IPR_SERIAL_NUM_LEN 8
225
226/*
227 * Hardware literals
228 */
229#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
230#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
231#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
232#define IPR_GET_FMT2_BAR_SEL(mbx) \
233(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
234#define IPR_SDT_FMT2_BAR0_SEL 0x0
235#define IPR_SDT_FMT2_BAR1_SEL 0x1
236#define IPR_SDT_FMT2_BAR2_SEL 0x2
237#define IPR_SDT_FMT2_BAR3_SEL 0x3
238#define IPR_SDT_FMT2_BAR4_SEL 0x4
239#define IPR_SDT_FMT2_BAR5_SEL 0x5
240#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
241#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
dcbad00e 242#define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
1da177e4 243#define IPR_DOORBELL 0x82800000
3d1d0da6 244#define IPR_RUNTIME_RESET 0x40000000
1da177e4 245
214777ba 246#define IPR_IPL_INIT_MIN_STAGE_TIME 5
438b0331 247#define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
214777ba
WB		 248#define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
249#define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
250#define IPR_IPL_INIT_STAGE_MASK 0xff000000
251#define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
252#define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
253
1da177e4
LT		 254#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
255#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
256#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
257#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
258#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
259#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
260#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
261#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
262#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
263#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
264#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
265
266#define IPR_PCII_ERROR_INTERRUPTS \
267(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
268IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
269
270#define IPR_PCII_OPER_INTERRUPTS \
271(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
272
273#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
274#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
275
276#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
277#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
278
279/*
280 * Dump literals
281 */
282#define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
283#define IPR_NUM_SDT_ENTRIES 511
284#define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
285
286/*
287 * Misc literals
288 */
289#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
290
291/*
292 * Adapter interface types
293 */
294
295struct ipr_res_addr {
296 u8 reserved;
297 u8 bus;
298 u8 target;
299 u8 lun;
300#define IPR_GET_PHYS_LOC(res_addr) \
301 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
302}__attribute__((packed, aligned (4)));
303
304struct ipr_std_inq_vpids {
305 u8 vendor_id[IPR_VENDOR_ID_LEN];
306 u8 product_id[IPR_PROD_ID_LEN];
307}__attribute__((packed));
308
cfc32139
BK		 309struct ipr_vpd {
310 struct ipr_std_inq_vpids vpids;
311 u8 sn[IPR_SERIAL_NUM_LEN];
312}__attribute__((packed));
313
ee0f05b8
BK		 314struct ipr_ext_vpd {
315 struct ipr_vpd vpd;
316 __be32 wwid[2];
317}__attribute__((packed));
318
1da177e4
LT		 319struct ipr_std_inq_data {
320 u8 peri_qual_dev_type;
321#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
322#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
323
324 u8 removeable_medium_rsvd;
325#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
326
327#define IPR_IS_DASD_DEVICE(std_inq) \
328((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
329!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
330
331#define IPR_IS_SES_DEVICE(std_inq) \
332(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
333
334 u8 version;
335 u8 aen_naca_fmt;
336 u8 additional_len;
337 u8 sccs_rsvd;
338 u8 bq_enc_multi;
339 u8 sync_cmdq_flags;
340
341 struct ipr_std_inq_vpids vpids;
342
343 u8 ros_rsvd_ram_rsvd[4];
344
345 u8 serial_num[IPR_SERIAL_NUM_LEN];
346}__attribute__ ((packed));
347
3e7ebdfa
WB		 348#define IPR_RES_TYPE_AF_DASD 0x00
349#define IPR_RES_TYPE_GENERIC_SCSI 0x01
350#define IPR_RES_TYPE_VOLUME_SET 0x02
351#define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
352#define IPR_RES_TYPE_GENERIC_ATA 0x04
353#define IPR_RES_TYPE_ARRAY 0x05
354#define IPR_RES_TYPE_IOAFP 0xff
355
1da177e4 356struct ipr_config_table_entry {
b5145d25
BK		 357 u8 proto;
358#define IPR_PROTO_SATA 0x02
359#define IPR_PROTO_SATA_ATAPI 0x03
360#define IPR_PROTO_SAS_STP 0x06
3e7ebdfa 361#define IPR_PROTO_SAS_STP_ATAPI 0x07
1da177e4
LT		 362 u8 array_id;
363 u8 flags;
3e7ebdfa 364#define IPR_IS_IOA_RESOURCE 0x80
1da177e4 365 u8 rsvd_subtype;
3e7ebdfa
WB		 366
367#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
368#define IPR_QUEUE_FROZEN_MODEL 0
ee0a90fa
BK		 369#define IPR_QUEUE_NACA_MODEL 1
370
1da177e4
LT		 371 struct ipr_res_addr res_addr;
372 __be32 res_handle;
373 __be32 reserved4[2];
374 struct ipr_std_inq_data std_inq_data;
375}__attribute__ ((packed, aligned (4)));
376
3e7ebdfa
WB		 377struct ipr_config_table_entry64 {
378 u8 res_type;
379 u8 proto;
380 u8 vset_num;
381 u8 array_id;
382 __be16 flags;
383 __be16 res_flags;
384#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
385 __be32 res_handle;
386 u8 dev_id_type;
387 u8 reserved[3];
388 __be64 dev_id;
389 __be64 lun;
390 __be64 lun_wwn[2];
391#define IPR_MAX_RES_PATH_LENGTH 24
392 __be64 res_path;
393 struct ipr_std_inq_data std_inq_data;
394 u8 reserved2[4];
395 __be64 reserved3[2]; // description text
396 u8 reserved4[8];
397}__attribute__ ((packed, aligned (8)));
398
1da177e4
LT		 399struct ipr_config_table_hdr {
400 u8 num_entries;
401 u8 flags;
402#define IPR_UCODE_DOWNLOAD_REQ 0x10
403 __be16 reserved;
404}__attribute__((packed, aligned (4)));
405
3e7ebdfa
WB		 406struct ipr_config_table_hdr64 {
407 __be16 num_entries;
408 __be16 reserved;
409 u8 flags;
410 u8 reserved2[11];
411}__attribute__((packed, aligned (4)));
412
1da177e4
LT		 413struct ipr_config_table {
414 struct ipr_config_table_hdr hdr;
3e7ebdfa 415 struct ipr_config_table_entry dev[0];
1da177e4
LT		 416}__attribute__((packed, aligned (4)));
417
3e7ebdfa
WB		 418struct ipr_config_table64 {
419 struct ipr_config_table_hdr64 hdr64;
420 struct ipr_config_table_entry64 dev[0];
421}__attribute__((packed, aligned (8)));
422
423struct ipr_config_table_entry_wrapper {
424 union {
425 struct ipr_config_table_entry *cfgte;
426 struct ipr_config_table_entry64 *cfgte64;
427 } u;
428};
429
1da177e4 430struct ipr_hostrcb_cfg_ch_not {
3e7ebdfa
WB		 431 union {
432 struct ipr_config_table_entry cfgte;
433 struct ipr_config_table_entry64 cfgte64;
434 } u;
1da177e4
LT		 435 u8 reserved[936];
436}__attribute__((packed, aligned (4)));
437
438struct ipr_supported_device {
439 __be16 data_length;
440 u8 reserved;
441 u8 num_records;
442 struct ipr_std_inq_vpids vpids;
443 u8 reserved2[16];
444}__attribute__((packed, aligned (4)));
445
446/* Command packet structure */
447struct ipr_cmd_pkt {
448 __be16 reserved; /* Reserved by IOA */
449 u8 request_type;
450#define IPR_RQTYPE_SCSICDB 0x00
451#define IPR_RQTYPE_IOACMD 0x01
452#define IPR_RQTYPE_HCAM 0x02
b5145d25 453#define IPR_RQTYPE_ATA_PASSTHRU 0x04
1da177e4 454
a32c055f 455 u8 reserved2;
1da177e4
LT		 456
457 u8 flags_hi;
458#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
459#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
460#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
461#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
462#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
463
464 u8 flags_lo;
465#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
466#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
467#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
468#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
469#define IPR_FLAGS_LO_ORDERED_TASK 0x04
470#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
471#define IPR_FLAGS_LO_ACA_TASK 0x08
472
473 u8 cdb[16];
474 __be16 timeout;
475}__attribute__ ((packed, aligned(4)));
476
a32c055f 477struct ipr_ioarcb_ata_regs { /* 22 bytes */
b5145d25
BK		 478 u8 flags;
479#define IPR_ATA_FLAG_PACKET_CMD 0x80
480#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
481#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
482 u8 reserved[3];
483
484 __be16 data;
485 u8 feature;
486 u8 nsect;
487 u8 lbal;
488 u8 lbam;
489 u8 lbah;
490 u8 device;
491 u8 command;
492 u8 reserved2[3];
493 u8 hob_feature;
494 u8 hob_nsect;
495 u8 hob_lbal;
496 u8 hob_lbam;
497 u8 hob_lbah;
498 u8 ctl;
499}__attribute__ ((packed, aligned(4)));
500
51b1c7e1
BK		 501struct ipr_ioadl_desc {
502 __be32 flags_and_data_len;
503#define IPR_IOADL_FLAGS_MASK 0xff000000
504#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
505#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
506#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
507#define IPR_IOADL_FLAGS_READ 0x48000000
508#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
509#define IPR_IOADL_FLAGS_WRITE 0x68000000
510#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
511#define IPR_IOADL_FLAGS_LAST 0x01000000
512
513 __be32 address;
514}__attribute__((packed, aligned (8)));
515
a32c055f
WB		 516struct ipr_ioadl64_desc {
517 __be32 flags;
518 __be32 data_len;
519 __be64 address;
520}__attribute__((packed, aligned (16)));
521
522struct ipr_ata64_ioadl {
523 struct ipr_ioarcb_ata_regs regs;
524 u16 reserved[5];
525 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
526}__attribute__((packed, aligned (16)));
527
b5145d25
BK		 528struct ipr_ioarcb_add_data {
529 union {
530 struct ipr_ioarcb_ata_regs regs;
51b1c7e1 531 struct ipr_ioadl_desc ioadl[5];
b5145d25 532 __be32 add_cmd_parms[10];
a32c055f
WB		 533 } u;
534}__attribute__ ((packed, aligned (4)));
535
536struct ipr_ioarcb_sis64_add_addr_ecb {
537 __be64 ioasa_host_pci_addr;
538 __be64 data_ioadl_addr;
539 __be64 reserved;
540 __be32 ext_control_buf[4];
541}__attribute__((packed, aligned (8)));
b5145d25 542
1da177e4
LT		 543/* IOA Request Control Block 128 bytes */
544struct ipr_ioarcb {
a32c055f
WB		 545 union {
546 __be32 ioarcb_host_pci_addr;
547 __be64 ioarcb_host_pci_addr64;
548 } a;
1da177e4
LT		 549 __be32 res_handle;
550 __be32 host_response_handle;
551 __be32 reserved1;
552 __be32 reserved2;
553 __be32 reserved3;
554
a32c055f 555 __be32 data_transfer_length;
1da177e4
LT		 556 __be32 read_data_transfer_length;
557 __be32 write_ioadl_addr;
a32c055f 558 __be32 ioadl_len;
1da177e4
LT		 559 __be32 read_ioadl_addr;
560 __be32 read_ioadl_len;
561
562 __be32 ioasa_host_pci_addr;
563 __be16 ioasa_len;
564 __be16 reserved4;
565
566 struct ipr_cmd_pkt cmd_pkt;
567
a32c055f
WB		 568 __be16 add_cmd_parms_offset;
569 __be16 add_cmd_parms_len;
570
571 union {
572 struct ipr_ioarcb_add_data add_data;
573 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
574 } u;
575
1da177e4
LT		 576}__attribute__((packed, aligned (4)));
577
1da177e4
LT		 578struct ipr_ioasa_vset {
579 __be32 failing_lba_hi;
580 __be32 failing_lba_lo;
c8f74892 581 __be32 reserved;
1da177e4
LT		 582}__attribute__((packed, aligned (4)));
583
584struct ipr_ioasa_af_dasd {
585 __be32 failing_lba;
c8f74892 586 __be32 reserved[2];
1da177e4
LT		 587}__attribute__((packed, aligned (4)));
588
589struct ipr_ioasa_gpdd {
590 u8 end_state;
591 u8 bus_phase;
592 __be16 reserved;
c8f74892 593 __be32 ioa_data[2];
1da177e4
LT		 594}__attribute__((packed, aligned (4)));
595
b5145d25
BK		 596struct ipr_ioasa_gata {
597 u8 error;
598 u8 nsect; /* Interrupt reason */
599 u8 lbal;
600 u8 lbam;
601 u8 lbah;
602 u8 device;
603 u8 status;
604 u8 alt_status; /* ATA CTL */
605 u8 hob_nsect;
606 u8 hob_lbal;
607 u8 hob_lbam;
608 u8 hob_lbah;
609}__attribute__((packed, aligned (4)));
610
c8f74892
BK		 611struct ipr_auto_sense {
612 __be16 auto_sense_len;
613 __be16 ioa_data_len;
614 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
615};
1da177e4 616
96d21f00 617struct ipr_ioasa_hdr {
1da177e4
LT		 618 __be32 ioasc;
619#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
620#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
621#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
622#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
623
624 __be16 ret_stat_len; /* Length of the returned IOASA */
625
626 __be16 avail_stat_len; /* Total Length of status available. */
627
628 __be32 residual_data_len; /* number of bytes in the host data */
629 /* buffers that were not used by the IOARCB command. */
630
631 __be32 ilid;
632#define IPR_NO_ILID 0
633#define IPR_DRIVER_ILID 0xffffffff
634
635 __be32 fd_ioasc;
636
637 __be32 fd_phys_locator;
638
639 __be32 fd_res_handle;
640
641 __be32 ioasc_specific; /* status code specific field */
c8f74892
BK		 642#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
643#define IPR_AUTOSENSE_VALID 0x40000000
b5145d25 644#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
1da177e4
LT		 645#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
646#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
647#define IPR_FIELD_POINTER_MASK 0x0000ffff
648
96d21f00
WB		 649}__attribute__((packed, aligned (4)));
650
651struct ipr_ioasa {
652 struct ipr_ioasa_hdr hdr;
653
654 union {
655 struct ipr_ioasa_vset vset;
656 struct ipr_ioasa_af_dasd dasd;
657 struct ipr_ioasa_gpdd gpdd;
658 struct ipr_ioasa_gata gata;
659 } u;
660
661 struct ipr_auto_sense auto_sense;
662}__attribute__((packed, aligned (4)));
663
664struct ipr_ioasa64 {
665 struct ipr_ioasa_hdr hdr;
666 u8 fd_res_path[8];
667
1da177e4
LT		 668 union {
669 struct ipr_ioasa_vset vset;
670 struct ipr_ioasa_af_dasd dasd;
671 struct ipr_ioasa_gpdd gpdd;
b5145d25 672 struct ipr_ioasa_gata gata;
1da177e4 673 } u;
c8f74892
BK		 674
675 struct ipr_auto_sense auto_sense;
1da177e4
LT		 676}__attribute__((packed, aligned (4)));
677
678struct ipr_mode_parm_hdr {
679 u8 length;
680 u8 medium_type;
681 u8 device_spec_parms;
682 u8 block_desc_len;
683}__attribute__((packed));
684
685struct ipr_mode_pages {
686 struct ipr_mode_parm_hdr hdr;
687 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
688}__attribute__((packed));
689
690struct ipr_mode_page_hdr {
691 u8 ps_page_code;
692#define IPR_MODE_PAGE_PS 0x80
693#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
694 u8 page_length;
695}__attribute__ ((packed));
696
697struct ipr_dev_bus_entry {
698 struct ipr_res_addr res_addr;
699 u8 flags;
700#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
701#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
702#define IPR_SCSI_ATTR_QAS_MASK 0xC0
703#define IPR_SCSI_ATTR_ENABLE_TM 0x20
704#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
705#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
706#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
707
708 u8 scsi_id;
709 u8 bus_width;
710 u8 extended_reset_delay;
711#define IPR_EXTENDED_RESET_DELAY 7
712
713 __be32 max_xfer_rate;
714
715 u8 spinup_delay;
716 u8 reserved3;
717 __be16 reserved4;
718}__attribute__((packed, aligned (4)));
719
720struct ipr_mode_page28 {
721 struct ipr_mode_page_hdr hdr;
722 u8 num_entries;
723 u8 entry_length;
724 struct ipr_dev_bus_entry bus[0];
725}__attribute__((packed));
726
ac09c349
BK		 727struct ipr_mode_page24 {
728 struct ipr_mode_page_hdr hdr;
729 u8 flags;
730#define IPR_ENABLE_DUAL_IOA_AF 0x80
731}__attribute__((packed));
732
1da177e4
LT		 733struct ipr_ioa_vpd {
734 struct ipr_std_inq_data std_inq_data;
735 u8 ascii_part_num[12];
736 u8 reserved[40];
737 u8 ascii_plant_code[4];
738}__attribute__((packed));
739
740struct ipr_inquiry_page3 {
741 u8 peri_qual_dev_type;
742 u8 page_code;
743 u8 reserved1;
744 u8 page_length;
745 u8 ascii_len;
746 u8 reserved2[3];
747 u8 load_id[4];
748 u8 major_release;
749 u8 card_type;
750 u8 minor_release[2];
751 u8 ptf_number[4];
752 u8 patch_number[4];
753}__attribute__((packed));
754
ac09c349
BK		 755struct ipr_inquiry_cap {
756 u8 peri_qual_dev_type;
757 u8 page_code;
758 u8 reserved1;
759 u8 page_length;
760 u8 ascii_len;
761 u8 reserved2;
762 u8 sis_version[2];
763 u8 cap;
764#define IPR_CAP_DUAL_IOA_RAID 0x80
765 u8 reserved3[15];
766}__attribute__((packed));
767
62275040
BK		 768#define IPR_INQUIRY_PAGE0_ENTRIES 20
769struct ipr_inquiry_page0 {
770 u8 peri_qual_dev_type;
771 u8 page_code;
772 u8 reserved1;
773 u8 len;
774 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
775}__attribute__((packed));
776
1da177e4 777struct ipr_hostrcb_device_data_entry {
cfc32139 778 struct ipr_vpd vpd;
1da177e4 779 struct ipr_res_addr dev_res_addr;
cfc32139
BK		 780 struct ipr_vpd new_vpd;
781 struct ipr_vpd ioa_last_with_dev_vpd;
782 struct ipr_vpd cfc_last_with_dev_vpd;
1da177e4
LT		 783 __be32 ioa_data[5];
784}__attribute__((packed, aligned (4)));
785
ee0f05b8
BK		 786struct ipr_hostrcb_device_data_entry_enhanced {
787 struct ipr_ext_vpd vpd;
788 u8 ccin[4];
789 struct ipr_res_addr dev_res_addr;
790 struct ipr_ext_vpd new_vpd;
791 u8 new_ccin[4];
792 struct ipr_ext_vpd ioa_last_with_dev_vpd;
793 struct ipr_ext_vpd cfc_last_with_dev_vpd;
794}__attribute__((packed, aligned (4)));
795
4565e370
WB		 796struct ipr_hostrcb64_device_data_entry_enhanced {
797 struct ipr_ext_vpd vpd;
798 u8 ccin[4];
799 u8 res_path[8];
800 struct ipr_ext_vpd new_vpd;
801 u8 new_ccin[4];
802 struct ipr_ext_vpd ioa_last_with_dev_vpd;
803 struct ipr_ext_vpd cfc_last_with_dev_vpd;
804}__attribute__((packed, aligned (4)));
805
1da177e4 806struct ipr_hostrcb_array_data_entry {
cfc32139 807 struct ipr_vpd vpd;
1da177e4
LT		 808 struct ipr_res_addr expected_dev_res_addr;
809 struct ipr_res_addr dev_res_addr;
810}__attribute__((packed, aligned (4)));
811
4565e370
WB		 812struct ipr_hostrcb64_array_data_entry {
813 struct ipr_ext_vpd vpd;
814 u8 ccin[4];
815 u8 expected_res_path[8];
816 u8 res_path[8];
817}__attribute__((packed, aligned (4)));
818
ee0f05b8
BK		 819struct ipr_hostrcb_array_data_entry_enhanced {
820 struct ipr_ext_vpd vpd;
821 u8 ccin[4];
822 struct ipr_res_addr expected_dev_res_addr;
823 struct ipr_res_addr dev_res_addr;
824}__attribute__((packed, aligned (4)));
825
1da177e4 826struct ipr_hostrcb_type_ff_error {
438b0331 827 __be32 ioa_data[758];
1da177e4
LT		 828}__attribute__((packed, aligned (4)));
829
830struct ipr_hostrcb_type_01_error {
831 __be32 seek_counter;
832 __be32 read_counter;
833 u8 sense_data[32];
834 __be32 ioa_data[236];
835}__attribute__((packed, aligned (4)));
836
837struct ipr_hostrcb_type_02_error {
cfc32139
BK		 838 struct ipr_vpd ioa_vpd;
839 struct ipr_vpd cfc_vpd;
840 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
841 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
1da177e4 842 __be32 ioa_data[3];
1da177e4
LT		 843}__attribute__((packed, aligned (4)));
844
ee0f05b8
BK		 845struct ipr_hostrcb_type_12_error {
846 struct ipr_ext_vpd ioa_vpd;
847 struct ipr_ext_vpd cfc_vpd;
848 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
849 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
850 __be32 ioa_data[3];
851}__attribute__((packed, aligned (4)));
852
1da177e4 853struct ipr_hostrcb_type_03_error {
cfc32139
BK		 854 struct ipr_vpd ioa_vpd;
855 struct ipr_vpd cfc_vpd;
1da177e4
LT		 856 __be32 errors_detected;
857 __be32 errors_logged;
858 u8 ioa_data[12];
cfc32139 859 struct ipr_hostrcb_device_data_entry dev[3];
1da177e4
LT		 860}__attribute__((packed, aligned (4)));
861
ee0f05b8
BK		 862struct ipr_hostrcb_type_13_error {
863 struct ipr_ext_vpd ioa_vpd;
864 struct ipr_ext_vpd cfc_vpd;
865 __be32 errors_detected;
866 __be32 errors_logged;
867 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
868}__attribute__((packed, aligned (4)));
869
4565e370
WB		 870struct ipr_hostrcb_type_23_error {
871 struct ipr_ext_vpd ioa_vpd;
872 struct ipr_ext_vpd cfc_vpd;
873 __be32 errors_detected;
874 __be32 errors_logged;
875 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
876}__attribute__((packed, aligned (4)));
877
1da177e4 878struct ipr_hostrcb_type_04_error {
cfc32139
BK		 879 struct ipr_vpd ioa_vpd;
880 struct ipr_vpd cfc_vpd;
1da177e4
LT		 881 u8 ioa_data[12];
882 struct ipr_hostrcb_array_data_entry array_member[10];
883 __be32 exposed_mode_adn;
884 __be32 array_id;
cfc32139 885 struct ipr_vpd incomp_dev_vpd;
1da177e4
LT		 886 __be32 ioa_data2;
887 struct ipr_hostrcb_array_data_entry array_member2[8];
888 struct ipr_res_addr last_func_vset_res_addr;
889 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
890 u8 protection_level[8];
1da177e4
LT		 891}__attribute__((packed, aligned (4)));
892
ee0f05b8
BK		 893struct ipr_hostrcb_type_14_error {
894 struct ipr_ext_vpd ioa_vpd;
895 struct ipr_ext_vpd cfc_vpd;
896 __be32 exposed_mode_adn;
897 __be32 array_id;
898 struct ipr_res_addr last_func_vset_res_addr;
899 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
900 u8 protection_level[8];
901 __be32 num_entries;
902 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
903}__attribute__((packed, aligned (4)));
904
4565e370
WB		 905struct ipr_hostrcb_type_24_error {
906 struct ipr_ext_vpd ioa_vpd;
907 struct ipr_ext_vpd cfc_vpd;
908 u8 reserved[2];
909 u8 exposed_mode_adn;
910#define IPR_INVALID_ARRAY_DEV_NUM 0xff
911 u8 array_id;
912 u8 last_res_path[8];
913 u8 protection_level[8];
914 struct ipr_ext_vpd array_vpd;
915 u8 description[16];
916 u8 reserved2[3];
917 u8 num_entries;
918 struct ipr_hostrcb64_array_data_entry array_member[32];
919}__attribute__((packed, aligned (4)));
920
b0df54bb
BK		 921struct ipr_hostrcb_type_07_error {
922 u8 failure_reason[64];
923 struct ipr_vpd vpd;
924 u32 data[222];
925}__attribute__((packed, aligned (4)));
926
ee0f05b8
BK		 927struct ipr_hostrcb_type_17_error {
928 u8 failure_reason[64];
929 struct ipr_ext_vpd vpd;
930 u32 data[476];
931}__attribute__((packed, aligned (4)));
932
49dc6a18
BK		 933struct ipr_hostrcb_config_element {
934 u8 type_status;
935#define IPR_PATH_CFG_TYPE_MASK 0xF0
936#define IPR_PATH_CFG_NOT_EXIST 0x00
937#define IPR_PATH_CFG_IOA_PORT 0x10
938#define IPR_PATH_CFG_EXP_PORT 0x20
939#define IPR_PATH_CFG_DEVICE_PORT 0x30
940#define IPR_PATH_CFG_DEVICE_LUN 0x40
941
942#define IPR_PATH_CFG_STATUS_MASK 0x0F
943#define IPR_PATH_CFG_NO_PROB 0x00
944#define IPR_PATH_CFG_DEGRADED 0x01
945#define IPR_PATH_CFG_FAILED 0x02
946#define IPR_PATH_CFG_SUSPECT 0x03
947#define IPR_PATH_NOT_DETECTED 0x04
948#define IPR_PATH_INCORRECT_CONN 0x05
949
950 u8 cascaded_expander;
951 u8 phy;
952 u8 link_rate;
953#define IPR_PHY_LINK_RATE_MASK 0x0F
954
955 __be32 wwid[2];
956}__attribute__((packed, aligned (4)));
957
4565e370
WB		 958struct ipr_hostrcb64_config_element {
959 __be16 length;
960 u8 descriptor_id;
961#define IPR_DESCRIPTOR_MASK 0xC0
962#define IPR_DESCRIPTOR_SIS64 0x00
963
964 u8 reserved;
965 u8 type_status;
966
967 u8 reserved2[2];
968 u8 link_rate;
969
970 u8 res_path[8];
971 __be32 wwid[2];
972}__attribute__((packed, aligned (8)));
973
49dc6a18
BK		 974struct ipr_hostrcb_fabric_desc {
975 __be16 length;
976 u8 ioa_port;
977 u8 cascaded_expander;
978 u8 phy;
979 u8 path_state;
980#define IPR_PATH_ACTIVE_MASK 0xC0
981#define IPR_PATH_NO_INFO 0x00
982#define IPR_PATH_ACTIVE 0x40
983#define IPR_PATH_NOT_ACTIVE 0x80
984
985#define IPR_PATH_STATE_MASK 0x0F
986#define IPR_PATH_STATE_NO_INFO 0x00
987#define IPR_PATH_HEALTHY 0x01
988#define IPR_PATH_DEGRADED 0x02
989#define IPR_PATH_FAILED 0x03
990
991 __be16 num_entries;
992 struct ipr_hostrcb_config_element elem[1];
993}__attribute__((packed, aligned (4)));
994
4565e370
WB		 995struct ipr_hostrcb64_fabric_desc {
996 __be16 length;
997 u8 descriptor_id;
998
999 u8 reserved;
1000 u8 path_state;
1001
1002 u8 reserved2[2];
1003 u8 res_path[8];
1004 u8 reserved3[6];
1005 __be16 num_entries;
1006 struct ipr_hostrcb64_config_element elem[1];
1007}__attribute__((packed, aligned (8)));
1008
49dc6a18
BK		 1009#define for_each_fabric_cfg(fabric, cfg) \
1010 for (cfg = (fabric)->elem; \
1011 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1012 cfg++)
1013
1014struct ipr_hostrcb_type_20_error {
1015 u8 failure_reason[64];
1016 u8 reserved[3];
1017 u8 num_entries;
1018 struct ipr_hostrcb_fabric_desc desc[1];
1019}__attribute__((packed, aligned (4)));
1020
4565e370
WB		 1021struct ipr_hostrcb_type_30_error {
1022 u8 failure_reason[64];
1023 u8 reserved[3];
1024 u8 num_entries;
1025 struct ipr_hostrcb64_fabric_desc desc[1];
1026}__attribute__((packed, aligned (4)));
1027
1da177e4 1028struct ipr_hostrcb_error {
4565e370
WB		 1029 __be32 fd_ioasc;
1030 struct ipr_res_addr fd_res_addr;
1031 __be32 fd_res_handle;
1da177e4
LT		 1032 __be32 prc;
1033 union {
1034 struct ipr_hostrcb_type_ff_error type_ff_error;
1035 struct ipr_hostrcb_type_01_error type_01_error;
1036 struct ipr_hostrcb_type_02_error type_02_error;
1037 struct ipr_hostrcb_type_03_error type_03_error;
1038 struct ipr_hostrcb_type_04_error type_04_error;
b0df54bb 1039 struct ipr_hostrcb_type_07_error type_07_error;
ee0f05b8
BK		 1040 struct ipr_hostrcb_type_12_error type_12_error;
1041 struct ipr_hostrcb_type_13_error type_13_error;
1042 struct ipr_hostrcb_type_14_error type_14_error;
1043 struct ipr_hostrcb_type_17_error type_17_error;
49dc6a18 1044 struct ipr_hostrcb_type_20_error type_20_error;
1da177e4
LT		 1045 } u;
1046}__attribute__((packed, aligned (4)));
1047
4565e370
WB		 1048struct ipr_hostrcb64_error {
1049 __be32 fd_ioasc;
1050 __be32 ioa_fw_level;
1051 __be32 fd_res_handle;
1052 __be32 prc;
1053 __be64 fd_dev_id;
1054 __be64 fd_lun;
1055 u8 fd_res_path[8];
1056 __be64 time_stamp;
1057 u8 reserved[2];
1058 union {
1059 struct ipr_hostrcb_type_ff_error type_ff_error;
1060 struct ipr_hostrcb_type_12_error type_12_error;
1061 struct ipr_hostrcb_type_17_error type_17_error;
1062 struct ipr_hostrcb_type_23_error type_23_error;
1063 struct ipr_hostrcb_type_24_error type_24_error;
1064 struct ipr_hostrcb_type_30_error type_30_error;
1065 } u;
1066}__attribute__((packed, aligned (8)));
1067
1da177e4
LT		 1068struct ipr_hostrcb_raw {
1069 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1070}__attribute__((packed, aligned (4)));
1071
1072struct ipr_hcam {
1073 u8 op_code;
1074#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1075#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1076
1077 u8 notify_type;
1078#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1079#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1080#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1081#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1082#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1083
1084 u8 notifications_lost;
1085#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1086#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1087
1088 u8 flags;
1089#define IPR_HOSTRCB_INTERNAL_OPER 0x80
1090#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1091
1092 u8 overlay_id;
1093#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1094#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1095#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1096#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1097#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
b0df54bb 1098#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
ee0f05b8
BK		 1099#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1100#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1101#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1102#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1103#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
49dc6a18 1104#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
4565e370
WB		 1105#define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1106#define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1107#define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1108#define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1109#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1da177e4
LT		 1110
1111 u8 reserved1[3];
1112 __be32 ilid;
1113 __be32 time_since_last_ioa_reset;
1114 __be32 reserved2;
1115 __be32 length;
1116
1117 union {
1118 struct ipr_hostrcb_error error;
4565e370 1119 struct ipr_hostrcb64_error error64;
1da177e4
LT		 1120 struct ipr_hostrcb_cfg_ch_not ccn;
1121 struct ipr_hostrcb_raw raw;
1122 } u;
1123}__attribute__((packed, aligned (4)));
1124
1125struct ipr_hostrcb {
1126 struct ipr_hcam hcam;
1127 dma_addr_t hostrcb_dma;
1128 struct list_head queue;
49dc6a18 1129 struct ipr_ioa_cfg *ioa_cfg;
4565e370 1130 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1da177e4
LT		 1131};
1132
1133/* IPR smart dump table structures */
1134struct ipr_sdt_entry {
dcbad00e
WB		 1135 __be32 start_token;
1136 __be32 end_token;
1137 u8 reserved[4];
1da177e4
LT		 1138
1139 u8 flags;
1140#define IPR_SDT_ENDIAN 0x80
1141#define IPR_SDT_VALID_ENTRY 0x20
1142
1143 u8 resv;
1144 __be16 priority;
1145}__attribute__((packed, aligned (4)));
1146
1147struct ipr_sdt_header {
1148 __be32 state;
1149 __be32 num_entries;
1150 __be32 num_entries_used;
1151 __be32 dump_size;
1152}__attribute__((packed, aligned (4)));
1153
1154struct ipr_sdt {
1155 struct ipr_sdt_header hdr;
1156 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
1157}__attribute__((packed, aligned (4)));
1158
1159struct ipr_uc_sdt {
1160 struct ipr_sdt_header hdr;
1161 struct ipr_sdt_entry entry[1];
1162}__attribute__((packed, aligned (4)));
1163
1164/*
1165 * Driver types
1166 */
1167struct ipr_bus_attributes {
1168 u8 bus;
1169 u8 qas_enabled;
1170 u8 bus_width;
1171 u8 reserved;
1172 u32 max_xfer_rate;
1173};
1174
35a39691
BK		 1175struct ipr_sata_port {
1176 struct ipr_ioa_cfg *ioa_cfg;
1177 struct ata_port *ap;
1178 struct ipr_resource_entry *res;
1179 struct ipr_ioasa_gata ioasa;
1180};
1181
1da177e4 1182struct ipr_resource_entry {
1da177e4
LT		 1183 u8 needs_sync_complete:1;
1184 u8 in_erp:1;
1185 u8 add_to_ml:1;
1186 u8 del_from_ml:1;
1187 u8 resetting_device:1;
1188
3e7ebdfa
WB		 1189 u32 bus; /* AKA channel */
1190 u32 target; /* AKA id */
1191 u32 lun;
1192#define IPR_ARRAY_VIRTUAL_BUS 0x1
1193#define IPR_VSET_VIRTUAL_BUS 0x2
1194#define IPR_IOAFP_VIRTUAL_BUS 0x3
1195
1196#define IPR_GET_RES_PHYS_LOC(res) \
1197 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1198
1199 u8 ata_class;
1200
1201 u8 flags;
1202 __be16 res_flags;
1203
7be96900 1204 u8 type;
3e7ebdfa
WB		 1205
1206 u8 qmodel;
1207 struct ipr_std_inq_data std_inq_data;
1208
1209 __be32 res_handle;
1210 __be64 dev_id;
1211 struct scsi_lun dev_lun;
1212 u8 res_path[8];
1213
1214 struct ipr_ioa_cfg *ioa_cfg;
1da177e4 1215 struct scsi_device *sdev;
35a39691 1216 struct ipr_sata_port *sata_port;
1da177e4 1217 struct list_head queue;
3e7ebdfa 1218}; /* struct ipr_resource_entry */
1da177e4
LT		 1219
1220struct ipr_resource_hdr {
1221 u16 num_entries;
1222 u16 reserved;
1223};
1224
1da177e4
LT		 1225struct ipr_misc_cbs {
1226 struct ipr_ioa_vpd ioa_vpd;
62275040 1227 struct ipr_inquiry_page0 page0_data;
1da177e4 1228 struct ipr_inquiry_page3 page3_data;
ac09c349 1229 struct ipr_inquiry_cap cap;
1da177e4
LT		 1230 struct ipr_mode_pages mode_pages;
1231 struct ipr_supported_device supp_dev;
1232};
1233
1234struct ipr_interrupt_offsets {
1235 unsigned long set_interrupt_mask_reg;
1236 unsigned long clr_interrupt_mask_reg;
214777ba 1237 unsigned long clr_interrupt_mask_reg32;
1da177e4 1238 unsigned long sense_interrupt_mask_reg;
214777ba 1239 unsigned long sense_interrupt_mask_reg32;
1da177e4 1240 unsigned long clr_interrupt_reg;
214777ba 1241 unsigned long clr_interrupt_reg32;
1da177e4
LT		 1242
1243 unsigned long sense_interrupt_reg;
214777ba 1244 unsigned long sense_interrupt_reg32;
1da177e4
LT		 1245 unsigned long ioarrin_reg;
1246 unsigned long sense_uproc_interrupt_reg;
214777ba 1247 unsigned long sense_uproc_interrupt_reg32;
1da177e4 1248 unsigned long set_uproc_interrupt_reg;
214777ba 1249 unsigned long set_uproc_interrupt_reg32;
1da177e4 1250 unsigned long clr_uproc_interrupt_reg;
214777ba
WB		 1251 unsigned long clr_uproc_interrupt_reg32;
1252
1253 unsigned long init_feedback_reg;
dcbad00e
WB		 1254
1255 unsigned long dump_addr_reg;
1256 unsigned long dump_data_reg;
1da177e4
LT		 1257};
1258
1259struct ipr_interrupts {
1260 void __iomem *set_interrupt_mask_reg;
1261 void __iomem *clr_interrupt_mask_reg;
214777ba 1262 void __iomem *clr_interrupt_mask_reg32;
1da177e4 1263 void __iomem *sense_interrupt_mask_reg;
214777ba 1264 void __iomem *sense_interrupt_mask_reg32;
1da177e4 1265 void __iomem *clr_interrupt_reg;
214777ba 1266 void __iomem *clr_interrupt_reg32;
1da177e4
LT		 1267
1268 void __iomem *sense_interrupt_reg;
214777ba 1269 void __iomem *sense_interrupt_reg32;
1da177e4
LT		 1270 void __iomem *ioarrin_reg;
1271 void __iomem *sense_uproc_interrupt_reg;
214777ba 1272 void __iomem *sense_uproc_interrupt_reg32;
1da177e4 1273 void __iomem *set_uproc_interrupt_reg;
214777ba 1274 void __iomem *set_uproc_interrupt_reg32;
1da177e4 1275 void __iomem *clr_uproc_interrupt_reg;
214777ba
WB		 1276 void __iomem *clr_uproc_interrupt_reg32;
1277
1278 void __iomem *init_feedback_reg;
dcbad00e
WB		 1279
1280 void __iomem *dump_addr_reg;
1281 void __iomem *dump_data_reg;
1da177e4
LT		 1282};
1283
1284struct ipr_chip_cfg_t {
1285 u32 mailbox;
1286 u8 cache_line_size;
1287 struct ipr_interrupt_offsets regs;
1288};
1289
1290struct ipr_chip_t {
1291 u16 vendor;
1292 u16 device;
1be7bd82
WB		 1293 u16 intr_type;
1294#define IPR_USE_LSI 0x00
1295#define IPR_USE_MSI 0x01
a32c055f
WB		 1296 u16 sis_type;
1297#define IPR_SIS32 0x00
1298#define IPR_SIS64 0x01
1da177e4
LT		 1299 const struct ipr_chip_cfg_t *cfg;
1300};
1301
1302enum ipr_shutdown_type {
1303 IPR_SHUTDOWN_NORMAL = 0x00,
1304 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1305 IPR_SHUTDOWN_ABBREV = 0x80,
1306 IPR_SHUTDOWN_NONE = 0x100
1307};
1308
1309struct ipr_trace_entry {
1310 u32 time;
1311
1312 u8 op_code;
35a39691 1313 u8 ata_op_code;
1da177e4
LT		 1314 u8 type;
1315#define IPR_TRACE_START 0x00
1316#define IPR_TRACE_FINISH 0xff
35a39691 1317 u8 cmd_index;
1da177e4
LT		 1318
1319 __be32 res_handle;
1320 union {
1321 u32 ioasc;
1322 u32 add_data;
1323 u32 res_addr;
1324 } u;
1325};
1326
1327struct ipr_sglist {
1328 u32 order;
1329 u32 num_sg;
12baa420 1330 u32 num_dma_sg;
1da177e4
LT		 1331 u32 buffer_len;
1332 struct scatterlist scatterlist[1];
1333};
1334
1335enum ipr_sdt_state {
1336 INACTIVE,
1337 WAIT_FOR_DUMP,
1338 GET_DUMP,
1339 ABORT_DUMP,
1340 DUMP_OBTAINED
1341};
1342
1343/* Per-controller data */
1344struct ipr_ioa_cfg {
1345 char eye_catcher[8];
1346#define IPR_EYECATCHER "iprcfg"
1347
1348 struct list_head queue;
1349
1350 u8 allow_interrupts:1;
1351 u8 in_reset_reload:1;
1352 u8 in_ioa_bringdown:1;
1353 u8 ioa_unit_checked:1;
1354 u8 ioa_is_dead:1;
1355 u8 dump_taken:1;
1356 u8 allow_cmds:1;
1357 u8 allow_ml_add_del:1;
ce155cce 1358 u8 needs_hard_reset:1;
ac09c349 1359 u8 dual_raid:1;
463fc696 1360 u8 needs_warm_reset:1;
95fecd90 1361 u8 msi_received:1;
a32c055f 1362 u8 sis64:1;
463fc696
BK		 1363
1364 u8 revid;
1da177e4 1365
3e7ebdfa
WB		 1366 /*
1367 * Bitmaps for SIS64 generated target values
1368 */
1369 unsigned long *target_ids;
1370 unsigned long *array_ids;
1371 unsigned long *vset_ids;
1372
1da177e4
LT		 1373 u16 type; /* CCIN of the card */
1374
1375 u8 log_level;
1376#define IPR_MAX_LOG_LEVEL 4
1377#define IPR_DEFAULT_LOG_LEVEL 2
1378
1379#define IPR_NUM_TRACE_INDEX_BITS 8
1380#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1381#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1382 char trace_start[8];
1383#define IPR_TRACE_START_LABEL "trace"
1384 struct ipr_trace_entry *trace;
1385 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1386
1387 /*
1388 * Queue for free command blocks
1389 */
1390 char ipr_free_label[8];
1391#define IPR_FREEQ_LABEL "free-q"
1392 struct list_head free_q;
1393
1394 /*
1395 * Queue for command blocks outstanding to the adapter
1396 */
1397 char ipr_pending_label[8];
1398#define IPR_PENDQ_LABEL "pend-q"
1399 struct list_head pending_q;
1400
1401 char cfg_table_start[8];
1402#define IPR_CFG_TBL_START "cfg"
3e7ebdfa
WB		 1403 union {
1404 struct ipr_config_table *cfg_table;
1405 struct ipr_config_table64 *cfg_table64;
1406 } u;
1da177e4 1407 dma_addr_t cfg_table_dma;
3e7ebdfa
WB		 1408 u32 cfg_table_size;
1409 u32 max_devs_supported;
1da177e4
LT		 1410
1411 char resource_table_label[8];
1412#define IPR_RES_TABLE_LABEL "res_tbl"
1413 struct ipr_resource_entry *res_entries;
1414 struct list_head free_res_q;
1415 struct list_head used_res_q;
1416
1417 char ipr_hcam_label[8];
1418#define IPR_HCAM_LABEL "hcams"
1419 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1420 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1421 struct list_head hostrcb_free_q;
1422 struct list_head hostrcb_pending_q;
1423
1424 __be32 *host_rrq;
1425 dma_addr_t host_rrq_dma;
1426#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1427#define IPR_HRRQ_RESP_BIT_SET 0x00000002
1428#define IPR_HRRQ_TOGGLE_BIT 0x00000001
1429#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1430 volatile __be32 *hrrq_start;
1431 volatile __be32 *hrrq_end;
1432 volatile __be32 *hrrq_curr;
1433 volatile u32 toggle_bit;
1434
1435 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1436
5469cb5b 1437 unsigned int transop_timeout;
1da177e4 1438 const struct ipr_chip_cfg_t *chip_cfg;
1be7bd82 1439 const struct ipr_chip_t *ipr_chip;
1da177e4
LT		 1440
1441 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1442 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1443 void __iomem *ioa_mailbox;
1444 struct ipr_interrupts regs;
1445
1446 u16 saved_pcix_cmd_reg;
1447 u16 reset_retries;
1448
1449 u32 errors_logged;
3d1d0da6 1450 u32 doorbell;
1da177e4
LT		 1451
1452 struct Scsi_Host *host;
1453 struct pci_dev *pdev;
1454 struct ipr_sglist *ucode_sglist;
1da177e4
LT		 1455 u8 saved_mode_page_len;
1456
1457 struct work_struct work_q;
1458
1459 wait_queue_head_t reset_wait_q;
95fecd90 1460 wait_queue_head_t msi_wait_q;
1da177e4
LT		 1461
1462 struct ipr_dump *dump;
1463 enum ipr_sdt_state sdt_state;
1464
1465 struct ipr_misc_cbs *vpd_cbs;
1466 dma_addr_t vpd_cbs_dma;
1467
1468 struct pci_pool *ipr_cmd_pool;
1469
1470 struct ipr_cmnd *reset_cmd;
463fc696 1471 int (*reset) (struct ipr_cmnd *);
1da177e4 1472
35a39691 1473 struct ata_host ata_host;
1da177e4 1474 char ipr_cmd_label[8];
0124ca9d 1475#define IPR_CMD_LABEL "ipr_cmd"
1da177e4 1476 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
a32c055f 1477 dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
3e7ebdfa 1478}; /* struct ipr_ioa_cfg */
1da177e4
LT		 1479
1480struct ipr_cmnd {
1481 struct ipr_ioarcb ioarcb;
a32c055f
WB		 1482 union {
1483 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1484 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1485 struct ipr_ata64_ioadl ata_ioadl;
1486 } i;
96d21f00
WB		 1487 union {
1488 struct ipr_ioasa ioasa;
1489 struct ipr_ioasa64 ioasa64;
1490 } s;
1da177e4
LT		 1491 struct list_head queue;
1492 struct scsi_cmnd *scsi_cmd;
35a39691 1493 struct ata_queued_cmd *qc;
1da177e4
LT		 1494 struct completion completion;
1495 struct timer_list timer;
1496 void (*done) (struct ipr_cmnd *);
1497 int (*job_step) (struct ipr_cmnd *);
dfed823e 1498 int (*job_step_failed) (struct ipr_cmnd *);
1da177e4
LT		 1499 u16 cmd_index;
1500 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1501 dma_addr_t sense_buffer_dma;
1502 unsigned short dma_use_sg;
a32c055f 1503 dma_addr_t dma_addr;
1da177e4
LT		 1504 struct ipr_cmnd *sibling;
1505 union {
1506 enum ipr_shutdown_type shutdown_type;
1507 struct ipr_hostrcb *hostrcb;
1508 unsigned long time_left;
1509 unsigned long scratch;
1510 struct ipr_resource_entry *res;
1511 struct scsi_device *sdev;
1512 } u;
1513
1514 struct ipr_ioa_cfg *ioa_cfg;
1515};
1516
1517struct ipr_ses_table_entry {
1518 char product_id[17];
1519 char compare_product_id_byte[17];
1520 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1521};
1522
1523struct ipr_dump_header {
1524 u32 eye_catcher;
1525#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1526 u32 len;
1527 u32 num_entries;
1528 u32 first_entry_offset;
1529 u32 status;
1530#define IPR_DUMP_STATUS_SUCCESS 0
1531#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1532#define IPR_DUMP_STATUS_FAILED 0xffffffff
1533 u32 os;
1534#define IPR_DUMP_OS_LINUX 0x4C4E5558
1535 u32 driver_name;
1536#define IPR_DUMP_DRIVER_NAME 0x49505232
1537}__attribute__((packed, aligned (4)));
1538
1539struct ipr_dump_entry_header {
1540 u32 eye_catcher;
1541#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1542 u32 len;
1543 u32 num_elems;
1544 u32 offset;
1545 u32 data_type;
1546#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1547#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1548 u32 id;
1549#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1550#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1551#define IPR_DUMP_TRACE_ID 0x54524143
1552#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1553#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1554#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1555#define IPR_DUMP_PEND_OPS 0x414F5053
1556 u32 status;
1557}__attribute__((packed, aligned (4)));
1558
1559struct ipr_dump_location_entry {
1560 struct ipr_dump_entry_header hdr;
71610f55 1561 u8 location[20];
1da177e4
LT		 1562}__attribute__((packed));
1563
1564struct ipr_dump_trace_entry {
1565 struct ipr_dump_entry_header hdr;
1566 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1567}__attribute__((packed, aligned (4)));
1568
1569struct ipr_dump_version_entry {
1570 struct ipr_dump_entry_header hdr;
1571 u8 version[sizeof(IPR_DRIVER_VERSION)];
1572};
1573
1574struct ipr_dump_ioa_type_entry {
1575 struct ipr_dump_entry_header hdr;
1576 u32 type;
1577 u32 fw_version;
1578};
1579
1580struct ipr_driver_dump {
1581 struct ipr_dump_header hdr;
1582 struct ipr_dump_version_entry version_entry;
1583 struct ipr_dump_location_entry location_entry;
1584 struct ipr_dump_ioa_type_entry ioa_type_entry;
1585 struct ipr_dump_trace_entry trace_entry;
1586}__attribute__((packed));
1587
1588struct ipr_ioa_dump {
1589 struct ipr_dump_entry_header hdr;
1590 struct ipr_sdt sdt;
1591 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1592 u32 reserved;
1593 u32 next_page_index;
1594 u32 page_offset;
1595 u32 format;
1da177e4
LT		 1596}__attribute__((packed, aligned (4)));
1597
1598struct ipr_dump {
1599 struct kref kref;
1600 struct ipr_ioa_cfg *ioa_cfg;
1601 struct ipr_driver_dump driver_dump;
1602 struct ipr_ioa_dump ioa_dump;
1603};
1604
1605struct ipr_error_table_t {
1606 u32 ioasc;
1607 int log_ioasa;
1608 int log_hcam;
1609 char *error;
1610};
1611
1612struct ipr_software_inq_lid_info {
1613 __be32 load_id;
1614 __be32 timestamp[3];
1615}__attribute__((packed, aligned (4)));
1616
1617struct ipr_ucode_image_header {
1618 __be32 header_length;
1619 __be32 lid_table_offset;
1620 u8 major_release;
1621 u8 card_type;
1622 u8 minor_release[2];
1623 u8 reserved[20];
1624 char eyecatcher[16];
1625 __be32 num_lids;
1626 struct ipr_software_inq_lid_info lid[1];
1627}__attribute__((packed, aligned (4)));
1628
1629/*
1630 * Macros
1631 */
d3c74871 1632#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1da177e4
LT		 1633
1634#ifdef CONFIG_SCSI_IPR_TRACE
1635#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1636#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1637#else
1638#define ipr_create_trace_file(kobj, attr) 0
1639#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1640#endif
1641
1642#ifdef CONFIG_SCSI_IPR_DUMP
1643#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1644#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1645#else
1646#define ipr_create_dump_file(kobj, attr) 0
1647#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1648#endif
1649
1650/*
1651 * Error logging macros
1652 */
1653#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1654#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1da177e4
LT		 1655#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1656
3e7ebdfa
WB		 1657#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1658 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1659 bus, target, lun, ##__VA_ARGS__)
1660
1661#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1662 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1663
fb3ed3cb
BK		 1664#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1665 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1666 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1da177e4 1667
fb3ed3cb
BK		 1668#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1669 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1da177e4 1670
fa15b1f6
BK		 1671#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1672{ \
1673 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1674 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1675 } else { \
1676 ipr_err(fmt": %d:%d:%d:%d\n", \
1677 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1678 (res).bus, (res).target, (res).lun); \
1679 } \
1680}
1681
49dc6a18 1682#define ipr_hcam_err(hostrcb, fmt, ...) \
4565e370
WB		 1683{ \
1684 if (ipr_is_device(hostrcb)) { \
1685 if ((hostrcb)->ioa_cfg->sis64) { \
1686 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
5adcbeb3
WB		 1687 ipr_format_res_path(hostrcb->hcam.u.error64.fd_res_path, \
1688 hostrcb->rp_buffer, \
1689 sizeof(hostrcb->rp_buffer)), \
4565e370
WB		 1690 __VA_ARGS__); \
1691 } else { \
1692 ipr_ra_err((hostrcb)->ioa_cfg, \
1693 (hostrcb)->hcam.u.error.fd_res_addr, \
1694 fmt, __VA_ARGS__); \
1695 } \
1696 } else { \
1697 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1698 } \
49dc6a18
BK		 1699}
1700
1da177e4 1701#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
cadbd4a5 1702 __FILE__, __func__, __LINE__)
1da177e4 1703
cadbd4a5
HH		 1704#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1705#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1da177e4
LT		 1706
1707#define ipr_err_separator \
1708ipr_err("----------------------------------------------------------\n")
1709
1710
1711/*
1712 * Inlines
1713 */
1714
1715/**
1716 * ipr_is_ioa_resource - Determine if a resource is the IOA
1717 * @res: resource entry struct
1718 *
1719 * Return value:
1720 * 1 if IOA / 0 if not IOA
1721 **/
1722static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1723{
3e7ebdfa 1724 return res->type == IPR_RES_TYPE_IOAFP;
1da177e4
LT		 1725}
1726
1727/**
1728 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1729 * @res: resource entry struct
1730 *
1731 * Return value:
1732 * 1 if AF DASD / 0 if not AF DASD
1733 **/
1734static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1735{
3e7ebdfa
WB		 1736 return res->type == IPR_RES_TYPE_AF_DASD ||
1737 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1da177e4
LT		 1738}
1739
1740/**
1741 * ipr_is_vset_device - Determine if a resource is a VSET
1742 * @res: resource entry struct
1743 *
1744 * Return value:
1745 * 1 if VSET / 0 if not VSET
1746 **/
1747static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1748{
3e7ebdfa 1749 return res->type == IPR_RES_TYPE_VOLUME_SET;
1da177e4
LT		 1750}
1751
1752/**
1753 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1754 * @res: resource entry struct
1755 *
1756 * Return value:
1757 * 1 if GSCSI / 0 if not GSCSI
1758 **/
1759static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1760{
3e7ebdfa 1761 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1da177e4
LT		 1762}
1763
e4fbf44e
BK		 1764/**
1765 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1766 * @res: resource entry struct
1767 *
1768 * Return value:
1769 * 1 if SCSI disk / 0 if not SCSI disk
1770 **/
1771static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1772{
1773 if (ipr_is_af_dasd_device(res) ||
3e7ebdfa 1774 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
e4fbf44e
BK		 1775 return 1;
1776 else
1777 return 0;
1778}
1779
b5145d25
BK		 1780/**
1781 * ipr_is_gata - Determine if a resource is a generic ATA resource
1782 * @res: resource entry struct
1783 *
1784 * Return value:
1785 * 1 if GATA / 0 if not GATA
1786 **/
1787static inline int ipr_is_gata(struct ipr_resource_entry *res)
1788{
3e7ebdfa 1789 return res->type == IPR_RES_TYPE_GENERIC_ATA;
b5145d25
BK		 1790}
1791
ee0a90fa
BK		 1792/**
1793 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1794 * @res: resource entry struct
1795 *
1796 * Return value:
1797 * 1 if NACA queueing model / 0 if not NACA queueing model
1798 **/
1799static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1800{
3e7ebdfa 1801 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
ee0a90fa
BK		 1802 return 1;
1803 return 0;
1804}
1805
1da177e4 1806/**
4565e370
WB		 1807 * ipr_is_device - Determine if the hostrcb structure is related to a device
1808 * @hostrcb: host resource control blocks struct
1da177e4
LT		 1809 *
1810 * Return value:
1811 * 1 if AF / 0 if not AF
1812 **/
4565e370 1813static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1da177e4 1814{
4565e370
WB		 1815 struct ipr_res_addr *res_addr;
1816 u8 *res_path;
1817
1818 if (hostrcb->ioa_cfg->sis64) {
1819 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1820 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1821 res_path[0] == 0x81) && res_path[2] != 0xFF)
1822 return 1;
1823 } else {
1824 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1825
1826 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1827 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1828 return 1;
1829 }
1da177e4
LT		 1830 return 0;
1831}
1832
1833/**
1834 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1835 * @sdt_word: SDT address
1836 *
1837 * Return value:
1838 * 1 if format 2 / 0 if not
1839 **/
1840static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1841{
1842 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1843
1844 switch (bar_sel) {
1845 case IPR_SDT_FMT2_BAR0_SEL:
1846 case IPR_SDT_FMT2_BAR1_SEL:
1847 case IPR_SDT_FMT2_BAR2_SEL:
1848 case IPR_SDT_FMT2_BAR3_SEL:
1849 case IPR_SDT_FMT2_BAR4_SEL:
1850 case IPR_SDT_FMT2_BAR5_SEL:
1851 case IPR_SDT_FMT2_EXP_ROM_SEL:
1852 return 1;
1853 };
1854
1855 return 0;
1856}
1857
1858#endif
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