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Merge branch 'i2c-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelvar...
[net-next-2.6.git] / drivers / scsi / ipr.h
CommitLineData
1da177e4
LT		 1/*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
fa195afe 22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
1da177e4
LT		 23 * that broke 64bit platforms.
24 */
25
26#ifndef _IPR_H
27#define _IPR_H
28
46d74563 29#include <asm/unaligned.h>
1da177e4
LT		 30#include <linux/types.h>
31#include <linux/completion.h>
35a39691 32#include <linux/libata.h>
1da177e4
LT		 33#include <linux/list.h>
34#include <linux/kref.h>
35#include <scsi/scsi.h>
36#include <scsi/scsi_cmnd.h>
37
38/*
39 * Literals
40 */
a87b04de
WB		 41#define IPR_DRIVER_VERSION "2.5.1"
42#define IPR_DRIVER_DATE "(August 10, 2010)"
1da177e4 43
1da177e4
LT		 44/*
45 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
46 * ops per device for devices not running tagged command queuing.
47 * This can be adjusted at runtime through sysfs device attributes.
48 */
49#define IPR_MAX_CMD_PER_LUN 6
b5145d25 50#define IPR_MAX_CMD_PER_ATA_LUN 1
1da177e4
LT		 51
52/*
53 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
54 * ops the mid-layer can send to the adapter.
55 */
56#define IPR_NUM_BASE_CMD_BLKS 100
57
60e7486b 58#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
d7b4627f
WB		 59
60#define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
61#define PCI_DEVICE_ID_IBM_CROC_ASIC_E2 0x034A
60e7486b 62
1da177e4
LT		 63#define IPR_SUBS_DEV_ID_2780 0x0264
64#define IPR_SUBS_DEV_ID_5702 0x0266
65#define IPR_SUBS_DEV_ID_5703 0x0278
b0f56d3d
WB		 66#define IPR_SUBS_DEV_ID_572E 0x028D
67#define IPR_SUBS_DEV_ID_573E 0x02D3
68#define IPR_SUBS_DEV_ID_573D 0x02D4
1da177e4
LT		 69#define IPR_SUBS_DEV_ID_571A 0x02C0
70#define IPR_SUBS_DEV_ID_571B 0x02BE
b0f56d3d 71#define IPR_SUBS_DEV_ID_571E 0x02BF
86f51436
BK		 72#define IPR_SUBS_DEV_ID_571F 0x02D5
73#define IPR_SUBS_DEV_ID_572A 0x02C1
74#define IPR_SUBS_DEV_ID_572B 0x02C2
60e7486b 75#define IPR_SUBS_DEV_ID_572F 0x02C3
185eb31c 76#define IPR_SUBS_DEV_ID_574E 0x030A
86f51436 77#define IPR_SUBS_DEV_ID_575B 0x030D
60e7486b 78#define IPR_SUBS_DEV_ID_575C 0x0338
185eb31c 79#define IPR_SUBS_DEV_ID_57B3 0x033A
60e7486b
BK		 80#define IPR_SUBS_DEV_ID_57B7 0x0360
81#define IPR_SUBS_DEV_ID_57B8 0x02C2
1da177e4 82
d7b4627f
WB		 83#define IPR_SUBS_DEV_ID_57B4 0x033B
84#define IPR_SUBS_DEV_ID_57B2 0x035F
32622bde 85#define IPR_SUBS_DEV_ID_57C4 0x0354
d7b4627f 86#define IPR_SUBS_DEV_ID_57C6 0x0357
b0f56d3d 87#define IPR_SUBS_DEV_ID_57CC 0x035C
d7b4627f
WB		 88
89#define IPR_SUBS_DEV_ID_57B5 0x033C
90#define IPR_SUBS_DEV_ID_57CE 0x035E
91#define IPR_SUBS_DEV_ID_57B1 0x0355
92
93#define IPR_SUBS_DEV_ID_574D 0x0356
94#define IPR_SUBS_DEV_ID_575D 0x035D
95
1da177e4
LT		 96#define IPR_NAME "ipr"
97
98/*
99 * Return codes
100 */
101#define IPR_RC_JOB_CONTINUE 1
102#define IPR_RC_JOB_RETURN 2
103
104/*
105 * IOASCs
106 */
107#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
65f56475 108#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
1da177e4
LT		 109#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
110#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
111#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
112#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
113#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
114#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
dfed823e 115#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
1da177e4 116#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
b0df54bb
BK		 117#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
118#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
1da177e4
LT		 119#define IPR_IOASC_BUS_WAS_RESET 0x06290000
120#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
121#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
122
123#define IPR_FIRST_DRIVER_IOASC 0x10000000
124#define IPR_IOASC_IOA_WAS_RESET 0x10000001
125#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
126
5469cb5b
BK		 127/* Driver data flags */
128#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
463fc696 129#define IPR_USE_PCI_WARM_RESET 0x00000002
5469cb5b 130
ac719aba 131#define IPR_DEFAULT_MAX_ERROR_DUMP 984
1da177e4
LT		 132#define IPR_NUM_LOG_HCAMS 2
133#define IPR_NUM_CFG_CHG_HCAMS 2
134#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
3e7ebdfa
WB		 135
136#define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
137#define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
138
d71a8b0c 139#define IPR_MAX_NUM_TARGETS_PER_BUS 256
1da177e4
LT		 140#define IPR_MAX_NUM_LUNS_PER_TARGET 256
141#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
142#define IPR_VSET_BUS 0xff
143#define IPR_IOA_BUS 0xff
144#define IPR_IOA_TARGET 0xff
145#define IPR_IOA_LUN 0xff
b5145d25 146#define IPR_MAX_NUM_BUSES 16
1da177e4
LT		 147#define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
148
149#define IPR_NUM_RESET_RELOAD_RETRIES 3
150
151/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
152#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
f72919ec 153 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
1da177e4
LT		 154
155#define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
156#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
157 IPR_NUM_INTERNAL_CMD_BLKS)
158
159#define IPR_MAX_PHYSICAL_DEVS 192
3e7ebdfa
WB		 160#define IPR_DEFAULT_SIS64_DEVS 1024
161#define IPR_MAX_SIS64_DEVS 4096
1da177e4
LT		 162
163#define IPR_MAX_SGLIST 64
164#define IPR_IOA_MAX_SECTORS 32767
165#define IPR_VSET_MAX_SECTORS 512
166#define IPR_MAX_CDB_LEN 16
3feeb89d 167#define IPR_MAX_HRRQ_RETRIES 3
1da177e4
LT		 168
169#define IPR_DEFAULT_BUS_WIDTH 16
170#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
171#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
172#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
173#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
174
175#define IPR_IOA_RES_HANDLE 0xffffffff
1121b794 176#define IPR_INVALID_RES_HANDLE 0
1da177e4
LT		 177#define IPR_IOA_RES_ADDR 0x00ffffff
178
179/*
180 * Adapter Commands
181 */
182#define IPR_QUERY_RSRC_STATE 0xC2
183#define IPR_RESET_DEVICE 0xC3
184#define IPR_RESET_TYPE_SELECT 0x80
185#define IPR_LUN_RESET 0x40
186#define IPR_TARGET_RESET 0x20
187#define IPR_BUS_RESET 0x10
b5145d25 188#define IPR_ATA_PHY_RESET 0x80
1da177e4
LT		 189#define IPR_ID_HOST_RR_Q 0xC4
190#define IPR_QUERY_IOA_CONFIG 0xC5
191#define IPR_CANCEL_ALL_REQUESTS 0xCE
192#define IPR_HOST_CONTROLLED_ASYNC 0xCF
193#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
194#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
195#define IPR_SET_SUPPORTED_DEVICES 0xFB
3e7ebdfa 196#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
1da177e4
LT		 197#define IPR_IOA_SHUTDOWN 0xF7
198#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
199
200/*
201 * Timeouts
202 */
203#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
204#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
205#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
ac09c349 206#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
1da177e4
LT		 207#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
208#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
209#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
210#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
211#define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
212#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
213#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
214#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
5469cb5b 215#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
1da177e4
LT		 216#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
217#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
218#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
463fc696 219#define IPR_PCI_RESET_TIMEOUT (HZ / 2)
1da177e4
LT		 220#define IPR_DUMP_TIMEOUT (15 * HZ)
221
222/*
223 * SCSI Literals
224 */
225#define IPR_VENDOR_ID_LEN 8
226#define IPR_PROD_ID_LEN 16
227#define IPR_SERIAL_NUM_LEN 8
228
229/*
230 * Hardware literals
231 */
232#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
233#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
234#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
235#define IPR_GET_FMT2_BAR_SEL(mbx) \
236(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
237#define IPR_SDT_FMT2_BAR0_SEL 0x0
238#define IPR_SDT_FMT2_BAR1_SEL 0x1
239#define IPR_SDT_FMT2_BAR2_SEL 0x2
240#define IPR_SDT_FMT2_BAR3_SEL 0x3
241#define IPR_SDT_FMT2_BAR4_SEL 0x4
242#define IPR_SDT_FMT2_BAR5_SEL 0x5
243#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
244#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
dcbad00e 245#define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
1da177e4 246#define IPR_DOORBELL 0x82800000
3d1d0da6 247#define IPR_RUNTIME_RESET 0x40000000
1da177e4 248
214777ba 249#define IPR_IPL_INIT_MIN_STAGE_TIME 5
438b0331 250#define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
214777ba
WB		 251#define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
252#define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
253#define IPR_IPL_INIT_STAGE_MASK 0xff000000
254#define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
255#define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
256
1da177e4
LT		 257#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
258#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
259#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
260#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
261#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
262#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
263#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
264#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
265#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
266#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
267#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
268
269#define IPR_PCII_ERROR_INTERRUPTS \
270(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
271IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
272
273#define IPR_PCII_OPER_INTERRUPTS \
274(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
275
276#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
277#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
cb237ef7 278#define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
1da177e4
LT		 279
280#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
281#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
282
283/*
284 * Dump literals
285 */
286#define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
287#define IPR_NUM_SDT_ENTRIES 511
288#define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
289
290/*
291 * Misc literals
292 */
293#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
294
295/*
296 * Adapter interface types
297 */
298
299struct ipr_res_addr {
300 u8 reserved;
301 u8 bus;
302 u8 target;
303 u8 lun;
304#define IPR_GET_PHYS_LOC(res_addr) \
305 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
306}__attribute__((packed, aligned (4)));
307
308struct ipr_std_inq_vpids {
309 u8 vendor_id[IPR_VENDOR_ID_LEN];
310 u8 product_id[IPR_PROD_ID_LEN];
311}__attribute__((packed));
312
cfc32139
BK		 313struct ipr_vpd {
314 struct ipr_std_inq_vpids vpids;
315 u8 sn[IPR_SERIAL_NUM_LEN];
316}__attribute__((packed));
317
ee0f05b8
BK		 318struct ipr_ext_vpd {
319 struct ipr_vpd vpd;
320 __be32 wwid[2];
321}__attribute__((packed));
322
7262026f
WB		 323struct ipr_ext_vpd64 {
324 struct ipr_vpd vpd;
325 __be32 wwid[4];
326}__attribute__((packed));
327
1da177e4
LT		 328struct ipr_std_inq_data {
329 u8 peri_qual_dev_type;
330#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
331#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
332
333 u8 removeable_medium_rsvd;
334#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
335
336#define IPR_IS_DASD_DEVICE(std_inq) \
337((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
338!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
339
340#define IPR_IS_SES_DEVICE(std_inq) \
341(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
342
343 u8 version;
344 u8 aen_naca_fmt;
345 u8 additional_len;
346 u8 sccs_rsvd;
347 u8 bq_enc_multi;
348 u8 sync_cmdq_flags;
349
350 struct ipr_std_inq_vpids vpids;
351
352 u8 ros_rsvd_ram_rsvd[4];
353
354 u8 serial_num[IPR_SERIAL_NUM_LEN];
355}__attribute__ ((packed));
356
3e7ebdfa
WB		 357#define IPR_RES_TYPE_AF_DASD 0x00
358#define IPR_RES_TYPE_GENERIC_SCSI 0x01
359#define IPR_RES_TYPE_VOLUME_SET 0x02
360#define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
361#define IPR_RES_TYPE_GENERIC_ATA 0x04
362#define IPR_RES_TYPE_ARRAY 0x05
363#define IPR_RES_TYPE_IOAFP 0xff
364
1da177e4 365struct ipr_config_table_entry {
b5145d25
BK		 366 u8 proto;
367#define IPR_PROTO_SATA 0x02
368#define IPR_PROTO_SATA_ATAPI 0x03
369#define IPR_PROTO_SAS_STP 0x06
3e7ebdfa 370#define IPR_PROTO_SAS_STP_ATAPI 0x07
1da177e4
LT		 371 u8 array_id;
372 u8 flags;
3e7ebdfa 373#define IPR_IS_IOA_RESOURCE 0x80
1da177e4 374 u8 rsvd_subtype;
3e7ebdfa
WB		 375
376#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
377#define IPR_QUEUE_FROZEN_MODEL 0
ee0a90fa
BK		 378#define IPR_QUEUE_NACA_MODEL 1
379
1da177e4
LT		 380 struct ipr_res_addr res_addr;
381 __be32 res_handle;
46d74563 382 __be32 lun_wwn[2];
1da177e4
LT		 383 struct ipr_std_inq_data std_inq_data;
384}__attribute__ ((packed, aligned (4)));
385
3e7ebdfa
WB		 386struct ipr_config_table_entry64 {
387 u8 res_type;
388 u8 proto;
389 u8 vset_num;
390 u8 array_id;
391 __be16 flags;
392 __be16 res_flags;
393#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
394 __be32 res_handle;
395 u8 dev_id_type;
396 u8 reserved[3];
397 __be64 dev_id;
398 __be64 lun;
399 __be64 lun_wwn[2];
400#define IPR_MAX_RES_PATH_LENGTH 24
401 __be64 res_path;
402 struct ipr_std_inq_data std_inq_data;
403 u8 reserved2[4];
7262026f 404 __be64 reserved3[2];
3e7ebdfa
WB		 405 u8 reserved4[8];
406}__attribute__ ((packed, aligned (8)));
407
1da177e4
LT		 408struct ipr_config_table_hdr {
409 u8 num_entries;
410 u8 flags;
411#define IPR_UCODE_DOWNLOAD_REQ 0x10
412 __be16 reserved;
413}__attribute__((packed, aligned (4)));
414
3e7ebdfa
WB		 415struct ipr_config_table_hdr64 {
416 __be16 num_entries;
417 __be16 reserved;
418 u8 flags;
419 u8 reserved2[11];
420}__attribute__((packed, aligned (4)));
421
1da177e4
LT		 422struct ipr_config_table {
423 struct ipr_config_table_hdr hdr;
3e7ebdfa 424 struct ipr_config_table_entry dev[0];
1da177e4
LT		 425}__attribute__((packed, aligned (4)));
426
3e7ebdfa
WB		 427struct ipr_config_table64 {
428 struct ipr_config_table_hdr64 hdr64;
429 struct ipr_config_table_entry64 dev[0];
430}__attribute__((packed, aligned (8)));
431
432struct ipr_config_table_entry_wrapper {
433 union {
434 struct ipr_config_table_entry *cfgte;
435 struct ipr_config_table_entry64 *cfgte64;
436 } u;
437};
438
1da177e4 439struct ipr_hostrcb_cfg_ch_not {
3e7ebdfa
WB		 440 union {
441 struct ipr_config_table_entry cfgte;
442 struct ipr_config_table_entry64 cfgte64;
443 } u;
1da177e4
LT		 444 u8 reserved[936];
445}__attribute__((packed, aligned (4)));
446
447struct ipr_supported_device {
448 __be16 data_length;
449 u8 reserved;
450 u8 num_records;
451 struct ipr_std_inq_vpids vpids;
452 u8 reserved2[16];
453}__attribute__((packed, aligned (4)));
454
455/* Command packet structure */
456struct ipr_cmd_pkt {
457 __be16 reserved; /* Reserved by IOA */
458 u8 request_type;
459#define IPR_RQTYPE_SCSICDB 0x00
460#define IPR_RQTYPE_IOACMD 0x01
461#define IPR_RQTYPE_HCAM 0x02
b5145d25 462#define IPR_RQTYPE_ATA_PASSTHRU 0x04
1da177e4 463
a32c055f 464 u8 reserved2;
1da177e4
LT		 465
466 u8 flags_hi;
467#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
468#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
469#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
470#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
471#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
472
473 u8 flags_lo;
474#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
475#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
476#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
477#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
478#define IPR_FLAGS_LO_ORDERED_TASK 0x04
479#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
480#define IPR_FLAGS_LO_ACA_TASK 0x08
481
482 u8 cdb[16];
483 __be16 timeout;
484}__attribute__ ((packed, aligned(4)));
485
a32c055f 486struct ipr_ioarcb_ata_regs { /* 22 bytes */
b5145d25
BK		 487 u8 flags;
488#define IPR_ATA_FLAG_PACKET_CMD 0x80
489#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
490#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
491 u8 reserved[3];
492
493 __be16 data;
494 u8 feature;
495 u8 nsect;
496 u8 lbal;
497 u8 lbam;
498 u8 lbah;
499 u8 device;
500 u8 command;
501 u8 reserved2[3];
502 u8 hob_feature;
503 u8 hob_nsect;
504 u8 hob_lbal;
505 u8 hob_lbam;
506 u8 hob_lbah;
507 u8 ctl;
508}__attribute__ ((packed, aligned(4)));
509
51b1c7e1
BK		 510struct ipr_ioadl_desc {
511 __be32 flags_and_data_len;
512#define IPR_IOADL_FLAGS_MASK 0xff000000
513#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
514#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
515#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
516#define IPR_IOADL_FLAGS_READ 0x48000000
517#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
518#define IPR_IOADL_FLAGS_WRITE 0x68000000
519#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
520#define IPR_IOADL_FLAGS_LAST 0x01000000
521
522 __be32 address;
523}__attribute__((packed, aligned (8)));
524
a32c055f
WB		 525struct ipr_ioadl64_desc {
526 __be32 flags;
527 __be32 data_len;
528 __be64 address;
529}__attribute__((packed, aligned (16)));
530
531struct ipr_ata64_ioadl {
532 struct ipr_ioarcb_ata_regs regs;
533 u16 reserved[5];
534 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
535}__attribute__((packed, aligned (16)));
536
b5145d25
BK		 537struct ipr_ioarcb_add_data {
538 union {
539 struct ipr_ioarcb_ata_regs regs;
51b1c7e1 540 struct ipr_ioadl_desc ioadl[5];
b5145d25 541 __be32 add_cmd_parms[10];
a32c055f
WB		 542 } u;
543}__attribute__ ((packed, aligned (4)));
544
545struct ipr_ioarcb_sis64_add_addr_ecb {
546 __be64 ioasa_host_pci_addr;
547 __be64 data_ioadl_addr;
548 __be64 reserved;
549 __be32 ext_control_buf[4];
550}__attribute__((packed, aligned (8)));
b5145d25 551
1da177e4
LT		 552/* IOA Request Control Block 128 bytes */
553struct ipr_ioarcb {
a32c055f
WB		 554 union {
555 __be32 ioarcb_host_pci_addr;
556 __be64 ioarcb_host_pci_addr64;
557 } a;
1da177e4
LT		 558 __be32 res_handle;
559 __be32 host_response_handle;
560 __be32 reserved1;
561 __be32 reserved2;
562 __be32 reserved3;
563
a32c055f 564 __be32 data_transfer_length;
1da177e4
LT		 565 __be32 read_data_transfer_length;
566 __be32 write_ioadl_addr;
a32c055f 567 __be32 ioadl_len;
1da177e4
LT		 568 __be32 read_ioadl_addr;
569 __be32 read_ioadl_len;
570
571 __be32 ioasa_host_pci_addr;
572 __be16 ioasa_len;
573 __be16 reserved4;
574
575 struct ipr_cmd_pkt cmd_pkt;
576
a32c055f
WB		 577 __be16 add_cmd_parms_offset;
578 __be16 add_cmd_parms_len;
579
580 union {
581 struct ipr_ioarcb_add_data add_data;
582 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
583 } u;
584
1da177e4
LT		 585}__attribute__((packed, aligned (4)));
586
1da177e4
LT		 587struct ipr_ioasa_vset {
588 __be32 failing_lba_hi;
589 __be32 failing_lba_lo;
c8f74892 590 __be32 reserved;
1da177e4
LT		 591}__attribute__((packed, aligned (4)));
592
593struct ipr_ioasa_af_dasd {
594 __be32 failing_lba;
c8f74892 595 __be32 reserved[2];
1da177e4
LT		 596}__attribute__((packed, aligned (4)));
597
598struct ipr_ioasa_gpdd {
599 u8 end_state;
600 u8 bus_phase;
601 __be16 reserved;
c8f74892 602 __be32 ioa_data[2];
1da177e4
LT		 603}__attribute__((packed, aligned (4)));
604
b5145d25
BK		 605struct ipr_ioasa_gata {
606 u8 error;
607 u8 nsect; /* Interrupt reason */
608 u8 lbal;
609 u8 lbam;
610 u8 lbah;
611 u8 device;
612 u8 status;
613 u8 alt_status; /* ATA CTL */
614 u8 hob_nsect;
615 u8 hob_lbal;
616 u8 hob_lbam;
617 u8 hob_lbah;
618}__attribute__((packed, aligned (4)));
619
c8f74892
BK		 620struct ipr_auto_sense {
621 __be16 auto_sense_len;
622 __be16 ioa_data_len;
623 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
624};
1da177e4 625
96d21f00 626struct ipr_ioasa_hdr {
1da177e4
LT		 627 __be32 ioasc;
628#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
629#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
630#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
631#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
632
633 __be16 ret_stat_len; /* Length of the returned IOASA */
634
635 __be16 avail_stat_len; /* Total Length of status available. */
636
637 __be32 residual_data_len; /* number of bytes in the host data */
638 /* buffers that were not used by the IOARCB command. */
639
640 __be32 ilid;
641#define IPR_NO_ILID 0
642#define IPR_DRIVER_ILID 0xffffffff
643
644 __be32 fd_ioasc;
645
646 __be32 fd_phys_locator;
647
648 __be32 fd_res_handle;
649
650 __be32 ioasc_specific; /* status code specific field */
c8f74892
BK		 651#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
652#define IPR_AUTOSENSE_VALID 0x40000000
b5145d25 653#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
1da177e4
LT		 654#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
655#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
656#define IPR_FIELD_POINTER_MASK 0x0000ffff
657
96d21f00
WB		 658}__attribute__((packed, aligned (4)));
659
660struct ipr_ioasa {
661 struct ipr_ioasa_hdr hdr;
662
663 union {
664 struct ipr_ioasa_vset vset;
665 struct ipr_ioasa_af_dasd dasd;
666 struct ipr_ioasa_gpdd gpdd;
667 struct ipr_ioasa_gata gata;
668 } u;
669
670 struct ipr_auto_sense auto_sense;
671}__attribute__((packed, aligned (4)));
672
673struct ipr_ioasa64 {
674 struct ipr_ioasa_hdr hdr;
675 u8 fd_res_path[8];
676
1da177e4
LT		 677 union {
678 struct ipr_ioasa_vset vset;
679 struct ipr_ioasa_af_dasd dasd;
680 struct ipr_ioasa_gpdd gpdd;
b5145d25 681 struct ipr_ioasa_gata gata;
1da177e4 682 } u;
c8f74892
BK		 683
684 struct ipr_auto_sense auto_sense;
1da177e4
LT		 685}__attribute__((packed, aligned (4)));
686
687struct ipr_mode_parm_hdr {
688 u8 length;
689 u8 medium_type;
690 u8 device_spec_parms;
691 u8 block_desc_len;
692}__attribute__((packed));
693
694struct ipr_mode_pages {
695 struct ipr_mode_parm_hdr hdr;
696 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
697}__attribute__((packed));
698
699struct ipr_mode_page_hdr {
700 u8 ps_page_code;
701#define IPR_MODE_PAGE_PS 0x80
702#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
703 u8 page_length;
704}__attribute__ ((packed));
705
706struct ipr_dev_bus_entry {
707 struct ipr_res_addr res_addr;
708 u8 flags;
709#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
710#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
711#define IPR_SCSI_ATTR_QAS_MASK 0xC0
712#define IPR_SCSI_ATTR_ENABLE_TM 0x20
713#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
714#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
715#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
716
717 u8 scsi_id;
718 u8 bus_width;
719 u8 extended_reset_delay;
720#define IPR_EXTENDED_RESET_DELAY 7
721
722 __be32 max_xfer_rate;
723
724 u8 spinup_delay;
725 u8 reserved3;
726 __be16 reserved4;
727}__attribute__((packed, aligned (4)));
728
729struct ipr_mode_page28 {
730 struct ipr_mode_page_hdr hdr;
731 u8 num_entries;
732 u8 entry_length;
733 struct ipr_dev_bus_entry bus[0];
734}__attribute__((packed));
735
ac09c349
BK		 736struct ipr_mode_page24 {
737 struct ipr_mode_page_hdr hdr;
738 u8 flags;
739#define IPR_ENABLE_DUAL_IOA_AF 0x80
740}__attribute__((packed));
741
1da177e4
LT		 742struct ipr_ioa_vpd {
743 struct ipr_std_inq_data std_inq_data;
744 u8 ascii_part_num[12];
745 u8 reserved[40];
746 u8 ascii_plant_code[4];
747}__attribute__((packed));
748
749struct ipr_inquiry_page3 {
750 u8 peri_qual_dev_type;
751 u8 page_code;
752 u8 reserved1;
753 u8 page_length;
754 u8 ascii_len;
755 u8 reserved2[3];
756 u8 load_id[4];
757 u8 major_release;
758 u8 card_type;
759 u8 minor_release[2];
760 u8 ptf_number[4];
761 u8 patch_number[4];
762}__attribute__((packed));
763
ac09c349
BK		 764struct ipr_inquiry_cap {
765 u8 peri_qual_dev_type;
766 u8 page_code;
767 u8 reserved1;
768 u8 page_length;
769 u8 ascii_len;
770 u8 reserved2;
771 u8 sis_version[2];
772 u8 cap;
773#define IPR_CAP_DUAL_IOA_RAID 0x80
774 u8 reserved3[15];
775}__attribute__((packed));
776
62275040
BK		 777#define IPR_INQUIRY_PAGE0_ENTRIES 20
778struct ipr_inquiry_page0 {
779 u8 peri_qual_dev_type;
780 u8 page_code;
781 u8 reserved1;
782 u8 len;
783 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
784}__attribute__((packed));
785
1da177e4 786struct ipr_hostrcb_device_data_entry {
cfc32139 787 struct ipr_vpd vpd;
1da177e4 788 struct ipr_res_addr dev_res_addr;
cfc32139
BK		 789 struct ipr_vpd new_vpd;
790 struct ipr_vpd ioa_last_with_dev_vpd;
791 struct ipr_vpd cfc_last_with_dev_vpd;
1da177e4
LT		 792 __be32 ioa_data[5];
793}__attribute__((packed, aligned (4)));
794
ee0f05b8
BK		 795struct ipr_hostrcb_device_data_entry_enhanced {
796 struct ipr_ext_vpd vpd;
797 u8 ccin[4];
798 struct ipr_res_addr dev_res_addr;
799 struct ipr_ext_vpd new_vpd;
800 u8 new_ccin[4];
801 struct ipr_ext_vpd ioa_last_with_dev_vpd;
802 struct ipr_ext_vpd cfc_last_with_dev_vpd;
803}__attribute__((packed, aligned (4)));
804
4565e370
WB		 805struct ipr_hostrcb64_device_data_entry_enhanced {
806 struct ipr_ext_vpd vpd;
807 u8 ccin[4];
808 u8 res_path[8];
809 struct ipr_ext_vpd new_vpd;
810 u8 new_ccin[4];
811 struct ipr_ext_vpd ioa_last_with_dev_vpd;
812 struct ipr_ext_vpd cfc_last_with_dev_vpd;
813}__attribute__((packed, aligned (4)));
814
1da177e4 815struct ipr_hostrcb_array_data_entry {
cfc32139 816 struct ipr_vpd vpd;
1da177e4
LT		 817 struct ipr_res_addr expected_dev_res_addr;
818 struct ipr_res_addr dev_res_addr;
819}__attribute__((packed, aligned (4)));
820
4565e370
WB		 821struct ipr_hostrcb64_array_data_entry {
822 struct ipr_ext_vpd vpd;
823 u8 ccin[4];
824 u8 expected_res_path[8];
825 u8 res_path[8];
826}__attribute__((packed, aligned (4)));
827
ee0f05b8
BK		 828struct ipr_hostrcb_array_data_entry_enhanced {
829 struct ipr_ext_vpd vpd;
830 u8 ccin[4];
831 struct ipr_res_addr expected_dev_res_addr;
832 struct ipr_res_addr dev_res_addr;
833}__attribute__((packed, aligned (4)));
834
1da177e4 835struct ipr_hostrcb_type_ff_error {
438b0331 836 __be32 ioa_data[758];
1da177e4
LT		 837}__attribute__((packed, aligned (4)));
838
839struct ipr_hostrcb_type_01_error {
840 __be32 seek_counter;
841 __be32 read_counter;
842 u8 sense_data[32];
843 __be32 ioa_data[236];
844}__attribute__((packed, aligned (4)));
845
846struct ipr_hostrcb_type_02_error {
cfc32139
BK		 847 struct ipr_vpd ioa_vpd;
848 struct ipr_vpd cfc_vpd;
849 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
850 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
1da177e4 851 __be32 ioa_data[3];
1da177e4
LT		 852}__attribute__((packed, aligned (4)));
853
ee0f05b8
BK		 854struct ipr_hostrcb_type_12_error {
855 struct ipr_ext_vpd ioa_vpd;
856 struct ipr_ext_vpd cfc_vpd;
857 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
858 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
859 __be32 ioa_data[3];
860}__attribute__((packed, aligned (4)));
861
1da177e4 862struct ipr_hostrcb_type_03_error {
cfc32139
BK		 863 struct ipr_vpd ioa_vpd;
864 struct ipr_vpd cfc_vpd;
1da177e4
LT		 865 __be32 errors_detected;
866 __be32 errors_logged;
867 u8 ioa_data[12];
cfc32139 868 struct ipr_hostrcb_device_data_entry dev[3];
1da177e4
LT		 869}__attribute__((packed, aligned (4)));
870
ee0f05b8
BK		 871struct ipr_hostrcb_type_13_error {
872 struct ipr_ext_vpd ioa_vpd;
873 struct ipr_ext_vpd cfc_vpd;
874 __be32 errors_detected;
875 __be32 errors_logged;
876 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
877}__attribute__((packed, aligned (4)));
878
4565e370
WB		 879struct ipr_hostrcb_type_23_error {
880 struct ipr_ext_vpd ioa_vpd;
881 struct ipr_ext_vpd cfc_vpd;
882 __be32 errors_detected;
883 __be32 errors_logged;
884 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
885}__attribute__((packed, aligned (4)));
886
1da177e4 887struct ipr_hostrcb_type_04_error {
cfc32139
BK		 888 struct ipr_vpd ioa_vpd;
889 struct ipr_vpd cfc_vpd;
1da177e4
LT		 890 u8 ioa_data[12];
891 struct ipr_hostrcb_array_data_entry array_member[10];
892 __be32 exposed_mode_adn;
893 __be32 array_id;
cfc32139 894 struct ipr_vpd incomp_dev_vpd;
1da177e4
LT		 895 __be32 ioa_data2;
896 struct ipr_hostrcb_array_data_entry array_member2[8];
897 struct ipr_res_addr last_func_vset_res_addr;
898 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
899 u8 protection_level[8];
1da177e4
LT		 900}__attribute__((packed, aligned (4)));
901
ee0f05b8
BK		 902struct ipr_hostrcb_type_14_error {
903 struct ipr_ext_vpd ioa_vpd;
904 struct ipr_ext_vpd cfc_vpd;
905 __be32 exposed_mode_adn;
906 __be32 array_id;
907 struct ipr_res_addr last_func_vset_res_addr;
908 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
909 u8 protection_level[8];
910 __be32 num_entries;
911 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
912}__attribute__((packed, aligned (4)));
913
4565e370
WB		 914struct ipr_hostrcb_type_24_error {
915 struct ipr_ext_vpd ioa_vpd;
916 struct ipr_ext_vpd cfc_vpd;
917 u8 reserved[2];
918 u8 exposed_mode_adn;
919#define IPR_INVALID_ARRAY_DEV_NUM 0xff
920 u8 array_id;
921 u8 last_res_path[8];
922 u8 protection_level[8];
7262026f 923 struct ipr_ext_vpd64 array_vpd;
4565e370
WB		 924 u8 description[16];
925 u8 reserved2[3];
926 u8 num_entries;
927 struct ipr_hostrcb64_array_data_entry array_member[32];
928}__attribute__((packed, aligned (4)));
929
b0df54bb
BK		 930struct ipr_hostrcb_type_07_error {
931 u8 failure_reason[64];
932 struct ipr_vpd vpd;
933 u32 data[222];
934}__attribute__((packed, aligned (4)));
935
ee0f05b8
BK		 936struct ipr_hostrcb_type_17_error {
937 u8 failure_reason[64];
938 struct ipr_ext_vpd vpd;
939 u32 data[476];
940}__attribute__((packed, aligned (4)));
941
49dc6a18
BK		 942struct ipr_hostrcb_config_element {
943 u8 type_status;
944#define IPR_PATH_CFG_TYPE_MASK 0xF0
945#define IPR_PATH_CFG_NOT_EXIST 0x00
946#define IPR_PATH_CFG_IOA_PORT 0x10
947#define IPR_PATH_CFG_EXP_PORT 0x20
948#define IPR_PATH_CFG_DEVICE_PORT 0x30
949#define IPR_PATH_CFG_DEVICE_LUN 0x40
950
951#define IPR_PATH_CFG_STATUS_MASK 0x0F
952#define IPR_PATH_CFG_NO_PROB 0x00
953#define IPR_PATH_CFG_DEGRADED 0x01
954#define IPR_PATH_CFG_FAILED 0x02
955#define IPR_PATH_CFG_SUSPECT 0x03
956#define IPR_PATH_NOT_DETECTED 0x04
957#define IPR_PATH_INCORRECT_CONN 0x05
958
959 u8 cascaded_expander;
960 u8 phy;
961 u8 link_rate;
962#define IPR_PHY_LINK_RATE_MASK 0x0F
963
964 __be32 wwid[2];
965}__attribute__((packed, aligned (4)));
966
4565e370
WB		 967struct ipr_hostrcb64_config_element {
968 __be16 length;
969 u8 descriptor_id;
970#define IPR_DESCRIPTOR_MASK 0xC0
971#define IPR_DESCRIPTOR_SIS64 0x00
972
973 u8 reserved;
974 u8 type_status;
975
976 u8 reserved2[2];
977 u8 link_rate;
978
979 u8 res_path[8];
980 __be32 wwid[2];
981}__attribute__((packed, aligned (8)));
982
49dc6a18
BK		 983struct ipr_hostrcb_fabric_desc {
984 __be16 length;
985 u8 ioa_port;
986 u8 cascaded_expander;
987 u8 phy;
988 u8 path_state;
989#define IPR_PATH_ACTIVE_MASK 0xC0
990#define IPR_PATH_NO_INFO 0x00
991#define IPR_PATH_ACTIVE 0x40
992#define IPR_PATH_NOT_ACTIVE 0x80
993
994#define IPR_PATH_STATE_MASK 0x0F
995#define IPR_PATH_STATE_NO_INFO 0x00
996#define IPR_PATH_HEALTHY 0x01
997#define IPR_PATH_DEGRADED 0x02
998#define IPR_PATH_FAILED 0x03
999
1000 __be16 num_entries;
1001 struct ipr_hostrcb_config_element elem[1];
1002}__attribute__((packed, aligned (4)));
1003
4565e370
WB		 1004struct ipr_hostrcb64_fabric_desc {
1005 __be16 length;
1006 u8 descriptor_id;
1007
8701f185 1008 u8 reserved[2];
4565e370
WB		 1009 u8 path_state;
1010
1011 u8 reserved2[2];
1012 u8 res_path[8];
1013 u8 reserved3[6];
1014 __be16 num_entries;
1015 struct ipr_hostrcb64_config_element elem[1];
1016}__attribute__((packed, aligned (8)));
1017
49dc6a18
BK		 1018#define for_each_fabric_cfg(fabric, cfg) \
1019 for (cfg = (fabric)->elem; \
1020 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1021 cfg++)
1022
1023struct ipr_hostrcb_type_20_error {
1024 u8 failure_reason[64];
1025 u8 reserved[3];
1026 u8 num_entries;
1027 struct ipr_hostrcb_fabric_desc desc[1];
1028}__attribute__((packed, aligned (4)));
1029
4565e370
WB		 1030struct ipr_hostrcb_type_30_error {
1031 u8 failure_reason[64];
1032 u8 reserved[3];
1033 u8 num_entries;
1034 struct ipr_hostrcb64_fabric_desc desc[1];
1035}__attribute__((packed, aligned (4)));
1036
1da177e4 1037struct ipr_hostrcb_error {
4565e370
WB		 1038 __be32 fd_ioasc;
1039 struct ipr_res_addr fd_res_addr;
1040 __be32 fd_res_handle;
1da177e4
LT		 1041 __be32 prc;
1042 union {
1043 struct ipr_hostrcb_type_ff_error type_ff_error;
1044 struct ipr_hostrcb_type_01_error type_01_error;
1045 struct ipr_hostrcb_type_02_error type_02_error;
1046 struct ipr_hostrcb_type_03_error type_03_error;
1047 struct ipr_hostrcb_type_04_error type_04_error;
b0df54bb 1048 struct ipr_hostrcb_type_07_error type_07_error;
ee0f05b8
BK		 1049 struct ipr_hostrcb_type_12_error type_12_error;
1050 struct ipr_hostrcb_type_13_error type_13_error;
1051 struct ipr_hostrcb_type_14_error type_14_error;
1052 struct ipr_hostrcb_type_17_error type_17_error;
49dc6a18 1053 struct ipr_hostrcb_type_20_error type_20_error;
1da177e4
LT		 1054 } u;
1055}__attribute__((packed, aligned (4)));
1056
4565e370
WB		 1057struct ipr_hostrcb64_error {
1058 __be32 fd_ioasc;
1059 __be32 ioa_fw_level;
1060 __be32 fd_res_handle;
1061 __be32 prc;
1062 __be64 fd_dev_id;
1063 __be64 fd_lun;
1064 u8 fd_res_path[8];
1065 __be64 time_stamp;
8701f185 1066 u8 reserved[16];
4565e370
WB		 1067 union {
1068 struct ipr_hostrcb_type_ff_error type_ff_error;
1069 struct ipr_hostrcb_type_12_error type_12_error;
1070 struct ipr_hostrcb_type_17_error type_17_error;
1071 struct ipr_hostrcb_type_23_error type_23_error;
1072 struct ipr_hostrcb_type_24_error type_24_error;
1073 struct ipr_hostrcb_type_30_error type_30_error;
1074 } u;
1075}__attribute__((packed, aligned (8)));
1076
1da177e4
LT		 1077struct ipr_hostrcb_raw {
1078 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1079}__attribute__((packed, aligned (4)));
1080
1081struct ipr_hcam {
1082 u8 op_code;
1083#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1084#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1085
1086 u8 notify_type;
1087#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1088#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1089#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1090#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1091#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1092
1093 u8 notifications_lost;
1094#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1095#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1096
1097 u8 flags;
1098#define IPR_HOSTRCB_INTERNAL_OPER 0x80
1099#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1100
1101 u8 overlay_id;
1102#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1103#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1104#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1105#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1106#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
b0df54bb 1107#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
ee0f05b8
BK		 1108#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1109#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1110#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1111#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1112#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
49dc6a18 1113#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
4565e370
WB		 1114#define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1115#define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1116#define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1117#define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1118#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1da177e4
LT		 1119
1120 u8 reserved1[3];
1121 __be32 ilid;
1122 __be32 time_since_last_ioa_reset;
1123 __be32 reserved2;
1124 __be32 length;
1125
1126 union {
1127 struct ipr_hostrcb_error error;
4565e370 1128 struct ipr_hostrcb64_error error64;
1da177e4
LT		 1129 struct ipr_hostrcb_cfg_ch_not ccn;
1130 struct ipr_hostrcb_raw raw;
1131 } u;
1132}__attribute__((packed, aligned (4)));
1133
1134struct ipr_hostrcb {
1135 struct ipr_hcam hcam;
1136 dma_addr_t hostrcb_dma;
1137 struct list_head queue;
49dc6a18 1138 struct ipr_ioa_cfg *ioa_cfg;
4565e370 1139 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1da177e4
LT		 1140};
1141
1142/* IPR smart dump table structures */
1143struct ipr_sdt_entry {
dcbad00e
WB		 1144 __be32 start_token;
1145 __be32 end_token;
1146 u8 reserved[4];
1da177e4
LT		 1147
1148 u8 flags;
1149#define IPR_SDT_ENDIAN 0x80
1150#define IPR_SDT_VALID_ENTRY 0x20
1151
1152 u8 resv;
1153 __be16 priority;
1154}__attribute__((packed, aligned (4)));
1155
1156struct ipr_sdt_header {
1157 __be32 state;
1158 __be32 num_entries;
1159 __be32 num_entries_used;
1160 __be32 dump_size;
1161}__attribute__((packed, aligned (4)));
1162
1163struct ipr_sdt {
1164 struct ipr_sdt_header hdr;
1165 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
1166}__attribute__((packed, aligned (4)));
1167
1168struct ipr_uc_sdt {
1169 struct ipr_sdt_header hdr;
1170 struct ipr_sdt_entry entry[1];
1171}__attribute__((packed, aligned (4)));
1172
1173/*
1174 * Driver types
1175 */
1176struct ipr_bus_attributes {
1177 u8 bus;
1178 u8 qas_enabled;
1179 u8 bus_width;
1180 u8 reserved;
1181 u32 max_xfer_rate;
1182};
1183
35a39691
BK		 1184struct ipr_sata_port {
1185 struct ipr_ioa_cfg *ioa_cfg;
1186 struct ata_port *ap;
1187 struct ipr_resource_entry *res;
1188 struct ipr_ioasa_gata ioasa;
1189};
1190
1da177e4 1191struct ipr_resource_entry {
1da177e4
LT		 1192 u8 needs_sync_complete:1;
1193 u8 in_erp:1;
1194 u8 add_to_ml:1;
1195 u8 del_from_ml:1;
1196 u8 resetting_device:1;
1197
3e7ebdfa
WB		 1198 u32 bus; /* AKA channel */
1199 u32 target; /* AKA id */
1200 u32 lun;
1201#define IPR_ARRAY_VIRTUAL_BUS 0x1
1202#define IPR_VSET_VIRTUAL_BUS 0x2
1203#define IPR_IOAFP_VIRTUAL_BUS 0x3
1204
1205#define IPR_GET_RES_PHYS_LOC(res) \
1206 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1207
1208 u8 ata_class;
1209
1210 u8 flags;
1211 __be16 res_flags;
1212
7be96900 1213 u8 type;
3e7ebdfa
WB		 1214
1215 u8 qmodel;
1216 struct ipr_std_inq_data std_inq_data;
1217
1218 __be32 res_handle;
1219 __be64 dev_id;
46d74563 1220 __be64 lun_wwn;
3e7ebdfa
WB		 1221 struct scsi_lun dev_lun;
1222 u8 res_path[8];
1223
1224 struct ipr_ioa_cfg *ioa_cfg;
1da177e4 1225 struct scsi_device *sdev;
35a39691 1226 struct ipr_sata_port *sata_port;
1da177e4 1227 struct list_head queue;
3e7ebdfa 1228}; /* struct ipr_resource_entry */
1da177e4
LT		 1229
1230struct ipr_resource_hdr {
1231 u16 num_entries;
1232 u16 reserved;
1233};
1234
1da177e4
LT		 1235struct ipr_misc_cbs {
1236 struct ipr_ioa_vpd ioa_vpd;
62275040 1237 struct ipr_inquiry_page0 page0_data;
1da177e4 1238 struct ipr_inquiry_page3 page3_data;
ac09c349 1239 struct ipr_inquiry_cap cap;
1da177e4
LT		 1240 struct ipr_mode_pages mode_pages;
1241 struct ipr_supported_device supp_dev;
1242};
1243
1244struct ipr_interrupt_offsets {
1245 unsigned long set_interrupt_mask_reg;
1246 unsigned long clr_interrupt_mask_reg;
214777ba 1247 unsigned long clr_interrupt_mask_reg32;
1da177e4 1248 unsigned long sense_interrupt_mask_reg;
214777ba 1249 unsigned long sense_interrupt_mask_reg32;
1da177e4 1250 unsigned long clr_interrupt_reg;
214777ba 1251 unsigned long clr_interrupt_reg32;
1da177e4
LT		 1252
1253 unsigned long sense_interrupt_reg;
214777ba 1254 unsigned long sense_interrupt_reg32;
1da177e4
LT		 1255 unsigned long ioarrin_reg;
1256 unsigned long sense_uproc_interrupt_reg;
214777ba 1257 unsigned long sense_uproc_interrupt_reg32;
1da177e4 1258 unsigned long set_uproc_interrupt_reg;
214777ba 1259 unsigned long set_uproc_interrupt_reg32;
1da177e4 1260 unsigned long clr_uproc_interrupt_reg;
214777ba
WB		 1261 unsigned long clr_uproc_interrupt_reg32;
1262
1263 unsigned long init_feedback_reg;
dcbad00e
WB		 1264
1265 unsigned long dump_addr_reg;
1266 unsigned long dump_data_reg;
8701f185 1267
4289a086 1268#define IPR_ENDIAN_SWAP_KEY 0x00080800
8701f185 1269 unsigned long endian_swap_reg;
1da177e4
LT		 1270};
1271
1272struct ipr_interrupts {
1273 void __iomem *set_interrupt_mask_reg;
1274 void __iomem *clr_interrupt_mask_reg;
214777ba 1275 void __iomem *clr_interrupt_mask_reg32;
1da177e4 1276 void __iomem *sense_interrupt_mask_reg;
214777ba 1277 void __iomem *sense_interrupt_mask_reg32;
1da177e4 1278 void __iomem *clr_interrupt_reg;
214777ba 1279 void __iomem *clr_interrupt_reg32;
1da177e4
LT		 1280
1281 void __iomem *sense_interrupt_reg;
214777ba 1282 void __iomem *sense_interrupt_reg32;
1da177e4
LT		 1283 void __iomem *ioarrin_reg;
1284 void __iomem *sense_uproc_interrupt_reg;
214777ba 1285 void __iomem *sense_uproc_interrupt_reg32;
1da177e4 1286 void __iomem *set_uproc_interrupt_reg;
214777ba 1287 void __iomem *set_uproc_interrupt_reg32;
1da177e4 1288 void __iomem *clr_uproc_interrupt_reg;
214777ba
WB		 1289 void __iomem *clr_uproc_interrupt_reg32;
1290
1291 void __iomem *init_feedback_reg;
dcbad00e
WB		 1292
1293 void __iomem *dump_addr_reg;
1294 void __iomem *dump_data_reg;
8701f185
WB		 1295
1296 void __iomem *endian_swap_reg;
1da177e4
LT		 1297};
1298
1299struct ipr_chip_cfg_t {
1300 u32 mailbox;
1301 u8 cache_line_size;
1302 struct ipr_interrupt_offsets regs;
1303};
1304
1305struct ipr_chip_t {
1306 u16 vendor;
1307 u16 device;
1be7bd82
WB		 1308 u16 intr_type;
1309#define IPR_USE_LSI 0x00
1310#define IPR_USE_MSI 0x01
a32c055f
WB		 1311 u16 sis_type;
1312#define IPR_SIS32 0x00
1313#define IPR_SIS64 0x01
cb237ef7
WB		 1314 u16 bist_method;
1315#define IPR_PCI_CFG 0x00
1316#define IPR_MMIO 0x01
1da177e4
LT		 1317 const struct ipr_chip_cfg_t *cfg;
1318};
1319
1320enum ipr_shutdown_type {
1321 IPR_SHUTDOWN_NORMAL = 0x00,
1322 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1323 IPR_SHUTDOWN_ABBREV = 0x80,
1324 IPR_SHUTDOWN_NONE = 0x100
1325};
1326
1327struct ipr_trace_entry {
1328 u32 time;
1329
1330 u8 op_code;
35a39691 1331 u8 ata_op_code;
1da177e4
LT		 1332 u8 type;
1333#define IPR_TRACE_START 0x00
1334#define IPR_TRACE_FINISH 0xff
35a39691 1335 u8 cmd_index;
1da177e4
LT		 1336
1337 __be32 res_handle;
1338 union {
1339 u32 ioasc;
1340 u32 add_data;
1341 u32 res_addr;
1342 } u;
1343};
1344
1345struct ipr_sglist {
1346 u32 order;
1347 u32 num_sg;
12baa420 1348 u32 num_dma_sg;
1da177e4
LT		 1349 u32 buffer_len;
1350 struct scatterlist scatterlist[1];
1351};
1352
1353enum ipr_sdt_state {
1354 INACTIVE,
1355 WAIT_FOR_DUMP,
1356 GET_DUMP,
1357 ABORT_DUMP,
1358 DUMP_OBTAINED
1359};
1360
1361/* Per-controller data */
1362struct ipr_ioa_cfg {
1363 char eye_catcher[8];
1364#define IPR_EYECATCHER "iprcfg"
1365
1366 struct list_head queue;
1367
1368 u8 allow_interrupts:1;
1369 u8 in_reset_reload:1;
1370 u8 in_ioa_bringdown:1;
1371 u8 ioa_unit_checked:1;
1372 u8 ioa_is_dead:1;
1373 u8 dump_taken:1;
1374 u8 allow_cmds:1;
1375 u8 allow_ml_add_del:1;
ce155cce 1376 u8 needs_hard_reset:1;
ac09c349 1377 u8 dual_raid:1;
463fc696 1378 u8 needs_warm_reset:1;
95fecd90 1379 u8 msi_received:1;
a32c055f 1380 u8 sis64:1;
463fc696
BK		 1381
1382 u8 revid;
1da177e4 1383
3e7ebdfa
WB		 1384 /*
1385 * Bitmaps for SIS64 generated target values
1386 */
1387 unsigned long *target_ids;
1388 unsigned long *array_ids;
1389 unsigned long *vset_ids;
1390
1da177e4
LT		 1391 u16 type; /* CCIN of the card */
1392
1393 u8 log_level;
1394#define IPR_MAX_LOG_LEVEL 4
1395#define IPR_DEFAULT_LOG_LEVEL 2
1396
1397#define IPR_NUM_TRACE_INDEX_BITS 8
1398#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1399#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1400 char trace_start[8];
1401#define IPR_TRACE_START_LABEL "trace"
1402 struct ipr_trace_entry *trace;
1403 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1404
1405 /*
1406 * Queue for free command blocks
1407 */
1408 char ipr_free_label[8];
1409#define IPR_FREEQ_LABEL "free-q"
1410 struct list_head free_q;
1411
1412 /*
1413 * Queue for command blocks outstanding to the adapter
1414 */
1415 char ipr_pending_label[8];
1416#define IPR_PENDQ_LABEL "pend-q"
1417 struct list_head pending_q;
1418
1419 char cfg_table_start[8];
1420#define IPR_CFG_TBL_START "cfg"
3e7ebdfa
WB		 1421 union {
1422 struct ipr_config_table *cfg_table;
1423 struct ipr_config_table64 *cfg_table64;
1424 } u;
1da177e4 1425 dma_addr_t cfg_table_dma;
3e7ebdfa
WB		 1426 u32 cfg_table_size;
1427 u32 max_devs_supported;
1da177e4
LT		 1428
1429 char resource_table_label[8];
1430#define IPR_RES_TABLE_LABEL "res_tbl"
1431 struct ipr_resource_entry *res_entries;
1432 struct list_head free_res_q;
1433 struct list_head used_res_q;
1434
1435 char ipr_hcam_label[8];
1436#define IPR_HCAM_LABEL "hcams"
1437 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1438 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1439 struct list_head hostrcb_free_q;
1440 struct list_head hostrcb_pending_q;
1441
1442 __be32 *host_rrq;
1443 dma_addr_t host_rrq_dma;
1444#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1445#define IPR_HRRQ_RESP_BIT_SET 0x00000002
1446#define IPR_HRRQ_TOGGLE_BIT 0x00000001
1447#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1448 volatile __be32 *hrrq_start;
1449 volatile __be32 *hrrq_end;
1450 volatile __be32 *hrrq_curr;
1451 volatile u32 toggle_bit;
1452
1453 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1454
5469cb5b 1455 unsigned int transop_timeout;
1da177e4 1456 const struct ipr_chip_cfg_t *chip_cfg;
1be7bd82 1457 const struct ipr_chip_t *ipr_chip;
1da177e4
LT		 1458
1459 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1460 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1461 void __iomem *ioa_mailbox;
1462 struct ipr_interrupts regs;
1463
1464 u16 saved_pcix_cmd_reg;
1465 u16 reset_retries;
1466
1467 u32 errors_logged;
3d1d0da6 1468 u32 doorbell;
1da177e4
LT		 1469
1470 struct Scsi_Host *host;
1471 struct pci_dev *pdev;
1472 struct ipr_sglist *ucode_sglist;
1da177e4
LT		 1473 u8 saved_mode_page_len;
1474
1475 struct work_struct work_q;
1476
1477 wait_queue_head_t reset_wait_q;
95fecd90 1478 wait_queue_head_t msi_wait_q;
1da177e4
LT		 1479
1480 struct ipr_dump *dump;
1481 enum ipr_sdt_state sdt_state;
1482
1483 struct ipr_misc_cbs *vpd_cbs;
1484 dma_addr_t vpd_cbs_dma;
1485
1486 struct pci_pool *ipr_cmd_pool;
1487
1488 struct ipr_cmnd *reset_cmd;
463fc696 1489 int (*reset) (struct ipr_cmnd *);
1da177e4 1490
35a39691 1491 struct ata_host ata_host;
1da177e4 1492 char ipr_cmd_label[8];
0124ca9d 1493#define IPR_CMD_LABEL "ipr_cmd"
1da177e4 1494 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
a32c055f 1495 dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
3e7ebdfa 1496}; /* struct ipr_ioa_cfg */
1da177e4
LT		 1497
1498struct ipr_cmnd {
1499 struct ipr_ioarcb ioarcb;
a32c055f
WB		 1500 union {
1501 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1502 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1503 struct ipr_ata64_ioadl ata_ioadl;
1504 } i;
96d21f00
WB		 1505 union {
1506 struct ipr_ioasa ioasa;
1507 struct ipr_ioasa64 ioasa64;
1508 } s;
1da177e4
LT		 1509 struct list_head queue;
1510 struct scsi_cmnd *scsi_cmd;
35a39691 1511 struct ata_queued_cmd *qc;
1da177e4
LT		 1512 struct completion completion;
1513 struct timer_list timer;
1514 void (*done) (struct ipr_cmnd *);
1515 int (*job_step) (struct ipr_cmnd *);
dfed823e 1516 int (*job_step_failed) (struct ipr_cmnd *);
1da177e4
LT		 1517 u16 cmd_index;
1518 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1519 dma_addr_t sense_buffer_dma;
1520 unsigned short dma_use_sg;
a32c055f 1521 dma_addr_t dma_addr;
1da177e4
LT		 1522 struct ipr_cmnd *sibling;
1523 union {
1524 enum ipr_shutdown_type shutdown_type;
1525 struct ipr_hostrcb *hostrcb;
1526 unsigned long time_left;
1527 unsigned long scratch;
1528 struct ipr_resource_entry *res;
1529 struct scsi_device *sdev;
1530 } u;
1531
1532 struct ipr_ioa_cfg *ioa_cfg;
1533};
1534
1535struct ipr_ses_table_entry {
1536 char product_id[17];
1537 char compare_product_id_byte[17];
1538 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1539};
1540
1541struct ipr_dump_header {
1542 u32 eye_catcher;
1543#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1544 u32 len;
1545 u32 num_entries;
1546 u32 first_entry_offset;
1547 u32 status;
1548#define IPR_DUMP_STATUS_SUCCESS 0
1549#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1550#define IPR_DUMP_STATUS_FAILED 0xffffffff
1551 u32 os;
1552#define IPR_DUMP_OS_LINUX 0x4C4E5558
1553 u32 driver_name;
1554#define IPR_DUMP_DRIVER_NAME 0x49505232
1555}__attribute__((packed, aligned (4)));
1556
1557struct ipr_dump_entry_header {
1558 u32 eye_catcher;
1559#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1560 u32 len;
1561 u32 num_elems;
1562 u32 offset;
1563 u32 data_type;
1564#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1565#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1566 u32 id;
1567#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1568#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1569#define IPR_DUMP_TRACE_ID 0x54524143
1570#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1571#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1572#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1573#define IPR_DUMP_PEND_OPS 0x414F5053
1574 u32 status;
1575}__attribute__((packed, aligned (4)));
1576
1577struct ipr_dump_location_entry {
1578 struct ipr_dump_entry_header hdr;
71610f55 1579 u8 location[20];
1da177e4
LT		 1580}__attribute__((packed));
1581
1582struct ipr_dump_trace_entry {
1583 struct ipr_dump_entry_header hdr;
1584 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1585}__attribute__((packed, aligned (4)));
1586
1587struct ipr_dump_version_entry {
1588 struct ipr_dump_entry_header hdr;
1589 u8 version[sizeof(IPR_DRIVER_VERSION)];
1590};
1591
1592struct ipr_dump_ioa_type_entry {
1593 struct ipr_dump_entry_header hdr;
1594 u32 type;
1595 u32 fw_version;
1596};
1597
1598struct ipr_driver_dump {
1599 struct ipr_dump_header hdr;
1600 struct ipr_dump_version_entry version_entry;
1601 struct ipr_dump_location_entry location_entry;
1602 struct ipr_dump_ioa_type_entry ioa_type_entry;
1603 struct ipr_dump_trace_entry trace_entry;
1604}__attribute__((packed));
1605
1606struct ipr_ioa_dump {
1607 struct ipr_dump_entry_header hdr;
1608 struct ipr_sdt sdt;
1609 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1610 u32 reserved;
1611 u32 next_page_index;
1612 u32 page_offset;
1613 u32 format;
1da177e4
LT		 1614}__attribute__((packed, aligned (4)));
1615
1616struct ipr_dump {
1617 struct kref kref;
1618 struct ipr_ioa_cfg *ioa_cfg;
1619 struct ipr_driver_dump driver_dump;
1620 struct ipr_ioa_dump ioa_dump;
1621};
1622
1623struct ipr_error_table_t {
1624 u32 ioasc;
1625 int log_ioasa;
1626 int log_hcam;
1627 char *error;
1628};
1629
1630struct ipr_software_inq_lid_info {
1631 __be32 load_id;
1632 __be32 timestamp[3];
1633}__attribute__((packed, aligned (4)));
1634
1635struct ipr_ucode_image_header {
1636 __be32 header_length;
1637 __be32 lid_table_offset;
1638 u8 major_release;
1639 u8 card_type;
1640 u8 minor_release[2];
1641 u8 reserved[20];
1642 char eyecatcher[16];
1643 __be32 num_lids;
1644 struct ipr_software_inq_lid_info lid[1];
1645}__attribute__((packed, aligned (4)));
1646
1647/*
1648 * Macros
1649 */
d3c74871 1650#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1da177e4
LT		 1651
1652#ifdef CONFIG_SCSI_IPR_TRACE
1653#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1654#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1655#else
1656#define ipr_create_trace_file(kobj, attr) 0
1657#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1658#endif
1659
1660#ifdef CONFIG_SCSI_IPR_DUMP
1661#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1662#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1663#else
1664#define ipr_create_dump_file(kobj, attr) 0
1665#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1666#endif
1667
1668/*
1669 * Error logging macros
1670 */
1671#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1672#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1da177e4
LT		 1673#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1674
3e7ebdfa
WB		 1675#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1676 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1677 bus, target, lun, ##__VA_ARGS__)
1678
1679#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1680 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1681
fb3ed3cb
BK		 1682#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1683 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1684 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1da177e4 1685
fb3ed3cb
BK		 1686#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1687 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1da177e4 1688
fa15b1f6
BK		 1689#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1690{ \
1691 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1692 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1693 } else { \
1694 ipr_err(fmt": %d:%d:%d:%d\n", \
1695 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1696 (res).bus, (res).target, (res).lun); \
1697 } \
1698}
1699
49dc6a18 1700#define ipr_hcam_err(hostrcb, fmt, ...) \
4565e370
WB		 1701{ \
1702 if (ipr_is_device(hostrcb)) { \
1703 if ((hostrcb)->ioa_cfg->sis64) { \
1704 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
5adcbeb3
WB		 1705 ipr_format_res_path(hostrcb->hcam.u.error64.fd_res_path, \
1706 hostrcb->rp_buffer, \
1707 sizeof(hostrcb->rp_buffer)), \
4565e370
WB		 1708 __VA_ARGS__); \
1709 } else { \
1710 ipr_ra_err((hostrcb)->ioa_cfg, \
1711 (hostrcb)->hcam.u.error.fd_res_addr, \
1712 fmt, __VA_ARGS__); \
1713 } \
1714 } else { \
1715 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1716 } \
49dc6a18
BK		 1717}
1718
1da177e4 1719#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
cadbd4a5 1720 __FILE__, __func__, __LINE__)
1da177e4 1721
cadbd4a5
HH		 1722#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1723#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1da177e4
LT		 1724
1725#define ipr_err_separator \
1726ipr_err("----------------------------------------------------------\n")
1727
1728
1729/*
1730 * Inlines
1731 */
1732
1733/**
1734 * ipr_is_ioa_resource - Determine if a resource is the IOA
1735 * @res: resource entry struct
1736 *
1737 * Return value:
1738 * 1 if IOA / 0 if not IOA
1739 **/
1740static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1741{
3e7ebdfa 1742 return res->type == IPR_RES_TYPE_IOAFP;
1da177e4
LT		 1743}
1744
1745/**
1746 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1747 * @res: resource entry struct
1748 *
1749 * Return value:
1750 * 1 if AF DASD / 0 if not AF DASD
1751 **/
1752static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1753{
3e7ebdfa
WB		 1754 return res->type == IPR_RES_TYPE_AF_DASD ||
1755 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1da177e4
LT		 1756}
1757
1758/**
1759 * ipr_is_vset_device - Determine if a resource is a VSET
1760 * @res: resource entry struct
1761 *
1762 * Return value:
1763 * 1 if VSET / 0 if not VSET
1764 **/
1765static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1766{
3e7ebdfa 1767 return res->type == IPR_RES_TYPE_VOLUME_SET;
1da177e4
LT		 1768}
1769
1770/**
1771 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1772 * @res: resource entry struct
1773 *
1774 * Return value:
1775 * 1 if GSCSI / 0 if not GSCSI
1776 **/
1777static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1778{
3e7ebdfa 1779 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1da177e4
LT		 1780}
1781
e4fbf44e
BK		 1782/**
1783 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1784 * @res: resource entry struct
1785 *
1786 * Return value:
1787 * 1 if SCSI disk / 0 if not SCSI disk
1788 **/
1789static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1790{
1791 if (ipr_is_af_dasd_device(res) ||
3e7ebdfa 1792 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
e4fbf44e
BK		 1793 return 1;
1794 else
1795 return 0;
1796}
1797
b5145d25
BK		 1798/**
1799 * ipr_is_gata - Determine if a resource is a generic ATA resource
1800 * @res: resource entry struct
1801 *
1802 * Return value:
1803 * 1 if GATA / 0 if not GATA
1804 **/
1805static inline int ipr_is_gata(struct ipr_resource_entry *res)
1806{
3e7ebdfa 1807 return res->type == IPR_RES_TYPE_GENERIC_ATA;
b5145d25
BK		 1808}
1809
ee0a90fa
BK		 1810/**
1811 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1812 * @res: resource entry struct
1813 *
1814 * Return value:
1815 * 1 if NACA queueing model / 0 if not NACA queueing model
1816 **/
1817static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1818{
3e7ebdfa 1819 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
ee0a90fa
BK		 1820 return 1;
1821 return 0;
1822}
1823
1da177e4 1824/**
4565e370
WB		 1825 * ipr_is_device - Determine if the hostrcb structure is related to a device
1826 * @hostrcb: host resource control blocks struct
1da177e4
LT		 1827 *
1828 * Return value:
1829 * 1 if AF / 0 if not AF
1830 **/
4565e370 1831static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1da177e4 1832{
4565e370
WB		 1833 struct ipr_res_addr *res_addr;
1834 u8 *res_path;
1835
1836 if (hostrcb->ioa_cfg->sis64) {
1837 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1838 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1839 res_path[0] == 0x81) && res_path[2] != 0xFF)
1840 return 1;
1841 } else {
1842 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1843
1844 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1845 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1846 return 1;
1847 }
1da177e4
LT		 1848 return 0;
1849}
1850
1851/**
1852 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1853 * @sdt_word: SDT address
1854 *
1855 * Return value:
1856 * 1 if format 2 / 0 if not
1857 **/
1858static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1859{
1860 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1861
1862 switch (bar_sel) {
1863 case IPR_SDT_FMT2_BAR0_SEL:
1864 case IPR_SDT_FMT2_BAR1_SEL:
1865 case IPR_SDT_FMT2_BAR2_SEL:
1866 case IPR_SDT_FMT2_BAR3_SEL:
1867 case IPR_SDT_FMT2_BAR4_SEL:
1868 case IPR_SDT_FMT2_BAR5_SEL:
1869 case IPR_SDT_FMT2_EXP_ROM_SEL:
1870 return 1;
1871 };
1872
1873 return 0;
1874}
1875
c5f10187
WB		 1876#ifndef writeq
1877static inline void writeq(u64 val, void __iomem *addr)
1878{
1879 writel(((u32) (val >> 32)), addr);
1880 writel(((u32) (val)), (addr + 4));
1881}
1da177e4 1882#endif
c5f10187
WB		 1883
1884#endif /* _IPR_H */
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