[net-next-2.6.git] / drivers / scsi / bfa / bfa_hw_ct.c

/*
 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
 * All rights reserved
 * www.brocade.com
 *
 * Linux driver for Brocade Fibre Channel Host Bus Adapter.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License (GPL) Version 2 as
 * published by the Free Software Foundation
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */

#include "bfa_modules.h"
#include "bfi_ctreg.h"

BFA_TRC_FILE(HAL, IOCFC_CT);

static u32 __ct_msix_err_vec_reg[] = {
	HOST_MSIX_ERR_INDEX_FN0,
	HOST_MSIX_ERR_INDEX_FN1,
	HOST_MSIX_ERR_INDEX_FN2,
	HOST_MSIX_ERR_INDEX_FN3,
};

static void
bfa_hwct_msix_lpu_err_set(struct bfa_s *bfa, bfa_boolean_t msix, int vec)
{
	int fn = bfa_ioc_pcifn(&bfa->ioc);
	void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);

	if (msix)
		writel(vec, kva + __ct_msix_err_vec_reg[fn]);
	else
		writel(0, kva + __ct_msix_err_vec_reg[fn]);
}

/*
 * Dummy interrupt handler for handling spurious interrupt during chip-reinit.
 */
static void
bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec)
{
}

void
bfa_hwct_reginit(struct bfa_s *bfa)
{
	struct bfa_iocfc_regs_s	*bfa_regs = &bfa->iocfc.bfa_regs;
	void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
	int			i, q, fn = bfa_ioc_pcifn(&bfa->ioc);

	if (fn == 0) {
		bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
		bfa_regs->intr_mask   = (kva + HOSTFN0_INT_MSK);
	} else {
		bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
		bfa_regs->intr_mask   = (kva + HOSTFN1_INT_MSK);
	}

	for (i = 0; i < BFI_IOC_MAX_CQS; i++) {
		/*
		 * CPE registers
		 */
		q = CPE_Q_NUM(fn, i);
		bfa_regs->cpe_q_pi[i] = (kva + CPE_PI_PTR_Q(q << 5));
		bfa_regs->cpe_q_ci[i] = (kva + CPE_CI_PTR_Q(q << 5));
		bfa_regs->cpe_q_depth[i] = (kva + CPE_DEPTH_Q(q << 5));
		bfa_regs->cpe_q_ctrl[i] = (kva + CPE_QCTRL_Q(q << 5));

		/*
		 * RME registers
		 */
		q = CPE_Q_NUM(fn, i);
		bfa_regs->rme_q_pi[i] = (kva + RME_PI_PTR_Q(q << 5));
		bfa_regs->rme_q_ci[i] = (kva + RME_CI_PTR_Q(q << 5));
		bfa_regs->rme_q_depth[i] = (kva + RME_DEPTH_Q(q << 5));
		bfa_regs->rme_q_ctrl[i] = (kva + RME_QCTRL_Q(q << 5));
	}
}

void
bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq)
{
	u32	r32;

	r32 = readl(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
	writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
}

void
bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq)
{
	u32	r32;

	r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
	writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
}

void
bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
		 u32 *num_vecs, u32 *max_vec_bit)
{
	*msix_vecs_bmap = (1 << BFA_MSIX_CT_MAX) - 1;
	*max_vec_bit = (1 << (BFA_MSIX_CT_MAX - 1));
	*num_vecs = BFA_MSIX_CT_MAX;
}

/*
 * Setup MSI-X vector for catapult
 */
void
bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
{
	bfa_assert((nvecs == 1) || (nvecs == BFA_MSIX_CT_MAX));
	bfa_trc(bfa, nvecs);

	bfa->msix.nvecs = nvecs;
	bfa_hwct_msix_uninstall(bfa);
}

void
bfa_hwct_msix_install(struct bfa_s *bfa)
{
	int i;

	if (bfa->msix.nvecs == 0)
		return;

	if (bfa->msix.nvecs == 1) {
		for (i = 0; i < BFA_MSIX_CT_MAX; i++)
			bfa->msix.handler[i] = bfa_msix_all;
		return;
	}

	for (i = BFA_MSIX_CPE_Q0; i <= BFA_MSIX_CPE_Q3; i++)
		bfa->msix.handler[i] = bfa_msix_reqq;

	for (; i <= BFA_MSIX_RME_Q3; i++)
		bfa->msix.handler[i] = bfa_msix_rspq;

	bfa_assert(i == BFA_MSIX_LPU_ERR);
	bfa->msix.handler[BFA_MSIX_LPU_ERR] = bfa_msix_lpu_err;
}

void
bfa_hwct_msix_uninstall(struct bfa_s *bfa)
{
	int i;

	for (i = 0; i < BFA_MSIX_CT_MAX; i++)
		bfa->msix.handler[i] = bfa_hwct_msix_dummy;
}

/*
 * Enable MSI-X vectors
 */
void
bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
{
	bfa_trc(bfa, 0);
	bfa_hwct_msix_lpu_err_set(bfa, msix, BFA_MSIX_LPU_ERR);
	bfa_ioc_isr_mode_set(&bfa->ioc, msix);
}

void
bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
{
	*start = BFA_MSIX_RME_Q0;
	*end = BFA_MSIX_RME_Q3;
}
Commit	Line	Data
7725ccfd	1	/*
a36c61f9	2	* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
7725ccfd JH	3	* All rights reserved
	4	* www.brocade.com
	5	*
	6	* Linux driver for Brocade Fibre Channel Host Bus Adapter.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License (GPL) Version 2 as
	10	* published by the Free Software Foundation
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*/
	17
a36c61f9 KG	18	#include "bfa_modules.h"
a36c61f9 KG	19	#include "bfi_ctreg.h"
7725ccfd JH	20
	21	BFA_TRC_FILE(HAL, IOCFC_CT);
	22
	23	static u32 __ct_msix_err_vec_reg[] = {
	24	HOST_MSIX_ERR_INDEX_FN0,
	25	HOST_MSIX_ERR_INDEX_FN1,
	26	HOST_MSIX_ERR_INDEX_FN2,
	27	HOST_MSIX_ERR_INDEX_FN3,
	28	};
	29
	30	static void
	31	bfa_hwct_msix_lpu_err_set(struct bfa_s *bfa, bfa_boolean_t msix, int vec)
	32	{
	33	int fn = bfa_ioc_pcifn(&bfa->ioc);
53440260	34	void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
7725ccfd JH	35
7725ccfd JH	36	if (msix)
53440260	37	writel(vec, kva + __ct_msix_err_vec_reg[fn]);
7725ccfd	38	else
53440260	39	writel(0, kva + __ct_msix_err_vec_reg[fn]);
7725ccfd JH	40	}
7725ccfd JH	41
5fbe25c7	42	/*
7725ccfd JH	43	* Dummy interrupt handler for handling spurious interrupt during chip-reinit.
	44	*/
	45	static void
	46	bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec)
	47	{
	48	}
	49
	50	void
	51	bfa_hwct_reginit(struct bfa_s *bfa)
	52	{
	53	struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
53440260	54	void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
a36c61f9	55	int i, q, fn = bfa_ioc_pcifn(&bfa->ioc);
7725ccfd JH	56
	57	if (fn == 0) {
	58	bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
	59	bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK);
	60	} else {
	61	bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
	62	bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
	63	}
	64
	65	for (i = 0; i < BFI_IOC_MAX_CQS; i++) {
	66	/*
	67	* CPE registers
	68	*/
	69	q = CPE_Q_NUM(fn, i);
	70	bfa_regs->cpe_q_pi[i] = (kva + CPE_PI_PTR_Q(q << 5));
	71	bfa_regs->cpe_q_ci[i] = (kva + CPE_CI_PTR_Q(q << 5));
	72	bfa_regs->cpe_q_depth[i] = (kva + CPE_DEPTH_Q(q << 5));
	73	bfa_regs->cpe_q_ctrl[i] = (kva + CPE_QCTRL_Q(q << 5));
	74
	75	/*
	76	* RME registers
	77	*/
	78	q = CPE_Q_NUM(fn, i);
	79	bfa_regs->rme_q_pi[i] = (kva + RME_PI_PTR_Q(q << 5));
	80	bfa_regs->rme_q_ci[i] = (kva + RME_CI_PTR_Q(q << 5));
	81	bfa_regs->rme_q_depth[i] = (kva + RME_DEPTH_Q(q << 5));
	82	bfa_regs->rme_q_ctrl[i] = (kva + RME_QCTRL_Q(q << 5));
	83	}
	84	}
	85
f5713c5d KG	86	void
	87	bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq)
	88	{
a36c61f9	89	u32 r32;
f5713c5d	90
53440260 JH	91	r32 = readl(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
53440260 JH	92	writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
f5713c5d KG	93	}
f5713c5d KG	94
7725ccfd JH	95	void
	96	bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq)
	97	{
	98	u32 r32;
	99
53440260 JH	100	r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
53440260 JH	101	writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
7725ccfd JH	102	}
	103
	104	void
	105	bfa_hwct_msix_getvecs(struct bfa_s bfa, u32 msix_vecs_bmap,
	106	u32 num_vecs, u32 max_vec_bit)
	107	{
	108	*msix_vecs_bmap = (1 << BFA_MSIX_CT_MAX) - 1;
	109	*max_vec_bit = (1 << (BFA_MSIX_CT_MAX - 1));
	110	*num_vecs = BFA_MSIX_CT_MAX;
	111	}
	112
5fbe25c7	113	/*
7725ccfd JH	114	* Setup MSI-X vector for catapult
	115	*/
	116	void
	117	bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
	118	{
	119	bfa_assert((nvecs == 1) \|\| (nvecs == BFA_MSIX_CT_MAX));
	120	bfa_trc(bfa, nvecs);
	121
	122	bfa->msix.nvecs = nvecs;
	123	bfa_hwct_msix_uninstall(bfa);
	124	}
	125
	126	void
	127	bfa_hwct_msix_install(struct bfa_s *bfa)
	128	{
	129	int i;
	130
	131	if (bfa->msix.nvecs == 0)
	132	return;
	133
	134	if (bfa->msix.nvecs == 1) {
	135	for (i = 0; i < BFA_MSIX_CT_MAX; i++)
	136	bfa->msix.handler[i] = bfa_msix_all;
	137	return;
	138	}
	139
	140	for (i = BFA_MSIX_CPE_Q0; i <= BFA_MSIX_CPE_Q3; i++)
	141	bfa->msix.handler[i] = bfa_msix_reqq;
	142
	143	for (; i <= BFA_MSIX_RME_Q3; i++)
	144	bfa->msix.handler[i] = bfa_msix_rspq;
	145
	146	bfa_assert(i == BFA_MSIX_LPU_ERR);
	147	bfa->msix.handler[BFA_MSIX_LPU_ERR] = bfa_msix_lpu_err;
	148	}
	149
	150	void
	151	bfa_hwct_msix_uninstall(struct bfa_s *bfa)
	152	{
	153	int i;
	154
	155	for (i = 0; i < BFA_MSIX_CT_MAX; i++)
	156	bfa->msix.handler[i] = bfa_hwct_msix_dummy;
	157	}
	158
5fbe25c7	159	/*
7725ccfd JH	160	* Enable MSI-X vectors
	161	*/
	162	void
	163	bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
	164	{
	165	bfa_trc(bfa, 0);
	166	bfa_hwct_msix_lpu_err_set(bfa, msix, BFA_MSIX_LPU_ERR);
	167	bfa_ioc_isr_mode_set(&bfa->ioc, msix);
	168	}
	169
36d345a7 JH	170	void
	171	bfa_hwct_msix_get_rme_range(struct bfa_s bfa, u32 start, u32 *end)
	172	{
	173	*start = BFA_MSIX_RME_Q0;
	174	*end = BFA_MSIX_RME_Q3;
	175	}