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[SCSI] replace __inline with inline
[net-next-2.6.git] / drivers / scsi / aic7xxx / aic7xxx_pci.c
CommitLineData
1da177e4
LT		 1/*
2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
5 *
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2001 Adaptec Inc.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
5e46631b 42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#79 $
1da177e4
LT		 43 */
44
45#ifdef __linux__
46#include "aic7xxx_osm.h"
47#include "aic7xxx_inline.h"
48#include "aic7xxx_93cx6.h"
49#else
50#include <dev/aic7xxx/aic7xxx_osm.h>
51#include <dev/aic7xxx/aic7xxx_inline.h>
52#include <dev/aic7xxx/aic7xxx_93cx6.h>
53#endif
54
55#include "aic7xxx_pci.h"
56
1beb6fa8 57static inline uint64_t
1da177e4
LT		 58ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
59{
60 uint64_t id;
61
62 id = subvendor
63 | (subdevice << 16)
64 | ((uint64_t)vendor << 32)
65 | ((uint64_t)device << 48);
66
67 return (id);
68}
69
70#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */
71#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
72
73#define DEVID_9005_TYPE(id) ((id) & 0xF)
74#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
75#define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
76#define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
77#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
78
79#define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
80#define DEVID_9005_MAXRATE_U160 0x0
81#define DEVID_9005_MAXRATE_ULTRA2 0x1
82#define DEVID_9005_MAXRATE_ULTRA 0x2
83#define DEVID_9005_MAXRATE_FAST 0x3
84
85#define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
86
87#define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
88#define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
89
90#define SUBID_9005_TYPE(id) ((id) & 0xF)
91#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
92#define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
93#define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
94#define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
95
96#define SUBID_9005_TYPE_KNOWN(id) \
97 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
98 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
99 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
100 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
101
102#define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
103#define SUBID_9005_MAXRATE_ULTRA2 0x0
104#define SUBID_9005_MAXRATE_ULTRA 0x1
105#define SUBID_9005_MAXRATE_U160 0x2
106#define SUBID_9005_MAXRATE_RESERVED 0x3
107
108#define SUBID_9005_SEEPTYPE(id) \
109 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
110 ? ((id) & 0xC0) >> 6 \
111 : ((id) & 0x300) >> 8)
112#define SUBID_9005_SEEPTYPE_NONE 0x0
113#define SUBID_9005_SEEPTYPE_1K 0x1
114#define SUBID_9005_SEEPTYPE_2K_4K 0x2
115#define SUBID_9005_SEEPTYPE_RESERVED 0x3
116#define SUBID_9005_AUTOTERM(id) \
117 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
118 ? (((id) & 0x400) >> 10) == 0 \
119 : (((id) & 0x40) >> 6) == 0)
120
121#define SUBID_9005_NUMCHAN(id) \
122 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
123 ? ((id) & 0x300) >> 8 \
124 : ((id) & 0xC00) >> 10)
125
126#define SUBID_9005_LEGACYCONN(id) \
127 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
128 ? 0 \
129 : ((id) & 0x80) >> 7)
130
131#define SUBID_9005_MFUNCENB(id) \
132 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
133 ? ((id) & 0x800) >> 11 \
134 : ((id) & 0x1000) >> 12)
135/*
136 * Informational only. Should use chip register to be
137 * certain, but may be use in identification strings.
138 */
139#define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
140#define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
141#define SUBID_9005_CARD_SEDIFF_MASK 0x8000
142
143static ahc_device_setup_t ahc_aic785X_setup;
144static ahc_device_setup_t ahc_aic7860_setup;
145static ahc_device_setup_t ahc_apa1480_setup;
146static ahc_device_setup_t ahc_aic7870_setup;
b2d8bfe1 147static ahc_device_setup_t ahc_aic7870h_setup;
1da177e4 148static ahc_device_setup_t ahc_aha394X_setup;
b2d8bfe1 149static ahc_device_setup_t ahc_aha394Xh_setup;
1da177e4 150static ahc_device_setup_t ahc_aha494X_setup;
b2d8bfe1 151static ahc_device_setup_t ahc_aha494Xh_setup;
1da177e4
LT		 152static ahc_device_setup_t ahc_aha398X_setup;
153static ahc_device_setup_t ahc_aic7880_setup;
b2d8bfe1 154static ahc_device_setup_t ahc_aic7880h_setup;
1da177e4
LT		 155static ahc_device_setup_t ahc_aha2940Pro_setup;
156static ahc_device_setup_t ahc_aha394XU_setup;
b2d8bfe1 157static ahc_device_setup_t ahc_aha394XUh_setup;
1da177e4
LT		 158static ahc_device_setup_t ahc_aha398XU_setup;
159static ahc_device_setup_t ahc_aic7890_setup;
160static ahc_device_setup_t ahc_aic7892_setup;
161static ahc_device_setup_t ahc_aic7895_setup;
b2d8bfe1 162static ahc_device_setup_t ahc_aic7895h_setup;
1da177e4
LT		 163static ahc_device_setup_t ahc_aic7896_setup;
164static ahc_device_setup_t ahc_aic7899_setup;
165static ahc_device_setup_t ahc_aha29160C_setup;
166static ahc_device_setup_t ahc_raid_setup;
167static ahc_device_setup_t ahc_aha394XX_setup;
168static ahc_device_setup_t ahc_aha494XX_setup;
169static ahc_device_setup_t ahc_aha398XX_setup;
170
980b306a 171static const struct ahc_pci_identity ahc_pci_ident_table[] = {
1da177e4
LT		 172 /* aic7850 based controllers */
173 {
174 ID_AHA_2902_04_10_15_20C_30C,
175 ID_ALL_MASK,
176 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
177 ahc_aic785X_setup
178 },
179 /* aic7860 based controllers */
180 {
181 ID_AHA_2930CU,
182 ID_ALL_MASK,
183 "Adaptec 2930CU SCSI adapter",
184 ahc_aic7860_setup
185 },
186 {
187 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
188 ID_DEV_VENDOR_MASK,
189 "Adaptec 1480A Ultra SCSI adapter",
190 ahc_apa1480_setup
191 },
192 {
193 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
194 ID_DEV_VENDOR_MASK,
195 "Adaptec 2940A Ultra SCSI adapter",
196 ahc_aic7860_setup
197 },
198 {
199 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
200 ID_DEV_VENDOR_MASK,
201 "Adaptec 2940A/CN Ultra SCSI adapter",
202 ahc_aic7860_setup
203 },
204 {
205 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
206 ID_DEV_VENDOR_MASK,
207 "Adaptec 2930C Ultra SCSI adapter (VAR)",
208 ahc_aic7860_setup
209 },
210 /* aic7870 based controllers */
211 {
212 ID_AHA_2940,
213 ID_ALL_MASK,
214 "Adaptec 2940 SCSI adapter",
215 ahc_aic7870_setup
216 },
217 {
218 ID_AHA_3940,
219 ID_ALL_MASK,
220 "Adaptec 3940 SCSI adapter",
221 ahc_aha394X_setup
222 },
223 {
224 ID_AHA_398X,
225 ID_ALL_MASK,
226 "Adaptec 398X SCSI RAID adapter",
227 ahc_aha398X_setup
228 },
229 {
230 ID_AHA_2944,
231 ID_ALL_MASK,
232 "Adaptec 2944 SCSI adapter",
b2d8bfe1 233 ahc_aic7870h_setup
1da177e4
LT		 234 },
235 {
236 ID_AHA_3944,
237 ID_ALL_MASK,
238 "Adaptec 3944 SCSI adapter",
b2d8bfe1 239 ahc_aha394Xh_setup
1da177e4
LT		 240 },
241 {
242 ID_AHA_4944,
243 ID_ALL_MASK,
244 "Adaptec 4944 SCSI adapter",
b2d8bfe1 245 ahc_aha494Xh_setup
1da177e4
LT		 246 },
247 /* aic7880 based controllers */
248 {
249 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
250 ID_DEV_VENDOR_MASK,
251 "Adaptec 2940 Ultra SCSI adapter",
252 ahc_aic7880_setup
253 },
254 {
255 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
256 ID_DEV_VENDOR_MASK,
257 "Adaptec 3940 Ultra SCSI adapter",
258 ahc_aha394XU_setup
259 },
260 {
261 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
262 ID_DEV_VENDOR_MASK,
263 "Adaptec 2944 Ultra SCSI adapter",
b2d8bfe1 264 ahc_aic7880h_setup
1da177e4
LT		 265 },
266 {
267 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
268 ID_DEV_VENDOR_MASK,
269 "Adaptec 3944 Ultra SCSI adapter",
b2d8bfe1 270 ahc_aha394XUh_setup
1da177e4
LT		 271 },
272 {
273 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
274 ID_DEV_VENDOR_MASK,
275 "Adaptec 398X Ultra SCSI RAID adapter",
276 ahc_aha398XU_setup
277 },
278 {
279 /*
280 * XXX Don't know the slot numbers
281 * so we can't identify channels
282 */
283 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
284 ID_DEV_VENDOR_MASK,
285 "Adaptec 4944 Ultra SCSI adapter",
b2d8bfe1 286 ahc_aic7880h_setup
1da177e4
LT		 287 },
288 {
289 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
290 ID_DEV_VENDOR_MASK,
291 "Adaptec 2930 Ultra SCSI adapter",
292 ahc_aic7880_setup
293 },
294 {
295 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
296 ID_DEV_VENDOR_MASK,
297 "Adaptec 2940 Pro Ultra SCSI adapter",
298 ahc_aha2940Pro_setup
299 },
300 {
301 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
302 ID_DEV_VENDOR_MASK,
303 "Adaptec 2940/CN Ultra SCSI adapter",
304 ahc_aic7880_setup
305 },
306 /* Ignore all SISL (AAC on MB) based controllers. */
307 {
308 ID_9005_SISL_ID,
309 ID_9005_SISL_MASK,
310 NULL,
311 NULL
312 },
313 /* aic7890 based controllers */
314 {
315 ID_AHA_2930U2,
316 ID_ALL_MASK,
317 "Adaptec 2930 Ultra2 SCSI adapter",
318 ahc_aic7890_setup
319 },
320 {
321 ID_AHA_2940U2B,
322 ID_ALL_MASK,
323 "Adaptec 2940B Ultra2 SCSI adapter",
324 ahc_aic7890_setup
325 },
326 {
327 ID_AHA_2940U2_OEM,
328 ID_ALL_MASK,
329 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
330 ahc_aic7890_setup
331 },
332 {
333 ID_AHA_2940U2,
334 ID_ALL_MASK,
335 "Adaptec 2940 Ultra2 SCSI adapter",
336 ahc_aic7890_setup
337 },
338 {
339 ID_AHA_2950U2B,
340 ID_ALL_MASK,
341 "Adaptec 2950 Ultra2 SCSI adapter",
342 ahc_aic7890_setup
343 },
344 {
345 ID_AIC7890_ARO,
346 ID_ALL_MASK,
347 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
348 ahc_aic7890_setup
349 },
350 {
351 ID_AAA_131U2,
352 ID_ALL_MASK,
353 "Adaptec AAA-131 Ultra2 RAID adapter",
354 ahc_aic7890_setup
355 },
356 /* aic7892 based controllers */
357 {
358 ID_AHA_29160,
359 ID_ALL_MASK,
360 "Adaptec 29160 Ultra160 SCSI adapter",
361 ahc_aic7892_setup
362 },
363 {
364 ID_AHA_29160_CPQ,
365 ID_ALL_MASK,
366 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
367 ahc_aic7892_setup
368 },
369 {
370 ID_AHA_29160N,
371 ID_ALL_MASK,
372 "Adaptec 29160N Ultra160 SCSI adapter",
373 ahc_aic7892_setup
374 },
375 {
376 ID_AHA_29160C,
377 ID_ALL_MASK,
378 "Adaptec 29160C Ultra160 SCSI adapter",
379 ahc_aha29160C_setup
380 },
381 {
382 ID_AHA_29160B,
383 ID_ALL_MASK,
384 "Adaptec 29160B Ultra160 SCSI adapter",
385 ahc_aic7892_setup
386 },
387 {
388 ID_AHA_19160B,
389 ID_ALL_MASK,
390 "Adaptec 19160B Ultra160 SCSI adapter",
391 ahc_aic7892_setup
392 },
393 {
394 ID_AIC7892_ARO,
395 ID_ALL_MASK,
396 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
397 ahc_aic7892_setup
398 },
5e46631b
HR		 399 {
400 ID_AHA_2915_30LP,
401 ID_ALL_MASK,
402 "Adaptec 2915/30LP Ultra160 SCSI adapter",
403 ahc_aic7892_setup
404 },
1da177e4
LT		 405 /* aic7895 based controllers */
406 {
407 ID_AHA_2940U_DUAL,
408 ID_ALL_MASK,
409 "Adaptec 2940/DUAL Ultra SCSI adapter",
410 ahc_aic7895_setup
411 },
412 {
413 ID_AHA_3940AU,
414 ID_ALL_MASK,
415 "Adaptec 3940A Ultra SCSI adapter",
416 ahc_aic7895_setup
417 },
418 {
419 ID_AHA_3944AU,
420 ID_ALL_MASK,
421 "Adaptec 3944A Ultra SCSI adapter",
b2d8bfe1 422 ahc_aic7895h_setup
1da177e4
LT		 423 },
424 {
425 ID_AIC7895_ARO,
426 ID_AIC7895_ARO_MASK,
427 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
428 ahc_aic7895_setup
429 },
430 /* aic7896/97 based controllers */
431 {
432 ID_AHA_3950U2B_0,
433 ID_ALL_MASK,
434 "Adaptec 3950B Ultra2 SCSI adapter",
435 ahc_aic7896_setup
436 },
437 {
438 ID_AHA_3950U2B_1,
439 ID_ALL_MASK,
440 "Adaptec 3950B Ultra2 SCSI adapter",
441 ahc_aic7896_setup
442 },
443 {
444 ID_AHA_3950U2D_0,
445 ID_ALL_MASK,
446 "Adaptec 3950D Ultra2 SCSI adapter",
447 ahc_aic7896_setup
448 },
449 {
450 ID_AHA_3950U2D_1,
451 ID_ALL_MASK,
452 "Adaptec 3950D Ultra2 SCSI adapter",
453 ahc_aic7896_setup
454 },
455 {
456 ID_AIC7896_ARO,
457 ID_ALL_MASK,
458 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
459 ahc_aic7896_setup
460 },
461 /* aic7899 based controllers */
462 {
463 ID_AHA_3960D,
464 ID_ALL_MASK,
465 "Adaptec 3960D Ultra160 SCSI adapter",
466 ahc_aic7899_setup
467 },
468 {
469 ID_AHA_3960D_CPQ,
470 ID_ALL_MASK,
471 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
472 ahc_aic7899_setup
473 },
474 {
475 ID_AIC7899_ARO,
476 ID_ALL_MASK,
477 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
478 ahc_aic7899_setup
479 },
480 /* Generic chip probes for devices we don't know 'exactly' */
481 {
482 ID_AIC7850 & ID_DEV_VENDOR_MASK,
483 ID_DEV_VENDOR_MASK,
484 "Adaptec aic7850 SCSI adapter",
485 ahc_aic785X_setup
486 },
487 {
488 ID_AIC7855 & ID_DEV_VENDOR_MASK,
489 ID_DEV_VENDOR_MASK,
490 "Adaptec aic7855 SCSI adapter",
491 ahc_aic785X_setup
492 },
493 {
494 ID_AIC7859 & ID_DEV_VENDOR_MASK,
495 ID_DEV_VENDOR_MASK,
496 "Adaptec aic7859 SCSI adapter",
497 ahc_aic7860_setup
498 },
499 {
500 ID_AIC7860 & ID_DEV_VENDOR_MASK,
501 ID_DEV_VENDOR_MASK,
502 "Adaptec aic7860 Ultra SCSI adapter",
503 ahc_aic7860_setup
504 },
505 {
506 ID_AIC7870 & ID_DEV_VENDOR_MASK,
507 ID_DEV_VENDOR_MASK,
508 "Adaptec aic7870 SCSI adapter",
509 ahc_aic7870_setup
510 },
511 {
512 ID_AIC7880 & ID_DEV_VENDOR_MASK,
513 ID_DEV_VENDOR_MASK,
514 "Adaptec aic7880 Ultra SCSI adapter",
515 ahc_aic7880_setup
516 },
517 {
518 ID_AIC7890 & ID_9005_GENERIC_MASK,
519 ID_9005_GENERIC_MASK,
520 "Adaptec aic7890/91 Ultra2 SCSI adapter",
521 ahc_aic7890_setup
522 },
523 {
524 ID_AIC7892 & ID_9005_GENERIC_MASK,
525 ID_9005_GENERIC_MASK,
526 "Adaptec aic7892 Ultra160 SCSI adapter",
527 ahc_aic7892_setup
528 },
529 {
530 ID_AIC7895 & ID_DEV_VENDOR_MASK,
531 ID_DEV_VENDOR_MASK,
532 "Adaptec aic7895 Ultra SCSI adapter",
533 ahc_aic7895_setup
534 },
535 {
536 ID_AIC7896 & ID_9005_GENERIC_MASK,
537 ID_9005_GENERIC_MASK,
538 "Adaptec aic7896/97 Ultra2 SCSI adapter",
539 ahc_aic7896_setup
540 },
541 {
542 ID_AIC7899 & ID_9005_GENERIC_MASK,
543 ID_9005_GENERIC_MASK,
544 "Adaptec aic7899 Ultra160 SCSI adapter",
545 ahc_aic7899_setup
546 },
547 {
548 ID_AIC7810 & ID_DEV_VENDOR_MASK,
549 ID_DEV_VENDOR_MASK,
550 "Adaptec aic7810 RAID memory controller",
551 ahc_raid_setup
552 },
553 {
554 ID_AIC7815 & ID_DEV_VENDOR_MASK,
555 ID_DEV_VENDOR_MASK,
556 "Adaptec aic7815 RAID memory controller",
557 ahc_raid_setup
558 }
559};
560
289fe5b1 561static const u_int ahc_num_pci_devs = ARRAY_SIZE(ahc_pci_ident_table);
1da177e4
LT		 562
563#define AHC_394X_SLOT_CHANNEL_A 4
564#define AHC_394X_SLOT_CHANNEL_B 5
565
566#define AHC_398X_SLOT_CHANNEL_A 4
567#define AHC_398X_SLOT_CHANNEL_B 8
568#define AHC_398X_SLOT_CHANNEL_C 12
569
570#define AHC_494X_SLOT_CHANNEL_A 4
571#define AHC_494X_SLOT_CHANNEL_B 5
572#define AHC_494X_SLOT_CHANNEL_C 6
573#define AHC_494X_SLOT_CHANNEL_D 7
574
575#define DEVCONFIG 0x40
576#define PCIERRGENDIS 0x80000000ul
577#define SCBSIZE32 0x00010000ul /* aic789X only */
578#define REXTVALID 0x00001000ul /* ultra cards only */
579#define MPORTMODE 0x00000400ul /* aic7870+ only */
580#define RAMPSM 0x00000200ul /* aic7870+ only */
581#define VOLSENSE 0x00000100ul
582#define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
583#define SCBRAMSEL 0x00000080ul
584#define MRDCEN 0x00000040ul
585#define EXTSCBTIME 0x00000020ul /* aic7870 only */
586#define EXTSCBPEN 0x00000010ul /* aic7870 only */
587#define BERREN 0x00000008ul
588#define DACEN 0x00000004ul
589#define STPWLEVEL 0x00000002ul
590#define DIFACTNEGEN 0x00000001ul /* aic7870 only */
591
592#define CSIZE_LATTIME 0x0c
593#define CACHESIZE 0x0000003ful /* only 5 bits */
594#define LATTIME 0x0000ff00ul
595
596/* PCI STATUS definitions */
597#define DPE 0x80
598#define SSE 0x40
599#define RMA 0x20
600#define RTA 0x10
601#define STA 0x08
602#define DPR 0x01
603
604static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
605 uint16_t subvendor, uint16_t subdevice);
606static int ahc_ext_scbram_present(struct ahc_softc *ahc);
607static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
608 int pcheck, int fast, int large);
609static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
610static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
611static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
612 struct seeprom_config *sc);
613static void configure_termination(struct ahc_softc *ahc,
614 struct seeprom_descriptor *sd,
615 u_int adapter_control,
616 u_int *sxfrctl1);
617
618static void ahc_new_term_detect(struct ahc_softc *ahc,
619 int *enableSEC_low,
620 int *enableSEC_high,
621 int *enablePRI_low,
622 int *enablePRI_high,
623 int *eeprom_present);
624static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
625 int *internal68_present,
626 int *externalcable_present,
627 int *eeprom_present);
628static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
629 int *externalcable_present,
630 int *eeprom_present);
631static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
632static uint8_t read_brdctl(struct ahc_softc *ahc);
633static void ahc_pci_intr(struct ahc_softc *ahc);
634static int ahc_pci_chip_init(struct ahc_softc *ahc);
1da177e4
LT		 635
636static int
637ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
638 uint16_t subdevice, uint16_t subvendor)
639{
640 int result;
641
642 /* Default to invalid. */
643 result = 0;
644 if (vendor == 0x9005
645 && subvendor == 0x9005
646 && subdevice != device
647 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
648
649 switch (SUBID_9005_TYPE(subdevice)) {
650 case SUBID_9005_TYPE_MB:
651 break;
652 case SUBID_9005_TYPE_CARD:
653 case SUBID_9005_TYPE_LCCARD:
654 /*
655 * Currently only trust Adaptec cards to
656 * get the sub device info correct.
657 */
658 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
659 result = 1;
660 break;
661 case SUBID_9005_TYPE_RAID:
662 break;
663 default:
664 break;
665 }
666 }
667 return (result);
668}
669
980b306a 670const struct ahc_pci_identity *
1da177e4
LT		 671ahc_find_pci_device(ahc_dev_softc_t pci)
672{
673 uint64_t full_id;
674 uint16_t device;
675 uint16_t vendor;
676 uint16_t subdevice;
677 uint16_t subvendor;
980b306a 678 const struct ahc_pci_identity *entry;
1da177e4
LT		 679 u_int i;
680
681 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
682 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
683 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
684 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
685 full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
686
687 /*
688 * If the second function is not hooked up, ignore it.
689 * Unfortunately, not all MB vendors implement the
690 * subdevice ID as per the Adaptec spec, so do our best
691 * to sanity check it prior to accepting the subdevice
692 * ID as valid.
693 */
694 if (ahc_get_pci_function(pci) > 0
695 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
696 && SUBID_9005_MFUNCENB(subdevice) == 0)
697 return (NULL);
698
699 for (i = 0; i < ahc_num_pci_devs; i++) {
700 entry = &ahc_pci_ident_table[i];
701 if (entry->full_id == (full_id & entry->id_mask)) {
702 /* Honor exclusion entries. */
703 if (entry->name == NULL)
704 return (NULL);
705 return (entry);
706 }
707 }
708 return (NULL);
709}
710
711int
980b306a 712ahc_pci_config(struct ahc_softc *ahc, const struct ahc_pci_identity *entry)
1da177e4 713{
1da177e4
LT		 714 u_int command;
715 u_int our_id;
716 u_int sxfrctl1;
717 u_int scsiseq;
718 u_int dscommand0;
719 uint32_t devconfig;
720 int error;
721 uint8_t sblkctl;
722
723 our_id = 0;
724 error = entry->setup(ahc);
725 if (error != 0)
726 return (error);
727 ahc->chip |= AHC_PCI;
728 ahc->description = entry->name;
729
730 pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0);
731
732 error = ahc_pci_map_registers(ahc);
733 if (error != 0)
734 return (error);
735
736 /*
737 * Before we continue probing the card, ensure that
738 * its interrupts are *disabled*. We don't want
739 * a misstep to hang the machine in an interrupt
740 * storm.
741 */
742 ahc_intr_enable(ahc, FALSE);
743
744 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
745
746 /*
747 * If we need to support high memory, enable dual
748 * address cycles. This bit must be set to enable
749 * high address bit generation even if we are on a
750 * 64bit bus (PCI64BIT set in devconfig).
751 */
752 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
753
754 if (bootverbose)
755 printf("%s: Enabling 39Bit Addressing\n",
756 ahc_name(ahc));
757 devconfig |= DACEN;
758 }
759
760 /* Ensure that pci error generation, a test feature, is disabled. */
761 devconfig |= PCIERRGENDIS;
762
763 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
764
765 /* Ensure busmastering is enabled */
766 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
767 command |= PCIM_CMD_BUSMASTEREN;
768
769 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
770
771 /* On all PCI adapters, we allow SCB paging */
772 ahc->flags |= AHC_PAGESCBS;
773
774 error = ahc_softc_init(ahc);
775 if (error != 0)
776 return (error);
777
778 /*
779 * Disable PCI parity error checking. Users typically
780 * do this to work around broken PCI chipsets that get
781 * the parity timing wrong and thus generate lots of spurious
782 * errors. The chip only allows us to disable *all* parity
783 * error reporting when doing this, so CIO bus, scb ram, and
784 * scratch ram parity errors will be ignored too.
785 */
786 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
787 ahc->seqctl |= FAILDIS;
788
789 ahc->bus_intr = ahc_pci_intr;
790 ahc->bus_chip_init = ahc_pci_chip_init;
1da177e4
LT		 791
792 /* Remeber how the card was setup in case there is no SEEPROM */
793 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
794 ahc_pause(ahc);
795 if ((ahc->features & AHC_ULTRA2) != 0)
796 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
797 else
798 our_id = ahc_inb(ahc, SCSIID) & OID;
799 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
800 scsiseq = ahc_inb(ahc, SCSISEQ);
801 } else {
802 sxfrctl1 = STPWEN;
803 our_id = 7;
804 scsiseq = 0;
805 }
806
807 error = ahc_reset(ahc, /*reinit*/FALSE);
808 if (error != 0)
809 return (ENXIO);
810
811 if ((ahc->features & AHC_DT) != 0) {
812 u_int sfunct;
813
814 /* Perform ALT-Mode Setup */
815 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
816 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
817 ahc_outb(ahc, OPTIONMODE,
818 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
819 ahc_outb(ahc, SFUNCT, sfunct);
820
821 /* Normal mode setup */
822 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
823 |TARGCRCENDEN);
824 }
825
826 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
827 dscommand0 |= MPARCKEN|CACHETHEN;
828 if ((ahc->features & AHC_ULTRA2) != 0) {
829
830 /*
831 * DPARCKEN doesn't work correctly on
832 * some MBs so don't use it.
833 */
834 dscommand0 &= ~DPARCKEN;
835 }
836
837 /*
838 * Handle chips that must have cache line
839 * streaming (dis/en)abled.
840 */
841 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
842 dscommand0 |= CACHETHEN;
843
844 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
845 dscommand0 &= ~CACHETHEN;
846
847 ahc_outb(ahc, DSCOMMAND0, dscommand0);
848
849 ahc->pci_cachesize =
850 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
851 /*bytes*/1) & CACHESIZE;
852 ahc->pci_cachesize *= 4;
853
854 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
855 && ahc->pci_cachesize == 4) {
856
857 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
858 0, /*bytes*/1);
859 ahc->pci_cachesize = 0;
860 }
861
862 /*
863 * We cannot perform ULTRA speeds without the presense
864 * of the external precision resistor.
865 */
866 if ((ahc->features & AHC_ULTRA) != 0) {
867 uint32_t devconfig;
868
869 devconfig = ahc_pci_read_config(ahc->dev_softc,
870 DEVCONFIG, /*bytes*/4);
871 if ((devconfig & REXTVALID) == 0)
872 ahc->features &= ~AHC_ULTRA;
873 }
874
875 /* See if we have a SEEPROM and perform auto-term */
876 check_extport(ahc, &sxfrctl1);
877
878 /*
879 * Take the LED out of diagnostic mode
880 */
881 sblkctl = ahc_inb(ahc, SBLKCTL);
882 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
883
884 if ((ahc->features & AHC_ULTRA2) != 0) {
885 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
886 } else {
887 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
888 }
889
890 if (ahc->flags & AHC_USEDEFAULTS) {
891 /*
892 * PCI Adapter default setup
893 * Should only be used if the adapter does not have
894 * a SEEPROM.
895 */
896 /* See if someone else set us up already */
897 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
898 && scsiseq != 0) {
899 printf("%s: Using left over BIOS settings\n",
900 ahc_name(ahc));
901 ahc->flags &= ~AHC_USEDEFAULTS;
902 ahc->flags |= AHC_BIOS_ENABLED;
903 } else {
904 /*
905 * Assume only one connector and always turn
906 * on termination.
907 */
908 our_id = 0x07;
909 sxfrctl1 = STPWEN;
910 }
911 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
912
913 ahc->our_id = our_id;
914 }
915
916 /*
917 * Take a look to see if we have external SRAM.
918 * We currently do not attempt to use SRAM that is
919 * shared among multiple controllers.
920 */
921 ahc_probe_ext_scbram(ahc);
922
923 /*
924 * Record our termination setting for the
925 * generic initialization routine.
926 */
927 if ((sxfrctl1 & STPWEN) != 0)
928 ahc->flags |= AHC_TERM_ENB_A;
929
930 /*
931 * Save chip register configuration data for chip resets
932 * that occur during runtime and resume events.
933 */
934 ahc->bus_softc.pci_softc.devconfig =
935 ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
936 ahc->bus_softc.pci_softc.command =
937 ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
938 ahc->bus_softc.pci_softc.csize_lattime =
939 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
940 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
941 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
942 if ((ahc->features & AHC_DT) != 0) {
943 u_int sfunct;
944
945 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
946 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
947 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
948 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
949 ahc_outb(ahc, SFUNCT, sfunct);
950 ahc->bus_softc.pci_softc.crccontrol1 =
951 ahc_inb(ahc, CRCCONTROL1);
952 }
953 if ((ahc->features & AHC_MULTI_FUNC) != 0)
954 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
955
956 if ((ahc->features & AHC_ULTRA2) != 0)
957 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
958
959 /* Core initialization */
960 error = ahc_init(ahc);
961 if (error != 0)
962 return (error);
a2f5bfcf 963 ahc->init_level++;
1da177e4
LT		 964
965 /*
966 * Allow interrupts now that we are completely setup.
967 */
a2f5bfcf 968 return ahc_pci_map_int(ahc);
1da177e4
LT		 969}
970
971/*
972 * Test for the presense of external sram in an
973 * "unshared" configuration.
974 */
975static int
976ahc_ext_scbram_present(struct ahc_softc *ahc)
977{
978 u_int chip;
979 int ramps;
980 int single_user;
981 uint32_t devconfig;
982
983 chip = ahc->chip & AHC_CHIPID_MASK;
984 devconfig = ahc_pci_read_config(ahc->dev_softc,
985 DEVCONFIG, /*bytes*/4);
986 single_user = (devconfig & MPORTMODE) != 0;
987
988 if ((ahc->features & AHC_ULTRA2) != 0)
989 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
990 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
991 /*
992 * External SCBRAM arbitration is flakey
993 * on these chips. Unfortunately this means
994 * we don't use the extra SCB ram space on the
995 * 3940AUW.
996 */
997 ramps = 0;
998 else if (chip >= AHC_AIC7870)
999 ramps = (devconfig & RAMPSM) != 0;
1000 else
1001 ramps = 0;
1002
1003 if (ramps && single_user)
1004 return (1);
1005 return (0);
1006}
1007
1008/*
1009 * Enable external scbram.
1010 */
1011static void
1012ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1013 int fast, int large)
1014{
1015 uint32_t devconfig;
1016
1017 if (ahc->features & AHC_MULTI_FUNC) {
1018 /*
1019 * Set the SCB Base addr (highest address bit)
1020 * depending on which channel we are.
1021 */
1022 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc));
1023 }
1024
1025 ahc->flags &= ~AHC_LSCBS_ENABLED;
1026 if (large)
1027 ahc->flags |= AHC_LSCBS_ENABLED;
1028 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1029 if ((ahc->features & AHC_ULTRA2) != 0) {
1030 u_int dscommand0;
1031
1032 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1033 if (enable)
1034 dscommand0 &= ~INTSCBRAMSEL;
1035 else
1036 dscommand0 |= INTSCBRAMSEL;
1037 if (large)
1038 dscommand0 &= ~USCBSIZE32;
1039 else
1040 dscommand0 |= USCBSIZE32;
1041 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1042 } else {
1043 if (fast)
1044 devconfig &= ~EXTSCBTIME;
1045 else
1046 devconfig |= EXTSCBTIME;
1047 if (enable)
1048 devconfig &= ~SCBRAMSEL;
1049 else
1050 devconfig |= SCBRAMSEL;
1051 if (large)
1052 devconfig &= ~SCBSIZE32;
1053 else
1054 devconfig |= SCBSIZE32;
1055 }
1056 if (pcheck)
1057 devconfig |= EXTSCBPEN;
1058 else
1059 devconfig &= ~EXTSCBPEN;
1060
1061 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1062}
1063
1064/*
1065 * Take a look to see if we have external SRAM.
1066 * We currently do not attempt to use SRAM that is
1067 * shared among multiple controllers.
1068 */
1069static void
1070ahc_probe_ext_scbram(struct ahc_softc *ahc)
1071{
1072 int num_scbs;
1073 int test_num_scbs;
1074 int enable;
1075 int pcheck;
1076 int fast;
1077 int large;
1078
1079 enable = FALSE;
1080 pcheck = FALSE;
1081 fast = FALSE;
1082 large = FALSE;
1083 num_scbs = 0;
1084
1085 if (ahc_ext_scbram_present(ahc) == 0)
1086 goto done;
1087
1088 /*
1089 * Probe for the best parameters to use.
1090 */
1091 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1092 num_scbs = ahc_probe_scbs(ahc);
1093 if (num_scbs == 0) {
1094 /* The SRAM wasn't really present. */
1095 goto done;
1096 }
1097 enable = TRUE;
1098
1099 /*
1100 * Clear any outstanding parity error
1101 * and ensure that parity error reporting
1102 * is enabled.
1103 */
1104 ahc_outb(ahc, SEQCTL, 0);
1105 ahc_outb(ahc, CLRINT, CLRPARERR);
1106 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1107
1108 /* Now see if we can do parity */
1109 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1110 num_scbs = ahc_probe_scbs(ahc);
1111 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1112 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1113 pcheck = TRUE;
1114
1115 /* Clear any resulting parity error */
1116 ahc_outb(ahc, CLRINT, CLRPARERR);
1117 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1118
1119 /* Now see if we can do fast timing */
1120 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1121 test_num_scbs = ahc_probe_scbs(ahc);
1122 if (test_num_scbs == num_scbs
1123 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1124 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1125 fast = TRUE;
1126
1127 /*
1128 * See if we can use large SCBs and still maintain
1129 * the same overall count of SCBs.
1130 */
1131 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1132 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1133 test_num_scbs = ahc_probe_scbs(ahc);
1134 if (test_num_scbs >= num_scbs) {
1135 large = TRUE;
1136 num_scbs = test_num_scbs;
1137 if (num_scbs >= 64) {
1138 /*
1139 * We have enough space to move the
1140 * "busy targets table" into SCB space
1141 * and make it qualify all the way to the
1142 * lun level.
1143 */
1144 ahc->flags |= AHC_SCB_BTT;
1145 }
1146 }
1147 }
1148done:
1149 /*
1150 * Disable parity error reporting until we
1151 * can load instruction ram.
1152 */
1153 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1154 /* Clear any latched parity error */
1155 ahc_outb(ahc, CLRINT, CLRPARERR);
1156 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1157 if (bootverbose && enable) {
1158 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1159 ahc_name(ahc), fast ? "fast" : "slow",
1160 pcheck ? ", parity checking enabled" : "",
1161 large ? 64 : 32);
1162 }
1163 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1164}
1165
1166/*
1167 * Perform some simple tests that should catch situations where
1168 * our registers are invalidly mapped.
1169 */
1170int
1171ahc_pci_test_register_access(struct ahc_softc *ahc)
1172{
1173 int error;
1174 u_int status1;
1175 uint32_t cmd;
1176 uint8_t hcntrl;
1177
1178 error = EIO;
1179
1180 /*
1181 * Enable PCI error interrupt status, but suppress NMIs
1182 * generated by SERR raised due to target aborts.
1183 */
1184 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1185 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1186 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1187
1188 /*
1189 * First a simple test to see if any
1190 * registers can be read. Reading
1191 * HCNTRL has no side effects and has
1192 * at least one bit that is guaranteed to
1193 * be zero so it is a good register to
1194 * use for this test.
1195 */
1196 hcntrl = ahc_inb(ahc, HCNTRL);
5e46631b 1197
1da177e4
LT		 1198 if (hcntrl == 0xFF)
1199 goto fail;
1200
5e46631b
HR		 1201 if ((hcntrl & CHIPRST) != 0) {
1202 /*
1203 * The chip has not been initialized since
1204 * PCI/EISA/VLB bus reset. Don't trust
1205 * "left over BIOS data".
1206 */
1207 ahc->flags |= AHC_NO_BIOS_INIT;
1208 }
1209
1da177e4
LT		 1210 /*
1211 * Next create a situation where write combining
1212 * or read prefetching could be initiated by the
1213 * CPU or host bridge. Our device does not support
1214 * either, so look for data corruption and/or flagged
1215 * PCI errors. First pause without causing another
1216 * chip reset.
1217 */
1218 hcntrl &= ~CHIPRST;
1219 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1220 while (ahc_is_paused(ahc) == 0)
1221 ;
1222
1223 /* Clear any PCI errors that occurred before our driver attached. */
1224 status1 = ahc_pci_read_config(ahc->dev_softc,
1225 PCIR_STATUS + 1, /*bytes*/1);
1226 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1227 status1, /*bytes*/1);
1228 ahc_outb(ahc, CLRINT, CLRPARERR);
1229
1230 ahc_outb(ahc, SEQCTL, PERRORDIS);
1231 ahc_outb(ahc, SCBPTR, 0);
1232 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1233 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1234 goto fail;
1235
1236 status1 = ahc_pci_read_config(ahc->dev_softc,
1237 PCIR_STATUS + 1, /*bytes*/1);
1238 if ((status1 & STA) != 0)
1239 goto fail;
1240
1241 error = 0;
1242
1243fail:
1244 /* Silently clear any latched errors. */
1245 status1 = ahc_pci_read_config(ahc->dev_softc,
1246 PCIR_STATUS + 1, /*bytes*/1);
1247 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1248 status1, /*bytes*/1);
1249 ahc_outb(ahc, CLRINT, CLRPARERR);
1250 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1251 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1252 return (error);
1253}
1254
1255/*
1256 * Check the external port logic for a serial eeprom
1257 * and termination/cable detection contrls.
1258 */
1259static void
1260check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1261{
1262 struct seeprom_descriptor sd;
1263 struct seeprom_config *sc;
1264 int have_seeprom;
1265 int have_autoterm;
1266
1267 sd.sd_ahc = ahc;
1268 sd.sd_control_offset = SEECTL;
1269 sd.sd_status_offset = SEECTL;
1270 sd.sd_dataout_offset = SEECTL;
1271 sc = ahc->seep_config;
1272
1273 /*
1274 * For some multi-channel devices, the c46 is simply too
1275 * small to work. For the other controller types, we can
1276 * get our information from either SEEPROM type. Set the
1277 * type to start our probe with accordingly.
1278 */
1279 if (ahc->flags & AHC_LARGE_SEEPROM)
1280 sd.sd_chip = C56_66;
1281 else
1282 sd.sd_chip = C46;
1283
1284 sd.sd_MS = SEEMS;
1285 sd.sd_RDY = SEERDY;
1286 sd.sd_CS = SEECS;
1287 sd.sd_CK = SEECK;
1288 sd.sd_DO = SEEDO;
1289 sd.sd_DI = SEEDI;
1290
1291 have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1292 if (have_seeprom) {
1293
1294 if (bootverbose)
1295 printf("%s: Reading SEEPROM...", ahc_name(ahc));
1296
1297 for (;;) {
1298 u_int start_addr;
1299
1300 start_addr = 32 * (ahc->channel - 'A');
1301
1302 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1303 start_addr,
1304 sizeof(*sc)/2);
1305
1306 if (have_seeprom)
1307 have_seeprom = ahc_verify_cksum(sc);
1308
1309 if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1310 if (bootverbose) {
1311 if (have_seeprom == 0)
1312 printf ("checksum error\n");
1313 else
1314 printf ("done.\n");
1315 }
1316 break;
1317 }
1318 sd.sd_chip = C56_66;
1319 }
1320 ahc_release_seeprom(&sd);
5e46631b
HR		 1321
1322 /* Remember the SEEPROM type for later */
1323 if (sd.sd_chip == C56_66)
1324 ahc->flags |= AHC_LARGE_SEEPROM;
1da177e4
LT		 1325 }
1326
1327 if (!have_seeprom) {
1328 /*
1329 * Pull scratch ram settings and treat them as
1330 * if they are the contents of an seeprom if
1331 * the 'ADPT' signature is found in SCB2.
1332 * We manually compose the data as 16bit values
1333 * to avoid endian issues.
1334 */
1335 ahc_outb(ahc, SCBPTR, 2);
1336 if (ahc_inb(ahc, SCB_BASE) == 'A'
1337 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1338 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1339 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1340 uint16_t *sc_data;
1341 int i;
1342
1343 sc_data = (uint16_t *)sc;
1344 for (i = 0; i < 32; i++, sc_data++) {
1345 int j;
1346
1347 j = i * 2;
1348 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1349 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1350 }
1351 have_seeprom = ahc_verify_cksum(sc);
1352 if (have_seeprom)
1353 ahc->flags |= AHC_SCB_CONFIG_USED;
1354 }
1355 /*
1356 * Clear any SCB parity errors in case this data and
1357 * its associated parity was not initialized by the BIOS
1358 */
1359 ahc_outb(ahc, CLRINT, CLRPARERR);
1360 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1361 }
1362
1363 if (!have_seeprom) {
1364 if (bootverbose)
1365 printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1366 ahc->flags |= AHC_USEDEFAULTS;
1367 free(ahc->seep_config, M_DEVBUF);
1368 ahc->seep_config = NULL;
1369 sc = NULL;
1370 } else {
1371 ahc_parse_pci_eeprom(ahc, sc);
1372 }
1373
1374 /*
1375 * Cards that have the external logic necessary to talk to
1376 * a SEEPROM, are almost certain to have the remaining logic
1377 * necessary for auto-termination control. This assumption
1378 * hasn't failed yet...
1379 */
1380 have_autoterm = have_seeprom;
1381
1382 /*
1383 * Some low-cost chips have SEEPROM and auto-term control built
1384 * in, instead of using a GAL. They can tell us directly
1385 * if the termination logic is enabled.
1386 */
1387 if ((ahc->features & AHC_SPIOCAP) != 0) {
1388 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1389 have_autoterm = FALSE;
1390 }
1391
1392 if (have_autoterm) {
1393 ahc->flags |= AHC_HAS_TERM_LOGIC;
1394 ahc_acquire_seeprom(ahc, &sd);
1395 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1396 ahc_release_seeprom(&sd);
1397 } else if (have_seeprom) {
1398 *sxfrctl1 &= ~STPWEN;
1399 if ((sc->adapter_control & CFSTERM) != 0)
1400 *sxfrctl1 |= STPWEN;
1401 if (bootverbose)
1402 printf("%s: Low byte termination %sabled\n",
1403 ahc_name(ahc),
1404 (*sxfrctl1 & STPWEN) ? "en" : "dis");
1405 }
1406}
1407
1408static void
1409ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1410{
1411 /*
1412 * Put the data we've collected down into SRAM
1413 * where ahc_init will find it.
1414 */
1415 int i;
1416 int max_targ = sc->max_targets & CFMAXTARG;
1417 u_int scsi_conf;
1418 uint16_t discenable;
1419 uint16_t ultraenb;
1420
1421 discenable = 0;
1422 ultraenb = 0;
1423 if ((sc->adapter_control & CFULTRAEN) != 0) {
1424 /*
1425 * Determine if this adapter has a "newstyle"
1426 * SEEPROM format.
1427 */
1428 for (i = 0; i < max_targ; i++) {
1429 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1430 ahc->flags |= AHC_NEWEEPROM_FMT;
1431 break;
1432 }
1433 }
1434 }
1435
1436 for (i = 0; i < max_targ; i++) {
1437 u_int scsirate;
1438 uint16_t target_mask;
1439
1440 target_mask = 0x01 << i;
1441 if (sc->device_flags[i] & CFDISC)
1442 discenable |= target_mask;
1443 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1444 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1445 ultraenb |= target_mask;
1446 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1447 ultraenb |= target_mask;
1448 }
1449 if ((sc->device_flags[i] & CFXFER) == 0x04
1450 && (ultraenb & target_mask) != 0) {
1451 /* Treat 10MHz as a non-ultra speed */
1452 sc->device_flags[i] &= ~CFXFER;
1453 ultraenb &= ~target_mask;
1454 }
1455 if ((ahc->features & AHC_ULTRA2) != 0) {
1456 u_int offset;
1457
1458 if (sc->device_flags[i] & CFSYNCH)
1459 offset = MAX_OFFSET_ULTRA2;
1460 else
1461 offset = 0;
1462 ahc_outb(ahc, TARG_OFFSET + i, offset);
1463
1464 /*
1465 * The ultra enable bits contain the
1466 * high bit of the ultra2 sync rate
1467 * field.
1468 */
1469 scsirate = (sc->device_flags[i] & CFXFER)
1470 | ((ultraenb & target_mask) ? 0x8 : 0x0);
1471 if (sc->device_flags[i] & CFWIDEB)
1472 scsirate |= WIDEXFER;
1473 } else {
1474 scsirate = (sc->device_flags[i] & CFXFER) << 4;
1475 if (sc->device_flags[i] & CFSYNCH)
1476 scsirate |= SOFS;
1477 if (sc->device_flags[i] & CFWIDEB)
1478 scsirate |= WIDEXFER;
1479 }
1480 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1481 }
1482 ahc->our_id = sc->brtime_id & CFSCSIID;
1483
1484 scsi_conf = (ahc->our_id & 0x7);
1485 if (sc->adapter_control & CFSPARITY)
1486 scsi_conf |= ENSPCHK;
1487 if (sc->adapter_control & CFRESETB)
1488 scsi_conf |= RESET_SCSI;
1489
1490 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1491
1492 if (sc->bios_control & CFEXTEND)
1493 ahc->flags |= AHC_EXTENDED_TRANS_A;
1494
1495 if (sc->bios_control & CFBIOSEN)
1496 ahc->flags |= AHC_BIOS_ENABLED;
1497 if (ahc->features & AHC_ULTRA
1498 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1499 /* Should we enable Ultra mode? */
1500 if (!(sc->adapter_control & CFULTRAEN))
1501 /* Treat us as a non-ultra card */
1502 ultraenb = 0;
1503 }
1504
1505 if (sc->signature == CFSIGNATURE
1506 || sc->signature == CFSIGNATURE2) {
1507 uint32_t devconfig;
1508
1509 /* Honor the STPWLEVEL settings */
1510 devconfig = ahc_pci_read_config(ahc->dev_softc,
1511 DEVCONFIG, /*bytes*/4);
1512 devconfig &= ~STPWLEVEL;
1513 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1514 devconfig |= STPWLEVEL;
1515 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
1516 devconfig, /*bytes*/4);
1517 }
1518 /* Set SCSICONF info */
1519 ahc_outb(ahc, SCSICONF, scsi_conf);
1520 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1521 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1522 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1523 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1524}
1525
1526static void
1527configure_termination(struct ahc_softc *ahc,
1528 struct seeprom_descriptor *sd,
1529 u_int adapter_control,
1530 u_int *sxfrctl1)
1531{
1532 uint8_t brddat;
1533
1534 brddat = 0;
1535
1536 /*
1537 * Update the settings in sxfrctl1 to match the
1538 * termination settings
1539 */
1540 *sxfrctl1 = 0;
1541
1542 /*
1543 * SEECS must be on for the GALS to latch
1544 * the data properly. Be sure to leave MS
1545 * on or we will release the seeprom.
1546 */
1547 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1548 if ((adapter_control & CFAUTOTERM) != 0
1549 || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1550 int internal50_present;
1551 int internal68_present;
1552 int externalcable_present;
1553 int eeprom_present;
1554 int enableSEC_low;
1555 int enableSEC_high;
1556 int enablePRI_low;
1557 int enablePRI_high;
1558 int sum;
1559
1560 enableSEC_low = 0;
1561 enableSEC_high = 0;
1562 enablePRI_low = 0;
1563 enablePRI_high = 0;
1564 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1565 ahc_new_term_detect(ahc, &enableSEC_low,
1566 &enableSEC_high,
1567 &enablePRI_low,
1568 &enablePRI_high,
1569 &eeprom_present);
1570 if ((adapter_control & CFSEAUTOTERM) == 0) {
1571 if (bootverbose)
1572 printf("%s: Manual SE Termination\n",
1573 ahc_name(ahc));
1574 enableSEC_low = (adapter_control & CFSELOWTERM);
1575 enableSEC_high =
1576 (adapter_control & CFSEHIGHTERM);
1577 }
1578 if ((adapter_control & CFAUTOTERM) == 0) {
1579 if (bootverbose)
1580 printf("%s: Manual LVD Termination\n",
1581 ahc_name(ahc));
1582 enablePRI_low = (adapter_control & CFSTERM);
1583 enablePRI_high = (adapter_control & CFWSTERM);
1584 }
1585 /* Make the table calculations below happy */
1586 internal50_present = 0;
1587 internal68_present = 1;
1588 externalcable_present = 1;
1589 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1590 aic785X_cable_detect(ahc, &internal50_present,
1591 &externalcable_present,
1592 &eeprom_present);
1593 /* Can never support a wide connector. */
1594 internal68_present = 0;
1595 } else {
1596 aic787X_cable_detect(ahc, &internal50_present,
1597 &internal68_present,
1598 &externalcable_present,
1599 &eeprom_present);
1600 }
1601
1602 if ((ahc->features & AHC_WIDE) == 0)
1603 internal68_present = 0;
1604
1605 if (bootverbose
1606 && (ahc->features & AHC_ULTRA2) == 0) {
1607 printf("%s: internal 50 cable %s present",
1608 ahc_name(ahc),
1609 internal50_present ? "is":"not");
1610
1611 if ((ahc->features & AHC_WIDE) != 0)
1612 printf(", internal 68 cable %s present",
1613 internal68_present ? "is":"not");
1614 printf("\n%s: external cable %s present\n",
1615 ahc_name(ahc),
1616 externalcable_present ? "is":"not");
1617 }
1618 if (bootverbose)
1619 printf("%s: BIOS eeprom %s present\n",
1620 ahc_name(ahc), eeprom_present ? "is" : "not");
1621
1622 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1623 /*
1624 * The 50 pin connector is a separate bus,
1625 * so force it to always be terminated.
1626 * In the future, perform current sensing
1627 * to determine if we are in the middle of
1628 * a properly terminated bus.
1629 */
1630 internal50_present = 0;
1631 }
1632
1633 /*
1634 * Now set the termination based on what
1635 * we found.
1636 * Flash Enable = BRDDAT7
1637 * Secondary High Term Enable = BRDDAT6
1638 * Secondary Low Term Enable = BRDDAT5 (7890)
1639 * Primary High Term Enable = BRDDAT4 (7890)
1640 */
1641 if ((ahc->features & AHC_ULTRA2) == 0
1642 && (internal50_present != 0)
1643 && (internal68_present != 0)
1644 && (externalcable_present != 0)) {
1645 printf("%s: Illegal cable configuration!!. "
1646 "Only two connectors on the "
1647 "adapter may be used at a "
1648 "time!\n", ahc_name(ahc));
1649
1650 /*
1651 * Pretend there are no cables in the hope
1652 * that having all of the termination on
1653 * gives us a more stable bus.
1654 */
1655 internal50_present = 0;
1656 internal68_present = 0;
1657 externalcable_present = 0;
1658 }
1659
1660 if ((ahc->features & AHC_WIDE) != 0
1661 && ((externalcable_present == 0)
1662 || (internal68_present == 0)
1663 || (enableSEC_high != 0))) {
1664 brddat |= BRDDAT6;
1665 if (bootverbose) {
1666 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1667 printf("%s: 68 pin termination "
1668 "Enabled\n", ahc_name(ahc));
1669 else
1670 printf("%s: %sHigh byte termination "
1671 "Enabled\n", ahc_name(ahc),
1672 enableSEC_high ? "Secondary "
1673 : "");
1674 }
1675 }
1676
1677 sum = internal50_present + internal68_present
1678 + externalcable_present;
1679 if (sum < 2 || (enableSEC_low != 0)) {
1680 if ((ahc->features & AHC_ULTRA2) != 0)
1681 brddat |= BRDDAT5;
1682 else
1683 *sxfrctl1 |= STPWEN;
1684 if (bootverbose) {
1685 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1686 printf("%s: 50 pin termination "
1687 "Enabled\n", ahc_name(ahc));
1688 else
1689 printf("%s: %sLow byte termination "
1690 "Enabled\n", ahc_name(ahc),
1691 enableSEC_low ? "Secondary "
1692 : "");
1693 }
1694 }
1695
1696 if (enablePRI_low != 0) {
1697 *sxfrctl1 |= STPWEN;
1698 if (bootverbose)
1699 printf("%s: Primary Low Byte termination "
1700 "Enabled\n", ahc_name(ahc));
1701 }
1702
1703 /*
1704 * Setup STPWEN before setting up the rest of
1705 * the termination per the tech note on the U160 cards.
1706 */
1707 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1708
1709 if (enablePRI_high != 0) {
1710 brddat |= BRDDAT4;
1711 if (bootverbose)
1712 printf("%s: Primary High Byte "
1713 "termination Enabled\n",
1714 ahc_name(ahc));
1715 }
1716
1717 write_brdctl(ahc, brddat);
1718
1719 } else {
1720 if ((adapter_control & CFSTERM) != 0) {
1721 *sxfrctl1 |= STPWEN;
1722
1723 if (bootverbose)
1724 printf("%s: %sLow byte termination Enabled\n",
1725 ahc_name(ahc),
1726 (ahc->features & AHC_ULTRA2) ? "Primary "
1727 : "");
1728 }
1729
1730 if ((adapter_control & CFWSTERM) != 0
1731 && (ahc->features & AHC_WIDE) != 0) {
1732 brddat |= BRDDAT6;
1733 if (bootverbose)
1734 printf("%s: %sHigh byte termination Enabled\n",
1735 ahc_name(ahc),
1736 (ahc->features & AHC_ULTRA2)
1737 ? "Secondary " : "");
1738 }
1739
1740 /*
1741 * Setup STPWEN before setting up the rest of
1742 * the termination per the tech note on the U160 cards.
1743 */
1744 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1745
1746 if ((ahc->features & AHC_WIDE) != 0)
1747 write_brdctl(ahc, brddat);
1748 }
1749 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1750}
1751
1752static void
1753ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1754 int *enableSEC_high, int *enablePRI_low,
1755 int *enablePRI_high, int *eeprom_present)
1756{
1757 uint8_t brdctl;
1758
1759 /*
1760 * BRDDAT7 = Eeprom
1761 * BRDDAT6 = Enable Secondary High Byte termination
1762 * BRDDAT5 = Enable Secondary Low Byte termination
1763 * BRDDAT4 = Enable Primary high byte termination
1764 * BRDDAT3 = Enable Primary low byte termination
1765 */
1766 brdctl = read_brdctl(ahc);
1767 *eeprom_present = brdctl & BRDDAT7;
1768 *enableSEC_high = (brdctl & BRDDAT6);
1769 *enableSEC_low = (brdctl & BRDDAT5);
1770 *enablePRI_high = (brdctl & BRDDAT4);
1771 *enablePRI_low = (brdctl & BRDDAT3);
1772}
1773
1774static void
1775aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1776 int *internal68_present, int *externalcable_present,
1777 int *eeprom_present)
1778{
1779 uint8_t brdctl;
1780
1781 /*
1782 * First read the status of our cables.
1783 * Set the rom bank to 0 since the
1784 * bank setting serves as a multiplexor
1785 * for the cable detection logic.
1786 * BRDDAT5 controls the bank switch.
1787 */
1788 write_brdctl(ahc, 0);
1789
1790 /*
1791 * Now read the state of the internal
1792 * connectors. BRDDAT6 is INT50 and
1793 * BRDDAT7 is INT68.
1794 */
1795 brdctl = read_brdctl(ahc);
1796 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1797 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1798
1799 /*
1800 * Set the rom bank to 1 and determine
1801 * the other signals.
1802 */
1803 write_brdctl(ahc, BRDDAT5);
1804
1805 /*
1806 * Now read the state of the external
1807 * connectors. BRDDAT6 is EXT68 and
1808 * BRDDAT7 is EPROMPS.
1809 */
1810 brdctl = read_brdctl(ahc);
1811 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1812 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1813}
1814
1815static void
1816aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1817 int *externalcable_present, int *eeprom_present)
1818{
1819 uint8_t brdctl;
1820 uint8_t spiocap;
1821
1822 spiocap = ahc_inb(ahc, SPIOCAP);
1823 spiocap &= ~SOFTCMDEN;
1824 spiocap |= EXT_BRDCTL;
1825 ahc_outb(ahc, SPIOCAP, spiocap);
1826 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1827 ahc_flush_device_writes(ahc);
1828 ahc_delay(500);
1829 ahc_outb(ahc, BRDCTL, 0);
1830 ahc_flush_device_writes(ahc);
1831 ahc_delay(500);
1832 brdctl = ahc_inb(ahc, BRDCTL);
1833 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1834 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1835 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1836}
1837
1838int
1839ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1840{
1841 int wait;
1842
1843 if ((ahc->features & AHC_SPIOCAP) != 0
1844 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1845 return (0);
1846
1847 /*
1848 * Request access of the memory port. When access is
1849 * granted, SEERDY will go high. We use a 1 second
1850 * timeout which should be near 1 second more than
1851 * is needed. Reason: after the chip reset, there
1852 * should be no contention.
1853 */
1854 SEEPROM_OUTB(sd, sd->sd_MS);
1855 wait = 1000; /* 1 second timeout in msec */
1856 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1857 ahc_delay(1000); /* delay 1 msec */
1858 }
1859 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1860 SEEPROM_OUTB(sd, 0);
1861 return (0);
1862 }
1863 return(1);
1864}
1865
1866void
1867ahc_release_seeprom(struct seeprom_descriptor *sd)
1868{
1869 /* Release access to the memory port and the serial EEPROM. */
1870 SEEPROM_OUTB(sd, 0);
1871}
1872
1873static void
1874write_brdctl(struct ahc_softc *ahc, uint8_t value)
1875{
1876 uint8_t brdctl;
1877
1878 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1879 brdctl = BRDSTB;
1880 if (ahc->channel == 'B')
1881 brdctl |= BRDCS;
1882 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1883 brdctl = 0;
1884 } else {
1885 brdctl = BRDSTB|BRDCS;
1886 }
1887 ahc_outb(ahc, BRDCTL, brdctl);
1888 ahc_flush_device_writes(ahc);
1889 brdctl |= value;
1890 ahc_outb(ahc, BRDCTL, brdctl);
1891 ahc_flush_device_writes(ahc);
1892 if ((ahc->features & AHC_ULTRA2) != 0)
1893 brdctl |= BRDSTB_ULTRA2;
1894 else
1895 brdctl &= ~BRDSTB;
1896 ahc_outb(ahc, BRDCTL, brdctl);
1897 ahc_flush_device_writes(ahc);
1898 if ((ahc->features & AHC_ULTRA2) != 0)
1899 brdctl = 0;
1900 else
1901 brdctl &= ~BRDCS;
1902 ahc_outb(ahc, BRDCTL, brdctl);
1903}
1904
1905static uint8_t
1906read_brdctl(struct ahc_softc *ahc)
1907{
1908 uint8_t brdctl;
1909 uint8_t value;
1910
1911 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1912 brdctl = BRDRW;
1913 if (ahc->channel == 'B')
1914 brdctl |= BRDCS;
1915 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1916 brdctl = BRDRW_ULTRA2;
1917 } else {
1918 brdctl = BRDRW|BRDCS;
1919 }
1920 ahc_outb(ahc, BRDCTL, brdctl);
1921 ahc_flush_device_writes(ahc);
1922 value = ahc_inb(ahc, BRDCTL);
1923 ahc_outb(ahc, BRDCTL, 0);
1924 return (value);
1925}
1926
1927static void
1928ahc_pci_intr(struct ahc_softc *ahc)
1929{
1930 u_int error;
1931 u_int status1;
1932
1933 error = ahc_inb(ahc, ERROR);
1934 if ((error & PCIERRSTAT) == 0)
1935 return;
1936
1937 status1 = ahc_pci_read_config(ahc->dev_softc,
1938 PCIR_STATUS + 1, /*bytes*/1);
1939
1940 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
1941 ahc_name(ahc),
1942 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
1943
1944 if (status1 & DPE) {
1945 ahc->pci_target_perr_count++;
1946 printf("%s: Data Parity Error Detected during address "
1947 "or write data phase\n", ahc_name(ahc));
1948 }
1949 if (status1 & SSE) {
1950 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
1951 }
1952 if (status1 & RMA) {
1953 printf("%s: Received a Master Abort\n", ahc_name(ahc));
1954 }
1955 if (status1 & RTA) {
1956 printf("%s: Received a Target Abort\n", ahc_name(ahc));
1957 }
1958 if (status1 & STA) {
1959 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
1960 }
1961 if (status1 & DPR) {
1962 printf("%s: Data Parity Error has been reported via PERR#\n",
1963 ahc_name(ahc));
1964 }
1965
1966 /* Clear latched errors. */
1967 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1968 status1, /*bytes*/1);
1969
1970 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
1971 printf("%s: Latched PCIERR interrupt with "
1972 "no status bits set\n", ahc_name(ahc));
1973 } else {
1974 ahc_outb(ahc, CLRINT, CLRPARERR);
1975 }
1976
1977 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) {
1978 printf(
1979"%s: WARNING WARNING WARNING WARNING\n"
1980"%s: Too many PCI parity errors observed as a target.\n"
1981"%s: Some device on this bus is generating bad parity.\n"
1982"%s: This is an error *observed by*, not *generated by*, this controller.\n"
1983"%s: PCI parity error checking has been disabled.\n"
1984"%s: WARNING WARNING WARNING WARNING\n",
1985 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
1986 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc));
1987 ahc->seqctl |= FAILDIS;
1988 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1989 }
1990 ahc_unpause(ahc);
1991}
1992
1993static int
1994ahc_pci_chip_init(struct ahc_softc *ahc)
1995{
1996 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
1997 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
1998 if ((ahc->features & AHC_DT) != 0) {
1999 u_int sfunct;
2000
2001 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2002 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2003 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2004 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2005 ahc_outb(ahc, SFUNCT, sfunct);
2006 ahc_outb(ahc, CRCCONTROL1,
2007 ahc->bus_softc.pci_softc.crccontrol1);
2008 }
2009 if ((ahc->features & AHC_MULTI_FUNC) != 0)
2010 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2011
2012 if ((ahc->features & AHC_ULTRA2) != 0)
2013 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2014
2015 return (ahc_chip_init(ahc));
2016}
2017
03e7925d 2018#ifdef CONFIG_PM
b5720729 2019void
1da177e4
LT		 2020ahc_pci_resume(struct ahc_softc *ahc)
2021{
1da177e4
LT		 2022 /*
2023 * We assume that the OS has restored our register
2024 * mappings, etc. Just update the config space registers
2025 * that the OS doesn't know about and rely on our chip
2026 * reset handler to handle the rest.
2027 */
c42bcefb
DV		 2028 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
2029 ahc->bus_softc.pci_softc.devconfig, /*bytes*/4);
2030 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
2031 ahc->bus_softc.pci_softc.command, /*bytes*/1);
2032 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
2033 ahc->bus_softc.pci_softc.csize_lattime, /*bytes*/1);
1da177e4
LT		 2034 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2035 struct seeprom_descriptor sd;
2036 u_int sxfrctl1;
2037
2038 sd.sd_ahc = ahc;
2039 sd.sd_control_offset = SEECTL;
2040 sd.sd_status_offset = SEECTL;
2041 sd.sd_dataout_offset = SEECTL;
2042
2043 ahc_acquire_seeprom(ahc, &sd);
2044 configure_termination(ahc, &sd,
2045 ahc->seep_config->adapter_control,
2046 &sxfrctl1);
2047 ahc_release_seeprom(&sd);
2048 }
1da177e4 2049}
03e7925d 2050#endif
1da177e4
LT		 2051
2052static int
2053ahc_aic785X_setup(struct ahc_softc *ahc)
2054{
2055 ahc_dev_softc_t pci;
2056 uint8_t rev;
2057
2058 pci = ahc->dev_softc;
2059 ahc->channel = 'A';
2060 ahc->chip = AHC_AIC7850;
2061 ahc->features = AHC_AIC7850_FE;
2062 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2063 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2064 if (rev >= 1)
2065 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2066 ahc->instruction_ram_size = 512;
2067 return (0);
2068}
2069
2070static int
2071ahc_aic7860_setup(struct ahc_softc *ahc)
2072{
2073 ahc_dev_softc_t pci;
2074 uint8_t rev;
2075
2076 pci = ahc->dev_softc;
2077 ahc->channel = 'A';
2078 ahc->chip = AHC_AIC7860;
2079 ahc->features = AHC_AIC7860_FE;
2080 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2081 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2082 if (rev >= 1)
2083 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2084 ahc->instruction_ram_size = 512;
2085 return (0);
2086}
2087
2088static int
2089ahc_apa1480_setup(struct ahc_softc *ahc)
2090{
2091 int error;
2092
2093 error = ahc_aic7860_setup(ahc);
2094 if (error != 0)
2095 return (error);
2096 ahc->features |= AHC_REMOVABLE;
2097 return (0);
2098}
2099
2100static int
2101ahc_aic7870_setup(struct ahc_softc *ahc)
2102{
2103
2104 ahc->channel = 'A';
2105 ahc->chip = AHC_AIC7870;
2106 ahc->features = AHC_AIC7870_FE;
2107 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2108 ahc->instruction_ram_size = 512;
2109 return (0);
2110}
2111
b2d8bfe1
JB		 2112static int
2113ahc_aic7870h_setup(struct ahc_softc *ahc)
2114{
2115 int error = ahc_aic7870_setup(ahc);
2116
2117 ahc->features |= AHC_HVD;
2118
2119 return error;
2120}
2121
1da177e4
LT		 2122static int
2123ahc_aha394X_setup(struct ahc_softc *ahc)
2124{
2125 int error;
2126
2127 error = ahc_aic7870_setup(ahc);
2128 if (error == 0)
2129 error = ahc_aha394XX_setup(ahc);
2130 return (error);
2131}
2132
b2d8bfe1
JB		 2133static int
2134ahc_aha394Xh_setup(struct ahc_softc *ahc)
2135{
2136 int error = ahc_aha394X_setup(ahc);
2137
2138 ahc->features |= AHC_HVD;
2139
2140 return error;
2141}
2142
1da177e4
LT		 2143static int
2144ahc_aha398X_setup(struct ahc_softc *ahc)
2145{
2146 int error;
2147
2148 error = ahc_aic7870_setup(ahc);
2149 if (error == 0)
2150 error = ahc_aha398XX_setup(ahc);
2151 return (error);
2152}
2153
2154static int
2155ahc_aha494X_setup(struct ahc_softc *ahc)
2156{
2157 int error;
2158
2159 error = ahc_aic7870_setup(ahc);
2160 if (error == 0)
2161 error = ahc_aha494XX_setup(ahc);
2162 return (error);
2163}
2164
b2d8bfe1
JB		 2165static int
2166ahc_aha494Xh_setup(struct ahc_softc *ahc)
2167{
2168 int error = ahc_aha494X_setup(ahc);
2169
2170 ahc->features |= AHC_HVD;
2171
2172 return error;
2173}
2174
1da177e4
LT		 2175static int
2176ahc_aic7880_setup(struct ahc_softc *ahc)
2177{
2178 ahc_dev_softc_t pci;
2179 uint8_t rev;
2180
2181 pci = ahc->dev_softc;
2182 ahc->channel = 'A';
2183 ahc->chip = AHC_AIC7880;
2184 ahc->features = AHC_AIC7880_FE;
2185 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2186 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2187 if (rev >= 1) {
2188 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2189 } else {
2190 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2191 }
2192 ahc->instruction_ram_size = 512;
2193 return (0);
2194}
2195
b2d8bfe1
JB		 2196static int
2197ahc_aic7880h_setup(struct ahc_softc *ahc)
2198{
2199 int error = ahc_aic7880_setup(ahc);
2200
2201 ahc->features |= AHC_HVD;
2202
2203 return error;
2204}
2205
2206
1da177e4
LT		 2207static int
2208ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2209{
2210
2211 ahc->flags |= AHC_INT50_SPEEDFLEX;
2212 return (ahc_aic7880_setup(ahc));
2213}
2214
2215static int
2216ahc_aha394XU_setup(struct ahc_softc *ahc)
2217{
2218 int error;
2219
2220 error = ahc_aic7880_setup(ahc);
2221 if (error == 0)
2222 error = ahc_aha394XX_setup(ahc);
2223 return (error);
2224}
2225
b2d8bfe1
JB		 2226static int
2227ahc_aha394XUh_setup(struct ahc_softc *ahc)
2228{
2229 int error = ahc_aha394XU_setup(ahc);
2230
2231 ahc->features |= AHC_HVD;
2232
2233 return error;
2234}
2235
1da177e4
LT		 2236static int
2237ahc_aha398XU_setup(struct ahc_softc *ahc)
2238{
2239 int error;
2240
2241 error = ahc_aic7880_setup(ahc);
2242 if (error == 0)
2243 error = ahc_aha398XX_setup(ahc);
2244 return (error);
2245}
2246
2247static int
2248ahc_aic7890_setup(struct ahc_softc *ahc)
2249{
2250 ahc_dev_softc_t pci;
2251 uint8_t rev;
2252
2253 pci = ahc->dev_softc;
2254 ahc->channel = 'A';
2255 ahc->chip = AHC_AIC7890;
2256 ahc->features = AHC_AIC7890_FE;
2257 ahc->flags |= AHC_NEWEEPROM_FMT;
2258 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2259 if (rev == 0)
2260 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2261 ahc->instruction_ram_size = 768;
2262 return (0);
2263}
2264
2265static int
2266ahc_aic7892_setup(struct ahc_softc *ahc)
2267{
2268
2269 ahc->channel = 'A';
2270 ahc->chip = AHC_AIC7892;
2271 ahc->features = AHC_AIC7892_FE;
2272 ahc->flags |= AHC_NEWEEPROM_FMT;
2273 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2274 ahc->instruction_ram_size = 1024;
2275 return (0);
2276}
2277
2278static int
2279ahc_aic7895_setup(struct ahc_softc *ahc)
2280{
2281 ahc_dev_softc_t pci;
2282 uint8_t rev;
2283
2284 pci = ahc->dev_softc;
2285 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2286 /*
2287 * The 'C' revision of the aic7895 has a few additional features.
2288 */
2289 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2290 if (rev >= 4) {
2291 ahc->chip = AHC_AIC7895C;
2292 ahc->features = AHC_AIC7895C_FE;
2293 } else {
2294 u_int command;
2295
2296 ahc->chip = AHC_AIC7895;
2297 ahc->features = AHC_AIC7895_FE;
2298
2299 /*
2300 * The BIOS disables the use of MWI transactions
2301 * since it does not have the MWI bug work around
2302 * we have. Disabling MWI reduces performance, so
2303 * turn it on again.
2304 */
2305 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2306 command |= PCIM_CMD_MWRICEN;
2307 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2308 ahc->bugs |= AHC_PCI_MWI_BUG;
2309 }
2310 /*
2311 * XXX Does CACHETHEN really not work??? What about PCI retry?
2312 * on C level chips. Need to test, but for now, play it safe.
2313 */
2314 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2315 | AHC_CACHETHEN_BUG;
2316
2317#if 0
2318 uint32_t devconfig;
2319
2320 /*
2321 * Cachesize must also be zero due to stray DAC
2322 * problem when sitting behind some bridges.
2323 */
2324 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2325 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2326 devconfig |= MRDCEN;
2327 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2328#endif
2329 ahc->flags |= AHC_NEWEEPROM_FMT;
2330 ahc->instruction_ram_size = 512;
2331 return (0);
2332}
2333
b2d8bfe1
JB		 2334static int
2335ahc_aic7895h_setup(struct ahc_softc *ahc)
2336{
2337 int error = ahc_aic7895_setup(ahc);
2338
2339 ahc->features |= AHC_HVD;
2340
2341 return error;
2342}
2343
1da177e4
LT		 2344static int
2345ahc_aic7896_setup(struct ahc_softc *ahc)
2346{
2347 ahc_dev_softc_t pci;
2348
2349 pci = ahc->dev_softc;
2350 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2351 ahc->chip = AHC_AIC7896;
2352 ahc->features = AHC_AIC7896_FE;
2353 ahc->flags |= AHC_NEWEEPROM_FMT;
2354 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2355 ahc->instruction_ram_size = 768;
2356 return (0);
2357}
2358
2359static int
2360ahc_aic7899_setup(struct ahc_softc *ahc)
2361{
2362 ahc_dev_softc_t pci;
2363
2364 pci = ahc->dev_softc;
2365 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2366 ahc->chip = AHC_AIC7899;
2367 ahc->features = AHC_AIC7899_FE;
2368 ahc->flags |= AHC_NEWEEPROM_FMT;
2369 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2370 ahc->instruction_ram_size = 1024;
2371 return (0);
2372}
2373
2374static int
2375ahc_aha29160C_setup(struct ahc_softc *ahc)
2376{
2377 int error;
2378
2379 error = ahc_aic7899_setup(ahc);
2380 if (error != 0)
2381 return (error);
2382 ahc->features |= AHC_REMOVABLE;
2383 return (0);
2384}
2385
2386static int
2387ahc_raid_setup(struct ahc_softc *ahc)
2388{
2389 printf("RAID functionality unsupported\n");
2390 return (ENXIO);
2391}
2392
2393static int
2394ahc_aha394XX_setup(struct ahc_softc *ahc)
2395{
2396 ahc_dev_softc_t pci;
2397
2398 pci = ahc->dev_softc;
2399 switch (ahc_get_pci_slot(pci)) {
2400 case AHC_394X_SLOT_CHANNEL_A:
2401 ahc->channel = 'A';
2402 break;
2403 case AHC_394X_SLOT_CHANNEL_B:
2404 ahc->channel = 'B';
2405 break;
2406 default:
2407 printf("adapter at unexpected slot %d\n"
2408 "unable to map to a channel\n",
2409 ahc_get_pci_slot(pci));
2410 ahc->channel = 'A';
2411 }
2412 return (0);
2413}
2414
2415static int
2416ahc_aha398XX_setup(struct ahc_softc *ahc)
2417{
2418 ahc_dev_softc_t pci;
2419
2420 pci = ahc->dev_softc;
2421 switch (ahc_get_pci_slot(pci)) {
2422 case AHC_398X_SLOT_CHANNEL_A:
2423 ahc->channel = 'A';
2424 break;
2425 case AHC_398X_SLOT_CHANNEL_B:
2426 ahc->channel = 'B';
2427 break;
2428 case AHC_398X_SLOT_CHANNEL_C:
2429 ahc->channel = 'C';
2430 break;
2431 default:
2432 printf("adapter at unexpected slot %d\n"
2433 "unable to map to a channel\n",
2434 ahc_get_pci_slot(pci));
2435 ahc->channel = 'A';
2436 break;
2437 }
2438 ahc->flags |= AHC_LARGE_SEEPROM;
2439 return (0);
2440}
2441
2442static int
2443ahc_aha494XX_setup(struct ahc_softc *ahc)
2444{
2445 ahc_dev_softc_t pci;
2446
2447 pci = ahc->dev_softc;
2448 switch (ahc_get_pci_slot(pci)) {
2449 case AHC_494X_SLOT_CHANNEL_A:
2450 ahc->channel = 'A';
2451 break;
2452 case AHC_494X_SLOT_CHANNEL_B:
2453 ahc->channel = 'B';
2454 break;
2455 case AHC_494X_SLOT_CHANNEL_C:
2456 ahc->channel = 'C';
2457 break;
2458 case AHC_494X_SLOT_CHANNEL_D:
2459 ahc->channel = 'D';
2460 break;
2461 default:
2462 printf("adapter at unexpected slot %d\n"
2463 "unable to map to a channel\n",
2464 ahc_get_pci_slot(pci));
2465 ahc->channel = 'A';
2466 }
2467 ahc->flags |= AHC_LARGE_SEEPROM;
2468 return (0);
2469}
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