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[PATCH] ahci: kill pp->cmd_tbl_sg
[net-next-2.6.git] / drivers / scsi / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
87507cfd 43#include <linux/dma-mapping.h>
a9524a76 44#include <linux/device.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4
LT		 47#include <linux/libata.h>
48#include <asm/io.h>
49
50#define DRV_NAME "ahci"
af64371a 51#define DRV_VERSION "1.3"
1da177e4
LT		 52
53
54enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
dd410ff1
TH		 59 AHCI_MAX_CMDS = 1,
60 AHCI_CMD_SZ = 32,
61 AHCI_CMD_SLOT_SZ = 32 * AHCI_CMD_SZ,
1da177e4 62 AHCI_RX_FIS_SZ = 256,
a0ea7328 63 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 68 AHCI_RX_FIS_SZ,
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
4b10e559 72 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 75
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
78cd52d0 77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 78
79 board_ahci = 0,
bf2af2a2 80 board_ahci_vt8251 = 1,
1da177e4
LT		 81
82 /* global controller registers */
83 HOST_CAP = 0x00, /* host capabilities */
84 HOST_CTL = 0x04, /* global host control */
85 HOST_IRQ_STAT = 0x08, /* interrupt status */
86 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
87 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
88
89 /* HOST_CTL bits */
90 HOST_RESET = (1 << 0), /* reset controller; self-clear */
91 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
92 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
93
94 /* HOST_CAP bits */
22b49985 95 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
979db803 96 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 97 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 98
99 /* registers for each SATA port */
100 PORT_LST_ADDR = 0x00, /* command list DMA addr */
101 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
102 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
103 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
104 PORT_IRQ_STAT = 0x10, /* interrupt status */
105 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
106 PORT_CMD = 0x18, /* port command */
107 PORT_TFDATA = 0x20, /* taskfile data */
108 PORT_SIG = 0x24, /* device TF signature */
109 PORT_CMD_ISSUE = 0x38, /* command issue */
110 PORT_SCR = 0x28, /* SATA phy register block */
111 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
112 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
113 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
114 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
115
116 /* PORT_IRQ_{STAT,MASK} bits */
117 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
118 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
119 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
120 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
121 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
122 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
123 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
124 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
125
126 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
127 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
128 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
129 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
130 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
131 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
132 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
133 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
134 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
135
78cd52d0
TH		 136 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
137 PORT_IRQ_IF_ERR |
138 PORT_IRQ_CONNECT |
139 PORT_IRQ_UNK_FIS,
140 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
141 PORT_IRQ_TF_ERR |
142 PORT_IRQ_HBUS_DATA_ERR,
143 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
144 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
145 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 146
147 /* PORT_CMD bits */
02eaa666 148 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
1da177e4
LT		 149 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
150 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
151 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 152 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 153 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
154 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
155 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
156
157 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
158 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
159 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4
JG		 160
161 /* hpriv->flags bits */
162 AHCI_FLAG_MSI = (1 << 0),
bf2af2a2
BJ		 163
164 /* ap->flags bits */
165 AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
1da177e4
LT		 166};
167
168struct ahci_cmd_hdr {
169 u32 opts;
170 u32 status;
171 u32 tbl_addr;
172 u32 tbl_addr_hi;
173 u32 reserved[4];
174};
175
176struct ahci_sg {
177 u32 addr;
178 u32 addr_hi;
179 u32 reserved;
180 u32 flags_size;
181};
182
183struct ahci_host_priv {
184 unsigned long flags;
185 u32 cap; /* cache of HOST_CAP register */
186 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
187};
188
189struct ahci_port_priv {
190 struct ahci_cmd_hdr *cmd_slot;
191 dma_addr_t cmd_slot_dma;
192 void *cmd_tbl;
193 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 194 void *rx_fis;
195 dma_addr_t rx_fis_dma;
196};
197
198static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
199static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
200static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 201static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4 202static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
4bd00f6a 203static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes);
1da177e4 204static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 205static int ahci_port_start(struct ata_port *ap);
206static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 207static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
208static void ahci_qc_prep(struct ata_queued_cmd *qc);
209static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 210static void ahci_freeze(struct ata_port *ap);
211static void ahci_thaw(struct ata_port *ap);
212static void ahci_error_handler(struct ata_port *ap);
213static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
907f4678 214static void ahci_remove_one (struct pci_dev *pdev);
1da177e4 215
193515d5 216static struct scsi_host_template ahci_sht = {
1da177e4
LT		 217 .module = THIS_MODULE,
218 .name = DRV_NAME,
219 .ioctl = ata_scsi_ioctl,
220 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 221 .can_queue = ATA_DEF_QUEUE,
222 .this_id = ATA_SHT_THIS_ID,
223 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 224 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
225 .emulated = ATA_SHT_EMULATED,
226 .use_clustering = AHCI_USE_CLUSTERING,
227 .proc_name = DRV_NAME,
228 .dma_boundary = AHCI_DMA_BOUNDARY,
229 .slave_configure = ata_scsi_slave_config,
230 .bios_param = ata_std_bios_param,
1da177e4
LT		 231};
232
057ace5e 233static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 234 .port_disable = ata_port_disable,
235
236 .check_status = ahci_check_status,
237 .check_altstatus = ahci_check_status,
1da177e4
LT		 238 .dev_select = ata_noop_dev_select,
239
240 .tf_read = ahci_tf_read,
241
4bd00f6a 242 .probe_reset = ahci_probe_reset,
1da177e4
LT		 243
244 .qc_prep = ahci_qc_prep,
245 .qc_issue = ahci_qc_issue,
246
1da177e4
LT		 247 .irq_handler = ahci_interrupt,
248 .irq_clear = ahci_irq_clear,
249
250 .scr_read = ahci_scr_read,
251 .scr_write = ahci_scr_write,
252
78cd52d0
TH		 253 .freeze = ahci_freeze,
254 .thaw = ahci_thaw,
255
256 .error_handler = ahci_error_handler,
257 .post_internal_cmd = ahci_post_internal_cmd,
258
1da177e4
LT		 259 .port_start = ahci_port_start,
260 .port_stop = ahci_port_stop,
1da177e4
LT		 261};
262
98ac62de 263static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 264 /* board_ahci */
265 {
266 .sht = &ahci_sht,
267 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
4bd00f6a 268 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
7da79312 269 .pio_mask = 0x1f, /* pio0-4 */
1da177e4
LT		 270 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
271 .port_ops = &ahci_ops,
272 },
bf2af2a2
BJ		 273 /* board_ahci_vt8251 */
274 {
275 .sht = &ahci_sht,
276 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
277 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
278 AHCI_FLAG_RESET_NEEDS_CLO,
279 .pio_mask = 0x1f, /* pio0-4 */
280 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
281 .port_ops = &ahci_ops,
282 },
1da177e4
LT		 283};
284
3b7d697d 285static const struct pci_device_id ahci_pci_tbl[] = {
1da177e4
LT		 286 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
287 board_ahci }, /* ICH6 */
288 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
289 board_ahci }, /* ICH6M */
290 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
291 board_ahci }, /* ICH7 */
292 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
293 board_ahci }, /* ICH7M */
294 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
295 board_ahci }, /* ICH7R */
296 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
297 board_ahci }, /* ULi M5288 */
680d3235
JG		 298 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
299 board_ahci }, /* ESB2 */
300 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
301 board_ahci }, /* ESB2 */
302 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
303 board_ahci }, /* ESB2 */
3db368f7
JG		 304 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
305 board_ahci }, /* ICH7-M DH */
f285757c
JG		 306 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
307 board_ahci }, /* ICH8 */
308 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
309 board_ahci }, /* ICH8 */
310 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
311 board_ahci }, /* ICH8 */
312 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
313 board_ahci }, /* ICH8M */
314 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
315 board_ahci }, /* ICH8M */
bd12097c
JG		 316 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
317 board_ahci }, /* JMicron JMB360 */
9220a2d0
JG		 318 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
319 board_ahci }, /* JMicron JMB363 */
8b316a39
JG		 320 { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
321 board_ahci }, /* ATI SB600 non-raid */
322 { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
323 board_ahci }, /* ATI SB600 raid */
bf2af2a2
BJ		 324 { PCI_VENDOR_ID_VIA, 0x3349, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
325 board_ahci_vt8251 }, /* VIA VT8251 */
1da177e4
LT		 326 { } /* terminate list */
327};
328
329
330static struct pci_driver ahci_pci_driver = {
331 .name = DRV_NAME,
332 .id_table = ahci_pci_tbl,
333 .probe = ahci_init_one,
907f4678 334 .remove = ahci_remove_one,
1da177e4
LT		 335};
336
337
338static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
339{
340 return base + 0x100 + (port * 0x80);
341}
342
ea6ba10b 343static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
1da177e4 344{
ea6ba10b 345 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
1da177e4
LT		 346}
347
1da177e4
LT		 348static int ahci_port_start(struct ata_port *ap)
349{
350 struct device *dev = ap->host_set->dev;
351 struct ahci_host_priv *hpriv = ap->host_set->private_data;
352 struct ahci_port_priv *pp;
ea6ba10b
JG		 353 void __iomem *mmio = ap->host_set->mmio_base;
354 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
355 void *mem;
1da177e4 356 dma_addr_t mem_dma;
6037d6bb 357 int rc;
1da177e4 358
1da177e4 359 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
0a139e79
TH		 360 if (!pp)
361 return -ENOMEM;
1da177e4
LT		 362 memset(pp, 0, sizeof(*pp));
363
6037d6bb
JG		 364 rc = ata_pad_alloc(ap, dev);
365 if (rc) {
cedc9a47 366 kfree(pp);
6037d6bb 367 return rc;
cedc9a47
JG		 368 }
369
1da177e4
LT		 370 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
371 if (!mem) {
6037d6bb 372 ata_pad_free(ap, dev);
0a139e79
TH		 373 kfree(pp);
374 return -ENOMEM;
1da177e4
LT		 375 }
376 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
377
378 /*
379 * First item in chunk of DMA memory: 32-slot command table,
380 * 32 bytes each in size
381 */
382 pp->cmd_slot = mem;
383 pp->cmd_slot_dma = mem_dma;
384
385 mem += AHCI_CMD_SLOT_SZ;
386 mem_dma += AHCI_CMD_SLOT_SZ;
387
388 /*
389 * Second item: Received-FIS area
390 */
391 pp->rx_fis = mem;
392 pp->rx_fis_dma = mem_dma;
393
394 mem += AHCI_RX_FIS_SZ;
395 mem_dma += AHCI_RX_FIS_SZ;
396
397 /*
398 * Third item: data area for storing a single command
399 * and its scatter-gather table
400 */
401 pp->cmd_tbl = mem;
402 pp->cmd_tbl_dma = mem_dma;
403
1da177e4
LT		 404 ap->private_data = pp;
405
406 if (hpriv->cap & HOST_CAP_64)
407 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
408 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
409 readl(port_mmio + PORT_LST_ADDR); /* flush */
410
411 if (hpriv->cap & HOST_CAP_64)
412 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
413 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
414 readl(port_mmio + PORT_FIS_ADDR); /* flush */
415
416 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
417 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
418 PORT_CMD_START, port_mmio + PORT_CMD);
419 readl(port_mmio + PORT_CMD); /* flush */
420
421 return 0;
1da177e4
LT		 422}
423
424
425static void ahci_port_stop(struct ata_port *ap)
426{
427 struct device *dev = ap->host_set->dev;
428 struct ahci_port_priv *pp = ap->private_data;
ea6ba10b
JG		 429 void __iomem *mmio = ap->host_set->mmio_base;
430 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4
LT		 431 u32 tmp;
432
433 tmp = readl(port_mmio + PORT_CMD);
434 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
435 writel(tmp, port_mmio + PORT_CMD);
436 readl(port_mmio + PORT_CMD); /* flush */
437
438 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
439 * this is slightly incorrect.
440 */
441 msleep(500);
442
443 ap->private_data = NULL;
444 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
445 pp->cmd_slot, pp->cmd_slot_dma);
6037d6bb 446 ata_pad_free(ap, dev);
1da177e4 447 kfree(pp);
1da177e4
LT		 448}
449
450static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
451{
452 unsigned int sc_reg;
453
454 switch (sc_reg_in) {
455 case SCR_STATUS: sc_reg = 0; break;
456 case SCR_CONTROL: sc_reg = 1; break;
457 case SCR_ERROR: sc_reg = 2; break;
458 case SCR_ACTIVE: sc_reg = 3; break;
459 default:
460 return 0xffffffffU;
461 }
462
1e4f2a96 463 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 464}
465
466
467static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
468 u32 val)
469{
470 unsigned int sc_reg;
471
472 switch (sc_reg_in) {
473 case SCR_STATUS: sc_reg = 0; break;
474 case SCR_CONTROL: sc_reg = 1; break;
475 case SCR_ERROR: sc_reg = 2; break;
476 case SCR_ACTIVE: sc_reg = 3; break;
477 default:
478 return;
479 }
480
1e4f2a96 481 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 482}
483
7c76d1e8
TH		 484static int ahci_stop_engine(struct ata_port *ap)
485{
486 void __iomem *mmio = ap->host_set->mmio_base;
487 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
488 int work;
489 u32 tmp;
490
491 tmp = readl(port_mmio + PORT_CMD);
492 tmp &= ~PORT_CMD_START;
493 writel(tmp, port_mmio + PORT_CMD);
494
495 /* wait for engine to stop. TODO: this could be
496 * as long as 500 msec
497 */
498 work = 1000;
499 while (work-- > 0) {
500 tmp = readl(port_mmio + PORT_CMD);
501 if ((tmp & PORT_CMD_LIST_ON) == 0)
502 return 0;
503 udelay(10);
504 }
505
506 return -EIO;
507}
508
509static void ahci_start_engine(struct ata_port *ap)
510{
511 void __iomem *mmio = ap->host_set->mmio_base;
512 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
513 u32 tmp;
514
515 tmp = readl(port_mmio + PORT_CMD);
516 tmp |= PORT_CMD_START;
517 writel(tmp, port_mmio + PORT_CMD);
518 readl(port_mmio + PORT_CMD); /* flush */
519}
520
422b7595 521static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4
LT		 522{
523 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
524 struct ata_taskfile tf;
422b7595
TH		 525 u32 tmp;
526
527 tmp = readl(port_mmio + PORT_SIG);
528 tf.lbah = (tmp >> 24) & 0xff;
529 tf.lbam = (tmp >> 16) & 0xff;
530 tf.lbal = (tmp >> 8) & 0xff;
531 tf.nsect = (tmp) & 0xff;
532
533 return ata_dev_classify(&tf);
534}
535
a42fc659 536static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts)
cc9278ed 537{
cc9278ed
TH		 538 pp->cmd_slot[0].opts = cpu_to_le32(opts);
539 pp->cmd_slot[0].status = 0;
540 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
541 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
542}
543
bf2af2a2 544static int ahci_clo(struct ata_port *ap)
4658f79b 545{
bf2af2a2 546 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
4658f79b 547 struct ahci_host_priv *hpriv = ap->host_set->private_data;
bf2af2a2
BJ		 548 u32 tmp;
549
550 if (!(hpriv->cap & HOST_CAP_CLO))
551 return -EOPNOTSUPP;
552
553 tmp = readl(port_mmio + PORT_CMD);
554 tmp |= PORT_CMD_CLO;
555 writel(tmp, port_mmio + PORT_CMD);
556
557 tmp = ata_wait_register(port_mmio + PORT_CMD,
558 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
559 if (tmp & PORT_CMD_CLO)
560 return -EIO;
561
562 return 0;
563}
564
565static int ahci_softreset(struct ata_port *ap, unsigned int *class)
566{
4658f79b
TH		 567 struct ahci_port_priv *pp = ap->private_data;
568 void __iomem *mmio = ap->host_set->mmio_base;
569 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
570 const u32 cmd_fis_len = 5; /* five dwords */
571 const char *reason = NULL;
572 struct ata_taskfile tf;
75fe1806 573 u32 tmp;
4658f79b
TH		 574 u8 *fis;
575 int rc;
576
577 DPRINTK("ENTER\n");
578
81952c54 579 if (ata_port_offline(ap)) {
c2a65852
TH		 580 DPRINTK("PHY reports no device\n");
581 *class = ATA_DEV_NONE;
582 return 0;
583 }
584
4658f79b
TH		 585 /* prepare for SRST (AHCI-1.1 10.4.1) */
586 rc = ahci_stop_engine(ap);
587 if (rc) {
588 reason = "failed to stop engine";
589 goto fail_restart;
590 }
591
592 /* check BUSY/DRQ, perform Command List Override if necessary */
593 ahci_tf_read(ap, &tf);
594 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
bf2af2a2 595 rc = ahci_clo(ap);
4658f79b 596
bf2af2a2
BJ		 597 if (rc == -EOPNOTSUPP) {
598 reason = "port busy but CLO unavailable";
599 goto fail_restart;
600 } else if (rc) {
601 reason = "port busy but CLO failed";
4658f79b
TH		 602 goto fail_restart;
603 }
604 }
605
606 /* restart engine */
607 ahci_start_engine(ap);
608
3373efd8 609 ata_tf_init(ap->device, &tf);
4658f79b
TH		 610 fis = pp->cmd_tbl;
611
612 /* issue the first D2H Register FIS */
613 ahci_fill_cmd_slot(pp, cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
614
615 tf.ctl |= ATA_SRST;
616 ata_tf_to_fis(&tf, fis, 0);
617 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
618
619 writel(1, port_mmio + PORT_CMD_ISSUE);
4658f79b 620
75fe1806
TH		 621 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
622 if (tmp & 0x1) {
4658f79b
TH		 623 rc = -EIO;
624 reason = "1st FIS failed";
625 goto fail;
626 }
627
628 /* spec says at least 5us, but be generous and sleep for 1ms */
629 msleep(1);
630
631 /* issue the second D2H Register FIS */
632 ahci_fill_cmd_slot(pp, cmd_fis_len);
633
634 tf.ctl &= ~ATA_SRST;
635 ata_tf_to_fis(&tf, fis, 0);
636 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
637
638 writel(1, port_mmio + PORT_CMD_ISSUE);
639 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
640
641 /* spec mandates ">= 2ms" before checking status.
642 * We wait 150ms, because that was the magic delay used for
643 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
644 * between when the ATA command register is written, and then
645 * status is checked. Because waiting for "a while" before
646 * checking status is fine, post SRST, we perform this magic
647 * delay here as well.
648 */
649 msleep(150);
650
651 *class = ATA_DEV_NONE;
81952c54 652 if (ata_port_online(ap)) {
4658f79b
TH		 653 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
654 rc = -EIO;
655 reason = "device not ready";
656 goto fail;
657 }
658 *class = ahci_dev_classify(ap);
659 }
660
661 DPRINTK("EXIT, class=%u\n", *class);
662 return 0;
663
664 fail_restart:
665 ahci_start_engine(ap);
666 fail:
f15a1daf 667 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 668 return rc;
669}
670
2bf2cb26 671static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
422b7595 672{
4bd00f6a
TH		 673 int rc;
674
675 DPRINTK("ENTER\n");
1da177e4 676
e0bfd149 677 ahci_stop_engine(ap);
2bf2cb26 678 rc = sata_std_hardreset(ap, class);
e0bfd149 679 ahci_start_engine(ap);
1da177e4 680
81952c54 681 if (rc == 0 && ata_port_online(ap))
4bd00f6a
TH		 682 *class = ahci_dev_classify(ap);
683 if (*class == ATA_DEV_UNKNOWN)
684 *class = ATA_DEV_NONE;
1da177e4 685
4bd00f6a
TH		 686 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
687 return rc;
688}
689
690static void ahci_postreset(struct ata_port *ap, unsigned int *class)
691{
692 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
693 u32 new_tmp, tmp;
694
695 ata_std_postreset(ap, class);
02eaa666
JG		 696
697 /* Make sure port's ATAPI bit is set appropriately */
698 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 699 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 700 new_tmp |= PORT_CMD_ATAPI;
701 else
702 new_tmp &= ~PORT_CMD_ATAPI;
703 if (new_tmp != tmp) {
704 writel(new_tmp, port_mmio + PORT_CMD);
705 readl(port_mmio + PORT_CMD); /* flush */
706 }
1da177e4
LT		 707}
708
4bd00f6a
TH		 709static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
710{
bf2af2a2
BJ		 711 if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) &&
712 (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) {
713 /* ATA_BUSY hasn't cleared, so send a CLO */
714 ahci_clo(ap);
715 }
716
4658f79b
TH		 717 return ata_drive_probe_reset(ap, ata_std_probeinit,
718 ahci_softreset, ahci_hardreset,
4bd00f6a
TH		 719 ahci_postreset, classes);
720}
721
1da177e4
LT		 722static u8 ahci_check_status(struct ata_port *ap)
723{
1e4f2a96 724 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4
LT		 725
726 return readl(mmio + PORT_TFDATA) & 0xFF;
727}
728
1da177e4
LT		 729static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
730{
731 struct ahci_port_priv *pp = ap->private_data;
732 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
733
734 ata_tf_from_fis(d2h_fis, tf);
735}
736
828d09de 737static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
1da177e4
LT		 738{
739 struct ahci_port_priv *pp = qc->ap->private_data;
cedc9a47
JG		 740 struct scatterlist *sg;
741 struct ahci_sg *ahci_sg;
828d09de 742 unsigned int n_sg = 0;
1da177e4
LT		 743
744 VPRINTK("ENTER\n");
745
746 /*
747 * Next, the S/G list.
748 */
a9764c2b 749 ahci_sg = pp->cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
cedc9a47
JG		 750 ata_for_each_sg(sg, qc) {
751 dma_addr_t addr = sg_dma_address(sg);
752 u32 sg_len = sg_dma_len(sg);
753
754 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
755 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
756 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 757
cedc9a47 758 ahci_sg++;
828d09de 759 n_sg++;
1da177e4 760 }
828d09de
JG		 761
762 return n_sg;
1da177e4
LT		 763}
764
765static void ahci_qc_prep(struct ata_queued_cmd *qc)
766{
a0ea7328
JG		 767 struct ata_port *ap = qc->ap;
768 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 769 int is_atapi = is_atapi_taskfile(&qc->tf);
1da177e4
LT		 770 u32 opts;
771 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 772 unsigned int n_elem;
1da177e4 773
1da177e4
LT		 774 /*
775 * Fill in command table information. First, the header,
776 * a SATA Register - Host to Device command FIS.
777 */
778 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
cc9278ed 779 if (is_atapi) {
a0ea7328 780 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
6e7846e9
TH		 781 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb,
782 qc->dev->cdb_len);
a0ea7328 783 }
1da177e4 784
cc9278ed
TH		 785 n_elem = 0;
786 if (qc->flags & ATA_QCFLAG_DMAMAP)
787 n_elem = ahci_fill_sg(qc);
1da177e4 788
cc9278ed
TH		 789 /*
790 * Fill in command slot information.
791 */
792 opts = cmd_fis_len | n_elem << 16;
793 if (qc->tf.flags & ATA_TFLAG_WRITE)
794 opts |= AHCI_CMD_WRITE;
795 if (is_atapi)
4b10e559 796 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 797
a42fc659 798 ahci_fill_cmd_slot(pp, opts);
1da177e4
LT		 799}
800
78cd52d0 801static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 802{
78cd52d0
TH		 803 struct ahci_port_priv *pp = ap->private_data;
804 struct ata_eh_info *ehi = &ap->eh_info;
805 unsigned int err_mask = 0, action = 0;
806 struct ata_queued_cmd *qc;
807 u32 serror;
1da177e4 808
78cd52d0 809 ata_ehi_clear_desc(ehi);
1da177e4 810
78cd52d0
TH		 811 /* AHCI needs SError cleared; otherwise, it might lock up */
812 serror = ahci_scr_read(ap, SCR_ERROR);
813 ahci_scr_write(ap, SCR_ERROR, serror);
1da177e4 814
78cd52d0
TH		 815 /* analyze @irq_stat */
816 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
817
818 if (irq_stat & PORT_IRQ_TF_ERR)
819 err_mask |= AC_ERR_DEV;
820
821 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
822 err_mask |= AC_ERR_HOST_BUS;
823 action |= ATA_EH_SOFTRESET;
1da177e4
LT		 824 }
825
78cd52d0
TH		 826 if (irq_stat & PORT_IRQ_IF_ERR) {
827 err_mask |= AC_ERR_ATA_BUS;
828 action |= ATA_EH_SOFTRESET;
829 ata_ehi_push_desc(ehi, ", interface fatal error");
830 }
1da177e4 831
78cd52d0
TH		 832 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
833 err_mask |= AC_ERR_ATA_BUS;
834 action |= ATA_EH_SOFTRESET;
835 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
836 "connection status changed" : "PHY RDY changed");
837 }
838
839 if (irq_stat & PORT_IRQ_UNK_FIS) {
840 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1da177e4 841
78cd52d0
TH		 842 err_mask |= AC_ERR_HSM;
843 action |= ATA_EH_SOFTRESET;
844 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
845 unk[0], unk[1], unk[2], unk[3]);
846 }
1da177e4 847
78cd52d0
TH		 848 /* okay, let's hand over to EH */
849 ehi->serror |= serror;
850 ehi->action |= action;
b8f6153e 851
1da177e4 852 qc = ata_qc_from_tag(ap, ap->active_tag);
78cd52d0
TH		 853 if (qc)
854 qc->err_mask |= err_mask;
855 else
856 ehi->err_mask |= err_mask;
a72ec4ce 857
78cd52d0
TH		 858 if (irq_stat & PORT_IRQ_FREEZE)
859 ata_port_freeze(ap);
860 else
861 ata_port_abort(ap);
1da177e4
LT		 862}
863
78cd52d0 864static void ahci_host_intr(struct ata_port *ap)
1da177e4 865{
ea6ba10b
JG		 866 void __iomem *mmio = ap->host_set->mmio_base;
867 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
78cd52d0
TH		 868 struct ata_queued_cmd *qc;
869 u32 status, ci;
1da177e4
LT		 870
871 status = readl(port_mmio + PORT_IRQ_STAT);
872 writel(status, port_mmio + PORT_IRQ_STAT);
873
78cd52d0
TH		 874 if (unlikely(status & PORT_IRQ_ERROR)) {
875 ahci_error_intr(ap, status);
876 return;
1da177e4
LT		 877 }
878
78cd52d0
TH		 879 if ((qc = ata_qc_from_tag(ap, ap->active_tag))) {
880 ci = readl(port_mmio + PORT_CMD_ISSUE);
881 if ((ci & 0x1) == 0) {
a22e2eb0 882 ata_qc_complete(qc);
78cd52d0 883 return;
a22e2eb0 884 }
1da177e4
LT		 885 }
886
2a3917a8
TH		 887 /* hmmm... a spurious interupt */
888
889 /* ignore interim PIO setup fis interrupts */
890 if (ata_tag_valid(ap->active_tag)) {
891 struct ata_queued_cmd *qc =
892 ata_qc_from_tag(ap, ap->active_tag);
893
894 if (qc && qc->tf.protocol == ATA_PROT_PIO &&
895 (status & PORT_IRQ_PIOS_FIS))
896 return;
897 }
898
78cd52d0
TH		 899 if (ata_ratelimit())
900 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
901 "(irq_stat 0x%x active_tag %d)\n",
902 status, ap->active_tag);
1da177e4
LT		 903}
904
905static void ahci_irq_clear(struct ata_port *ap)
906{
907 /* TODO */
908}
909
910static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
911{
912 struct ata_host_set *host_set = dev_instance;
913 struct ahci_host_priv *hpriv;
914 unsigned int i, handled = 0;
ea6ba10b 915 void __iomem *mmio;
1da177e4
LT		 916 u32 irq_stat, irq_ack = 0;
917
918 VPRINTK("ENTER\n");
919
920 hpriv = host_set->private_data;
921 mmio = host_set->mmio_base;
922
923 /* sigh. 0xffffffff is a valid return from h/w */
924 irq_stat = readl(mmio + HOST_IRQ_STAT);
925 irq_stat &= hpriv->port_map;
926 if (!irq_stat)
927 return IRQ_NONE;
928
929 spin_lock(&host_set->lock);
930
931 for (i = 0; i < host_set->n_ports; i++) {
932 struct ata_port *ap;
1da177e4 933
67846b30
JG		 934 if (!(irq_stat & (1 << i)))
935 continue;
936
1da177e4 937 ap = host_set->ports[i];
67846b30 938 if (ap) {
78cd52d0 939 ahci_host_intr(ap);
67846b30
JG		 940 VPRINTK("port %u\n", i);
941 } else {
942 VPRINTK("port %u (no irq)\n", i);
6971ed1f
TH		 943 if (ata_ratelimit())
944 dev_printk(KERN_WARNING, host_set->dev,
a9524a76 945 "interrupt on disabled port %u\n", i);
1da177e4 946 }
67846b30
JG		 947
948 irq_ack |= (1 << i);
1da177e4
LT		 949 }
950
951 if (irq_ack) {
952 writel(irq_ack, mmio + HOST_IRQ_STAT);
953 handled = 1;
954 }
955
78cd52d0 956 spin_unlock(&host_set->lock);
1da177e4
LT		 957
958 VPRINTK("EXIT\n");
959
960 return IRQ_RETVAL(handled);
961}
962
9a3d9eb0 963static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 964{
965 struct ata_port *ap = qc->ap;
ea6ba10b 966 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4 967
1da177e4
LT		 968 writel(1, port_mmio + PORT_CMD_ISSUE);
969 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
970
971 return 0;
972}
973
78cd52d0
TH		 974static void ahci_freeze(struct ata_port *ap)
975{
976 void __iomem *mmio = ap->host_set->mmio_base;
977 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
978
979 /* turn IRQ off */
980 writel(0, port_mmio + PORT_IRQ_MASK);
981}
982
983static void ahci_thaw(struct ata_port *ap)
984{
985 void __iomem *mmio = ap->host_set->mmio_base;
986 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
987 u32 tmp;
988
989 /* clear IRQ */
990 tmp = readl(port_mmio + PORT_IRQ_STAT);
991 writel(tmp, port_mmio + PORT_IRQ_STAT);
992 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
993
994 /* turn IRQ back on */
995 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
996}
997
998static void ahci_error_handler(struct ata_port *ap)
999{
1000 if (!(ap->flags & ATA_FLAG_FROZEN)) {
1001 /* restart engine */
1002 ahci_stop_engine(ap);
1003 ahci_start_engine(ap);
1004 }
1005
1006 /* perform recovery */
1007 ata_do_eh(ap, ahci_softreset, ahci_hardreset, ahci_postreset);
1008}
1009
1010static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1011{
1012 struct ata_port *ap = qc->ap;
1013
1014 if (qc->flags & ATA_QCFLAG_FAILED)
1015 qc->err_mask |= AC_ERR_OTHER;
1016
1017 if (qc->err_mask) {
1018 /* make DMA engine forget about the failed command */
1019 ahci_stop_engine(ap);
1020 ahci_start_engine(ap);
1021 }
1022}
1023
1da177e4
LT		 1024static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1025 unsigned int port_idx)
1026{
1027 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1028 base = ahci_port_base_ul(base, port_idx);
1029 VPRINTK("base now==0x%lx\n", base);
1030
1031 port->cmd_addr = base;
1032 port->scr_addr = base + PORT_SCR;
1033
1034 VPRINTK("EXIT\n");
1035}
1036
1037static int ahci_host_init(struct ata_probe_ent *probe_ent)
1038{
1039 struct ahci_host_priv *hpriv = probe_ent->private_data;
1040 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1041 void __iomem *mmio = probe_ent->mmio_base;
1042 u32 tmp, cap_save;
1da177e4
LT		 1043 unsigned int i, j, using_dac;
1044 int rc;
1045 void __iomem *port_mmio;
1046
1047 cap_save = readl(mmio + HOST_CAP);
1048 cap_save &= ( (1<<28) | (1<<17) );
1049 cap_save |= (1 << 27);
1050
1051 /* global controller reset */
1052 tmp = readl(mmio + HOST_CTL);
1053 if ((tmp & HOST_RESET) == 0) {
1054 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1055 readl(mmio + HOST_CTL); /* flush */
1056 }
1057
1058 /* reset must complete within 1 second, or
1059 * the hardware should be considered fried.
1060 */
1061 ssleep(1);
1062
1063 tmp = readl(mmio + HOST_CTL);
1064 if (tmp & HOST_RESET) {
a9524a76
JG		 1065 dev_printk(KERN_ERR, &pdev->dev,
1066 "controller reset failed (0x%x)\n", tmp);
1da177e4
LT		 1067 return -EIO;
1068 }
1069
1070 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1071 (void) readl(mmio + HOST_CTL); /* flush */
1072 writel(cap_save, mmio + HOST_CAP);
1073 writel(0xf, mmio + HOST_PORTS_IMPL);
1074 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1075
bd12097c
JG		 1076 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1077 u16 tmp16;
1078
1079 pci_read_config_word(pdev, 0x92, &tmp16);
1080 tmp16 |= 0xf;
1081 pci_write_config_word(pdev, 0x92, tmp16);
1082 }
1da177e4
LT		 1083
1084 hpriv->cap = readl(mmio + HOST_CAP);
1085 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1086 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1087
1088 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1089 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1090
1091 using_dac = hpriv->cap & HOST_CAP_64;
1092 if (using_dac &&
1093 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1094 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1095 if (rc) {
1096 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1097 if (rc) {
a9524a76
JG		 1098 dev_printk(KERN_ERR, &pdev->dev,
1099 "64-bit DMA enable failed\n");
1da177e4
LT		 1100 return rc;
1101 }
1102 }
1da177e4
LT		 1103 } else {
1104 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1105 if (rc) {
a9524a76
JG		 1106 dev_printk(KERN_ERR, &pdev->dev,
1107 "32-bit DMA enable failed\n");
1da177e4
LT		 1108 return rc;
1109 }
1110 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1111 if (rc) {
a9524a76
JG		 1112 dev_printk(KERN_ERR, &pdev->dev,
1113 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 1114 return rc;
1115 }
1116 }
1117
1118 for (i = 0; i < probe_ent->n_ports; i++) {
1119#if 0 /* BIOSen initialize this incorrectly */
1120 if (!(hpriv->port_map & (1 << i)))
1121 continue;
1122#endif
1123
1124 port_mmio = ahci_port_base(mmio, i);
1125 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
1126
1127 ahci_setup_port(&probe_ent->port[i],
1128 (unsigned long) mmio, i);
1129
1130 /* make sure port is not active */
1131 tmp = readl(port_mmio + PORT_CMD);
1132 VPRINTK("PORT_CMD 0x%x\n", tmp);
1133 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1134 PORT_CMD_FIS_RX | PORT_CMD_START)) {
1135 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1136 PORT_CMD_FIS_RX | PORT_CMD_START);
1137 writel(tmp, port_mmio + PORT_CMD);
1138 readl(port_mmio + PORT_CMD); /* flush */
1139
1140 /* spec says 500 msecs for each bit, so
1141 * this is slightly incorrect.
1142 */
1143 msleep(500);
1144 }
1145
1146 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
1147
1148 j = 0;
1149 while (j < 100) {
1150 msleep(10);
1151 tmp = readl(port_mmio + PORT_SCR_STAT);
1152 if ((tmp & 0xf) == 0x3)
1153 break;
1154 j++;
1155 }
1156
1157 tmp = readl(port_mmio + PORT_SCR_ERR);
1158 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1159 writel(tmp, port_mmio + PORT_SCR_ERR);
1160
1161 /* ack any pending irq events for this port */
1162 tmp = readl(port_mmio + PORT_IRQ_STAT);
1163 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1164 if (tmp)
1165 writel(tmp, port_mmio + PORT_IRQ_STAT);
1166
1167 writel(1 << i, mmio + HOST_IRQ_STAT);
1da177e4
LT		 1168 }
1169
1170 tmp = readl(mmio + HOST_CTL);
1171 VPRINTK("HOST_CTL 0x%x\n", tmp);
1172 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1173 tmp = readl(mmio + HOST_CTL);
1174 VPRINTK("HOST_CTL 0x%x\n", tmp);
1175
1176 pci_set_master(pdev);
1177
1178 return 0;
1179}
1180
1da177e4
LT		 1181static void ahci_print_info(struct ata_probe_ent *probe_ent)
1182{
1183 struct ahci_host_priv *hpriv = probe_ent->private_data;
1184 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
ea6ba10b 1185 void __iomem *mmio = probe_ent->mmio_base;
1da177e4
LT		 1186 u32 vers, cap, impl, speed;
1187 const char *speed_s;
1188 u16 cc;
1189 const char *scc_s;
1190
1191 vers = readl(mmio + HOST_VERSION);
1192 cap = hpriv->cap;
1193 impl = hpriv->port_map;
1194
1195 speed = (cap >> 20) & 0xf;
1196 if (speed == 1)
1197 speed_s = "1.5";
1198 else if (speed == 2)
1199 speed_s = "3";
1200 else
1201 speed_s = "?";
1202
1203 pci_read_config_word(pdev, 0x0a, &cc);
1204 if (cc == 0x0101)
1205 scc_s = "IDE";
1206 else if (cc == 0x0106)
1207 scc_s = "SATA";
1208 else if (cc == 0x0104)
1209 scc_s = "RAID";
1210 else
1211 scc_s = "unknown";
1212
a9524a76
JG		 1213 dev_printk(KERN_INFO, &pdev->dev,
1214 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1215 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1216 ,
1da177e4
LT		 1217
1218 (vers >> 24) & 0xff,
1219 (vers >> 16) & 0xff,
1220 (vers >> 8) & 0xff,
1221 vers & 0xff,
1222
1223 ((cap >> 8) & 0x1f) + 1,
1224 (cap & 0x1f) + 1,
1225 speed_s,
1226 impl,
1227 scc_s);
1228
a9524a76
JG		 1229 dev_printk(KERN_INFO, &pdev->dev,
1230 "flags: "
1da177e4
LT		 1231 "%s%s%s%s%s%s"
1232 "%s%s%s%s%s%s%s\n"
1233 ,
1da177e4
LT		 1234
1235 cap & (1 << 31) ? "64bit " : "",
1236 cap & (1 << 30) ? "ncq " : "",
1237 cap & (1 << 28) ? "ilck " : "",
1238 cap & (1 << 27) ? "stag " : "",
1239 cap & (1 << 26) ? "pm " : "",
1240 cap & (1 << 25) ? "led " : "",
1241
1242 cap & (1 << 24) ? "clo " : "",
1243 cap & (1 << 19) ? "nz " : "",
1244 cap & (1 << 18) ? "only " : "",
1245 cap & (1 << 17) ? "pmp " : "",
1246 cap & (1 << 15) ? "pio " : "",
1247 cap & (1 << 14) ? "slum " : "",
1248 cap & (1 << 13) ? "part " : ""
1249 );
1250}
1251
1252static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1253{
1254 static int printed_version;
1255 struct ata_probe_ent *probe_ent = NULL;
1256 struct ahci_host_priv *hpriv;
1257 unsigned long base;
ea6ba10b 1258 void __iomem *mmio_base;
1da177e4 1259 unsigned int board_idx = (unsigned int) ent->driver_data;
907f4678 1260 int have_msi, pci_dev_busy = 0;
1da177e4
LT		 1261 int rc;
1262
1263 VPRINTK("ENTER\n");
1264
1265 if (!printed_version++)
a9524a76 1266 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4
LT		 1267
1268 rc = pci_enable_device(pdev);
1269 if (rc)
1270 return rc;
1271
1272 rc = pci_request_regions(pdev, DRV_NAME);
1273 if (rc) {
1274 pci_dev_busy = 1;
1275 goto err_out;
1276 }
1277
907f4678
JG		 1278 if (pci_enable_msi(pdev) == 0)
1279 have_msi = 1;
1280 else {
1281 pci_intx(pdev, 1);
1282 have_msi = 0;
1283 }
1da177e4
LT		 1284
1285 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1286 if (probe_ent == NULL) {
1287 rc = -ENOMEM;
907f4678 1288 goto err_out_msi;
1da177e4
LT		 1289 }
1290
1291 memset(probe_ent, 0, sizeof(*probe_ent));
1292 probe_ent->dev = pci_dev_to_dev(pdev);
1293 INIT_LIST_HEAD(&probe_ent->node);
1294
374b1873 1295 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1da177e4
LT		 1296 if (mmio_base == NULL) {
1297 rc = -ENOMEM;
1298 goto err_out_free_ent;
1299 }
1300 base = (unsigned long) mmio_base;
1301
1302 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1303 if (!hpriv) {
1304 rc = -ENOMEM;
1305 goto err_out_iounmap;
1306 }
1307 memset(hpriv, 0, sizeof(*hpriv));
1308
1309 probe_ent->sht = ahci_port_info[board_idx].sht;
1310 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1311 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1312 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1313 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1314
1315 probe_ent->irq = pdev->irq;
1316 probe_ent->irq_flags = SA_SHIRQ;
1317 probe_ent->mmio_base = mmio_base;
1318 probe_ent->private_data = hpriv;
1319
4b0060f4
JG		 1320 if (have_msi)
1321 hpriv->flags |= AHCI_FLAG_MSI;
907f4678 1322
bd12097c
JG		 1323 /* JMicron-specific fixup: make sure we're in AHCI mode */
1324 if (pdev->vendor == 0x197b)
1325 pci_write_config_byte(pdev, 0x41, 0xa1);
1326
1da177e4
LT		 1327 /* initialize adapter */
1328 rc = ahci_host_init(probe_ent);
1329 if (rc)
1330 goto err_out_hpriv;
1331
1332 ahci_print_info(probe_ent);
1333
1334 /* FIXME: check ata_device_add return value */
1335 ata_device_add(probe_ent);
1336 kfree(probe_ent);
1337
1338 return 0;
1339
1340err_out_hpriv:
1341 kfree(hpriv);
1342err_out_iounmap:
374b1873 1343 pci_iounmap(pdev, mmio_base);
1da177e4
LT		 1344err_out_free_ent:
1345 kfree(probe_ent);
907f4678
JG		 1346err_out_msi:
1347 if (have_msi)
1348 pci_disable_msi(pdev);
1349 else
1350 pci_intx(pdev, 0);
1da177e4
LT		 1351 pci_release_regions(pdev);
1352err_out:
1353 if (!pci_dev_busy)
1354 pci_disable_device(pdev);
1355 return rc;
1356}
1357
907f4678
JG		 1358static void ahci_remove_one (struct pci_dev *pdev)
1359{
1360 struct device *dev = pci_dev_to_dev(pdev);
1361 struct ata_host_set *host_set = dev_get_drvdata(dev);
1362 struct ahci_host_priv *hpriv = host_set->private_data;
1363 struct ata_port *ap;
1364 unsigned int i;
1365 int have_msi;
1366
1367 for (i = 0; i < host_set->n_ports; i++) {
1368 ap = host_set->ports[i];
1369
1370 scsi_remove_host(ap->host);
1371 }
1372
4b0060f4 1373 have_msi = hpriv->flags & AHCI_FLAG_MSI;
907f4678 1374 free_irq(host_set->irq, host_set);
907f4678
JG		 1375
1376 for (i = 0; i < host_set->n_ports; i++) {
1377 ap = host_set->ports[i];
1378
1379 ata_scsi_release(ap->host);
1380 scsi_host_put(ap->host);
1381 }
1382
e005f01d 1383 kfree(hpriv);
374b1873 1384 pci_iounmap(pdev, host_set->mmio_base);
ead5de99
JG		 1385 kfree(host_set);
1386
907f4678
JG		 1387 if (have_msi)
1388 pci_disable_msi(pdev);
1389 else
1390 pci_intx(pdev, 0);
1391 pci_release_regions(pdev);
907f4678
JG		 1392 pci_disable_device(pdev);
1393 dev_set_drvdata(dev, NULL);
1394}
1da177e4
LT		 1395
1396static int __init ahci_init(void)
1397{
1398 return pci_module_init(&ahci_pci_driver);
1399}
1400
1da177e4
LT		 1401static void __exit ahci_exit(void)
1402{
1403 pci_unregister_driver(&ahci_pci_driver);
1404}
1405
1406
1407MODULE_AUTHOR("Jeff Garzik");
1408MODULE_DESCRIPTION("AHCI SATA low-level driver");
1409MODULE_LICENSE("GPL");
1410MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1411MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1412
1413module_init(ahci_init);
1414module_exit(ahci_exit);
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