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Merge branch 'for-2.6.36' of git://linux-nfs.org/~bfields/linux
[net-next-2.6.git] / drivers / platform / x86 / intel_ips.c
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aa7ffc01
JB		 1/*
2 * Copyright (c) 2009-2010 Intel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 * The full GNU General Public License is included in this distribution in
18 * the file called "COPYING".
19 *
20 * Authors:
21 * Jesse Barnes <jbarnes@virtuousgeek.org>
22 */
23
24/*
25 * Some Intel Ibex Peak based platforms support so-called "intelligent
26 * power sharing", which allows the CPU and GPU to cooperate to maximize
27 * performance within a given TDP (thermal design point). This driver
28 * performs the coordination between the CPU and GPU, monitors thermal and
29 * power statistics in the platform, and initializes power monitoring
30 * hardware. It also provides a few tunables to control behavior. Its
31 * primary purpose is to safely allow CPU and GPU turbo modes to be enabled
32 * by tracking power and thermal budget; secondarily it can boost turbo
33 * performance by allocating more power or thermal budget to the CPU or GPU
34 * based on available headroom and activity.
35 *
36 * The basic algorithm is driven by a 5s moving average of tempurature. If
37 * thermal headroom is available, the CPU and/or GPU power clamps may be
38 * adjusted upwards. If we hit the thermal ceiling or a thermal trigger,
39 * we scale back the clamp. Aside from trigger events (when we're critically
40 * close or over our TDP) we don't adjust the clamps more than once every
41 * five seconds.
42 *
43 * The thermal device (device 31, function 6) has a set of registers that
44 * are updated by the ME firmware. The ME should also take the clamp values
45 * written to those registers and write them to the CPU, but we currently
46 * bypass that functionality and write the CPU MSR directly.
47 *
48 * UNSUPPORTED:
49 * - dual MCP configs
50 *
51 * TODO:
52 * - handle CPU hotplug
53 * - provide turbo enable/disable api
aa7ffc01
JB		 54 *
55 * Related documents:
56 * - CDI 403777, 403778 - Auburndale EDS vol 1 & 2
57 * - CDI 401376 - Ibex Peak EDS
58 * - ref 26037, 26641 - IPS BIOS spec
59 * - ref 26489 - Nehalem BIOS writer's guide
60 * - ref 26921 - Ibex Peak BIOS Specification
61 */
62
63#include <linux/debugfs.h>
64#include <linux/delay.h>
65#include <linux/interrupt.h>
66#include <linux/kernel.h>
67#include <linux/kthread.h>
68#include <linux/module.h>
69#include <linux/pci.h>
70#include <linux/sched.h>
71#include <linux/seq_file.h>
72#include <linux/string.h>
73#include <linux/tick.h>
74#include <linux/timer.h>
75#include <drm/i915_drm.h>
76#include <asm/msr.h>
77#include <asm/processor.h>
78
79#define PCI_DEVICE_ID_INTEL_THERMAL_SENSOR 0x3b32
80
81/*
82 * Package level MSRs for monitor/control
83 */
84#define PLATFORM_INFO 0xce
85#define PLATFORM_TDP (1<<29)
86#define PLATFORM_RATIO (1<<28)
87
88#define IA32_MISC_ENABLE 0x1a0
89#define IA32_MISC_TURBO_EN (1ULL<<38)
90
91#define TURBO_POWER_CURRENT_LIMIT 0x1ac
92#define TURBO_TDC_OVR_EN (1UL<<31)
93#define TURBO_TDC_MASK (0x000000007fff0000UL)
94#define TURBO_TDC_SHIFT (16)
95#define TURBO_TDP_OVR_EN (1UL<<15)
96#define TURBO_TDP_MASK (0x0000000000003fffUL)
97
98/*
99 * Core/thread MSRs for monitoring
100 */
101#define IA32_PERF_CTL 0x199
102#define IA32_PERF_TURBO_DIS (1ULL<<32)
103
104/*
105 * Thermal PCI device regs
106 */
107#define THM_CFG_TBAR 0x10
108#define THM_CFG_TBAR_HI 0x14
109
110#define THM_TSIU 0x00
111#define THM_TSE 0x01
112#define TSE_EN 0xb8
113#define THM_TSS 0x02
114#define THM_TSTR 0x03
115#define THM_TSTTP 0x04
116#define THM_TSCO 0x08
117#define THM_TSES 0x0c
118#define THM_TSGPEN 0x0d
119#define TSGPEN_HOT_LOHI (1<<1)
120#define TSGPEN_CRIT_LOHI (1<<2)
121#define THM_TSPC 0x0e
122#define THM_PPEC 0x10
123#define THM_CTA 0x12
124#define THM_PTA 0x14
125#define PTA_SLOPE_MASK (0xff00)
126#define PTA_SLOPE_SHIFT 8
127#define PTA_OFFSET_MASK (0x00ff)
128#define THM_MGTA 0x16
129#define MGTA_SLOPE_MASK (0xff00)
130#define MGTA_SLOPE_SHIFT 8
131#define MGTA_OFFSET_MASK (0x00ff)
132#define THM_TRC 0x1a
133#define TRC_CORE2_EN (1<<15)
134#define TRC_THM_EN (1<<12)
135#define TRC_C6_WAR (1<<8)
136#define TRC_CORE1_EN (1<<7)
137#define TRC_CORE_PWR (1<<6)
138#define TRC_PCH_EN (1<<5)
139#define TRC_MCH_EN (1<<4)
140#define TRC_DIMM4 (1<<3)
141#define TRC_DIMM3 (1<<2)
142#define TRC_DIMM2 (1<<1)
143#define TRC_DIMM1 (1<<0)
144#define THM_TES 0x20
145#define THM_TEN 0x21
146#define TEN_UPDATE_EN 1
147#define THM_PSC 0x24
148#define PSC_NTG (1<<0) /* No GFX turbo support */
149#define PSC_NTPC (1<<1) /* No CPU turbo support */
150#define PSC_PP_DEF (0<<2) /* Perf policy up to driver */
151#define PSP_PP_PC (1<<2) /* BIOS prefers CPU perf */
152#define PSP_PP_BAL (2<<2) /* BIOS wants balanced perf */
153#define PSP_PP_GFX (3<<2) /* BIOS prefers GFX perf */
154#define PSP_PBRT (1<<4) /* BIOS run time support */
155#define THM_CTV1 0x30
156#define CTV_TEMP_ERROR (1<<15)
157#define CTV_TEMP_MASK 0x3f
158#define CTV_
159#define THM_CTV2 0x32
160#define THM_CEC 0x34 /* undocumented power accumulator in joules */
161#define THM_AE 0x3f
162#define THM_HTS 0x50 /* 32 bits */
163#define HTS_PCPL_MASK (0x7fe00000)
164#define HTS_PCPL_SHIFT 21
165#define HTS_GPL_MASK (0x001ff000)
166#define HTS_GPL_SHIFT 12
167#define HTS_PP_MASK (0x00000c00)
168#define HTS_PP_SHIFT 10
169#define HTS_PP_DEF 0
170#define HTS_PP_PROC 1
171#define HTS_PP_BAL 2
172#define HTS_PP_GFX 3
173#define HTS_PCTD_DIS (1<<9)
174#define HTS_GTD_DIS (1<<8)
175#define HTS_PTL_MASK (0x000000fe)
176#define HTS_PTL_SHIFT 1
177#define HTS_NVV (1<<0)
178#define THM_HTSHI 0x54 /* 16 bits */
179#define HTS2_PPL_MASK (0x03ff)
180#define HTS2_PRST_MASK (0x3c00)
181#define HTS2_PRST_SHIFT 10
182#define HTS2_PRST_UNLOADED 0
183#define HTS2_PRST_RUNNING 1
184#define HTS2_PRST_TDISOP 2 /* turbo disabled due to power */
185#define HTS2_PRST_TDISHT 3 /* turbo disabled due to high temp */
186#define HTS2_PRST_TDISUSR 4 /* user disabled turbo */
187#define HTS2_PRST_TDISPLAT 5 /* platform disabled turbo */
188#define HTS2_PRST_TDISPM 6 /* power management disabled turbo */
189#define HTS2_PRST_TDISERR 7 /* some kind of error disabled turbo */
190#define THM_PTL 0x56
191#define THM_MGTV 0x58
192#define TV_MASK 0x000000000000ff00
193#define TV_SHIFT 8
194#define THM_PTV 0x60
195#define PTV_MASK 0x00ff
196#define THM_MMGPC 0x64
197#define THM_MPPC 0x66
198#define THM_MPCPC 0x68
199#define THM_TSPIEN 0x82
200#define TSPIEN_AUX_LOHI (1<<0)
201#define TSPIEN_HOT_LOHI (1<<1)
202#define TSPIEN_CRIT_LOHI (1<<2)
203#define TSPIEN_AUX2_LOHI (1<<3)
204#define THM_TSLOCK 0x83
205#define THM_ATR 0x84
206#define THM_TOF 0x87
207#define THM_STS 0x98
208#define STS_PCPL_MASK (0x7fe00000)
209#define STS_PCPL_SHIFT 21
210#define STS_GPL_MASK (0x001ff000)
211#define STS_GPL_SHIFT 12
212#define STS_PP_MASK (0x00000c00)
213#define STS_PP_SHIFT 10
214#define STS_PP_DEF 0
215#define STS_PP_PROC 1
216#define STS_PP_BAL 2
217#define STS_PP_GFX 3
218#define STS_PCTD_DIS (1<<9)
219#define STS_GTD_DIS (1<<8)
220#define STS_PTL_MASK (0x000000fe)
221#define STS_PTL_SHIFT 1
222#define STS_NVV (1<<0)
223#define THM_SEC 0x9c
224#define SEC_ACK (1<<0)
225#define THM_TC3 0xa4
226#define THM_TC1 0xa8
227#define STS_PPL_MASK (0x0003ff00)
228#define STS_PPL_SHIFT 16
229#define THM_TC2 0xac
230#define THM_DTV 0xb0
231#define THM_ITV 0xd8
6230d18c 232#define ITV_ME_SEQNO_MASK 0x00ff0000 /* ME should update every ~200ms */
aa7ffc01
JB		 233#define ITV_ME_SEQNO_SHIFT (16)
234#define ITV_MCH_TEMP_MASK 0x0000ff00
235#define ITV_MCH_TEMP_SHIFT (8)
236#define ITV_PCH_TEMP_MASK 0x000000ff
237
238#define thm_readb(off) readb(ips->regmap + (off))
239#define thm_readw(off) readw(ips->regmap + (off))
240#define thm_readl(off) readl(ips->regmap + (off))
241#define thm_readq(off) readq(ips->regmap + (off))
242
243#define thm_writeb(off, val) writeb((val), ips->regmap + (off))
244#define thm_writew(off, val) writew((val), ips->regmap + (off))
245#define thm_writel(off, val) writel((val), ips->regmap + (off))
246
247static const int IPS_ADJUST_PERIOD = 5000; /* ms */
248
249/* For initial average collection */
250static const int IPS_SAMPLE_PERIOD = 200; /* ms */
251static const int IPS_SAMPLE_WINDOW = 5000; /* 5s moving window of samples */
252#define IPS_SAMPLE_COUNT (IPS_SAMPLE_WINDOW / IPS_SAMPLE_PERIOD)
253
254/* Per-SKU limits */
255struct ips_mcp_limits {
256 int cpu_family;
257 int cpu_model; /* includes extended model... */
258 int mcp_power_limit; /* mW units */
259 int core_power_limit;
260 int mch_power_limit;
261 int core_temp_limit; /* degrees C */
262 int mch_temp_limit;
263};
264
265/* Max temps are -10 degrees C to avoid PROCHOT# */
266
267struct ips_mcp_limits ips_sv_limits = {
268 .mcp_power_limit = 35000,
269 .core_power_limit = 29000,
270 .mch_power_limit = 20000,
271 .core_temp_limit = 95,
272 .mch_temp_limit = 90
273};
274
275struct ips_mcp_limits ips_lv_limits = {
276 .mcp_power_limit = 25000,
277 .core_power_limit = 21000,
278 .mch_power_limit = 13000,
279 .core_temp_limit = 95,
280 .mch_temp_limit = 90
281};
282
283struct ips_mcp_limits ips_ulv_limits = {
284 .mcp_power_limit = 18000,
285 .core_power_limit = 14000,
286 .mch_power_limit = 11000,
287 .core_temp_limit = 95,
288 .mch_temp_limit = 90
289};
290
291struct ips_driver {
292 struct pci_dev *dev;
293 void *regmap;
294 struct task_struct *monitor;
295 struct task_struct *adjust;
296 struct dentry *debug_root;
297
298 /* Average CPU core temps (all averages in .01 degrees C for precision) */
299 u16 ctv1_avg_temp;
300 u16 ctv2_avg_temp;
301 /* GMCH average */
302 u16 mch_avg_temp;
303 /* Average for the CPU (both cores?) */
304 u16 mcp_avg_temp;
305 /* Average power consumption (in mW) */
306 u32 cpu_avg_power;
307 u32 mch_avg_power;
308
309 /* Offset values */
310 u16 cta_val;
311 u16 pta_val;
312 u16 mgta_val;
313
314 /* Maximums & prefs, protected by turbo status lock */
315 spinlock_t turbo_status_lock;
316 u16 mcp_temp_limit;
317 u16 mcp_power_limit;
318 u16 core_power_limit;
319 u16 mch_power_limit;
320 bool cpu_turbo_enabled;
321 bool __cpu_turbo_on;
322 bool gpu_turbo_enabled;
323 bool __gpu_turbo_on;
324 bool gpu_preferred;
325 bool poll_turbo_status;
326 bool second_cpu;
354aeeb1 327 bool turbo_toggle_allowed;
aa7ffc01
JB		 328 struct ips_mcp_limits *limits;
329
330 /* Optional MCH interfaces for if i915 is in use */
331 unsigned long (*read_mch_val)(void);
332 bool (*gpu_raise)(void);
333 bool (*gpu_lower)(void);
334 bool (*gpu_busy)(void);
335 bool (*gpu_turbo_disable)(void);
336
337 /* For restoration at unload */
338 u64 orig_turbo_limit;
339 u64 orig_turbo_ratios;
340};
341
342/**
343 * ips_cpu_busy - is CPU busy?
344 * @ips: IPS driver struct
345 *
346 * Check CPU for load to see whether we should increase its thermal budget.
347 *
348 * RETURNS:
349 * True if the CPU could use more power, false otherwise.
350 */
351static bool ips_cpu_busy(struct ips_driver *ips)
352{
353 if ((avenrun[0] >> FSHIFT) > 1)
354 return true;
355
356 return false;
357}
358
359/**
360 * ips_cpu_raise - raise CPU power clamp
361 * @ips: IPS driver struct
362 *
363 * Raise the CPU power clamp by %IPS_CPU_STEP, in accordance with TDP for
364 * this platform.
365 *
366 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR upwards (as
367 * long as we haven't hit the TDP limit for the SKU).
368 */
369static void ips_cpu_raise(struct ips_driver *ips)
370{
371 u64 turbo_override;
372 u16 cur_tdp_limit, new_tdp_limit;
373
374 if (!ips->cpu_turbo_enabled)
375 return;
376
377 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
378
379 cur_tdp_limit = turbo_override & TURBO_TDP_MASK;
380 new_tdp_limit = cur_tdp_limit + 8; /* 1W increase */
381
382 /* Clamp to SKU TDP limit */
383 if (((new_tdp_limit * 10) / 8) > ips->core_power_limit)
384 new_tdp_limit = cur_tdp_limit;
385
386 thm_writew(THM_MPCPC, (new_tdp_limit * 10) / 8);
387
388 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDC_OVR_EN;
389 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
390
391 turbo_override &= ~TURBO_TDP_MASK;
392 turbo_override |= new_tdp_limit;
393
394 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
395}
396
397/**
398 * ips_cpu_lower - lower CPU power clamp
399 * @ips: IPS driver struct
400 *
401 * Lower CPU power clamp b %IPS_CPU_STEP if possible.
402 *
403 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR down, going
404 * as low as the platform limits will allow (though we could go lower there
405 * wouldn't be much point).
406 */
407static void ips_cpu_lower(struct ips_driver *ips)
408{
409 u64 turbo_override;
410 u16 cur_limit, new_limit;
411
412 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
413
414 cur_limit = turbo_override & TURBO_TDP_MASK;
415 new_limit = cur_limit - 8; /* 1W decrease */
416
417 /* Clamp to SKU TDP limit */
d24a9da5 418 if (new_limit < (ips->orig_turbo_limit & TURBO_TDP_MASK))
aa7ffc01
JB		 419 new_limit = ips->orig_turbo_limit & TURBO_TDP_MASK;
420
421 thm_writew(THM_MPCPC, (new_limit * 10) / 8);
422
423 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDC_OVR_EN;
424 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
425
426 turbo_override &= ~TURBO_TDP_MASK;
427 turbo_override |= new_limit;
428
429 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
430}
431
432/**
433 * do_enable_cpu_turbo - internal turbo enable function
434 * @data: unused
435 *
436 * Internal function for actually updating MSRs. When we enable/disable
437 * turbo, we need to do it on each CPU; this function is the one called
438 * by on_each_cpu() when needed.
439 */
440static void do_enable_cpu_turbo(void *data)
441{
442 u64 perf_ctl;
443
444 rdmsrl(IA32_PERF_CTL, perf_ctl);
445 if (perf_ctl & IA32_PERF_TURBO_DIS) {
446 perf_ctl &= ~IA32_PERF_TURBO_DIS;
447 wrmsrl(IA32_PERF_CTL, perf_ctl);
448 }
449}
450
451/**
452 * ips_enable_cpu_turbo - enable turbo mode on all CPUs
453 * @ips: IPS driver struct
454 *
455 * Enable turbo mode by clearing the disable bit in IA32_PERF_CTL on
456 * all logical threads.
457 */
458static void ips_enable_cpu_turbo(struct ips_driver *ips)
459{
460 /* Already on, no need to mess with MSRs */
461 if (ips->__cpu_turbo_on)
462 return;
463
354aeeb1
JB		 464 if (ips->turbo_toggle_allowed)
465 on_each_cpu(do_enable_cpu_turbo, ips, 1);
aa7ffc01
JB		 466
467 ips->__cpu_turbo_on = true;
468}
469
470/**
471 * do_disable_cpu_turbo - internal turbo disable function
472 * @data: unused
473 *
474 * Internal function for actually updating MSRs. When we enable/disable
475 * turbo, we need to do it on each CPU; this function is the one called
476 * by on_each_cpu() when needed.
477 */
478static void do_disable_cpu_turbo(void *data)
479{
480 u64 perf_ctl;
481
482 rdmsrl(IA32_PERF_CTL, perf_ctl);
483 if (!(perf_ctl & IA32_PERF_TURBO_DIS)) {
484 perf_ctl |= IA32_PERF_TURBO_DIS;
485 wrmsrl(IA32_PERF_CTL, perf_ctl);
486 }
487}
488
489/**
490 * ips_disable_cpu_turbo - disable turbo mode on all CPUs
491 * @ips: IPS driver struct
492 *
493 * Disable turbo mode by setting the disable bit in IA32_PERF_CTL on
494 * all logical threads.
495 */
496static void ips_disable_cpu_turbo(struct ips_driver *ips)
497{
498 /* Already off, leave it */
499 if (!ips->__cpu_turbo_on)
500 return;
501
354aeeb1
JB		 502 if (ips->turbo_toggle_allowed)
503 on_each_cpu(do_disable_cpu_turbo, ips, 1);
aa7ffc01
JB		 504
505 ips->__cpu_turbo_on = false;
506}
507
508/**
509 * ips_gpu_busy - is GPU busy?
510 * @ips: IPS driver struct
511 *
512 * Check GPU for load to see whether we should increase its thermal budget.
513 * We need to call into the i915 driver in this case.
514 *
515 * RETURNS:
516 * True if the GPU could use more power, false otherwise.
517 */
518static bool ips_gpu_busy(struct ips_driver *ips)
519{
0385e521
JB		 520 if (!ips->gpu_turbo_enabled)
521 return false;
522
523 return ips->gpu_busy();
aa7ffc01
JB		 524}
525
526/**
527 * ips_gpu_raise - raise GPU power clamp
528 * @ips: IPS driver struct
529 *
530 * Raise the GPU frequency/power if possible. We need to call into the
531 * i915 driver in this case.
532 */
533static void ips_gpu_raise(struct ips_driver *ips)
534{
535 if (!ips->gpu_turbo_enabled)
536 return;
537
538 if (!ips->gpu_raise())
539 ips->gpu_turbo_enabled = false;
540
541 return;
542}
543
544/**
545 * ips_gpu_lower - lower GPU power clamp
546 * @ips: IPS driver struct
547 *
548 * Lower GPU frequency/power if possible. Need to call i915.
549 */
550static void ips_gpu_lower(struct ips_driver *ips)
551{
552 if (!ips->gpu_turbo_enabled)
553 return;
554
555 if (!ips->gpu_lower())
556 ips->gpu_turbo_enabled = false;
557
558 return;
559}
560
561/**
562 * ips_enable_gpu_turbo - notify the gfx driver turbo is available
563 * @ips: IPS driver struct
564 *
565 * Call into the graphics driver indicating that it can safely use
566 * turbo mode.
567 */
568static void ips_enable_gpu_turbo(struct ips_driver *ips)
569{
570 if (ips->__gpu_turbo_on)
571 return;
572 ips->__gpu_turbo_on = true;
573}
574
575/**
576 * ips_disable_gpu_turbo - notify the gfx driver to disable turbo mode
577 * @ips: IPS driver struct
578 *
579 * Request that the graphics driver disable turbo mode.
580 */
581static void ips_disable_gpu_turbo(struct ips_driver *ips)
582{
583 /* Avoid calling i915 if turbo is already disabled */
584 if (!ips->__gpu_turbo_on)
585 return;
586
587 if (!ips->gpu_turbo_disable())
588 dev_err(&ips->dev->dev, "failed to disable graphis turbo\n");
589 else
590 ips->__gpu_turbo_on = false;
591}
592
593/**
594 * mcp_exceeded - check whether we're outside our thermal & power limits
595 * @ips: IPS driver struct
596 *
597 * Check whether the MCP is over its thermal or power budget.
598 */
599static bool mcp_exceeded(struct ips_driver *ips)
600{
601 unsigned long flags;
602 bool ret = false;
a8c096ad
TG		 603 u32 temp_limit;
604 u32 avg_power;
605 const char *msg = "MCP limit exceeded: ";
aa7ffc01
JB		 606
607 spin_lock_irqsave(&ips->turbo_status_lock, flags);
a8c096ad
TG		 608
609 temp_limit = ips->mcp_temp_limit * 100;
610 if (ips->mcp_avg_temp > temp_limit) {
611 dev_info(&ips->dev->dev,
612 "%sAvg temp %u, limit %u\n", msg, ips->mcp_avg_temp,
613 temp_limit);
aa7ffc01 614 ret = true;
a8c096ad 615 }
aa7ffc01 616
a8c096ad
TG		 617 avg_power = ips->cpu_avg_power + ips->mch_avg_power;
618 if (avg_power > ips->mcp_power_limit) {
1a14703d 619 dev_info(&ips->dev->dev,
a8c096ad
TG		 620 "%sAvg power %u, limit %u\n", msg, avg_power,
621 ips->mcp_power_limit);
622 ret = true;
623 }
624
625 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
aa7ffc01
JB		 626
627 return ret;
628}
629
630/**
631 * cpu_exceeded - check whether a CPU core is outside its limits
632 * @ips: IPS driver struct
633 * @cpu: CPU number to check
634 *
635 * Check a given CPU's average temp or power is over its limit.
636 */
637static bool cpu_exceeded(struct ips_driver *ips, int cpu)
638{
639 unsigned long flags;
640 int avg;
641 bool ret = false;
642
643 spin_lock_irqsave(&ips->turbo_status_lock, flags);
644 avg = cpu ? ips->ctv2_avg_temp : ips->ctv1_avg_temp;
645 if (avg > (ips->limits->core_temp_limit * 100))
646 ret = true;
0385e521 647 if (ips->cpu_avg_power > ips->core_power_limit * 100)
aa7ffc01
JB		 648 ret = true;
649 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
650
651 if (ret)
1a14703d 652 dev_info(&ips->dev->dev,
aa7ffc01
JB		 653 "CPU power or thermal limit exceeded\n");
654
655 return ret;
656}
657
658/**
659 * mch_exceeded - check whether the GPU is over budget
660 * @ips: IPS driver struct
661 *
662 * Check the MCH temp & power against their maximums.
663 */
664static bool mch_exceeded(struct ips_driver *ips)
665{
666 unsigned long flags;
667 bool ret = false;
668
669 spin_lock_irqsave(&ips->turbo_status_lock, flags);
670 if (ips->mch_avg_temp > (ips->limits->mch_temp_limit * 100))
671 ret = true;
0385e521
JB		 672 if (ips->mch_avg_power > ips->mch_power_limit)
673 ret = true;
aa7ffc01
JB		 674 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
675
676 return ret;
677}
678
eceab272
JB		 679/**
680 * verify_limits - verify BIOS provided limits
681 * @ips: IPS structure
682 *
683 * BIOS can optionally provide non-default limits for power and temp. Check
684 * them here and use the defaults if the BIOS values are not provided or
685 * are otherwise unusable.
686 */
687static void verify_limits(struct ips_driver *ips)
688{
689 if (ips->mcp_power_limit < ips->limits->mcp_power_limit ||
690 ips->mcp_power_limit > 35000)
691 ips->mcp_power_limit = ips->limits->mcp_power_limit;
692
693 if (ips->mcp_temp_limit < ips->limits->core_temp_limit ||
694 ips->mcp_temp_limit < ips->limits->mch_temp_limit ||
695 ips->mcp_temp_limit > 150)
696 ips->mcp_temp_limit = min(ips->limits->core_temp_limit,
697 ips->limits->mch_temp_limit);
698}
699
aa7ffc01
JB		 700/**
701 * update_turbo_limits - get various limits & settings from regs
702 * @ips: IPS driver struct
703 *
704 * Update the IPS power & temp limits, along with turbo enable flags,
705 * based on latest register contents.
706 *
707 * Used at init time and for runtime BIOS support, which requires polling
708 * the regs for updates (as a result of AC->DC transition for example).
709 *
710 * LOCKING:
711 * Caller must hold turbo_status_lock (outside of init)
712 */
713static void update_turbo_limits(struct ips_driver *ips)
714{
715 u32 hts = thm_readl(THM_HTS);
716
717 ips->cpu_turbo_enabled = !(hts & HTS_PCTD_DIS);
96f3823f
JB		 718 /*
719 * Disable turbo for now, until we can figure out why the power figures
720 * are wrong
721 */
722 ips->cpu_turbo_enabled = false;
723
070c0ee1
AW		 724 if (ips->gpu_busy)
725 ips->gpu_turbo_enabled = !(hts & HTS_GTD_DIS);
96f3823f 726
aa7ffc01
JB		 727 ips->core_power_limit = thm_readw(THM_MPCPC);
728 ips->mch_power_limit = thm_readw(THM_MMGPC);
729 ips->mcp_temp_limit = thm_readw(THM_PTL);
730 ips->mcp_power_limit = thm_readw(THM_MPPC);
731
eceab272 732 verify_limits(ips);
aa7ffc01
JB		 733 /* Ignore BIOS CPU vs GPU pref */
734}
735
736/**
737 * ips_adjust - adjust power clamp based on thermal state
738 * @data: ips driver structure
739 *
740 * Wake up every 5s or so and check whether we should adjust the power clamp.
741 * Check CPU and GPU load to determine which needs adjustment. There are
742 * several things to consider here:
743 * - do we need to adjust up or down?
744 * - is CPU busy?
745 * - is GPU busy?
746 * - is CPU in turbo?
747 * - is GPU in turbo?
748 * - is CPU or GPU preferred? (CPU is default)
749 *
750 * So, given the above, we do the following:
751 * - up (TDP available)
752 * - CPU not busy, GPU not busy - nothing
753 * - CPU busy, GPU not busy - adjust CPU up
754 * - CPU not busy, GPU busy - adjust GPU up
755 * - CPU busy, GPU busy - adjust preferred unit up, taking headroom from
756 * non-preferred unit if necessary
757 * - down (at TDP limit)
758 * - adjust both CPU and GPU down if possible
759 *
760 cpu+ gpu+ cpu+gpu- cpu-gpu+ cpu-gpu-
761cpu < gpu < cpu+gpu+ cpu+ gpu+ nothing
762cpu < gpu >= cpu+gpu-(mcp<) cpu+gpu-(mcp<) gpu- gpu-
763cpu >= gpu < cpu-gpu+(mcp<) cpu- cpu-gpu+(mcp<) cpu-
764cpu >= gpu >= cpu-gpu- cpu-gpu- cpu-gpu- cpu-gpu-
765 *
766 */
767static int ips_adjust(void *data)
768{
769 struct ips_driver *ips = data;
770 unsigned long flags;
771
772 dev_dbg(&ips->dev->dev, "starting ips-adjust thread\n");
773
774 /*
775 * Adjust CPU and GPU clamps every 5s if needed. Doing it more
776 * often isn't recommended due to ME interaction.
777 */
778 do {
779 bool cpu_busy = ips_cpu_busy(ips);
780 bool gpu_busy = ips_gpu_busy(ips);
781
782 spin_lock_irqsave(&ips->turbo_status_lock, flags);
783 if (ips->poll_turbo_status)
784 update_turbo_limits(ips);
785 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
786
787 /* Update turbo status if necessary */
788 if (ips->cpu_turbo_enabled)
789 ips_enable_cpu_turbo(ips);
790 else
791 ips_disable_cpu_turbo(ips);
792
793 if (ips->gpu_turbo_enabled)
794 ips_enable_gpu_turbo(ips);
795 else
796 ips_disable_gpu_turbo(ips);
797
798 /* We're outside our comfort zone, crank them down */
0385e521 799 if (mcp_exceeded(ips)) {
aa7ffc01
JB		 800 ips_cpu_lower(ips);
801 ips_gpu_lower(ips);
802 goto sleep;
803 }
804
805 if (!cpu_exceeded(ips, 0) && cpu_busy)
806 ips_cpu_raise(ips);
807 else
808 ips_cpu_lower(ips);
809
810 if (!mch_exceeded(ips) && gpu_busy)
811 ips_gpu_raise(ips);
812 else
813 ips_gpu_lower(ips);
814
815sleep:
816 schedule_timeout_interruptible(msecs_to_jiffies(IPS_ADJUST_PERIOD));
817 } while (!kthread_should_stop());
818
819 dev_dbg(&ips->dev->dev, "ips-adjust thread stopped\n");
820
821 return 0;
822}
823
824/*
825 * Helpers for reading out temp/power values and calculating their
826 * averages for the decision making and monitoring functions.
827 */
828
829static u16 calc_avg_temp(struct ips_driver *ips, u16 *array)
830{
831 u64 total = 0;
832 int i;
833 u16 avg;
834
835 for (i = 0; i < IPS_SAMPLE_COUNT; i++)
836 total += (u64)(array[i] * 100);
837
838 do_div(total, IPS_SAMPLE_COUNT);
839
840 avg = (u16)total;
841
842 return avg;
843}
844
845static u16 read_mgtv(struct ips_driver *ips)
846{
847 u16 ret;
848 u64 slope, offset;
849 u64 val;
850
851 val = thm_readq(THM_MGTV);
852 val = (val & TV_MASK) >> TV_SHIFT;
853
854 slope = offset = thm_readw(THM_MGTA);
855 slope = (slope & MGTA_SLOPE_MASK) >> MGTA_SLOPE_SHIFT;
856 offset = offset & MGTA_OFFSET_MASK;
857
858 ret = ((val * slope + 0x40) >> 7) + offset;
859
0385e521 860 return 0; /* MCH temp reporting buggy */
aa7ffc01
JB		 861}
862
863static u16 read_ptv(struct ips_driver *ips)
864{
865 u16 val, slope, offset;
866
867 slope = (ips->pta_val & PTA_SLOPE_MASK) >> PTA_SLOPE_SHIFT;
868 offset = ips->pta_val & PTA_OFFSET_MASK;
869
870 val = thm_readw(THM_PTV) & PTV_MASK;
871
872 return val;
873}
874
875static u16 read_ctv(struct ips_driver *ips, int cpu)
876{
877 int reg = cpu ? THM_CTV2 : THM_CTV1;
878 u16 val;
879
880 val = thm_readw(reg);
881 if (!(val & CTV_TEMP_ERROR))
882 val = (val) >> 6; /* discard fractional component */
883 else
884 val = 0;
885
886 return val;
887}
888
889static u32 get_cpu_power(struct ips_driver *ips, u32 *last, int period)
890{
891 u32 val;
892 u32 ret;
893
894 /*
895 * CEC is in joules/65535. Take difference over time to
896 * get watts.
897 */
898 val = thm_readl(THM_CEC);
899
900 /* period is in ms and we want mW */
901 ret = (((val - *last) * 1000) / period);
902 ret = (ret * 1000) / 65535;
903 *last = val;
904
96f3823f 905 return 0;
aa7ffc01
JB		 906}
907
908static const u16 temp_decay_factor = 2;
909static u16 update_average_temp(u16 avg, u16 val)
910{
911 u16 ret;
912
913 /* Multiply by 100 for extra precision */
914 ret = (val * 100 / temp_decay_factor) +
915 (((temp_decay_factor - 1) * avg) / temp_decay_factor);
916 return ret;
917}
918
919static const u16 power_decay_factor = 2;
920static u16 update_average_power(u32 avg, u32 val)
921{
922 u32 ret;
923
924 ret = (val / power_decay_factor) +
925 (((power_decay_factor - 1) * avg) / power_decay_factor);
926
927 return ret;
928}
929
930static u32 calc_avg_power(struct ips_driver *ips, u32 *array)
931{
932 u64 total = 0;
933 u32 avg;
934 int i;
935
936 for (i = 0; i < IPS_SAMPLE_COUNT; i++)
937 total += array[i];
938
939 do_div(total, IPS_SAMPLE_COUNT);
940 avg = (u32)total;
941
942 return avg;
943}
944
945static void monitor_timeout(unsigned long arg)
946{
947 wake_up_process((struct task_struct *)arg);
948}
949
950/**
951 * ips_monitor - temp/power monitoring thread
952 * @data: ips driver structure
953 *
954 * This is the main function for the IPS driver. It monitors power and
955 * tempurature in the MCP and adjusts CPU and GPU power clams accordingly.
956 *
957 * We keep a 5s moving average of power consumption and tempurature. Using
958 * that data, along with CPU vs GPU preference, we adjust the power clamps
959 * up or down.
960 */
961static int ips_monitor(void *data)
962{
963 struct ips_driver *ips = data;
964 struct timer_list timer;
965 unsigned long seqno_timestamp, expire, last_msecs, last_sample_period;
966 int i;
e9ec7f35
JS		 967 u32 *cpu_samples, *mchp_samples, old_cpu_power;
968 u16 *mcp_samples, *ctv1_samples, *ctv2_samples, *mch_samples;
aa7ffc01
JB		 969 u8 cur_seqno, last_seqno;
970
971 mcp_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
972 ctv1_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
973 ctv2_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
974 mch_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
975 cpu_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL);
976 mchp_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL);
e9ec7f35
JS		 977 if (!mcp_samples || !ctv1_samples || !ctv2_samples || !mch_samples ||
978 !cpu_samples || !mchp_samples) {
aa7ffc01
JB		 979 dev_err(&ips->dev->dev,
980 "failed to allocate sample array, ips disabled\n");
981 kfree(mcp_samples);
982 kfree(ctv1_samples);
983 kfree(ctv2_samples);
984 kfree(mch_samples);
985 kfree(cpu_samples);
e9ec7f35 986 kfree(mchp_samples);
aa7ffc01
JB		 987 return -ENOMEM;
988 }
989
990 last_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >>
991 ITV_ME_SEQNO_SHIFT;
992 seqno_timestamp = get_jiffies_64();
993
c21eae4f 994 old_cpu_power = thm_readl(THM_CEC);
aa7ffc01
JB		 995 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
996
997 /* Collect an initial average */
998 for (i = 0; i < IPS_SAMPLE_COUNT; i++) {
999 u32 mchp, cpu_power;
1000 u16 val;
1001
1002 mcp_samples[i] = read_ptv(ips);
1003
1004 val = read_ctv(ips, 0);
1005 ctv1_samples[i] = val;
1006
1007 val = read_ctv(ips, 1);
1008 ctv2_samples[i] = val;
1009
1010 val = read_mgtv(ips);
1011 mch_samples[i] = val;
1012
1013 cpu_power = get_cpu_power(ips, &old_cpu_power,
1014 IPS_SAMPLE_PERIOD);
1015 cpu_samples[i] = cpu_power;
1016
1017 if (ips->read_mch_val) {
1018 mchp = ips->read_mch_val();
1019 mchp_samples[i] = mchp;
1020 }
1021
1022 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
1023 if (kthread_should_stop())
1024 break;
1025 }
1026
1027 ips->mcp_avg_temp = calc_avg_temp(ips, mcp_samples);
1028 ips->ctv1_avg_temp = calc_avg_temp(ips, ctv1_samples);
1029 ips->ctv2_avg_temp = calc_avg_temp(ips, ctv2_samples);
1030 ips->mch_avg_temp = calc_avg_temp(ips, mch_samples);
1031 ips->cpu_avg_power = calc_avg_power(ips, cpu_samples);
1032 ips->mch_avg_power = calc_avg_power(ips, mchp_samples);
1033 kfree(mcp_samples);
1034 kfree(ctv1_samples);
1035 kfree(ctv2_samples);
1036 kfree(mch_samples);
1037 kfree(cpu_samples);
1038 kfree(mchp_samples);
1039
1040 /* Start the adjustment thread now that we have data */
1041 wake_up_process(ips->adjust);
1042
1043 /*
1044 * Ok, now we have an initial avg. From here on out, we track the
1045 * running avg using a decaying average calculation. This allows
1046 * us to reduce the sample frequency if the CPU and GPU are idle.
1047 */
1048 old_cpu_power = thm_readl(THM_CEC);
1049 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
1050 last_sample_period = IPS_SAMPLE_PERIOD;
1051
1052 setup_deferrable_timer_on_stack(&timer, monitor_timeout,
1053 (unsigned long)current);
1054 do {
1055 u32 cpu_val, mch_val;
1056 u16 val;
1057
1058 /* MCP itself */
1059 val = read_ptv(ips);
1060 ips->mcp_avg_temp = update_average_temp(ips->mcp_avg_temp, val);
1061
1062 /* Processor 0 */
1063 val = read_ctv(ips, 0);
1064 ips->ctv1_avg_temp =
1065 update_average_temp(ips->ctv1_avg_temp, val);
1066 /* Power */
1067 cpu_val = get_cpu_power(ips, &old_cpu_power,
1068 last_sample_period);
1069 ips->cpu_avg_power =
1070 update_average_power(ips->cpu_avg_power, cpu_val);
1071
1072 if (ips->second_cpu) {
1073 /* Processor 1 */
1074 val = read_ctv(ips, 1);
1075 ips->ctv2_avg_temp =
1076 update_average_temp(ips->ctv2_avg_temp, val);
1077 }
1078
1079 /* MCH */
1080 val = read_mgtv(ips);
1081 ips->mch_avg_temp = update_average_temp(ips->mch_avg_temp, val);
1082 /* Power */
1083 if (ips->read_mch_val) {
1084 mch_val = ips->read_mch_val();
1085 ips->mch_avg_power =
1086 update_average_power(ips->mch_avg_power,
1087 mch_val);
1088 }
1089
1090 /*
1091 * Make sure ME is updating thermal regs.
1092 * Note:
1093 * If it's been more than a second since the last update,
1094 * the ME is probably hung.
1095 */
1096 cur_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >>
1097 ITV_ME_SEQNO_SHIFT;
1098 if (cur_seqno == last_seqno &&
1099 time_after(jiffies, seqno_timestamp + HZ)) {
1100 dev_warn(&ips->dev->dev, "ME failed to update for more than 1s, likely hung\n");
1101 } else {
1102 seqno_timestamp = get_jiffies_64();
1103 last_seqno = cur_seqno;
1104 }
1105
1106 last_msecs = jiffies_to_msecs(jiffies);
1107 expire = jiffies + msecs_to_jiffies(IPS_SAMPLE_PERIOD);
1108
1109 __set_current_state(TASK_UNINTERRUPTIBLE);
1110 mod_timer(&timer, expire);
1111 schedule();
1112
1113 /* Calculate actual sample period for power averaging */
1114 last_sample_period = jiffies_to_msecs(jiffies) - last_msecs;
1115 if (!last_sample_period)
1116 last_sample_period = 1;
1117 } while (!kthread_should_stop());
1118
1119 del_timer_sync(&timer);
1120 destroy_timer_on_stack(&timer);
1121
1122 dev_dbg(&ips->dev->dev, "ips-monitor thread stopped\n");
1123
1124 return 0;
1125}
1126
1127#if 0
1128#define THM_DUMPW(reg) \
1129 { \
1130 u16 val = thm_readw(reg); \
1131 dev_dbg(&ips->dev->dev, #reg ": 0x%04x\n", val); \
1132 }
1133#define THM_DUMPL(reg) \
1134 { \
1135 u32 val = thm_readl(reg); \
1136 dev_dbg(&ips->dev->dev, #reg ": 0x%08x\n", val); \
1137 }
1138#define THM_DUMPQ(reg) \
1139 { \
1140 u64 val = thm_readq(reg); \
1141 dev_dbg(&ips->dev->dev, #reg ": 0x%016x\n", val); \
1142 }
1143
1144static void dump_thermal_info(struct ips_driver *ips)
1145{
1146 u16 ptl;
1147
1148 ptl = thm_readw(THM_PTL);
1149 dev_dbg(&ips->dev->dev, "Processor temp limit: %d\n", ptl);
1150
1151 THM_DUMPW(THM_CTA);
1152 THM_DUMPW(THM_TRC);
1153 THM_DUMPW(THM_CTV1);
1154 THM_DUMPL(THM_STS);
1155 THM_DUMPW(THM_PTV);
1156 THM_DUMPQ(THM_MGTV);
1157}
1158#endif
1159
1160/**
1161 * ips_irq_handler - handle temperature triggers and other IPS events
1162 * @irq: irq number
1163 * @arg: unused
1164 *
1165 * Handle temperature limit trigger events, generally by lowering the clamps.
1166 * If we're at a critical limit, we clamp back to the lowest possible value
1167 * to prevent emergency shutdown.
1168 */
1169static irqreturn_t ips_irq_handler(int irq, void *arg)
1170{
1171 struct ips_driver *ips = arg;
1172 u8 tses = thm_readb(THM_TSES);
1173 u8 tes = thm_readb(THM_TES);
1174
1175 if (!tses && !tes)
1176 return IRQ_NONE;
1177
1178 dev_info(&ips->dev->dev, "TSES: 0x%02x\n", tses);
1179 dev_info(&ips->dev->dev, "TES: 0x%02x\n", tes);
1180
1181 /* STS update from EC? */
1182 if (tes & 1) {
1183 u32 sts, tc1;
1184
1185 sts = thm_readl(THM_STS);
1186 tc1 = thm_readl(THM_TC1);
1187
1188 if (sts & STS_NVV) {
1189 spin_lock(&ips->turbo_status_lock);
1190 ips->core_power_limit = (sts & STS_PCPL_MASK) >>
1191 STS_PCPL_SHIFT;
1192 ips->mch_power_limit = (sts & STS_GPL_MASK) >>
1193 STS_GPL_SHIFT;
1194 /* ignore EC CPU vs GPU pref */
1195 ips->cpu_turbo_enabled = !(sts & STS_PCTD_DIS);
96f3823f
JB		 1196 /*
1197 * Disable turbo for now, until we can figure
1198 * out why the power figures are wrong
1199 */
1200 ips->cpu_turbo_enabled = false;
070c0ee1
AW		 1201 if (ips->gpu_busy)
1202 ips->gpu_turbo_enabled = !(sts & STS_GTD_DIS);
aa7ffc01
JB		 1203 ips->mcp_temp_limit = (sts & STS_PTL_MASK) >>
1204 STS_PTL_SHIFT;
1205 ips->mcp_power_limit = (tc1 & STS_PPL_MASK) >>
1206 STS_PPL_SHIFT;
eceab272 1207 verify_limits(ips);
aa7ffc01
JB		 1208 spin_unlock(&ips->turbo_status_lock);
1209
1210 thm_writeb(THM_SEC, SEC_ACK);
1211 }
1212 thm_writeb(THM_TES, tes);
1213 }
1214
1215 /* Thermal trip */
1216 if (tses) {
1217 dev_warn(&ips->dev->dev,
1218 "thermal trip occurred, tses: 0x%04x\n", tses);
1219 thm_writeb(THM_TSES, tses);
1220 }
1221
1222 return IRQ_HANDLED;
1223}
1224
1225#ifndef CONFIG_DEBUG_FS
1226static void ips_debugfs_init(struct ips_driver *ips) { return; }
1227static void ips_debugfs_cleanup(struct ips_driver *ips) { return; }
1228#else
1229
1230/* Expose current state and limits in debugfs if possible */
1231
1232struct ips_debugfs_node {
1233 struct ips_driver *ips;
1234 char *name;
1235 int (*show)(struct seq_file *m, void *data);
1236};
1237
1238static int show_cpu_temp(struct seq_file *m, void *data)
1239{
1240 struct ips_driver *ips = m->private;
1241
1242 seq_printf(m, "%d.%02d\n", ips->ctv1_avg_temp / 100,
1243 ips->ctv1_avg_temp % 100);
1244
1245 return 0;
1246}
1247
1248static int show_cpu_power(struct seq_file *m, void *data)
1249{
1250 struct ips_driver *ips = m->private;
1251
1252 seq_printf(m, "%dmW\n", ips->cpu_avg_power);
1253
1254 return 0;
1255}
1256
1257static int show_cpu_clamp(struct seq_file *m, void *data)
1258{
1259 u64 turbo_override;
1260 int tdp, tdc;
1261
1262 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1263
1264 tdp = (int)(turbo_override & TURBO_TDP_MASK);
1265 tdc = (int)((turbo_override & TURBO_TDC_MASK) >> TURBO_TDC_SHIFT);
1266
1267 /* Convert to .1W/A units */
1268 tdp = tdp * 10 / 8;
1269 tdc = tdc * 10 / 8;
1270
1271 /* Watts Amperes */
1272 seq_printf(m, "%d.%dW %d.%dA\n", tdp / 10, tdp % 10,
1273 tdc / 10, tdc % 10);
1274
1275 return 0;
1276}
1277
1278static int show_mch_temp(struct seq_file *m, void *data)
1279{
1280 struct ips_driver *ips = m->private;
1281
1282 seq_printf(m, "%d.%02d\n", ips->mch_avg_temp / 100,
1283 ips->mch_avg_temp % 100);
1284
1285 return 0;
1286}
1287
1288static int show_mch_power(struct seq_file *m, void *data)
1289{
1290 struct ips_driver *ips = m->private;
1291
1292 seq_printf(m, "%dmW\n", ips->mch_avg_power);
1293
1294 return 0;
1295}
1296
1297static struct ips_debugfs_node ips_debug_files[] = {
1298 { NULL, "cpu_temp", show_cpu_temp },
1299 { NULL, "cpu_power", show_cpu_power },
1300 { NULL, "cpu_clamp", show_cpu_clamp },
1301 { NULL, "mch_temp", show_mch_temp },
1302 { NULL, "mch_power", show_mch_power },
1303};
1304
1305static int ips_debugfs_open(struct inode *inode, struct file *file)
1306{
1307 struct ips_debugfs_node *node = inode->i_private;
1308
1309 return single_open(file, node->show, node->ips);
1310}
1311
1312static const struct file_operations ips_debugfs_ops = {
1313 .owner = THIS_MODULE,
1314 .open = ips_debugfs_open,
1315 .read = seq_read,
1316 .llseek = seq_lseek,
1317 .release = single_release,
1318};
1319
1320static void ips_debugfs_cleanup(struct ips_driver *ips)
1321{
1322 if (ips->debug_root)
1323 debugfs_remove_recursive(ips->debug_root);
1324 return;
1325}
1326
1327static void ips_debugfs_init(struct ips_driver *ips)
1328{
1329 int i;
1330
1331 ips->debug_root = debugfs_create_dir("ips", NULL);
1332 if (!ips->debug_root) {
1333 dev_err(&ips->dev->dev,
1334 "failed to create debugfs entries: %ld\n",
1335 PTR_ERR(ips->debug_root));
1336 return;
1337 }
1338
1339 for (i = 0; i < ARRAY_SIZE(ips_debug_files); i++) {
1340 struct dentry *ent;
1341 struct ips_debugfs_node *node = &ips_debug_files[i];
1342
1343 node->ips = ips;
1344 ent = debugfs_create_file(node->name, S_IFREG | S_IRUGO,
1345 ips->debug_root, node,
1346 &ips_debugfs_ops);
1347 if (!ent) {
1348 dev_err(&ips->dev->dev,
1349 "failed to create debug file: %ld\n",
1350 PTR_ERR(ent));
1351 goto err_cleanup;
1352 }
1353 }
1354
1355 return;
1356
1357err_cleanup:
1358 ips_debugfs_cleanup(ips);
1359 return;
1360}
1361#endif /* CONFIG_DEBUG_FS */
1362
1363/**
1364 * ips_detect_cpu - detect whether CPU supports IPS
1365 *
1366 * Walk our list and see if we're on a supported CPU. If we find one,
1367 * return the limits for it.
1368 */
1369static struct ips_mcp_limits *ips_detect_cpu(struct ips_driver *ips)
1370{
1371 u64 turbo_power, misc_en;
1372 struct ips_mcp_limits *limits = NULL;
1373 u16 tdp;
1374
1375 if (!(boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 37)) {
1376 dev_info(&ips->dev->dev, "Non-IPS CPU detected.\n");
1377 goto out;
1378 }
1379
1380 rdmsrl(IA32_MISC_ENABLE, misc_en);
1381 /*
1382 * If the turbo enable bit isn't set, we shouldn't try to enable/disable
1383 * turbo manually or we'll get an illegal MSR access, even though
1384 * turbo will still be available.
1385 */
354aeeb1
JB		 1386 if (misc_en & IA32_MISC_TURBO_EN)
1387 ips->turbo_toggle_allowed = true;
1388 else
1389 ips->turbo_toggle_allowed = false;
aa7ffc01
JB		 1390
1391 if (strstr(boot_cpu_data.x86_model_id, "CPU M"))
1392 limits = &ips_sv_limits;
1393 else if (strstr(boot_cpu_data.x86_model_id, "CPU L"))
1394 limits = &ips_lv_limits;
1395 else if (strstr(boot_cpu_data.x86_model_id, "CPU U"))
1396 limits = &ips_ulv_limits;
52d7ee55 1397 else {
aa7ffc01 1398 dev_info(&ips->dev->dev, "No CPUID match found.\n");
52d7ee55
DC		 1399 goto out;
1400 }
aa7ffc01
JB		 1401
1402 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_power);
1403 tdp = turbo_power & TURBO_TDP_MASK;
1404
1405 /* Sanity check TDP against CPU */
4fd07ac0
JB		 1406 if (limits->core_power_limit != (tdp / 8) * 1000) {
1407 dev_info(&ips->dev->dev, "CPU TDP doesn't match expected value (found %d, expected %d)\n",
1408 tdp / 8, limits->core_power_limit / 1000);
1409 limits->core_power_limit = (tdp / 8) * 1000;
aa7ffc01
JB		 1410 }
1411
1412out:
1413 return limits;
1414}
1415
1416/**
1417 * ips_get_i915_syms - try to get GPU control methods from i915 driver
1418 * @ips: IPS driver
1419 *
1420 * The i915 driver exports several interfaces to allow the IPS driver to
1421 * monitor and control graphics turbo mode. If we can find them, we can
1422 * enable graphics turbo, otherwise we must disable it to avoid exceeding
1423 * thermal and power limits in the MCP.
1424 */
1425static bool ips_get_i915_syms(struct ips_driver *ips)
1426{
1427 ips->read_mch_val = symbol_get(i915_read_mch_val);
1428 if (!ips->read_mch_val)
1429 goto out_err;
1430 ips->gpu_raise = symbol_get(i915_gpu_raise);
1431 if (!ips->gpu_raise)
1432 goto out_put_mch;
1433 ips->gpu_lower = symbol_get(i915_gpu_lower);
1434 if (!ips->gpu_lower)
1435 goto out_put_raise;
1436 ips->gpu_busy = symbol_get(i915_gpu_busy);
1437 if (!ips->gpu_busy)
1438 goto out_put_lower;
1439 ips->gpu_turbo_disable = symbol_get(i915_gpu_turbo_disable);
1440 if (!ips->gpu_turbo_disable)
1441 goto out_put_busy;
1442
1443 return true;
1444
1445out_put_busy:
fed522f7 1446 symbol_put(i915_gpu_busy);
aa7ffc01
JB		 1447out_put_lower:
1448 symbol_put(i915_gpu_lower);
1449out_put_raise:
1450 symbol_put(i915_gpu_raise);
1451out_put_mch:
1452 symbol_put(i915_read_mch_val);
1453out_err:
1454 return false;
1455}
1456
1457static DEFINE_PCI_DEVICE_TABLE(ips_id_table) = {
1458 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
1459 PCI_DEVICE_ID_INTEL_THERMAL_SENSOR), },
1460 { 0, }
1461};
1462
1463MODULE_DEVICE_TABLE(pci, ips_id_table);
1464
1465static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id)
1466{
1467 u64 platform_info;
1468 struct ips_driver *ips;
1469 u32 hts;
1470 int ret = 0;
1471 u16 htshi, trc, trc_required_mask;
1472 u8 tse;
1473
1474 ips = kzalloc(sizeof(struct ips_driver), GFP_KERNEL);
1475 if (!ips)
1476 return -ENOMEM;
1477
1478 pci_set_drvdata(dev, ips);
1479 ips->dev = dev;
1480
1481 ips->limits = ips_detect_cpu(ips);
1482 if (!ips->limits) {
1483 dev_info(&dev->dev, "IPS not supported on this CPU\n");
1484 ret = -ENXIO;
1485 goto error_free;
1486 }
1487
1488 spin_lock_init(&ips->turbo_status_lock);
1489
5629236b
KV		 1490 ret = pci_enable_device(dev);
1491 if (ret) {
1492 dev_err(&dev->dev, "can't enable PCI device, aborting\n");
1493 goto error_free;
1494 }
1495
aa7ffc01
JB		 1496 if (!pci_resource_start(dev, 0)) {
1497 dev_err(&dev->dev, "TBAR not assigned, aborting\n");
1498 ret = -ENXIO;
1499 goto error_free;
1500 }
1501
1502 ret = pci_request_regions(dev, "ips thermal sensor");
1503 if (ret) {
1504 dev_err(&dev->dev, "thermal resource busy, aborting\n");
1505 goto error_free;
1506 }
1507
aa7ffc01
JB		 1508
1509 ips->regmap = ioremap(pci_resource_start(dev, 0),
1510 pci_resource_len(dev, 0));
1511 if (!ips->regmap) {
1512 dev_err(&dev->dev, "failed to map thermal regs, aborting\n");
1513 ret = -EBUSY;
1514 goto error_release;
1515 }
1516
1517 tse = thm_readb(THM_TSE);
1518 if (tse != TSE_EN) {
1519 dev_err(&dev->dev, "thermal device not enabled (0x%02x), aborting\n", tse);
1520 ret = -ENXIO;
1521 goto error_unmap;
1522 }
1523
1524 trc = thm_readw(THM_TRC);
1525 trc_required_mask = TRC_CORE1_EN | TRC_CORE_PWR | TRC_MCH_EN;
1526 if ((trc & trc_required_mask) != trc_required_mask) {
1527 dev_err(&dev->dev, "thermal reporting for required devices not enabled, aborting\n");
1528 ret = -ENXIO;
1529 goto error_unmap;
1530 }
1531
1532 if (trc & TRC_CORE2_EN)
1533 ips->second_cpu = true;
1534
aa7ffc01
JB		 1535 update_turbo_limits(ips);
1536 dev_dbg(&dev->dev, "max cpu power clamp: %dW\n",
1537 ips->mcp_power_limit / 10);
1538 dev_dbg(&dev->dev, "max core power clamp: %dW\n",
1539 ips->core_power_limit / 10);
1540 /* BIOS may update limits at runtime */
1541 if (thm_readl(THM_PSC) & PSP_PBRT)
1542 ips->poll_turbo_status = true;
1543
0385e521
JB		 1544 if (!ips_get_i915_syms(ips)) {
1545 dev_err(&dev->dev, "failed to get i915 symbols, graphics turbo disabled\n");
1546 ips->gpu_turbo_enabled = false;
1547 } else {
1548 dev_dbg(&dev->dev, "graphics turbo enabled\n");
1549 ips->gpu_turbo_enabled = true;
1550 }
1551
aa7ffc01
JB		 1552 /*
1553 * Check PLATFORM_INFO MSR to make sure this chip is
1554 * turbo capable.
1555 */
1556 rdmsrl(PLATFORM_INFO, platform_info);
1557 if (!(platform_info & PLATFORM_TDP)) {
1558 dev_err(&dev->dev, "platform indicates TDP override unavailable, aborting\n");
1559 ret = -ENODEV;
1560 goto error_unmap;
1561 }
1562
1563 /*
1564 * IRQ handler for ME interaction
1565 * Note: don't use MSI here as the PCH has bugs.
1566 */
1567 pci_disable_msi(dev);
1568 ret = request_irq(dev->irq, ips_irq_handler, IRQF_SHARED, "ips",
1569 ips);
1570 if (ret) {
1571 dev_err(&dev->dev, "request irq failed, aborting\n");
1572 goto error_unmap;
1573 }
1574
1575 /* Enable aux, hot & critical interrupts */
1576 thm_writeb(THM_TSPIEN, TSPIEN_AUX2_LOHI | TSPIEN_CRIT_LOHI |
1577 TSPIEN_HOT_LOHI | TSPIEN_AUX_LOHI);
1578 thm_writeb(THM_TEN, TEN_UPDATE_EN);
1579
1580 /* Collect adjustment values */
1581 ips->cta_val = thm_readw(THM_CTA);
1582 ips->pta_val = thm_readw(THM_PTA);
1583 ips->mgta_val = thm_readw(THM_MGTA);
1584
1585 /* Save turbo limits & ratios */
1586 rdmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);
1587
96f3823f
JB		 1588 ips_disable_cpu_turbo(ips);
1589 ips->cpu_turbo_enabled = false;
aa7ffc01 1590
a7abda8d 1591 /* Create thermal adjust thread */
1592 ips->adjust = kthread_create(ips_adjust, ips, "ips-adjust");
1593 if (IS_ERR(ips->adjust)) {
aa7ffc01 1594 dev_err(&dev->dev,
a7abda8d 1595 "failed to create thermal adjust thread, aborting\n");
aa7ffc01
JB		 1596 ret = -ENOMEM;
1597 goto error_free_irq;
a7abda8d 1598
aa7ffc01
JB		 1599 }
1600
a7abda8d 1601 /*
1602 * Set up the work queue and monitor thread. The monitor thread
1603 * will wake up ips_adjust thread.
1604 */
1605 ips->monitor = kthread_run(ips_monitor, ips, "ips-monitor");
1606 if (IS_ERR(ips->monitor)) {
aa7ffc01 1607 dev_err(&dev->dev,
a7abda8d 1608 "failed to create thermal monitor thread, aborting\n");
aa7ffc01
JB		 1609 ret = -ENOMEM;
1610 goto error_thread_cleanup;
1611 }
1612
1613 hts = (ips->core_power_limit << HTS_PCPL_SHIFT) |
1614 (ips->mcp_temp_limit << HTS_PTL_SHIFT) | HTS_NVV;
1615 htshi = HTS2_PRST_RUNNING << HTS2_PRST_SHIFT;
1616
1617 thm_writew(THM_HTSHI, htshi);
1618 thm_writel(THM_HTS, hts);
1619
1620 ips_debugfs_init(ips);
1621
1622 dev_info(&dev->dev, "IPS driver initialized, MCP temp limit %d\n",
1623 ips->mcp_temp_limit);
1624 return ret;
1625
1626error_thread_cleanup:
a7abda8d 1627 kthread_stop(ips->adjust);
aa7ffc01
JB		 1628error_free_irq:
1629 free_irq(ips->dev->irq, ips);
1630error_unmap:
1631 iounmap(ips->regmap);
1632error_release:
1633 pci_release_regions(dev);
1634error_free:
1635 kfree(ips);
1636 return ret;
1637}
1638
1639static void ips_remove(struct pci_dev *dev)
1640{
1641 struct ips_driver *ips = pci_get_drvdata(dev);
1642 u64 turbo_override;
1643
1644 if (!ips)
1645 return;
1646
1647 ips_debugfs_cleanup(ips);
1648
1649 /* Release i915 driver */
1650 if (ips->read_mch_val)
1651 symbol_put(i915_read_mch_val);
1652 if (ips->gpu_raise)
1653 symbol_put(i915_gpu_raise);
1654 if (ips->gpu_lower)
1655 symbol_put(i915_gpu_lower);
1656 if (ips->gpu_busy)
1657 symbol_put(i915_gpu_busy);
1658 if (ips->gpu_turbo_disable)
1659 symbol_put(i915_gpu_turbo_disable);
1660
1661 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1662 turbo_override &= ~(TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN);
1663 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1664 wrmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);
1665
1666 free_irq(ips->dev->irq, ips);
1667 if (ips->adjust)
1668 kthread_stop(ips->adjust);
1669 if (ips->monitor)
1670 kthread_stop(ips->monitor);
1671 iounmap(ips->regmap);
1672 pci_release_regions(dev);
1673 kfree(ips);
1674 dev_dbg(&dev->dev, "IPS driver removed\n");
1675}
1676
1677#ifdef CONFIG_PM
1678static int ips_suspend(struct pci_dev *dev, pm_message_t state)
1679{
1680 return 0;
1681}
1682
1683static int ips_resume(struct pci_dev *dev)
1684{
1685 return 0;
1686}
1687#else
1688#define ips_suspend NULL
1689#define ips_resume NULL
1690#endif /* CONFIG_PM */
1691
1692static void ips_shutdown(struct pci_dev *dev)
1693{
1694}
1695
1696static struct pci_driver ips_pci_driver = {
1697 .name = "intel ips",
1698 .id_table = ips_id_table,
1699 .probe = ips_probe,
1700 .remove = ips_remove,
1701 .suspend = ips_suspend,
1702 .resume = ips_resume,
1703 .shutdown = ips_shutdown,
1704};
1705
1706static int __init ips_init(void)
1707{
1708 return pci_register_driver(&ips_pci_driver);
1709}
1710module_init(ips_init);
1711
1712static void ips_exit(void)
1713{
1714 pci_unregister_driver(&ips_pci_driver);
1715 return;
1716}
1717module_exit(ips_exit);
1718
1719MODULE_LICENSE("GPL");
1720MODULE_AUTHOR("Jesse Barnes <jbarnes@virtuousgeek.org>");
1721MODULE_DESCRIPTION("Intelligent Power Sharing Driver");
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