[net-next-2.6.git] / drivers / pcmcia / m32r_pcc.c

/*
 *  drivers/pcmcia/m32r_pcc.c
 *
 *  Device driver for the PCMCIA functionality of M32R.
 *
 *  Copyright (c) 2001, 2002, 2003, 2004
 *    Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/timer.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/bitops.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/addrspace.h>

#include <pcmcia/ss.h>
#include <pcmcia/cs.h>

/* XXX: should be moved into asm/irq.h */
#define PCC0_IRQ 24
#define PCC1_IRQ 25

#include "m32r_pcc.h"

#define CHAOS_PCC_DEBUG
#ifdef CHAOS_PCC_DEBUG
	static volatile u_short dummy_readbuf;
#endif

#define PCC_DEBUG_DBEX


/* Poll status interval -- 0 means default to interrupt */
static int poll_interval = 0;

typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;

typedef struct pcc_socket {
	u_short			type, flags;
	struct pcmcia_socket	socket;
	unsigned int		number;
	unsigned int		ioaddr;
	u_long			mapaddr;
	u_long			base;	/* PCC register base */
	u_char			cs_irq, intr;
	pccard_io_map		io_map[MAX_IO_WIN];
	pccard_mem_map		mem_map[MAX_WIN];
	u_char			io_win;
	u_char			mem_win;
	pcc_as_t		current_space;
	u_char			last_iodbex;
#ifdef CHAOS_PCC_DEBUG
	u_char			last_iosize;
#endif
#ifdef CONFIG_PROC_FS
	struct proc_dir_entry *proc;
#endif
} pcc_socket_t;

static int pcc_sockets = 0;
static pcc_socket_t socket[M32R_MAX_PCC] = {
	{ 0, }, /* ... */
};

/*====================================================================*/

static unsigned int pcc_get(u_short, unsigned int);
static void pcc_set(u_short, unsigned int , unsigned int );

static DEFINE_SPINLOCK(pcc_lock);

void pcc_iorw(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int wr, int flag)
{
	u_long addr;
	u_long flags;
	int need_ex;
#ifdef PCC_DEBUG_DBEX
	int _dbex;
#endif
	pcc_socket_t *t = &socket[sock];
#ifdef CHAOS_PCC_DEBUG
	int map_changed = 0;
#endif

	/* Need lock ? */
	spin_lock_irqsave(&pcc_lock, flags);

	/*
	 * Check if need dbex
	 */
	need_ex = (size > 1 && flag == 0) ? PCMOD_DBEX : 0;
#ifdef PCC_DEBUG_DBEX
	_dbex = need_ex;
	need_ex = 0;
#endif

	/*
	 * calculate access address
	 */
	addr = t->mapaddr + port - t->ioaddr + KSEG1; /* XXX */

	/*
	 * Check current mapping
	 */
	if (t->current_space != as_io || t->last_iodbex != need_ex) {

		u_long cbsz;

		/*
		 * Disable first
		 */
		pcc_set(sock, PCCR, 0);

		/*
		 * Set mode and io address
		 */
		cbsz = (t->flags & MAP_16BIT) ? 0 : PCMOD_CBSZ;
		pcc_set(sock, PCMOD, PCMOD_AS_IO | cbsz | need_ex);
		pcc_set(sock, PCADR, addr & 0x1ff00000);

		/*
		 * Enable and read it
		 */
		pcc_set(sock, PCCR, 1);

#ifdef CHAOS_PCC_DEBUG
#if 0
		map_changed = (t->current_space == as_attr && size == 2); /* XXX */
#else
		map_changed = 1;
#endif
#endif
		t->current_space = as_io;
	}

	/*
	 * access to IO space
	 */
	if (size == 1) {
		/* Byte */
		unsigned char *bp = (unsigned char *)buf;

#ifdef CHAOS_DEBUG
		if (map_changed) {
			dummy_readbuf = readb(addr);
		}
#endif
		if (wr) {
			/* write Byte */
			while (nmemb--) {
				writeb(*bp++, addr);
			}
		} else {
			/* read Byte */
			while (nmemb--) {
	    		*bp++ = readb(addr);
			}
		}
	} else {
		/* Word */
		unsigned short *bp = (unsigned short *)buf;

#ifdef CHAOS_PCC_DEBUG
		if (map_changed) {
			dummy_readbuf = readw(addr);
		}
#endif
		if (wr) {
			/* write Word */
			while (nmemb--) {
#ifdef PCC_DEBUG_DBEX
				if (_dbex) {
					unsigned char *cp = (unsigned char *)bp;
					unsigned short tmp;
					tmp = cp[1] << 8 | cp[0];
					writew(tmp, addr);
					bp++;
				} else
#endif
				writew(*bp++, addr);
	    	}
	    } else {
	    	/* read Word */
	    	while (nmemb--) {
#ifdef  PCC_DEBUG_DBEX
				if (_dbex) {
					unsigned char *cp = (unsigned char *)bp;
					unsigned short tmp;
					tmp = readw(addr);
					cp[0] = tmp & 0xff;
					cp[1] = (tmp >> 8) & 0xff;
					bp++;
				} else
#endif
				*bp++ = readw(addr);
	    	}
	    }
	}

#if 1
	/* addr is no longer used */
	if ((addr = pcc_get(sock, PCIRC)) & PCIRC_BWERR) {
	  printk("m32r_pcc: BWERR detected : port 0x%04lx : iosize %dbit\n",
			 port, size * 8);
	  pcc_set(sock, PCIRC, addr);
	}
#endif
	/*
	 * save state
	 */
	t->last_iosize = size;
	t->last_iodbex = need_ex;

	/* Need lock ? */

	spin_unlock_irqrestore(&pcc_lock,flags);

	return;
}

void pcc_ioread(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
	pcc_iorw(sock, port, buf, size, nmemb, 0, flag);
}

void pcc_iowrite(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
    pcc_iorw(sock, port, buf, size, nmemb, 1, flag);
}

/*====================================================================*/

#define IS_REGISTERED		0x2000
#define IS_ALIVE		0x8000

typedef struct pcc_t {
	char			*name;
	u_short			flags;
} pcc_t;

static pcc_t pcc[] = {
	{ "xnux2", 0 }, { "xnux2", 0 },
};

static irqreturn_t pcc_interrupt(int, void *);

/*====================================================================*/

static struct timer_list poll_timer;

static unsigned int pcc_get(u_short sock, unsigned int reg)
{
	return inl(socket[sock].base + reg);
}


static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
{
  	outl(data, socket[sock].base + reg);
}

/*======================================================================

	See if a card is present, powered up, in IO mode, and already
	bound to a (non PC Card) Linux driver.  We leave these alone.

	We make an exception for cards that seem to be serial devices.

======================================================================*/

static int __init is_alive(u_short sock)
{
	unsigned int stat;
	unsigned int f;

	stat = pcc_get(sock, PCIRC);
	f = (stat & (PCIRC_CDIN1 | PCIRC_CDIN2)) >> 16;
	if(!f){
		printk("m32r_pcc: No Card is detected at socket %d : stat = 0x%08x\n",stat,sock);
		return 0;
	}
	if(f!=3)
		printk("m32r_pcc: Insertion fail (%.8x) at socket %d\n",stat,sock);
	else
		printk("m32r_pcc: Card is Inserted at socket %d(%.8x)\n",sock,stat);
	return 0;
}

static void add_pcc_socket(ulong base, int irq, ulong mapaddr,
			   unsigned int ioaddr)
{
  	pcc_socket_t *t = &socket[pcc_sockets];

	/* add sockets */
	t->ioaddr = ioaddr;
	t->mapaddr = mapaddr;
	t->base = base;
#ifdef CHAOS_PCC_DEBUG
	t->flags = MAP_16BIT;
#else
	t->flags = 0;
#endif
	if (is_alive(pcc_sockets))
		t->flags |= IS_ALIVE;

	/* add pcc */
	if (t->base > 0) {
		request_region(t->base, 0x20, "m32r-pcc");
	}

	printk(KERN_INFO "  %s ", pcc[pcc_sockets].name);
	printk("pcc at 0x%08lx\n", t->base);

	/* Update socket interrupt information, capabilities */
	t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
	t->socket.map_size = M32R_PCC_MAPSIZE;
	t->socket.io_offset = ioaddr;	/* use for io access offset */
	t->socket.irq_mask = 0;
	t->socket.pci_irq = 2 + pcc_sockets; /* XXX */

	request_irq(irq, pcc_interrupt, 0, "m32r-pcc", pcc_interrupt);

	pcc_sockets++;

	return;
}


/*====================================================================*/

static irqreturn_t pcc_interrupt(int irq, void *dev)
{
	int i, j, irc;
	u_int events, active;
	int handled = 0;

	pr_debug("m32r_pcc: pcc_interrupt(%d)\n", irq);

	for (j = 0; j < 20; j++) {
		active = 0;
		for (i = 0; i < pcc_sockets; i++) {
			if ((socket[i].cs_irq != irq) &&
				(socket[i].socket.pci_irq != irq))
				continue;
			handled = 1;
			irc = pcc_get(i, PCIRC);
			irc >>=16;
			pr_debug("m32r_pcc: interrupt: socket %d pcirc 0x%02x ",
				i, irc);
			if (!irc)
				continue;

			events = (irc) ? SS_DETECT : 0;
			events |= (pcc_get(i,PCCR) & PCCR_PCEN) ? SS_READY : 0;
			pr_debug("m32r_pcc: event 0x%02x\n", events);

			if (events)
				pcmcia_parse_events(&socket[i].socket, events);

			active |= events;
			active = 0;
		}
		if (!active) break;
	}
	if (j == 20)
		printk(KERN_NOTICE "m32r-pcc: infinite loop in interrupt handler\n");

	pr_debug("m32r_pcc: interrupt done\n");

	return IRQ_RETVAL(handled);
} /* pcc_interrupt */

static void pcc_interrupt_wrapper(u_long data)
{
	pcc_interrupt(0, NULL);
	init_timer(&poll_timer);
	poll_timer.expires = jiffies + poll_interval;
	add_timer(&poll_timer);
}

/*====================================================================*/

static int _pcc_get_status(u_short sock, u_int *value)
{
	u_int status;

	status = pcc_get(sock,PCIRC);
	*value = ((status & PCIRC_CDIN1) && (status & PCIRC_CDIN2))
		? SS_DETECT : 0;

	status = pcc_get(sock,PCCR);

#if 0
	*value |= (status & PCCR_PCEN) ? SS_READY : 0;
#else
	*value |= SS_READY; /* XXX: always */
#endif

	status = pcc_get(sock,PCCSIGCR);
	*value |= (status & PCCSIGCR_VEN) ? SS_POWERON : 0;

	pr_debug("m32r_pcc: GetStatus(%d) = %#4.4x\n", sock, *value);
	return 0;
} /* _get_status */

/*====================================================================*/

static int _pcc_set_socket(u_short sock, socket_state_t *state)
{
	u_long reg = 0;

	pr_debug("m32r_pcc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
		  "io_irq %d, csc_mask %#2.2x)", sock, state->flags,
		  state->Vcc, state->Vpp, state->io_irq, state->csc_mask);

	if (state->Vcc) {
		/*
		 * 5V only
		 */
		if (state->Vcc == 50) {
			reg |= PCCSIGCR_VEN;
		} else {
			return -EINVAL;
		}
	}

	if (state->flags & SS_RESET) {
		pr_debug("m32r_pcc: :RESET\n");
		reg |= PCCSIGCR_CRST;
	}
	if (state->flags & SS_OUTPUT_ENA){
		pr_debug("m32r_pcc: :OUTPUT_ENA\n");
		/* bit clear */
	} else {
		reg |= PCCSIGCR_SEN;
	}

	pcc_set(sock,PCCSIGCR,reg);

	if(state->flags & SS_IOCARD){
		pr_debug("m32r_pcc: :IOCARD");
	}
	if (state->flags & SS_PWR_AUTO) {
		pr_debug("m32r_pcc: :PWR_AUTO");
	}
	if (state->csc_mask & SS_DETECT)
		pr_debug("m32r_pcc: :csc-SS_DETECT");
	if (state->flags & SS_IOCARD) {
		if (state->csc_mask & SS_STSCHG)
			pr_debug("m32r_pcc: :STSCHG");
	} else {
		if (state->csc_mask & SS_BATDEAD)
			pr_debug("m32r_pcc: :BATDEAD");
		if (state->csc_mask & SS_BATWARN)
			pr_debug("m32r_pcc: :BATWARN");
		if (state->csc_mask & SS_READY)
			pr_debug("m32r_pcc: :READY");
	}
	pr_debug("m32r_pcc: \n");
	return 0;
} /* _set_socket */

/*====================================================================*/

static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
{
	u_char map;

	pr_debug("m32r_pcc: SetIOMap(%d, %d, %#2.2x, %d ns, "
		  "%#llx-%#llx)\n", sock, io->map, io->flags,
		  io->speed, (unsigned long long)io->start,
		  (unsigned long long)io->stop);
	map = io->map;

	return 0;
} /* _set_io_map */

/*====================================================================*/

static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
{

	u_char map = mem->map;
	u_long mode;
	u_long addr;
	pcc_socket_t *t = &socket[sock];
#ifdef CHAOS_PCC_DEBUG
#if 0
	pcc_as_t last = t->current_space;
#endif
#endif

	pr_debug("m32r_pcc: SetMemMap(%d, %d, %#2.2x, %d ns, "
		 "%#llx,  %#x)\n", sock, map, mem->flags,
		 mem->speed, (unsigned long long)mem->static_start,
		 mem->card_start);

	/*
	 * sanity check
	 */
	if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
		return -EINVAL;
	}

	/*
	 * de-activate
	 */
	if ((mem->flags & MAP_ACTIVE) == 0) {
		t->current_space = as_none;
		return 0;
	}

	/*
	 * Disable first
	 */
	pcc_set(sock, PCCR, 0);

	/*
	 * Set mode
	 */
	if (mem->flags & MAP_ATTRIB) {
		mode = PCMOD_AS_ATTRIB | PCMOD_CBSZ;
		t->current_space = as_attr;
	} else {
		mode = 0; /* common memory */
		t->current_space = as_comm;
	}
	pcc_set(sock, PCMOD, mode);

	/*
	 * Set address
	 */
	addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
	pcc_set(sock, PCADR, addr);

	mem->static_start = addr + mem->card_start;

	/*
	 * Enable again
	 */
	pcc_set(sock, PCCR, 1);

#ifdef CHAOS_PCC_DEBUG
#if 0
	if (last != as_attr) {
#else
	if (1) {
#endif
		dummy_readbuf = *(u_char *)(addr + KSEG1);
	}
#endif

	return 0;

} /* _set_mem_map */

#if 0 /* driver model ordering issue */
/*======================================================================

	Routines for accessing socket information and register dumps via
	/proc/bus/pccard/...

======================================================================*/

static ssize_t show_info(struct class_device *class_dev, char *buf)
{
	pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
		socket.dev);

	return sprintf(buf, "type:     %s\nbase addr:    0x%08lx\n",
		pcc[s->type].name, s->base);
}

static ssize_t show_exca(struct class_device *class_dev, char *buf)
{
	/* FIXME */

	return 0;
}

static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
#endif

/*====================================================================*/

/* this is horribly ugly... proper locking needs to be done here at
 * some time... */
#define LOCKED(x) do {					\
	int retval;					\
	unsigned long flags;				\
	spin_lock_irqsave(&pcc_lock, flags);		\
	retval = x;					\
	spin_unlock_irqrestore(&pcc_lock, flags);	\
	return retval;					\
} while (0)


static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
{
	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;

	if (socket[sock].flags & IS_ALIVE) {
		*value = 0;
		return -EINVAL;
	}
	LOCKED(_pcc_get_status(sock, value));
}

static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
{
	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;

	if (socket[sock].flags & IS_ALIVE)
		return -EINVAL;

	LOCKED(_pcc_set_socket(sock, state));
}

static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
{
	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;

	if (socket[sock].flags & IS_ALIVE)
		return -EINVAL;
	LOCKED(_pcc_set_io_map(sock, io));
}

static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
{
	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;

	if (socket[sock].flags & IS_ALIVE)
		return -EINVAL;
	LOCKED(_pcc_set_mem_map(sock, mem));
}

static int pcc_init(struct pcmcia_socket *s)
{
	pr_debug("m32r_pcc: init call\n");
	return 0;
}

static struct pccard_operations pcc_operations = {
	.init			= pcc_init,
	.get_status		= pcc_get_status,
	.set_socket		= pcc_set_socket,
	.set_io_map		= pcc_set_io_map,
	.set_mem_map		= pcc_set_mem_map,
};

/*====================================================================*/

static struct platform_driver pcc_driver = {
	.driver = {
		.name		= "pcc",
		.owner		= THIS_MODULE,
	},
};

static struct platform_device pcc_device = {
	.name = "pcc",
	.id = 0,
};

/*====================================================================*/

static int __init init_m32r_pcc(void)
{
	int i, ret;

	ret = platform_driver_register(&pcc_driver);
	if (ret)
		return ret;

	ret = platform_device_register(&pcc_device);
	if (ret){
		platform_driver_unregister(&pcc_driver);
		return ret;
	}

	printk(KERN_INFO "m32r PCC probe:\n");

	pcc_sockets = 0;

	add_pcc_socket(M32R_PCC0_BASE, PCC0_IRQ, M32R_PCC0_MAPBASE, 0x1000);

#ifdef CONFIG_M32RPCC_SLOT2
	add_pcc_socket(M32R_PCC1_BASE, PCC1_IRQ, M32R_PCC1_MAPBASE, 0x2000);
#endif

	if (pcc_sockets == 0) {
		printk("socket is not found.\n");
		platform_device_unregister(&pcc_device);
		platform_driver_unregister(&pcc_driver);
		return -ENODEV;
	}

	/* Set up interrupt handler(s) */

	for (i = 0 ; i < pcc_sockets ; i++) {
		socket[i].socket.dev.parent = &pcc_device.dev;
		socket[i].socket.ops = &pcc_operations;
		socket[i].socket.resource_ops = &pccard_static_ops;
		socket[i].socket.owner = THIS_MODULE;
		socket[i].number = i;
		ret = pcmcia_register_socket(&socket[i].socket);
		if (!ret)
			socket[i].flags |= IS_REGISTERED;

#if 0	/* driver model ordering issue */
		class_device_create_file(&socket[i].socket.dev,
					 &class_device_attr_info);
		class_device_create_file(&socket[i].socket.dev,
					 &class_device_attr_exca);
#endif
	}

	/* Finally, schedule a polling interrupt */
	if (poll_interval != 0) {
		poll_timer.function = pcc_interrupt_wrapper;
		poll_timer.data = 0;
		init_timer(&poll_timer);
		poll_timer.expires = jiffies + poll_interval;
		add_timer(&poll_timer);
	}

	return 0;
} /* init_m32r_pcc */

static void __exit exit_m32r_pcc(void)
{
	int i;

	for (i = 0; i < pcc_sockets; i++)
		if (socket[i].flags & IS_REGISTERED)
			pcmcia_unregister_socket(&socket[i].socket);

	platform_device_unregister(&pcc_device);
	if (poll_interval != 0)
		del_timer_sync(&poll_timer);

	platform_driver_unregister(&pcc_driver);
} /* exit_m32r_pcc */

module_init(init_m32r_pcc);
module_exit(exit_m32r_pcc);
MODULE_LICENSE("Dual MPL/GPL");
/*====================================================================*/
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pcmcia/m32r_pcc.c
	3	*
	4	* Device driver for the PCMCIA functionality of M32R.
	5	*
	6	* Copyright (c) 2001, 2002, 2003, 2004
	7	* Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/moduleparam.h>
	12	#include <linux/init.h>
1da177e4 LT	13	#include <linux/types.h>
	14	#include <linux/fcntl.h>
	15	#include <linux/string.h>
	16	#include <linux/kernel.h>
	17	#include <linux/errno.h>
	18	#include <linux/timer.h>
1da177e4 LT	19	#include <linux/ioport.h>
	20	#include <linux/delay.h>
	21	#include <linux/workqueue.h>
	22	#include <linux/interrupt.h>
d052d1be	23	#include <linux/platform_device.h>
1977f032	24	#include <linux/bitops.h>
1da177e4 LT	25	#include <asm/irq.h>
1da177e4 LT	26	#include <asm/io.h>
1da177e4 LT	27	#include <asm/system.h>
	28	#include <asm/addrspace.h>
	29
1da177e4 LT	30	#include <pcmcia/ss.h>
	31	#include <pcmcia/cs.h>
	32
	33	/* XXX: should be moved into asm/irq.h */
	34	#define PCC0_IRQ 24
	35	#define PCC1_IRQ 25
	36
	37	#include "m32r_pcc.h"
	38
	39	#define CHAOS_PCC_DEBUG
	40	#ifdef CHAOS_PCC_DEBUG
	41	static volatile u_short dummy_readbuf;
	42	#endif
	43
	44	#define PCC_DEBUG_DBEX
	45
1da177e4 LT	46
	47	/* Poll status interval -- 0 means default to interrupt */
	48	static int poll_interval = 0;
	49
	50	typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
	51
	52	typedef struct pcc_socket {
	53	u_short type, flags;
	54	struct pcmcia_socket socket;
	55	unsigned int number;
906da809	56	unsigned int ioaddr;
1da177e4 LT	57	u_long mapaddr;
	58	u_long base; /* PCC register base */
	59	u_char cs_irq, intr;
	60	pccard_io_map io_map[MAX_IO_WIN];
	61	pccard_mem_map mem_map[MAX_WIN];
	62	u_char io_win;
	63	u_char mem_win;
	64	pcc_as_t current_space;
	65	u_char last_iodbex;
	66	#ifdef CHAOS_PCC_DEBUG
	67	u_char last_iosize;
	68	#endif
	69	#ifdef CONFIG_PROC_FS
	70	struct proc_dir_entry *proc;
	71	#endif
	72	} pcc_socket_t;
	73
	74	static int pcc_sockets = 0;
	75	static pcc_socket_t socket[M32R_MAX_PCC] = {
	76	{ 0, }, /* ... */
	77	};
	78
	79	/====================================================================/
	80
	81	static unsigned int pcc_get(u_short, unsigned int);
	82	static void pcc_set(u_short, unsigned int , unsigned int );
	83
	84	static DEFINE_SPINLOCK(pcc_lock);
	85
	86	void pcc_iorw(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int wr, int flag)
	87	{
	88	u_long addr;
	89	u_long flags;
	90	int need_ex;
	91	#ifdef PCC_DEBUG_DBEX
	92	int _dbex;
	93	#endif
	94	pcc_socket_t *t = &socket[sock];
	95	#ifdef CHAOS_PCC_DEBUG
	96	int map_changed = 0;
	97	#endif
	98
	99	/* Need lock ? */
	100	spin_lock_irqsave(&pcc_lock, flags);
	101
	102	/*
	103	* Check if need dbex
	104	*/
	105	need_ex = (size > 1 && flag == 0) ? PCMOD_DBEX : 0;
	106	#ifdef PCC_DEBUG_DBEX
	107	_dbex = need_ex;
	108	need_ex = 0;
	109	#endif
	110
	111	/*
	112	* calculate access address
	113	*/
	114	addr = t->mapaddr + port - t->ioaddr + KSEG1; /* XXX */
	115
	116	/*
	117	* Check current mapping
	118	*/
	119	if (t->current_space != as_io \|\| t->last_iodbex != need_ex) {
	120
121	u_long cbsz;
122
123	/*
124	* Disable first
125	*/
126	pcc_set(sock, PCCR, 0);
127
128	/*
129	* Set mode and io address
130	*/
131	cbsz = (t->flags & MAP_16BIT) ? 0 : PCMOD_CBSZ;
132	pcc_set(sock, PCMOD, PCMOD_AS_IO \| cbsz \| need_ex);
133	pcc_set(sock, PCADR, addr & 0x1ff00000);
134
135	/*
136	* Enable and read it
137	*/
138	pcc_set(sock, PCCR, 1);
139
140	#ifdef CHAOS_PCC_DEBUG
141	#if 0
142	map_changed = (t->current_space == as_attr && size == 2); /* XXX */
143	#else
144	map_changed = 1;
145	#endif
146	#endif
147	t->current_space = as_io;
148	}
149
150	/*
151	* access to IO space
152	*/
153	if (size == 1) {
154	/* Byte */
155	unsigned char bp = (unsigned char )buf;
156
157	#ifdef CHAOS_DEBUG
158	if (map_changed) {
159	dummy_readbuf = readb(addr);
160	}
161	#endif
162	if (wr) {
163	/* write Byte */
164	while (nmemb--) {
165	writeb(*bp++, addr);
166	}
167	} else {
168	/* read Byte */
169	while (nmemb--) {
170	*bp++ = readb(addr);
171	}
172	}
173	} else {
174	/* Word */
175	unsigned short bp = (unsigned short )buf;
176
177	#ifdef CHAOS_PCC_DEBUG
178	if (map_changed) {
179	dummy_readbuf = readw(addr);
180	}
181	#endif
182	if (wr) {
183	/* write Word */
184	while (nmemb--) {
185	#ifdef PCC_DEBUG_DBEX
186	if (_dbex) {
187	unsigned char cp = (unsigned char )bp;
188	unsigned short tmp;
189	tmp = cp[1] << 8 \| cp[0];
190	writew(tmp, addr);
191	bp++;
192	} else
193	#endif
194	writew(*bp++, addr);
195	}
196	} else {
197	/* read Word */
198	while (nmemb--) {
199	#ifdef PCC_DEBUG_DBEX
200	if (_dbex) {
201	unsigned char cp = (unsigned char )bp;
202	unsigned short tmp;
203	tmp = readw(addr);
204	cp[0] = tmp & 0xff;
205	cp[1] = (tmp >> 8) & 0xff;
206	bp++;
207	} else
208	#endif
209	*bp++ = readw(addr);
210	}
211	}
212	}
213
214	#if 1
215	/* addr is no longer used */
216	if ((addr = pcc_get(sock, PCIRC)) & PCIRC_BWERR) {
217	printk("m32r_pcc: BWERR detected : port 0x%04lx : iosize %dbit\n",
218	port, size * 8);
219	pcc_set(sock, PCIRC, addr);
220	}
221	#endif
222	/*
223	* save state
224	*/
225	t->last_iosize = size;
226	t->last_iodbex = need_ex;
227
228	/* Need lock ? */
229
230	spin_unlock_irqrestore(&pcc_lock,flags);
231
232	return;
233	}
234
235	void pcc_ioread(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
236	pcc_iorw(sock, port, buf, size, nmemb, 0, flag);
237	}
238
239	void pcc_iowrite(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
240	pcc_iorw(sock, port, buf, size, nmemb, 1, flag);
241	}
242
243	/====================================================================/
244
245	#define IS_REGISTERED 0x2000
246	#define IS_ALIVE 0x8000
247
248	typedef struct pcc_t {
249	char *name;
250	u_short flags;
251	} pcc_t;
252
253	static pcc_t pcc[] = {
254	{ "xnux2", 0 }, { "xnux2", 0 },
255	};
256
7d12e780	257	static irqreturn_t pcc_interrupt(int, void *);
1da177e4 LT	258
	259	/====================================================================/
	260
	261	static struct timer_list poll_timer;
	262
	263	static unsigned int pcc_get(u_short sock, unsigned int reg)
	264	{
	265	return inl(socket[sock].base + reg);
	266	}
	267
	268
	269	static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
	270	{
	271	outl(data, socket[sock].base + reg);
	272	}
	273
	274	/*======================================================================
	275
	276	See if a card is present, powered up, in IO mode, and already
	277	bound to a (non PC Card) Linux driver. We leave these alone.
	278
	279	We make an exception for cards that seem to be serial devices.
	280
	281	======================================================================*/
	282
	283	static int __init is_alive(u_short sock)
	284	{
	285	unsigned int stat;
	286	unsigned int f;
	287
	288	stat = pcc_get(sock, PCIRC);
	289	f = (stat & (PCIRC_CDIN1 \| PCIRC_CDIN2)) >> 16;
	290	if(!f){
	291	printk("m32r_pcc: No Card is detected at socket %d : stat = 0x%08x\n",stat,sock);
	292	return 0;
	293	}
	294	if(f!=3)
	295	printk("m32r_pcc: Insertion fail (%.8x) at socket %d\n",stat,sock);
	296	else
	297	printk("m32r_pcc: Card is Inserted at socket %d(%.8x)\n",sock,stat);
	298	return 0;
	299	}
	300
906da809 OJ	301	static void add_pcc_socket(ulong base, int irq, ulong mapaddr,
906da809 OJ	302	unsigned int ioaddr)
1da177e4 LT	303	{
	304	pcc_socket_t *t = &socket[pcc_sockets];
	305
	306	/* add sockets */
	307	t->ioaddr = ioaddr;
	308	t->mapaddr = mapaddr;
	309	t->base = base;
	310	#ifdef CHAOS_PCC_DEBUG
	311	t->flags = MAP_16BIT;
	312	#else
	313	t->flags = 0;
	314	#endif
	315	if (is_alive(pcc_sockets))
	316	t->flags \|= IS_ALIVE;
	317
	318	/* add pcc */
	319	if (t->base > 0) {
	320	request_region(t->base, 0x20, "m32r-pcc");
	321	}
	322
	323	printk(KERN_INFO " %s ", pcc[pcc_sockets].name);
	324	printk("pcc at 0x%08lx\n", t->base);
	325
	326	/* Update socket interrupt information, capabilities */
	327	t->socket.features \|= (SS_CAP_PCCARD \| SS_CAP_STATIC_MAP);
	328	t->socket.map_size = M32R_PCC_MAPSIZE;
	329	t->socket.io_offset = ioaddr; /* use for io access offset */
	330	t->socket.irq_mask = 0;
	331	t->socket.pci_irq = 2 + pcc_sockets; /* XXX */
	332
	333	request_irq(irq, pcc_interrupt, 0, "m32r-pcc", pcc_interrupt);
	334
	335	pcc_sockets++;
	336
	337	return;
	338	}
	339
	340
	341	/====================================================================/
	342
7d12e780	343	static irqreturn_t pcc_interrupt(int irq, void *dev)
1da177e4 LT	344	{
	345	int i, j, irc;
	346	u_int events, active;
	347	int handled = 0;
	348
c9f50ddd	349	pr_debug("m32r_pcc: pcc_interrupt(%d)\n", irq);
1da177e4 LT	350
	351	for (j = 0; j < 20; j++) {
	352	active = 0;
	353	for (i = 0; i < pcc_sockets; i++) {
	354	if ((socket[i].cs_irq != irq) &&
	355	(socket[i].socket.pci_irq != irq))
	356	continue;
	357	handled = 1;
	358	irc = pcc_get(i, PCIRC);
	359	irc >>=16;
c9f50ddd DB	360	pr_debug("m32r_pcc: interrupt: socket %d pcirc 0x%02x ",
c9f50ddd DB	361	i, irc);
1da177e4 LT	362	if (!irc)
	363	continue;
	364
	365	events = (irc) ? SS_DETECT : 0;
	366	events \|= (pcc_get(i,PCCR) & PCCR_PCEN) ? SS_READY : 0;
c9f50ddd	367	pr_debug("m32r_pcc: event 0x%02x\n", events);
1da177e4 LT	368
	369	if (events)
	370	pcmcia_parse_events(&socket[i].socket, events);
	371
	372	active \|= events;
	373	active = 0;
	374	}
	375	if (!active) break;
	376	}
	377	if (j == 20)
	378	printk(KERN_NOTICE "m32r-pcc: infinite loop in interrupt handler\n");
	379
c9f50ddd	380	pr_debug("m32r_pcc: interrupt done\n");
1da177e4 LT	381
	382	return IRQ_RETVAL(handled);
	383	} /* pcc_interrupt */
	384
	385	static void pcc_interrupt_wrapper(u_long data)
	386	{
9c8e7f5c	387	pcc_interrupt(0, NULL);
1da177e4 LT	388	init_timer(&poll_timer);
	389	poll_timer.expires = jiffies + poll_interval;
	390	add_timer(&poll_timer);
	391	}
	392
	393	/====================================================================/
	394
	395	static int _pcc_get_status(u_short sock, u_int *value)
	396	{
	397	u_int status;
	398
	399	status = pcc_get(sock,PCIRC);
	400	*value = ((status & PCIRC_CDIN1) && (status & PCIRC_CDIN2))
	401	? SS_DETECT : 0;
	402
	403	status = pcc_get(sock,PCCR);
	404
	405	#if 0
	406	*value \|= (status & PCCR_PCEN) ? SS_READY : 0;
	407	#else
	408	value \|= SS_READY; / XXX: always */
	409	#endif
	410
	411	status = pcc_get(sock,PCCSIGCR);
	412	*value \|= (status & PCCSIGCR_VEN) ? SS_POWERON : 0;
	413
c9f50ddd	414	pr_debug("m32r_pcc: GetStatus(%d) = %#4.4x\n", sock, *value);
1da177e4 LT	415	return 0;
	416	} /* _get_status */
	417
	418	/====================================================================/
	419
1da177e4 LT	420	static int _pcc_set_socket(u_short sock, socket_state_t *state)
	421	{
	422	u_long reg = 0;
	423
c9f50ddd	424	pr_debug("m32r_pcc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
1da177e4 LT	425	"io_irq %d, csc_mask %#2.2x)", sock, state->flags,
	426	state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
	427
	428	if (state->Vcc) {
	429	/*
	430	* 5V only
	431	*/
	432	if (state->Vcc == 50) {
	433	reg \|= PCCSIGCR_VEN;
	434	} else {
	435	return -EINVAL;
	436	}
	437	}
	438
	439	if (state->flags & SS_RESET) {
c9f50ddd	440	pr_debug("m32r_pcc: :RESET\n");
1da177e4 LT	441	reg \|= PCCSIGCR_CRST;
	442	}
	443	if (state->flags & SS_OUTPUT_ENA){
c9f50ddd	444	pr_debug("m32r_pcc: :OUTPUT_ENA\n");
1da177e4 LT	445	/* bit clear */
	446	} else {
	447	reg \|= PCCSIGCR_SEN;
	448	}
	449
	450	pcc_set(sock,PCCSIGCR,reg);
	451
1da177e4	452	if(state->flags & SS_IOCARD){
c9f50ddd	453	pr_debug("m32r_pcc: :IOCARD");
1da177e4 LT	454	}
1da177e4 LT	455	if (state->flags & SS_PWR_AUTO) {
c9f50ddd	456	pr_debug("m32r_pcc: :PWR_AUTO");
1da177e4 LT	457	}
1da177e4 LT	458	if (state->csc_mask & SS_DETECT)
c9f50ddd	459	pr_debug("m32r_pcc: :csc-SS_DETECT");
1da177e4 LT	460	if (state->flags & SS_IOCARD) {
1da177e4 LT	461	if (state->csc_mask & SS_STSCHG)
c9f50ddd	462	pr_debug("m32r_pcc: :STSCHG");
1da177e4 LT	463	} else {
1da177e4 LT	464	if (state->csc_mask & SS_BATDEAD)
c9f50ddd	465	pr_debug("m32r_pcc: :BATDEAD");
1da177e4	466	if (state->csc_mask & SS_BATWARN)
c9f50ddd	467	pr_debug("m32r_pcc: :BATWARN");
1da177e4	468	if (state->csc_mask & SS_READY)
c9f50ddd	469	pr_debug("m32r_pcc: :READY");
1da177e4	470	}
c9f50ddd	471	pr_debug("m32r_pcc: \n");
1da177e4 LT	472	return 0;
	473	} /* _set_socket */
	474
	475	/====================================================================/
	476
	477	static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
	478	{
	479	u_char map;
	480
c9f50ddd	481	pr_debug("m32r_pcc: SetIOMap(%d, %d, %#2.2x, %d ns, "
5f784336 WS	482	"%#llx-%#llx)\n", sock, io->map, io->flags,
	483	io->speed, (unsigned long long)io->start,
	484	(unsigned long long)io->stop);
1da177e4 LT	485	map = io->map;
	486
	487	return 0;
	488	} /* _set_io_map */
	489
	490	/====================================================================/
	491
	492	static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
	493	{
	494
	495	u_char map = mem->map;
	496	u_long mode;
	497	u_long addr;
	498	pcc_socket_t *t = &socket[sock];
	499	#ifdef CHAOS_PCC_DEBUG
	500	#if 0
	501	pcc_as_t last = t->current_space;
	502	#endif
	503	#endif
	504
c9f50ddd	505	pr_debug("m32r_pcc: SetMemMap(%d, %d, %#2.2x, %d ns, "
5f784336 WS	506	"%#llx, %#x)\n", sock, map, mem->flags,
	507	mem->speed, (unsigned long long)mem->static_start,
	508	mem->card_start);
1da177e4 LT	509
	510	/*
	511	* sanity check
	512	*/
	513	if ((map > MAX_WIN) \|\| (mem->card_start > 0x3ffffff)){
	514	return -EINVAL;
	515	}
	516
	517	/*
	518	* de-activate
	519	*/
	520	if ((mem->flags & MAP_ACTIVE) == 0) {
	521	t->current_space = as_none;
	522	return 0;
	523	}
	524
	525	/*
	526	* Disable first
	527	*/
	528	pcc_set(sock, PCCR, 0);
	529
	530	/*
	531	* Set mode
	532	*/
	533	if (mem->flags & MAP_ATTRIB) {
	534	mode = PCMOD_AS_ATTRIB \| PCMOD_CBSZ;
	535	t->current_space = as_attr;
	536	} else {
	537	mode = 0; /* common memory */
	538	t->current_space = as_comm;
	539	}
	540	pcc_set(sock, PCMOD, mode);
	541
	542	/*
	543	* Set address
	544	*/
	545	addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
	546	pcc_set(sock, PCADR, addr);
	547
	548	mem->static_start = addr + mem->card_start;
	549
	550	/*
	551	* Enable again
	552	*/
	553	pcc_set(sock, PCCR, 1);
	554
	555	#ifdef CHAOS_PCC_DEBUG
	556	#if 0
	557	if (last != as_attr) {
	558	#else
	559	if (1) {
	560	#endif
	561	dummy_readbuf = (u_char )(addr + KSEG1);
	562	}
	563	#endif
	564
	565	return 0;
	566
	567	} /* _set_mem_map */
	568
	569	#if 0 /* driver model ordering issue */
	570	/*======================================================================
	571
	572	Routines for accessing socket information and register dumps via
573	/proc/bus/pccard/...
574
575	======================================================================*/
576
577	static ssize_t show_info(struct class_device class_dev, char buf)
578	{
579	pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
580	socket.dev);
581
582	return sprintf(buf, "type: %s\nbase addr: 0x%08lx\n",
583	pcc[s->type].name, s->base);
584	}
585
586	static ssize_t show_exca(struct class_device class_dev, char buf)
587	{
588	/* FIXME */
589
590	return 0;
591	}
592
593	static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
594	static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
595	#endif
596
597	/====================================================================/
598
599	/* this is horribly ugly... proper locking needs to be done here at
600	* some time... */
601	#define LOCKED(x) do { \
602	int retval; \
603	unsigned long flags; \
604	spin_lock_irqsave(&pcc_lock, flags); \
605	retval = x; \
606	spin_unlock_irqrestore(&pcc_lock, flags); \
607	return retval; \
608	} while (0)
609
610
611	static int pcc_get_status(struct pcmcia_socket s, u_int value)
612	{
613	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
614
615	if (socket[sock].flags & IS_ALIVE) {
616	*value = 0;
617	return -EINVAL;
618	}
619	LOCKED(_pcc_get_status(sock, value));
620	}
621
1da177e4 LT	622	static int pcc_set_socket(struct pcmcia_socket s, socket_state_t state)
	623	{
	624	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
	625
	626	if (socket[sock].flags & IS_ALIVE)
	627	return -EINVAL;
	628
	629	LOCKED(_pcc_set_socket(sock, state));
	630	}
	631
	632	static int pcc_set_io_map(struct pcmcia_socket s, struct pccard_io_map io)
	633	{
	634	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
	635
	636	if (socket[sock].flags & IS_ALIVE)
	637	return -EINVAL;
	638	LOCKED(_pcc_set_io_map(sock, io));
	639	}
	640
	641	static int pcc_set_mem_map(struct pcmcia_socket s, struct pccard_mem_map mem)
	642	{
	643	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
	644
	645	if (socket[sock].flags & IS_ALIVE)
	646	return -EINVAL;
	647	LOCKED(_pcc_set_mem_map(sock, mem));
	648	}
	649
	650	static int pcc_init(struct pcmcia_socket *s)
	651	{
c9f50ddd	652	pr_debug("m32r_pcc: init call\n");
1da177e4 LT	653	return 0;
	654	}
	655
	656	static struct pccard_operations pcc_operations = {
	657	.init = pcc_init,
	658	.get_status = pcc_get_status,
1da177e4 LT	659	.set_socket = pcc_set_socket,
	660	.set_io_map = pcc_set_io_map,
	661	.set_mem_map = pcc_set_mem_map,
	662	};
	663
	664	/====================================================================/
	665
7a192ec3 ML	666	static struct platform_driver pcc_driver = {
	667	.driver = {
	668	.name = "pcc",
	669	.owner = THIS_MODULE,
	670	},
1da177e4 LT	671	};
	672
	673	static struct platform_device pcc_device = {
	674	.name = "pcc",
	675	.id = 0,
	676	};
	677
	678	/====================================================================/
	679
	680	static int __init init_m32r_pcc(void)
	681	{
	682	int i, ret;
	683
7a192ec3	684	ret = platform_driver_register(&pcc_driver);
1da177e4 LT	685	if (ret)
	686	return ret;
	687
	688	ret = platform_device_register(&pcc_device);
	689	if (ret){
7a192ec3	690	platform_driver_unregister(&pcc_driver);
1da177e4 LT	691	return ret;
	692	}
	693
	694	printk(KERN_INFO "m32r PCC probe:\n");
	695
	696	pcc_sockets = 0;
	697
	698	add_pcc_socket(M32R_PCC0_BASE, PCC0_IRQ, M32R_PCC0_MAPBASE, 0x1000);
	699
	700	#ifdef CONFIG_M32RPCC_SLOT2
	701	add_pcc_socket(M32R_PCC1_BASE, PCC1_IRQ, M32R_PCC1_MAPBASE, 0x2000);
	702	#endif
	703
	704	if (pcc_sockets == 0) {
	705	printk("socket is not found.\n");
	706	platform_device_unregister(&pcc_device);
7a192ec3	707	platform_driver_unregister(&pcc_driver);
1da177e4 LT	708	return -ENODEV;
	709	}
	710
	711	/* Set up interrupt handler(s) */
	712
	713	for (i = 0 ; i < pcc_sockets ; i++) {
ccbe48f7	714	socket[i].socket.dev.parent = &pcc_device.dev;
1da177e4 LT	715	socket[i].socket.ops = &pcc_operations;
	716	socket[i].socket.resource_ops = &pccard_static_ops;
	717	socket[i].socket.owner = THIS_MODULE;
	718	socket[i].number = i;
	719	ret = pcmcia_register_socket(&socket[i].socket);
	720	if (!ret)
	721	socket[i].flags \|= IS_REGISTERED;
	722
	723	#if 0 /* driver model ordering issue */
	724	class_device_create_file(&socket[i].socket.dev,
	725	&class_device_attr_info);
	726	class_device_create_file(&socket[i].socket.dev,
	727	&class_device_attr_exca);
	728	#endif
	729	}
	730
	731	/* Finally, schedule a polling interrupt */
	732	if (poll_interval != 0) {
	733	poll_timer.function = pcc_interrupt_wrapper;
	734	poll_timer.data = 0;
	735	init_timer(&poll_timer);
	736	poll_timer.expires = jiffies + poll_interval;
	737	add_timer(&poll_timer);
	738	}
	739
	740	return 0;
	741	} /* init_m32r_pcc */
	742
	743	static void __exit exit_m32r_pcc(void)
	744	{
	745	int i;
	746
	747	for (i = 0; i < pcc_sockets; i++)
	748	if (socket[i].flags & IS_REGISTERED)
	749	pcmcia_unregister_socket(&socket[i].socket);
	750
	751	platform_device_unregister(&pcc_device);
	752	if (poll_interval != 0)
	753	del_timer_sync(&poll_timer);
	754
7a192ec3	755	platform_driver_unregister(&pcc_driver);
1da177e4 LT	756	} /* exit_m32r_pcc */
	757
	758	module_init(init_m32r_pcc);
	759	module_exit(exit_m32r_pcc);
	760	MODULE_LICENSE("Dual MPL/GPL");
	761	/====================================================================/