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Merge branch 'pdc-regression' into release
[net-next-2.6.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
25be5e6c 23#include <linux/acpi.h>
9f23ed3b 24#include <linux/kallsyms.h>
75e07fc3 25#include <linux/dmi.h>
649426ef 26#include <linux/pci-aspm.h>
32a9a682 27#include <linux/ioport.h>
93177a74 28#include <asm/dma.h> /* isa_dma_bridge_buggy */
bc56b9e0 29#include "pci.h"
1da177e4 30
32a9a682 31/*
0cdbe30f
YS		 32 * This quirk function disables memory decoding and releases memory resources
33 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
32a9a682
YS		 34 * It also rounds up size to specified alignment.
35 * Later on, the kernel will assign page-aligned memory resource back
0cdbe30f 36 * to the device.
32a9a682
YS		 37 */
38static void __devinit quirk_resource_alignment(struct pci_dev *dev)
39{
40 int i;
41 struct resource *r;
42 resource_size_t align, size;
0cdbe30f 43 u16 command;
32a9a682
YS		 44
45 if (!pci_is_reassigndev(dev))
46 return;
47
48 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
49 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
50 dev_warn(&dev->dev,
51 "Can't reassign resources to host bridge.\n");
52 return;
53 }
54
0cdbe30f
YS		 55 dev_info(&dev->dev,
56 "Disabling memory decoding and releasing memory resources.\n");
57 pci_read_config_word(dev, PCI_COMMAND, &command);
58 command &= ~PCI_COMMAND_MEMORY;
59 pci_write_config_word(dev, PCI_COMMAND, command);
32a9a682
YS		 60
61 align = pci_specified_resource_alignment(dev);
62 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
63 r = &dev->resource[i];
64 if (!(r->flags & IORESOURCE_MEM))
65 continue;
66 size = resource_size(r);
67 if (size < align) {
68 size = align;
69 dev_info(&dev->dev,
70 "Rounding up size of resource #%d to %#llx.\n",
71 i, (unsigned long long)size);
72 }
73 r->end = size - 1;
74 r->start = 0;
75 }
76 /* Need to disable bridge's resource window,
77 * to enable the kernel to reassign new resource
78 * window later on.
79 */
80 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
81 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
82 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
83 r = &dev->resource[i];
84 if (!(r->flags & IORESOURCE_MEM))
85 continue;
86 r->end = resource_size(r) - 1;
87 r->start = 0;
88 }
89 pci_disable_bridge_window(dev);
90 }
91}
92DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
93
253d2e54
JP		 94/*
95 * Decoding should be disabled for a PCI device during BAR sizing to avoid
96 * conflict. But doing so may cause problems on host bridge and perhaps other
97 * key system devices. For devices that need to have mmio decoding always-on,
98 * we need to set the dev->mmio_always_on bit.
99 */
100static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
101{
102 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
103 dev->mmio_always_on = 1;
104}
105DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_mmio_always_on);
106
bd8481e1
DT		 107/* The Mellanox Tavor device gives false positive parity errors
108 * Mark this device with a broken_parity_status, to allow
109 * PCI scanning code to "skip" this now blacklisted device.
110 */
111static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
112{
113 dev->broken_parity_status = 1; /* This device gives false positives */
114}
115DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
116DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
117
1da177e4
LT		 118/* Deal with broken BIOS'es that neglect to enable passive release,
119 which can cause problems in combination with the 82441FX/PPro MTRRs */
1597cacb 120static void quirk_passive_release(struct pci_dev *dev)
1da177e4
LT		 121{
122 struct pci_dev *d = NULL;
123 unsigned char dlc;
124
125 /* We have to make sure a particular bit is set in the PIIX3
126 ISA bridge, so we have to go out and find it. */
127 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
128 pci_read_config_byte(d, 0x82, &dlc);
129 if (!(dlc & 1<<1)) {
999da9fd 130 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
1da177e4
LT		 131 dlc |= 1<<1;
132 pci_write_config_byte(d, 0x82, dlc);
133 }
134 }
135}
652c538e
AM		 136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
137DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
1da177e4
LT		 138
139/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
140 but VIA don't answer queries. If you happen to have good contacts at VIA
141 ask them for me please -- Alan
142
143 This appears to be BIOS not version dependent. So presumably there is a
144 chipset level fix */
1da177e4
LT		 145
146static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
147{
148 if (!isa_dma_bridge_buggy) {
149 isa_dma_bridge_buggy=1;
f0fda801 150 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
1da177e4
LT		 151 }
152}
153 /*
154 * Its not totally clear which chipsets are the problematic ones
155 * We know 82C586 and 82C596 variants are affected.
156 */
652c538e
AM		 157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
1da177e4 164
4731fdcf
LB		 165/*
166 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
167 * for some HT machines to use C4 w/o hanging.
168 */
169static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
170{
171 u32 pmbase;
172 u16 pm1a;
173
174 pci_read_config_dword(dev, 0x40, &pmbase);
175 pmbase = pmbase & 0xff80;
176 pm1a = inw(pmbase);
177
178 if (pm1a & 0x10) {
179 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
180 outw(0x10, pmbase);
181 }
182}
183DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
184
1da177e4
LT		 185/*
186 * Chipsets where PCI->PCI transfers vanish or hang
187 */
188static void __devinit quirk_nopcipci(struct pci_dev *dev)
189{
190 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
f0fda801 191 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
1da177e4
LT		 192 pci_pci_problems |= PCIPCI_FAIL;
193 }
194}
652c538e
AM		 195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
236561e5
AC		 197
198static void __devinit quirk_nopciamd(struct pci_dev *dev)
199{
200 u8 rev;
201 pci_read_config_byte(dev, 0x08, &rev);
202 if (rev == 0x13) {
203 /* Erratum 24 */
f0fda801 204 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
236561e5
AC		 205 pci_pci_problems |= PCIAGP_FAIL;
206 }
207}
652c538e 208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
1da177e4
LT		 209
210/*
211 * Triton requires workarounds to be used by the drivers
212 */
213static void __devinit quirk_triton(struct pci_dev *dev)
214{
215 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
f0fda801 216 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 217 pci_pci_problems |= PCIPCI_TRITON;
218 }
219}
652c538e
AM		 220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
1da177e4
LT		 224
225/*
226 * VIA Apollo KT133 needs PCI latency patch
227 * Made according to a windows driver based patch by George E. Breese
228 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
229 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
230 * the info on which Mr Breese based his work.
231 *
232 * Updated based on further information from the site and also on
233 * information provided by VIA
234 */
1597cacb 235static void quirk_vialatency(struct pci_dev *dev)
1da177e4
LT		 236{
237 struct pci_dev *p;
1da177e4
LT		 238 u8 busarb;
239 /* Ok we have a potential problem chipset here. Now see if we have
240 a buggy southbridge */
241
242 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
243 if (p!=NULL) {
1da177e4
LT		 244 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
245 /* Check for buggy part revisions */
2b1afa87 246 if (p->revision < 0x40 || p->revision > 0x42)
1da177e4
LT		 247 goto exit;
248 } else {
249 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
250 if (p==NULL) /* No problem parts */
251 goto exit;
1da177e4 252 /* Check for buggy part revisions */
2b1afa87 253 if (p->revision < 0x10 || p->revision > 0x12)
1da177e4
LT		 254 goto exit;
255 }
256
257 /*
258 * Ok we have the problem. Now set the PCI master grant to
259 * occur every master grant. The apparent bug is that under high
260 * PCI load (quite common in Linux of course) you can get data
261 * loss when the CPU is held off the bus for 3 bus master requests
262 * This happens to include the IDE controllers....
263 *
264 * VIA only apply this fix when an SB Live! is present but under
265 * both Linux and Windows this isnt enough, and we have seen
266 * corruption without SB Live! but with things like 3 UDMA IDE
267 * controllers. So we ignore that bit of the VIA recommendation..
268 */
269
270 pci_read_config_byte(dev, 0x76, &busarb);
271 /* Set bit 4 and bi 5 of byte 76 to 0x01
272 "Master priority rotation on every PCI master grant */
273 busarb &= ~(1<<5);
274 busarb |= (1<<4);
275 pci_write_config_byte(dev, 0x76, busarb);
f0fda801 276 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
1da177e4
LT		 277exit:
278 pci_dev_put(p);
279}
652c538e
AM		 280DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1597cacb 283/* Must restore this on a resume from RAM */
652c538e
AM		 284DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
285DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
286DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1da177e4
LT		 287
288/*
289 * VIA Apollo VP3 needs ETBF on BT848/878
290 */
291static void __devinit quirk_viaetbf(struct pci_dev *dev)
292{
293 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
f0fda801 294 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 295 pci_pci_problems |= PCIPCI_VIAETBF;
296 }
297}
652c538e 298DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
1da177e4
LT		 299
300static void __devinit quirk_vsfx(struct pci_dev *dev)
301{
302 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
f0fda801 303 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 304 pci_pci_problems |= PCIPCI_VSFX;
305 }
306}
652c538e 307DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
1da177e4
LT		 308
309/*
310 * Ali Magik requires workarounds to be used by the drivers
311 * that DMA to AGP space. Latency must be set to 0xA and triton
312 * workaround applied too
313 * [Info kindly provided by ALi]
314 */
315static void __init quirk_alimagik(struct pci_dev *dev)
316{
317 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
f0fda801 318 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 319 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
320 }
321}
652c538e
AM		 322DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
1da177e4
LT		 324
325/*
326 * Natoma has some interesting boundary conditions with Zoran stuff
327 * at least
328 */
329static void __devinit quirk_natoma(struct pci_dev *dev)
330{
331 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
f0fda801 332 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 333 pci_pci_problems |= PCIPCI_NATOMA;
334 }
335}
652c538e
AM		 336DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
337DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
338DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
339DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
340DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
341DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
1da177e4
LT		 342
343/*
344 * This chip can cause PCI parity errors if config register 0xA0 is read
345 * while DMAs are occurring.
346 */
347static void __devinit quirk_citrine(struct pci_dev *dev)
348{
349 dev->cfg_size = 0xA0;
350}
652c538e 351DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
1da177e4
LT		 352
353/*
354 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
355 * If it's needed, re-allocate the region.
356 */
357static void __devinit quirk_s3_64M(struct pci_dev *dev)
358{
359 struct resource *r = &dev->resource[0];
360
361 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
362 r->start = 0;
363 r->end = 0x3ffffff;
364 }
365}
652c538e
AM		 366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
1da177e4 368
73d2eaac
AS		 369/*
370 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
371 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
372 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
373 * (which conflicts w/ BAR1's memory range).
374 */
375static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
376{
377 if (pci_resource_len(dev, 0) != 8) {
378 struct resource *res = &dev->resource[0];
379 res->end = res->start + 8 - 1;
380 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
381 "(incorrect header); workaround applied.\n");
382 }
383}
384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
385
6693e74a
LT		 386static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
387 unsigned size, int nr, const char *name)
1da177e4
LT		 388{
389 region &= ~(size-1);
390 if (region) {
085ae41f 391 struct pci_bus_region bus_region;
1da177e4
LT		 392 struct resource *res = dev->resource + nr;
393
394 res->name = pci_name(dev);
395 res->start = region;
396 res->end = region + size - 1;
397 res->flags = IORESOURCE_IO;
085ae41f
DM		 398
399 /* Convert from PCI bus to resource space. */
400 bus_region.start = res->start;
401 bus_region.end = res->end;
402 pcibios_bus_to_resource(dev, res, &bus_region);
403
f967a443
BH		 404 if (pci_claim_resource(dev, nr) == 0)
405 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
406 res, name);
1da177e4
LT		 407 }
408}
409
410/*
411 * ATI Northbridge setups MCE the processor if you even
412 * read somewhere between 0x3b0->0x3bb or read 0x3d3
413 */
414static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
415{
f0fda801 416 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
1da177e4
LT		 417 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
418 request_region(0x3b0, 0x0C, "RadeonIGP");
419 request_region(0x3d3, 0x01, "RadeonIGP");
420}
652c538e 421DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
1da177e4
LT		 422
423/*
424 * Let's make the southbridge information explicit instead
425 * of having to worry about people probing the ACPI areas,
426 * for example.. (Yes, it happens, and if you read the wrong
427 * ACPI register it will put the machine to sleep with no
428 * way of waking it up again. Bummer).
429 *
430 * ALI M7101: Two IO regions pointed to by words at
431 * 0xE0 (64 bytes of ACPI registers)
432 * 0xE2 (32 bytes of SMB registers)
433 */
434static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
435{
436 u16 region;
437
438 pci_read_config_word(dev, 0xE0, &region);
6693e74a 439 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 440 pci_read_config_word(dev, 0xE2, &region);
6693e74a 441 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4 442}
652c538e 443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
1da177e4 444
6693e74a
LT		 445static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
446{
447 u32 devres;
448 u32 mask, size, base;
449
450 pci_read_config_dword(dev, port, &devres);
451 if ((devres & enable) != enable)
452 return;
453 mask = (devres >> 16) & 15;
454 base = devres & 0xffff;
455 size = 16;
456 for (;;) {
457 unsigned bit = size >> 1;
458 if ((bit & mask) == bit)
459 break;
460 size = bit;
461 }
462 /*
463 * For now we only print it out. Eventually we'll want to
464 * reserve it (at least if it's in the 0x1000+ range), but
465 * let's get enough confirmation reports first.
466 */
467 base &= -size;
f0fda801 468 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 469}
470
471static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
472{
473 u32 devres;
474 u32 mask, size, base;
475
476 pci_read_config_dword(dev, port, &devres);
477 if ((devres & enable) != enable)
478 return;
479 base = devres & 0xffff0000;
480 mask = (devres & 0x3f) << 16;
481 size = 128 << 16;
482 for (;;) {
483 unsigned bit = size >> 1;
484 if ((bit & mask) == bit)
485 break;
486 size = bit;
487 }
488 /*
489 * For now we only print it out. Eventually we'll want to
490 * reserve it, but let's get enough confirmation reports first.
491 */
492 base &= -size;
f0fda801 493 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 494}
495
1da177e4
LT		 496/*
497 * PIIX4 ACPI: Two IO regions pointed to by longwords at
498 * 0x40 (64 bytes of ACPI registers)
08db2a70 499 * 0x90 (16 bytes of SMB registers)
6693e74a 500 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 501 */
502static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
503{
6693e74a 504 u32 region, res_a;
1da177e4
LT		 505
506 pci_read_config_dword(dev, 0x40, &region);
6693e74a 507 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 508 pci_read_config_dword(dev, 0x90, &region);
08db2a70 509 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 510
511 /* Device resource A has enables for some of the other ones */
512 pci_read_config_dword(dev, 0x5c, &res_a);
513
514 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
515 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
516
517 /* Device resource D is just bitfields for static resources */
518
519 /* Device 12 enabled? */
520 if (res_a & (1 << 29)) {
521 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
522 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
523 }
524 /* Device 13 enabled? */
525 if (res_a & (1 << 30)) {
526 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
527 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
528 }
529 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
530 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4 531}
652c538e
AM		 532DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
533DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
1da177e4
LT		 534
535/*
536 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
537 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
538 * 0x58 (64 bytes of GPIO I/O space)
539 */
540static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
541{
542 u32 region;
543
544 pci_read_config_dword(dev, 0x40, &region);
6693e74a 545 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 546
547 pci_read_config_dword(dev, 0x58, &region);
6693e74a 548 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4 549}
652c538e
AM		 550DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
551DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
552DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
553DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
554DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
555DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
556DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
557DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
558DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
559DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
1da177e4 560
894886e5 561static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
2cea752f
RM		 562{
563 u32 region;
564
565 pci_read_config_dword(dev, 0x40, &region);
566 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
567
568 pci_read_config_dword(dev, 0x48, &region);
569 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
570}
894886e5
LT		 571
572static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
573{
574 u32 val;
575 u32 size, base;
576
577 pci_read_config_dword(dev, reg, &val);
578
579 /* Enabled? */
580 if (!(val & 1))
581 return;
582 base = val & 0xfffc;
583 if (dynsize) {
584 /*
585 * This is not correct. It is 16, 32 or 64 bytes depending on
586 * register D31:F0:ADh bits 5:4.
587 *
588 * But this gets us at least _part_ of it.
589 */
590 size = 16;
591 } else {
592 size = 128;
593 }
594 base &= ~(size-1);
595
596 /* Just print it out for now. We should reserve it after more debugging */
597 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
598}
599
600static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
601{
602 /* Shared ACPI/GPIO decode with all ICH6+ */
603 ich6_lpc_acpi_gpio(dev);
604
605 /* ICH6-specific generic IO decode */
606 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
607 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
608}
609DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
610DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
611
612static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
613{
614 u32 val;
615 u32 mask, base;
616
617 pci_read_config_dword(dev, reg, &val);
618
619 /* Enabled? */
620 if (!(val & 1))
621 return;
622
623 /*
624 * IO base in bits 15:2, mask in bits 23:18, both
625 * are dword-based
626 */
627 base = val & 0xfffc;
628 mask = (val >> 16) & 0xfc;
629 mask |= 3;
630
631 /* Just print it out for now. We should reserve it after more debugging */
632 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
633}
634
635/* ICH7-10 has the same common LPC generic IO decode registers */
636static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
637{
638 /* We share the common ACPI/DPIO decode with ICH6 */
639 ich6_lpc_acpi_gpio(dev);
640
641 /* And have 4 ICH7+ generic decodes */
642 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
643 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
644 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
645 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
646}
647DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
648DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
649DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
650DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
651DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
652DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
653DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
654DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
655DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
656DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
657DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
658DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
659DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
2cea752f 660
1da177e4
LT		 661/*
662 * VIA ACPI: One IO region pointed to by longword at
663 * 0x48 or 0x20 (256 bytes of ACPI registers)
664 */
665static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
666{
1da177e4
LT		 667 u32 region;
668
651472fb 669 if (dev->revision & 0x10) {
1da177e4
LT		 670 pci_read_config_dword(dev, 0x48, &region);
671 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 672 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 673 }
674}
652c538e 675DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
1da177e4
LT		 676
677/*
678 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
679 * 0x48 (256 bytes of ACPI registers)
680 * 0x70 (128 bytes of hardware monitoring register)
681 * 0x90 (16 bytes of SMB registers)
682 */
683static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
684{
685 u16 hm;
686 u32 smb;
687
688 quirk_vt82c586_acpi(dev);
689
690 pci_read_config_word(dev, 0x70, &hm);
691 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 692 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 693
694 pci_read_config_dword(dev, 0x90, &smb);
695 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 696 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4 697}
652c538e 698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
1da177e4 699
6d85f29b
IK		 700/*
701 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
702 * 0x88 (128 bytes of power management registers)
703 * 0xd0 (16 bytes of SMB registers)
704 */
705static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
706{
707 u16 pm, smb;
708
709 pci_read_config_word(dev, 0x88, &pm);
710 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 711 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 712
713 pci_read_config_word(dev, 0xd0, &smb);
714 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 715 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 716}
717DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
718
1f56f4a2
GB		 719/*
720 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
721 * Disable fast back-to-back on the secondary bus segment
722 */
723static void __devinit quirk_xio2000a(struct pci_dev *dev)
724{
725 struct pci_dev *pdev;
726 u16 command;
727
728 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
729 "secondary bus fast back-to-back transfers disabled\n");
730 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
731 pci_read_config_word(pdev, PCI_COMMAND, &command);
732 if (command & PCI_COMMAND_FAST_BACK)
733 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
734 }
735}
736DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
737 quirk_xio2000a);
1da177e4
LT		 738
739#ifdef CONFIG_X86_IO_APIC
740
741#include <asm/io_apic.h>
742
743/*
744 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
745 * devices to the external APIC.
746 *
747 * TODO: When we have device-specific interrupt routers,
748 * this code will go away from quirks.
749 */
1597cacb 750static void quirk_via_ioapic(struct pci_dev *dev)
1da177e4
LT		 751{
752 u8 tmp;
753
754 if (nr_ioapics < 1)
755 tmp = 0; /* nothing routed to external APIC */
756 else
757 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
758
f0fda801 759 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
1da177e4
LT		 760 tmp == 0 ? "Disa" : "Ena");
761
762 /* Offset 0x58: External APIC IRQ output control */
763 pci_write_config_byte (dev, 0x58, tmp);
764}
652c538e 765DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
e1a2a51e 766DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1da177e4 767
a1740913
KW		 768/*
769 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
770 * This leads to doubled level interrupt rates.
771 * Set this bit to get rid of cycle wastage.
772 * Otherwise uncritical.
773 */
1597cacb 774static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
a1740913
KW		 775{
776 u8 misc_control2;
777#define BYPASS_APIC_DEASSERT 8
778
779 pci_read_config_byte(dev, 0x5B, &misc_control2);
780 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
f0fda801 781 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
a1740913
KW		 782 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
783 }
784}
785DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
e1a2a51e 786DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
a1740913 787
1da177e4
LT		 788/*
789 * The AMD io apic can hang the box when an apic irq is masked.
790 * We check all revs >= B0 (yet not in the pre production!) as the bug
791 * is currently marked NoFix
792 *
793 * We have multiple reports of hangs with this chipset that went away with
236561e5 794 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1da177e4
LT		 795 * of course. However the advice is demonstrably good even if so..
796 */
797static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
798{
44c10138 799 if (dev->revision >= 0x02) {
f0fda801 800 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
801 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
1da177e4
LT		 802 }
803}
652c538e 804DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1da177e4
LT		 805
806static void __init quirk_ioapic_rmw(struct pci_dev *dev)
807{
808 if (dev->devfn == 0 && dev->bus->number == 0)
809 sis_apic_bug = 1;
810}
652c538e 811DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
1da177e4
LT		 812#endif /* CONFIG_X86_IO_APIC */
813
d556ad4b
PO		 814/*
815 * Some settings of MMRBC can lead to data corruption so block changes.
816 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
817 */
818static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
819{
aa288d4d 820 if (dev->subordinate && dev->revision <= 0x12) {
f0fda801 821 dev_info(&dev->dev, "AMD8131 rev %x detected; "
822 "disabling PCI-X MMRBC\n", dev->revision);
d556ad4b
PO		 823 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
824 }
825}
826DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1da177e4 827
1da177e4
LT		 828/*
829 * FIXME: it is questionable that quirk_via_acpi
830 * is needed. It shows up as an ISA bridge, and does not
831 * support the PCI_INTERRUPT_LINE register at all. Therefore
832 * it seems like setting the pci_dev's 'irq' to the
833 * value of the ACPI SCI interrupt is only done for convenience.
834 * -jgarzik
835 */
836static void __devinit quirk_via_acpi(struct pci_dev *d)
837{
838 /*
839 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
840 */
841 u8 irq;
842 pci_read_config_byte(d, 0x42, &irq);
843 irq &= 0xf;
844 if (irq && (irq != 2))
845 d->irq = irq;
846}
652c538e
AM		 847DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
848DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1da177e4 849
09d6029f
DD		 850
851/*
1597cacb 852 * VIA bridges which have VLink
09d6029f 853 */
1597cacb 854
c06bb5d4
JD		 855static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
856
857static void quirk_via_bridge(struct pci_dev *dev)
858{
859 /* See what bridge we have and find the device ranges */
860 switch (dev->device) {
861 case PCI_DEVICE_ID_VIA_82C686:
cb7468ef
JD		 862 /* The VT82C686 is special, it attaches to PCI and can have
863 any device number. All its subdevices are functions of
864 that single device. */
865 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
866 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
c06bb5d4
JD		 867 break;
868 case PCI_DEVICE_ID_VIA_8237:
869 case PCI_DEVICE_ID_VIA_8237A:
870 via_vlink_dev_lo = 15;
871 break;
872 case PCI_DEVICE_ID_VIA_8235:
873 via_vlink_dev_lo = 16;
874 break;
875 case PCI_DEVICE_ID_VIA_8231:
876 case PCI_DEVICE_ID_VIA_8233_0:
877 case PCI_DEVICE_ID_VIA_8233A:
878 case PCI_DEVICE_ID_VIA_8233C_0:
879 via_vlink_dev_lo = 17;
880 break;
881 }
882}
883DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
884DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
885DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
886DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
888DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
889DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
890DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
09d6029f 891
1597cacb
AC		 892/**
893 * quirk_via_vlink - VIA VLink IRQ number update
894 * @dev: PCI device
895 *
896 * If the device we are dealing with is on a PIC IRQ we need to
897 * ensure that the IRQ line register which usually is not relevant
898 * for PCI cards, is actually written so that interrupts get sent
c06bb5d4
JD		 899 * to the right place.
900 * We only do this on systems where a VIA south bridge was detected,
901 * and only for VIA devices on the motherboard (see quirk_via_bridge
902 * above).
1597cacb
AC		 903 */
904
905static void quirk_via_vlink(struct pci_dev *dev)
25be5e6c
LB		 906{
907 u8 irq, new_irq;
908
c06bb5d4
JD		 909 /* Check if we have VLink at all */
910 if (via_vlink_dev_lo == -1)
09d6029f
DD		 911 return;
912
913 new_irq = dev->irq;
914
915 /* Don't quirk interrupts outside the legacy IRQ range */
916 if (!new_irq || new_irq > 15)
917 return;
918
1597cacb 919 /* Internal device ? */
c06bb5d4
JD		 920 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
921 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1597cacb
AC		 922 return;
923
924 /* This is an internal VLink device on a PIC interrupt. The BIOS
925 ought to have set this but may not have, so we redo it */
926
25be5e6c
LB		 927 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
928 if (new_irq != irq) {
f0fda801 929 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
930 irq, new_irq);
25be5e6c
LB		 931 udelay(15); /* unknown if delay really needed */
932 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
933 }
934}
1597cacb 935DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
25be5e6c 936
1da177e4
LT		 937/*
938 * VIA VT82C598 has its device ID settable and many BIOSes
939 * set it to the ID of VT82C597 for backward compatibility.
940 * We need to switch it off to be able to recognize the real
941 * type of the chip.
942 */
943static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
944{
945 pci_write_config_byte(dev, 0xfc, 0);
946 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
947}
652c538e 948DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1da177e4
LT		 949
950/*
951 * CardBus controllers have a legacy base address that enables them
952 * to respond as i82365 pcmcia controllers. We don't want them to
953 * do this even if the Linux CardBus driver is not loaded, because
954 * the Linux i82365 driver does not (and should not) handle CardBus.
955 */
1597cacb 956static void quirk_cardbus_legacy(struct pci_dev *dev)
1da177e4
LT		 957{
958 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
959 return;
960 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
961}
962DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
e1a2a51e 963DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1da177e4
LT		 964
965/*
966 * Following the PCI ordering rules is optional on the AMD762. I'm not
967 * sure what the designers were smoking but let's not inhale...
968 *
969 * To be fair to AMD, it follows the spec by default, its BIOS people
970 * who turn it off!
971 */
1597cacb 972static void quirk_amd_ordering(struct pci_dev *dev)
1da177e4
LT		 973{
974 u32 pcic;
975 pci_read_config_dword(dev, 0x4C, &pcic);
976 if ((pcic&6)!=6) {
977 pcic |= 6;
f0fda801 978 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1da177e4
LT		 979 pci_write_config_dword(dev, 0x4C, pcic);
980 pci_read_config_dword(dev, 0x84, &pcic);
981 pcic |= (1<<23); /* Required in this mode */
982 pci_write_config_dword(dev, 0x84, pcic);
983 }
984}
652c538e 985DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
e1a2a51e 986DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1da177e4
LT		 987
988/*
989 * DreamWorks provided workaround for Dunord I-3000 problem
990 *
991 * This card decodes and responds to addresses not apparently
992 * assigned to it. We force a larger allocation to ensure that
993 * nothing gets put too close to it.
994 */
995static void __devinit quirk_dunord ( struct pci_dev * dev )
996{
997 struct resource *r = &dev->resource [1];
998 r->start = 0;
999 r->end = 0xffffff;
1000}
652c538e 1001DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1da177e4
LT		 1002
1003/*
1004 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1005 * is subtractive decoding (transparent), and does indicate this
1006 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1007 * instead of 0x01.
1008 */
1009static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
1010{
1011 dev->transparent = 1;
1012}
652c538e
AM		 1013DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1014DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1da177e4
LT		 1015
1016/*
1017 * Common misconfiguration of the MediaGX/Geode PCI master that will
1018 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1019 * datasheets found at http://www.national.com/ds/GX for info on what
1020 * these bits do. <christer@weinigel.se>
1021 */
1597cacb 1022static void quirk_mediagx_master(struct pci_dev *dev)
1da177e4
LT		 1023{
1024 u8 reg;
1025 pci_read_config_byte(dev, 0x41, &reg);
1026 if (reg & 2) {
1027 reg &= ~2;
f0fda801 1028 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1da177e4
LT		 1029 pci_write_config_byte(dev, 0x41, reg);
1030 }
1031}
652c538e
AM		 1032DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1033DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1da177e4 1034
1da177e4
LT		 1035/*
1036 * Ensure C0 rev restreaming is off. This is normally done by
1037 * the BIOS but in the odd case it is not the results are corruption
1038 * hence the presence of a Linux check
1039 */
1597cacb 1040static void quirk_disable_pxb(struct pci_dev *pdev)
1da177e4
LT		 1041{
1042 u16 config;
1da177e4 1043
44c10138 1044 if (pdev->revision != 0x04) /* Only C0 requires this */
1da177e4
LT		 1045 return;
1046 pci_read_config_word(pdev, 0x40, &config);
1047 if (config & (1<<6)) {
1048 config &= ~(1<<6);
1049 pci_write_config_word(pdev, 0x40, config);
f0fda801 1050 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1da177e4
LT		 1051 }
1052}
652c538e 1053DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
e1a2a51e 1054DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1da177e4 1055
05a7d22b 1056static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
ab17443a 1057{
5deab536 1058 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
05a7d22b 1059 u8 tmp;
ab17443a 1060
05a7d22b
CC		 1061 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1062 if (tmp == 0x01) {
ab17443a
CH		 1063 pci_read_config_byte(pdev, 0x40, &tmp);
1064 pci_write_config_byte(pdev, 0x40, tmp|1);
1065 pci_write_config_byte(pdev, 0x9, 1);
1066 pci_write_config_byte(pdev, 0xa, 6);
1067 pci_write_config_byte(pdev, 0x40, tmp);
1068
c9f89475 1069 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
05a7d22b 1070 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
ab17443a
CH		 1071 }
1072}
05a7d22b 1073DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
e1a2a51e 1074DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
05a7d22b 1075DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
e1a2a51e 1076DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
5deab536
SH		 1077DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1078DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
ab17443a 1079
1da177e4
LT		 1080/*
1081 * Serverworks CSB5 IDE does not fully support native mode
1082 */
1083static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1084{
1085 u8 prog;
1086 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1087 if (prog & 5) {
1088 prog &= ~5;
1089 pdev->class &= ~5;
1090 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
368c73d4 1091 /* PCI layer will sort out resources */
1da177e4
LT		 1092 }
1093}
652c538e 1094DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1da177e4
LT		 1095
1096/*
1097 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1098 */
1099static void __init quirk_ide_samemode(struct pci_dev *pdev)
1100{
1101 u8 prog;
1102
1103 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1104
1105 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
f0fda801 1106 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1da177e4
LT		 1107 prog &= ~5;
1108 pdev->class &= ~5;
1109 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1da177e4
LT		 1110 }
1111}
368c73d4 1112DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1da177e4 1113
979b1791
AC		 1114/*
1115 * Some ATA devices break if put into D3
1116 */
1117
1118static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1119{
1120 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1121 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1122 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1123}
1124DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1125DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
7a661c6f
AC		 1126/* ALi loses some register settings that we cannot then restore */
1127DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1128/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1129 occur when mode detecting */
1130DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
979b1791 1131
1da177e4
LT		 1132/* This was originally an Alpha specific thing, but it really fits here.
1133 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1134 */
1135static void __init quirk_eisa_bridge(struct pci_dev *dev)
1136{
1137 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1138}
652c538e 1139DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1da177e4 1140
7daa0c4f 1141
1da177e4
LT		 1142/*
1143 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1144 * is not activated. The myth is that Asus said that they do not want the
1145 * users to be irritated by just another PCI Device in the Win98 device
1146 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1147 * package 2.7.0 for details)
1148 *
1149 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1150 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
d7698edc 1151 * becomes necessary to do this tweak in two steps -- the chosen trigger
1152 * is either the Host bridge (preferred) or on-board VGA controller.
9208ee82
JD		 1153 *
1154 * Note that we used to unhide the SMBus that way on Toshiba laptops
1155 * (Satellite A40 and Tecra M2) but then found that the thermal management
1156 * was done by SMM code, which could cause unsynchronized concurrent
1157 * accesses to the SMBus registers, with potentially bad effects. Thus you
1158 * should be very careful when adding new entries: if SMM is accessing the
1159 * Intel SMBus, this is a very good reason to leave it hidden.
a99acc83
JD		 1160 *
1161 * Likewise, many recent laptops use ACPI for thermal management. If the
1162 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1163 * natively, and keeping the SMBus hidden is the right thing to do. If you
1164 * are about to add an entry in the table below, please first disassemble
1165 * the DSDT and double-check that there is no code accessing the SMBus.
1da177e4 1166 */
9d24a81e 1167static int asus_hides_smbus;
1da177e4
LT		 1168
1169static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1170{
1171 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1172 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1173 switch(dev->subsystem_device) {
a00db371 1174 case 0x8025: /* P4B-LX */
1da177e4
LT		 1175 case 0x8070: /* P4B */
1176 case 0x8088: /* P4B533 */
1177 case 0x1626: /* L3C notebook */
1178 asus_hides_smbus = 1;
1179 }
2f2d39d2 1180 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1da177e4
LT		 1181 switch(dev->subsystem_device) {
1182 case 0x80b1: /* P4GE-V */
1183 case 0x80b2: /* P4PE */
1184 case 0x8093: /* P4B533-V */
1185 asus_hides_smbus = 1;
1186 }
2f2d39d2 1187 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1da177e4
LT		 1188 switch(dev->subsystem_device) {
1189 case 0x8030: /* P4T533 */
1190 asus_hides_smbus = 1;
1191 }
2f2d39d2 1192 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1da177e4
LT		 1193 switch (dev->subsystem_device) {
1194 case 0x8070: /* P4G8X Deluxe */
1195 asus_hides_smbus = 1;
1196 }
2f2d39d2 1197 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
321311af
JD		 1198 switch (dev->subsystem_device) {
1199 case 0x80c9: /* PU-DLS */
1200 asus_hides_smbus = 1;
1201 }
2f2d39d2 1202 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1da177e4
LT		 1203 switch (dev->subsystem_device) {
1204 case 0x1751: /* M2N notebook */
1205 case 0x1821: /* M5N notebook */
4096ed0f 1206 case 0x1897: /* A6L notebook */
1da177e4
LT		 1207 asus_hides_smbus = 1;
1208 }
2f2d39d2 1209 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1da177e4
LT		 1210 switch (dev->subsystem_device) {
1211 case 0x184b: /* W1N notebook */
1212 case 0x186a: /* M6Ne notebook */
1213 asus_hides_smbus = 1;
1214 }
2f2d39d2 1215 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
2e45785c
JD		 1216 switch (dev->subsystem_device) {
1217 case 0x80f2: /* P4P800-X */
1218 asus_hides_smbus = 1;
1219 }
2f2d39d2 1220 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
acc06632
RM		 1221 switch (dev->subsystem_device) {
1222 case 0x1882: /* M6V notebook */
2d1e1c75 1223 case 0x1977: /* A6VA notebook */
acc06632
RM		 1224 asus_hides_smbus = 1;
1225 }
1da177e4
LT		 1226 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1227 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1228 switch(dev->subsystem_device) {
1229 case 0x088C: /* HP Compaq nc8000 */
1230 case 0x0890: /* HP Compaq nc6000 */
1231 asus_hides_smbus = 1;
1232 }
2f2d39d2 1233 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1da177e4
LT		 1234 switch (dev->subsystem_device) {
1235 case 0x12bc: /* HP D330L */
e3b1bd57 1236 case 0x12bd: /* HP D530 */
74c57428 1237 case 0x006a: /* HP Compaq nx9500 */
1da177e4
LT		 1238 asus_hides_smbus = 1;
1239 }
677cc644
JD		 1240 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1241 switch (dev->subsystem_device) {
1242 case 0x12bf: /* HP xw4100 */
1243 asus_hides_smbus = 1;
1244 }
1da177e4
LT		 1245 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1246 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1247 switch(dev->subsystem_device) {
1248 case 0xC00C: /* Samsung P35 notebook */
1249 asus_hides_smbus = 1;
1250 }
c87f883e
RIZ		 1251 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1252 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1253 switch(dev->subsystem_device) {
1254 case 0x0058: /* Compaq Evo N620c */
1255 asus_hides_smbus = 1;
1256 }
d7698edc 1257 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1258 switch(dev->subsystem_device) {
1259 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1260 /* Motherboard doesn't have Host bridge
1261 * subvendor/subdevice IDs, therefore checking
1262 * its on-board VGA controller */
1263 asus_hides_smbus = 1;
1264 }
8293b0f6 1265 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
10260d9a
JD		 1266 switch(dev->subsystem_device) {
1267 case 0x00b8: /* Compaq Evo D510 CMT */
1268 case 0x00b9: /* Compaq Evo D510 SFF */
6b5096e4 1269 case 0x00ba: /* Compaq Evo D510 USDT */
8293b0f6
DS		 1270 /* Motherboard doesn't have Host bridge
1271 * subvendor/subdevice IDs and on-board VGA
1272 * controller is disabled if an AGP card is
1273 * inserted, therefore checking USB UHCI
1274 * Controller #1 */
10260d9a
JD		 1275 asus_hides_smbus = 1;
1276 }
27e46859
KH		 1277 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1278 switch (dev->subsystem_device) {
1279 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1280 /* Motherboard doesn't have host bridge
1281 * subvendor/subdevice IDs, therefore checking
1282 * its on-board VGA controller */
1283 asus_hides_smbus = 1;
1284 }
1da177e4
LT		 1285 }
1286}
652c538e
AM		 1287DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1290DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
677cc644 1291DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
652c538e
AM		 1292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1293DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1294DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1295DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1296DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1297
1298DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
8293b0f6 1299DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
27e46859 1300DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
d7698edc 1301
1597cacb 1302static void asus_hides_smbus_lpc(struct pci_dev *dev)
1da177e4
LT		 1303{
1304 u16 val;
1305
1306 if (likely(!asus_hides_smbus))
1307 return;
1308
1309 pci_read_config_word(dev, 0xF2, &val);
1310 if (val & 0x8) {
1311 pci_write_config_word(dev, 0xF2, val & (~0x8));
1312 pci_read_config_word(dev, 0xF2, &val);
1313 if (val & 0x8)
f0fda801 1314 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1da177e4 1315 else
f0fda801 1316 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1da177e4
LT		 1317 }
1318}
652c538e
AM		 1319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1322DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1323DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
e1a2a51e
RW		 1326DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1327DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1328DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1329DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1330DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1331DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1332DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1597cacb 1333
e1a2a51e
RW		 1334/* It appears we just have one such device. If not, we have a warning */
1335static void __iomem *asus_rcba_base;
1336static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
acc06632 1337{
e1a2a51e 1338 u32 rcba;
acc06632
RM		 1339
1340 if (likely(!asus_hides_smbus))
1341 return;
e1a2a51e
RW		 1342 WARN_ON(asus_rcba_base);
1343
acc06632 1344 pci_read_config_dword(dev, 0xF0, &rcba);
e1a2a51e
RW		 1345 /* use bits 31:14, 16 kB aligned */
1346 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1347 if (asus_rcba_base == NULL)
1348 return;
1349}
1350
1351static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1352{
1353 u32 val;
1354
1355 if (likely(!asus_hides_smbus || !asus_rcba_base))
1356 return;
1357 /* read the Function Disable register, dword mode only */
1358 val = readl(asus_rcba_base + 0x3418);
1359 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1360}
1361
1362static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1363{
1364 if (likely(!asus_hides_smbus || !asus_rcba_base))
1365 return;
1366 iounmap(asus_rcba_base);
1367 asus_rcba_base = NULL;
f0fda801 1368 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
acc06632 1369}
e1a2a51e
RW		 1370
1371static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1372{
1373 asus_hides_smbus_lpc_ich6_suspend(dev);
1374 asus_hides_smbus_lpc_ich6_resume_early(dev);
1375 asus_hides_smbus_lpc_ich6_resume(dev);
1376}
652c538e 1377DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
e1a2a51e
RW		 1378DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1379DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1380DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
ce007ea5 1381
1da177e4
LT		 1382/*
1383 * SiS 96x south bridge: BIOS typically hides SMBus device...
1384 */
1597cacb 1385static void quirk_sis_96x_smbus(struct pci_dev *dev)
1da177e4
LT		 1386{
1387 u8 val = 0;
1da177e4 1388 pci_read_config_byte(dev, 0x77, &val);
2f5c33b3 1389 if (val & 0x10) {
f0fda801 1390 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
2f5c33b3
MH		 1391 pci_write_config_byte(dev, 0x77, val & ~0x10);
1392 }
1da177e4 1393}
652c538e
AM		 1394DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1395DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1396DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1397DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
e1a2a51e
RW		 1398DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1399DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1400DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1401DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1da177e4 1402
1da177e4
LT		 1403/*
1404 * ... This is further complicated by the fact that some SiS96x south
1405 * bridges pretend to be 85C503/5513 instead. In that case see if we
1406 * spotted a compatible north bridge to make sure.
1407 * (pci_find_device doesn't work yet)
1408 *
1409 * We can also enable the sis96x bit in the discovery register..
1410 */
1da177e4
LT		 1411#define SIS_DETECT_REGISTER 0x40
1412
1597cacb 1413static void quirk_sis_503(struct pci_dev *dev)
1da177e4
LT		 1414{
1415 u8 reg;
1416 u16 devid;
1417
1418 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1419 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1420 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1421 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1422 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1423 return;
1424 }
1425
1da177e4 1426 /*
2f5c33b3
MH		 1427 * Ok, it now shows up as a 96x.. run the 96x quirk by
1428 * hand in case it has already been processed.
1429 * (depends on link order, which is apparently not guaranteed)
1da177e4
LT		 1430 */
1431 dev->device = devid;
2f5c33b3 1432 quirk_sis_96x_smbus(dev);
1da177e4 1433}
652c538e 1434DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
e1a2a51e 1435DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1da177e4 1436
1da177e4 1437
e5548e96
BJD		 1438/*
1439 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1440 * and MC97 modem controller are disabled when a second PCI soundcard is
1441 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1442 * -- bjd
1443 */
1597cacb 1444static void asus_hides_ac97_lpc(struct pci_dev *dev)
e5548e96
BJD		 1445{
1446 u8 val;
1447 int asus_hides_ac97 = 0;
1448
1449 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1450 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1451 asus_hides_ac97 = 1;
1452 }
1453
1454 if (!asus_hides_ac97)
1455 return;
1456
1457 pci_read_config_byte(dev, 0x50, &val);
1458 if (val & 0xc0) {
1459 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1460 pci_read_config_byte(dev, 0x50, &val);
1461 if (val & 0xc0)
f0fda801 1462 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
e5548e96 1463 else
f0fda801 1464 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
e5548e96
BJD		 1465 }
1466}
652c538e 1467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
e1a2a51e 1468DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1597cacb 1469
77967052 1470#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1471
1472/*
1473 * If we are using libata we can drive this chip properly but must
1474 * do this early on to make the additional device appear during
1475 * the PCI scanning.
1476 */
5ee2ae7f 1477static void quirk_jmicron_ata(struct pci_dev *pdev)
15e0c694 1478{
e34bb370 1479 u32 conf1, conf5, class;
15e0c694
AC		 1480 u8 hdr;
1481
1482 /* Only poke fn 0 */
1483 if (PCI_FUNC(pdev->devfn))
1484 return;
1485
5ee2ae7f
TH		 1486 pci_read_config_dword(pdev, 0x40, &conf1);
1487 pci_read_config_dword(pdev, 0x80, &conf5);
15e0c694 1488
5ee2ae7f
TH		 1489 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1490 conf5 &= ~(1 << 24); /* Clear bit 24 */
1491
1492 switch (pdev->device) {
4daedcfe
TH		 1493 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1494 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
5b6ae5ba 1495 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
5ee2ae7f
TH		 1496 /* The controller should be in single function ahci mode */
1497 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1498 break;
1499
1500 case PCI_DEVICE_ID_JMICRON_JMB365:
1501 case PCI_DEVICE_ID_JMICRON_JMB366:
1502 /* Redirect IDE second PATA port to the right spot */
1503 conf5 |= (1 << 24);
1504 /* Fall through */
1505 case PCI_DEVICE_ID_JMICRON_JMB361:
1506 case PCI_DEVICE_ID_JMICRON_JMB363:
5b6ae5ba 1507 case PCI_DEVICE_ID_JMICRON_JMB369:
5ee2ae7f
TH		 1508 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1509 /* Set the class codes correctly and then direct IDE 0 */
3a9e3a51 1510 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
5ee2ae7f
TH		 1511 break;
1512
1513 case PCI_DEVICE_ID_JMICRON_JMB368:
1514 /* The controller should be in single function IDE mode */
1515 conf1 |= 0x00C00000; /* Set 22, 23 */
1516 break;
15e0c694 1517 }
5ee2ae7f
TH		 1518
1519 pci_write_config_dword(pdev, 0x40, conf1);
1520 pci_write_config_dword(pdev, 0x80, conf5);
1521
1522 /* Update pdev accordingly */
1523 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1524 pdev->hdr_type = hdr & 0x7f;
1525 pdev->multifunction = !!(hdr & 0x80);
e34bb370
TH		 1526
1527 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1528 pdev->class = class >> 8;
15e0c694 1529}
5ee2ae7f
TH		 1530DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1531DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
4daedcfe 1532DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
5ee2ae7f 1533DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
5b6ae5ba 1534DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
5ee2ae7f
TH		 1535DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1536DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1537DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
5b6ae5ba 1538DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
e1a2a51e
RW		 1539DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1540DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
4daedcfe 1541DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
e1a2a51e 1542DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
5b6ae5ba 1543DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
e1a2a51e
RW		 1544DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1545DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1546DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
5b6ae5ba 1547DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
15e0c694
AC		 1548
1549#endif
1550
1da177e4
LT		 1551#ifdef CONFIG_X86_IO_APIC
1552static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1553{
1554 int i;
1555
1556 if ((pdev->class >> 8) != 0xff00)
1557 return;
1558
1559 /* the first BAR is the location of the IO APIC...we must
1560 * not touch this (and it's already covered by the fixmap), so
1561 * forcibly insert it into the resource tree */
1562 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1563 insert_resource(&iomem_resource, &pdev->resource[0]);
1564
1565 /* The next five BARs all seem to be rubbish, so just clean
1566 * them out */
1567 for (i=1; i < 6; i++) {
1568 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1569 }
1570
1571}
652c538e 1572DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1da177e4
LT		 1573#endif
1574
1da177e4
LT		 1575static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1576{
0ba379ec
EB		 1577 pci_msi_off(pdev);
1578 pdev->no_msi = 1;
1da177e4 1579}
652c538e
AM		 1580DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1581DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1da177e4 1583
4602b88d
KA		 1584
1585/*
1586 * It's possible for the MSI to get corrupted if shpc and acpi
1587 * are used together on certain PXH-based systems.
1588 */
1589static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1590{
f5f2b131 1591 pci_msi_off(dev);
4602b88d 1592 dev->no_msi = 1;
f0fda801 1593 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
4602b88d
KA		 1594}
1595DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1596DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1597DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1598DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1599DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1600
ffadcc2f
KCA		 1601/*
1602 * Some Intel PCI Express chipsets have trouble with downstream
1603 * device power management.
1604 */
1605static void quirk_intel_pcie_pm(struct pci_dev * dev)
1606{
1607 pci_pm_d3_delay = 120;
1608 dev->no_d1d2 = 1;
1609}
1610
1611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1614DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1615DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1616DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1618DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1620DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1621DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1622DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1623DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1624DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1625DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1626DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1627DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1628DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1629DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1630DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1631DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1632
426b3b8d 1633#ifdef CONFIG_X86_IO_APIC
e1d3a908
SA		 1634/*
1635 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1636 * remap the original interrupt in the linux kernel to the boot interrupt, so
1637 * that a PCI device's interrupt handler is installed on the boot interrupt
1638 * line instead.
1639 */
1640static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1641{
41b9eb26 1642 if (noioapicquirk || noioapicreroute)
e1d3a908
SA		 1643 return;
1644
1645 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
fdcdaf6c
BH		 1646 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1647 dev->vendor, dev->device);
e1d3a908 1648}
88d1dce3
OD		 1649DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1650DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1651DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1652DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1653DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1654DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1655DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1656DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1657DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1658DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1659DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1660DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1661DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1662DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1663DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1664DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
e1d3a908 1665
426b3b8d
SA		 1666/*
1667 * On some chipsets we can disable the generation of legacy INTx boot
1668 * interrupts.
1669 */
1670
1671/*
1672 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1673 * 300641-004US, section 5.7.3.
1674 */
1675#define INTEL_6300_IOAPIC_ABAR 0x40
1676#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1677
1678static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1679{
1680 u16 pci_config_word;
1681
1682 if (noioapicquirk)
1683 return;
1684
1685 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1686 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1687 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1688
fdcdaf6c
BH		 1689 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1690 dev->vendor, dev->device);
426b3b8d 1691}
88d1dce3
OD		 1692DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1693DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
77251188
OD		 1694
1695/*
1696 * disable boot interrupts on HT-1000
1697 */
1698#define BC_HT1000_FEATURE_REG 0x64
1699#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1700#define BC_HT1000_MAP_IDX 0xC00
1701#define BC_HT1000_MAP_DATA 0xC01
1702
1703static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1704{
1705 u32 pci_config_dword;
1706 u8 irq;
1707
1708 if (noioapicquirk)
1709 return;
1710
1711 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1712 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1713 BC_HT1000_PIC_REGS_ENABLE);
1714
1715 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1716 outb(irq, BC_HT1000_MAP_IDX);
1717 outb(0x00, BC_HT1000_MAP_DATA);
1718 }
1719
1720 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1721
fdcdaf6c
BH		 1722 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1723 dev->vendor, dev->device);
77251188 1724}
88d1dce3
OD		 1725DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1726DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
542622da
OD		 1727
1728/*
1729 * disable boot interrupts on AMD and ATI chipsets
1730 */
1731/*
1732 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1733 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1734 * (due to an erratum).
1735 */
1736#define AMD_813X_MISC 0x40
1737#define AMD_813X_NOIOAMODE (1<<0)
4fd8bdc5 1738#define AMD_813X_REV_B1 0x12
bbe19443 1739#define AMD_813X_REV_B2 0x13
542622da
OD		 1740
1741static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1742{
1743 u32 pci_config_dword;
1744
1745 if (noioapicquirk)
1746 return;
4fd8bdc5
SA		 1747 if ((dev->revision == AMD_813X_REV_B1) ||
1748 (dev->revision == AMD_813X_REV_B2))
bbe19443 1749 return;
542622da
OD		 1750
1751 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1752 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1753 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1754
fdcdaf6c
BH		 1755 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1756 dev->vendor, dev->device);
542622da 1757}
4fd8bdc5
SA		 1758DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1759DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1760DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1761DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
542622da
OD		 1762
1763#define AMD_8111_PCI_IRQ_ROUTING 0x56
1764
1765static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1766{
1767 u16 pci_config_word;
1768
1769 if (noioapicquirk)
1770 return;
1771
1772 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1773 if (!pci_config_word) {
fdcdaf6c
BH		 1774 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1775 "already disabled\n", dev->vendor, dev->device);
542622da
OD		 1776 return;
1777 }
1778 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
fdcdaf6c
BH		 1779 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1780 dev->vendor, dev->device);
542622da 1781}
88d1dce3
OD		 1782DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1783DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
426b3b8d
SA		 1784#endif /* CONFIG_X86_IO_APIC */
1785
33dced2e
SS		 1786/*
1787 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1788 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1789 * Re-allocate the region if needed...
1790 */
1791static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1792{
1793 struct resource *r = &dev->resource[0];
1794
1795 if (r->start & 0x8) {
1796 r->start = 0;
1797 r->end = 0xf;
1798 }
1799}
1800DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1801 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1802 quirk_tc86c001_ide);
1803
1da177e4
LT		 1804static void __devinit quirk_netmos(struct pci_dev *dev)
1805{
1806 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1807 unsigned int num_serial = dev->subsystem_device & 0xf;
1808
1809 /*
1810 * These Netmos parts are multiport serial devices with optional
1811 * parallel ports. Even when parallel ports are present, they
1812 * are identified as class SERIAL, which means the serial driver
1813 * will claim them. To prevent this, mark them as class OTHER.
1814 * These combo devices should be claimed by parport_serial.
1815 *
1816 * The subdevice ID is of the form 0x00PS, where <P> is the number
1817 * of parallel ports and <S> is the number of serial ports.
1818 */
1819 switch (dev->device) {
4c9c1686
JS		 1820 case PCI_DEVICE_ID_NETMOS_9835:
1821 /* Well, this rule doesn't hold for the following 9835 device */
1822 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1823 dev->subsystem_device == 0x0299)
1824 return;
1da177e4
LT		 1825 case PCI_DEVICE_ID_NETMOS_9735:
1826 case PCI_DEVICE_ID_NETMOS_9745:
1da177e4
LT		 1827 case PCI_DEVICE_ID_NETMOS_9845:
1828 case PCI_DEVICE_ID_NETMOS_9855:
1829 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1830 num_parallel) {
f0fda801 1831 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1da177e4
LT		 1832 "%u serial); changing class SERIAL to OTHER "
1833 "(use parport_serial)\n",
1834 dev->device, num_parallel, num_serial);
1835 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1836 (dev->class & 0xff);
1837 }
1838 }
1839}
1840DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1841
16a74744
BH		 1842static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1843{
e64aeccb 1844 u16 command, pmcsr;
16a74744
BH		 1845 u8 __iomem *csr;
1846 u8 cmd_hi;
e64aeccb 1847 int pm;
16a74744
BH		 1848
1849 switch (dev->device) {
1850 /* PCI IDs taken from drivers/net/e100.c */
1851 case 0x1029:
1852 case 0x1030 ... 0x1034:
1853 case 0x1038 ... 0x103E:
1854 case 0x1050 ... 0x1057:
1855 case 0x1059:
1856 case 0x1064 ... 0x106B:
1857 case 0x1091 ... 0x1095:
1858 case 0x1209:
1859 case 0x1229:
1860 case 0x2449:
1861 case 0x2459:
1862 case 0x245D:
1863 case 0x27DC:
1864 break;
1865 default:
1866 return;
1867 }
1868
1869 /*
1870 * Some firmware hands off the e100 with interrupts enabled,
1871 * which can cause a flood of interrupts if packets are
1872 * received before the driver attaches to the device. So
1873 * disable all e100 interrupts here. The driver will
1874 * re-enable them when it's ready.
1875 */
1876 pci_read_config_word(dev, PCI_COMMAND, &command);
16a74744 1877
1bef7dc0 1878 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
16a74744
BH		 1879 return;
1880
e64aeccb
IK		 1881 /*
1882 * Check that the device is in the D0 power state. If it's not,
1883 * there is no point to look any further.
1884 */
1885 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1886 if (pm) {
1887 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1888 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1889 return;
1890 }
1891
1bef7dc0
BH		 1892 /* Convert from PCI bus to resource space. */
1893 csr = ioremap(pci_resource_start(dev, 0), 8);
16a74744 1894 if (!csr) {
f0fda801 1895 dev_warn(&dev->dev, "Can't map e100 registers\n");
16a74744
BH		 1896 return;
1897 }
1898
1899 cmd_hi = readb(csr + 3);
1900 if (cmd_hi == 0) {
f0fda801 1901 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1902 "disabling\n");
16a74744
BH		 1903 writeb(1, csr + 3);
1904 }
1905
1906 iounmap(csr);
1907}
4e68fc97 1908DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
a5312e28 1909
649426ef
AD		 1910/*
1911 * The 82575 and 82598 may experience data corruption issues when transitioning
1912 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1913 */
1914static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1915{
1916 dev_info(&dev->dev, "Disabling L0s\n");
1917 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1918}
1919DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1920DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1921DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1922DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1923DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1924DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1925DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1926DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1927DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1928DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1931DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1932DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1933
a5312e28
IK		 1934static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1935{
1936 /* rev 1 ncr53c810 chips don't set the class at all which means
1937 * they don't get their resources remapped. Fix that here.
1938 */
1939
1940 if (dev->class == PCI_CLASS_NOT_DEFINED) {
f0fda801 1941 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
a5312e28
IK		 1942 dev->class = PCI_CLASS_STORAGE_SCSI;
1943 }
1944}
1945DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1946
9d265124
DY		 1947/* Enable 1k I/O space granularity on the Intel P64H2 */
1948static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1949{
1950 u16 en1k;
1951 u8 io_base_lo, io_limit_lo;
1952 unsigned long base, limit;
1953 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1954
1955 pci_read_config_word(dev, 0x40, &en1k);
1956
1957 if (en1k & 0x200) {
f0fda801 1958 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
9d265124
DY		 1959
1960 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1961 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1962 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1963 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1964
1965 if (base <= limit) {
1966 res->start = base;
1967 res->end = limit + 0x3ff;
1968 }
1969 }
1970}
1971DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1972
15a260d5
DY		 1973/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1974 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1975 * in drivers/pci/setup-bus.c
1976 */
1977static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1978{
1979 u16 en1k, iobl_adr, iobl_adr_1k;
1980 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1981
1982 pci_read_config_word(dev, 0x40, &en1k);
1983
1984 if (en1k & 0x200) {
1985 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1986
1987 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1988
1989 if (iobl_adr != iobl_adr_1k) {
f0fda801 1990 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
15a260d5
DY		 1991 iobl_adr,iobl_adr_1k);
1992 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1993 }
1994 }
1995}
1996DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1997
cf34a8e0
BG		 1998/* Under some circumstances, AER is not linked with extended capabilities.
1999 * Force it to be linked by setting the corresponding control bit in the
2000 * config space.
2001 */
1597cacb 2002static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
cf34a8e0
BG		 2003{
2004 uint8_t b;
2005 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2006 if (!(b & 0x20)) {
2007 pci_write_config_byte(dev, 0xf41, b | 0x20);
f0fda801 2008 dev_info(&dev->dev,
2009 "Linking AER extended capability\n");
cf34a8e0
BG		 2010 }
2011 }
2012}
2013DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2014 quirk_nvidia_ck804_pcie_aer_ext_cap);
e1a2a51e 2015DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1597cacb 2016 quirk_nvidia_ck804_pcie_aer_ext_cap);
cf34a8e0 2017
53a9bf42
TY		 2018static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2019{
2020 /*
2021 * Disable PCI Bus Parking and PCI Master read caching on CX700
2022 * which causes unspecified timing errors with a VT6212L on the PCI
ca846392
TY		 2023 * bus leading to USB2.0 packet loss.
2024 *
2025 * This quirk is only enabled if a second (on the external PCI bus)
2026 * VT6212L is found -- the CX700 core itself also contains a USB
2027 * host controller with the same PCI ID as the VT6212L.
53a9bf42
TY		 2028 */
2029
ca846392
TY		 2030 /* Count VT6212L instances */
2031 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2032 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
53a9bf42 2033 uint8_t b;
ca846392
TY		 2034
2035 /* p should contain the first (internal) VT6212L -- see if we have
2036 an external one by searching again */
2037 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2038 if (!p)
2039 return;
2040 pci_dev_put(p);
2041
53a9bf42
TY		 2042 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2043 if (b & 0x40) {
2044 /* Turn off PCI Bus Parking */
2045 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2046
bc043274
TY		 2047 dev_info(&dev->dev,
2048 "Disabling VIA CX700 PCI parking\n");
2049 }
2050 }
2051
2052 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2053 if (b != 0) {
53a9bf42
TY		 2054 /* Turn off PCI Master read caching */
2055 pci_write_config_byte(dev, 0x72, 0x0);
bc043274
TY		 2056
2057 /* Set PCI Master Bus time-out to "1x16 PCLK" */
53a9bf42 2058 pci_write_config_byte(dev, 0x75, 0x1);
bc043274
TY		 2059
2060 /* Disable "Read FIFO Timer" */
53a9bf42
TY		 2061 pci_write_config_byte(dev, 0x77, 0x0);
2062
d6505a52 2063 dev_info(&dev->dev,
bc043274 2064 "Disabling VIA CX700 PCI caching\n");
53a9bf42
TY		 2065 }
2066 }
2067}
ca846392 2068DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
53a9bf42 2069
99cb233d
BL		 2070/*
2071 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2072 * VPD end tag will hang the device. This problem was initially
2073 * observed when a vpd entry was created in sysfs
2074 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2075 * will dump 32k of data. Reading a full 32k will cause an access
2076 * beyond the VPD end tag causing the device to hang. Once the device
2077 * is hung, the bnx2 driver will not be able to reset the device.
2078 * We believe that it is legal to read beyond the end tag and
2079 * therefore the solution is to limit the read/write length.
2080 */
2081static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2082{
9d82d8ea 2083 /*
35405f25
DH		 2084 * Only disable the VPD capability for 5706, 5706S, 5708,
2085 * 5708S and 5709 rev. A
9d82d8ea 2086 */
99cb233d 2087 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
35405f25 2088 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
99cb233d 2089 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
9d82d8ea 2090 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
99cb233d
BL		 2091 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2092 (dev->revision & 0xf0) == 0x0)) {
2093 if (dev->vpd)
2094 dev->vpd->len = 0x80;
2095 }
2096}
2097
bffadffd
YZ		 2098DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2099 PCI_DEVICE_ID_NX2_5706,
2100 quirk_brcm_570x_limit_vpd);
2101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2102 PCI_DEVICE_ID_NX2_5706S,
2103 quirk_brcm_570x_limit_vpd);
2104DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2105 PCI_DEVICE_ID_NX2_5708,
2106 quirk_brcm_570x_limit_vpd);
2107DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2108 PCI_DEVICE_ID_NX2_5708S,
2109 quirk_brcm_570x_limit_vpd);
2110DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2111 PCI_DEVICE_ID_NX2_5709,
2112 quirk_brcm_570x_limit_vpd);
2113DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2114 PCI_DEVICE_ID_NX2_5709S,
2115 quirk_brcm_570x_limit_vpd);
99cb233d 2116
26c56dc0
MM		 2117/* Originally in EDAC sources for i82875P:
2118 * Intel tells BIOS developers to hide device 6 which
2119 * configures the overflow device access containing
2120 * the DRBs - this is where we expose device 6.
2121 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2122 */
2123static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2124{
2125 u8 reg;
2126
2127 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2128 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2129 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2130 }
2131}
2132
2133DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2134 quirk_unhide_mch_dev6);
2135DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2136 quirk_unhide_mch_dev6);
2137
2138
3f79e107 2139#ifdef CONFIG_PCI_MSI
ebdf7d39
TH		 2140/* Some chipsets do not support MSI. We cannot easily rely on setting
2141 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2142 * some other busses controlled by the chipset even if Linux is not
2143 * aware of it. Instead of setting the flag on all busses in the
2144 * machine, simply disable MSI globally.
3f79e107 2145 */
ebdf7d39 2146static void __init quirk_disable_all_msi(struct pci_dev *dev)
3f79e107 2147{
88187dfa 2148 pci_no_msi();
f0fda801 2149 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
3f79e107 2150}
ebdf7d39
TH		 2151DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2152DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2153DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
66d715c9 2154DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
184b812f 2155DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
162dedd3 2156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
549e1561 2157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
3f79e107
BG		 2158
2159/* Disable MSI on chipsets that are known to not support it */
2160static void __devinit quirk_disable_msi(struct pci_dev *dev)
2161{
2162 if (dev->subordinate) {
f0fda801 2163 dev_warn(&dev->dev, "MSI quirk detected; "
2164 "subordinate MSI disabled\n");
3f79e107
BG		 2165 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2166 }
2167}
2168DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
134b3450 2169DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
9313ff45 2170DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
6397c75c 2171
aff61369
CL		 2172/*
2173 * The APC bridge device in AMD 780 family northbridges has some random
2174 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2175 * we use the possible vendor/device IDs of the host bridge for the
2176 * declared quirk, and search for the APC bridge by slot number.
2177 */
2178static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2179{
2180 struct pci_dev *apc_bridge;
2181
2182 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2183 if (apc_bridge) {
2184 if (apc_bridge->device == 0x9602)
2185 quirk_disable_msi(apc_bridge);
2186 pci_dev_put(apc_bridge);
2187 }
2188}
2189DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2190DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2191
6397c75c
BG		 2192/* Go through the list of Hypertransport capabilities and
2193 * return 1 if a HT MSI capability is found and enabled */
2194static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2195{
7a380507
ME		 2196 int pos, ttl = 48;
2197
2198 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2199 while (pos && ttl--) {
2200 u8 flags;
2201
2202 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2203 &flags) == 0)
2204 {
f0fda801 2205 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
7a380507 2206 flags & HT_MSI_FLAGS_ENABLE ?
f0fda801 2207 "enabled" : "disabled");
7a380507 2208 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
6397c75c 2209 }
7a380507
ME		 2210
2211 pos = pci_find_next_ht_capability(dev, pos,
2212 HT_CAPTYPE_MSI_MAPPING);
6397c75c
BG		 2213 }
2214 return 0;
2215}
2216
2217/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2218static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2219{
2220 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
f0fda801 2221 dev_warn(&dev->dev, "MSI quirk detected; "
2222 "subordinate MSI disabled\n");
6397c75c
BG		 2223 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2224 }
2225}
2226DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2227 quirk_msi_ht_cap);
6bae1d96 2228
6397c75c
BG		 2229/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2230 * MSI are supported if the MSI capability set in any of these mappings.
2231 */
2232static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2233{
2234 struct pci_dev *pdev;
2235
2236 if (!dev->subordinate)
2237 return;
2238
2239 /* check HT MSI cap on this chipset and the root one.
2240 * a single one having MSI is enough to be sure that MSI are supported.
2241 */
11f242f0 2242 pdev = pci_get_slot(dev->bus, 0);
9ac0ce85
JJ		 2243 if (!pdev)
2244 return;
0c875c28 2245 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
f0fda801 2246 dev_warn(&dev->dev, "MSI quirk detected; "
2247 "subordinate MSI disabled\n");
6397c75c
BG		 2248 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2249 }
11f242f0 2250 pci_dev_put(pdev);
6397c75c
BG		 2251}
2252DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2253 quirk_nvidia_ck804_msi_ht_cap);
ba698ad4 2254
415b6d0e
BH		 2255/* Force enable MSI mapping capability on HT bridges */
2256static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2257{
2258 int pos, ttl = 48;
2259
2260 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2261 while (pos && ttl--) {
2262 u8 flags;
2263
2264 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2265 &flags) == 0) {
2266 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2267
2268 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2269 flags | HT_MSI_FLAGS_ENABLE);
2270 }
2271 pos = pci_find_next_ht_capability(dev, pos,
2272 HT_CAPTYPE_MSI_MAPPING);
2273 }
2274}
415b6d0e
BH		 2275DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2276 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2277 ht_enable_msi_mapping);
9dc625e7 2278
e0ae4f55
YL		 2279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2280 ht_enable_msi_mapping);
2281
e4146bb9 2282/* The P5N32-SLI motherboards from Asus have a problem with msi
75e07fc3
AP		 2283 * for the MCP55 NIC. It is not yet determined whether the msi problem
2284 * also affects other devices. As for now, turn off msi for this device.
2285 */
2286static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2287{
e4146bb9
BH		 2288 if (dmi_name_in_vendors("P5N32-SLI PREMIUM") ||
2289 dmi_name_in_vendors("P5N32-E SLI")) {
75e07fc3 2290 dev_info(&dev->dev,
e4146bb9 2291 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
75e07fc3
AP		 2292 dev->no_msi = 1;
2293 }
2294}
2295DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2296 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2297 nvenet_msi_disable);
2298
de745306
YL		 2299static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2300{
2301 int pos, ttl = 48;
2302 int found = 0;
2303
2304 /* check if there is HT MSI cap or enabled on this device */
2305 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2306 while (pos && ttl--) {
2307 u8 flags;
2308
2309 if (found < 1)
2310 found = 1;
2311 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2312 &flags) == 0) {
2313 if (flags & HT_MSI_FLAGS_ENABLE) {
2314 if (found < 2) {
2315 found = 2;
2316 break;
2317 }
2318 }
2319 }
2320 pos = pci_find_next_ht_capability(dev, pos,
2321 HT_CAPTYPE_MSI_MAPPING);
2322 }
2323
2324 return found;
2325}
2326
2327static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2328{
2329 struct pci_dev *dev;
2330 int pos;
2331 int i, dev_no;
2332 int found = 0;
2333
2334 dev_no = host_bridge->devfn >> 3;
2335 for (i = dev_no + 1; i < 0x20; i++) {
2336 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2337 if (!dev)
2338 continue;
2339
2340 /* found next host bridge ?*/
2341 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2342 if (pos != 0) {
2343 pci_dev_put(dev);
2344 break;
2345 }
2346
2347 if (ht_check_msi_mapping(dev)) {
2348 found = 1;
2349 pci_dev_put(dev);
2350 break;
2351 }
2352 pci_dev_put(dev);
2353 }
2354
2355 return found;
2356}
2357
eeafda70
YL		 2358#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2359#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2360
2361static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2362{
2363 int pos, ctrl_off;
2364 int end = 0;
2365 u16 flags, ctrl;
2366
2367 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2368
2369 if (!pos)
2370 goto out;
2371
2372 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2373
2374 ctrl_off = ((flags >> 10) & 1) ?
2375 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2376 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2377
2378 if (ctrl & (1 << 6))
2379 end = 1;
2380
2381out:
2382 return end;
2383}
2384
1dec6b05 2385static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2386{
2387 struct pci_dev *host_bridge;
1dec6b05
YL		 2388 int pos;
2389 int i, dev_no;
2390 int found = 0;
2391
2392 dev_no = dev->devfn >> 3;
2393 for (i = dev_no; i >= 0; i--) {
2394 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2395 if (!host_bridge)
2396 continue;
2397
2398 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2399 if (pos != 0) {
2400 found = 1;
2401 break;
2402 }
2403 pci_dev_put(host_bridge);
2404 }
2405
2406 if (!found)
2407 return;
2408
eeafda70
YL		 2409 /* don't enable end_device/host_bridge with leaf directly here */
2410 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2411 host_bridge_with_leaf(host_bridge))
de745306
YL		 2412 goto out;
2413
1dec6b05
YL		 2414 /* root did that ! */
2415 if (msi_ht_cap_enabled(host_bridge))
2416 goto out;
2417
2418 ht_enable_msi_mapping(dev);
2419
2420out:
2421 pci_dev_put(host_bridge);
2422}
2423
2424static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2425{
2426 int pos, ttl = 48;
2427
2428 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2429 while (pos && ttl--) {
2430 u8 flags;
2431
2432 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2433 &flags) == 0) {
6a958d5b 2434 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
1dec6b05
YL		 2435
2436 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2437 flags & ~HT_MSI_FLAGS_ENABLE);
2438 }
2439 pos = pci_find_next_ht_capability(dev, pos,
2440 HT_CAPTYPE_MSI_MAPPING);
2441 }
2442}
2443
de745306 2444static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
1dec6b05
YL		 2445{
2446 struct pci_dev *host_bridge;
2447 int pos;
2448 int found;
2449
3d2a5318
RW		 2450 if (!pci_msi_enabled())
2451 return;
2452
1dec6b05
YL		 2453 /* check if there is HT MSI cap or enabled on this device */
2454 found = ht_check_msi_mapping(dev);
2455
2456 /* no HT MSI CAP */
2457 if (found == 0)
2458 return;
9dc625e7
PC		 2459
2460 /*
2461 * HT MSI mapping should be disabled on devices that are below
2462 * a non-Hypertransport host bridge. Locate the host bridge...
2463 */
2464 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2465 if (host_bridge == NULL) {
2466 dev_warn(&dev->dev,
2467 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2468 return;
2469 }
2470
2471 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2472 if (pos != 0) {
2473 /* Host bridge is to HT */
1dec6b05
YL		 2474 if (found == 1) {
2475 /* it is not enabled, try to enable it */
de745306
YL		 2476 if (all)
2477 ht_enable_msi_mapping(dev);
2478 else
2479 nv_ht_enable_msi_mapping(dev);
1dec6b05 2480 }
9dc625e7
PC		 2481 return;
2482 }
2483
1dec6b05
YL		 2484 /* HT MSI is not enabled */
2485 if (found == 1)
2486 return;
9dc625e7 2487
1dec6b05
YL		 2488 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2489 ht_disable_msi_mapping(dev);
9dc625e7 2490}
de745306
YL		 2491
2492static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2493{
2494 return __nv_msi_ht_cap_quirk(dev, 1);
2495}
2496
2497static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2498{
2499 return __nv_msi_ht_cap_quirk(dev, 0);
2500}
2501
2502DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
6dab62ee 2503DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
de745306
YL		 2504
2505DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
6dab62ee 2506DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
9dc625e7 2507
ba698ad4
DM		 2508static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2509{
2510 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2511}
4600c9d7
SH		 2512static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2513{
2514 struct pci_dev *p;
2515
2516 /* SB700 MSI issue will be fixed at HW level from revision A21,
2517 * we need check PCI REVISION ID of SMBus controller to get SB700
2518 * revision.
2519 */
2520 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2521 NULL);
2522 if (!p)
2523 return;
2524
2525 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2526 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2527 pci_dev_put(p);
2528}
ba698ad4
DM		 2529DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2530 PCI_DEVICE_ID_TIGON3_5780,
2531 quirk_msi_intx_disable_bug);
2532DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2533 PCI_DEVICE_ID_TIGON3_5780S,
2534 quirk_msi_intx_disable_bug);
2535DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2536 PCI_DEVICE_ID_TIGON3_5714,
2537 quirk_msi_intx_disable_bug);
2538DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2539 PCI_DEVICE_ID_TIGON3_5714S,
2540 quirk_msi_intx_disable_bug);
2541DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2542 PCI_DEVICE_ID_TIGON3_5715,
2543 quirk_msi_intx_disable_bug);
2544DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2545 PCI_DEVICE_ID_TIGON3_5715S,
2546 quirk_msi_intx_disable_bug);
2547
bc38b411 2548DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
4600c9d7 2549 quirk_msi_intx_disable_ati_bug);
bc38b411 2550DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
4600c9d7 2551 quirk_msi_intx_disable_ati_bug);
bc38b411 2552DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
4600c9d7 2553 quirk_msi_intx_disable_ati_bug);
bc38b411 2554DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
4600c9d7 2555 quirk_msi_intx_disable_ati_bug);
bc38b411 2556DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
4600c9d7 2557 quirk_msi_intx_disable_ati_bug);
bc38b411
DM		 2558
2559DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2560 quirk_msi_intx_disable_bug);
2561DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2562 quirk_msi_intx_disable_bug);
2563DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2564 quirk_msi_intx_disable_bug);
2565
3f79e107 2566#endif /* CONFIG_PCI_MSI */
3d137310 2567
7eb93b17
YZ		 2568#ifdef CONFIG_PCI_IOV
2569
2570/*
2571 * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the
2572 * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the
2573 * old Flash Memory Space.
2574 */
2575static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
2576{
2577 int pos, flags;
2578 u32 bar, start, size;
2579
2580 if (PAGE_SIZE > 0x10000)
2581 return;
2582
2583 flags = pci_resource_flags(dev, 0);
2584 if ((flags & PCI_BASE_ADDRESS_SPACE) !=
2585 PCI_BASE_ADDRESS_SPACE_MEMORY ||
2586 (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !=
2587 PCI_BASE_ADDRESS_MEM_TYPE_32)
2588 return;
2589
2590 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
2591 if (!pos)
2592 return;
2593
2594 pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
2595 if (bar & PCI_BASE_ADDRESS_MEM_MASK)
2596 return;
2597
2598 start = pci_resource_start(dev, 1);
2599 size = pci_resource_len(dev, 1);
2600 if (!start || size != 0x400000 || start & (size - 1))
2601 return;
2602
2603 pci_resource_flags(dev, 1) = 0;
2604 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
2605 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
2606 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
2607
2608 dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n");
2609}
2610DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
2611DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
2612DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
dcb4ea2e
AD		 2613DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov);
2614DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov);
6f1186be 2615DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov);
7a0deb6b 2616DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1518, quirk_i82576_sriov);
7eb93b17
YZ		 2617
2618#endif /* CONFIG_PCI_IOV */
2619
3322340a
FR		 2620/* Allow manual resource allocation for PCI hotplug bridges
2621 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2622 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2623 * kernel fails to allocate resources when hotplug device is
2624 * inserted and PCI bus is rescanned.
2625 */
2626static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2627{
2628 dev->is_hotplug_bridge = 1;
2629}
2630
2631DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2632
03cd8f7e
ML		 2633/*
2634 * This is a quirk for the Ricoh MMC controller found as a part of
2635 * some mulifunction chips.
2636
2637 * This is very similiar and based on the ricoh_mmc driver written by
2638 * Philip Langdale. Thank you for these magic sequences.
2639 *
2640 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2641 * and one or both of cardbus or firewire.
2642 *
2643 * It happens that they implement SD and MMC
2644 * support as separate controllers (and PCI functions). The linux SDHCI
2645 * driver supports MMC cards but the chip detects MMC cards in hardware
2646 * and directs them to the MMC controller - so the SDHCI driver never sees
2647 * them.
2648 *
2649 * To get around this, we must disable the useless MMC controller.
2650 * At that point, the SDHCI controller will start seeing them
2651 * It seems to be the case that the relevant PCI registers to deactivate the
2652 * MMC controller live on PCI function 0, which might be the cardbus controller
2653 * or the firewire controller, depending on the particular chip in question
2654 *
2655 * This has to be done early, because as soon as we disable the MMC controller
2656 * other pci functions shift up one level, e.g. function #2 becomes function
2657 * #1, and this will confuse the pci core.
2658 */
2659
2660#ifdef CONFIG_MMC_RICOH_MMC
2661static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2662{
2663 /* disable via cardbus interface */
2664 u8 write_enable;
2665 u8 write_target;
2666 u8 disable;
2667
2668 /* disable must be done via function #0 */
2669 if (PCI_FUNC(dev->devfn))
2670 return;
2671
2672 pci_read_config_byte(dev, 0xB7, &disable);
2673 if (disable & 0x02)
2674 return;
2675
2676 pci_read_config_byte(dev, 0x8E, &write_enable);
2677 pci_write_config_byte(dev, 0x8E, 0xAA);
2678 pci_read_config_byte(dev, 0x8D, &write_target);
2679 pci_write_config_byte(dev, 0x8D, 0xB7);
2680 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2681 pci_write_config_byte(dev, 0x8E, write_enable);
2682 pci_write_config_byte(dev, 0x8D, write_target);
2683
2684 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2685 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2686}
2687DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2688DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2689
2690static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2691{
2692 /* disable via firewire interface */
2693 u8 write_enable;
2694 u8 disable;
2695
2696 /* disable must be done via function #0 */
2697 if (PCI_FUNC(dev->devfn))
2698 return;
2699
2700 pci_read_config_byte(dev, 0xCB, &disable);
2701
2702 if (disable & 0x02)
2703 return;
2704
2705 pci_read_config_byte(dev, 0xCA, &write_enable);
2706 pci_write_config_byte(dev, 0xCA, 0x57);
2707 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2708 pci_write_config_byte(dev, 0xCA, write_enable);
2709
2710 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2711 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2712}
2713DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2714DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2715#endif /*CONFIG_MMC_RICOH_MMC*/
2716
2717
bfb0f330
JB		 2718static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2719 struct pci_fixup *end)
3d137310
TP		 2720{
2721 while (f < end) {
2722 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
bfb0f330 2723 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
c9bbb4ab 2724 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
3d137310
TP		 2725 f->hook(dev);
2726 }
2727 f++;
2728 }
2729}
2730
2731extern struct pci_fixup __start_pci_fixups_early[];
2732extern struct pci_fixup __end_pci_fixups_early[];
2733extern struct pci_fixup __start_pci_fixups_header[];
2734extern struct pci_fixup __end_pci_fixups_header[];
2735extern struct pci_fixup __start_pci_fixups_final[];
2736extern struct pci_fixup __end_pci_fixups_final[];
2737extern struct pci_fixup __start_pci_fixups_enable[];
2738extern struct pci_fixup __end_pci_fixups_enable[];
2739extern struct pci_fixup __start_pci_fixups_resume[];
2740extern struct pci_fixup __end_pci_fixups_resume[];
2741extern struct pci_fixup __start_pci_fixups_resume_early[];
2742extern struct pci_fixup __end_pci_fixups_resume_early[];
2743extern struct pci_fixup __start_pci_fixups_suspend[];
2744extern struct pci_fixup __end_pci_fixups_suspend[];
2745
2746
2747void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2748{
2749 struct pci_fixup *start, *end;
2750
2751 switch(pass) {
2752 case pci_fixup_early:
2753 start = __start_pci_fixups_early;
2754 end = __end_pci_fixups_early;
2755 break;
2756
2757 case pci_fixup_header:
2758 start = __start_pci_fixups_header;
2759 end = __end_pci_fixups_header;
2760 break;
2761
2762 case pci_fixup_final:
2763 start = __start_pci_fixups_final;
2764 end = __end_pci_fixups_final;
2765 break;
2766
2767 case pci_fixup_enable:
2768 start = __start_pci_fixups_enable;
2769 end = __end_pci_fixups_enable;
2770 break;
2771
2772 case pci_fixup_resume:
2773 start = __start_pci_fixups_resume;
2774 end = __end_pci_fixups_resume;
2775 break;
2776
2777 case pci_fixup_resume_early:
2778 start = __start_pci_fixups_resume_early;
2779 end = __end_pci_fixups_resume_early;
2780 break;
2781
2782 case pci_fixup_suspend:
2783 start = __start_pci_fixups_suspend;
2784 end = __end_pci_fixups_suspend;
2785 break;
2786
2787 default:
2788 /* stupid compiler warning, you would think with an enum... */
2789 return;
2790 }
2791 pci_do_fixups(dev, start, end);
2792}
93177a74 2793EXPORT_SYMBOL(pci_fixup_device);
8d86fb2c 2794
00010268 2795static int __init pci_apply_final_quirks(void)
8d86fb2c
DW		 2796{
2797 struct pci_dev *dev = NULL;
ac1aa47b
JB		 2798 u8 cls = 0;
2799 u8 tmp;
2800
2801 if (pci_cache_line_size)
2802 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
2803 pci_cache_line_size << 2);
8d86fb2c 2804
4e344b1c 2805 for_each_pci_dev(dev) {
8d86fb2c 2806 pci_fixup_device(pci_fixup_final, dev);
ac1aa47b
JB		 2807 /*
2808 * If arch hasn't set it explicitly yet, use the CLS
2809 * value shared by all PCI devices. If there's a
2810 * mismatch, fall back to the default value.
2811 */
2812 if (!pci_cache_line_size) {
2813 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
2814 if (!cls)
2815 cls = tmp;
2816 if (!tmp || cls == tmp)
2817 continue;
2818
2819 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
2820 "using %u bytes\n", cls << 2, tmp << 2,
2821 pci_dfl_cache_line_size << 2);
2822 pci_cache_line_size = pci_dfl_cache_line_size;
2823 }
2824 }
2825 if (!pci_cache_line_size) {
2826 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
2827 cls << 2, pci_dfl_cache_line_size << 2);
2820f333 2828 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
8d86fb2c
DW		 2829 }
2830
2831 return 0;
2832}
2833
cf6f3bf7 2834fs_initcall_sync(pci_apply_final_quirks);
b9c3b266
DC		 2835
2836/*
2837 * Followings are device-specific reset methods which can be used to
2838 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
2839 * not available.
2840 */
aeb30016
DC		 2841static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
2842{
2843 int pos;
2844
2845 /* only implement PCI_CLASS_SERIAL_USB at present */
2846 if (dev->class == PCI_CLASS_SERIAL_USB) {
2847 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
2848 if (!pos)
2849 return -ENOTTY;
2850
2851 if (probe)
2852 return 0;
2853
2854 pci_write_config_byte(dev, pos + 0x4, 1);
2855 msleep(100);
2856
2857 return 0;
2858 } else {
2859 return -ENOTTY;
2860 }
2861}
2862
c763e7b5
DC		 2863static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
2864{
2865 int pos;
2866
2867 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2868 if (!pos)
2869 return -ENOTTY;
2870
2871 if (probe)
2872 return 0;
2873
2874 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
2875 PCI_EXP_DEVCTL_BCR_FLR);
2876 msleep(100);
2877
2878 return 0;
2879}
2880
2881#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
2882
5b889bf2 2883static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
c763e7b5
DC		 2884 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
2885 reset_intel_82599_sfp_virtfn },
aeb30016
DC		 2886 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2887 reset_intel_generic_dev },
b9c3b266
DC		 2888 { 0 }
2889};
5b889bf2
RW		 2890
2891int pci_dev_specific_reset(struct pci_dev *dev, int probe)
2892{
df9d1e8a 2893 const struct pci_dev_reset_methods *i;
5b889bf2
RW		 2894
2895 for (i = pci_dev_reset_methods; i->reset; i++) {
2896 if ((i->vendor == dev->vendor ||
2897 i->vendor == (u16)PCI_ANY_ID) &&
2898 (i->device == dev->device ||
2899 i->device == (u16)PCI_ANY_ID))
2900 return i->reset(dev, probe);
2901 }
2902
2903 return -ENOTTY;
2904}
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