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pciehp: Remove unnecessary check in pciehp_ctrl.c
[net-next-2.6.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
25be5e6c 23#include <linux/acpi.h>
bc56b9e0 24#include "pci.h"
1da177e4 25
bd8481e1
DT		 26/* The Mellanox Tavor device gives false positive parity errors
27 * Mark this device with a broken_parity_status, to allow
28 * PCI scanning code to "skip" this now blacklisted device.
29 */
30static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
31{
32 dev->broken_parity_status = 1; /* This device gives false positives */
33}
34DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
35DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
36
1da177e4
LT		 37/* Deal with broken BIOS'es that neglect to enable passive release,
38 which can cause problems in combination with the 82441FX/PPro MTRRs */
39static void __devinit quirk_passive_release(struct pci_dev *dev)
40{
41 struct pci_dev *d = NULL;
42 unsigned char dlc;
43
44 /* We have to make sure a particular bit is set in the PIIX3
45 ISA bridge, so we have to go out and find it. */
46 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
47 pci_read_config_byte(d, 0x82, &dlc);
48 if (!(dlc & 1<<1)) {
49 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
50 dlc |= 1<<1;
51 pci_write_config_byte(d, 0x82, dlc);
52 }
53 }
54}
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
56
57/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
58 but VIA don't answer queries. If you happen to have good contacts at VIA
59 ask them for me please -- Alan
60
61 This appears to be BIOS not version dependent. So presumably there is a
62 chipset level fix */
63int isa_dma_bridge_buggy; /* Exported */
64
65static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
66{
67 if (!isa_dma_bridge_buggy) {
68 isa_dma_bridge_buggy=1;
69 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
70 }
71}
72 /*
73 * Its not totally clear which chipsets are the problematic ones
74 * We know 82C586 and 82C596 variants are affected.
75 */
76DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
77DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
78DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
79DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
80DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
81DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
83
84int pci_pci_problems;
85
86/*
87 * Chipsets where PCI->PCI transfers vanish or hang
88 */
89static void __devinit quirk_nopcipci(struct pci_dev *dev)
90{
91 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
92 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
93 pci_pci_problems |= PCIPCI_FAIL;
94 }
95}
236561e5
AC		 96
97static void __devinit quirk_nopciamd(struct pci_dev *dev)
98{
99 u8 rev;
100 pci_read_config_byte(dev, 0x08, &rev);
101 if (rev == 0x13) {
102 /* Erratum 24 */
103 printk(KERN_INFO "Chipset erratum: Disabling direct PCI/AGP transfers.\n");
104 pci_pci_problems |= PCIAGP_FAIL;
105 }
106}
107
1da177e4
LT		 108DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
109DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
236561e5 110DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd );
1da177e4
LT		 111
112/*
113 * Triton requires workarounds to be used by the drivers
114 */
115static void __devinit quirk_triton(struct pci_dev *dev)
116{
117 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
118 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
119 pci_pci_problems |= PCIPCI_TRITON;
120 }
121}
122DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
123DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
124DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
125DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
126
127/*
128 * VIA Apollo KT133 needs PCI latency patch
129 * Made according to a windows driver based patch by George E. Breese
130 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
131 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
132 * the info on which Mr Breese based his work.
133 *
134 * Updated based on further information from the site and also on
135 * information provided by VIA
136 */
137static void __devinit quirk_vialatency(struct pci_dev *dev)
138{
139 struct pci_dev *p;
140 u8 rev;
141 u8 busarb;
142 /* Ok we have a potential problem chipset here. Now see if we have
143 a buggy southbridge */
144
145 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
146 if (p!=NULL) {
147 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
148 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
149 /* Check for buggy part revisions */
150 if (rev < 0x40 || rev > 0x42)
151 goto exit;
152 } else {
153 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
154 if (p==NULL) /* No problem parts */
155 goto exit;
156 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
157 /* Check for buggy part revisions */
158 if (rev < 0x10 || rev > 0x12)
159 goto exit;
160 }
161
162 /*
163 * Ok we have the problem. Now set the PCI master grant to
164 * occur every master grant. The apparent bug is that under high
165 * PCI load (quite common in Linux of course) you can get data
166 * loss when the CPU is held off the bus for 3 bus master requests
167 * This happens to include the IDE controllers....
168 *
169 * VIA only apply this fix when an SB Live! is present but under
170 * both Linux and Windows this isnt enough, and we have seen
171 * corruption without SB Live! but with things like 3 UDMA IDE
172 * controllers. So we ignore that bit of the VIA recommendation..
173 */
174
175 pci_read_config_byte(dev, 0x76, &busarb);
176 /* Set bit 4 and bi 5 of byte 76 to 0x01
177 "Master priority rotation on every PCI master grant */
178 busarb &= ~(1<<5);
179 busarb |= (1<<4);
180 pci_write_config_byte(dev, 0x76, busarb);
181 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
182exit:
183 pci_dev_put(p);
184}
185DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
186DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
187DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
188
189/*
190 * VIA Apollo VP3 needs ETBF on BT848/878
191 */
192static void __devinit quirk_viaetbf(struct pci_dev *dev)
193{
194 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
195 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
196 pci_pci_problems |= PCIPCI_VIAETBF;
197 }
198}
199DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
200
201static void __devinit quirk_vsfx(struct pci_dev *dev)
202{
203 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
204 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
205 pci_pci_problems |= PCIPCI_VSFX;
206 }
207}
208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
209
210/*
211 * Ali Magik requires workarounds to be used by the drivers
212 * that DMA to AGP space. Latency must be set to 0xA and triton
213 * workaround applied too
214 * [Info kindly provided by ALi]
215 */
216static void __init quirk_alimagik(struct pci_dev *dev)
217{
218 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
219 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
220 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
221 }
222}
223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
224DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
225
226/*
227 * Natoma has some interesting boundary conditions with Zoran stuff
228 * at least
229 */
230static void __devinit quirk_natoma(struct pci_dev *dev)
231{
232 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
233 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
234 pci_pci_problems |= PCIPCI_NATOMA;
235 }
236}
237DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
238DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
240DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
241DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
242DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
243
244/*
245 * This chip can cause PCI parity errors if config register 0xA0 is read
246 * while DMAs are occurring.
247 */
248static void __devinit quirk_citrine(struct pci_dev *dev)
249{
250 dev->cfg_size = 0xA0;
251}
252DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
253
254/*
255 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
256 * If it's needed, re-allocate the region.
257 */
258static void __devinit quirk_s3_64M(struct pci_dev *dev)
259{
260 struct resource *r = &dev->resource[0];
261
262 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
263 r->start = 0;
264 r->end = 0x3ffffff;
265 }
266}
267DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
268DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
269
6693e74a
LT		 270static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
271 unsigned size, int nr, const char *name)
1da177e4
LT		 272{
273 region &= ~(size-1);
274 if (region) {
085ae41f 275 struct pci_bus_region bus_region;
1da177e4
LT		 276 struct resource *res = dev->resource + nr;
277
278 res->name = pci_name(dev);
279 res->start = region;
280 res->end = region + size - 1;
281 res->flags = IORESOURCE_IO;
085ae41f
DM		 282
283 /* Convert from PCI bus to resource space. */
284 bus_region.start = res->start;
285 bus_region.end = res->end;
286 pcibios_bus_to_resource(dev, res, &bus_region);
287
1da177e4 288 pci_claim_resource(dev, nr);
6693e74a 289 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
1da177e4
LT		 290 }
291}
292
293/*
294 * ATI Northbridge setups MCE the processor if you even
295 * read somewhere between 0x3b0->0x3bb or read 0x3d3
296 */
297static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
298{
299 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
300 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
301 request_region(0x3b0, 0x0C, "RadeonIGP");
302 request_region(0x3d3, 0x01, "RadeonIGP");
303}
304DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
305
306/*
307 * Let's make the southbridge information explicit instead
308 * of having to worry about people probing the ACPI areas,
309 * for example.. (Yes, it happens, and if you read the wrong
310 * ACPI register it will put the machine to sleep with no
311 * way of waking it up again. Bummer).
312 *
313 * ALI M7101: Two IO regions pointed to by words at
314 * 0xE0 (64 bytes of ACPI registers)
315 * 0xE2 (32 bytes of SMB registers)
316 */
317static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
318{
319 u16 region;
320
321 pci_read_config_word(dev, 0xE0, &region);
6693e74a 322 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 323 pci_read_config_word(dev, 0xE2, &region);
6693e74a 324 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4
LT		 325}
326DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
327
6693e74a
LT		 328static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
329{
330 u32 devres;
331 u32 mask, size, base;
332
333 pci_read_config_dword(dev, port, &devres);
334 if ((devres & enable) != enable)
335 return;
336 mask = (devres >> 16) & 15;
337 base = devres & 0xffff;
338 size = 16;
339 for (;;) {
340 unsigned bit = size >> 1;
341 if ((bit & mask) == bit)
342 break;
343 size = bit;
344 }
345 /*
346 * For now we only print it out. Eventually we'll want to
347 * reserve it (at least if it's in the 0x1000+ range), but
348 * let's get enough confirmation reports first.
349 */
350 base &= -size;
351 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1);
352}
353
354static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
355{
356 u32 devres;
357 u32 mask, size, base;
358
359 pci_read_config_dword(dev, port, &devres);
360 if ((devres & enable) != enable)
361 return;
362 base = devres & 0xffff0000;
363 mask = (devres & 0x3f) << 16;
364 size = 128 << 16;
365 for (;;) {
366 unsigned bit = size >> 1;
367 if ((bit & mask) == bit)
368 break;
369 size = bit;
370 }
371 /*
372 * For now we only print it out. Eventually we'll want to
373 * reserve it, but let's get enough confirmation reports first.
374 */
375 base &= -size;
376 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1);
377}
378
1da177e4
LT		 379/*
380 * PIIX4 ACPI: Two IO regions pointed to by longwords at
381 * 0x40 (64 bytes of ACPI registers)
08db2a70 382 * 0x90 (16 bytes of SMB registers)
6693e74a 383 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 384 */
385static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
386{
6693e74a 387 u32 region, res_a;
1da177e4
LT		 388
389 pci_read_config_dword(dev, 0x40, &region);
6693e74a 390 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 391 pci_read_config_dword(dev, 0x90, &region);
08db2a70 392 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 393
394 /* Device resource A has enables for some of the other ones */
395 pci_read_config_dword(dev, 0x5c, &res_a);
396
397 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
398 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
399
400 /* Device resource D is just bitfields for static resources */
401
402 /* Device 12 enabled? */
403 if (res_a & (1 << 29)) {
404 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
405 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
406 }
407 /* Device 13 enabled? */
408 if (res_a & (1 << 30)) {
409 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
410 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
411 }
412 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
413 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4
LT		 414}
415DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
c6764664 416DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi );
1da177e4
LT		 417
418/*
419 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
420 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
421 * 0x58 (64 bytes of GPIO I/O space)
422 */
423static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
424{
425 u32 region;
426
427 pci_read_config_dword(dev, 0x40, &region);
6693e74a 428 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 429
430 pci_read_config_dword(dev, 0x58, &region);
6693e74a 431 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4
LT		 432}
433DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
434DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
435DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
436DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
437DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
438DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
3aa8c4fe 442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
1da177e4 443
2cea752f
RM		 444static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
445{
446 u32 region;
447
448 pci_read_config_dword(dev, 0x40, &region);
449 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
450
451 pci_read_config_dword(dev, 0x48, &region);
452 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
453}
65ae4ddd 454DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi );
2cea752f
RM		 455DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
456
1da177e4
LT		 457/*
458 * VIA ACPI: One IO region pointed to by longword at
459 * 0x48 or 0x20 (256 bytes of ACPI registers)
460 */
461static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
462{
463 u8 rev;
464 u32 region;
465
466 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
467 if (rev & 0x10) {
468 pci_read_config_dword(dev, 0x48, &region);
469 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 470 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 471 }
472}
473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
474
475/*
476 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
477 * 0x48 (256 bytes of ACPI registers)
478 * 0x70 (128 bytes of hardware monitoring register)
479 * 0x90 (16 bytes of SMB registers)
480 */
481static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
482{
483 u16 hm;
484 u32 smb;
485
486 quirk_vt82c586_acpi(dev);
487
488 pci_read_config_word(dev, 0x70, &hm);
489 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 490 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 491
492 pci_read_config_dword(dev, 0x90, &smb);
493 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 494 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4
LT		 495}
496DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
497
6d85f29b
IK		 498/*
499 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
500 * 0x88 (128 bytes of power management registers)
501 * 0xd0 (16 bytes of SMB registers)
502 */
503static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
504{
505 u16 pm, smb;
506
507 pci_read_config_word(dev, 0x88, &pm);
508 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 509 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 510
511 pci_read_config_word(dev, 0xd0, &smb);
512 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 513 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 514}
515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
516
1da177e4
LT		 517
518#ifdef CONFIG_X86_IO_APIC
519
520#include <asm/io_apic.h>
521
522/*
523 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
524 * devices to the external APIC.
525 *
526 * TODO: When we have device-specific interrupt routers,
527 * this code will go away from quirks.
528 */
529static void __devinit quirk_via_ioapic(struct pci_dev *dev)
530{
531 u8 tmp;
532
533 if (nr_ioapics < 1)
534 tmp = 0; /* nothing routed to external APIC */
535 else
536 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
537
538 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
539 tmp == 0 ? "Disa" : "Ena");
540
541 /* Offset 0x58: External APIC IRQ output control */
542 pci_write_config_byte (dev, 0x58, tmp);
543}
544DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
545
a1740913
KW		 546/*
547 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
548 * This leads to doubled level interrupt rates.
549 * Set this bit to get rid of cycle wastage.
550 * Otherwise uncritical.
551 */
552static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
553{
554 u8 misc_control2;
555#define BYPASS_APIC_DEASSERT 8
556
557 pci_read_config_byte(dev, 0x5B, &misc_control2);
558 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
559 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
560 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
561 }
562}
563DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
564
1da177e4
LT		 565/*
566 * The AMD io apic can hang the box when an apic irq is masked.
567 * We check all revs >= B0 (yet not in the pre production!) as the bug
568 * is currently marked NoFix
569 *
570 * We have multiple reports of hangs with this chipset that went away with
236561e5 571 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1da177e4
LT		 572 * of course. However the advice is demonstrably good even if so..
573 */
574static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
575{
576 u8 rev;
577
578 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
579 if (rev >= 0x02) {
236561e5 580 printk(KERN_WARNING "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1da177e4
LT		 581 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
582 }
583}
584DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
585
586static void __init quirk_ioapic_rmw(struct pci_dev *dev)
587{
588 if (dev->devfn == 0 && dev->bus->number == 0)
589 sis_apic_bug = 1;
590}
591DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
592
1da177e4
LT		 593#define AMD8131_revA0 0x01
594#define AMD8131_revB0 0x11
595#define AMD8131_MISC 0x40
596#define AMD8131_NIOAMODE_BIT 0
597static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
598{
599 unsigned char revid, tmp;
600
1da177e4
LT		 601 if (nr_ioapics == 0)
602 return;
603
604 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
605 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
606 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
607 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
608 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
609 pci_write_config_byte( dev, AMD8131_MISC, tmp);
610 }
611}
5da594b1 612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
1da177e4
LT		 613#endif /* CONFIG_X86_IO_APIC */
614
615
1da177e4
LT		 616/*
617 * FIXME: it is questionable that quirk_via_acpi
618 * is needed. It shows up as an ISA bridge, and does not
619 * support the PCI_INTERRUPT_LINE register at all. Therefore
620 * it seems like setting the pci_dev's 'irq' to the
621 * value of the ACPI SCI interrupt is only done for convenience.
622 * -jgarzik
623 */
624static void __devinit quirk_via_acpi(struct pci_dev *d)
625{
626 /*
627 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
628 */
629 u8 irq;
630 pci_read_config_byte(d, 0x42, &irq);
631 irq &= 0xf;
632 if (irq && (irq != 2))
633 d->irq = irq;
634}
635DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
636DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
637
93cffffa
BH		 638/*
639 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
640 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
641 * when written, it makes an internal connection to the PIC.
642 * For these devices, this register is defined to be 4 bits wide.
643 * Normally this is fine. However for IO-APIC motherboards, or
644 * non-x86 architectures (yes Via exists on PPC among other places),
645 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
646 * interrupts delivered properly.
a7b862f6
CW		 647 *
648 * Some of the on-chip devices are actually '586 devices' so they are
649 * listed here.
93cffffa
BH		 650 */
651static void quirk_via_irq(struct pci_dev *dev)
25be5e6c
LB		 652{
653 u8 irq, new_irq;
654
25be5e6c
LB		 655 new_irq = dev->irq & 0xf;
656 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
657 if (new_irq != irq) {
75cf7456 658 printk(KERN_INFO "PCI: VIA IRQ fixup for %s, from %d to %d\n",
25be5e6c
LB		 659 pci_name(dev), irq, new_irq);
660 udelay(15); /* unknown if delay really needed */
661 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
662 }
663}
a7b862f6
CW		 664DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_via_irq);
665DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, quirk_via_irq);
666DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, quirk_via_irq);
667DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_irq);
1ae4f9ba 668DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, quirk_via_irq);
75cf7456
CW		 669DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_irq);
670DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_irq);
671DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irq);
25be5e6c 672
1da177e4
LT		 673/*
674 * VIA VT82C598 has its device ID settable and many BIOSes
675 * set it to the ID of VT82C597 for backward compatibility.
676 * We need to switch it off to be able to recognize the real
677 * type of the chip.
678 */
679static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
680{
681 pci_write_config_byte(dev, 0xfc, 0);
682 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
683}
684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
685
709cf5ea
MG		 686#ifdef CONFIG_ACPI_SLEEP
687
688/*
689 * Some VIA systems boot with the abnormal status flag set. This can cause
690 * the BIOS to re-POST the system on resume rather than passing control
691 * back to the OS. Clear the flag on boot
692 */
693static void __devinit quirk_via_abnormal_poweroff(struct pci_dev *dev)
694{
695 u32 reg;
696
697 acpi_hw_register_read(ACPI_MTX_DO_NOT_LOCK, ACPI_REGISTER_PM1_STATUS,
698 &reg);
699
700 if (reg & 0x800) {
701 printk("Clearing abnormal poweroff flag\n");
702 acpi_hw_register_write(ACPI_MTX_DO_NOT_LOCK,
703 ACPI_REGISTER_PM1_STATUS,
704 (u16)0x800);
705 }
706}
707
708DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_abnormal_poweroff);
709DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_abnormal_poweroff);
710
711#endif
712
1da177e4
LT		 713/*
714 * CardBus controllers have a legacy base address that enables them
715 * to respond as i82365 pcmcia controllers. We don't want them to
716 * do this even if the Linux CardBus driver is not loaded, because
717 * the Linux i82365 driver does not (and should not) handle CardBus.
718 */
719static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
720{
721 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
722 return;
723 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
724}
725DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
726
727/*
728 * Following the PCI ordering rules is optional on the AMD762. I'm not
729 * sure what the designers were smoking but let's not inhale...
730 *
731 * To be fair to AMD, it follows the spec by default, its BIOS people
732 * who turn it off!
733 */
734static void __devinit quirk_amd_ordering(struct pci_dev *dev)
735{
736 u32 pcic;
737 pci_read_config_dword(dev, 0x4C, &pcic);
738 if ((pcic&6)!=6) {
739 pcic |= 6;
740 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
741 pci_write_config_dword(dev, 0x4C, pcic);
742 pci_read_config_dword(dev, 0x84, &pcic);
743 pcic |= (1<<23); /* Required in this mode */
744 pci_write_config_dword(dev, 0x84, pcic);
745 }
746}
747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
748
749/*
750 * DreamWorks provided workaround for Dunord I-3000 problem
751 *
752 * This card decodes and responds to addresses not apparently
753 * assigned to it. We force a larger allocation to ensure that
754 * nothing gets put too close to it.
755 */
756static void __devinit quirk_dunord ( struct pci_dev * dev )
757{
758 struct resource *r = &dev->resource [1];
759 r->start = 0;
760 r->end = 0xffffff;
761}
762DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
763
764/*
765 * i82380FB mobile docking controller: its PCI-to-PCI bridge
766 * is subtractive decoding (transparent), and does indicate this
767 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
768 * instead of 0x01.
769 */
770static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
771{
772 dev->transparent = 1;
773}
774DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
775DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
776
777/*
778 * Common misconfiguration of the MediaGX/Geode PCI master that will
779 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
780 * datasheets found at http://www.national.com/ds/GX for info on what
781 * these bits do. <christer@weinigel.se>
782 */
783static void __init quirk_mediagx_master(struct pci_dev *dev)
784{
785 u8 reg;
786 pci_read_config_byte(dev, 0x41, &reg);
787 if (reg & 2) {
788 reg &= ~2;
789 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
790 pci_write_config_byte(dev, 0x41, reg);
791 }
792}
793DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
794
795/*
796 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
797 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
798 * secondary channels respectively). If the device reports Compatible mode
799 * but does use BAR0-3 for address decoding, we assume that firmware has
800 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
801 * Exceptions (if they exist) must be handled in chip/architecture specific
802 * fixups.
803 *
804 * Note: for non x86 people. You may need an arch specific quirk to handle
805 * moving IDE devices to native mode as well. Some plug in card devices power
806 * up in compatible mode and assume the BIOS will adjust them.
807 *
808 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
809 * we do now ? We don't want is pci_enable_device to come along
810 * and assign new resources. Both approaches work for that.
811 */
812static void __devinit quirk_ide_bases(struct pci_dev *dev)
813{
814 struct resource *res;
815 int first_bar = 2, last_bar = 0;
816
817 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
818 return;
819
820 res = &dev->resource[0];
821
822 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
823 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
824 res[0].start = res[0].end = res[0].flags = 0;
825 res[1].start = res[1].end = res[1].flags = 0;
826 first_bar = 0;
827 last_bar = 1;
828 }
829
830 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
831 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
832 res[2].start = res[2].end = res[2].flags = 0;
833 res[3].start = res[3].end = res[3].flags = 0;
834 last_bar = 3;
835 }
836
837 if (!last_bar)
838 return;
839
840 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
841 first_bar, last_bar, pci_name(dev));
842}
843DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
844
845/*
846 * Ensure C0 rev restreaming is off. This is normally done by
847 * the BIOS but in the odd case it is not the results are corruption
848 * hence the presence of a Linux check
849 */
850static void __init quirk_disable_pxb(struct pci_dev *pdev)
851{
852 u16 config;
853 u8 rev;
854
855 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
856 if (rev != 0x04) /* Only C0 requires this */
857 return;
858 pci_read_config_word(pdev, 0x40, &config);
859 if (config & (1<<6)) {
860 config &= ~(1<<6);
861 pci_write_config_word(pdev, 0x40, config);
862 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
863 }
864}
865DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
866
1da177e4
LT		 867
868/*
869 * Serverworks CSB5 IDE does not fully support native mode
870 */
871static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
872{
873 u8 prog;
874 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
875 if (prog & 5) {
876 prog &= ~5;
877 pdev->class &= ~5;
878 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
879 /* need to re-assign BARs for compat mode */
880 quirk_ide_bases(pdev);
881 }
882}
883DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
884
885/*
886 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
887 */
888static void __init quirk_ide_samemode(struct pci_dev *pdev)
889{
890 u8 prog;
891
892 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
893
894 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
895 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
896 prog &= ~5;
897 pdev->class &= ~5;
898 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
899 /* need to re-assign BARs for compat mode */
900 quirk_ide_bases(pdev);
901 }
902}
903DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
904
905/* This was originally an Alpha specific thing, but it really fits here.
906 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
907 */
908static void __init quirk_eisa_bridge(struct pci_dev *dev)
909{
910 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
911}
912DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
913
7daa0c4f
JG		 914/*
915 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled
916 * when a PCI-Soundcard is added. The BIOS only gives Options
917 * "Disabled" and "AUTO". This Quirk Sets the corresponding
918 * Register-Value to enable the Soundcard.
bd91fde9
CW		 919 *
920 * FIXME: Presently this quirk will run on anything that has an 8237
921 * which isn't correct, we need to check DMI tables or something in
922 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it
923 * runs everywhere at present we suppress the printk output in most
924 * irrelevant cases.
7daa0c4f
JG		 925 */
926static void __init k8t_sound_hostbridge(struct pci_dev *dev)
927{
928 unsigned char val;
929
7daa0c4f
JG		 930 pci_read_config_byte(dev, 0x50, &val);
931 if (val == 0x88 || val == 0xc8) {
bd91fde9
CW		 932 /* Assume it's probably a MSI-K8T-Neo2Fir */
933 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n");
7daa0c4f
JG		 934 pci_write_config_byte(dev, 0x50, val & (~0x40));
935
936 /* Verify the Change for Status output */
937 pci_read_config_byte(dev, 0x50, &val);
938 if (val & 0x40)
bd91fde9 939 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n");
7daa0c4f 940 else
bd91fde9 941 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n");
7daa0c4f 942 }
7daa0c4f
JG		 943}
944DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);
945
ce007ea5 946#ifndef CONFIG_ACPI_SLEEP
1da177e4
LT		 947/*
948 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
949 * is not activated. The myth is that Asus said that they do not want the
950 * users to be irritated by just another PCI Device in the Win98 device
951 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
952 * package 2.7.0 for details)
953 *
954 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
955 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
956 * becomes necessary to do this tweak in two steps -- I've chosen the Host
957 * bridge as trigger.
ce007ea5
CDH		 958 *
959 * Actually, leaving it unhidden and not redoing the quirk over suspend2ram
960 * will cause thermal management to break down, and causing machine to
961 * overheat.
1da177e4 962 */
ce007ea5 963static int __initdata asus_hides_smbus;
1da177e4
LT		 964
965static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
966{
967 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
968 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
969 switch(dev->subsystem_device) {
a00db371 970 case 0x8025: /* P4B-LX */
1da177e4
LT		 971 case 0x8070: /* P4B */
972 case 0x8088: /* P4B533 */
973 case 0x1626: /* L3C notebook */
974 asus_hides_smbus = 1;
975 }
976 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
977 switch(dev->subsystem_device) {
978 case 0x80b1: /* P4GE-V */
979 case 0x80b2: /* P4PE */
980 case 0x8093: /* P4B533-V */
981 asus_hides_smbus = 1;
982 }
983 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
984 switch(dev->subsystem_device) {
985 case 0x8030: /* P4T533 */
986 asus_hides_smbus = 1;
987 }
988 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
989 switch (dev->subsystem_device) {
990 case 0x8070: /* P4G8X Deluxe */
991 asus_hides_smbus = 1;
992 }
321311af
JD		 993 if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
994 switch (dev->subsystem_device) {
995 case 0x80c9: /* PU-DLS */
996 asus_hides_smbus = 1;
997 }
1da177e4
LT		 998 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
999 switch (dev->subsystem_device) {
1000 case 0x1751: /* M2N notebook */
1001 case 0x1821: /* M5N notebook */
1002 asus_hides_smbus = 1;
1003 }
1004 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1005 switch (dev->subsystem_device) {
1006 case 0x184b: /* W1N notebook */
1007 case 0x186a: /* M6Ne notebook */
1008 asus_hides_smbus = 1;
1009 }
acc06632
RM		 1010 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1011 switch (dev->subsystem_device) {
1012 case 0x1882: /* M6V notebook */
2d1e1c75 1013 case 0x1977: /* A6VA notebook */
acc06632
RM		 1014 asus_hides_smbus = 1;
1015 }
1016 }
1da177e4
LT		 1017 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1018 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1019 switch(dev->subsystem_device) {
1020 case 0x088C: /* HP Compaq nc8000 */
1021 case 0x0890: /* HP Compaq nc6000 */
1022 asus_hides_smbus = 1;
1023 }
1024 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1025 switch (dev->subsystem_device) {
1026 case 0x12bc: /* HP D330L */
e3b1bd57 1027 case 0x12bd: /* HP D530 */
1da177e4
LT		 1028 asus_hides_smbus = 1;
1029 }
3c0a654e 1030 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1031 switch (dev->subsystem_device) {
1032 case 0x099c: /* HP Compaq nx6110 */
1033 asus_hides_smbus = 1;
1034 }
1035 }
1da177e4
LT		 1036 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
1037 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1038 switch(dev->subsystem_device) {
1039 case 0x0001: /* Toshiba Satellite A40 */
1040 asus_hides_smbus = 1;
1041 }
e96e2f14
DG		 1042 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1043 switch(dev->subsystem_device) {
1044 case 0x0001: /* Toshiba Tecra M2 */
1045 asus_hides_smbus = 1;
1046 }
1da177e4
LT		 1047 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1048 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1049 switch(dev->subsystem_device) {
1050 case 0xC00C: /* Samsung P35 notebook */
1051 asus_hides_smbus = 1;
1052 }
c87f883e
RIZ		 1053 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1054 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1055 switch(dev->subsystem_device) {
1056 case 0x0058: /* Compaq Evo N620c */
1057 asus_hides_smbus = 1;
1058 }
1da177e4
LT		 1059 }
1060}
1061DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
1062DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
1063DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
1064DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
1065DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
321311af 1066DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge );
1da177e4
LT		 1067DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
1068DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
acc06632 1069DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
1da177e4
LT		 1070
1071static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
1072{
1073 u16 val;
1074
1075 if (likely(!asus_hides_smbus))
1076 return;
1077
1078 pci_read_config_word(dev, 0xF2, &val);
1079 if (val & 0x8) {
1080 pci_write_config_word(dev, 0xF2, val & (~0x8));
1081 pci_read_config_word(dev, 0xF2, &val);
1082 if (val & 0x8)
1083 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1084 else
1085 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
1086 }
1087}
1088DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1089DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
321311af 1090DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc );
1da177e4
LT		 1091DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1092DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1093DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
1094
acc06632
RM		 1095static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1096{
1097 u32 val, rcba;
1098 void __iomem *base;
1099
1100 if (likely(!asus_hides_smbus))
1101 return;
1102 pci_read_config_dword(dev, 0xF0, &rcba);
1103 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1104 if (base == NULL) return;
1105 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1106 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1107 iounmap(base);
1108 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1109}
1110DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1111
ce007ea5
CDH		 1112#endif
1113
1da177e4
LT		 1114/*
1115 * SiS 96x south bridge: BIOS typically hides SMBus device...
1116 */
1117static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
1118{
1119 u8 val = 0;
1120 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
1121 pci_read_config_byte(dev, 0x77, &val);
1122 pci_write_config_byte(dev, 0x77, val & ~0x10);
1123 pci_read_config_byte(dev, 0x77, &val);
1124}
1125
1da177e4
LT		 1126/*
1127 * ... This is further complicated by the fact that some SiS96x south
1128 * bridges pretend to be 85C503/5513 instead. In that case see if we
1129 * spotted a compatible north bridge to make sure.
1130 * (pci_find_device doesn't work yet)
1131 *
1132 * We can also enable the sis96x bit in the discovery register..
1133 */
1134static int __devinitdata sis_96x_compatible = 0;
1135
1136#define SIS_DETECT_REGISTER 0x40
1137
1138static void __init quirk_sis_503(struct pci_dev *dev)
1139{
1140 u8 reg;
1141 u16 devid;
1142
1143 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1144 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1145 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1146 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1147 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1148 return;
1149 }
1150
1151 /* Make people aware that we changed the config.. */
1152 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1153
1154 /*
1155 * Ok, it now shows up as a 96x.. The 96x quirks are after
1156 * the 503 quirk in the quirk table, so they'll automatically
1157 * run and enable things like the SMBus device
1158 */
1159 dev->device = devid;
1160}
1161
1162static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1163{
1164 sis_96x_compatible = 1;
1165}
1166DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1167DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1168DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1169DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1170DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1171DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1172
1173DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
e5548e96
BJD		 1174/*
1175 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1176 * and MC97 modem controller are disabled when a second PCI soundcard is
1177 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1178 * -- bjd
1179 */
1180static void __init asus_hides_ac97_lpc(struct pci_dev *dev)
1181{
1182 u8 val;
1183 int asus_hides_ac97 = 0;
1184
1185 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1186 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1187 asus_hides_ac97 = 1;
1188 }
1189
1190 if (!asus_hides_ac97)
1191 return;
1192
1193 pci_read_config_byte(dev, 0x50, &val);
1194 if (val & 0xc0) {
1195 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1196 pci_read_config_byte(dev, 0x50, &val);
1197 if (val & 0xc0)
1198 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1199 else
1200 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n");
1201 }
1202}
1203DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1204
1da177e4
LT		 1205
1206DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1207DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1208DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1209DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1210
77967052 1211#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1212
1213/*
1214 * If we are using libata we can drive this chip properly but must
1215 * do this early on to make the additional device appear during
1216 * the PCI scanning.
1217 */
1218
1219static void __devinit quirk_jmicron_dualfn(struct pci_dev *pdev)
1220{
1221 u32 conf;
1222 u8 hdr;
1223
1224 /* Only poke fn 0 */
1225 if (PCI_FUNC(pdev->devfn))
1226 return;
1227
1228 switch(pdev->device) {
1229 case PCI_DEVICE_ID_JMICRON_JMB365:
1230 case PCI_DEVICE_ID_JMICRON_JMB366:
1231 /* Redirect IDE second PATA port to the right spot */
1232 pci_read_config_dword(pdev, 0x80, &conf);
1233 conf |= (1 << 24);
1234 /* Fall through */
1235 pci_write_config_dword(pdev, 0x80, conf);
1236 case PCI_DEVICE_ID_JMICRON_JMB361:
1237 case PCI_DEVICE_ID_JMICRON_JMB363:
1238 pci_read_config_dword(pdev, 0x40, &conf);
1239 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1240 /* Set the class codes correctly and then direct IDE 0 */
1241 conf &= ~0x000F0200; /* Clear bit 9 and 16-19 */
1242 conf |= 0x00C20002; /* Set bit 1, 17, 22, 23 */
1243 pci_write_config_dword(pdev, 0x40, conf);
1244
1245 /* Reconfigure so that the PCI scanner discovers the
1246 device is now multifunction */
1247
1248 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1249 pdev->hdr_type = hdr & 0x7f;
1250 pdev->multifunction = !!(hdr & 0x80);
1251
1252 break;
1253 }
1254}
1255
1256DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn);
1257
1258#endif
1259
1da177e4
LT		 1260#ifdef CONFIG_X86_IO_APIC
1261static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1262{
1263 int i;
1264
1265 if ((pdev->class >> 8) != 0xff00)
1266 return;
1267
1268 /* the first BAR is the location of the IO APIC...we must
1269 * not touch this (and it's already covered by the fixmap), so
1270 * forcibly insert it into the resource tree */
1271 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1272 insert_resource(&iomem_resource, &pdev->resource[0]);
1273
1274 /* The next five BARs all seem to be rubbish, so just clean
1275 * them out */
1276 for (i=1; i < 6; i++) {
1277 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1278 }
1279
1280}
1281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1282#endif
1283
2bd0fa3b
JB		 1284enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 };
1285/* Defaults to combined */
1286static enum ide_combined_type combined_mode;
1287
1288static int __init combined_setup(char *str)
1289{
1290 if (!strncmp(str, "ide", 3))
1291 combined_mode = IDE;
1292 else if (!strncmp(str, "libata", 6))
1293 combined_mode = LIBATA;
1294 else /* "combined" or anything else defaults to old behavior */
1295 combined_mode = COMBINED;
1296
1297 return 1;
1298}
1299__setup("combined_mode=", combined_setup);
1300
77967052 1301#ifdef CONFIG_SATA_INTEL_COMBINED
1da177e4
LT		 1302static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1303{
1304 u8 prog, comb, tmp;
1305 int ich = 0;
1306
1307 /*
1308 * Narrow down to Intel SATA PCI devices.
1309 */
1310 switch (pdev->device) {
1311 /* PCI ids taken from drivers/scsi/ata_piix.c */
1312 case 0x24d1:
1313 case 0x24df:
1314 case 0x25a3:
1315 case 0x25b0:
1316 ich = 5;
1317 break;
1318 case 0x2651:
1319 case 0x2652:
1320 case 0x2653:
c368ca4e 1321 case 0x2680: /* ESB2 */
1da177e4
LT		 1322 ich = 6;
1323 break;
1324 case 0x27c0:
1325 case 0x27c4:
1326 ich = 7;
1327 break;
012b265f
JG		 1328 case 0x2828: /* ICH8M */
1329 ich = 8;
1330 break;
1da177e4
LT		 1331 default:
1332 /* we do not handle this PCI device */
1333 return;
1334 }
1335
1336 /*
1337 * Read combined mode register.
1338 */
1339 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1340
1341 if (ich == 5) {
1342 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1343 if (tmp == 0x4) /* bits 10x */
1344 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1345 else if (tmp == 0x6) /* bits 11x */
1346 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1347 else
1348 return; /* not in combined mode */
1349 } else {
012b265f 1350 WARN_ON((ich != 6) && (ich != 7) && (ich != 8));
1da177e4
LT		 1351 tmp &= 0x3; /* interesting bits 1:0 */
1352 if (tmp & (1 << 0))
1353 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1354 else if (tmp & (1 << 1))
1355 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1356 else
1357 return; /* not in combined mode */
1358 }
1359
1360 /*
1361 * Read programming interface register.
1362 * (Tells us if it's legacy or native mode)
1363 */
1364 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1365
1366 /* if SATA port is in native mode, we're ok. */
1367 if (prog & comb)
1368 return;
1369
2bd0fa3b
JB		 1370 /* Don't reserve any so the IDE driver can get them (but only if
1371 * combined_mode=ide).
1372 */
1373 if (combined_mode == IDE)
1374 return;
1375
1376 /* Grab them both for libata if combined_mode=libata. */
1377 if (combined_mode == LIBATA) {
1378 request_region(0x1f0, 8, "libata"); /* port 0 */
1379 request_region(0x170, 8, "libata"); /* port 1 */
1380 return;
1381 }
1382
1da177e4
LT		 1383 /* SATA port is in legacy mode. Reserve port so that
1384 * IDE driver does not attempt to use it. If request_region
1385 * fails, it will be obvious at boot time, so we don't bother
1386 * checking return values.
1387 */
1388 if (comb == (1 << 0))
1389 request_region(0x1f0, 8, "libata"); /* port 0 */
1390 else
1391 request_region(0x170, 8, "libata"); /* port 1 */
1392}
1393DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
77967052 1394#endif /* CONFIG_SATA_INTEL_COMBINED */
1da177e4
LT		 1395
1396
1397int pcie_mch_quirk;
1398
1399static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1400{
1401 pcie_mch_quirk = 1;
1402}
1403DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1404DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1405DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1406
4602b88d
KA		 1407
1408/*
1409 * It's possible for the MSI to get corrupted if shpc and acpi
1410 * are used together on certain PXH-based systems.
1411 */
1412static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1413{
1414 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
1415 PCI_CAP_ID_MSI);
1416 dev->no_msi = 1;
1417
1418 printk(KERN_WARNING "PCI: PXH quirk detected, "
1419 "disabling MSI for SHPC device\n");
1420}
1421DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1422DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1423DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1424DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1425DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1426
ffadcc2f
KCA		 1427/*
1428 * Some Intel PCI Express chipsets have trouble with downstream
1429 * device power management.
1430 */
1431static void quirk_intel_pcie_pm(struct pci_dev * dev)
1432{
1433 pci_pm_d3_delay = 120;
1434 dev->no_d1d2 = 1;
1435}
1436
1437DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1438DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1439DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1440DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1441DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1442DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1443DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1444DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1445DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1446DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1447DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1448DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1449DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1450DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1451DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1452DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1453DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1454DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1455DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1456DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1457DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1458
c408a379
KA		 1459/*
1460 * Fixup the cardbus bridges on the IBM Dock II docking station
1461 */
1462static void __devinit quirk_ibm_dock2_cardbus(struct pci_dev *dev)
1463{
1464 u32 val;
1465
1466 /*
1467 * tie the 2 interrupt pins to INTA, and configure the
1468 * multifunction routing register to handle this.
1469 */
1470 if ((dev->subsystem_vendor == PCI_VENDOR_ID_IBM) &&
1471 (dev->subsystem_device == 0x0148)) {
1472 printk(KERN_INFO "PCI: Found IBM Dock II Cardbus Bridge "
1473 "applying quirk\n");
1474 pci_read_config_dword(dev, 0x8c, &val);
1475 val = ((val & 0xffffff00) | 0x1002);
1476 pci_write_config_dword(dev, 0x8c, val);
1477 pci_read_config_dword(dev, 0x80, &val);
1478 val = ((val & 0x00ffff00) | 0x2864c077);
1479 pci_write_config_dword(dev, 0x80, val);
1480 }
1481}
1482
1483DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420,
1484 quirk_ibm_dock2_cardbus);
1485
1da177e4
LT		 1486static void __devinit quirk_netmos(struct pci_dev *dev)
1487{
1488 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1489 unsigned int num_serial = dev->subsystem_device & 0xf;
1490
1491 /*
1492 * These Netmos parts are multiport serial devices with optional
1493 * parallel ports. Even when parallel ports are present, they
1494 * are identified as class SERIAL, which means the serial driver
1495 * will claim them. To prevent this, mark them as class OTHER.
1496 * These combo devices should be claimed by parport_serial.
1497 *
1498 * The subdevice ID is of the form 0x00PS, where <P> is the number
1499 * of parallel ports and <S> is the number of serial ports.
1500 */
1501 switch (dev->device) {
1502 case PCI_DEVICE_ID_NETMOS_9735:
1503 case PCI_DEVICE_ID_NETMOS_9745:
1504 case PCI_DEVICE_ID_NETMOS_9835:
1505 case PCI_DEVICE_ID_NETMOS_9845:
1506 case PCI_DEVICE_ID_NETMOS_9855:
1507 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1508 num_parallel) {
1509 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1510 "%u serial); changing class SERIAL to OTHER "
1511 "(use parport_serial)\n",
1512 dev->device, num_parallel, num_serial);
1513 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1514 (dev->class & 0xff);
1515 }
1516 }
1517}
1518DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1519
16a74744
BH		 1520static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1521{
1522 u16 command;
1523 u32 bar;
1524 u8 __iomem *csr;
1525 u8 cmd_hi;
1526
1527 switch (dev->device) {
1528 /* PCI IDs taken from drivers/net/e100.c */
1529 case 0x1029:
1530 case 0x1030 ... 0x1034:
1531 case 0x1038 ... 0x103E:
1532 case 0x1050 ... 0x1057:
1533 case 0x1059:
1534 case 0x1064 ... 0x106B:
1535 case 0x1091 ... 0x1095:
1536 case 0x1209:
1537 case 0x1229:
1538 case 0x2449:
1539 case 0x2459:
1540 case 0x245D:
1541 case 0x27DC:
1542 break;
1543 default:
1544 return;
1545 }
1546
1547 /*
1548 * Some firmware hands off the e100 with interrupts enabled,
1549 * which can cause a flood of interrupts if packets are
1550 * received before the driver attaches to the device. So
1551 * disable all e100 interrupts here. The driver will
1552 * re-enable them when it's ready.
1553 */
1554 pci_read_config_word(dev, PCI_COMMAND, &command);
1555 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar);
1556
1557 if (!(command & PCI_COMMAND_MEMORY) || !bar)
1558 return;
1559
1560 csr = ioremap(bar, 8);
1561 if (!csr) {
1562 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n",
1563 pci_name(dev));
1564 return;
1565 }
1566
1567 cmd_hi = readb(csr + 3);
1568 if (cmd_hi == 0) {
1569 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts "
1570 "enabled, disabling\n", pci_name(dev));
1571 writeb(1, csr + 3);
1572 }
1573
1574 iounmap(csr);
1575}
1576DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
a5312e28
IK		 1577
1578static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1579{
1580 /* rev 1 ncr53c810 chips don't set the class at all which means
1581 * they don't get their resources remapped. Fix that here.
1582 */
1583
1584 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1585 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n");
1586 dev->class = PCI_CLASS_STORAGE_SCSI;
1587 }
1588}
1589DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1590
1591
1da177e4
LT		 1592static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1593{
1594 while (f < end) {
1595 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1596 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1597 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1598 f->hook(dev);
1599 }
1600 f++;
1601 }
1602}
1603
1604extern struct pci_fixup __start_pci_fixups_early[];
1605extern struct pci_fixup __end_pci_fixups_early[];
1606extern struct pci_fixup __start_pci_fixups_header[];
1607extern struct pci_fixup __end_pci_fixups_header[];
1608extern struct pci_fixup __start_pci_fixups_final[];
1609extern struct pci_fixup __end_pci_fixups_final[];
1610extern struct pci_fixup __start_pci_fixups_enable[];
1611extern struct pci_fixup __end_pci_fixups_enable[];
1612
1613
1614void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1615{
1616 struct pci_fixup *start, *end;
1617
1618 switch(pass) {
1619 case pci_fixup_early:
1620 start = __start_pci_fixups_early;
1621 end = __end_pci_fixups_early;
1622 break;
1623
1624 case pci_fixup_header:
1625 start = __start_pci_fixups_header;
1626 end = __end_pci_fixups_header;
1627 break;
1628
1629 case pci_fixup_final:
1630 start = __start_pci_fixups_final;
1631 end = __end_pci_fixups_final;
1632 break;
1633
1634 case pci_fixup_enable:
1635 start = __start_pci_fixups_enable;
1636 end = __end_pci_fixups_enable;
1637 break;
1638
1639 default:
1640 /* stupid compiler warning, you would think with an enum... */
1641 return;
1642 }
1643 pci_do_fixups(dev, start, end);
1644}
1645
9d265124
DY		 1646/* Enable 1k I/O space granularity on the Intel P64H2 */
1647static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1648{
1649 u16 en1k;
1650 u8 io_base_lo, io_limit_lo;
1651 unsigned long base, limit;
1652 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1653
1654 pci_read_config_word(dev, 0x40, &en1k);
1655
1656 if (en1k & 0x200) {
1657 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n");
1658
1659 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1660 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1661 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1662 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1663
1664 if (base <= limit) {
1665 res->start = base;
1666 res->end = limit + 0x3ff;
1667 }
1668 }
1669}
1670DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1671
cf34a8e0
BG		 1672/* Under some circumstances, AER is not linked with extended capabilities.
1673 * Force it to be linked by setting the corresponding control bit in the
1674 * config space.
1675 */
1676static void __devinit quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1677{
1678 uint8_t b;
1679 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1680 if (!(b & 0x20)) {
1681 pci_write_config_byte(dev, 0xf41, b | 0x20);
1682 printk(KERN_INFO
1683 "PCI: Linking AER extended capability on %s\n",
1684 pci_name(dev));
1685 }
1686 }
1687}
1688DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1689 quirk_nvidia_ck804_pcie_aer_ext_cap);
1690
3f79e107
BG		 1691#ifdef CONFIG_PCI_MSI
1692/* To disable MSI globally */
1693int pci_msi_quirk;
1694
1695/* The Serverworks PCI-X chipset does not support MSI. We cannot easily rely
1696 * on setting PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1697 * some other busses controlled by the chipset even if Linux is not aware of it.
1698 * Instead of setting the flag on all busses in the machine, simply disable MSI
1699 * globally.
1700 */
1701static void __init quirk_svw_msi(struct pci_dev *dev)
1702{
1703 pci_msi_quirk = 1;
1704 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
1705}
1706DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi);
1707
1708/* Disable MSI on chipsets that are known to not support it */
1709static void __devinit quirk_disable_msi(struct pci_dev *dev)
1710{
1711 if (dev->subordinate) {
1712 printk(KERN_WARNING "PCI: MSI quirk detected. "
1713 "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n",
1714 pci_name(dev));
1715 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1716 }
1717}
1718DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
6397c75c
BG		 1719
1720/* Go through the list of Hypertransport capabilities and
1721 * return 1 if a HT MSI capability is found and enabled */
1722static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1723{
1724 u8 pos;
1725 int ttl;
1726 for (pos = pci_find_capability(dev, PCI_CAP_ID_HT), ttl = 48;
1727 pos && ttl;
1728 pos = pci_find_next_capability(dev, pos, PCI_CAP_ID_HT), ttl--) {
1729 u32 cap_hdr;
1730 /* MSI mapping section according to Hypertransport spec */
1731 if (pci_read_config_dword(dev, pos, &cap_hdr) == 0
1732 && (cap_hdr & 0xf8000000) == 0xa8000000 /* MSI mapping */) {
1733 printk(KERN_INFO "PCI: Found HT MSI mapping on %s with capability %s\n",
1734 pci_name(dev), cap_hdr & 0x10000 ? "enabled" : "disabled");
1735 return (cap_hdr & 0x10000) != 0; /* MSI mapping cap enabled */
1736 }
1737 }
1738 return 0;
1739}
1740
1741/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1742static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1743{
1744 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
1745 printk(KERN_WARNING "PCI: MSI quirk detected. "
1746 "MSI disabled on chipset %s.\n",
1747 pci_name(dev));
1748 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1749 }
1750}
1751DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1752 quirk_msi_ht_cap);
1753
1754/* The nVidia CK804 chipset may have 2 HT MSI mappings.
1755 * MSI are supported if the MSI capability set in any of these mappings.
1756 */
1757static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1758{
1759 struct pci_dev *pdev;
1760
1761 if (!dev->subordinate)
1762 return;
1763
1764 /* check HT MSI cap on this chipset and the root one.
1765 * a single one having MSI is enough to be sure that MSI are supported.
1766 */
1767 pdev = pci_find_slot(dev->bus->number, 0);
1768 if (dev->subordinate && !msi_ht_cap_enabled(dev)
1769 && !msi_ht_cap_enabled(pdev)) {
1770 printk(KERN_WARNING "PCI: MSI quirk detected. "
1771 "MSI disabled on chipset %s.\n",
1772 pci_name(dev));
1773 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1774 }
1775}
1776DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1777 quirk_nvidia_ck804_msi_ht_cap);
3f79e107
BG		 1778#endif /* CONFIG_PCI_MSI */
1779
1da177e4
LT		 1780EXPORT_SYMBOL(pcie_mch_quirk);
1781#ifdef CONFIG_HOTPLUG
1782EXPORT_SYMBOL(pci_fixup_device);
1783#endif
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