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PCI: Suspend and resume PCI Express ports with interrupts disabled
[net-next-2.6.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
25be5e6c 23#include <linux/acpi.h>
9f23ed3b 24#include <linux/kallsyms.h>
75e07fc3 25#include <linux/dmi.h>
bc56b9e0 26#include "pci.h"
1da177e4 27
3d137310
TP		 28int isa_dma_bridge_buggy;
29EXPORT_SYMBOL(isa_dma_bridge_buggy);
30int pci_pci_problems;
31EXPORT_SYMBOL(pci_pci_problems);
32int pcie_mch_quirk;
33EXPORT_SYMBOL(pcie_mch_quirk);
34
35#ifdef CONFIG_PCI_QUIRKS
bd8481e1
DT		 36/* The Mellanox Tavor device gives false positive parity errors
37 * Mark this device with a broken_parity_status, to allow
38 * PCI scanning code to "skip" this now blacklisted device.
39 */
40static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
41{
42 dev->broken_parity_status = 1; /* This device gives false positives */
43}
44DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
45DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
46
1da177e4
LT		 47/* Deal with broken BIOS'es that neglect to enable passive release,
48 which can cause problems in combination with the 82441FX/PPro MTRRs */
1597cacb 49static void quirk_passive_release(struct pci_dev *dev)
1da177e4
LT		 50{
51 struct pci_dev *d = NULL;
52 unsigned char dlc;
53
54 /* We have to make sure a particular bit is set in the PIIX3
55 ISA bridge, so we have to go out and find it. */
56 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
57 pci_read_config_byte(d, 0x82, &dlc);
58 if (!(dlc & 1<<1)) {
f0fda801 59 dev_err(&d->dev, "PIIX3: Enabling Passive Release\n");
1da177e4
LT		 60 dlc |= 1<<1;
61 pci_write_config_byte(d, 0x82, dlc);
62 }
63 }
64}
652c538e
AM		 65DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
66DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
1da177e4
LT		 67
68/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
69 but VIA don't answer queries. If you happen to have good contacts at VIA
70 ask them for me please -- Alan
71
72 This appears to be BIOS not version dependent. So presumably there is a
73 chipset level fix */
1da177e4
LT		 74
75static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
76{
77 if (!isa_dma_bridge_buggy) {
78 isa_dma_bridge_buggy=1;
f0fda801 79 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
1da177e4
LT		 80 }
81}
82 /*
83 * Its not totally clear which chipsets are the problematic ones
84 * We know 82C586 and 82C596 variants are affected.
85 */
652c538e
AM		 86DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
87DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
88DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
89DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
90DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
91DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
92DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
1da177e4 93
1da177e4
LT		 94/*
95 * Chipsets where PCI->PCI transfers vanish or hang
96 */
97static void __devinit quirk_nopcipci(struct pci_dev *dev)
98{
99 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
f0fda801 100 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
1da177e4
LT		 101 pci_pci_problems |= PCIPCI_FAIL;
102 }
103}
652c538e
AM		 104DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
105DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
236561e5
AC		 106
107static void __devinit quirk_nopciamd(struct pci_dev *dev)
108{
109 u8 rev;
110 pci_read_config_byte(dev, 0x08, &rev);
111 if (rev == 0x13) {
112 /* Erratum 24 */
f0fda801 113 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
236561e5
AC		 114 pci_pci_problems |= PCIAGP_FAIL;
115 }
116}
652c538e 117DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
1da177e4
LT		 118
119/*
120 * Triton requires workarounds to be used by the drivers
121 */
122static void __devinit quirk_triton(struct pci_dev *dev)
123{
124 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
f0fda801 125 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 126 pci_pci_problems |= PCIPCI_TRITON;
127 }
128}
652c538e
AM		 129DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
130DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
131DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
1da177e4
LT		 133
134/*
135 * VIA Apollo KT133 needs PCI latency patch
136 * Made according to a windows driver based patch by George E. Breese
137 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
138 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
139 * the info on which Mr Breese based his work.
140 *
141 * Updated based on further information from the site and also on
142 * information provided by VIA
143 */
1597cacb 144static void quirk_vialatency(struct pci_dev *dev)
1da177e4
LT		 145{
146 struct pci_dev *p;
1da177e4
LT		 147 u8 busarb;
148 /* Ok we have a potential problem chipset here. Now see if we have
149 a buggy southbridge */
150
151 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
152 if (p!=NULL) {
1da177e4
LT		 153 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
154 /* Check for buggy part revisions */
2b1afa87 155 if (p->revision < 0x40 || p->revision > 0x42)
1da177e4
LT		 156 goto exit;
157 } else {
158 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
159 if (p==NULL) /* No problem parts */
160 goto exit;
1da177e4 161 /* Check for buggy part revisions */
2b1afa87 162 if (p->revision < 0x10 || p->revision > 0x12)
1da177e4
LT		 163 goto exit;
164 }
165
166 /*
167 * Ok we have the problem. Now set the PCI master grant to
168 * occur every master grant. The apparent bug is that under high
169 * PCI load (quite common in Linux of course) you can get data
170 * loss when the CPU is held off the bus for 3 bus master requests
171 * This happens to include the IDE controllers....
172 *
173 * VIA only apply this fix when an SB Live! is present but under
174 * both Linux and Windows this isnt enough, and we have seen
175 * corruption without SB Live! but with things like 3 UDMA IDE
176 * controllers. So we ignore that bit of the VIA recommendation..
177 */
178
179 pci_read_config_byte(dev, 0x76, &busarb);
180 /* Set bit 4 and bi 5 of byte 76 to 0x01
181 "Master priority rotation on every PCI master grant */
182 busarb &= ~(1<<5);
183 busarb |= (1<<4);
184 pci_write_config_byte(dev, 0x76, busarb);
f0fda801 185 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
1da177e4
LT		 186exit:
187 pci_dev_put(p);
188}
652c538e
AM		 189DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
190DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
191DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1597cacb 192/* Must restore this on a resume from RAM */
652c538e
AM		 193DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
194DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
195DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1da177e4
LT		 196
197/*
198 * VIA Apollo VP3 needs ETBF on BT848/878
199 */
200static void __devinit quirk_viaetbf(struct pci_dev *dev)
201{
202 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
f0fda801 203 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 204 pci_pci_problems |= PCIPCI_VIAETBF;
205 }
206}
652c538e 207DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
1da177e4
LT		 208
209static void __devinit quirk_vsfx(struct pci_dev *dev)
210{
211 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
f0fda801 212 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 213 pci_pci_problems |= PCIPCI_VSFX;
214 }
215}
652c538e 216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
1da177e4
LT		 217
218/*
219 * Ali Magik requires workarounds to be used by the drivers
220 * that DMA to AGP space. Latency must be set to 0xA and triton
221 * workaround applied too
222 * [Info kindly provided by ALi]
223 */
224static void __init quirk_alimagik(struct pci_dev *dev)
225{
226 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
f0fda801 227 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 228 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
229 }
230}
652c538e
AM		 231DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
232DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
1da177e4
LT		 233
234/*
235 * Natoma has some interesting boundary conditions with Zoran stuff
236 * at least
237 */
238static void __devinit quirk_natoma(struct pci_dev *dev)
239{
240 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
f0fda801 241 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 242 pci_pci_problems |= PCIPCI_NATOMA;
243 }
244}
652c538e
AM		 245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
247DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
249DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
250DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
1da177e4
LT		 251
252/*
253 * This chip can cause PCI parity errors if config register 0xA0 is read
254 * while DMAs are occurring.
255 */
256static void __devinit quirk_citrine(struct pci_dev *dev)
257{
258 dev->cfg_size = 0xA0;
259}
652c538e 260DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
1da177e4
LT		 261
262/*
263 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
264 * If it's needed, re-allocate the region.
265 */
266static void __devinit quirk_s3_64M(struct pci_dev *dev)
267{
268 struct resource *r = &dev->resource[0];
269
270 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
271 r->start = 0;
272 r->end = 0x3ffffff;
273 }
274}
652c538e
AM		 275DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
1da177e4 277
6693e74a
LT		 278static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
279 unsigned size, int nr, const char *name)
1da177e4
LT		 280{
281 region &= ~(size-1);
282 if (region) {
085ae41f 283 struct pci_bus_region bus_region;
1da177e4
LT		 284 struct resource *res = dev->resource + nr;
285
286 res->name = pci_name(dev);
287 res->start = region;
288 res->end = region + size - 1;
289 res->flags = IORESOURCE_IO;
085ae41f
DM		 290
291 /* Convert from PCI bus to resource space. */
292 bus_region.start = res->start;
293 bus_region.end = res->end;
294 pcibios_bus_to_resource(dev, res, &bus_region);
295
1da177e4 296 pci_claim_resource(dev, nr);
f0fda801 297 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
1da177e4
LT		 298 }
299}
300
301/*
302 * ATI Northbridge setups MCE the processor if you even
303 * read somewhere between 0x3b0->0x3bb or read 0x3d3
304 */
305static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
306{
f0fda801 307 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
1da177e4
LT		 308 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
309 request_region(0x3b0, 0x0C, "RadeonIGP");
310 request_region(0x3d3, 0x01, "RadeonIGP");
311}
652c538e 312DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
1da177e4
LT		 313
314/*
315 * Let's make the southbridge information explicit instead
316 * of having to worry about people probing the ACPI areas,
317 * for example.. (Yes, it happens, and if you read the wrong
318 * ACPI register it will put the machine to sleep with no
319 * way of waking it up again. Bummer).
320 *
321 * ALI M7101: Two IO regions pointed to by words at
322 * 0xE0 (64 bytes of ACPI registers)
323 * 0xE2 (32 bytes of SMB registers)
324 */
325static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
326{
327 u16 region;
328
329 pci_read_config_word(dev, 0xE0, &region);
6693e74a 330 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 331 pci_read_config_word(dev, 0xE2, &region);
6693e74a 332 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4 333}
652c538e 334DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
1da177e4 335
6693e74a
LT		 336static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
337{
338 u32 devres;
339 u32 mask, size, base;
340
341 pci_read_config_dword(dev, port, &devres);
342 if ((devres & enable) != enable)
343 return;
344 mask = (devres >> 16) & 15;
345 base = devres & 0xffff;
346 size = 16;
347 for (;;) {
348 unsigned bit = size >> 1;
349 if ((bit & mask) == bit)
350 break;
351 size = bit;
352 }
353 /*
354 * For now we only print it out. Eventually we'll want to
355 * reserve it (at least if it's in the 0x1000+ range), but
356 * let's get enough confirmation reports first.
357 */
358 base &= -size;
f0fda801 359 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 360}
361
362static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
363{
364 u32 devres;
365 u32 mask, size, base;
366
367 pci_read_config_dword(dev, port, &devres);
368 if ((devres & enable) != enable)
369 return;
370 base = devres & 0xffff0000;
371 mask = (devres & 0x3f) << 16;
372 size = 128 << 16;
373 for (;;) {
374 unsigned bit = size >> 1;
375 if ((bit & mask) == bit)
376 break;
377 size = bit;
378 }
379 /*
380 * For now we only print it out. Eventually we'll want to
381 * reserve it, but let's get enough confirmation reports first.
382 */
383 base &= -size;
f0fda801 384 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 385}
386
1da177e4
LT		 387/*
388 * PIIX4 ACPI: Two IO regions pointed to by longwords at
389 * 0x40 (64 bytes of ACPI registers)
08db2a70 390 * 0x90 (16 bytes of SMB registers)
6693e74a 391 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 392 */
393static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
394{
6693e74a 395 u32 region, res_a;
1da177e4
LT		 396
397 pci_read_config_dword(dev, 0x40, &region);
6693e74a 398 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 399 pci_read_config_dword(dev, 0x90, &region);
08db2a70 400 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 401
402 /* Device resource A has enables for some of the other ones */
403 pci_read_config_dword(dev, 0x5c, &res_a);
404
405 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
406 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
407
408 /* Device resource D is just bitfields for static resources */
409
410 /* Device 12 enabled? */
411 if (res_a & (1 << 29)) {
412 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
413 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
414 }
415 /* Device 13 enabled? */
416 if (res_a & (1 << 30)) {
417 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
418 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
419 }
420 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
421 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4 422}
652c538e
AM		 423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
424DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
1da177e4
LT		 425
426/*
427 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
428 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
429 * 0x58 (64 bytes of GPIO I/O space)
430 */
431static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
432{
433 u32 region;
434
435 pci_read_config_dword(dev, 0x40, &region);
6693e74a 436 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 437
438 pci_read_config_dword(dev, 0x58, &region);
6693e74a 439 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4 440}
652c538e
AM		 441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
448DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
449DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
450DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
1da177e4 451
2cea752f
RM		 452static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
453{
454 u32 region;
455
456 pci_read_config_dword(dev, 0x40, &region);
457 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
458
459 pci_read_config_dword(dev, 0x48, &region);
460 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
461}
652c538e
AM		 462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi);
463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi);
464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi);
465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi);
466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi);
467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi);
468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi);
469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi);
470DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi);
471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi);
472DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi);
473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi);
474DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi);
475DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi);
2cea752f 476
1da177e4
LT		 477/*
478 * VIA ACPI: One IO region pointed to by longword at
479 * 0x48 or 0x20 (256 bytes of ACPI registers)
480 */
481static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
482{
1da177e4
LT		 483 u32 region;
484
651472fb 485 if (dev->revision & 0x10) {
1da177e4
LT		 486 pci_read_config_dword(dev, 0x48, &region);
487 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 488 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 489 }
490}
652c538e 491DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
1da177e4
LT		 492
493/*
494 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
495 * 0x48 (256 bytes of ACPI registers)
496 * 0x70 (128 bytes of hardware monitoring register)
497 * 0x90 (16 bytes of SMB registers)
498 */
499static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
500{
501 u16 hm;
502 u32 smb;
503
504 quirk_vt82c586_acpi(dev);
505
506 pci_read_config_word(dev, 0x70, &hm);
507 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 508 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 509
510 pci_read_config_dword(dev, 0x90, &smb);
511 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 512 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4 513}
652c538e 514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
1da177e4 515
6d85f29b
IK		 516/*
517 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
518 * 0x88 (128 bytes of power management registers)
519 * 0xd0 (16 bytes of SMB registers)
520 */
521static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
522{
523 u16 pm, smb;
524
525 pci_read_config_word(dev, 0x88, &pm);
526 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 527 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 528
529 pci_read_config_word(dev, 0xd0, &smb);
530 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 531 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 532}
533DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
534
1da177e4
LT		 535
536#ifdef CONFIG_X86_IO_APIC
537
538#include <asm/io_apic.h>
539
540/*
541 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
542 * devices to the external APIC.
543 *
544 * TODO: When we have device-specific interrupt routers,
545 * this code will go away from quirks.
546 */
1597cacb 547static void quirk_via_ioapic(struct pci_dev *dev)
1da177e4
LT		 548{
549 u8 tmp;
550
551 if (nr_ioapics < 1)
552 tmp = 0; /* nothing routed to external APIC */
553 else
554 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
555
f0fda801 556 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
1da177e4
LT		 557 tmp == 0 ? "Disa" : "Ena");
558
559 /* Offset 0x58: External APIC IRQ output control */
560 pci_write_config_byte (dev, 0x58, tmp);
561}
652c538e 562DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
e1a2a51e 563DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1da177e4 564
a1740913
KW		 565/*
566 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
567 * This leads to doubled level interrupt rates.
568 * Set this bit to get rid of cycle wastage.
569 * Otherwise uncritical.
570 */
1597cacb 571static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
a1740913
KW		 572{
573 u8 misc_control2;
574#define BYPASS_APIC_DEASSERT 8
575
576 pci_read_config_byte(dev, 0x5B, &misc_control2);
577 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
f0fda801 578 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
a1740913
KW		 579 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
580 }
581}
582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
e1a2a51e 583DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
a1740913 584
1da177e4
LT		 585/*
586 * The AMD io apic can hang the box when an apic irq is masked.
587 * We check all revs >= B0 (yet not in the pre production!) as the bug
588 * is currently marked NoFix
589 *
590 * We have multiple reports of hangs with this chipset that went away with
236561e5 591 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1da177e4
LT		 592 * of course. However the advice is demonstrably good even if so..
593 */
594static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
595{
44c10138 596 if (dev->revision >= 0x02) {
f0fda801 597 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
598 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
1da177e4
LT		 599 }
600}
652c538e 601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1da177e4
LT		 602
603static void __init quirk_ioapic_rmw(struct pci_dev *dev)
604{
605 if (dev->devfn == 0 && dev->bus->number == 0)
606 sis_apic_bug = 1;
607}
652c538e 608DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
1da177e4
LT		 609#endif /* CONFIG_X86_IO_APIC */
610
d556ad4b
PO		 611/*
612 * Some settings of MMRBC can lead to data corruption so block changes.
613 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
614 */
615static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
616{
aa288d4d 617 if (dev->subordinate && dev->revision <= 0x12) {
f0fda801 618 dev_info(&dev->dev, "AMD8131 rev %x detected; "
619 "disabling PCI-X MMRBC\n", dev->revision);
d556ad4b
PO		 620 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
621 }
622}
623DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1da177e4 624
1da177e4
LT		 625/*
626 * FIXME: it is questionable that quirk_via_acpi
627 * is needed. It shows up as an ISA bridge, and does not
628 * support the PCI_INTERRUPT_LINE register at all. Therefore
629 * it seems like setting the pci_dev's 'irq' to the
630 * value of the ACPI SCI interrupt is only done for convenience.
631 * -jgarzik
632 */
633static void __devinit quirk_via_acpi(struct pci_dev *d)
634{
635 /*
636 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
637 */
638 u8 irq;
639 pci_read_config_byte(d, 0x42, &irq);
640 irq &= 0xf;
641 if (irq && (irq != 2))
642 d->irq = irq;
643}
652c538e
AM		 644DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1da177e4 646
09d6029f
DD		 647
648/*
1597cacb 649 * VIA bridges which have VLink
09d6029f 650 */
1597cacb 651
c06bb5d4
JD		 652static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
653
654static void quirk_via_bridge(struct pci_dev *dev)
655{
656 /* See what bridge we have and find the device ranges */
657 switch (dev->device) {
658 case PCI_DEVICE_ID_VIA_82C686:
cb7468ef
JD		 659 /* The VT82C686 is special, it attaches to PCI and can have
660 any device number. All its subdevices are functions of
661 that single device. */
662 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
663 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
c06bb5d4
JD		 664 break;
665 case PCI_DEVICE_ID_VIA_8237:
666 case PCI_DEVICE_ID_VIA_8237A:
667 via_vlink_dev_lo = 15;
668 break;
669 case PCI_DEVICE_ID_VIA_8235:
670 via_vlink_dev_lo = 16;
671 break;
672 case PCI_DEVICE_ID_VIA_8231:
673 case PCI_DEVICE_ID_VIA_8233_0:
674 case PCI_DEVICE_ID_VIA_8233A:
675 case PCI_DEVICE_ID_VIA_8233C_0:
676 via_vlink_dev_lo = 17;
677 break;
678 }
679}
680DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
681DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
682DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
683DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
685DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
686DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
687DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
09d6029f 688
1597cacb
AC		 689/**
690 * quirk_via_vlink - VIA VLink IRQ number update
691 * @dev: PCI device
692 *
693 * If the device we are dealing with is on a PIC IRQ we need to
694 * ensure that the IRQ line register which usually is not relevant
695 * for PCI cards, is actually written so that interrupts get sent
c06bb5d4
JD		 696 * to the right place.
697 * We only do this on systems where a VIA south bridge was detected,
698 * and only for VIA devices on the motherboard (see quirk_via_bridge
699 * above).
1597cacb
AC		 700 */
701
702static void quirk_via_vlink(struct pci_dev *dev)
25be5e6c
LB		 703{
704 u8 irq, new_irq;
705
c06bb5d4
JD		 706 /* Check if we have VLink at all */
707 if (via_vlink_dev_lo == -1)
09d6029f
DD		 708 return;
709
710 new_irq = dev->irq;
711
712 /* Don't quirk interrupts outside the legacy IRQ range */
713 if (!new_irq || new_irq > 15)
714 return;
715
1597cacb 716 /* Internal device ? */
c06bb5d4
JD		 717 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
718 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1597cacb
AC		 719 return;
720
721 /* This is an internal VLink device on a PIC interrupt. The BIOS
722 ought to have set this but may not have, so we redo it */
723
25be5e6c
LB		 724 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
725 if (new_irq != irq) {
f0fda801 726 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
727 irq, new_irq);
25be5e6c
LB		 728 udelay(15); /* unknown if delay really needed */
729 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
730 }
731}
1597cacb 732DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
25be5e6c 733
1da177e4
LT		 734/*
735 * VIA VT82C598 has its device ID settable and many BIOSes
736 * set it to the ID of VT82C597 for backward compatibility.
737 * We need to switch it off to be able to recognize the real
738 * type of the chip.
739 */
740static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
741{
742 pci_write_config_byte(dev, 0xfc, 0);
743 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
744}
652c538e 745DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1da177e4
LT		 746
747/*
748 * CardBus controllers have a legacy base address that enables them
749 * to respond as i82365 pcmcia controllers. We don't want them to
750 * do this even if the Linux CardBus driver is not loaded, because
751 * the Linux i82365 driver does not (and should not) handle CardBus.
752 */
1597cacb 753static void quirk_cardbus_legacy(struct pci_dev *dev)
1da177e4
LT		 754{
755 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
756 return;
757 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
758}
759DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
e1a2a51e 760DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1da177e4
LT		 761
762/*
763 * Following the PCI ordering rules is optional on the AMD762. I'm not
764 * sure what the designers were smoking but let's not inhale...
765 *
766 * To be fair to AMD, it follows the spec by default, its BIOS people
767 * who turn it off!
768 */
1597cacb 769static void quirk_amd_ordering(struct pci_dev *dev)
1da177e4
LT		 770{
771 u32 pcic;
772 pci_read_config_dword(dev, 0x4C, &pcic);
773 if ((pcic&6)!=6) {
774 pcic |= 6;
f0fda801 775 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1da177e4
LT		 776 pci_write_config_dword(dev, 0x4C, pcic);
777 pci_read_config_dword(dev, 0x84, &pcic);
778 pcic |= (1<<23); /* Required in this mode */
779 pci_write_config_dword(dev, 0x84, pcic);
780 }
781}
652c538e 782DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
e1a2a51e 783DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1da177e4
LT		 784
785/*
786 * DreamWorks provided workaround for Dunord I-3000 problem
787 *
788 * This card decodes and responds to addresses not apparently
789 * assigned to it. We force a larger allocation to ensure that
790 * nothing gets put too close to it.
791 */
792static void __devinit quirk_dunord ( struct pci_dev * dev )
793{
794 struct resource *r = &dev->resource [1];
795 r->start = 0;
796 r->end = 0xffffff;
797}
652c538e 798DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1da177e4
LT		 799
800/*
801 * i82380FB mobile docking controller: its PCI-to-PCI bridge
802 * is subtractive decoding (transparent), and does indicate this
803 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
804 * instead of 0x01.
805 */
806static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
807{
808 dev->transparent = 1;
809}
652c538e
AM		 810DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
811DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1da177e4
LT		 812
813/*
814 * Common misconfiguration of the MediaGX/Geode PCI master that will
815 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
816 * datasheets found at http://www.national.com/ds/GX for info on what
817 * these bits do. <christer@weinigel.se>
818 */
1597cacb 819static void quirk_mediagx_master(struct pci_dev *dev)
1da177e4
LT		 820{
821 u8 reg;
822 pci_read_config_byte(dev, 0x41, &reg);
823 if (reg & 2) {
824 reg &= ~2;
f0fda801 825 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1da177e4
LT		 826 pci_write_config_byte(dev, 0x41, reg);
827 }
828}
652c538e
AM		 829DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
830DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1da177e4 831
1da177e4
LT		 832/*
833 * Ensure C0 rev restreaming is off. This is normally done by
834 * the BIOS but in the odd case it is not the results are corruption
835 * hence the presence of a Linux check
836 */
1597cacb 837static void quirk_disable_pxb(struct pci_dev *pdev)
1da177e4
LT		 838{
839 u16 config;
1da177e4 840
44c10138 841 if (pdev->revision != 0x04) /* Only C0 requires this */
1da177e4
LT		 842 return;
843 pci_read_config_word(pdev, 0x40, &config);
844 if (config & (1<<6)) {
845 config &= ~(1<<6);
846 pci_write_config_word(pdev, 0x40, config);
f0fda801 847 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1da177e4
LT		 848 }
849}
652c538e 850DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
e1a2a51e 851DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1da177e4 852
05a7d22b 853static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
ab17443a 854{
05a7d22b
CC		 855 /* set sb600/sb700/sb800 sata to ahci mode */
856 u8 tmp;
ab17443a 857
05a7d22b
CC		 858 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
859 if (tmp == 0x01) {
ab17443a
CH		 860 pci_read_config_byte(pdev, 0x40, &tmp);
861 pci_write_config_byte(pdev, 0x40, tmp|1);
862 pci_write_config_byte(pdev, 0x9, 1);
863 pci_write_config_byte(pdev, 0xa, 6);
864 pci_write_config_byte(pdev, 0x40, tmp);
865
c9f89475 866 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
05a7d22b 867 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
ab17443a
CH		 868 }
869}
05a7d22b 870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
e1a2a51e 871DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
05a7d22b 872DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
e1a2a51e 873DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
ab17443a 874
1da177e4
LT		 875/*
876 * Serverworks CSB5 IDE does not fully support native mode
877 */
878static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
879{
880 u8 prog;
881 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
882 if (prog & 5) {
883 prog &= ~5;
884 pdev->class &= ~5;
885 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
368c73d4 886 /* PCI layer will sort out resources */
1da177e4
LT		 887 }
888}
652c538e 889DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1da177e4
LT		 890
891/*
892 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
893 */
894static void __init quirk_ide_samemode(struct pci_dev *pdev)
895{
896 u8 prog;
897
898 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
899
900 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
f0fda801 901 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1da177e4
LT		 902 prog &= ~5;
903 pdev->class &= ~5;
904 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1da177e4
LT		 905 }
906}
368c73d4 907DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1da177e4 908
979b1791
AC		 909/*
910 * Some ATA devices break if put into D3
911 */
912
913static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
914{
915 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
916 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
917 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
918}
919DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
920DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
921
1da177e4
LT		 922/* This was originally an Alpha specific thing, but it really fits here.
923 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
924 */
925static void __init quirk_eisa_bridge(struct pci_dev *dev)
926{
927 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
928}
652c538e 929DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1da177e4 930
7daa0c4f 931
1da177e4
LT		 932/*
933 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
934 * is not activated. The myth is that Asus said that they do not want the
935 * users to be irritated by just another PCI Device in the Win98 device
936 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
937 * package 2.7.0 for details)
938 *
939 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
940 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
d7698edc 941 * becomes necessary to do this tweak in two steps -- the chosen trigger
942 * is either the Host bridge (preferred) or on-board VGA controller.
9208ee82
JD		 943 *
944 * Note that we used to unhide the SMBus that way on Toshiba laptops
945 * (Satellite A40 and Tecra M2) but then found that the thermal management
946 * was done by SMM code, which could cause unsynchronized concurrent
947 * accesses to the SMBus registers, with potentially bad effects. Thus you
948 * should be very careful when adding new entries: if SMM is accessing the
949 * Intel SMBus, this is a very good reason to leave it hidden.
a99acc83
JD		 950 *
951 * Likewise, many recent laptops use ACPI for thermal management. If the
952 * ACPI DSDT code accesses the SMBus, then Linux should not access it
953 * natively, and keeping the SMBus hidden is the right thing to do. If you
954 * are about to add an entry in the table below, please first disassemble
955 * the DSDT and double-check that there is no code accessing the SMBus.
1da177e4 956 */
9d24a81e 957static int asus_hides_smbus;
1da177e4
LT		 958
959static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
960{
961 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
962 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
963 switch(dev->subsystem_device) {
a00db371 964 case 0x8025: /* P4B-LX */
1da177e4
LT		 965 case 0x8070: /* P4B */
966 case 0x8088: /* P4B533 */
967 case 0x1626: /* L3C notebook */
968 asus_hides_smbus = 1;
969 }
2f2d39d2 970 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1da177e4
LT		 971 switch(dev->subsystem_device) {
972 case 0x80b1: /* P4GE-V */
973 case 0x80b2: /* P4PE */
974 case 0x8093: /* P4B533-V */
975 asus_hides_smbus = 1;
976 }
2f2d39d2 977 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1da177e4
LT		 978 switch(dev->subsystem_device) {
979 case 0x8030: /* P4T533 */
980 asus_hides_smbus = 1;
981 }
2f2d39d2 982 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1da177e4
LT		 983 switch (dev->subsystem_device) {
984 case 0x8070: /* P4G8X Deluxe */
985 asus_hides_smbus = 1;
986 }
2f2d39d2 987 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
321311af
JD		 988 switch (dev->subsystem_device) {
989 case 0x80c9: /* PU-DLS */
990 asus_hides_smbus = 1;
991 }
2f2d39d2 992 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1da177e4
LT		 993 switch (dev->subsystem_device) {
994 case 0x1751: /* M2N notebook */
995 case 0x1821: /* M5N notebook */
996 asus_hides_smbus = 1;
997 }
2f2d39d2 998 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1da177e4
LT		 999 switch (dev->subsystem_device) {
1000 case 0x184b: /* W1N notebook */
1001 case 0x186a: /* M6Ne notebook */
1002 asus_hides_smbus = 1;
1003 }
2f2d39d2 1004 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
2e45785c
JD		 1005 switch (dev->subsystem_device) {
1006 case 0x80f2: /* P4P800-X */
1007 asus_hides_smbus = 1;
1008 }
2f2d39d2 1009 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
acc06632
RM		 1010 switch (dev->subsystem_device) {
1011 case 0x1882: /* M6V notebook */
2d1e1c75 1012 case 0x1977: /* A6VA notebook */
acc06632
RM		 1013 asus_hides_smbus = 1;
1014 }
1da177e4
LT		 1015 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1016 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1017 switch(dev->subsystem_device) {
1018 case 0x088C: /* HP Compaq nc8000 */
1019 case 0x0890: /* HP Compaq nc6000 */
1020 asus_hides_smbus = 1;
1021 }
2f2d39d2 1022 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1da177e4
LT		 1023 switch (dev->subsystem_device) {
1024 case 0x12bc: /* HP D330L */
e3b1bd57 1025 case 0x12bd: /* HP D530 */
1da177e4
LT		 1026 asus_hides_smbus = 1;
1027 }
677cc644
JD		 1028 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1029 switch (dev->subsystem_device) {
1030 case 0x12bf: /* HP xw4100 */
1031 asus_hides_smbus = 1;
1032 }
1da177e4
LT		 1033 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1034 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1035 switch(dev->subsystem_device) {
1036 case 0xC00C: /* Samsung P35 notebook */
1037 asus_hides_smbus = 1;
1038 }
c87f883e
RIZ		 1039 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1040 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1041 switch(dev->subsystem_device) {
1042 case 0x0058: /* Compaq Evo N620c */
1043 asus_hides_smbus = 1;
1044 }
d7698edc 1045 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1046 switch(dev->subsystem_device) {
1047 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1048 /* Motherboard doesn't have Host bridge
1049 * subvendor/subdevice IDs, therefore checking
1050 * its on-board VGA controller */
1051 asus_hides_smbus = 1;
1052 }
10260d9a
JD		 1053 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_IG)
1054 switch(dev->subsystem_device) {
1055 case 0x00b8: /* Compaq Evo D510 CMT */
1056 case 0x00b9: /* Compaq Evo D510 SFF */
1057 asus_hides_smbus = 1;
1058 }
27e46859
KH		 1059 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1060 switch (dev->subsystem_device) {
1061 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1062 /* Motherboard doesn't have host bridge
1063 * subvendor/subdevice IDs, therefore checking
1064 * its on-board VGA controller */
1065 asus_hides_smbus = 1;
1066 }
1da177e4
LT		 1067 }
1068}
652c538e
AM		 1069DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1070DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1071DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1072DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
677cc644 1073DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
652c538e
AM		 1074DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1075DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1076DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1077DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1078DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1079
1080DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
10260d9a 1081DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_IG, asus_hides_smbus_hostbridge);
27e46859 1082DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
d7698edc 1083
1597cacb 1084static void asus_hides_smbus_lpc(struct pci_dev *dev)
1da177e4
LT		 1085{
1086 u16 val;
1087
1088 if (likely(!asus_hides_smbus))
1089 return;
1090
1091 pci_read_config_word(dev, 0xF2, &val);
1092 if (val & 0x8) {
1093 pci_write_config_word(dev, 0xF2, val & (~0x8));
1094 pci_read_config_word(dev, 0xF2, &val);
1095 if (val & 0x8)
f0fda801 1096 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1da177e4 1097 else
f0fda801 1098 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1da177e4
LT		 1099 }
1100}
652c538e
AM		 1101DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1102DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1103DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1104DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1105DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1106DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1107DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
e1a2a51e
RW		 1108DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1109DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1110DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1111DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1112DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1113DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1114DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1597cacb 1115
e1a2a51e
RW		 1116/* It appears we just have one such device. If not, we have a warning */
1117static void __iomem *asus_rcba_base;
1118static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
acc06632 1119{
e1a2a51e 1120 u32 rcba;
acc06632
RM		 1121
1122 if (likely(!asus_hides_smbus))
1123 return;
e1a2a51e
RW		 1124 WARN_ON(asus_rcba_base);
1125
acc06632 1126 pci_read_config_dword(dev, 0xF0, &rcba);
e1a2a51e
RW		 1127 /* use bits 31:14, 16 kB aligned */
1128 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1129 if (asus_rcba_base == NULL)
1130 return;
1131}
1132
1133static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1134{
1135 u32 val;
1136
1137 if (likely(!asus_hides_smbus || !asus_rcba_base))
1138 return;
1139 /* read the Function Disable register, dword mode only */
1140 val = readl(asus_rcba_base + 0x3418);
1141 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1142}
1143
1144static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1145{
1146 if (likely(!asus_hides_smbus || !asus_rcba_base))
1147 return;
1148 iounmap(asus_rcba_base);
1149 asus_rcba_base = NULL;
f0fda801 1150 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
acc06632 1151}
e1a2a51e
RW		 1152
1153static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1154{
1155 asus_hides_smbus_lpc_ich6_suspend(dev);
1156 asus_hides_smbus_lpc_ich6_resume_early(dev);
1157 asus_hides_smbus_lpc_ich6_resume(dev);
1158}
652c538e 1159DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
e1a2a51e
RW		 1160DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1161DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1162DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
ce007ea5 1163
1da177e4
LT		 1164/*
1165 * SiS 96x south bridge: BIOS typically hides SMBus device...
1166 */
1597cacb 1167static void quirk_sis_96x_smbus(struct pci_dev *dev)
1da177e4
LT		 1168{
1169 u8 val = 0;
1da177e4 1170 pci_read_config_byte(dev, 0x77, &val);
2f5c33b3 1171 if (val & 0x10) {
f0fda801 1172 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
2f5c33b3
MH		 1173 pci_write_config_byte(dev, 0x77, val & ~0x10);
1174 }
1da177e4 1175}
652c538e
AM		 1176DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1177DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1178DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1179DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
e1a2a51e
RW		 1180DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1181DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1182DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1183DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1da177e4 1184
1da177e4
LT		 1185/*
1186 * ... This is further complicated by the fact that some SiS96x south
1187 * bridges pretend to be 85C503/5513 instead. In that case see if we
1188 * spotted a compatible north bridge to make sure.
1189 * (pci_find_device doesn't work yet)
1190 *
1191 * We can also enable the sis96x bit in the discovery register..
1192 */
1da177e4
LT		 1193#define SIS_DETECT_REGISTER 0x40
1194
1597cacb 1195static void quirk_sis_503(struct pci_dev *dev)
1da177e4
LT		 1196{
1197 u8 reg;
1198 u16 devid;
1199
1200 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1201 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1202 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1203 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1204 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1205 return;
1206 }
1207
1da177e4 1208 /*
2f5c33b3
MH		 1209 * Ok, it now shows up as a 96x.. run the 96x quirk by
1210 * hand in case it has already been processed.
1211 * (depends on link order, which is apparently not guaranteed)
1da177e4
LT		 1212 */
1213 dev->device = devid;
2f5c33b3 1214 quirk_sis_96x_smbus(dev);
1da177e4 1215}
652c538e 1216DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
e1a2a51e 1217DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1da177e4 1218
1da177e4 1219
e5548e96
BJD		 1220/*
1221 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1222 * and MC97 modem controller are disabled when a second PCI soundcard is
1223 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1224 * -- bjd
1225 */
1597cacb 1226static void asus_hides_ac97_lpc(struct pci_dev *dev)
e5548e96
BJD		 1227{
1228 u8 val;
1229 int asus_hides_ac97 = 0;
1230
1231 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1232 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1233 asus_hides_ac97 = 1;
1234 }
1235
1236 if (!asus_hides_ac97)
1237 return;
1238
1239 pci_read_config_byte(dev, 0x50, &val);
1240 if (val & 0xc0) {
1241 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1242 pci_read_config_byte(dev, 0x50, &val);
1243 if (val & 0xc0)
f0fda801 1244 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
e5548e96 1245 else
f0fda801 1246 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
e5548e96
BJD		 1247 }
1248}
652c538e 1249DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
e1a2a51e 1250DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1597cacb 1251
77967052 1252#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1253
1254/*
1255 * If we are using libata we can drive this chip properly but must
1256 * do this early on to make the additional device appear during
1257 * the PCI scanning.
1258 */
5ee2ae7f 1259static void quirk_jmicron_ata(struct pci_dev *pdev)
15e0c694 1260{
e34bb370 1261 u32 conf1, conf5, class;
15e0c694
AC		 1262 u8 hdr;
1263
1264 /* Only poke fn 0 */
1265 if (PCI_FUNC(pdev->devfn))
1266 return;
1267
5ee2ae7f
TH		 1268 pci_read_config_dword(pdev, 0x40, &conf1);
1269 pci_read_config_dword(pdev, 0x80, &conf5);
15e0c694 1270
5ee2ae7f
TH		 1271 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1272 conf5 &= ~(1 << 24); /* Clear bit 24 */
1273
1274 switch (pdev->device) {
1275 case PCI_DEVICE_ID_JMICRON_JMB360:
1276 /* The controller should be in single function ahci mode */
1277 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1278 break;
1279
1280 case PCI_DEVICE_ID_JMICRON_JMB365:
1281 case PCI_DEVICE_ID_JMICRON_JMB366:
1282 /* Redirect IDE second PATA port to the right spot */
1283 conf5 |= (1 << 24);
1284 /* Fall through */
1285 case PCI_DEVICE_ID_JMICRON_JMB361:
1286 case PCI_DEVICE_ID_JMICRON_JMB363:
1287 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1288 /* Set the class codes correctly and then direct IDE 0 */
3a9e3a51 1289 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
5ee2ae7f
TH		 1290 break;
1291
1292 case PCI_DEVICE_ID_JMICRON_JMB368:
1293 /* The controller should be in single function IDE mode */
1294 conf1 |= 0x00C00000; /* Set 22, 23 */
1295 break;
15e0c694 1296 }
5ee2ae7f
TH		 1297
1298 pci_write_config_dword(pdev, 0x40, conf1);
1299 pci_write_config_dword(pdev, 0x80, conf5);
1300
1301 /* Update pdev accordingly */
1302 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1303 pdev->hdr_type = hdr & 0x7f;
1304 pdev->multifunction = !!(hdr & 0x80);
e34bb370
TH		 1305
1306 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1307 pdev->class = class >> 8;
15e0c694 1308}
5ee2ae7f
TH		 1309DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1310DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1311DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1312DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1313DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1314DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
e1a2a51e
RW		 1315DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1316DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1317DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1318DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1319DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1320DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
15e0c694
AC		 1321
1322#endif
1323
1da177e4
LT		 1324#ifdef CONFIG_X86_IO_APIC
1325static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1326{
1327 int i;
1328
1329 if ((pdev->class >> 8) != 0xff00)
1330 return;
1331
1332 /* the first BAR is the location of the IO APIC...we must
1333 * not touch this (and it's already covered by the fixmap), so
1334 * forcibly insert it into the resource tree */
1335 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1336 insert_resource(&iomem_resource, &pdev->resource[0]);
1337
1338 /* The next five BARs all seem to be rubbish, so just clean
1339 * them out */
1340 for (i=1; i < 6; i++) {
1341 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1342 }
1343
1344}
652c538e 1345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1da177e4
LT		 1346#endif
1347
1da177e4
LT		 1348static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1349{
1350 pcie_mch_quirk = 1;
1351}
652c538e
AM		 1352DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1353DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1354DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1da177e4 1355
4602b88d
KA		 1356
1357/*
1358 * It's possible for the MSI to get corrupted if shpc and acpi
1359 * are used together on certain PXH-based systems.
1360 */
1361static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1362{
f5f2b131 1363 pci_msi_off(dev);
4602b88d 1364 dev->no_msi = 1;
f0fda801 1365 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
4602b88d
KA		 1366}
1367DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1368DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1369DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1370DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1371DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1372
ffadcc2f
KCA		 1373/*
1374 * Some Intel PCI Express chipsets have trouble with downstream
1375 * device power management.
1376 */
1377static void quirk_intel_pcie_pm(struct pci_dev * dev)
1378{
1379 pci_pm_d3_delay = 120;
1380 dev->no_d1d2 = 1;
1381}
1382
1383DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1384DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1385DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1386DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1387DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1388DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1389DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1390DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1391DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1392DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1393DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1394DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1395DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1396DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1397DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1398DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1399DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1400DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1401DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1402DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1403DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1404
426b3b8d 1405#ifdef CONFIG_X86_IO_APIC
e1d3a908
SA		 1406/*
1407 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1408 * remap the original interrupt in the linux kernel to the boot interrupt, so
1409 * that a PCI device's interrupt handler is installed on the boot interrupt
1410 * line instead.
1411 */
1412static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1413{
41b9eb26 1414 if (noioapicquirk || noioapicreroute)
e1d3a908
SA		 1415 return;
1416
1417 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1418
1419 printk(KERN_INFO "PCI quirk: reroute interrupts for 0x%04x:0x%04x\n",
1420 dev->vendor, dev->device);
1421 return;
1422}
88d1dce3
OD		 1423DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1424DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1425DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1426DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1427DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1428DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1429DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1430DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1431DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1432DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1433DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1434DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1435DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1436DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1437DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1438DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
e1d3a908 1439
426b3b8d
SA		 1440/*
1441 * On some chipsets we can disable the generation of legacy INTx boot
1442 * interrupts.
1443 */
1444
1445/*
1446 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1447 * 300641-004US, section 5.7.3.
1448 */
1449#define INTEL_6300_IOAPIC_ABAR 0x40
1450#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1451
1452static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1453{
1454 u16 pci_config_word;
1455
1456 if (noioapicquirk)
1457 return;
1458
1459 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1460 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1461 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1462
1463 printk(KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n",
1464 dev->vendor, dev->device);
1465}
88d1dce3
OD		 1466DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1467DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
77251188
OD		 1468
1469/*
1470 * disable boot interrupts on HT-1000
1471 */
1472#define BC_HT1000_FEATURE_REG 0x64
1473#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1474#define BC_HT1000_MAP_IDX 0xC00
1475#define BC_HT1000_MAP_DATA 0xC01
1476
1477static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1478{
1479 u32 pci_config_dword;
1480 u8 irq;
1481
1482 if (noioapicquirk)
1483 return;
1484
1485 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1486 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1487 BC_HT1000_PIC_REGS_ENABLE);
1488
1489 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1490 outb(irq, BC_HT1000_MAP_IDX);
1491 outb(0x00, BC_HT1000_MAP_DATA);
1492 }
1493
1494 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1495
1496 printk(KERN_INFO "disabled boot interrupts on PCI device"
1497 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1498}
88d1dce3
OD		 1499DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1500DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
542622da
OD		 1501
1502/*
1503 * disable boot interrupts on AMD and ATI chipsets
1504 */
1505/*
1506 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1507 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1508 * (due to an erratum).
1509 */
1510#define AMD_813X_MISC 0x40
1511#define AMD_813X_NOIOAMODE (1<<0)
1512
1513static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1514{
1515 u32 pci_config_dword;
1516
1517 if (noioapicquirk)
1518 return;
1519
1520 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1521 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1522 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1523
1524 printk(KERN_INFO "disabled boot interrupts on PCI device "
1525 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1526}
88d1dce3
OD		 1527DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1528DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
542622da
OD		 1529
1530#define AMD_8111_PCI_IRQ_ROUTING 0x56
1531
1532static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1533{
1534 u16 pci_config_word;
1535
1536 if (noioapicquirk)
1537 return;
1538
1539 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1540 if (!pci_config_word) {
1541 printk(KERN_INFO "boot interrupts on PCI device 0x%04x:0x%04x "
1542 "already disabled\n",
1543 dev->vendor, dev->device);
1544 return;
1545 }
1546 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1547 printk(KERN_INFO "disabled boot interrupts on PCI device "
1548 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1549}
88d1dce3
OD		 1550DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1551DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
426b3b8d
SA		 1552#endif /* CONFIG_X86_IO_APIC */
1553
33dced2e
SS		 1554/*
1555 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1556 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1557 * Re-allocate the region if needed...
1558 */
1559static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1560{
1561 struct resource *r = &dev->resource[0];
1562
1563 if (r->start & 0x8) {
1564 r->start = 0;
1565 r->end = 0xf;
1566 }
1567}
1568DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1569 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1570 quirk_tc86c001_ide);
1571
1da177e4
LT		 1572static void __devinit quirk_netmos(struct pci_dev *dev)
1573{
1574 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1575 unsigned int num_serial = dev->subsystem_device & 0xf;
1576
1577 /*
1578 * These Netmos parts are multiport serial devices with optional
1579 * parallel ports. Even when parallel ports are present, they
1580 * are identified as class SERIAL, which means the serial driver
1581 * will claim them. To prevent this, mark them as class OTHER.
1582 * These combo devices should be claimed by parport_serial.
1583 *
1584 * The subdevice ID is of the form 0x00PS, where <P> is the number
1585 * of parallel ports and <S> is the number of serial ports.
1586 */
1587 switch (dev->device) {
1588 case PCI_DEVICE_ID_NETMOS_9735:
1589 case PCI_DEVICE_ID_NETMOS_9745:
1590 case PCI_DEVICE_ID_NETMOS_9835:
1591 case PCI_DEVICE_ID_NETMOS_9845:
1592 case PCI_DEVICE_ID_NETMOS_9855:
1593 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1594 num_parallel) {
f0fda801 1595 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1da177e4
LT		 1596 "%u serial); changing class SERIAL to OTHER "
1597 "(use parport_serial)\n",
1598 dev->device, num_parallel, num_serial);
1599 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1600 (dev->class & 0xff);
1601 }
1602 }
1603}
1604DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1605
16a74744
BH		 1606static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1607{
e64aeccb 1608 u16 command, pmcsr;
16a74744
BH		 1609 u8 __iomem *csr;
1610 u8 cmd_hi;
e64aeccb 1611 int pm;
16a74744
BH		 1612
1613 switch (dev->device) {
1614 /* PCI IDs taken from drivers/net/e100.c */
1615 case 0x1029:
1616 case 0x1030 ... 0x1034:
1617 case 0x1038 ... 0x103E:
1618 case 0x1050 ... 0x1057:
1619 case 0x1059:
1620 case 0x1064 ... 0x106B:
1621 case 0x1091 ... 0x1095:
1622 case 0x1209:
1623 case 0x1229:
1624 case 0x2449:
1625 case 0x2459:
1626 case 0x245D:
1627 case 0x27DC:
1628 break;
1629 default:
1630 return;
1631 }
1632
1633 /*
1634 * Some firmware hands off the e100 with interrupts enabled,
1635 * which can cause a flood of interrupts if packets are
1636 * received before the driver attaches to the device. So
1637 * disable all e100 interrupts here. The driver will
1638 * re-enable them when it's ready.
1639 */
1640 pci_read_config_word(dev, PCI_COMMAND, &command);
16a74744 1641
1bef7dc0 1642 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
16a74744
BH		 1643 return;
1644
e64aeccb
IK		 1645 /*
1646 * Check that the device is in the D0 power state. If it's not,
1647 * there is no point to look any further.
1648 */
1649 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1650 if (pm) {
1651 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1652 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1653 return;
1654 }
1655
1bef7dc0
BH		 1656 /* Convert from PCI bus to resource space. */
1657 csr = ioremap(pci_resource_start(dev, 0), 8);
16a74744 1658 if (!csr) {
f0fda801 1659 dev_warn(&dev->dev, "Can't map e100 registers\n");
16a74744
BH		 1660 return;
1661 }
1662
1663 cmd_hi = readb(csr + 3);
1664 if (cmd_hi == 0) {
f0fda801 1665 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1666 "disabling\n");
16a74744
BH		 1667 writeb(1, csr + 3);
1668 }
1669
1670 iounmap(csr);
1671}
4e68fc97 1672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
a5312e28
IK		 1673
1674static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1675{
1676 /* rev 1 ncr53c810 chips don't set the class at all which means
1677 * they don't get their resources remapped. Fix that here.
1678 */
1679
1680 if (dev->class == PCI_CLASS_NOT_DEFINED) {
f0fda801 1681 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
a5312e28
IK		 1682 dev->class = PCI_CLASS_STORAGE_SCSI;
1683 }
1684}
1685DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1686
9d265124
DY		 1687/* Enable 1k I/O space granularity on the Intel P64H2 */
1688static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1689{
1690 u16 en1k;
1691 u8 io_base_lo, io_limit_lo;
1692 unsigned long base, limit;
1693 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1694
1695 pci_read_config_word(dev, 0x40, &en1k);
1696
1697 if (en1k & 0x200) {
f0fda801 1698 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
9d265124
DY		 1699
1700 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1701 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1702 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1703 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1704
1705 if (base <= limit) {
1706 res->start = base;
1707 res->end = limit + 0x3ff;
1708 }
1709 }
1710}
1711DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1712
15a260d5
DY		 1713/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1714 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1715 * in drivers/pci/setup-bus.c
1716 */
1717static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1718{
1719 u16 en1k, iobl_adr, iobl_adr_1k;
1720 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1721
1722 pci_read_config_word(dev, 0x40, &en1k);
1723
1724 if (en1k & 0x200) {
1725 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1726
1727 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1728
1729 if (iobl_adr != iobl_adr_1k) {
f0fda801 1730 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
15a260d5
DY		 1731 iobl_adr,iobl_adr_1k);
1732 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1733 }
1734 }
1735}
1736DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1737
cf34a8e0
BG		 1738/* Under some circumstances, AER is not linked with extended capabilities.
1739 * Force it to be linked by setting the corresponding control bit in the
1740 * config space.
1741 */
1597cacb 1742static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
cf34a8e0
BG		 1743{
1744 uint8_t b;
1745 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1746 if (!(b & 0x20)) {
1747 pci_write_config_byte(dev, 0xf41, b | 0x20);
f0fda801 1748 dev_info(&dev->dev,
1749 "Linking AER extended capability\n");
cf34a8e0
BG		 1750 }
1751 }
1752}
1753DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1754 quirk_nvidia_ck804_pcie_aer_ext_cap);
e1a2a51e 1755DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1597cacb 1756 quirk_nvidia_ck804_pcie_aer_ext_cap);
cf34a8e0 1757
53a9bf42
TY		 1758static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1759{
1760 /*
1761 * Disable PCI Bus Parking and PCI Master read caching on CX700
1762 * which causes unspecified timing errors with a VT6212L on the PCI
1763 * bus leading to USB2.0 packet loss. The defaults are that these
1764 * features are turned off but some BIOSes turn them on.
1765 */
1766
1767 uint8_t b;
1768 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1769 if (b & 0x40) {
1770 /* Turn off PCI Bus Parking */
1771 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1772
bc043274
TY		 1773 dev_info(&dev->dev,
1774 "Disabling VIA CX700 PCI parking\n");
1775 }
1776 }
1777
1778 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1779 if (b != 0) {
53a9bf42
TY		 1780 /* Turn off PCI Master read caching */
1781 pci_write_config_byte(dev, 0x72, 0x0);
bc043274
TY		 1782
1783 /* Set PCI Master Bus time-out to "1x16 PCLK" */
53a9bf42 1784 pci_write_config_byte(dev, 0x75, 0x1);
bc043274
TY		 1785
1786 /* Disable "Read FIFO Timer" */
53a9bf42
TY		 1787 pci_write_config_byte(dev, 0x77, 0x0);
1788
d6505a52 1789 dev_info(&dev->dev,
bc043274 1790 "Disabling VIA CX700 PCI caching\n");
53a9bf42
TY		 1791 }
1792 }
1793}
1794DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1795
99cb233d
BL		 1796/*
1797 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
1798 * VPD end tag will hang the device. This problem was initially
1799 * observed when a vpd entry was created in sysfs
1800 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
1801 * will dump 32k of data. Reading a full 32k will cause an access
1802 * beyond the VPD end tag causing the device to hang. Once the device
1803 * is hung, the bnx2 driver will not be able to reset the device.
1804 * We believe that it is legal to read beyond the end tag and
1805 * therefore the solution is to limit the read/write length.
1806 */
1807static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
1808{
9d82d8ea 1809 /*
35405f25
DH		 1810 * Only disable the VPD capability for 5706, 5706S, 5708,
1811 * 5708S and 5709 rev. A
9d82d8ea 1812 */
99cb233d 1813 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
35405f25 1814 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
99cb233d 1815 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
9d82d8ea 1816 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
99cb233d
BL		 1817 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
1818 (dev->revision & 0xf0) == 0x0)) {
1819 if (dev->vpd)
1820 dev->vpd->len = 0x80;
1821 }
1822}
1823
bffadffd
YZ		 1824DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1825 PCI_DEVICE_ID_NX2_5706,
1826 quirk_brcm_570x_limit_vpd);
1827DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1828 PCI_DEVICE_ID_NX2_5706S,
1829 quirk_brcm_570x_limit_vpd);
1830DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1831 PCI_DEVICE_ID_NX2_5708,
1832 quirk_brcm_570x_limit_vpd);
1833DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1834 PCI_DEVICE_ID_NX2_5708S,
1835 quirk_brcm_570x_limit_vpd);
1836DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1837 PCI_DEVICE_ID_NX2_5709,
1838 quirk_brcm_570x_limit_vpd);
1839DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1840 PCI_DEVICE_ID_NX2_5709S,
1841 quirk_brcm_570x_limit_vpd);
99cb233d 1842
3f79e107 1843#ifdef CONFIG_PCI_MSI
ebdf7d39
TH		 1844/* Some chipsets do not support MSI. We cannot easily rely on setting
1845 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1846 * some other busses controlled by the chipset even if Linux is not
1847 * aware of it. Instead of setting the flag on all busses in the
1848 * machine, simply disable MSI globally.
3f79e107 1849 */
ebdf7d39 1850static void __init quirk_disable_all_msi(struct pci_dev *dev)
3f79e107 1851{
88187dfa 1852 pci_no_msi();
f0fda801 1853 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
3f79e107 1854}
ebdf7d39
TH		 1855DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
1856DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
1857DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
66d715c9 1858DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
184b812f 1859DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
3f79e107
BG		 1860
1861/* Disable MSI on chipsets that are known to not support it */
1862static void __devinit quirk_disable_msi(struct pci_dev *dev)
1863{
1864 if (dev->subordinate) {
f0fda801 1865 dev_warn(&dev->dev, "MSI quirk detected; "
1866 "subordinate MSI disabled\n");
3f79e107
BG		 1867 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1868 }
1869}
1870DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
6397c75c
BG		 1871
1872/* Go through the list of Hypertransport capabilities and
1873 * return 1 if a HT MSI capability is found and enabled */
1874static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1875{
7a380507
ME		 1876 int pos, ttl = 48;
1877
1878 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1879 while (pos && ttl--) {
1880 u8 flags;
1881
1882 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1883 &flags) == 0)
1884 {
f0fda801 1885 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
7a380507 1886 flags & HT_MSI_FLAGS_ENABLE ?
f0fda801 1887 "enabled" : "disabled");
7a380507 1888 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
6397c75c 1889 }
7a380507
ME		 1890
1891 pos = pci_find_next_ht_capability(dev, pos,
1892 HT_CAPTYPE_MSI_MAPPING);
6397c75c
BG		 1893 }
1894 return 0;
1895}
1896
1897/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1898static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1899{
1900 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
f0fda801 1901 dev_warn(&dev->dev, "MSI quirk detected; "
1902 "subordinate MSI disabled\n");
6397c75c
BG		 1903 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1904 }
1905}
1906DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1907 quirk_msi_ht_cap);
6bae1d96
SD		 1908
1909
6397c75c
BG		 1910/* The nVidia CK804 chipset may have 2 HT MSI mappings.
1911 * MSI are supported if the MSI capability set in any of these mappings.
1912 */
1913static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1914{
1915 struct pci_dev *pdev;
1916
1917 if (!dev->subordinate)
1918 return;
1919
1920 /* check HT MSI cap on this chipset and the root one.
1921 * a single one having MSI is enough to be sure that MSI are supported.
1922 */
11f242f0 1923 pdev = pci_get_slot(dev->bus, 0);
9ac0ce85
JJ		 1924 if (!pdev)
1925 return;
0c875c28 1926 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
f0fda801 1927 dev_warn(&dev->dev, "MSI quirk detected; "
1928 "subordinate MSI disabled\n");
6397c75c
BG		 1929 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1930 }
11f242f0 1931 pci_dev_put(pdev);
6397c75c
BG		 1932}
1933DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1934 quirk_nvidia_ck804_msi_ht_cap);
ba698ad4 1935
415b6d0e
BH		 1936/* Force enable MSI mapping capability on HT bridges */
1937static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 1938{
1939 int pos, ttl = 48;
1940
1941 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1942 while (pos && ttl--) {
1943 u8 flags;
1944
1945 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1946 &flags) == 0) {
1947 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
1948
1949 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1950 flags | HT_MSI_FLAGS_ENABLE);
1951 }
1952 pos = pci_find_next_ht_capability(dev, pos,
1953 HT_CAPTYPE_MSI_MAPPING);
1954 }
1955}
415b6d0e
BH		 1956DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
1957 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
1958 ht_enable_msi_mapping);
9dc625e7 1959
75e07fc3
AP		 1960/* The P5N32-SLI Premium motherboard from Asus has a problem with msi
1961 * for the MCP55 NIC. It is not yet determined whether the msi problem
1962 * also affects other devices. As for now, turn off msi for this device.
1963 */
1964static void __devinit nvenet_msi_disable(struct pci_dev *dev)
1965{
1966 if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) {
1967 dev_info(&dev->dev,
1968 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n");
1969 dev->no_msi = 1;
1970 }
1971}
1972DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
1973 PCI_DEVICE_ID_NVIDIA_NVENET_15,
1974 nvenet_msi_disable);
1975
9dc625e7
PC		 1976static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
1977{
1978 struct pci_dev *host_bridge;
1979 int pos, ttl = 48;
1980
1981 /*
1982 * HT MSI mapping should be disabled on devices that are below
1983 * a non-Hypertransport host bridge. Locate the host bridge...
1984 */
1985 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1986 if (host_bridge == NULL) {
1987 dev_warn(&dev->dev,
1988 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
1989 return;
1990 }
1991
1992 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
1993 if (pos != 0) {
1994 /* Host bridge is to HT */
1995 ht_enable_msi_mapping(dev);
1996 return;
1997 }
1998
1999 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2000 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2001 while (pos && ttl--) {
2002 u8 flags;
2003
2004 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2005 &flags) == 0) {
415b6d0e 2006 dev_info(&dev->dev, "Disabling HT MSI mapping");
9dc625e7
PC		 2007 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2008 flags & ~HT_MSI_FLAGS_ENABLE);
2009 }
2010 pos = pci_find_next_ht_capability(dev, pos,
2011 HT_CAPTYPE_MSI_MAPPING);
2012 }
2013}
2014DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
439a7733 2015DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
9dc625e7 2016
ba698ad4
DM		 2017static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2018{
2019 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2020}
4600c9d7
SH		 2021static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2022{
2023 struct pci_dev *p;
2024
2025 /* SB700 MSI issue will be fixed at HW level from revision A21,
2026 * we need check PCI REVISION ID of SMBus controller to get SB700
2027 * revision.
2028 */
2029 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2030 NULL);
2031 if (!p)
2032 return;
2033
2034 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2035 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2036 pci_dev_put(p);
2037}
ba698ad4
DM		 2038DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2039 PCI_DEVICE_ID_TIGON3_5780,
2040 quirk_msi_intx_disable_bug);
2041DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2042 PCI_DEVICE_ID_TIGON3_5780S,
2043 quirk_msi_intx_disable_bug);
2044DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2045 PCI_DEVICE_ID_TIGON3_5714,
2046 quirk_msi_intx_disable_bug);
2047DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2048 PCI_DEVICE_ID_TIGON3_5714S,
2049 quirk_msi_intx_disable_bug);
2050DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2051 PCI_DEVICE_ID_TIGON3_5715,
2052 quirk_msi_intx_disable_bug);
2053DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2054 PCI_DEVICE_ID_TIGON3_5715S,
2055 quirk_msi_intx_disable_bug);
2056
bc38b411 2057DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
4600c9d7 2058 quirk_msi_intx_disable_ati_bug);
bc38b411 2059DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
4600c9d7 2060 quirk_msi_intx_disable_ati_bug);
bc38b411 2061DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
4600c9d7 2062 quirk_msi_intx_disable_ati_bug);
bc38b411 2063DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
4600c9d7 2064 quirk_msi_intx_disable_ati_bug);
bc38b411 2065DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
4600c9d7 2066 quirk_msi_intx_disable_ati_bug);
bc38b411
DM		 2067
2068DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2069 quirk_msi_intx_disable_bug);
2070DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2071 quirk_msi_intx_disable_bug);
2072DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2073 quirk_msi_intx_disable_bug);
2074
3f79e107 2075#endif /* CONFIG_PCI_MSI */
3d137310 2076
bfb0f330
JB		 2077static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2078 struct pci_fixup *end)
3d137310
TP		 2079{
2080 while (f < end) {
2081 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
bfb0f330 2082 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
c9bbb4ab 2083 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
3d137310
TP		 2084 f->hook(dev);
2085 }
2086 f++;
2087 }
2088}
2089
2090extern struct pci_fixup __start_pci_fixups_early[];
2091extern struct pci_fixup __end_pci_fixups_early[];
2092extern struct pci_fixup __start_pci_fixups_header[];
2093extern struct pci_fixup __end_pci_fixups_header[];
2094extern struct pci_fixup __start_pci_fixups_final[];
2095extern struct pci_fixup __end_pci_fixups_final[];
2096extern struct pci_fixup __start_pci_fixups_enable[];
2097extern struct pci_fixup __end_pci_fixups_enable[];
2098extern struct pci_fixup __start_pci_fixups_resume[];
2099extern struct pci_fixup __end_pci_fixups_resume[];
2100extern struct pci_fixup __start_pci_fixups_resume_early[];
2101extern struct pci_fixup __end_pci_fixups_resume_early[];
2102extern struct pci_fixup __start_pci_fixups_suspend[];
2103extern struct pci_fixup __end_pci_fixups_suspend[];
2104
2105
2106void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2107{
2108 struct pci_fixup *start, *end;
2109
2110 switch(pass) {
2111 case pci_fixup_early:
2112 start = __start_pci_fixups_early;
2113 end = __end_pci_fixups_early;
2114 break;
2115
2116 case pci_fixup_header:
2117 start = __start_pci_fixups_header;
2118 end = __end_pci_fixups_header;
2119 break;
2120
2121 case pci_fixup_final:
2122 start = __start_pci_fixups_final;
2123 end = __end_pci_fixups_final;
2124 break;
2125
2126 case pci_fixup_enable:
2127 start = __start_pci_fixups_enable;
2128 end = __end_pci_fixups_enable;
2129 break;
2130
2131 case pci_fixup_resume:
2132 start = __start_pci_fixups_resume;
2133 end = __end_pci_fixups_resume;
2134 break;
2135
2136 case pci_fixup_resume_early:
2137 start = __start_pci_fixups_resume_early;
2138 end = __end_pci_fixups_resume_early;
2139 break;
2140
2141 case pci_fixup_suspend:
2142 start = __start_pci_fixups_suspend;
2143 end = __end_pci_fixups_suspend;
2144 break;
2145
2146 default:
2147 /* stupid compiler warning, you would think with an enum... */
2148 return;
2149 }
2150 pci_do_fixups(dev, start, end);
2151}
2152#else
2153void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {}
2154#endif
2155EXPORT_SYMBOL(pci_fixup_device);
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