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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * probe.c - PCI detection and setup code | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/slab.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/cpumask.h> | |
7d715a6c | 12 | #include <linux/pci-aspm.h> |
05843961 | 13 | #include <acpi/acpi_hest.h> |
bc56b9e0 | 14 | #include "pci.h" |
1da177e4 LT |
15 | |
16 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
17 | #define CARDBUS_RESERVE_BUSNR 3 | |
1da177e4 LT |
18 | |
19 | /* Ugh. Need to stop exporting this to modules. */ | |
20 | LIST_HEAD(pci_root_buses); | |
21 | EXPORT_SYMBOL(pci_root_buses); | |
22 | ||
70308923 GKH |
23 | |
24 | static int find_anything(struct device *dev, void *data) | |
25 | { | |
26 | return 1; | |
27 | } | |
1da177e4 | 28 | |
ed4aaadb ZY |
29 | /* |
30 | * Some device drivers need know if pci is initiated. | |
31 | * Basically, we think pci is not initiated when there | |
70308923 | 32 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
33 | */ |
34 | int no_pci_devices(void) | |
35 | { | |
70308923 GKH |
36 | struct device *dev; |
37 | int no_devices; | |
ed4aaadb | 38 | |
70308923 GKH |
39 | dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); |
40 | no_devices = (dev == NULL); | |
41 | put_device(dev); | |
42 | return no_devices; | |
43 | } | |
ed4aaadb ZY |
44 | EXPORT_SYMBOL(no_pci_devices); |
45 | ||
1da177e4 LT |
46 | /* |
47 | * PCI Bus Class Devices | |
48 | */ | |
fd7d1ced | 49 | static ssize_t pci_bus_show_cpuaffinity(struct device *dev, |
39106dcf | 50 | int type, |
fd7d1ced | 51 | struct device_attribute *attr, |
4327edf6 | 52 | char *buf) |
1da177e4 | 53 | { |
1da177e4 | 54 | int ret; |
588235bb | 55 | const struct cpumask *cpumask; |
1da177e4 | 56 | |
588235bb | 57 | cpumask = cpumask_of_pcibus(to_pci_bus(dev)); |
39106dcf | 58 | ret = type? |
588235bb MT |
59 | cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) : |
60 | cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask); | |
39106dcf MT |
61 | buf[ret++] = '\n'; |
62 | buf[ret] = '\0'; | |
1da177e4 LT |
63 | return ret; |
64 | } | |
39106dcf MT |
65 | |
66 | static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev, | |
67 | struct device_attribute *attr, | |
68 | char *buf) | |
69 | { | |
70 | return pci_bus_show_cpuaffinity(dev, 0, attr, buf); | |
71 | } | |
72 | ||
73 | static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev, | |
74 | struct device_attribute *attr, | |
75 | char *buf) | |
76 | { | |
77 | return pci_bus_show_cpuaffinity(dev, 1, attr, buf); | |
78 | } | |
79 | ||
80 | DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL); | |
81 | DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL); | |
1da177e4 LT |
82 | |
83 | /* | |
84 | * PCI Bus Class | |
85 | */ | |
fd7d1ced | 86 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 87 | { |
fd7d1ced | 88 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 LT |
89 | |
90 | if (pci_bus->bridge) | |
91 | put_device(pci_bus->bridge); | |
92 | kfree(pci_bus); | |
93 | } | |
94 | ||
95 | static struct class pcibus_class = { | |
96 | .name = "pci_bus", | |
fd7d1ced | 97 | .dev_release = &release_pcibus_dev, |
1da177e4 LT |
98 | }; |
99 | ||
100 | static int __init pcibus_class_init(void) | |
101 | { | |
102 | return class_register(&pcibus_class); | |
103 | } | |
104 | postcore_initcall(pcibus_class_init); | |
105 | ||
106 | /* | |
107 | * Translate the low bits of the PCI base | |
108 | * to the resource type | |
109 | */ | |
110 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) | |
111 | { | |
112 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) | |
113 | return IORESOURCE_IO; | |
114 | ||
115 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
116 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
117 | ||
118 | return IORESOURCE_MEM; | |
119 | } | |
120 | ||
6ac665c6 | 121 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
1da177e4 | 122 | { |
6ac665c6 | 123 | u64 size = mask & maxbase; /* Find the significant bits */ |
1da177e4 LT |
124 | if (!size) |
125 | return 0; | |
126 | ||
127 | /* Get the lowest of them to find the decode size, and | |
128 | from that the extent. */ | |
129 | size = (size & ~(size-1)) - 1; | |
130 | ||
131 | /* base == maxbase can be valid only if the BAR has | |
132 | already been programmed with all 1s. */ | |
133 | if (base == maxbase && ((base | size) & mask) != mask) | |
134 | return 0; | |
135 | ||
136 | return size; | |
137 | } | |
138 | ||
6ac665c6 MW |
139 | static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) |
140 | { | |
141 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { | |
142 | res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; | |
143 | return pci_bar_io; | |
144 | } | |
07eddf3d | 145 | |
6ac665c6 | 146 | res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
07eddf3d | 147 | |
e354597c | 148 | if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) |
6ac665c6 MW |
149 | return pci_bar_mem64; |
150 | return pci_bar_mem32; | |
07eddf3d YL |
151 | } |
152 | ||
0b400c7e YZ |
153 | /** |
154 | * pci_read_base - read a PCI BAR | |
155 | * @dev: the PCI device | |
156 | * @type: type of the BAR | |
157 | * @res: resource buffer to be filled in | |
158 | * @pos: BAR position in the config space | |
159 | * | |
160 | * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. | |
6ac665c6 | 161 | */ |
0b400c7e | 162 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
6ac665c6 | 163 | struct resource *res, unsigned int pos) |
07eddf3d | 164 | { |
6ac665c6 MW |
165 | u32 l, sz, mask; |
166 | ||
1ed67439 | 167 | mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
6ac665c6 MW |
168 | |
169 | res->name = pci_name(dev); | |
170 | ||
171 | pci_read_config_dword(dev, pos, &l); | |
1ed67439 | 172 | pci_write_config_dword(dev, pos, l | mask); |
6ac665c6 MW |
173 | pci_read_config_dword(dev, pos, &sz); |
174 | pci_write_config_dword(dev, pos, l); | |
175 | ||
176 | /* | |
177 | * All bits set in sz means the device isn't working properly. | |
178 | * If the BAR isn't implemented, all bits must be 0. If it's a | |
179 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit | |
180 | * 1 must be clear. | |
181 | */ | |
182 | if (!sz || sz == 0xffffffff) | |
183 | goto fail; | |
184 | ||
185 | /* | |
186 | * I don't know how l can have all bits set. Copied from old code. | |
187 | * Maybe it fixes a bug on some ancient platform. | |
188 | */ | |
189 | if (l == 0xffffffff) | |
190 | l = 0; | |
191 | ||
192 | if (type == pci_bar_unknown) { | |
193 | type = decode_bar(res, l); | |
194 | res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; | |
195 | if (type == pci_bar_io) { | |
196 | l &= PCI_BASE_ADDRESS_IO_MASK; | |
1f82de10 | 197 | mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT; |
6ac665c6 MW |
198 | } else { |
199 | l &= PCI_BASE_ADDRESS_MEM_MASK; | |
200 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
201 | } | |
202 | } else { | |
203 | res->flags |= (l & IORESOURCE_ROM_ENABLE); | |
204 | l &= PCI_ROM_ADDRESS_MASK; | |
205 | mask = (u32)PCI_ROM_ADDRESS_MASK; | |
206 | } | |
207 | ||
208 | if (type == pci_bar_mem64) { | |
209 | u64 l64 = l; | |
210 | u64 sz64 = sz; | |
211 | u64 mask64 = mask | (u64)~0 << 32; | |
212 | ||
213 | pci_read_config_dword(dev, pos + 4, &l); | |
214 | pci_write_config_dword(dev, pos + 4, ~0); | |
215 | pci_read_config_dword(dev, pos + 4, &sz); | |
216 | pci_write_config_dword(dev, pos + 4, l); | |
217 | ||
218 | l64 |= ((u64)l << 32); | |
219 | sz64 |= ((u64)sz << 32); | |
220 | ||
221 | sz64 = pci_size(l64, sz64, mask64); | |
222 | ||
223 | if (!sz64) | |
224 | goto fail; | |
225 | ||
cc5499c3 | 226 | if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { |
865df576 BH |
227 | dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n", |
228 | pos); | |
6ac665c6 | 229 | goto fail; |
c7dabef8 BH |
230 | } |
231 | ||
232 | res->flags |= IORESOURCE_MEM_64; | |
233 | if ((sizeof(resource_size_t) < 8) && l) { | |
6ac665c6 MW |
234 | /* Address above 32-bit boundary; disable the BAR */ |
235 | pci_write_config_dword(dev, pos, 0); | |
236 | pci_write_config_dword(dev, pos + 4, 0); | |
237 | res->start = 0; | |
238 | res->end = sz64; | |
239 | } else { | |
240 | res->start = l64; | |
241 | res->end = l64 + sz64; | |
c7dabef8 | 242 | dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", |
a369c791 | 243 | pos, res); |
6ac665c6 MW |
244 | } |
245 | } else { | |
246 | sz = pci_size(l, sz, mask); | |
247 | ||
248 | if (!sz) | |
249 | goto fail; | |
250 | ||
251 | res->start = l; | |
252 | res->end = l + sz; | |
f393d9b1 | 253 | |
c7dabef8 | 254 | dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res); |
6ac665c6 MW |
255 | } |
256 | ||
257 | out: | |
258 | return (type == pci_bar_mem64) ? 1 : 0; | |
259 | fail: | |
260 | res->flags = 0; | |
261 | goto out; | |
07eddf3d YL |
262 | } |
263 | ||
1da177e4 LT |
264 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
265 | { | |
6ac665c6 | 266 | unsigned int pos, reg; |
07eddf3d | 267 | |
6ac665c6 MW |
268 | for (pos = 0; pos < howmany; pos++) { |
269 | struct resource *res = &dev->resource[pos]; | |
1da177e4 | 270 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
6ac665c6 | 271 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
1da177e4 | 272 | } |
6ac665c6 | 273 | |
1da177e4 | 274 | if (rom) { |
6ac665c6 | 275 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
1da177e4 | 276 | dev->rom_base_reg = rom; |
6ac665c6 MW |
277 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
278 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE | | |
279 | IORESOURCE_SIZEALIGN; | |
280 | __pci_read_base(dev, pci_bar_mem32, res, rom); | |
1da177e4 LT |
281 | } |
282 | } | |
283 | ||
fa27b2d1 | 284 | static void __devinit pci_read_bridge_io(struct pci_bus *child) |
1da177e4 LT |
285 | { |
286 | struct pci_dev *dev = child->self; | |
287 | u8 io_base_lo, io_limit_lo; | |
1da177e4 LT |
288 | unsigned long base, limit; |
289 | struct resource *res; | |
1da177e4 | 290 | |
1da177e4 LT |
291 | res = child->resource[0]; |
292 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
293 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
294 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
295 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
296 | ||
297 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
298 | u16 io_base_hi, io_limit_hi; | |
299 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
300 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
301 | base |= (io_base_hi << 16); | |
302 | limit |= (io_limit_hi << 16); | |
303 | } | |
304 | ||
cd81e1ea | 305 | if (base && base <= limit) { |
1da177e4 | 306 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; |
9d265124 DY |
307 | if (!res->start) |
308 | res->start = base; | |
309 | if (!res->end) | |
310 | res->end = limit + 0xfff; | |
c7dabef8 | 311 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
cd81e1ea YL |
312 | } else { |
313 | dev_printk(KERN_DEBUG, &dev->dev, | |
314 | " bridge window [io %04lx - %04lx] reg reading\n", | |
315 | base, limit); | |
1da177e4 | 316 | } |
fa27b2d1 BH |
317 | } |
318 | ||
319 | static void __devinit pci_read_bridge_mmio(struct pci_bus *child) | |
320 | { | |
321 | struct pci_dev *dev = child->self; | |
322 | u16 mem_base_lo, mem_limit_lo; | |
323 | unsigned long base, limit; | |
324 | struct resource *res; | |
1da177e4 LT |
325 | |
326 | res = child->resource[1]; | |
327 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
328 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
329 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
330 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
cd81e1ea | 331 | if (base && base <= limit) { |
1da177e4 LT |
332 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; |
333 | res->start = base; | |
334 | res->end = limit + 0xfffff; | |
c7dabef8 | 335 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
cd81e1ea YL |
336 | } else { |
337 | dev_printk(KERN_DEBUG, &dev->dev, | |
338 | " bridge window [mem 0x%08lx - 0x%08lx] reg reading\n", | |
339 | base, limit + 0xfffff); | |
1da177e4 | 340 | } |
fa27b2d1 BH |
341 | } |
342 | ||
343 | static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child) | |
344 | { | |
345 | struct pci_dev *dev = child->self; | |
346 | u16 mem_base_lo, mem_limit_lo; | |
347 | unsigned long base, limit; | |
348 | struct resource *res; | |
1da177e4 LT |
349 | |
350 | res = child->resource[2]; | |
351 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
352 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
353 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
354 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
355 | ||
356 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
357 | u32 mem_base_hi, mem_limit_hi; | |
358 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
359 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
360 | ||
361 | /* | |
362 | * Some bridges set the base > limit by default, and some | |
363 | * (broken) BIOSes do not initialize them. If we find | |
364 | * this, just assume they are not being used. | |
365 | */ | |
366 | if (mem_base_hi <= mem_limit_hi) { | |
367 | #if BITS_PER_LONG == 64 | |
368 | base |= ((long) mem_base_hi) << 32; | |
369 | limit |= ((long) mem_limit_hi) << 32; | |
370 | #else | |
371 | if (mem_base_hi || mem_limit_hi) { | |
80ccba11 BH |
372 | dev_err(&dev->dev, "can't handle 64-bit " |
373 | "address space for bridge\n"); | |
1da177e4 LT |
374 | return; |
375 | } | |
376 | #endif | |
377 | } | |
378 | } | |
cd81e1ea | 379 | if (base && base <= limit) { |
1f82de10 YL |
380 | res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | |
381 | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
382 | if (res->flags & PCI_PREF_RANGE_TYPE_64) | |
383 | res->flags |= IORESOURCE_MEM_64; | |
1da177e4 LT |
384 | res->start = base; |
385 | res->end = limit + 0xfffff; | |
c7dabef8 | 386 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
cd81e1ea YL |
387 | } else { |
388 | dev_printk(KERN_DEBUG, &dev->dev, | |
389 | " bridge window [mem 0x%08lx - %08lx pref] reg reading\n", | |
390 | base, limit + 0xfffff); | |
1da177e4 LT |
391 | } |
392 | } | |
393 | ||
fa27b2d1 BH |
394 | void __devinit pci_read_bridge_bases(struct pci_bus *child) |
395 | { | |
396 | struct pci_dev *dev = child->self; | |
397 | int i; | |
398 | ||
399 | if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ | |
400 | return; | |
401 | ||
402 | dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n", | |
403 | child->secondary, child->subordinate, | |
404 | dev->transparent ? " (subtractive decode)" : ""); | |
405 | ||
fa27b2d1 BH |
406 | pci_read_bridge_io(child); |
407 | pci_read_bridge_mmio(child); | |
408 | pci_read_bridge_mmio_pref(child); | |
2adf7516 BH |
409 | |
410 | if (dev->transparent) { | |
411 | for (i = 3; i < PCI_BUS_NUM_RESOURCES; i++) { | |
412 | child->resource[i] = child->parent->resource[i - 3]; | |
413 | if (child->resource[i]) | |
414 | dev_printk(KERN_DEBUG, &dev->dev, | |
415 | " bridge window %pR (subtractive decode)\n", | |
416 | child->resource[i]); | |
417 | } | |
418 | } | |
fa27b2d1 BH |
419 | } |
420 | ||
96bde06a | 421 | static struct pci_bus * pci_alloc_bus(void) |
1da177e4 LT |
422 | { |
423 | struct pci_bus *b; | |
424 | ||
f5afe806 | 425 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
1da177e4 | 426 | if (b) { |
1da177e4 LT |
427 | INIT_LIST_HEAD(&b->node); |
428 | INIT_LIST_HEAD(&b->children); | |
429 | INIT_LIST_HEAD(&b->devices); | |
f46753c5 | 430 | INIT_LIST_HEAD(&b->slots); |
3749c51a MW |
431 | b->max_bus_speed = PCI_SPEED_UNKNOWN; |
432 | b->cur_bus_speed = PCI_SPEED_UNKNOWN; | |
1da177e4 LT |
433 | } |
434 | return b; | |
435 | } | |
436 | ||
9be60ca0 MW |
437 | static unsigned char pcix_bus_speed[] = { |
438 | PCI_SPEED_UNKNOWN, /* 0 */ | |
439 | PCI_SPEED_66MHz_PCIX, /* 1 */ | |
440 | PCI_SPEED_100MHz_PCIX, /* 2 */ | |
441 | PCI_SPEED_133MHz_PCIX, /* 3 */ | |
442 | PCI_SPEED_UNKNOWN, /* 4 */ | |
443 | PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ | |
444 | PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ | |
445 | PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ | |
446 | PCI_SPEED_UNKNOWN, /* 8 */ | |
447 | PCI_SPEED_66MHz_PCIX_266, /* 9 */ | |
448 | PCI_SPEED_100MHz_PCIX_266, /* A */ | |
449 | PCI_SPEED_133MHz_PCIX_266, /* B */ | |
450 | PCI_SPEED_UNKNOWN, /* C */ | |
451 | PCI_SPEED_66MHz_PCIX_533, /* D */ | |
452 | PCI_SPEED_100MHz_PCIX_533, /* E */ | |
453 | PCI_SPEED_133MHz_PCIX_533 /* F */ | |
454 | }; | |
455 | ||
3749c51a MW |
456 | static unsigned char pcie_link_speed[] = { |
457 | PCI_SPEED_UNKNOWN, /* 0 */ | |
458 | PCIE_SPEED_2_5GT, /* 1 */ | |
459 | PCIE_SPEED_5_0GT, /* 2 */ | |
9dfd97fe | 460 | PCIE_SPEED_8_0GT, /* 3 */ |
3749c51a MW |
461 | PCI_SPEED_UNKNOWN, /* 4 */ |
462 | PCI_SPEED_UNKNOWN, /* 5 */ | |
463 | PCI_SPEED_UNKNOWN, /* 6 */ | |
464 | PCI_SPEED_UNKNOWN, /* 7 */ | |
465 | PCI_SPEED_UNKNOWN, /* 8 */ | |
466 | PCI_SPEED_UNKNOWN, /* 9 */ | |
467 | PCI_SPEED_UNKNOWN, /* A */ | |
468 | PCI_SPEED_UNKNOWN, /* B */ | |
469 | PCI_SPEED_UNKNOWN, /* C */ | |
470 | PCI_SPEED_UNKNOWN, /* D */ | |
471 | PCI_SPEED_UNKNOWN, /* E */ | |
472 | PCI_SPEED_UNKNOWN /* F */ | |
473 | }; | |
474 | ||
475 | void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) | |
476 | { | |
477 | bus->cur_bus_speed = pcie_link_speed[linksta & 0xf]; | |
478 | } | |
479 | EXPORT_SYMBOL_GPL(pcie_update_link_speed); | |
480 | ||
45b4cdd5 MW |
481 | static unsigned char agp_speeds[] = { |
482 | AGP_UNKNOWN, | |
483 | AGP_1X, | |
484 | AGP_2X, | |
485 | AGP_4X, | |
486 | AGP_8X | |
487 | }; | |
488 | ||
489 | static enum pci_bus_speed agp_speed(int agp3, int agpstat) | |
490 | { | |
491 | int index = 0; | |
492 | ||
493 | if (agpstat & 4) | |
494 | index = 3; | |
495 | else if (agpstat & 2) | |
496 | index = 2; | |
497 | else if (agpstat & 1) | |
498 | index = 1; | |
499 | else | |
500 | goto out; | |
501 | ||
502 | if (agp3) { | |
503 | index += 2; | |
504 | if (index == 5) | |
505 | index = 0; | |
506 | } | |
507 | ||
508 | out: | |
509 | return agp_speeds[index]; | |
510 | } | |
511 | ||
512 | ||
9be60ca0 MW |
513 | static void pci_set_bus_speed(struct pci_bus *bus) |
514 | { | |
515 | struct pci_dev *bridge = bus->self; | |
516 | int pos; | |
517 | ||
45b4cdd5 MW |
518 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); |
519 | if (!pos) | |
520 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); | |
521 | if (pos) { | |
522 | u32 agpstat, agpcmd; | |
523 | ||
524 | pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); | |
525 | bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); | |
526 | ||
527 | pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); | |
528 | bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); | |
529 | } | |
530 | ||
9be60ca0 MW |
531 | pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); |
532 | if (pos) { | |
533 | u16 status; | |
534 | enum pci_bus_speed max; | |
535 | pci_read_config_word(bridge, pos + 2, &status); | |
536 | ||
537 | if (status & 0x8000) { | |
538 | max = PCI_SPEED_133MHz_PCIX_533; | |
539 | } else if (status & 0x4000) { | |
540 | max = PCI_SPEED_133MHz_PCIX_266; | |
541 | } else if (status & 0x0002) { | |
542 | if (((status >> 12) & 0x3) == 2) { | |
543 | max = PCI_SPEED_133MHz_PCIX_ECC; | |
544 | } else { | |
545 | max = PCI_SPEED_133MHz_PCIX; | |
546 | } | |
547 | } else { | |
548 | max = PCI_SPEED_66MHz_PCIX; | |
549 | } | |
550 | ||
551 | bus->max_bus_speed = max; | |
552 | bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf]; | |
553 | ||
554 | return; | |
555 | } | |
556 | ||
557 | pos = pci_find_capability(bridge, PCI_CAP_ID_EXP); | |
558 | if (pos) { | |
559 | u32 linkcap; | |
560 | u16 linksta; | |
561 | ||
562 | pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap); | |
563 | bus->max_bus_speed = pcie_link_speed[linkcap & 0xf]; | |
564 | ||
565 | pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta); | |
566 | pcie_update_link_speed(bus, linksta); | |
567 | } | |
568 | } | |
569 | ||
570 | ||
cbd4e055 AB |
571 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
572 | struct pci_dev *bridge, int busnr) | |
1da177e4 LT |
573 | { |
574 | struct pci_bus *child; | |
575 | int i; | |
576 | ||
577 | /* | |
578 | * Allocate a new bus, and inherit stuff from the parent.. | |
579 | */ | |
580 | child = pci_alloc_bus(); | |
581 | if (!child) | |
582 | return NULL; | |
583 | ||
1da177e4 LT |
584 | child->parent = parent; |
585 | child->ops = parent->ops; | |
586 | child->sysdata = parent->sysdata; | |
6e325a62 | 587 | child->bus_flags = parent->bus_flags; |
1da177e4 | 588 | |
fd7d1ced GKH |
589 | /* initialize some portions of the bus device, but don't register it |
590 | * now as the parent is not properly set up yet. This device will get | |
591 | * registered later in pci_bus_add_devices() | |
592 | */ | |
593 | child->dev.class = &pcibus_class; | |
1a927133 | 594 | dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
1da177e4 LT |
595 | |
596 | /* | |
597 | * Set up the primary, secondary and subordinate | |
598 | * bus numbers. | |
599 | */ | |
600 | child->number = child->secondary = busnr; | |
601 | child->primary = parent->secondary; | |
602 | child->subordinate = 0xff; | |
603 | ||
3789fa8a YZ |
604 | if (!bridge) |
605 | return child; | |
606 | ||
607 | child->self = bridge; | |
608 | child->bridge = get_device(&bridge->dev); | |
609 | ||
9be60ca0 MW |
610 | pci_set_bus_speed(child); |
611 | ||
1da177e4 | 612 | /* Set up default resource pointers and names.. */ |
fde09c6d | 613 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
1da177e4 LT |
614 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
615 | child->resource[i]->name = child->name; | |
616 | } | |
617 | bridge->subordinate = child; | |
618 | ||
619 | return child; | |
620 | } | |
621 | ||
451124a7 | 622 | struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
1da177e4 LT |
623 | { |
624 | struct pci_bus *child; | |
625 | ||
626 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 627 | if (child) { |
d71374da | 628 | down_write(&pci_bus_sem); |
1da177e4 | 629 | list_add_tail(&child->node, &parent->children); |
d71374da | 630 | up_write(&pci_bus_sem); |
e4ea9bb7 | 631 | } |
1da177e4 LT |
632 | return child; |
633 | } | |
634 | ||
96bde06a | 635 | static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) |
26f674ae GKH |
636 | { |
637 | struct pci_bus *parent = child->parent; | |
12f44f46 IK |
638 | |
639 | /* Attempts to fix that up are really dangerous unless | |
640 | we're going to re-assign all bus numbers. */ | |
641 | if (!pcibios_assign_all_busses()) | |
642 | return; | |
643 | ||
26f674ae GKH |
644 | while (parent->parent && parent->subordinate < max) { |
645 | parent->subordinate = max; | |
646 | pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); | |
647 | parent = parent->parent; | |
648 | } | |
649 | } | |
650 | ||
1da177e4 LT |
651 | /* |
652 | * If it's a bridge, configure it and scan the bus behind it. | |
653 | * For CardBus bridges, we don't scan behind as the devices will | |
654 | * be handled by the bridge driver itself. | |
655 | * | |
656 | * We need to process bridges in two passes -- first we scan those | |
657 | * already configured by the BIOS and after we are done with all of | |
658 | * them, we proceed to assigning numbers to the remaining buses in | |
659 | * order to avoid overlaps between old and new bus numbers. | |
660 | */ | |
0ab2b57f | 661 | int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
1da177e4 LT |
662 | { |
663 | struct pci_bus *child; | |
664 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 665 | u32 buses, i, j = 0; |
1da177e4 | 666 | u16 bctl; |
a1c19894 | 667 | int broken = 0; |
1da177e4 LT |
668 | |
669 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); | |
670 | ||
80ccba11 BH |
671 | dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n", |
672 | buses & 0xffffff, pass); | |
1da177e4 | 673 | |
a1c19894 BH |
674 | /* Check if setup is sensible at all */ |
675 | if (!pass && | |
676 | ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) { | |
677 | dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n"); | |
678 | broken = 1; | |
679 | } | |
680 | ||
1da177e4 LT |
681 | /* Disable MasterAbortMode during probing to avoid reporting |
682 | of bus errors (in some architectures) */ | |
683 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); | |
684 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
685 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
686 | ||
a1c19894 | 687 | if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) { |
1da177e4 LT |
688 | unsigned int cmax, busnr; |
689 | /* | |
690 | * Bus already configured by firmware, process it in the first | |
691 | * pass and just note the configuration. | |
692 | */ | |
693 | if (pass) | |
bbe8f9a3 | 694 | goto out; |
1da177e4 LT |
695 | busnr = (buses >> 8) & 0xFF; |
696 | ||
697 | /* | |
698 | * If we already got to this bus through a different bridge, | |
74710ded AC |
699 | * don't re-add it. This can happen with the i450NX chipset. |
700 | * | |
701 | * However, we continue to descend down the hierarchy and | |
702 | * scan remaining child buses. | |
1da177e4 | 703 | */ |
74710ded AC |
704 | child = pci_find_bus(pci_domain_nr(bus), busnr); |
705 | if (!child) { | |
706 | child = pci_add_new_bus(bus, dev, busnr); | |
707 | if (!child) | |
708 | goto out; | |
709 | child->primary = buses & 0xFF; | |
710 | child->subordinate = (buses >> 16) & 0xFF; | |
711 | child->bridge_ctl = bctl; | |
1da177e4 LT |
712 | } |
713 | ||
1da177e4 LT |
714 | cmax = pci_scan_child_bus(child); |
715 | if (cmax > max) | |
716 | max = cmax; | |
717 | if (child->subordinate > max) | |
718 | max = child->subordinate; | |
719 | } else { | |
720 | /* | |
721 | * We need to assign a number to this bus which we always | |
722 | * do in the second pass. | |
723 | */ | |
12f44f46 | 724 | if (!pass) { |
a1c19894 | 725 | if (pcibios_assign_all_busses() || broken) |
12f44f46 IK |
726 | /* Temporarily disable forwarding of the |
727 | configuration cycles on all bridges in | |
728 | this bus segment to avoid possible | |
729 | conflicts in the second pass between two | |
730 | bridges programmed with overlapping | |
731 | bus ranges. */ | |
732 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, | |
733 | buses & ~0xffffff); | |
bbe8f9a3 | 734 | goto out; |
12f44f46 | 735 | } |
1da177e4 LT |
736 | |
737 | /* Clear errors */ | |
738 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
739 | ||
cc57450f RS |
740 | /* Prevent assigning a bus number that already exists. |
741 | * This can happen when a bridge is hot-plugged */ | |
742 | if (pci_find_bus(pci_domain_nr(bus), max+1)) | |
bbe8f9a3 | 743 | goto out; |
6ef6f0e3 | 744 | child = pci_add_new_bus(bus, dev, ++max); |
1da177e4 LT |
745 | buses = (buses & 0xff000000) |
746 | | ((unsigned int)(child->primary) << 0) | |
747 | | ((unsigned int)(child->secondary) << 8) | |
748 | | ((unsigned int)(child->subordinate) << 16); | |
749 | ||
750 | /* | |
751 | * yenta.c forces a secondary latency timer of 176. | |
752 | * Copy that behaviour here. | |
753 | */ | |
754 | if (is_cardbus) { | |
755 | buses &= ~0xff000000; | |
756 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
757 | } | |
758 | ||
759 | /* | |
760 | * We need to blast all three values with a single write. | |
761 | */ | |
762 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); | |
763 | ||
764 | if (!is_cardbus) { | |
11949255 | 765 | child->bridge_ctl = bctl; |
26f674ae GKH |
766 | /* |
767 | * Adjust subordinate busnr in parent buses. | |
768 | * We do this before scanning for children because | |
769 | * some devices may not be detected if the bios | |
770 | * was lazy. | |
771 | */ | |
772 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
773 | /* Now we can scan all subordinate buses... */ |
774 | max = pci_scan_child_bus(child); | |
e3ac86d8 KA |
775 | /* |
776 | * now fix it up again since we have found | |
777 | * the real value of max. | |
778 | */ | |
779 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
780 | } else { |
781 | /* | |
782 | * For CardBus bridges, we leave 4 bus numbers | |
783 | * as cards with a PCI-to-PCI bridge can be | |
784 | * inserted later. | |
785 | */ | |
49887941 DB |
786 | for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { |
787 | struct pci_bus *parent = bus; | |
cc57450f RS |
788 | if (pci_find_bus(pci_domain_nr(bus), |
789 | max+i+1)) | |
790 | break; | |
49887941 DB |
791 | while (parent->parent) { |
792 | if ((!pcibios_assign_all_busses()) && | |
793 | (parent->subordinate > max) && | |
794 | (parent->subordinate <= max+i)) { | |
795 | j = 1; | |
796 | } | |
797 | parent = parent->parent; | |
798 | } | |
799 | if (j) { | |
800 | /* | |
801 | * Often, there are two cardbus bridges | |
802 | * -- try to leave one valid bus number | |
803 | * for each one. | |
804 | */ | |
805 | i /= 2; | |
806 | break; | |
807 | } | |
808 | } | |
cc57450f | 809 | max += i; |
26f674ae | 810 | pci_fixup_parent_subordinate_busnr(child, max); |
1da177e4 LT |
811 | } |
812 | /* | |
813 | * Set the subordinate bus number to its real value. | |
814 | */ | |
815 | child->subordinate = max; | |
816 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); | |
817 | } | |
818 | ||
cb3576fa GH |
819 | sprintf(child->name, |
820 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
821 | pci_domain_nr(bus), child->number); | |
1da177e4 | 822 | |
d55bef51 | 823 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
49887941 DB |
824 | while (bus->parent) { |
825 | if ((child->subordinate > bus->subordinate) || | |
826 | (child->number > bus->subordinate) || | |
827 | (child->number < bus->number) || | |
828 | (child->subordinate < bus->number)) { | |
865df576 BH |
829 | dev_info(&child->dev, "[bus %02x-%02x] %s " |
830 | "hidden behind%s bridge %s [bus %02x-%02x]\n", | |
d55bef51 BK |
831 | child->number, child->subordinate, |
832 | (bus->number > child->subordinate && | |
833 | bus->subordinate < child->number) ? | |
a6f29a98 JP |
834 | "wholly" : "partially", |
835 | bus->self->transparent ? " transparent" : "", | |
865df576 | 836 | dev_name(&bus->dev), |
d55bef51 | 837 | bus->number, bus->subordinate); |
49887941 DB |
838 | } |
839 | bus = bus->parent; | |
840 | } | |
841 | ||
bbe8f9a3 RB |
842 | out: |
843 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
844 | ||
1da177e4 LT |
845 | return max; |
846 | } | |
847 | ||
848 | /* | |
849 | * Read interrupt line and base address registers. | |
850 | * The architecture-dependent code can tweak these, of course. | |
851 | */ | |
852 | static void pci_read_irq(struct pci_dev *dev) | |
853 | { | |
854 | unsigned char irq; | |
855 | ||
856 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); | |
ffeff788 | 857 | dev->pin = irq; |
1da177e4 LT |
858 | if (irq) |
859 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
860 | dev->irq = irq; | |
861 | } | |
862 | ||
bb209c82 | 863 | void set_pcie_port_type(struct pci_dev *pdev) |
480b93b7 YZ |
864 | { |
865 | int pos; | |
866 | u16 reg16; | |
867 | ||
868 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
869 | if (!pos) | |
870 | return; | |
871 | pdev->is_pcie = 1; | |
0efea000 | 872 | pdev->pcie_cap = pos; |
480b93b7 YZ |
873 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
874 | pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; | |
875 | } | |
876 | ||
bb209c82 | 877 | void set_pcie_hotplug_bridge(struct pci_dev *pdev) |
28760489 EB |
878 | { |
879 | int pos; | |
880 | u16 reg16; | |
881 | u32 reg32; | |
882 | ||
06a1cbaf | 883 | pos = pci_pcie_cap(pdev); |
28760489 EB |
884 | if (!pos) |
885 | return; | |
886 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); | |
887 | if (!(reg16 & PCI_EXP_FLAGS_SLOT)) | |
888 | return; | |
889 | pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32); | |
890 | if (reg32 & PCI_EXP_SLTCAP_HPC) | |
891 | pdev->is_hotplug_bridge = 1; | |
892 | } | |
893 | ||
05843961 MD |
894 | static void set_pci_aer_firmware_first(struct pci_dev *pdev) |
895 | { | |
896 | if (acpi_hest_firmware_first_pci(pdev)) | |
897 | pdev->aer_firmware_first = 1; | |
898 | } | |
899 | ||
01abc2aa | 900 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 901 | |
1da177e4 LT |
902 | /** |
903 | * pci_setup_device - fill in class and map information of a device | |
904 | * @dev: the device structure to fill | |
905 | * | |
906 | * Initialize the device structure with information about the device's | |
907 | * vendor,class,memory and IO-space addresses,IRQ lines etc. | |
908 | * Called at initialisation of the PCI subsystem and by CardBus services. | |
480b93b7 YZ |
909 | * Returns 0 on success and negative if unknown type of device (not normal, |
910 | * bridge or CardBus). | |
1da177e4 | 911 | */ |
480b93b7 | 912 | int pci_setup_device(struct pci_dev *dev) |
1da177e4 LT |
913 | { |
914 | u32 class; | |
480b93b7 YZ |
915 | u8 hdr_type; |
916 | struct pci_slot *slot; | |
bc577d2b | 917 | int pos = 0; |
480b93b7 YZ |
918 | |
919 | if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) | |
920 | return -EIO; | |
921 | ||
922 | dev->sysdata = dev->bus->sysdata; | |
923 | dev->dev.parent = dev->bus->bridge; | |
924 | dev->dev.bus = &pci_bus_type; | |
925 | dev->hdr_type = hdr_type & 0x7f; | |
926 | dev->multifunction = !!(hdr_type & 0x80); | |
480b93b7 YZ |
927 | dev->error_state = pci_channel_io_normal; |
928 | set_pcie_port_type(dev); | |
05843961 | 929 | set_pci_aer_firmware_first(dev); |
480b93b7 YZ |
930 | |
931 | list_for_each_entry(slot, &dev->bus->slots, list) | |
932 | if (PCI_SLOT(dev->devfn) == slot->number) | |
933 | dev->slot = slot; | |
934 | ||
935 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) | |
936 | set this higher, assuming the system even supports it. */ | |
937 | dev->dma_mask = 0xffffffff; | |
1da177e4 | 938 | |
eebfcfb5 GKH |
939 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
940 | dev->bus->number, PCI_SLOT(dev->devfn), | |
941 | PCI_FUNC(dev->devfn)); | |
1da177e4 LT |
942 | |
943 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
b8a3a521 | 944 | dev->revision = class & 0xff; |
1da177e4 LT |
945 | class >>= 8; /* upper 3 bytes */ |
946 | dev->class = class; | |
947 | class >>= 8; | |
948 | ||
34a2e15e | 949 | dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n", |
1da177e4 LT |
950 | dev->vendor, dev->device, class, dev->hdr_type); |
951 | ||
853346e4 YZ |
952 | /* need to have dev->class ready */ |
953 | dev->cfg_size = pci_cfg_space_size(dev); | |
954 | ||
1da177e4 | 955 | /* "Unknown power state" */ |
3fe9d19f | 956 | dev->current_state = PCI_UNKNOWN; |
1da177e4 LT |
957 | |
958 | /* Early fixups, before probing the BARs */ | |
959 | pci_fixup_device(pci_fixup_early, dev); | |
f79b1b14 YZ |
960 | /* device class may be changed after fixup */ |
961 | class = dev->class >> 8; | |
1da177e4 LT |
962 | |
963 | switch (dev->hdr_type) { /* header type */ | |
964 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
965 | if (class == PCI_CLASS_BRIDGE_PCI) | |
966 | goto bad; | |
967 | pci_read_irq(dev); | |
968 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
969 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
970 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); | |
368c73d4 AC |
971 | |
972 | /* | |
973 | * Do the ugly legacy mode stuff here rather than broken chip | |
974 | * quirk code. Legacy mode ATA controllers have fixed | |
975 | * addresses. These are not always echoed in BAR0-3, and | |
976 | * BAR0-3 in a few cases contain junk! | |
977 | */ | |
978 | if (class == PCI_CLASS_STORAGE_IDE) { | |
979 | u8 progif; | |
980 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
981 | if ((progif & 1) == 0) { | |
af1bff4f LT |
982 | dev->resource[0].start = 0x1F0; |
983 | dev->resource[0].end = 0x1F7; | |
984 | dev->resource[0].flags = LEGACY_IO_RESOURCE; | |
985 | dev->resource[1].start = 0x3F6; | |
986 | dev->resource[1].end = 0x3F6; | |
987 | dev->resource[1].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
988 | } |
989 | if ((progif & 4) == 0) { | |
af1bff4f LT |
990 | dev->resource[2].start = 0x170; |
991 | dev->resource[2].end = 0x177; | |
992 | dev->resource[2].flags = LEGACY_IO_RESOURCE; | |
993 | dev->resource[3].start = 0x376; | |
994 | dev->resource[3].end = 0x376; | |
995 | dev->resource[3].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
996 | } |
997 | } | |
1da177e4 LT |
998 | break; |
999 | ||
1000 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
1001 | if (class != PCI_CLASS_BRIDGE_PCI) | |
1002 | goto bad; | |
1003 | /* The PCI-to-PCI bridge spec requires that subtractive | |
1004 | decoding (i.e. transparent) bridge must have programming | |
1005 | interface code of 0x01. */ | |
3efd273b | 1006 | pci_read_irq(dev); |
1da177e4 LT |
1007 | dev->transparent = ((dev->class & 0xff) == 1); |
1008 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
28760489 | 1009 | set_pcie_hotplug_bridge(dev); |
bc577d2b GB |
1010 | pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); |
1011 | if (pos) { | |
1012 | pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); | |
1013 | pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); | |
1014 | } | |
1da177e4 LT |
1015 | break; |
1016 | ||
1017 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
1018 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
1019 | goto bad; | |
1020 | pci_read_irq(dev); | |
1021 | pci_read_bases(dev, 1, 0); | |
1022 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
1023 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
1024 | break; | |
1025 | ||
1026 | default: /* unknown header */ | |
80ccba11 BH |
1027 | dev_err(&dev->dev, "unknown header type %02x, " |
1028 | "ignoring device\n", dev->hdr_type); | |
480b93b7 | 1029 | return -EIO; |
1da177e4 LT |
1030 | |
1031 | bad: | |
80ccba11 BH |
1032 | dev_err(&dev->dev, "ignoring class %02x (doesn't match header " |
1033 | "type %02x)\n", class, dev->hdr_type); | |
1da177e4 LT |
1034 | dev->class = PCI_CLASS_NOT_DEFINED; |
1035 | } | |
1036 | ||
1037 | /* We found a fine healthy device, go go go... */ | |
1038 | return 0; | |
1039 | } | |
1040 | ||
201de56e ZY |
1041 | static void pci_release_capabilities(struct pci_dev *dev) |
1042 | { | |
1043 | pci_vpd_release(dev); | |
d1b054da | 1044 | pci_iov_release(dev); |
201de56e ZY |
1045 | } |
1046 | ||
1da177e4 LT |
1047 | /** |
1048 | * pci_release_dev - free a pci device structure when all users of it are finished. | |
1049 | * @dev: device that's been disconnected | |
1050 | * | |
1051 | * Will be called only by the device core when all users of this pci device are | |
1052 | * done. | |
1053 | */ | |
1054 | static void pci_release_dev(struct device *dev) | |
1055 | { | |
1056 | struct pci_dev *pci_dev; | |
1057 | ||
1058 | pci_dev = to_pci_dev(dev); | |
201de56e | 1059 | pci_release_capabilities(pci_dev); |
1da177e4 LT |
1060 | kfree(pci_dev); |
1061 | } | |
1062 | ||
1063 | /** | |
1064 | * pci_cfg_space_size - get the configuration space size of the PCI device. | |
8f7020d3 | 1065 | * @dev: PCI device |
1da177e4 LT |
1066 | * |
1067 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
1068 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
1069 | * access it. Maybe we don't have a way to generate extended config space | |
1070 | * accesses, or the device is behind a reverse Express bridge. So we try | |
1071 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
1072 | * capability header. | |
1073 | */ | |
70b9f7dc | 1074 | int pci_cfg_space_size_ext(struct pci_dev *dev) |
1da177e4 | 1075 | { |
1da177e4 | 1076 | u32 status; |
557848c3 | 1077 | int pos = PCI_CFG_SPACE_SIZE; |
1da177e4 | 1078 | |
557848c3 | 1079 | if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) |
70b9f7dc YL |
1080 | goto fail; |
1081 | if (status == 0xffffffff) | |
1082 | goto fail; | |
1083 | ||
1084 | return PCI_CFG_SPACE_EXP_SIZE; | |
1085 | ||
1086 | fail: | |
1087 | return PCI_CFG_SPACE_SIZE; | |
1088 | } | |
1089 | ||
1090 | int pci_cfg_space_size(struct pci_dev *dev) | |
1091 | { | |
1092 | int pos; | |
1093 | u32 status; | |
dfadd9ed YL |
1094 | u16 class; |
1095 | ||
1096 | class = dev->class >> 8; | |
1097 | if (class == PCI_CLASS_BRIDGE_HOST) | |
1098 | return pci_cfg_space_size_ext(dev); | |
57741a77 | 1099 | |
06a1cbaf | 1100 | pos = pci_pcie_cap(dev); |
1da177e4 LT |
1101 | if (!pos) { |
1102 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1103 | if (!pos) | |
1104 | goto fail; | |
1105 | ||
1106 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); | |
1107 | if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) | |
1108 | goto fail; | |
1109 | } | |
1110 | ||
70b9f7dc | 1111 | return pci_cfg_space_size_ext(dev); |
1da177e4 LT |
1112 | |
1113 | fail: | |
1114 | return PCI_CFG_SPACE_SIZE; | |
1115 | } | |
1116 | ||
1117 | static void pci_release_bus_bridge_dev(struct device *dev) | |
1118 | { | |
1119 | kfree(dev); | |
1120 | } | |
1121 | ||
65891215 ME |
1122 | struct pci_dev *alloc_pci_dev(void) |
1123 | { | |
1124 | struct pci_dev *dev; | |
1125 | ||
1126 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
1127 | if (!dev) | |
1128 | return NULL; | |
1129 | ||
65891215 ME |
1130 | INIT_LIST_HEAD(&dev->bus_list); |
1131 | ||
1132 | return dev; | |
1133 | } | |
1134 | EXPORT_SYMBOL(alloc_pci_dev); | |
1135 | ||
1da177e4 LT |
1136 | /* |
1137 | * Read the config data for a PCI device, sanity-check it | |
1138 | * and fill in the dev structure... | |
1139 | */ | |
7f7b5de2 | 1140 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) |
1da177e4 LT |
1141 | { |
1142 | struct pci_dev *dev; | |
1143 | u32 l; | |
1da177e4 LT |
1144 | int delay = 1; |
1145 | ||
1146 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
1147 | return NULL; | |
1148 | ||
1149 | /* some broken boards return 0 or ~0 if a slot is empty: */ | |
1150 | if (l == 0xffffffff || l == 0x00000000 || | |
1151 | l == 0x0000ffff || l == 0xffff0000) | |
1152 | return NULL; | |
1153 | ||
1154 | /* Configuration request Retry Status */ | |
1155 | while (l == 0xffff0001) { | |
1156 | msleep(delay); | |
1157 | delay *= 2; | |
1158 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
1159 | return NULL; | |
1160 | /* Card hasn't responded in 60 seconds? Must be stuck. */ | |
1161 | if (delay > 60 * 1000) { | |
80ccba11 | 1162 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " |
1da177e4 LT |
1163 | "responding\n", pci_domain_nr(bus), |
1164 | bus->number, PCI_SLOT(devfn), | |
1165 | PCI_FUNC(devfn)); | |
1166 | return NULL; | |
1167 | } | |
1168 | } | |
1169 | ||
bab41e9b | 1170 | dev = alloc_pci_dev(); |
1da177e4 LT |
1171 | if (!dev) |
1172 | return NULL; | |
1173 | ||
1da177e4 | 1174 | dev->bus = bus; |
1da177e4 | 1175 | dev->devfn = devfn; |
1da177e4 LT |
1176 | dev->vendor = l & 0xffff; |
1177 | dev->device = (l >> 16) & 0xffff; | |
cef354db | 1178 | |
480b93b7 | 1179 | if (pci_setup_device(dev)) { |
1da177e4 LT |
1180 | kfree(dev); |
1181 | return NULL; | |
1182 | } | |
1da177e4 LT |
1183 | |
1184 | return dev; | |
1185 | } | |
1186 | ||
201de56e ZY |
1187 | static void pci_init_capabilities(struct pci_dev *dev) |
1188 | { | |
1189 | /* MSI/MSI-X list */ | |
1190 | pci_msi_init_pci_dev(dev); | |
1191 | ||
63f4898a RW |
1192 | /* Buffers for saving PCIe and PCI-X capabilities */ |
1193 | pci_allocate_cap_save_buffers(dev); | |
1194 | ||
201de56e ZY |
1195 | /* Power Management */ |
1196 | pci_pm_init(dev); | |
eb9c39d0 | 1197 | platform_pci_wakeup_init(dev); |
201de56e ZY |
1198 | |
1199 | /* Vital Product Data */ | |
1200 | pci_vpd_pci22_init(dev); | |
58c3a727 YZ |
1201 | |
1202 | /* Alternative Routing-ID Forwarding */ | |
1203 | pci_enable_ari(dev); | |
d1b054da YZ |
1204 | |
1205 | /* Single Root I/O Virtualization */ | |
1206 | pci_iov_init(dev); | |
ae21ee65 AK |
1207 | |
1208 | /* Enable ACS P2P upstream forwarding */ | |
5d990b62 | 1209 | pci_enable_acs(dev); |
201de56e ZY |
1210 | } |
1211 | ||
96bde06a | 1212 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 1213 | { |
cdb9b9f7 PM |
1214 | device_initialize(&dev->dev); |
1215 | dev->dev.release = pci_release_dev; | |
1216 | pci_dev_get(dev); | |
1da177e4 | 1217 | |
cdb9b9f7 | 1218 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 1219 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 1220 | dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4 | 1221 | |
4d57cdfa | 1222 | pci_set_dma_max_seg_size(dev, 65536); |
59fc67de | 1223 | pci_set_dma_seg_boundary(dev, 0xffffffff); |
4d57cdfa | 1224 | |
1da177e4 LT |
1225 | /* Fix up broken headers */ |
1226 | pci_fixup_device(pci_fixup_header, dev); | |
1227 | ||
4b77b0a2 RW |
1228 | /* Clear the state_saved flag. */ |
1229 | dev->state_saved = false; | |
1230 | ||
201de56e ZY |
1231 | /* Initialize various capabilities */ |
1232 | pci_init_capabilities(dev); | |
eb9d0fe4 | 1233 | |
1da177e4 LT |
1234 | /* |
1235 | * Add the device to our list of discovered devices | |
1236 | * and the bus list for fixup functions, etc. | |
1237 | */ | |
d71374da | 1238 | down_write(&pci_bus_sem); |
1da177e4 | 1239 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 1240 | up_write(&pci_bus_sem); |
cdb9b9f7 PM |
1241 | } |
1242 | ||
451124a7 | 1243 | struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
1244 | { |
1245 | struct pci_dev *dev; | |
1246 | ||
90bdb311 TP |
1247 | dev = pci_get_slot(bus, devfn); |
1248 | if (dev) { | |
1249 | pci_dev_put(dev); | |
1250 | return dev; | |
1251 | } | |
1252 | ||
cdb9b9f7 PM |
1253 | dev = pci_scan_device(bus, devfn); |
1254 | if (!dev) | |
1255 | return NULL; | |
1256 | ||
1257 | pci_device_add(dev, bus); | |
1da177e4 LT |
1258 | |
1259 | return dev; | |
1260 | } | |
b73e9687 | 1261 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 | 1262 | |
f07852d6 MW |
1263 | static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn) |
1264 | { | |
1265 | u16 cap; | |
4fb88c1a MW |
1266 | unsigned pos, next_fn; |
1267 | ||
1268 | if (!dev) | |
1269 | return 0; | |
1270 | ||
1271 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); | |
f07852d6 MW |
1272 | if (!pos) |
1273 | return 0; | |
1274 | pci_read_config_word(dev, pos + 4, &cap); | |
4fb88c1a MW |
1275 | next_fn = cap >> 8; |
1276 | if (next_fn <= fn) | |
1277 | return 0; | |
1278 | return next_fn; | |
f07852d6 MW |
1279 | } |
1280 | ||
1281 | static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn) | |
1282 | { | |
1283 | return (fn + 1) % 8; | |
1284 | } | |
1285 | ||
1286 | static unsigned no_next_fn(struct pci_dev *dev, unsigned fn) | |
1287 | { | |
1288 | return 0; | |
1289 | } | |
1290 | ||
1291 | static int only_one_child(struct pci_bus *bus) | |
1292 | { | |
1293 | struct pci_dev *parent = bus->self; | |
1294 | if (!parent || !pci_is_pcie(parent)) | |
1295 | return 0; | |
1296 | if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT || | |
1297 | parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) | |
1298 | return 1; | |
1299 | return 0; | |
1300 | } | |
1301 | ||
1da177e4 LT |
1302 | /** |
1303 | * pci_scan_slot - scan a PCI slot on a bus for devices. | |
1304 | * @bus: PCI bus to scan | |
1305 | * @devfn: slot number to scan (must have zero function.) | |
1306 | * | |
1307 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
1308 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 1309 | * will not have is_added set. |
1b69dfc6 TP |
1310 | * |
1311 | * Returns the number of new devices found. | |
1da177e4 | 1312 | */ |
96bde06a | 1313 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 | 1314 | { |
f07852d6 | 1315 | unsigned fn, nr = 0; |
1b69dfc6 | 1316 | struct pci_dev *dev; |
f07852d6 MW |
1317 | unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn; |
1318 | ||
1319 | if (only_one_child(bus) && (devfn > 0)) | |
1320 | return 0; /* Already scanned the entire slot */ | |
1da177e4 | 1321 | |
1b69dfc6 | 1322 | dev = pci_scan_single_device(bus, devfn); |
4fb88c1a MW |
1323 | if (!dev) |
1324 | return 0; | |
1325 | if (!dev->is_added) | |
1b69dfc6 TP |
1326 | nr++; |
1327 | ||
f07852d6 MW |
1328 | if (pci_ari_enabled(bus)) |
1329 | next_fn = next_ari_fn; | |
4fb88c1a | 1330 | else if (dev->multifunction) |
f07852d6 MW |
1331 | next_fn = next_trad_fn; |
1332 | ||
1333 | for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) { | |
1334 | dev = pci_scan_single_device(bus, devfn + fn); | |
1335 | if (dev) { | |
1336 | if (!dev->is_added) | |
1337 | nr++; | |
1338 | dev->multifunction = 1; | |
1da177e4 LT |
1339 | } |
1340 | } | |
7d715a6c | 1341 | |
149e1637 SL |
1342 | /* only one slot has pcie device */ |
1343 | if (bus->self && nr) | |
7d715a6c SL |
1344 | pcie_aspm_init_link_state(bus->self); |
1345 | ||
1da177e4 LT |
1346 | return nr; |
1347 | } | |
1348 | ||
0ab2b57f | 1349 | unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) |
1da177e4 LT |
1350 | { |
1351 | unsigned int devfn, pass, max = bus->secondary; | |
1352 | struct pci_dev *dev; | |
1353 | ||
0207c356 | 1354 | dev_dbg(&bus->dev, "scanning bus\n"); |
1da177e4 LT |
1355 | |
1356 | /* Go find them, Rover! */ | |
1357 | for (devfn = 0; devfn < 0x100; devfn += 8) | |
1358 | pci_scan_slot(bus, devfn); | |
1359 | ||
a28724b0 YZ |
1360 | /* Reserve buses for SR-IOV capability. */ |
1361 | max += pci_iov_bus_range(bus); | |
1362 | ||
1da177e4 LT |
1363 | /* |
1364 | * After performing arch-dependent fixup of the bus, look behind | |
1365 | * all PCI-to-PCI bridges on this bus. | |
1366 | */ | |
74710ded | 1367 | if (!bus->is_added) { |
0207c356 | 1368 | dev_dbg(&bus->dev, "fixups for bus\n"); |
74710ded AC |
1369 | pcibios_fixup_bus(bus); |
1370 | if (pci_is_root_bus(bus)) | |
1371 | bus->is_added = 1; | |
1372 | } | |
1373 | ||
1da177e4 LT |
1374 | for (pass=0; pass < 2; pass++) |
1375 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1376 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1377 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1378 | max = pci_scan_bridge(bus, dev, max, pass); | |
1379 | } | |
1380 | ||
1381 | /* | |
1382 | * We've scanned the bus and so we know all about what's on | |
1383 | * the other side of any bridges that may be on this bus plus | |
1384 | * any devices. | |
1385 | * | |
1386 | * Return how far we've got finding sub-buses. | |
1387 | */ | |
0207c356 | 1388 | dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); |
1da177e4 LT |
1389 | return max; |
1390 | } | |
1391 | ||
96bde06a | 1392 | struct pci_bus * pci_create_bus(struct device *parent, |
cdb9b9f7 | 1393 | int bus, struct pci_ops *ops, void *sysdata) |
1da177e4 LT |
1394 | { |
1395 | int error; | |
0207c356 | 1396 | struct pci_bus *b, *b2; |
1da177e4 LT |
1397 | struct device *dev; |
1398 | ||
1399 | b = pci_alloc_bus(); | |
1400 | if (!b) | |
1401 | return NULL; | |
1402 | ||
6a3b3e26 | 1403 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
1da177e4 LT |
1404 | if (!dev){ |
1405 | kfree(b); | |
1406 | return NULL; | |
1407 | } | |
1408 | ||
1409 | b->sysdata = sysdata; | |
1410 | b->ops = ops; | |
1411 | ||
0207c356 BH |
1412 | b2 = pci_find_bus(pci_domain_nr(b), bus); |
1413 | if (b2) { | |
1da177e4 | 1414 | /* If we already got to this bus through a different bridge, ignore it */ |
0207c356 | 1415 | dev_dbg(&b2->dev, "bus already known\n"); |
1da177e4 LT |
1416 | goto err_out; |
1417 | } | |
d71374da ZY |
1418 | |
1419 | down_write(&pci_bus_sem); | |
1da177e4 | 1420 | list_add_tail(&b->node, &pci_root_buses); |
d71374da | 1421 | up_write(&pci_bus_sem); |
1da177e4 | 1422 | |
1da177e4 LT |
1423 | dev->parent = parent; |
1424 | dev->release = pci_release_bus_bridge_dev; | |
1a927133 | 1425 | dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus); |
1da177e4 LT |
1426 | error = device_register(dev); |
1427 | if (error) | |
1428 | goto dev_reg_err; | |
1429 | b->bridge = get_device(dev); | |
1430 | ||
0d358f22 YL |
1431 | if (!parent) |
1432 | set_dev_node(b->bridge, pcibus_to_node(b)); | |
1433 | ||
fd7d1ced GKH |
1434 | b->dev.class = &pcibus_class; |
1435 | b->dev.parent = b->bridge; | |
1a927133 | 1436 | dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); |
fd7d1ced | 1437 | error = device_register(&b->dev); |
1da177e4 LT |
1438 | if (error) |
1439 | goto class_dev_reg_err; | |
fd7d1ced | 1440 | error = device_create_file(&b->dev, &dev_attr_cpuaffinity); |
1da177e4 | 1441 | if (error) |
fd7d1ced | 1442 | goto dev_create_file_err; |
1da177e4 LT |
1443 | |
1444 | /* Create legacy_io and legacy_mem files for this bus */ | |
1445 | pci_create_legacy_files(b); | |
1446 | ||
1da177e4 LT |
1447 | b->number = b->secondary = bus; |
1448 | b->resource[0] = &ioport_resource; | |
1449 | b->resource[1] = &iomem_resource; | |
1450 | ||
1da177e4 LT |
1451 | return b; |
1452 | ||
fd7d1ced GKH |
1453 | dev_create_file_err: |
1454 | device_unregister(&b->dev); | |
1da177e4 LT |
1455 | class_dev_reg_err: |
1456 | device_unregister(dev); | |
1457 | dev_reg_err: | |
d71374da | 1458 | down_write(&pci_bus_sem); |
1da177e4 | 1459 | list_del(&b->node); |
d71374da | 1460 | up_write(&pci_bus_sem); |
1da177e4 LT |
1461 | err_out: |
1462 | kfree(dev); | |
1463 | kfree(b); | |
1464 | return NULL; | |
1465 | } | |
cdb9b9f7 | 1466 | |
0ab2b57f | 1467 | struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, |
cdb9b9f7 PM |
1468 | int bus, struct pci_ops *ops, void *sysdata) |
1469 | { | |
1470 | struct pci_bus *b; | |
1471 | ||
1472 | b = pci_create_bus(parent, bus, ops, sysdata); | |
1473 | if (b) | |
1474 | b->subordinate = pci_scan_child_bus(b); | |
1475 | return b; | |
1476 | } | |
1da177e4 LT |
1477 | EXPORT_SYMBOL(pci_scan_bus_parented); |
1478 | ||
1479 | #ifdef CONFIG_HOTPLUG | |
3ed4fd96 AC |
1480 | /** |
1481 | * pci_rescan_bus - scan a PCI bus for devices. | |
1482 | * @bus: PCI bus to scan | |
1483 | * | |
1484 | * Scan a PCI bus and child buses for new devices, adds them, | |
1485 | * and enables them. | |
1486 | * | |
1487 | * Returns the max number of subordinate bus discovered. | |
1488 | */ | |
5446a6bd | 1489 | unsigned int __ref pci_rescan_bus(struct pci_bus *bus) |
3ed4fd96 AC |
1490 | { |
1491 | unsigned int max; | |
1492 | struct pci_dev *dev; | |
1493 | ||
1494 | max = pci_scan_child_bus(bus); | |
1495 | ||
705b1aaa | 1496 | down_read(&pci_bus_sem); |
3ed4fd96 AC |
1497 | list_for_each_entry(dev, &bus->devices, bus_list) |
1498 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1499 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1500 | if (dev->subordinate) | |
1501 | pci_bus_size_bridges(dev->subordinate); | |
705b1aaa | 1502 | up_read(&pci_bus_sem); |
3ed4fd96 AC |
1503 | |
1504 | pci_bus_assign_resources(bus); | |
1505 | pci_enable_bridges(bus); | |
1506 | pci_bus_add_devices(bus); | |
1507 | ||
1508 | return max; | |
1509 | } | |
1510 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
1511 | ||
1da177e4 | 1512 | EXPORT_SYMBOL(pci_add_new_bus); |
1da177e4 LT |
1513 | EXPORT_SYMBOL(pci_scan_slot); |
1514 | EXPORT_SYMBOL(pci_scan_bridge); | |
1da177e4 LT |
1515 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1516 | #endif | |
6b4b78fe | 1517 | |
99178b03 | 1518 | static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) |
6b4b78fe | 1519 | { |
99178b03 GKH |
1520 | const struct pci_dev *a = to_pci_dev(d_a); |
1521 | const struct pci_dev *b = to_pci_dev(d_b); | |
1522 | ||
6b4b78fe MD |
1523 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; |
1524 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
1525 | ||
1526 | if (a->bus->number < b->bus->number) return -1; | |
1527 | else if (a->bus->number > b->bus->number) return 1; | |
1528 | ||
1529 | if (a->devfn < b->devfn) return -1; | |
1530 | else if (a->devfn > b->devfn) return 1; | |
1531 | ||
1532 | return 0; | |
1533 | } | |
1534 | ||
5ff580c1 | 1535 | void __init pci_sort_breadthfirst(void) |
6b4b78fe | 1536 | { |
99178b03 | 1537 | bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
6b4b78fe | 1538 | } |