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f5fc0f86 LC |
1 | /* |
2 | * This file is part of wl1271 | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * | |
6 | * Contact: Luciano Coelho <luciano.coelho@nokia.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
5a0e3ad6 TH |
24 | #include <linux/gfp.h> |
25 | ||
f5fc0f86 LC |
26 | #include "wl1271.h" |
27 | #include "wl1271_acx.h" | |
28 | #include "wl1271_reg.h" | |
29 | #include "wl1271_rx.h" | |
30 | #include "wl1271_spi.h" | |
7b048c52 | 31 | #include "wl1271_io.h" |
f5fc0f86 LC |
32 | |
33 | static u8 wl1271_rx_get_mem_block(struct wl1271_fw_status *status, | |
34 | u32 drv_rx_counter) | |
35 | { | |
d0f63b20 LC |
36 | return le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]) & |
37 | RX_MEM_BLOCK_MASK; | |
f5fc0f86 LC |
38 | } |
39 | ||
40 | static u32 wl1271_rx_get_buf_size(struct wl1271_fw_status *status, | |
41 | u32 drv_rx_counter) | |
42 | { | |
d0f63b20 LC |
43 | return (le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]) & |
44 | RX_BUF_SIZE_MASK) >> RX_BUF_SIZE_SHIFT_DIV; | |
f5fc0f86 LC |
45 | } |
46 | ||
47 | /* The values of this table must match the wl1271_rates[] array */ | |
48 | static u8 wl1271_rx_rate_to_idx[] = { | |
49 | /* MCS rates are used only with 11n */ | |
50 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS7 */ | |
51 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS6 */ | |
52 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS5 */ | |
53 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS4 */ | |
54 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS3 */ | |
55 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS2 */ | |
56 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS1 */ | |
57 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS0 */ | |
58 | ||
59 | 11, /* WL1271_RATE_54 */ | |
60 | 10, /* WL1271_RATE_48 */ | |
61 | 9, /* WL1271_RATE_36 */ | |
62 | 8, /* WL1271_RATE_24 */ | |
63 | ||
64 | /* TI-specific rate */ | |
65 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_22 */ | |
66 | ||
67 | 7, /* WL1271_RATE_18 */ | |
68 | 6, /* WL1271_RATE_12 */ | |
69 | 3, /* WL1271_RATE_11 */ | |
70 | 5, /* WL1271_RATE_9 */ | |
71 | 4, /* WL1271_RATE_6 */ | |
72 | 2, /* WL1271_RATE_5_5 */ | |
73 | 1, /* WL1271_RATE_2 */ | |
74 | 0 /* WL1271_RATE_1 */ | |
75 | }; | |
76 | ||
a4102645 TP |
77 | /* The values of this table must match the wl1271_rates[] array */ |
78 | static u8 wl1271_5_ghz_rx_rate_to_idx[] = { | |
79 | /* MCS rates are used only with 11n */ | |
80 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS7 */ | |
81 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS6 */ | |
82 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS5 */ | |
83 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS4 */ | |
84 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS3 */ | |
85 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS2 */ | |
86 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS1 */ | |
87 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_MCS0 */ | |
88 | ||
89 | 7, /* WL1271_RATE_54 */ | |
90 | 6, /* WL1271_RATE_48 */ | |
91 | 5, /* WL1271_RATE_36 */ | |
92 | 4, /* WL1271_RATE_24 */ | |
93 | ||
94 | /* TI-specific rate */ | |
95 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_22 */ | |
96 | ||
97 | 3, /* WL1271_RATE_18 */ | |
98 | 2, /* WL1271_RATE_12 */ | |
99 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_11 */ | |
100 | 1, /* WL1271_RATE_9 */ | |
101 | 0, /* WL1271_RATE_6 */ | |
102 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_5_5 */ | |
103 | WL1271_RX_RATE_UNSUPPORTED, /* WL1271_RATE_2 */ | |
104 | WL1271_RX_RATE_UNSUPPORTED /* WL1271_RATE_1 */ | |
105 | }; | |
106 | ||
f5fc0f86 LC |
107 | static void wl1271_rx_status(struct wl1271 *wl, |
108 | struct wl1271_rx_descriptor *desc, | |
109 | struct ieee80211_rx_status *status, | |
110 | u8 beacon) | |
111 | { | |
112 | memset(status, 0, sizeof(struct ieee80211_rx_status)); | |
113 | ||
a4102645 TP |
114 | if ((desc->flags & WL1271_RX_DESC_BAND_MASK) == |
115 | WL1271_RX_DESC_BAND_BG) { | |
f5fc0f86 | 116 | status->band = IEEE80211_BAND_2GHZ; |
a4102645 TP |
117 | status->rate_idx = wl1271_rx_rate_to_idx[desc->rate]; |
118 | } else if ((desc->flags & WL1271_RX_DESC_BAND_MASK) == | |
119 | WL1271_RX_DESC_BAND_A) { | |
abb0b3bf | 120 | status->band = IEEE80211_BAND_5GHZ; |
a4102645 TP |
121 | status->rate_idx = wl1271_5_ghz_rx_rate_to_idx[desc->rate]; |
122 | } else | |
f5fc0f86 LC |
123 | wl1271_warning("unsupported band 0x%x", |
124 | desc->flags & WL1271_RX_DESC_BAND_MASK); | |
125 | ||
a4102645 TP |
126 | if (unlikely(status->rate_idx == WL1271_RX_RATE_UNSUPPORTED)) |
127 | wl1271_warning("unsupported rate"); | |
128 | ||
f5fc0f86 LC |
129 | /* |
130 | * FIXME: Add mactime handling. For IBSS (ad-hoc) we need to get the | |
131 | * timestamp from the beacon (acx_tsf_info). In BSS mode (infra) we | |
132 | * only need the mactime for monitor mode. For now the mactime is | |
133 | * not valid, so RX_FLAG_TSFT should not be set | |
134 | */ | |
135 | status->signal = desc->rssi; | |
136 | ||
f5fc0f86 LC |
137 | /* |
138 | * FIXME: In wl1251, the SNR should be divided by two. In wl1271 we | |
139 | * need to divide by two for now, but TI has been discussing about | |
140 | * changing it. This needs to be rechecked. | |
141 | */ | |
142 | status->noise = desc->rssi - (desc->snr >> 1); | |
143 | ||
144 | status->freq = ieee80211_channel_to_frequency(desc->channel); | |
145 | ||
146 | if (desc->flags & WL1271_RX_DESC_ENCRYPT_MASK) { | |
147 | status->flag |= RX_FLAG_IV_STRIPPED | RX_FLAG_MMIC_STRIPPED; | |
148 | ||
5d07b668 | 149 | if (likely(!(desc->status & WL1271_RX_DESC_DECRYPT_FAIL))) |
f5fc0f86 | 150 | status->flag |= RX_FLAG_DECRYPTED; |
5d07b668 TP |
151 | if (unlikely(desc->status & WL1271_RX_DESC_MIC_FAIL)) |
152 | status->flag |= RX_FLAG_MMIC_ERROR; | |
f5fc0f86 | 153 | } |
f5fc0f86 LC |
154 | } |
155 | ||
156 | static void wl1271_rx_handle_data(struct wl1271 *wl, u32 length) | |
157 | { | |
158 | struct ieee80211_rx_status rx_status; | |
159 | struct wl1271_rx_descriptor *desc; | |
160 | struct sk_buff *skb; | |
161 | u16 *fc; | |
162 | u8 *buf; | |
163 | u8 beacon = 0; | |
164 | ||
e9a6269d | 165 | skb = __dev_alloc_skb(length, GFP_KERNEL); |
f5fc0f86 LC |
166 | if (!skb) { |
167 | wl1271_error("Couldn't allocate RX frame"); | |
168 | return; | |
169 | } | |
170 | ||
171 | buf = skb_put(skb, length); | |
7b048c52 | 172 | wl1271_read(wl, WL1271_SLV_MEM_DATA, buf, length, true); |
f5fc0f86 LC |
173 | |
174 | /* the data read starts with the descriptor */ | |
175 | desc = (struct wl1271_rx_descriptor *) buf; | |
176 | ||
177 | /* now we pull the descriptor out of the buffer */ | |
178 | skb_pull(skb, sizeof(*desc)); | |
179 | ||
180 | fc = (u16 *)skb->data; | |
181 | if ((*fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_BEACON) | |
182 | beacon = 1; | |
183 | ||
184 | wl1271_rx_status(wl, desc, &rx_status, beacon); | |
185 | ||
186 | wl1271_debug(DEBUG_RX, "rx skb 0x%p: %d B %s", skb, skb->len, | |
187 | beacon ? "beacon" : ""); | |
188 | ||
189 | memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status)); | |
287d3741 | 190 | ieee80211_rx_ni(wl->hw, skb); |
f5fc0f86 LC |
191 | } |
192 | ||
193 | void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_status *status) | |
194 | { | |
195 | struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map; | |
196 | u32 buf_size; | |
197 | u32 fw_rx_counter = status->fw_rx_counter & NUM_RX_PKT_DESC_MOD_MASK; | |
198 | u32 drv_rx_counter = wl->rx_counter & NUM_RX_PKT_DESC_MOD_MASK; | |
199 | u32 mem_block; | |
200 | ||
201 | while (drv_rx_counter != fw_rx_counter) { | |
202 | mem_block = wl1271_rx_get_mem_block(status, drv_rx_counter); | |
203 | buf_size = wl1271_rx_get_buf_size(status, drv_rx_counter); | |
204 | ||
205 | if (buf_size == 0) { | |
206 | wl1271_warning("received empty data"); | |
207 | break; | |
208 | } | |
209 | ||
d0f63b20 LC |
210 | wl->rx_mem_pool_addr.addr = (mem_block << 8) + |
211 | le32_to_cpu(wl_mem_map->packet_memory_pool_start); | |
f5fc0f86 LC |
212 | wl->rx_mem_pool_addr.addr_extra = |
213 | wl->rx_mem_pool_addr.addr + 4; | |
214 | ||
215 | /* Choose the block we want to read */ | |
7b048c52 TP |
216 | wl1271_write(wl, WL1271_SLV_REG_DATA, &wl->rx_mem_pool_addr, |
217 | sizeof(wl->rx_mem_pool_addr), false); | |
f5fc0f86 LC |
218 | |
219 | wl1271_rx_handle_data(wl, buf_size); | |
220 | ||
221 | wl->rx_counter++; | |
222 | drv_rx_counter = wl->rx_counter & NUM_RX_PKT_DESC_MOD_MASK; | |
7b048c52 | 223 | wl1271_write32(wl, RX_DRIVER_COUNTER_ADDRESS, wl->rx_counter); |
f5fc0f86 | 224 | } |
f5fc0f86 | 225 | } |