[net-next-2.6.git] / drivers / net / wireless / wl12xx / wl1251_boot.c

/*
 * This file is part of wl1251
 *
 * Copyright (C) 2008 Nokia Corporation
 *
 * Contact: Kalle Valo <kalle.valo@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/gpio.h>
#include <linux/slab.h>

#include "wl1251_reg.h"
#include "wl1251_boot.h"
#include "wl1251_io.h"
#include "wl1251_spi.h"
#include "wl1251_event.h"
#include "wl1251_acx.h"

void wl1251_boot_target_enable_interrupts(struct wl1251 *wl)
{
	wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
	wl1251_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
}

int wl1251_boot_soft_reset(struct wl1251 *wl)
{
	unsigned long timeout;
	u32 boot_data;

	/* perform soft reset */
	wl1251_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);

	/* SOFT_RESET is self clearing */
	timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
	while (1) {
		boot_data = wl1251_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
		wl1251_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
		if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
			break;

		if (time_after(jiffies, timeout)) {
			/* 1.2 check pWhalBus->uSelfClearTime if the
			 * timeout was reached */
			wl1251_error("soft reset timeout");
			return -1;
		}

		udelay(SOFT_RESET_STALL_TIME);
	}

	/* disable Rx/Tx */
	wl1251_reg_write32(wl, ENABLE, 0x0);

	/* disable auto calibration on start*/
	wl1251_reg_write32(wl, SPARE_A2, 0xffff);

	return 0;
}

int wl1251_boot_init_seq(struct wl1251 *wl)
{
	u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq;

	/*
	 * col #1: INTEGER_DIVIDER
	 * col #2: FRACTIONAL_DIVIDER
	 * col #3: ATTN_BB
	 * col #4: ALPHA_BB
	 * col #5: STOP_TIME_BB
	 * col #6: BB_PLL_LOOP_FILTER
	 */
	static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = {

		{   83, 87381,  0xB, 5, 0xF00,  3}, /* REF_FREQ_19_2*/
		{   61, 141154, 0xB, 5, 0x1450, 2}, /* REF_FREQ_26_0*/
		{   41, 174763, 0xC, 6, 0x2D00, 1}, /* REF_FREQ_38_4*/
		{   40, 0,      0xC, 6, 0x2EE0, 1}, /* REF_FREQ_40_0*/
		{   47, 162280, 0xC, 6, 0x2760, 1}  /* REF_FREQ_33_6        */
	};

	/* read NVS params */
	scr_pad6 = wl1251_reg_read32(wl, SCR_PAD6);
	wl1251_debug(DEBUG_BOOT, "scr_pad6 0x%x", scr_pad6);

	/* read ELP_CMD */
	elp_cmd = wl1251_reg_read32(wl, ELP_CMD);
	wl1251_debug(DEBUG_BOOT, "elp_cmd 0x%x", elp_cmd);

	/* set the BB calibration time to be 300 usec (PLL_CAL_TIME) */
	ref_freq = scr_pad6 & 0x000000FF;
	wl1251_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq);

	wl1251_reg_write32(wl, PLL_CAL_TIME, 0x9);

	/*
	 * PG 1.2: set the clock buffer time to be 210 usec (CLK_BUF_TIME)
	 */
	wl1251_reg_write32(wl, CLK_BUF_TIME, 0x6);

	/*
	 * set the clock detect feature to work in the restart wu procedure
	 * (ELP_CFG_MODE[14]) and Select the clock source type
	 * (ELP_CFG_MODE[13:12])
	 */
	tmp = ((scr_pad6 & 0x0000FF00) << 4) | 0x00004000;
	wl1251_reg_write32(wl, ELP_CFG_MODE, tmp);

	/* PG 1.2: enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */
	elp_cmd |= 0x00000040;
	wl1251_reg_write32(wl, ELP_CMD, elp_cmd);

	/* PG 1.2: Set the BB PLL stable time to be 1000usec
	 * (PLL_STABLE_TIME) */
	wl1251_reg_write32(wl, CFG_PLL_SYNC_CNT, 0x20);

	/* PG 1.2: read clock request time */
	init_data = wl1251_reg_read32(wl, CLK_REQ_TIME);

	/*
	 * PG 1.2: set the clock request time to be ref_clk_settling_time -
	 * 1ms = 4ms
	 */
	if (init_data > 0x21)
		tmp = init_data - 0x21;
	else
		tmp = 0;
	wl1251_reg_write32(wl, CLK_REQ_TIME, tmp);

	/* set BB PLL configurations in RF AFE */
	wl1251_reg_write32(wl, 0x003058cc, 0x4B5);

	/* set RF_AFE_REG_5 */
	wl1251_reg_write32(wl, 0x003058d4, 0x50);

	/* set RF_AFE_CTRL_REG_2 */
	wl1251_reg_write32(wl, 0x00305948, 0x11c001);

	/*
	 * change RF PLL and BB PLL divider for VCO clock and adjust VCO
	 * bais current(RF_AFE_REG_13)
	 */
	wl1251_reg_write32(wl, 0x003058f4, 0x1e);

	/* set BB PLL configurations */
	tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000;
	wl1251_reg_write32(wl, 0x00305840, tmp);

	/* set fractional divider according to Appendix C-BB PLL
	 * Calculations
	 */
	tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER];
	wl1251_reg_write32(wl, 0x00305844, tmp);

	/* set the initial data for the sigma delta */
	wl1251_reg_write32(wl, 0x00305848, 0x3039);

	/*
	 * set the accumulator attenuation value, calibration loop1
	 * (alpha), calibration loop2 (beta), calibration loop3 (gamma) and
	 * the VCO gain
	 */
	tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) |
		(LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1;
	wl1251_reg_write32(wl, 0x00305854, tmp);

	/*
	 * set the calibration stop time after holdoff time expires and set
	 * settling time HOLD_OFF_TIME_BB
	 */
	tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000;
	wl1251_reg_write32(wl, 0x00305858, tmp);

	/*
	 * set BB PLL Loop filter capacitor3- BB_C3[2:0] and set BB PLL
	 * constant leakage current to linearize PFD to 0uA -
	 * BB_ILOOPF[7:3]
	 */
	tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030;
	wl1251_reg_write32(wl, 0x003058f8, tmp);

	/*
	 * set regulator output voltage for n divider to
	 * 1.35-BB_REFDIV[1:0], set charge pump current- BB_CPGAIN[4:2],
	 * set BB PLL Loop filter capacitor2- BB_C2[7:5], set gain of BB
	 * PLL auto-call to normal mode- BB_CALGAIN_3DB[8]
	 */
	wl1251_reg_write32(wl, 0x003058f0, 0x29);

	/* enable restart wakeup sequence (ELP_CMD[0]) */
	wl1251_reg_write32(wl, ELP_CMD, elp_cmd | 0x1);

	/* restart sequence completed */
	udelay(2000);

	return 0;
}

static void wl1251_boot_set_ecpu_ctrl(struct wl1251 *wl, u32 flag)
{
	u32 cpu_ctrl;

	/* 10.5.0 run the firmware (I) */
	cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);

	/* 10.5.1 run the firmware (II) */
	cpu_ctrl &= ~flag;
	wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
}

int wl1251_boot_run_firmware(struct wl1251 *wl)
{
	int loop, ret;
	u32 chip_id, interrupt;

	wl1251_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);

	chip_id = wl1251_reg_read32(wl, CHIP_ID_B);

	wl1251_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);

	if (chip_id != wl->chip_id) {
		wl1251_error("chip id doesn't match after firmware boot");
		return -EIO;
	}

	/* wait for init to complete */
	loop = 0;
	while (loop++ < INIT_LOOP) {
		udelay(INIT_LOOP_DELAY);
		interrupt = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);

		if (interrupt == 0xffffffff) {
			wl1251_error("error reading hardware complete "
				     "init indication");
			return -EIO;
		}
		/* check that ACX_INTR_INIT_COMPLETE is enabled */
		else if (interrupt & WL1251_ACX_INTR_INIT_COMPLETE) {
			wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
					   WL1251_ACX_INTR_INIT_COMPLETE);
			break;
		}
	}

	if (loop > INIT_LOOP) {
		wl1251_error("timeout waiting for the hardware to "
			     "complete initialization");
		return -EIO;
	}

	/* get hardware config command mail box */
	wl->cmd_box_addr = wl1251_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);

	/* get hardware config event mail box */
	wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR);

	/* set the working partition to its "running" mode offset */
	wl1251_set_partition(wl, WL1251_PART_WORK_MEM_START,
			     WL1251_PART_WORK_MEM_SIZE,
			     WL1251_PART_WORK_REG_START,
			     WL1251_PART_WORK_REG_SIZE);

	wl1251_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
		     wl->cmd_box_addr, wl->event_box_addr);

	wl1251_acx_fw_version(wl, wl->fw_ver, sizeof(wl->fw_ver));

	/*
	 * in case of full asynchronous mode the firmware event must be
	 * ready to receive event from the command mailbox
	 */

	/* enable gpio interrupts */
	wl1251_enable_interrupts(wl);

	/* Enable target's interrupts */
	wl->intr_mask = WL1251_ACX_INTR_RX0_DATA |
		WL1251_ACX_INTR_RX1_DATA |
		WL1251_ACX_INTR_TX_RESULT |
		WL1251_ACX_INTR_EVENT_A |
		WL1251_ACX_INTR_EVENT_B |
		WL1251_ACX_INTR_INIT_COMPLETE;
	wl1251_boot_target_enable_interrupts(wl);

	wl->event_mask = SCAN_COMPLETE_EVENT_ID | BSS_LOSE_EVENT_ID |
		SYNCHRONIZATION_TIMEOUT_EVENT_ID |
		ROAMING_TRIGGER_LOW_RSSI_EVENT_ID |
		ROAMING_TRIGGER_REGAINED_RSSI_EVENT_ID |
		REGAINED_BSS_EVENT_ID | BT_PTA_SENSE_EVENT_ID |
		BT_PTA_PREDICTION_EVENT_ID;

	ret = wl1251_event_unmask(wl);
	if (ret < 0) {
		wl1251_error("EVENT mask setting failed");
		return ret;
	}

	wl1251_event_mbox_config(wl);

	/* firmware startup completed */
	return 0;
}

static int wl1251_boot_upload_firmware(struct wl1251 *wl)
{
	int addr, chunk_num, partition_limit;
	size_t fw_data_len, len;
	u8 *p, *buf;

	/* whal_FwCtrl_LoadFwImageSm() */

	wl1251_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x",
		     wl1251_reg_read32(wl, CHIP_ID_B));

	/* 10.0 check firmware length and set partition */
	fw_data_len =  (wl->fw[4] << 24) | (wl->fw[5] << 16) |
		(wl->fw[6] << 8) | (wl->fw[7]);

	wl1251_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len,
		CHUNK_SIZE);

	if ((fw_data_len % 4) != 0) {
		wl1251_error("firmware length not multiple of four");
		return -EIO;
	}

	buf = kmalloc(CHUNK_SIZE, GFP_KERNEL);
	if (!buf) {
		wl1251_error("allocation for firmware upload chunk failed");
		return -ENOMEM;
	}

	wl1251_set_partition(wl, WL1251_PART_DOWN_MEM_START,
			     WL1251_PART_DOWN_MEM_SIZE,
			     WL1251_PART_DOWN_REG_START,
			     WL1251_PART_DOWN_REG_SIZE);

	/* 10.1 set partition limit and chunk num */
	chunk_num = 0;
	partition_limit = WL1251_PART_DOWN_MEM_SIZE;

	while (chunk_num < fw_data_len / CHUNK_SIZE) {
		/* 10.2 update partition, if needed */
		addr = WL1251_PART_DOWN_MEM_START +
			(chunk_num + 2) * CHUNK_SIZE;
		if (addr > partition_limit) {
			addr = WL1251_PART_DOWN_MEM_START +
				chunk_num * CHUNK_SIZE;
			partition_limit = chunk_num * CHUNK_SIZE +
				WL1251_PART_DOWN_MEM_SIZE;
			wl1251_set_partition(wl,
					     addr,
					     WL1251_PART_DOWN_MEM_SIZE,
					     WL1251_PART_DOWN_REG_START,
					     WL1251_PART_DOWN_REG_SIZE);
		}

		/* 10.3 upload the chunk */
		addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
		p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
		wl1251_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
			     p, addr);

		/* need to copy the chunk for dma */
		len = CHUNK_SIZE;
		memcpy(buf, p, len);
		wl1251_mem_write(wl, addr, buf, len);

		chunk_num++;
	}

	/* 10.4 upload the last chunk */
	addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
	p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;

	/* need to copy the chunk for dma */
	len = fw_data_len % CHUNK_SIZE;
	memcpy(buf, p, len);

	wl1251_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x",
		     len, p, addr);
	wl1251_mem_write(wl, addr, buf, len);

	kfree(buf);

	return 0;
}

static int wl1251_boot_upload_nvs(struct wl1251 *wl)
{
	size_t nvs_len, nvs_bytes_written, burst_len;
	int nvs_start, i;
	u32 dest_addr, val;
	u8 *nvs_ptr, *nvs;

	nvs = wl->nvs;
	if (nvs == NULL)
		return -ENODEV;

	nvs_ptr = nvs;

	nvs_len = wl->nvs_len;
	nvs_start = wl->fw_len;

	/*
	 * Layout before the actual NVS tables:
	 * 1 byte : burst length.
	 * 2 bytes: destination address.
	 * n bytes: data to burst copy.
	 *
	 * This is ended by a 0 length, then the NVS tables.
	 */

	while (nvs_ptr[0]) {
		burst_len = nvs_ptr[0];
		dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));

		/* We move our pointer to the data */
		nvs_ptr += 3;

		for (i = 0; i < burst_len; i++) {
			val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
			       | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));

			wl1251_debug(DEBUG_BOOT,
				     "nvs burst write 0x%x: 0x%x",
				     dest_addr, val);
			wl1251_mem_write32(wl, dest_addr, val);

			nvs_ptr += 4;
			dest_addr += 4;
		}
	}

	/*
	 * We've reached the first zero length, the first NVS table
	 * is 7 bytes further.
	 */
	nvs_ptr += 7;
	nvs_len -= nvs_ptr - nvs;
	nvs_len = ALIGN(nvs_len, 4);

	/* Now we must set the partition correctly */
	wl1251_set_partition(wl, nvs_start,
			     WL1251_PART_DOWN_MEM_SIZE,
			     WL1251_PART_DOWN_REG_START,
			     WL1251_PART_DOWN_REG_SIZE);

	/* And finally we upload the NVS tables */
	nvs_bytes_written = 0;
	while (nvs_bytes_written < nvs_len) {
		val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
		       | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));

		val = cpu_to_le32(val);

		wl1251_debug(DEBUG_BOOT,
			     "nvs write table 0x%x: 0x%x",
			     nvs_start, val);
		wl1251_mem_write32(wl, nvs_start, val);

		nvs_ptr += 4;
		nvs_bytes_written += 4;
		nvs_start += 4;
	}

	return 0;
}

int wl1251_boot(struct wl1251 *wl)
{
	int ret = 0, minor_minor_e2_ver;
	u32 tmp, boot_data;

	/* halt embedded ARM CPU while loading firmware */
	wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, ECPU_CONTROL_HALT);

	ret = wl1251_boot_soft_reset(wl);
	if (ret < 0)
		goto out;

	/* 2. start processing NVS file */
	if (wl->use_eeprom) {
		wl1251_reg_write32(wl, ACX_REG_EE_START, START_EEPROM_MGR);
		msleep(4000);
		wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, USE_EEPROM);
	} else {
		ret = wl1251_boot_upload_nvs(wl);
		if (ret < 0)
			goto out;

		/* write firmware's last address (ie. it's length) to
		 * ACX_EEPROMLESS_IND_REG */
		wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len);
	}

	/* 6. read the EEPROM parameters */
	tmp = wl1251_reg_read32(wl, SCR_PAD2);

	/* 7. read bootdata */
	wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8;
	wl->boot_attr.major = (tmp & 0x00FF0000) >> 16;
	tmp = wl1251_reg_read32(wl, SCR_PAD3);

	/* 8. check bootdata and call restart sequence */
	wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16;
	minor_minor_e2_ver = (tmp & 0xFF000000) >> 24;

	wl1251_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x "
		     "minorE2Ver 0x%x minor_minor_e2_ver 0x%x",
		     wl->boot_attr.radio_type, wl->boot_attr.major,
		     wl->boot_attr.minor, minor_minor_e2_ver);

	ret = wl1251_boot_init_seq(wl);
	if (ret < 0)
		goto out;

	/* 9. NVS processing done */
	boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);

	wl1251_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data);

	/* 10. check that ECPU_CONTROL_HALT bits are set in
	 * pWhalBus->uBootData and start uploading firmware
	 */
	if ((boot_data & ECPU_CONTROL_HALT) == 0) {
		wl1251_error("boot failed, ECPU_CONTROL_HALT not set");
		ret = -EIO;
		goto out;
	}

	ret = wl1251_boot_upload_firmware(wl);
	if (ret < 0)
		goto out;

	/* 10.5 start firmware */
	ret = wl1251_boot_run_firmware(wl);
	if (ret < 0)
		goto out;

out:
	return ret;
}
Commit	Line	Data
2f01a1f5	1	/*
80301cdc	2	* This file is part of wl1251
2f01a1f5 KV	3	*
	4	* Copyright (C) 2008 Nokia Corporation
	5	*
	6	* Contact: Kalle Valo <kalle.valo@nokia.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*
	22	*/
	23
	24	#include <linux/gpio.h>
5a0e3ad6	25	#include <linux/slab.h>
2f01a1f5	26
29d904c4	27	#include "wl1251_reg.h"
ef2f8d45	28	#include "wl1251_boot.h"
0764de64	29	#include "wl1251_io.h"
08d9f572	30	#include "wl1251_spi.h"
ef2f8d45	31	#include "wl1251_event.h"
0e71bb08	32	#include "wl1251_acx.h"
2f01a1f5	33
80301cdc	34	void wl1251_boot_target_enable_interrupts(struct wl1251 *wl)
2f01a1f5	35	{
80301cdc KV	36	wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
80301cdc KV	37	wl1251_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
2f01a1f5 KV	38	}
2f01a1f5 KV	39
80301cdc	40	int wl1251_boot_soft_reset(struct wl1251 *wl)
2f01a1f5 KV	41	{
	42	unsigned long timeout;
	43	u32 boot_data;
	44
	45	/* perform soft reset */
80301cdc	46	wl1251_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
2f01a1f5 KV	47
	48	/* SOFT_RESET is self clearing */
	49	timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
	50	while (1) {
80301cdc KV	51	boot_data = wl1251_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
80301cdc KV	52	wl1251_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
2f01a1f5 KV	53	if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
	54	break;
	55
	56	if (time_after(jiffies, timeout)) {
	57	/* 1.2 check pWhalBus->uSelfClearTime if the
	58	* timeout was reached */
80301cdc	59	wl1251_error("soft reset timeout");
2f01a1f5 KV	60	return -1;
	61	}
	62
	63	udelay(SOFT_RESET_STALL_TIME);
	64	}
	65
	66	/* disable Rx/Tx */
80301cdc	67	wl1251_reg_write32(wl, ENABLE, 0x0);
2f01a1f5 KV	68
2f01a1f5 KV	69	/* disable auto calibration on start*/
80301cdc	70	wl1251_reg_write32(wl, SPARE_A2, 0xffff);
2f01a1f5 KV	71
	72	return 0;
	73	}
	74
80301cdc	75	int wl1251_boot_init_seq(struct wl1251 *wl)
2f01a1f5 KV	76	{
	77	u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq;
	78
	79	/*
	80	* col #1: INTEGER_DIVIDER
	81	* col #2: FRACTIONAL_DIVIDER
	82	* col #3: ATTN_BB
	83	* col #4: ALPHA_BB
	84	* col #5: STOP_TIME_BB
	85	* col #6: BB_PLL_LOOP_FILTER
	86	*/
	87	static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = {
	88
	89	{ 83, 87381, 0xB, 5, 0xF00, 3}, /* REF_FREQ_19_2*/
	90	{ 61, 141154, 0xB, 5, 0x1450, 2}, /* REF_FREQ_26_0*/
	91	{ 41, 174763, 0xC, 6, 0x2D00, 1}, /* REF_FREQ_38_4*/
	92	{ 40, 0, 0xC, 6, 0x2EE0, 1}, /* REF_FREQ_40_0*/
	93	{ 47, 162280, 0xC, 6, 0x2760, 1} /* REF_FREQ_33_6 */
	94	};
	95
	96	/* read NVS params */
80301cdc KV	97	scr_pad6 = wl1251_reg_read32(wl, SCR_PAD6);
80301cdc KV	98	wl1251_debug(DEBUG_BOOT, "scr_pad6 0x%x", scr_pad6);
2f01a1f5 KV	99
2f01a1f5 KV	100	/* read ELP_CMD */
80301cdc KV	101	elp_cmd = wl1251_reg_read32(wl, ELP_CMD);
80301cdc KV	102	wl1251_debug(DEBUG_BOOT, "elp_cmd 0x%x", elp_cmd);
2f01a1f5 KV	103
	104	/* set the BB calibration time to be 300 usec (PLL_CAL_TIME) */
	105	ref_freq = scr_pad6 & 0x000000FF;
80301cdc	106	wl1251_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq);
2f01a1f5	107
80301cdc	108	wl1251_reg_write32(wl, PLL_CAL_TIME, 0x9);
2f01a1f5 KV	109
	110	/*
	111	* PG 1.2: set the clock buffer time to be 210 usec (CLK_BUF_TIME)
	112	*/
80301cdc	113	wl1251_reg_write32(wl, CLK_BUF_TIME, 0x6);
2f01a1f5 KV	114
	115	/*
	116	* set the clock detect feature to work in the restart wu procedure
	117	* (ELP_CFG_MODE[14]) and Select the clock source type
	118	* (ELP_CFG_MODE[13:12])
	119	*/
	120	tmp = ((scr_pad6 & 0x0000FF00) << 4) \| 0x00004000;
80301cdc	121	wl1251_reg_write32(wl, ELP_CFG_MODE, tmp);
2f01a1f5 KV	122
	123	/* PG 1.2: enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */
	124	elp_cmd \|= 0x00000040;
80301cdc	125	wl1251_reg_write32(wl, ELP_CMD, elp_cmd);
2f01a1f5 KV	126
	127	/* PG 1.2: Set the BB PLL stable time to be 1000usec
	128	* (PLL_STABLE_TIME) */
80301cdc	129	wl1251_reg_write32(wl, CFG_PLL_SYNC_CNT, 0x20);
2f01a1f5 KV	130
2f01a1f5 KV	131	/* PG 1.2: read clock request time */
80301cdc	132	init_data = wl1251_reg_read32(wl, CLK_REQ_TIME);
2f01a1f5 KV	133
	134	/*
	135	* PG 1.2: set the clock request time to be ref_clk_settling_time -
	136	* 1ms = 4ms
	137	*/
	138	if (init_data > 0x21)
	139	tmp = init_data - 0x21;
	140	else
	141	tmp = 0;
80301cdc	142	wl1251_reg_write32(wl, CLK_REQ_TIME, tmp);
2f01a1f5 KV	143
2f01a1f5 KV	144	/* set BB PLL configurations in RF AFE */
80301cdc	145	wl1251_reg_write32(wl, 0x003058cc, 0x4B5);
2f01a1f5 KV	146
2f01a1f5 KV	147	/* set RF_AFE_REG_5 */
80301cdc	148	wl1251_reg_write32(wl, 0x003058d4, 0x50);
2f01a1f5 KV	149
2f01a1f5 KV	150	/* set RF_AFE_CTRL_REG_2 */
80301cdc	151	wl1251_reg_write32(wl, 0x00305948, 0x11c001);
2f01a1f5 KV	152
	153	/*
	154	* change RF PLL and BB PLL divider for VCO clock and adjust VCO
	155	* bais current(RF_AFE_REG_13)
	156	*/
80301cdc	157	wl1251_reg_write32(wl, 0x003058f4, 0x1e);
2f01a1f5 KV	158
	159	/* set BB PLL configurations */
	160	tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] \| 0x00017000;
80301cdc	161	wl1251_reg_write32(wl, 0x00305840, tmp);
2f01a1f5 KV	162
	163	/* set fractional divider according to Appendix C-BB PLL
	164	* Calculations
	165	*/
	166	tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER];
80301cdc	167	wl1251_reg_write32(wl, 0x00305844, tmp);
2f01a1f5 KV	168
2f01a1f5 KV	169	/* set the initial data for the sigma delta */
80301cdc	170	wl1251_reg_write32(wl, 0x00305848, 0x3039);
2f01a1f5 KV	171
	172	/*
	173	* set the accumulator attenuation value, calibration loop1
	174	* (alpha), calibration loop2 (beta), calibration loop3 (gamma) and
	175	* the VCO gain
	176	*/
	177	tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) \|
	178	(LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) \| 0x1;
80301cdc	179	wl1251_reg_write32(wl, 0x00305854, tmp);
2f01a1f5 KV	180
	181	/*
	182	* set the calibration stop time after holdoff time expires and set
	183	* settling time HOLD_OFF_TIME_BB
	184	*/
	185	tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] \| 0x000A0000;
80301cdc	186	wl1251_reg_write32(wl, 0x00305858, tmp);
2f01a1f5 KV	187
	188	/*
	189	* set BB PLL Loop filter capacitor3- BB_C3[2:0] and set BB PLL
	190	* constant leakage current to linearize PFD to 0uA -
	191	* BB_ILOOPF[7:3]
	192	*/
	193	tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] \| 0x00000030;
80301cdc	194	wl1251_reg_write32(wl, 0x003058f8, tmp);
2f01a1f5 KV	195
	196	/*
	197	* set regulator output voltage for n divider to
	198	* 1.35-BB_REFDIV[1:0], set charge pump current- BB_CPGAIN[4:2],
	199	* set BB PLL Loop filter capacitor2- BB_C2[7:5], set gain of BB
	200	* PLL auto-call to normal mode- BB_CALGAIN_3DB[8]
	201	*/
80301cdc	202	wl1251_reg_write32(wl, 0x003058f0, 0x29);
2f01a1f5 KV	203
2f01a1f5 KV	204	/* enable restart wakeup sequence (ELP_CMD[0]) */
80301cdc	205	wl1251_reg_write32(wl, ELP_CMD, elp_cmd \| 0x1);
2f01a1f5 KV	206
	207	/* restart sequence completed */
	208	udelay(2000);
	209
	210	return 0;
	211	}
	212
0e71bb08 KV	213	static void wl1251_boot_set_ecpu_ctrl(struct wl1251 *wl, u32 flag)
	214	{
	215	u32 cpu_ctrl;
	216
	217	/* 10.5.0 run the firmware (I) */
	218	cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
	219
	220	/* 10.5.1 run the firmware (II) */
	221	cpu_ctrl &= ~flag;
	222	wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
	223	}
	224
80301cdc	225	int wl1251_boot_run_firmware(struct wl1251 *wl)
2f01a1f5 KV	226	{
	227	int loop, ret;
	228	u32 chip_id, interrupt;
	229
0e71bb08	230	wl1251_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
2f01a1f5	231
80301cdc	232	chip_id = wl1251_reg_read32(wl, CHIP_ID_B);
2f01a1f5	233
80301cdc	234	wl1251_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
2f01a1f5	235
0e71bb08	236	if (chip_id != wl->chip_id) {
80301cdc	237	wl1251_error("chip id doesn't match after firmware boot");
2f01a1f5 KV	238	return -EIO;
	239	}
	240
	241	/* wait for init to complete */
	242	loop = 0;
	243	while (loop++ < INIT_LOOP) {
	244	udelay(INIT_LOOP_DELAY);
80301cdc	245	interrupt = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
2f01a1f5 KV	246
2f01a1f5 KV	247	if (interrupt == 0xffffffff) {
80301cdc	248	wl1251_error("error reading hardware complete "
2f01a1f5 KV	249	"init indication");
	250	return -EIO;
	251	}
	252	/* check that ACX_INTR_INIT_COMPLETE is enabled */
0e71bb08	253	else if (interrupt & WL1251_ACX_INTR_INIT_COMPLETE) {
80301cdc	254	wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
0e71bb08	255	WL1251_ACX_INTR_INIT_COMPLETE);
2f01a1f5 KV	256	break;
	257	}
	258	}
	259
e8a4a6df	260	if (loop > INIT_LOOP) {
80301cdc	261	wl1251_error("timeout waiting for the hardware to "
2f01a1f5 KV	262	"complete initialization");
	263	return -EIO;
	264	}
	265
	266	/* get hardware config command mail box */
80301cdc	267	wl->cmd_box_addr = wl1251_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);
2f01a1f5 KV	268
2f01a1f5 KV	269	/* get hardware config event mail box */
80301cdc	270	wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
2f01a1f5 KV	271
2f01a1f5 KV	272	/* set the working partition to its "running" mode offset */
0e71bb08 KV	273	wl1251_set_partition(wl, WL1251_PART_WORK_MEM_START,
	274	WL1251_PART_WORK_MEM_SIZE,
	275	WL1251_PART_WORK_REG_START,
	276	WL1251_PART_WORK_REG_SIZE);
2f01a1f5	277
80301cdc	278	wl1251_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
2f01a1f5 KV	279	wl->cmd_box_addr, wl->event_box_addr);
2f01a1f5 KV	280
0e71bb08	281	wl1251_acx_fw_version(wl, wl->fw_ver, sizeof(wl->fw_ver));
0d1c3839	282
2f01a1f5 KV	283	/*
	284	* in case of full asynchronous mode the firmware event must be
	285	* ready to receive event from the command mailbox
	286	*/
	287
	288	/* enable gpio interrupts */
b5ed9c1b	289	wl1251_enable_interrupts(wl);
2f01a1f5	290
0e71bb08 KV	291	/* Enable target's interrupts */
	292	wl->intr_mask = WL1251_ACX_INTR_RX0_DATA \|
	293	WL1251_ACX_INTR_RX1_DATA \|
	294	WL1251_ACX_INTR_TX_RESULT \|
	295	WL1251_ACX_INTR_EVENT_A \|
	296	WL1251_ACX_INTR_EVENT_B \|
	297	WL1251_ACX_INTR_INIT_COMPLETE;
	298	wl1251_boot_target_enable_interrupts(wl);
2f01a1f5	299
a1590f24 JY	300	wl->event_mask = SCAN_COMPLETE_EVENT_ID \| BSS_LOSE_EVENT_ID \|
	301	SYNCHRONIZATION_TIMEOUT_EVENT_ID \|
	302	ROAMING_TRIGGER_LOW_RSSI_EVENT_ID \|
	303	ROAMING_TRIGGER_REGAINED_RSSI_EVENT_ID \|
	304	REGAINED_BSS_EVENT_ID \| BT_PTA_SENSE_EVENT_ID \|
	305	BT_PTA_PREDICTION_EVENT_ID;
2f01a1f5	306
80301cdc	307	ret = wl1251_event_unmask(wl);
2f01a1f5	308	if (ret < 0) {
80301cdc	309	wl1251_error("EVENT mask setting failed");
2f01a1f5 KV	310	return ret;
	311	}
	312
80301cdc	313	wl1251_event_mbox_config(wl);
2f01a1f5 KV	314
	315	/* firmware startup completed */
	316	return 0;
	317	}
0e71bb08 KV	318
	319	static int wl1251_boot_upload_firmware(struct wl1251 *wl)
	320	{
	321	int addr, chunk_num, partition_limit;
c74ddfd5 KV	322	size_t fw_data_len, len;
c74ddfd5 KV	323	u8 p, buf;
0e71bb08 KV	324
	325	/* whal_FwCtrl_LoadFwImageSm() */
	326
	327	wl1251_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x",
	328	wl1251_reg_read32(wl, CHIP_ID_B));
	329
	330	/* 10.0 check firmware length and set partition */
	331	fw_data_len = (wl->fw[4] << 24) \| (wl->fw[5] << 16) \|
	332	(wl->fw[6] << 8) \| (wl->fw[7]);
	333
	334	wl1251_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len,
	335	CHUNK_SIZE);
	336
	337	if ((fw_data_len % 4) != 0) {
	338	wl1251_error("firmware length not multiple of four");
	339	return -EIO;
	340	}
	341
c74ddfd5 KV	342	buf = kmalloc(CHUNK_SIZE, GFP_KERNEL);
	343	if (!buf) {
	344	wl1251_error("allocation for firmware upload chunk failed");
	345	return -ENOMEM;
	346	}
	347
0e71bb08 KV	348	wl1251_set_partition(wl, WL1251_PART_DOWN_MEM_START,
	349	WL1251_PART_DOWN_MEM_SIZE,
	350	WL1251_PART_DOWN_REG_START,
	351	WL1251_PART_DOWN_REG_SIZE);
	352
	353	/* 10.1 set partition limit and chunk num */
	354	chunk_num = 0;
	355	partition_limit = WL1251_PART_DOWN_MEM_SIZE;
	356
	357	while (chunk_num < fw_data_len / CHUNK_SIZE) {
	358	/* 10.2 update partition, if needed */
	359	addr = WL1251_PART_DOWN_MEM_START +
	360	(chunk_num + 2) * CHUNK_SIZE;
	361	if (addr > partition_limit) {
	362	addr = WL1251_PART_DOWN_MEM_START +
	363	chunk_num * CHUNK_SIZE;
	364	partition_limit = chunk_num * CHUNK_SIZE +
	365	WL1251_PART_DOWN_MEM_SIZE;
	366	wl1251_set_partition(wl,
	367	addr,
	368	WL1251_PART_DOWN_MEM_SIZE,
	369	WL1251_PART_DOWN_REG_START,
	370	WL1251_PART_DOWN_REG_SIZE);
	371	}
	372
	373	/* 10.3 upload the chunk */
	374	addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
	375	p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
	376	wl1251_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
	377	p, addr);
c74ddfd5 KV	378
	379	/* need to copy the chunk for dma */
	380	len = CHUNK_SIZE;
	381	memcpy(buf, p, len);
	382	wl1251_mem_write(wl, addr, buf, len);
0e71bb08 KV	383
	384	chunk_num++;
	385	}
	386
	387	/* 10.4 upload the last chunk */
	388	addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
	389	p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
c74ddfd5 KV	390
	391	/* need to copy the chunk for dma */
	392	len = fw_data_len % CHUNK_SIZE;
	393	memcpy(buf, p, len);
	394
0e71bb08	395	wl1251_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x",
c74ddfd5 KV	396	len, p, addr);
	397	wl1251_mem_write(wl, addr, buf, len);
	398
	399	kfree(buf);
0e71bb08 KV	400
	401	return 0;
	402	}
	403
	404	static int wl1251_boot_upload_nvs(struct wl1251 *wl)
	405	{
	406	size_t nvs_len, nvs_bytes_written, burst_len;
	407	int nvs_start, i;
	408	u32 dest_addr, val;
	409	u8 nvs_ptr, nvs;
	410
	411	nvs = wl->nvs;
	412	if (nvs == NULL)
	413	return -ENODEV;
	414
	415	nvs_ptr = nvs;
	416
	417	nvs_len = wl->nvs_len;
	418	nvs_start = wl->fw_len;
	419
	420	/*
	421	* Layout before the actual NVS tables:
	422	* 1 byte : burst length.
	423	* 2 bytes: destination address.
	424	* n bytes: data to burst copy.
	425	*
	426	* This is ended by a 0 length, then the NVS tables.
	427	*/
	428
	429	while (nvs_ptr[0]) {
	430	burst_len = nvs_ptr[0];
	431	dest_addr = (nvs_ptr[1] & 0xfe) \| ((u32)(nvs_ptr[2] << 8));
	432
	433	/* We move our pointer to the data */
	434	nvs_ptr += 3;
	435
	436	for (i = 0; i < burst_len; i++) {
	437	val = (nvs_ptr[0] \| (nvs_ptr[1] << 8)
	438	\| (nvs_ptr[2] << 16) \| (nvs_ptr[3] << 24));
	439
	440	wl1251_debug(DEBUG_BOOT,
	441	"nvs burst write 0x%x: 0x%x",
	442	dest_addr, val);
	443	wl1251_mem_write32(wl, dest_addr, val);
	444
	445	nvs_ptr += 4;
	446	dest_addr += 4;
	447	}
	448	}
	449
	450	/*
	451	* We've reached the first zero length, the first NVS table
	452	* is 7 bytes further.
	453	*/
	454	nvs_ptr += 7;
	455	nvs_len -= nvs_ptr - nvs;
	456	nvs_len = ALIGN(nvs_len, 4);
	457
	458	/* Now we must set the partition correctly */
	459	wl1251_set_partition(wl, nvs_start,
	460	WL1251_PART_DOWN_MEM_SIZE,
	461	WL1251_PART_DOWN_REG_START,
	462	WL1251_PART_DOWN_REG_SIZE);
	463
464	/* And finally we upload the NVS tables */
465	nvs_bytes_written = 0;
466	while (nvs_bytes_written < nvs_len) {
467	val = (nvs_ptr[0] \| (nvs_ptr[1] << 8)
468	\| (nvs_ptr[2] << 16) \| (nvs_ptr[3] << 24));
469
470	val = cpu_to_le32(val);
471
472	wl1251_debug(DEBUG_BOOT,
473	"nvs write table 0x%x: 0x%x",
474	nvs_start, val);
475	wl1251_mem_write32(wl, nvs_start, val);
476
477	nvs_ptr += 4;
478	nvs_bytes_written += 4;
479	nvs_start += 4;
480	}
481
482	return 0;
483	}
484
485	int wl1251_boot(struct wl1251 *wl)
486	{
487	int ret = 0, minor_minor_e2_ver;
488	u32 tmp, boot_data;
489
bcd64e0c BC	490	/* halt embedded ARM CPU while loading firmware */
	491	wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, ECPU_CONTROL_HALT);
	492
0e71bb08 KV	493	ret = wl1251_boot_soft_reset(wl);
	494	if (ret < 0)
	495	goto out;
	496
	497	/* 2. start processing NVS file */
c95cf3d0 DJW	498	if (wl->use_eeprom) {
	499	wl1251_reg_write32(wl, ACX_REG_EE_START, START_EEPROM_MGR);
	500	msleep(4000);
	501	wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, USE_EEPROM);
	502	} else {
	503	ret = wl1251_boot_upload_nvs(wl);
	504	if (ret < 0)
	505	goto out;
	506
	507	/* write firmware's last address (ie. it's length) to
	508	* ACX_EEPROMLESS_IND_REG */
	509	wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len);
	510	}
0e71bb08 KV	511
	512	/* 6. read the EEPROM parameters */
	513	tmp = wl1251_reg_read32(wl, SCR_PAD2);
	514
	515	/* 7. read bootdata */
	516	wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8;
	517	wl->boot_attr.major = (tmp & 0x00FF0000) >> 16;
	518	tmp = wl1251_reg_read32(wl, SCR_PAD3);
	519
	520	/* 8. check bootdata and call restart sequence */
	521	wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16;
	522	minor_minor_e2_ver = (tmp & 0xFF000000) >> 24;
	523
	524	wl1251_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x "
	525	"minorE2Ver 0x%x minor_minor_e2_ver 0x%x",
	526	wl->boot_attr.radio_type, wl->boot_attr.major,
	527	wl->boot_attr.minor, minor_minor_e2_ver);
	528
	529	ret = wl1251_boot_init_seq(wl);
	530	if (ret < 0)
	531	goto out;
	532
	533	/* 9. NVS processing done */
	534	boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
	535
	536	wl1251_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data);
	537
	538	/* 10. check that ECPU_CONTROL_HALT bits are set in
	539	* pWhalBus->uBootData and start uploading firmware
	540	*/
	541	if ((boot_data & ECPU_CONTROL_HALT) == 0) {
	542	wl1251_error("boot failed, ECPU_CONTROL_HALT not set");
	543	ret = -EIO;
	544	goto out;
	545	}
	546
	547	ret = wl1251_boot_upload_firmware(wl);
	548	if (ret < 0)
	549	goto out;
	550
	551	/* 10.5 start firmware */
	552	ret = wl1251_boot_run_firmware(wl);
	553	if (ret < 0)
	554	goto out;
	555
	556	out:
	557	return ret;
	558	}