]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/wireless/rt2x00/rt2800lib.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drivers/net: Convert unbounded kzalloc calls to kcalloc
[net-next-2.6.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
CommitLineData
89297425 1/*
a5ea2f02 2 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
9c9a0d14 3 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 4 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 5
9c9a0d14 6 Based on the original rt2800pci.c and rt2800usb.c.
9c9a0d14
GW		 7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 13 <http://rt2x00.serialmonkey.com>
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31/*
32 Module: rt2800lib
33 Abstract: rt2800 generic device routines.
34 */
35
f31c9a8c 36#include <linux/crc-ccitt.h>
89297425
BZ		 37#include <linux/kernel.h>
38#include <linux/module.h>
5a0e3ad6 39#include <linux/slab.h>
89297425
BZ		 40
41#include "rt2x00.h"
42#include "rt2800lib.h"
43#include "rt2800.h"
44
89297425
BZ		 45/*
46 * Register access.
47 * All access to the CSR registers will go through the methods
48 * rt2800_register_read and rt2800_register_write.
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers BBPCSR and RFCSR to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
57 * The _lock versions must be used if you already hold the csr_mutex
58 */
59#define WAIT_FOR_BBP(__dev, __reg) \
60 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
61#define WAIT_FOR_RFCSR(__dev, __reg) \
62 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
63#define WAIT_FOR_RF(__dev, __reg) \
64 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
65#define WAIT_FOR_MCU(__dev, __reg) \
66 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
67 H2M_MAILBOX_CSR_OWNER, (__reg))
68
baff8006
HS		 69static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
70{
71 /* check for rt2872 on SoC */
72 if (!rt2x00_is_soc(rt2x00dev) ||
73 !rt2x00_rt(rt2x00dev, RT2872))
74 return false;
75
76 /* we know for sure that these rf chipsets are used on rt305x boards */
77 if (rt2x00_rf(rt2x00dev, RF3020) ||
78 rt2x00_rf(rt2x00dev, RF3021) ||
79 rt2x00_rf(rt2x00dev, RF3022))
80 return true;
81
82 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
83 return false;
84}
85
fcf51541
BZ		 86static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
87 const unsigned int word, const u8 value)
89297425
BZ		 88{
89 u32 reg;
90
91 mutex_lock(&rt2x00dev->csr_mutex);
92
93 /*
94 * Wait until the BBP becomes available, afterwards we
95 * can safely write the new data into the register.
96 */
97 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
98 reg = 0;
99 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
efc7d36f 103 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 104
105 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
106 }
107
108 mutex_unlock(&rt2x00dev->csr_mutex);
109}
89297425 110
fcf51541
BZ		 111static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
112 const unsigned int word, u8 *value)
89297425
BZ		 113{
114 u32 reg;
115
116 mutex_lock(&rt2x00dev->csr_mutex);
117
118 /*
119 * Wait until the BBP becomes available, afterwards we
120 * can safely write the read request into the register.
121 * After the data has been written, we wait until hardware
122 * returns the correct value, if at any time the register
123 * doesn't become available in time, reg will be 0xffffffff
124 * which means we return 0xff to the caller.
125 */
126 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
127 reg = 0;
128 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
efc7d36f 131 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
89297425
BZ		 132
133 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
134
135 WAIT_FOR_BBP(rt2x00dev, &reg);
136 }
137
138 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
139
140 mutex_unlock(&rt2x00dev->csr_mutex);
141}
89297425 142
fcf51541
BZ		 143static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
144 const unsigned int word, const u8 value)
89297425
BZ		 145{
146 u32 reg;
147
148 mutex_lock(&rt2x00dev->csr_mutex);
149
150 /*
151 * Wait until the RFCSR becomes available, afterwards we
152 * can safely write the new data into the register.
153 */
154 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
155 reg = 0;
156 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
157 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
160
161 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
162 }
163
164 mutex_unlock(&rt2x00dev->csr_mutex);
165}
89297425 166
fcf51541
BZ		 167static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
168 const unsigned int word, u8 *value)
89297425
BZ		 169{
170 u32 reg;
171
172 mutex_lock(&rt2x00dev->csr_mutex);
173
174 /*
175 * Wait until the RFCSR becomes available, afterwards we
176 * can safely write the read request into the register.
177 * After the data has been written, we wait until hardware
178 * returns the correct value, if at any time the register
179 * doesn't become available in time, reg will be 0xffffffff
180 * which means we return 0xff to the caller.
181 */
182 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
183 reg = 0;
184 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
185 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
187
188 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
189
190 WAIT_FOR_RFCSR(rt2x00dev, &reg);
191 }
192
193 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
194
195 mutex_unlock(&rt2x00dev->csr_mutex);
196}
89297425 197
fcf51541
BZ		 198static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
199 const unsigned int word, const u32 value)
89297425
BZ		 200{
201 u32 reg;
202
203 mutex_lock(&rt2x00dev->csr_mutex);
204
205 /*
206 * Wait until the RF becomes available, afterwards we
207 * can safely write the new data into the register.
208 */
209 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
210 reg = 0;
211 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
215
216 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
217 rt2x00_rf_write(rt2x00dev, word, value);
218 }
219
220 mutex_unlock(&rt2x00dev->csr_mutex);
221}
89297425
BZ		 222
223void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
224 const u8 command, const u8 token,
225 const u8 arg0, const u8 arg1)
226{
227 u32 reg;
228
ee303e54 229 /*
cea90e55 230 * SOC devices don't support MCU requests.
ee303e54 231 */
cea90e55 232 if (rt2x00_is_soc(rt2x00dev))
ee303e54 233 return;
89297425
BZ		 234
235 mutex_lock(&rt2x00dev->csr_mutex);
236
237 /*
238 * Wait until the MCU becomes available, afterwards we
239 * can safely write the new data into the register.
240 */
241 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
242 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
246 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
247
248 reg = 0;
249 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
250 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
251 }
252
253 mutex_unlock(&rt2x00dev->csr_mutex);
254}
255EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 256
67a4c1e2
GW		 257int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
258{
259 unsigned int i;
260 u32 reg;
261
262 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
263 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
264 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
265 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
266 return 0;
267
268 msleep(1);
269 }
270
271 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
272 return -EACCES;
273}
274EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
275
f31c9a8c
ID		 276static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
277{
278 u16 fw_crc;
279 u16 crc;
280
281 /*
282 * The last 2 bytes in the firmware array are the crc checksum itself,
283 * this means that we should never pass those 2 bytes to the crc
284 * algorithm.
285 */
286 fw_crc = (data[len - 2] << 8 | data[len - 1]);
287
288 /*
289 * Use the crc ccitt algorithm.
290 * This will return the same value as the legacy driver which
291 * used bit ordering reversion on the both the firmware bytes
292 * before input input as well as on the final output.
293 * Obviously using crc ccitt directly is much more efficient.
294 */
295 crc = crc_ccitt(~0, data, len - 2);
296
297 /*
298 * There is a small difference between the crc-itu-t + bitrev and
299 * the crc-ccitt crc calculation. In the latter method the 2 bytes
300 * will be swapped, use swab16 to convert the crc to the correct
301 * value.
302 */
303 crc = swab16(crc);
304
305 return fw_crc == crc;
306}
307
308int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
309 const u8 *data, const size_t len)
310{
311 size_t offset = 0;
312 size_t fw_len;
313 bool multiple;
314
315 /*
316 * PCI(e) & SOC devices require firmware with a length
317 * of 8kb. USB devices require firmware files with a length
318 * of 4kb. Certain USB chipsets however require different firmware,
319 * which Ralink only provides attached to the original firmware
320 * file. Thus for USB devices, firmware files have a length
321 * which is a multiple of 4kb.
322 */
323 if (rt2x00_is_usb(rt2x00dev)) {
324 fw_len = 4096;
325 multiple = true;
326 } else {
327 fw_len = 8192;
328 multiple = true;
329 }
330
331 /*
332 * Validate the firmware length
333 */
334 if (len != fw_len && (!multiple || (len % fw_len) != 0))
335 return FW_BAD_LENGTH;
336
337 /*
338 * Check if the chipset requires one of the upper parts
339 * of the firmware.
340 */
341 if (rt2x00_is_usb(rt2x00dev) &&
342 !rt2x00_rt(rt2x00dev, RT2860) &&
343 !rt2x00_rt(rt2x00dev, RT2872) &&
344 !rt2x00_rt(rt2x00dev, RT3070) &&
345 ((len / fw_len) == 1))
346 return FW_BAD_VERSION;
347
348 /*
349 * 8kb firmware files must be checked as if it were
350 * 2 separate firmware files.
351 */
352 while (offset < len) {
353 if (!rt2800_check_firmware_crc(data + offset, fw_len))
354 return FW_BAD_CRC;
355
356 offset += fw_len;
357 }
358
359 return FW_OK;
360}
361EXPORT_SYMBOL_GPL(rt2800_check_firmware);
362
363int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
364 const u8 *data, const size_t len)
365{
366 unsigned int i;
367 u32 reg;
368
369 /*
370 * Wait for stable hardware.
371 */
372 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
373 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
374 if (reg && reg != ~0)
375 break;
376 msleep(1);
377 }
378
379 if (i == REGISTER_BUSY_COUNT) {
380 ERROR(rt2x00dev, "Unstable hardware.\n");
381 return -EBUSY;
382 }
383
384 if (rt2x00_is_pci(rt2x00dev))
385 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
386
387 /*
388 * Disable DMA, will be reenabled later when enabling
389 * the radio.
390 */
391 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
392 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
393 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
394 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
395 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
396 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
397 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
398
399 /*
400 * Write firmware to the device.
401 */
402 rt2800_drv_write_firmware(rt2x00dev, data, len);
403
404 /*
405 * Wait for device to stabilize.
406 */
407 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
408 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
409 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
410 break;
411 msleep(1);
412 }
413
414 if (i == REGISTER_BUSY_COUNT) {
415 ERROR(rt2x00dev, "PBF system register not ready.\n");
416 return -EBUSY;
417 }
418
419 /*
420 * Initialize firmware.
421 */
422 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
423 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
424 msleep(1);
425
426 return 0;
427}
428EXPORT_SYMBOL_GPL(rt2800_load_firmware);
429
0b8004aa 430void rt2800_write_txwi(__le32 *txwi, struct txentry_desc *txdesc)
59679b91 431{
59679b91
GW		 432 u32 word;
433
434 /*
435 * Initialize TX Info descriptor
436 */
437 rt2x00_desc_read(txwi, 0, &word);
438 rt2x00_set_field32(&word, TXWI_W0_FRAG,
439 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
440 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
441 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
442 rt2x00_set_field32(&word, TXWI_W0_TS,
443 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
444 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
445 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
446 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
447 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
448 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
449 rt2x00_set_field32(&word, TXWI_W0_BW,
450 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
451 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
452 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
453 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
454 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
455 rt2x00_desc_write(txwi, 0, word);
456
457 rt2x00_desc_read(txwi, 1, &word);
458 rt2x00_set_field32(&word, TXWI_W1_ACK,
459 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
460 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
461 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
462 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
463 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
464 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
465 txdesc->key_idx : 0xff);
466 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
467 txdesc->length);
468 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1);
469 rt2x00_desc_write(txwi, 1, word);
470
471 /*
472 * Always write 0 to IV/EIV fields, hardware will insert the IV
473 * from the IVEIV register when TXD_W3_WIV is set to 0.
474 * When TXD_W3_WIV is set to 1 it will use the IV data
475 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
476 * crypto entry in the registers should be used to encrypt the frame.
477 */
478 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
479 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
480}
481EXPORT_SYMBOL_GPL(rt2800_write_txwi);
482
74861922 483static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxwi_w2)
2de64dd2 484{
74861922
ID		 485 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
486 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
487 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
488 u16 eeprom;
489 u8 offset0;
490 u8 offset1;
491 u8 offset2;
492
493 if (rt2x00dev->rx_status.band == IEEE80211_BAND_2GHZ) {
494 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
495 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
496 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
497 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
498 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
499 } else {
500 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
501 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
502 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
503 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
504 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
505 }
506
507 /*
508 * Convert the value from the descriptor into the RSSI value
509 * If the value in the descriptor is 0, it is considered invalid
510 * and the default (extremely low) rssi value is assumed
511 */
512 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
513 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
514 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
515
516 /*
517 * mac80211 only accepts a single RSSI value. Calculating the
518 * average doesn't deliver a fair answer either since -60:-60 would
519 * be considered equally good as -50:-70 while the second is the one
520 * which gives less energy...
521 */
522 rssi0 = max(rssi0, rssi1);
523 return max(rssi0, rssi2);
524}
525
526void rt2800_process_rxwi(struct queue_entry *entry,
527 struct rxdone_entry_desc *rxdesc)
528{
529 __le32 *rxwi = (__le32 *) entry->skb->data;
2de64dd2
GW		 530 u32 word;
531
532 rt2x00_desc_read(rxwi, 0, &word);
533
534 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
535 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
536
537 rt2x00_desc_read(rxwi, 1, &word);
538
539 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
540 rxdesc->flags |= RX_FLAG_SHORT_GI;
541
542 if (rt2x00_get_field32(word, RXWI_W1_BW))
543 rxdesc->flags |= RX_FLAG_40MHZ;
544
545 /*
546 * Detect RX rate, always use MCS as signal type.
547 */
548 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
549 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
550 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
551
552 /*
553 * Mask of 0x8 bit to remove the short preamble flag.
554 */
555 if (rxdesc->rate_mode == RATE_MODE_CCK)
556 rxdesc->signal &= ~0x8;
557
558 rt2x00_desc_read(rxwi, 2, &word);
559
74861922
ID		 560 /*
561 * Convert descriptor AGC value to RSSI value.
562 */
563 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
2de64dd2
GW		 564
565 /*
566 * Remove RXWI descriptor from start of buffer.
567 */
74861922 568 skb_pull(entry->skb, RXWI_DESC_SIZE);
2de64dd2
GW		 569}
570EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
571
f0194b2d
GW		 572void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
573{
574 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
575 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
576 unsigned int beacon_base;
577 u32 reg;
578
579 /*
580 * Disable beaconing while we are reloading the beacon data,
581 * otherwise we might be sending out invalid data.
582 */
583 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
584 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
585 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
586
587 /*
588 * Add space for the TXWI in front of the skb.
589 */
590 skb_push(entry->skb, TXWI_DESC_SIZE);
591 memset(entry->skb, 0, TXWI_DESC_SIZE);
592
593 /*
594 * Register descriptor details in skb frame descriptor.
595 */
596 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
597 skbdesc->desc = entry->skb->data;
598 skbdesc->desc_len = TXWI_DESC_SIZE;
599
600 /*
601 * Add the TXWI for the beacon to the skb.
602 */
603 rt2800_write_txwi((__le32 *)entry->skb->data, txdesc);
604
605 /*
606 * Dump beacon to userspace through debugfs.
607 */
608 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
609
610 /*
611 * Write entire beacon with TXWI to register.
612 */
613 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
614 rt2800_register_multiwrite(rt2x00dev, beacon_base,
615 entry->skb->data, entry->skb->len);
616
617 /*
618 * Enable beaconing again.
619 */
620 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
621 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
622 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
623 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
624
625 /*
626 * Clean up beacon skb.
627 */
628 dev_kfree_skb_any(entry->skb);
629 entry->skb = NULL;
630}
50e888ea 631EXPORT_SYMBOL_GPL(rt2800_write_beacon);
f0194b2d 632
fdb87251
HS		 633static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
634 unsigned int beacon_base)
635{
636 int i;
637
638 /*
639 * For the Beacon base registers we only need to clear
640 * the whole TXWI which (when set to 0) will invalidate
641 * the entire beacon.
642 */
643 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
644 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
645}
646
f4450616
BZ		 647#ifdef CONFIG_RT2X00_LIB_DEBUGFS
648const struct rt2x00debug rt2800_rt2x00debug = {
649 .owner = THIS_MODULE,
650 .csr = {
651 .read = rt2800_register_read,
652 .write = rt2800_register_write,
653 .flags = RT2X00DEBUGFS_OFFSET,
654 .word_base = CSR_REG_BASE,
655 .word_size = sizeof(u32),
656 .word_count = CSR_REG_SIZE / sizeof(u32),
657 },
658 .eeprom = {
659 .read = rt2x00_eeprom_read,
660 .write = rt2x00_eeprom_write,
661 .word_base = EEPROM_BASE,
662 .word_size = sizeof(u16),
663 .word_count = EEPROM_SIZE / sizeof(u16),
664 },
665 .bbp = {
666 .read = rt2800_bbp_read,
667 .write = rt2800_bbp_write,
668 .word_base = BBP_BASE,
669 .word_size = sizeof(u8),
670 .word_count = BBP_SIZE / sizeof(u8),
671 },
672 .rf = {
673 .read = rt2x00_rf_read,
674 .write = rt2800_rf_write,
675 .word_base = RF_BASE,
676 .word_size = sizeof(u32),
677 .word_count = RF_SIZE / sizeof(u32),
678 },
679};
680EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
681#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
682
683int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
684{
685 u32 reg;
686
687 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
688 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
689}
690EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
691
692#ifdef CONFIG_RT2X00_LIB_LEDS
693static void rt2800_brightness_set(struct led_classdev *led_cdev,
694 enum led_brightness brightness)
695{
696 struct rt2x00_led *led =
697 container_of(led_cdev, struct rt2x00_led, led_dev);
698 unsigned int enabled = brightness != LED_OFF;
699 unsigned int bg_mode =
700 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
701 unsigned int polarity =
702 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
703 EEPROM_FREQ_LED_POLARITY);
704 unsigned int ledmode =
705 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
706 EEPROM_FREQ_LED_MODE);
707
708 if (led->type == LED_TYPE_RADIO) {
709 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
710 enabled ? 0x20 : 0);
711 } else if (led->type == LED_TYPE_ASSOC) {
712 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
713 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
714 } else if (led->type == LED_TYPE_QUALITY) {
715 /*
716 * The brightness is divided into 6 levels (0 - 5),
717 * The specs tell us the following levels:
718 * 0, 1 ,3, 7, 15, 31
719 * to determine the level in a simple way we can simply
720 * work with bitshifting:
721 * (1 << level) - 1
722 */
723 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
724 (1 << brightness / (LED_FULL / 6)) - 1,
725 polarity);
726 }
727}
728
729static int rt2800_blink_set(struct led_classdev *led_cdev,
730 unsigned long *delay_on, unsigned long *delay_off)
731{
732 struct rt2x00_led *led =
733 container_of(led_cdev, struct rt2x00_led, led_dev);
734 u32 reg;
735
736 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
737 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
738 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 739 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
740
741 return 0;
742}
743
b3579d6a 744static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 745 struct rt2x00_led *led, enum led_type type)
746{
747 led->rt2x00dev = rt2x00dev;
748 led->type = type;
749 led->led_dev.brightness_set = rt2800_brightness_set;
750 led->led_dev.blink_set = rt2800_blink_set;
751 led->flags = LED_INITIALIZED;
752}
f4450616
BZ		 753#endif /* CONFIG_RT2X00_LIB_LEDS */
754
755/*
756 * Configuration handlers.
757 */
758static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
759 struct rt2x00lib_crypto *crypto,
760 struct ieee80211_key_conf *key)
761{
762 struct mac_wcid_entry wcid_entry;
763 struct mac_iveiv_entry iveiv_entry;
764 u32 offset;
765 u32 reg;
766
767 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
768
e4a0ab34
ID		 769 if (crypto->cmd == SET_KEY) {
770 rt2800_register_read(rt2x00dev, offset, &reg);
771 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
772 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
773 /*
774 * Both the cipher as the BSS Idx numbers are split in a main
775 * value of 3 bits, and a extended field for adding one additional
776 * bit to the value.
777 */
778 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
779 (crypto->cipher & 0x7));
780 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
781 (crypto->cipher & 0x8) >> 3);
782 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
783 (crypto->bssidx & 0x7));
784 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
785 (crypto->bssidx & 0x8) >> 3);
786 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
787 rt2800_register_write(rt2x00dev, offset, reg);
788 } else {
789 rt2800_register_write(rt2x00dev, offset, 0);
790 }
f4450616
BZ		 791
792 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
793
794 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
795 if ((crypto->cipher == CIPHER_TKIP) ||
796 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
797 (crypto->cipher == CIPHER_AES))
798 iveiv_entry.iv[3] |= 0x20;
799 iveiv_entry.iv[3] |= key->keyidx << 6;
800 rt2800_register_multiwrite(rt2x00dev, offset,
801 &iveiv_entry, sizeof(iveiv_entry));
802
803 offset = MAC_WCID_ENTRY(key->hw_key_idx);
804
805 memset(&wcid_entry, 0, sizeof(wcid_entry));
806 if (crypto->cmd == SET_KEY)
807 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
808 rt2800_register_multiwrite(rt2x00dev, offset,
809 &wcid_entry, sizeof(wcid_entry));
810}
811
812int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
813 struct rt2x00lib_crypto *crypto,
814 struct ieee80211_key_conf *key)
815{
816 struct hw_key_entry key_entry;
817 struct rt2x00_field32 field;
818 u32 offset;
819 u32 reg;
820
821 if (crypto->cmd == SET_KEY) {
822 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
823
824 memcpy(key_entry.key, crypto->key,
825 sizeof(key_entry.key));
826 memcpy(key_entry.tx_mic, crypto->tx_mic,
827 sizeof(key_entry.tx_mic));
828 memcpy(key_entry.rx_mic, crypto->rx_mic,
829 sizeof(key_entry.rx_mic));
830
831 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
832 rt2800_register_multiwrite(rt2x00dev, offset,
833 &key_entry, sizeof(key_entry));
834 }
835
836 /*
837 * The cipher types are stored over multiple registers
838 * starting with SHARED_KEY_MODE_BASE each word will have
839 * 32 bits and contains the cipher types for 2 bssidx each.
840 * Using the correct defines correctly will cause overhead,
841 * so just calculate the correct offset.
842 */
843 field.bit_offset = 4 * (key->hw_key_idx % 8);
844 field.bit_mask = 0x7 << field.bit_offset;
845
846 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
847
848 rt2800_register_read(rt2x00dev, offset, &reg);
849 rt2x00_set_field32(&reg, field,
850 (crypto->cmd == SET_KEY) * crypto->cipher);
851 rt2800_register_write(rt2x00dev, offset, reg);
852
853 /*
854 * Update WCID information
855 */
856 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
857
858 return 0;
859}
860EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
861
862int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
863 struct rt2x00lib_crypto *crypto,
864 struct ieee80211_key_conf *key)
865{
866 struct hw_key_entry key_entry;
867 u32 offset;
868
869 if (crypto->cmd == SET_KEY) {
870 /*
871 * 1 pairwise key is possible per AID, this means that the AID
872 * equals our hw_key_idx. Make sure the WCID starts _after_ the
873 * last possible shared key entry.
874 */
875 if (crypto->aid > (256 - 32))
876 return -ENOSPC;
877
878 key->hw_key_idx = 32 + crypto->aid;
879
880 memcpy(key_entry.key, crypto->key,
881 sizeof(key_entry.key));
882 memcpy(key_entry.tx_mic, crypto->tx_mic,
883 sizeof(key_entry.tx_mic));
884 memcpy(key_entry.rx_mic, crypto->rx_mic,
885 sizeof(key_entry.rx_mic));
886
887 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
888 rt2800_register_multiwrite(rt2x00dev, offset,
889 &key_entry, sizeof(key_entry));
890 }
891
892 /*
893 * Update WCID information
894 */
895 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
896
897 return 0;
898}
899EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
900
901void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
902 const unsigned int filter_flags)
903{
904 u32 reg;
905
906 /*
907 * Start configuration steps.
908 * Note that the version error will always be dropped
909 * and broadcast frames will always be accepted since
910 * there is no filter for it at this time.
911 */
912 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
913 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
914 !(filter_flags & FIF_FCSFAIL));
915 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
916 !(filter_flags & FIF_PLCPFAIL));
917 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
918 !(filter_flags & FIF_PROMISC_IN_BSS));
919 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
920 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
921 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
922 !(filter_flags & FIF_ALLMULTI));
923 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
924 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
925 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
926 !(filter_flags & FIF_CONTROL));
927 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
928 !(filter_flags & FIF_CONTROL));
929 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
930 !(filter_flags & FIF_CONTROL));
931 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
932 !(filter_flags & FIF_CONTROL));
933 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
934 !(filter_flags & FIF_CONTROL));
935 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
936 !(filter_flags & FIF_PSPOLL));
937 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
938 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
939 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
940 !(filter_flags & FIF_CONTROL));
941 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
942}
943EXPORT_SYMBOL_GPL(rt2800_config_filter);
944
945void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
946 struct rt2x00intf_conf *conf, const unsigned int flags)
947{
f4450616
BZ		 948 u32 reg;
949
950 if (flags & CONFIG_UPDATE_TYPE) {
951 /*
952 * Clear current synchronisation setup.
f4450616 953 */
fdb87251
HS		 954 rt2800_clear_beacon(rt2x00dev,
955 HW_BEACON_OFFSET(intf->beacon->entry_idx));
f4450616
BZ		 956 /*
957 * Enable synchronisation.
958 */
959 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
960 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
961 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef 962 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
ab8966dd
HS		 963 (conf->sync == TSF_SYNC_ADHOC ||
964 conf->sync == TSF_SYNC_AP_NONE));
f4450616 965 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
9f926fb5
HS		 966
967 /*
968 * Enable pre tbtt interrupt for beaconing modes
969 */
970 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
971 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
ab8966dd 972 (conf->sync == TSF_SYNC_AP_NONE));
9f926fb5
HS		 973 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
974
f4450616
BZ		 975 }
976
977 if (flags & CONFIG_UPDATE_MAC) {
978 reg = le32_to_cpu(conf->mac[1]);
979 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
980 conf->mac[1] = cpu_to_le32(reg);
981
982 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
983 conf->mac, sizeof(conf->mac));
984 }
985
986 if (flags & CONFIG_UPDATE_BSSID) {
987 reg = le32_to_cpu(conf->bssid[1]);
d440cb9e
ID		 988 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
989 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
f4450616
BZ		 990 conf->bssid[1] = cpu_to_le32(reg);
991
992 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
993 conf->bssid, sizeof(conf->bssid));
994 }
995}
996EXPORT_SYMBOL_GPL(rt2800_config_intf);
997
998void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
999{
1000 u32 reg;
1001
f4450616
BZ		 1002 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1003 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1004 !!erp->short_preamble);
1005 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1006 !!erp->short_preamble);
1007 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1008
1009 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1010 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1011 erp->cts_protection ? 2 : 0);
1012 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1013
1014 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1015 erp->basic_rates);
1016 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1017
1018 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1019 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
f4450616
BZ		 1020 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1021
1022 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
f4450616 1023 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
f4450616
BZ		 1024 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1025
1026 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1027 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1028 erp->beacon_int * 16);
1029 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1030}
1031EXPORT_SYMBOL_GPL(rt2800_config_erp);
1032
1033void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1034{
1035 u8 r1;
1036 u8 r3;
1037
1038 rt2800_bbp_read(rt2x00dev, 1, &r1);
1039 rt2800_bbp_read(rt2x00dev, 3, &r3);
1040
1041 /*
1042 * Configure the TX antenna.
1043 */
1044 switch ((int)ant->tx) {
1045 case 1:
1046 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1047 break;
1048 case 2:
1049 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1050 break;
1051 case 3:
e22557f2 1052 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
f4450616
BZ		 1053 break;
1054 }
1055
1056 /*
1057 * Configure the RX antenna.
1058 */
1059 switch ((int)ant->rx) {
1060 case 1:
1061 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1062 break;
1063 case 2:
1064 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1065 break;
1066 case 3:
1067 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1068 break;
1069 }
1070
1071 rt2800_bbp_write(rt2x00dev, 3, r3);
1072 rt2800_bbp_write(rt2x00dev, 1, r1);
1073}
1074EXPORT_SYMBOL_GPL(rt2800_config_ant);
1075
1076static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1077 struct rt2x00lib_conf *libconf)
1078{
1079 u16 eeprom;
1080 short lna_gain;
1081
1082 if (libconf->rf.channel <= 14) {
1083 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1084 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1085 } else if (libconf->rf.channel <= 64) {
1086 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1087 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1088 } else if (libconf->rf.channel <= 128) {
1089 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1090 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1091 } else {
1092 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1093 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1094 }
1095
1096 rt2x00dev->lna_gain = lna_gain;
1097}
1098
06855ef4
GW		 1099static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1100 struct ieee80211_conf *conf,
1101 struct rf_channel *rf,
1102 struct channel_info *info)
f4450616
BZ		 1103{
1104 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1105
1106 if (rt2x00dev->default_ant.tx == 1)
1107 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1108
1109 if (rt2x00dev->default_ant.rx == 1) {
1110 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1111 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1112 } else if (rt2x00dev->default_ant.rx == 2)
1113 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1114
1115 if (rf->channel > 14) {
1116 /*
1117 * When TX power is below 0, we should increase it by 7 to
1118 * make it a positive value (Minumum value is -7).
1119 * However this means that values between 0 and 7 have
1120 * double meaning, and we should set a 7DBm boost flag.
1121 */
1122 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1123 (info->tx_power1 >= 0));
1124
1125 if (info->tx_power1 < 0)
1126 info->tx_power1 += 7;
1127
1128 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
1129 TXPOWER_A_TO_DEV(info->tx_power1));
1130
1131 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1132 (info->tx_power2 >= 0));
1133
1134 if (info->tx_power2 < 0)
1135 info->tx_power2 += 7;
1136
1137 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
1138 TXPOWER_A_TO_DEV(info->tx_power2));
1139 } else {
1140 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
1141 TXPOWER_G_TO_DEV(info->tx_power1));
1142 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
1143 TXPOWER_G_TO_DEV(info->tx_power2));
1144 }
1145
1146 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1147
1148 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1149 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1150 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1151 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1152
1153 udelay(200);
1154
1155 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1156 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1157 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1158 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1159
1160 udelay(200);
1161
1162 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1163 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1164 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1165 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1166}
1167
06855ef4
GW		 1168static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1169 struct ieee80211_conf *conf,
1170 struct rf_channel *rf,
1171 struct channel_info *info)
f4450616
BZ		 1172{
1173 u8 rfcsr;
1174
1175 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 1176 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 1177
1178 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 1179 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 1180 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1181
1182 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1183 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1184 TXPOWER_G_TO_DEV(info->tx_power1));
1185 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1186
5a673964
HS		 1187 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1188 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1189 TXPOWER_G_TO_DEV(info->tx_power2));
1190 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1191
f4450616
BZ		 1192 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1193 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1194 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1195
1196 rt2800_rfcsr_write(rt2x00dev, 24,
1197 rt2x00dev->calibration[conf_is_ht40(conf)]);
1198
71976907 1199 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 1200 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 1201 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 1202}
1203
1204static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1205 struct ieee80211_conf *conf,
1206 struct rf_channel *rf,
1207 struct channel_info *info)
1208{
1209 u32 reg;
1210 unsigned int tx_pin;
1211 u8 bbp;
1212
06855ef4
GW		 1213 if (rt2x00_rf(rt2x00dev, RF2020) ||
1214 rt2x00_rf(rt2x00dev, RF3020) ||
1215 rt2x00_rf(rt2x00dev, RF3021) ||
1216 rt2x00_rf(rt2x00dev, RF3022))
1217 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 1218 else
06855ef4 1219 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 1220
1221 /*
1222 * Change BBP settings
1223 */
1224 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1225 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1226 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1227 rt2800_bbp_write(rt2x00dev, 86, 0);
1228
1229 if (rf->channel <= 14) {
1230 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1231 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1232 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1233 } else {
1234 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1235 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1236 }
1237 } else {
1238 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1239
1240 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1241 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1242 else
1243 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1244 }
1245
1246 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
a21ee724 1247 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1248 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1249 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1250 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1251
1252 tx_pin = 0;
1253
1254 /* Turn on unused PA or LNA when not using 1T or 1R */
1255 if (rt2x00dev->default_ant.tx != 1) {
1256 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1257 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1258 }
1259
1260 /* Turn on unused PA or LNA when not using 1T or 1R */
1261 if (rt2x00dev->default_ant.rx != 1) {
1262 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1263 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1264 }
1265
1266 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1267 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1268 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1269 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1270 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1271 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1272
1273 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1274
1275 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1276 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1277 rt2800_bbp_write(rt2x00dev, 4, bbp);
1278
1279 rt2800_bbp_read(rt2x00dev, 3, &bbp);
a21ee724 1280 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
f4450616
BZ		 1281 rt2800_bbp_write(rt2x00dev, 3, bbp);
1282
8d0c9b65 1283 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 1284 if (conf_is_ht40(conf)) {
1285 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1286 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1287 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1288 } else {
1289 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1290 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1291 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1292 }
1293 }
1294
1295 msleep(1);
1296}
1297
1298static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5e846004 1299 const int max_txpower)
f4450616 1300{
5e846004
HS		 1301 u8 txpower;
1302 u8 max_value = (u8)max_txpower;
1303 u16 eeprom;
1304 int i;
f4450616 1305 u32 reg;
f4450616 1306 u8 r1;
5e846004 1307 u32 offset;
f4450616 1308
5e846004
HS		 1309 /*
1310 * set to normal tx power mode: +/- 0dBm
1311 */
f4450616 1312 rt2800_bbp_read(rt2x00dev, 1, &r1);
a3f84ca4 1313 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
f4450616
BZ		 1314 rt2800_bbp_write(rt2x00dev, 1, r1);
1315
5e846004
HS		 1316 /*
1317 * The eeprom contains the tx power values for each rate. These
1318 * values map to 100% tx power. Each 16bit word contains four tx
1319 * power values and the order is the same as used in the TX_PWR_CFG
1320 * registers.
1321 */
1322 offset = TX_PWR_CFG_0;
1323
1324 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1325 /* just to be safe */
1326 if (offset > TX_PWR_CFG_4)
1327 break;
1328
1329 rt2800_register_read(rt2x00dev, offset, &reg);
1330
1331 /* read the next four txpower values */
1332 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1333 &eeprom);
1334
1335 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1336 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1337 * TX_PWR_CFG_4: unknown */
1338 txpower = rt2x00_get_field16(eeprom,
1339 EEPROM_TXPOWER_BYRATE_RATE0);
1340 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1341 min(txpower, max_value));
1342
1343 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1344 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1345 * TX_PWR_CFG_4: unknown */
1346 txpower = rt2x00_get_field16(eeprom,
1347 EEPROM_TXPOWER_BYRATE_RATE1);
1348 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1349 min(txpower, max_value));
1350
1351 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1352 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1353 * TX_PWR_CFG_4: unknown */
1354 txpower = rt2x00_get_field16(eeprom,
1355 EEPROM_TXPOWER_BYRATE_RATE2);
1356 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1357 min(txpower, max_value));
1358
1359 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1360 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1361 * TX_PWR_CFG_4: unknown */
1362 txpower = rt2x00_get_field16(eeprom,
1363 EEPROM_TXPOWER_BYRATE_RATE3);
1364 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1365 min(txpower, max_value));
1366
1367 /* read the next four txpower values */
1368 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1369 &eeprom);
1370
1371 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1372 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1373 * TX_PWR_CFG_4: unknown */
1374 txpower = rt2x00_get_field16(eeprom,
1375 EEPROM_TXPOWER_BYRATE_RATE0);
1376 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1377 min(txpower, max_value));
1378
1379 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1380 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1381 * TX_PWR_CFG_4: unknown */
1382 txpower = rt2x00_get_field16(eeprom,
1383 EEPROM_TXPOWER_BYRATE_RATE1);
1384 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1385 min(txpower, max_value));
1386
1387 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1388 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1389 * TX_PWR_CFG_4: unknown */
1390 txpower = rt2x00_get_field16(eeprom,
1391 EEPROM_TXPOWER_BYRATE_RATE2);
1392 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1393 min(txpower, max_value));
1394
1395 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1396 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1397 * TX_PWR_CFG_4: unknown */
1398 txpower = rt2x00_get_field16(eeprom,
1399 EEPROM_TXPOWER_BYRATE_RATE3);
1400 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1401 min(txpower, max_value));
1402
1403 rt2800_register_write(rt2x00dev, offset, reg);
1404
1405 /* next TX_PWR_CFG register */
1406 offset += 4;
1407 }
f4450616
BZ		 1408}
1409
1410static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1411 struct rt2x00lib_conf *libconf)
1412{
1413 u32 reg;
1414
1415 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1416 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1417 libconf->conf->short_frame_max_tx_count);
1418 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1419 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 1420 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1421}
1422
1423static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1424 struct rt2x00lib_conf *libconf)
1425{
1426 enum dev_state state =
1427 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1428 STATE_SLEEP : STATE_AWAKE;
1429 u32 reg;
1430
1431 if (state == STATE_SLEEP) {
1432 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1433
1434 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1435 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1436 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1437 libconf->conf->listen_interval - 1);
1438 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1439 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1440
1441 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1442 } else {
f4450616
BZ		 1443 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1444 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1445 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1446 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1447 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1448
1449 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1450 }
1451}
1452
1453void rt2800_config(struct rt2x00_dev *rt2x00dev,
1454 struct rt2x00lib_conf *libconf,
1455 const unsigned int flags)
1456{
1457 /* Always recalculate LNA gain before changing configuration */
1458 rt2800_config_lna_gain(rt2x00dev, libconf);
1459
1460 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1461 rt2800_config_channel(rt2x00dev, libconf->conf,
1462 &libconf->rf, &libconf->channel);
1463 if (flags & IEEE80211_CONF_CHANGE_POWER)
1464 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1465 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1466 rt2800_config_retry_limit(rt2x00dev, libconf);
1467 if (flags & IEEE80211_CONF_CHANGE_PS)
1468 rt2800_config_ps(rt2x00dev, libconf);
1469}
1470EXPORT_SYMBOL_GPL(rt2800_config);
1471
1472/*
1473 * Link tuning
1474 */
1475void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1476{
1477 u32 reg;
1478
1479 /*
1480 * Update FCS error count from register.
1481 */
1482 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1483 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1484}
1485EXPORT_SYMBOL_GPL(rt2800_link_stats);
1486
1487static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1488{
1489 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1490 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1491 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1492 rt2x00_rt(rt2x00dev, RT3090) ||
1493 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1494 return 0x1c + (2 * rt2x00dev->lna_gain);
1495 else
1496 return 0x2e + rt2x00dev->lna_gain;
1497 }
1498
1499 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1500 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1501 else
1502 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1503}
1504
1505static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1506 struct link_qual *qual, u8 vgc_level)
1507{
1508 if (qual->vgc_level != vgc_level) {
1509 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1510 qual->vgc_level = vgc_level;
1511 qual->vgc_level_reg = vgc_level;
1512 }
1513}
1514
1515void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1516{
1517 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1518}
1519EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1520
1521void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1522 const u32 count)
1523{
8d0c9b65 1524 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1525 return;
1526
1527 /*
1528 * When RSSI is better then -80 increase VGC level with 0x10
1529 */
1530 rt2800_set_vgc(rt2x00dev, qual,
1531 rt2800_get_default_vgc(rt2x00dev) +
1532 ((qual->rssi > -80) * 0x10));
1533}
1534EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1535
1536/*
1537 * Initialization functions.
1538 */
1539int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1540{
1541 u32 reg;
d5385bfc 1542 u16 eeprom;
fcf51541 1543 unsigned int i;
e3a896b9 1544 int ret;
fcf51541 1545
a9dce149
GW		 1546 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1547 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1548 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1549 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1550 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1551 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1552 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1553
e3a896b9
GW		 1554 ret = rt2800_drv_init_registers(rt2x00dev);
1555 if (ret)
1556 return ret;
fcf51541
BZ		 1557
1558 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1559 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1560 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1561 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1562 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1563 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1564
1565 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1566 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1567 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1568 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1569 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1570 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1571
1572 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1573 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1574
1575 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1576
1577 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
8544df32 1578 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
fcf51541
BZ		 1579 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1580 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1581 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1582 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1583 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1584 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1585
a9dce149
GW		 1586 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1587
1588 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1589 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1590 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1591 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1592
64522957 1593 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1594 rt2x00_rt(rt2x00dev, RT3090) ||
1595 rt2x00_rt(rt2x00dev, RT3390)) {
fcf51541
BZ		 1596 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1597 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1598 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1599 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1600 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1601 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1602 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1603 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1604 0x0000002c);
1605 else
1606 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1607 0x0000000f);
1608 } else {
1609 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1610 }
d5385bfc 1611 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1612 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1613
1614 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1615 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1616 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1617 } else {
1618 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1619 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1620 }
c295a81d
HS		 1621 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1622 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1623 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1624 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
fcf51541
BZ		 1625 } else {
1626 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1627 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1628 }
1629
1630 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1631 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1632 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1633 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1634 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1635 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1636 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1637 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1638 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1639 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1640
1641 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1642 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1643 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1644 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1645 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1646
1647 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1648 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1649 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1650 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1651 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1652 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1653 else
1654 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1655 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1656 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1657 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1658
a9dce149
GW		 1659 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1660 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1661 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1662 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1663 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1664 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1665 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1666 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1667 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1668
fcf51541
BZ		 1669 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1670
a9dce149
GW		 1671 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1672 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1673 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1674 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1675 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1676 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1677 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1678 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1679
fcf51541
BZ		 1680 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1681 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 1682 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 1683 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1684 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 1685 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 1686 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1687 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1688 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1689
1690 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 1691 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1692 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1693 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1694 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1695 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1696 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1697 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1698 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1699 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1700 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1701 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1702
1703 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 1704 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1705 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1706 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1707 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1708 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1709 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1710 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1711 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1712 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1713 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1714 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1715
1716 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1717 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1718 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1719 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1720 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1721 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1722 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1723 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1724 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1725 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1726 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1727 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1728
1729 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1730 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
a9dce149
GW		 1731 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1732 !rt2x00_is_usb(rt2x00dev));
fcf51541
BZ		 1733 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1734 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1735 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1736 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1737 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1738 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1739 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1740 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1741 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1742
1743 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1744 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1745 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1746 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1747 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1748 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1749 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1750 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1751 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1752 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1753 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1754 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1755
1756 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1757 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1758 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1759 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1760 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1761 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1762 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1763 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1764 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1765 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1766 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1767 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1768
cea90e55 1769 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 1770 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1771
1772 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1773 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1774 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1775 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1776 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1777 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1778 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1779 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1780 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1781 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1782 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1783 }
1784
1785 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1786 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1787
1788 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1789 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1790 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1791 IEEE80211_MAX_RTS_THRESHOLD);
1792 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1793 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1794
1795 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149 1796
a21c2ab4
HS		 1797 /*
1798 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1799 * time should be set to 16. However, the original Ralink driver uses
1800 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1801 * connection problems with 11g + CTS protection. Hence, use the same
1802 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1803 */
a9dce149 1804 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
a21c2ab4
HS		 1805 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1806 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
a9dce149
GW		 1807 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1808 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1809 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1810 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1811
fcf51541
BZ		 1812 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1813
1814 /*
1815 * ASIC will keep garbage value after boot, clear encryption keys.
1816 */
1817 for (i = 0; i < 4; i++)
1818 rt2800_register_write(rt2x00dev,
1819 SHARED_KEY_MODE_ENTRY(i), 0);
1820
1821 for (i = 0; i < 256; i++) {
1822 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1823 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1824 wcid, sizeof(wcid));
1825
1826 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1827 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1828 }
1829
1830 /*
1831 * Clear all beacons
fcf51541 1832 */
fdb87251
HS		 1833 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
1834 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
1835 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
1836 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
1837 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
1838 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
1839 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
1840 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
fcf51541 1841
cea90e55 1842 if (rt2x00_is_usb(rt2x00dev)) {
785c3c06
GW		 1843 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
1844 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
1845 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
fcf51541
BZ		 1846 }
1847
1848 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1849 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1850 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1851 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1852 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1853 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1854 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1855 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1856 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1857 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1858
1859 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1860 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1861 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1862 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1863 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1864 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1865 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1866 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1867 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1868 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1869
1870 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1871 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1872 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1873 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1874 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1875 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1876 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1877 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1878 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1879 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1880
1881 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1882 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1883 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1884 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1885 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1886 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1887
1888 /*
1889 * We must clear the error counters.
1890 * These registers are cleared on read,
1891 * so we may pass a useless variable to store the value.
1892 */
1893 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1894 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1895 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1896 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1897 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1898 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1899
9f926fb5
HS		 1900 /*
1901 * Setup leadtime for pre tbtt interrupt to 6ms
1902 */
1903 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
1904 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
1905 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
1906
fcf51541
BZ		 1907 return 0;
1908}
1909EXPORT_SYMBOL_GPL(rt2800_init_registers);
1910
1911static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1912{
1913 unsigned int i;
1914 u32 reg;
1915
1916 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1917 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1918 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1919 return 0;
1920
1921 udelay(REGISTER_BUSY_DELAY);
1922 }
1923
1924 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1925 return -EACCES;
1926}
1927
1928static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1929{
1930 unsigned int i;
1931 u8 value;
1932
1933 /*
1934 * BBP was enabled after firmware was loaded,
1935 * but we need to reactivate it now.
1936 */
1937 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1938 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1939 msleep(1);
1940
1941 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1942 rt2800_bbp_read(rt2x00dev, 0, &value);
1943 if ((value != 0xff) && (value != 0x00))
1944 return 0;
1945 udelay(REGISTER_BUSY_DELAY);
1946 }
1947
1948 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1949 return -EACCES;
1950}
1951
1952int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1953{
1954 unsigned int i;
1955 u16 eeprom;
1956 u8 reg_id;
1957 u8 value;
1958
1959 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1960 rt2800_wait_bbp_ready(rt2x00dev)))
1961 return -EACCES;
1962
baff8006
HS		 1963 if (rt2800_is_305x_soc(rt2x00dev))
1964 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1965
fcf51541
BZ		 1966 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1967 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 1968
1969 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1970 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1971 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1972 } else {
1973 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1974 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1975 }
1976
fcf51541 1977 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 1978
d5385bfc 1979 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1980 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1981 rt2x00_rt(rt2x00dev, RT3090) ||
1982 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 1983 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1984 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1985 rt2800_bbp_write(rt2x00dev, 81, 0x33);
baff8006
HS		 1986 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1987 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1988 rt2800_bbp_write(rt2x00dev, 80, 0x08);
8cdd15e0
GW		 1989 } else {
1990 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1991 }
1992
fcf51541
BZ		 1993 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1994 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149 1995
5ed8f458 1996 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
a9dce149
GW		 1997 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1998 else
1999 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2000
fcf51541
BZ		 2001 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2002 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2003 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 2004
d5385bfc 2005 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2006 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904 2007 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
baff8006
HS		 2008 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2009 rt2800_is_305x_soc(rt2x00dev))
8cdd15e0
GW		 2010 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2011 else
2012 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2013
baff8006
HS		 2014 if (rt2800_is_305x_soc(rt2x00dev))
2015 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2016 else
2017 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 2018 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 2019
64522957 2020 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2021 rt2x00_rt(rt2x00dev, RT3090) ||
2022 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc 2023 rt2800_bbp_read(rt2x00dev, 138, &value);
fcf51541 2024
d5385bfc
GW		 2025 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2026 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2027 value |= 0x20;
2028 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2029 value &= ~0x02;
fcf51541 2030
d5385bfc 2031 rt2800_bbp_write(rt2x00dev, 138, value);
fcf51541
BZ		 2032 }
2033
fcf51541
BZ		 2034
2035 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2036 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2037
2038 if (eeprom != 0xffff && eeprom != 0x0000) {
2039 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2040 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2041 rt2800_bbp_write(rt2x00dev, reg_id, value);
2042 }
2043 }
2044
2045 return 0;
2046}
2047EXPORT_SYMBOL_GPL(rt2800_init_bbp);
2048
2049static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2050 bool bw40, u8 rfcsr24, u8 filter_target)
2051{
2052 unsigned int i;
2053 u8 bbp;
2054 u8 rfcsr;
2055 u8 passband;
2056 u8 stopband;
2057 u8 overtuned = 0;
2058
2059 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2060
2061 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2062 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2063 rt2800_bbp_write(rt2x00dev, 4, bbp);
2064
2065 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2066 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2067 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2068
2069 /*
2070 * Set power & frequency of passband test tone
2071 */
2072 rt2800_bbp_write(rt2x00dev, 24, 0);
2073
2074 for (i = 0; i < 100; i++) {
2075 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2076 msleep(1);
2077
2078 rt2800_bbp_read(rt2x00dev, 55, &passband);
2079 if (passband)
2080 break;
2081 }
2082
2083 /*
2084 * Set power & frequency of stopband test tone
2085 */
2086 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2087
2088 for (i = 0; i < 100; i++) {
2089 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2090 msleep(1);
2091
2092 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2093
2094 if ((passband - stopband) <= filter_target) {
2095 rfcsr24++;
2096 overtuned += ((passband - stopband) == filter_target);
2097 } else
2098 break;
2099
2100 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2101 }
2102
2103 rfcsr24 -= !!overtuned;
2104
2105 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2106 return rfcsr24;
2107}
2108
2109int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2110{
2111 u8 rfcsr;
2112 u8 bbp;
8cdd15e0
GW		 2113 u32 reg;
2114 u16 eeprom;
fcf51541 2115
d5385bfc 2116 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 2117 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 2118 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383 2119 !rt2x00_rt(rt2x00dev, RT3390) &&
baff8006 2120 !rt2800_is_305x_soc(rt2x00dev))
fcf51541
BZ		 2121 return 0;
2122
fcf51541
BZ		 2123 /*
2124 * Init RF calibration.
2125 */
2126 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2127 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2128 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2129 msleep(1);
2130 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2131 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2132
d5385bfc 2133 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 2134 rt2x00_rt(rt2x00dev, RT3071) ||
2135 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 2136 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2137 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2138 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2139 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2140 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 2141 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 2142 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2143 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2144 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2145 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2146 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2147 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2148 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2149 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2150 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2151 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2152 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2153 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 2154 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 2155 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2156 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2157 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2158 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2159 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
fcf51541 2160 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
cc78e904
GW		 2161 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2162 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2163 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2164 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2165 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2166 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
fcf51541 2167 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
cc78e904
GW		 2168 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2169 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
fcf51541 2170 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
cc78e904
GW		 2171 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2172 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2173 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2174 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2175 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2176 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2177 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
fcf51541 2178 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
cc78e904 2179 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
fcf51541 2180 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
cc78e904
GW		 2181 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2182 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2183 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2184 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2185 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2186 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2187 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
baff8006 2188 } else if (rt2800_is_305x_soc(rt2x00dev)) {
23812383
HS		 2189 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2190 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2191 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2192 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2193 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2194 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2195 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2196 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2197 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2198 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2199 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2200 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2201 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2202 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2203 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2204 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2205 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2206 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2207 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2208 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2209 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2210 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2211 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2212 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2213 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2214 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2215 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2216 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2217 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2218 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
baff8006
HS		 2219 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2220 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2221 return 0;
8cdd15e0
GW		 2222 }
2223
2224 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2225 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2226 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2227 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2228 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 2229 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2230 rt2x00_rt(rt2x00dev, RT3090)) {
d5385bfc
GW		 2231 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2232 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2233 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2234
2235 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2236
2237 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2238 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 2239 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2240 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
d5385bfc
GW		 2241 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2242 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2243 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2244 else
2245 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2246 }
2247 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
cc78e904
GW		 2248 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2249 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2250 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2251 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 2252 }
2253
2254 /*
2255 * Set RX Filter calibration for 20MHz and 40MHz
2256 */
8cdd15e0
GW		 2257 if (rt2x00_rt(rt2x00dev, RT3070)) {
2258 rt2x00dev->calibration[0] =
2259 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2260 rt2x00dev->calibration[1] =
2261 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 2262 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2263 rt2x00_rt(rt2x00dev, RT3090) ||
2264 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2265 rt2x00dev->calibration[0] =
2266 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2267 rt2x00dev->calibration[1] =
2268 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 2269 }
fcf51541
BZ		 2270
2271 /*
2272 * Set back to initial state
2273 */
2274 rt2800_bbp_write(rt2x00dev, 24, 0);
2275
2276 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2277 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2278 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2279
2280 /*
2281 * set BBP back to BW20
2282 */
2283 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2284 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2285 rt2800_bbp_write(rt2x00dev, 4, bbp);
2286
d5385bfc 2287 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 2288 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2289 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2290 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 2291 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2292
2293 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2294 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2295 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2296
2297 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2298 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
64522957 2299 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 2300 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2301 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
8440c292 2302 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
d5385bfc
GW		 2303 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2304 }
8cdd15e0
GW		 2305 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2306 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2307 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2308 rt2x00_get_field16(eeprom,
2309 EEPROM_TXMIXER_GAIN_BG_VAL));
2310 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2311
64522957
GW		 2312 if (rt2x00_rt(rt2x00dev, RT3090)) {
2313 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2314
2315 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2316 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2317 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2318 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2319 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2320
2321 rt2800_bbp_write(rt2x00dev, 138, bbp);
2322 }
2323
2324 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 2325 rt2x00_rt(rt2x00dev, RT3090) ||
2326 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 2327 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2328 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2329 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2330 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2331 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2332 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2333 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2334
2335 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2336 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2337 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2338
2339 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2340 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2341 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2342
2343 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2344 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2345 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2346 }
2347
2348 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
8cdd15e0 2349 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
d5385bfc
GW		 2350 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2351 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
8cdd15e0
GW		 2352 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2353 else
2354 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2355 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2356 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2357 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2358 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2359 }
2360
fcf51541
BZ		 2361 return 0;
2362}
2363EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
2ce33995 2364
30e84034
BZ		 2365int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2366{
2367 u32 reg;
2368
2369 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2370
2371 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2372}
2373EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2374
2375static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2376{
2377 u32 reg;
2378
31a4cf1f
GW		 2379 mutex_lock(&rt2x00dev->csr_mutex);
2380
2381 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 2382 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2383 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2384 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 2385 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 2386
2387 /* Wait until the EEPROM has been loaded */
2388 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2389
2390 /* Apparently the data is read from end to start */
31a4cf1f
GW		 2391 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2392 (u32 *)&rt2x00dev->eeprom[i]);
2393 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2394 (u32 *)&rt2x00dev->eeprom[i + 2]);
2395 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2396 (u32 *)&rt2x00dev->eeprom[i + 4]);
2397 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2398 (u32 *)&rt2x00dev->eeprom[i + 6]);
2399
2400 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 2401}
2402
2403void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2404{
2405 unsigned int i;
2406
2407 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2408 rt2800_efuse_read(rt2x00dev, i);
2409}
2410EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2411
38bd7b8a
BZ		 2412int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2413{
2414 u16 word;
2415 u8 *mac;
2416 u8 default_lna_gain;
2417
2418 /*
2419 * Start validation of the data that has been read.
2420 */
2421 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2422 if (!is_valid_ether_addr(mac)) {
2423 random_ether_addr(mac);
2424 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2425 }
2426
2427 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2428 if (word == 0xffff) {
2429 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2430 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2431 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2432 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2433 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec 2434 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
e148b4c8 2435 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2436 /*
2437 * There is a max of 2 RX streams for RT28x0 series
2438 */
2439 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2440 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2441 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2442 }
2443
2444 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2445 if (word == 0xffff) {
2446 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2447 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2448 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2449 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2450 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2451 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2452 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2453 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2454 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2455 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
ec2d1791
GW		 2456 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2457 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
38bd7b8a
BZ		 2458 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2459 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2460 }
2461
2462 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2463 if ((word & 0x00ff) == 0x00ff) {
2464 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
ec2d1791
GW		 2465 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2466 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2467 }
2468 if ((word & 0xff00) == 0xff00) {
38bd7b8a
BZ		 2469 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2470 LED_MODE_TXRX_ACTIVITY);
2471 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2472 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2473 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2474 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2475 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
ec2d1791 2476 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
38bd7b8a
BZ		 2477 }
2478
2479 /*
2480 * During the LNA validation we are going to use
2481 * lna0 as correct value. Note that EEPROM_LNA
2482 * is never validated.
2483 */
2484 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2485 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2486
2487 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2488 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2489 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2490 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2491 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2492 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2493
2494 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2495 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2496 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2497 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2498 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2499 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2500 default_lna_gain);
2501 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2502
2503 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2504 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2505 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2506 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2507 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2508 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2509
2510 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2511 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2512 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2513 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2514 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2515 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2516 default_lna_gain);
2517 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2518
2519 return 0;
2520}
2521EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2522
2523int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2524{
2525 u32 reg;
2526 u16 value;
2527 u16 eeprom;
2528
2529 /*
2530 * Read EEPROM word for configuration.
2531 */
2532 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2533
2534 /*
2535 * Identify RF chipset.
2536 */
2537 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2538 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2539
49e721ec
GW		 2540 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2541 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2542
2543 if (!rt2x00_rt(rt2x00dev, RT2860) &&
49e721ec 2544 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 2545 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 2546 !rt2x00_rt(rt2x00dev, RT3070) &&
2547 !rt2x00_rt(rt2x00dev, RT3071) &&
2548 !rt2x00_rt(rt2x00dev, RT3090) &&
2549 !rt2x00_rt(rt2x00dev, RT3390) &&
2550 !rt2x00_rt(rt2x00dev, RT3572)) {
2551 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2552 return -ENODEV;
f273fe55 2553 }
714fa663 2554
5122d898
GW		 2555 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2556 !rt2x00_rf(rt2x00dev, RF2850) &&
2557 !rt2x00_rf(rt2x00dev, RF2720) &&
2558 !rt2x00_rf(rt2x00dev, RF2750) &&
2559 !rt2x00_rf(rt2x00dev, RF3020) &&
2560 !rt2x00_rf(rt2x00dev, RF2020) &&
2561 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265
GW		 2562 !rt2x00_rf(rt2x00dev, RF3022) &&
2563 !rt2x00_rf(rt2x00dev, RF3052)) {
38bd7b8a
BZ		 2564 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2565 return -ENODEV;
2566 }
2567
2568 /*
2569 * Identify default antenna configuration.
2570 */
2571 rt2x00dev->default_ant.tx =
2572 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2573 rt2x00dev->default_ant.rx =
2574 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2575
2576 /*
2577 * Read frequency offset and RF programming sequence.
2578 */
2579 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2580 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2581
2582 /*
2583 * Read external LNA informations.
2584 */
2585 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2586
2587 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2588 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2589 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2590 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2591
2592 /*
2593 * Detect if this device has an hardware controlled radio.
2594 */
2595 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2596 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2597
2598 /*
2599 * Store led settings, for correct led behaviour.
2600 */
2601#ifdef CONFIG_RT2X00_LIB_LEDS
2602 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2603 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2604 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2605
2606 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2607#endif /* CONFIG_RT2X00_LIB_LEDS */
2608
2609 return 0;
2610}
2611EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2612
4da2933f 2613/*
55f9321a 2614 * RF value list for rt28xx
4da2933f
BZ		 2615 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2616 */
2617static const struct rf_channel rf_vals[] = {
2618 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2619 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2620 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2621 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2622 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2623 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2624 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2625 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2626 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2627 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2628 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2629 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2630 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2631 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2632
2633 /* 802.11 UNI / HyperLan 2 */
2634 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2635 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2636 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2637 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2638 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2639 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2640 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2641 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2642 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2643 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2644 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2645 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2646
2647 /* 802.11 HyperLan 2 */
2648 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2649 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2650 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2651 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2652 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2653 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2654 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2655 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2656 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2657 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2658 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2659 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2660 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2661 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2662 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2663 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2664
2665 /* 802.11 UNII */
2666 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2667 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2668 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2669 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2670 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2671 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2672 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2673 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2674 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2675 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2676 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2677
2678 /* 802.11 Japan */
2679 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2680 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2681 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2682 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2683 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2684 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2685 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2686};
2687
2688/*
55f9321a
ID		 2689 * RF value list for rt3xxx
2690 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4da2933f 2691 */
55f9321a 2692static const struct rf_channel rf_vals_3x[] = {
4da2933f
BZ		 2693 {1, 241, 2, 2 },
2694 {2, 241, 2, 7 },
2695 {3, 242, 2, 2 },
2696 {4, 242, 2, 7 },
2697 {5, 243, 2, 2 },
2698 {6, 243, 2, 7 },
2699 {7, 244, 2, 2 },
2700 {8, 244, 2, 7 },
2701 {9, 245, 2, 2 },
2702 {10, 245, 2, 7 },
2703 {11, 246, 2, 2 },
2704 {12, 246, 2, 7 },
2705 {13, 247, 2, 2 },
2706 {14, 248, 2, 4 },
55f9321a
ID		 2707
2708 /* 802.11 UNI / HyperLan 2 */
2709 {36, 0x56, 0, 4},
2710 {38, 0x56, 0, 6},
2711 {40, 0x56, 0, 8},
2712 {44, 0x57, 0, 0},
2713 {46, 0x57, 0, 2},
2714 {48, 0x57, 0, 4},
2715 {52, 0x57, 0, 8},
2716 {54, 0x57, 0, 10},
2717 {56, 0x58, 0, 0},
2718 {60, 0x58, 0, 4},
2719 {62, 0x58, 0, 6},
2720 {64, 0x58, 0, 8},
2721
2722 /* 802.11 HyperLan 2 */
2723 {100, 0x5b, 0, 8},
2724 {102, 0x5b, 0, 10},
2725 {104, 0x5c, 0, 0},
2726 {108, 0x5c, 0, 4},
2727 {110, 0x5c, 0, 6},
2728 {112, 0x5c, 0, 8},
2729 {116, 0x5d, 0, 0},
2730 {118, 0x5d, 0, 2},
2731 {120, 0x5d, 0, 4},
2732 {124, 0x5d, 0, 8},
2733 {126, 0x5d, 0, 10},
2734 {128, 0x5e, 0, 0},
2735 {132, 0x5e, 0, 4},
2736 {134, 0x5e, 0, 6},
2737 {136, 0x5e, 0, 8},
2738 {140, 0x5f, 0, 0},
2739
2740 /* 802.11 UNII */
2741 {149, 0x5f, 0, 9},
2742 {151, 0x5f, 0, 11},
2743 {153, 0x60, 0, 1},
2744 {157, 0x60, 0, 5},
2745 {159, 0x60, 0, 7},
2746 {161, 0x60, 0, 9},
2747 {165, 0x61, 0, 1},
2748 {167, 0x61, 0, 3},
2749 {169, 0x61, 0, 5},
2750 {171, 0x61, 0, 7},
2751 {173, 0x61, 0, 9},
4da2933f
BZ		 2752};
2753
2754int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2755{
4da2933f
BZ		 2756 struct hw_mode_spec *spec = &rt2x00dev->spec;
2757 struct channel_info *info;
2758 char *tx_power1;
2759 char *tx_power2;
2760 unsigned int i;
2761 u16 eeprom;
2762
93b6bd26
GW		 2763 /*
2764 * Disable powersaving as default on PCI devices.
2765 */
cea90e55 2766 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 2767 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2768
4da2933f
BZ		 2769 /*
2770 * Initialize all hw fields.
2771 */
2772 rt2x00dev->hw->flags =
2773 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2774 IEEE80211_HW_SIGNAL_DBM |
2775 IEEE80211_HW_SUPPORTS_PS |
1df90809
HS		 2776 IEEE80211_HW_PS_NULLFUNC_STACK |
2777 IEEE80211_HW_AMPDU_AGGREGATION;
4da2933f 2778
4da2933f
BZ		 2779 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2780 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2781 rt2x00_eeprom_addr(rt2x00dev,
2782 EEPROM_MAC_ADDR_0));
2783
3f2bee24
HS		 2784 /*
2785 * As rt2800 has a global fallback table we cannot specify
2786 * more then one tx rate per frame but since the hw will
2787 * try several rates (based on the fallback table) we should
2788 * still initialize max_rates to the maximum number of rates
2789 * we are going to try. Otherwise mac80211 will truncate our
2790 * reported tx rates and the rc algortihm will end up with
2791 * incorrect data.
2792 */
2793 rt2x00dev->hw->max_rates = 7;
2794 rt2x00dev->hw->max_rate_tries = 1;
2795
4da2933f
BZ		 2796 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2797
2798 /*
2799 * Initialize hw_mode information.
2800 */
2801 spec->supported_bands = SUPPORT_BAND_2GHZ;
2802 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2803
5122d898 2804 if (rt2x00_rf(rt2x00dev, RF2820) ||
55f9321a 2805 rt2x00_rf(rt2x00dev, RF2720)) {
4da2933f
BZ		 2806 spec->num_channels = 14;
2807 spec->channels = rf_vals;
55f9321a
ID		 2808 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
2809 rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 2810 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2811 spec->num_channels = ARRAY_SIZE(rf_vals);
2812 spec->channels = rf_vals;
5122d898
GW		 2813 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2814 rt2x00_rf(rt2x00dev, RF2020) ||
2815 rt2x00_rf(rt2x00dev, RF3021) ||
2816 rt2x00_rf(rt2x00dev, RF3022)) {
55f9321a
ID		 2817 spec->num_channels = 14;
2818 spec->channels = rf_vals_3x;
2819 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
2820 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2821 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
2822 spec->channels = rf_vals_3x;
4da2933f
BZ		 2823 }
2824
2825 /*
2826 * Initialize HT information.
2827 */
5122d898 2828 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 2829 spec->ht.ht_supported = true;
2830 else
2831 spec->ht.ht_supported = false;
2832
4da2933f 2833 spec->ht.cap =
06443e46 2834 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4da2933f
BZ		 2835 IEEE80211_HT_CAP_GRN_FLD |
2836 IEEE80211_HT_CAP_SGI_20 |
aa674631 2837 IEEE80211_HT_CAP_SGI_40;
22cabaa6
HS		 2838
2839 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
2840 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
2841
aa674631
ID		 2842 spec->ht.cap |=
2843 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
2844 IEEE80211_HT_CAP_RX_STBC_SHIFT;
2845
4da2933f
BZ		 2846 spec->ht.ampdu_factor = 3;
2847 spec->ht.ampdu_density = 4;
2848 spec->ht.mcs.tx_params =
2849 IEEE80211_HT_MCS_TX_DEFINED |
2850 IEEE80211_HT_MCS_TX_RX_DIFF |
2851 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2852 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2853
2854 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2855 case 3:
2856 spec->ht.mcs.rx_mask[2] = 0xff;
2857 case 2:
2858 spec->ht.mcs.rx_mask[1] = 0xff;
2859 case 1:
2860 spec->ht.mcs.rx_mask[0] = 0xff;
2861 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2862 break;
2863 }
2864
2865 /*
2866 * Create channel information array
2867 */
baeb2ffa 2868 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4da2933f
BZ		 2869 if (!info)
2870 return -ENOMEM;
2871
2872 spec->channels_info = info;
2873
2874 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2875 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2876
2877 for (i = 0; i < 14; i++) {
2878 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2879 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2880 }
2881
2882 if (spec->num_channels > 14) {
2883 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2884 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2885
2886 for (i = 14; i < spec->num_channels; i++) {
2887 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2888 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2889 }
2890 }
2891
2892 return 0;
2893}
2894EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2895
2ce33995
BZ		 2896/*
2897 * IEEE80211 stack callback functions.
2898 */
e783619e
HS		 2899void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
2900 u16 *iv16)
2ce33995
BZ		 2901{
2902 struct rt2x00_dev *rt2x00dev = hw->priv;
2903 struct mac_iveiv_entry iveiv_entry;
2904 u32 offset;
2905
2906 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2907 rt2800_register_multiread(rt2x00dev, offset,
2908 &iveiv_entry, sizeof(iveiv_entry));
2909
855da5e0
JL		 2910 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2911 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995 2912}
e783619e 2913EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2ce33995 2914
e783619e 2915int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2ce33995
BZ		 2916{
2917 struct rt2x00_dev *rt2x00dev = hw->priv;
2918 u32 reg;
2919 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2920
2921 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2922 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2923 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2924
2925 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2926 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2927 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2928
2929 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2930 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2931 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2932
2933 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2934 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2935 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2936
2937 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2938 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2939 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2940
2941 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2942 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2943 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2944
2945 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2946 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2947 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2948
2949 return 0;
2950}
e783619e 2951EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2ce33995 2952
e783619e
HS		 2953int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2954 const struct ieee80211_tx_queue_params *params)
2ce33995
BZ		 2955{
2956 struct rt2x00_dev *rt2x00dev = hw->priv;
2957 struct data_queue *queue;
2958 struct rt2x00_field32 field;
2959 int retval;
2960 u32 reg;
2961 u32 offset;
2962
2963 /*
2964 * First pass the configuration through rt2x00lib, that will
2965 * update the queue settings and validate the input. After that
2966 * we are free to update the registers based on the value
2967 * in the queue parameter.
2968 */
2969 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2970 if (retval)
2971 return retval;
2972
2973 /*
2974 * We only need to perform additional register initialization
2975 * for WMM queues/
2976 */
2977 if (queue_idx >= 4)
2978 return 0;
2979
2980 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2981
2982 /* Update WMM TXOP register */
2983 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2984 field.bit_offset = (queue_idx & 1) * 16;
2985 field.bit_mask = 0xffff << field.bit_offset;
2986
2987 rt2800_register_read(rt2x00dev, offset, &reg);
2988 rt2x00_set_field32(&reg, field, queue->txop);
2989 rt2800_register_write(rt2x00dev, offset, reg);
2990
2991 /* Update WMM registers */
2992 field.bit_offset = queue_idx * 4;
2993 field.bit_mask = 0xf << field.bit_offset;
2994
2995 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2996 rt2x00_set_field32(&reg, field, queue->aifs);
2997 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2998
2999 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3000 rt2x00_set_field32(&reg, field, queue->cw_min);
3001 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3002
3003 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3004 rt2x00_set_field32(&reg, field, queue->cw_max);
3005 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3006
3007 /* Update EDCA registers */
3008 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3009
3010 rt2800_register_read(rt2x00dev, offset, &reg);
3011 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3012 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3013 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3014 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3015 rt2800_register_write(rt2x00dev, offset, reg);
3016
3017 return 0;
3018}
e783619e 3019EXPORT_SYMBOL_GPL(rt2800_conf_tx);
2ce33995 3020
e783619e 3021u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2ce33995
BZ		 3022{
3023 struct rt2x00_dev *rt2x00dev = hw->priv;
3024 u64 tsf;
3025 u32 reg;
3026
3027 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3028 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3029 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3030 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3031
3032 return tsf;
3033}
e783619e 3034EXPORT_SYMBOL_GPL(rt2800_get_tsf);
2ce33995 3035
e783619e
HS		 3036int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3037 enum ieee80211_ampdu_mlme_action action,
3038 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
1df90809 3039{
1df90809
HS		 3040 int ret = 0;
3041
3042 switch (action) {
3043 case IEEE80211_AMPDU_RX_START:
3044 case IEEE80211_AMPDU_RX_STOP:
3045 /* we don't support RX aggregation yet */
3046 ret = -ENOTSUPP;
3047 break;
3048 case IEEE80211_AMPDU_TX_START:
3049 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3050 break;
3051 case IEEE80211_AMPDU_TX_STOP:
3052 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3053 break;
3054 case IEEE80211_AMPDU_TX_OPERATIONAL:
3055 break;
3056 default:
4e9e58c6 3057 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
1df90809
HS		 3058 }
3059
3060 return ret;
3061}
e783619e 3062EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
a5ea2f02
ID		 3063
3064MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3065MODULE_VERSION(DRV_VERSION);
3066MODULE_DESCRIPTION("Ralink RT2800 library");
3067MODULE_LICENSE("GPL");
Clone of davem's net-next-2.6 tree