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wl1271: fix a bunch of sparse warnings
[net-next-2.6.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
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89297425 1/*
9c9a0d14 2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
cce5fc45 3 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
89297425 4
9c9a0d14
GW		 5 Based on the original rt2800pci.c and rt2800usb.c.
6 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
89297425
BZ		 13 <http://rt2x00.serialmonkey.com>
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31/*
32 Module: rt2800lib
33 Abstract: rt2800 generic device routines.
34 */
35
36#include <linux/kernel.h>
37#include <linux/module.h>
38
39#include "rt2x00.h"
ac394917 40#if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
fcf51541
BZ		 41#include "rt2x00usb.h"
42#endif
714fa663
GW		 43#if defined(CONFIG_RT2X00_LIB_PCI) || defined(CONFIG_RT2X00_LIB_PCI_MODULE)
44#include "rt2x00pci.h"
45#endif
89297425
BZ		 46#include "rt2800lib.h"
47#include "rt2800.h"
fcf51541 48#include "rt2800usb.h"
89297425
BZ		 49
50MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
51MODULE_DESCRIPTION("rt2800 library");
52MODULE_LICENSE("GPL");
53
54/*
55 * Register access.
56 * All access to the CSR registers will go through the methods
57 * rt2800_register_read and rt2800_register_write.
58 * BBP and RF register require indirect register access,
59 * and use the CSR registers BBPCSR and RFCSR to achieve this.
60 * These indirect registers work with busy bits,
61 * and we will try maximal REGISTER_BUSY_COUNT times to access
62 * the register while taking a REGISTER_BUSY_DELAY us delay
63 * between each attampt. When the busy bit is still set at that time,
64 * the access attempt is considered to have failed,
65 * and we will print an error.
66 * The _lock versions must be used if you already hold the csr_mutex
67 */
68#define WAIT_FOR_BBP(__dev, __reg) \
69 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
70#define WAIT_FOR_RFCSR(__dev, __reg) \
71 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
72#define WAIT_FOR_RF(__dev, __reg) \
73 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
74#define WAIT_FOR_MCU(__dev, __reg) \
75 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
76 H2M_MAILBOX_CSR_OWNER, (__reg))
77
fcf51541
BZ		 78static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
79 const unsigned int word, const u8 value)
89297425
BZ		 80{
81 u32 reg;
82
83 mutex_lock(&rt2x00dev->csr_mutex);
84
85 /*
86 * Wait until the BBP becomes available, afterwards we
87 * can safely write the new data into the register.
88 */
89 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
90 reg = 0;
91 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
92 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
93 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
94 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
cea90e55 95 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
89297425
BZ		 96 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
97
98 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
99 }
100
101 mutex_unlock(&rt2x00dev->csr_mutex);
102}
89297425 103
fcf51541
BZ		 104static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
105 const unsigned int word, u8 *value)
89297425
BZ		 106{
107 u32 reg;
108
109 mutex_lock(&rt2x00dev->csr_mutex);
110
111 /*
112 * Wait until the BBP becomes available, afterwards we
113 * can safely write the read request into the register.
114 * After the data has been written, we wait until hardware
115 * returns the correct value, if at any time the register
116 * doesn't become available in time, reg will be 0xffffffff
117 * which means we return 0xff to the caller.
118 */
119 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
120 reg = 0;
121 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
122 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
123 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
cea90e55 124 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
89297425
BZ		 125 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
126
127 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
128
129 WAIT_FOR_BBP(rt2x00dev, &reg);
130 }
131
132 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
133
134 mutex_unlock(&rt2x00dev->csr_mutex);
135}
89297425 136
fcf51541
BZ		 137static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
138 const unsigned int word, const u8 value)
89297425
BZ		 139{
140 u32 reg;
141
142 mutex_lock(&rt2x00dev->csr_mutex);
143
144 /*
145 * Wait until the RFCSR becomes available, afterwards we
146 * can safely write the new data into the register.
147 */
148 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
149 reg = 0;
150 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
151 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
152 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
153 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
154
155 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
156 }
157
158 mutex_unlock(&rt2x00dev->csr_mutex);
159}
89297425 160
fcf51541
BZ		 161static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
162 const unsigned int word, u8 *value)
89297425
BZ		 163{
164 u32 reg;
165
166 mutex_lock(&rt2x00dev->csr_mutex);
167
168 /*
169 * Wait until the RFCSR becomes available, afterwards we
170 * can safely write the read request into the register.
171 * After the data has been written, we wait until hardware
172 * returns the correct value, if at any time the register
173 * doesn't become available in time, reg will be 0xffffffff
174 * which means we return 0xff to the caller.
175 */
176 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
177 reg = 0;
178 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
179 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
180 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
181
182 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
183
184 WAIT_FOR_RFCSR(rt2x00dev, &reg);
185 }
186
187 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
188
189 mutex_unlock(&rt2x00dev->csr_mutex);
190}
89297425 191
fcf51541
BZ		 192static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
193 const unsigned int word, const u32 value)
89297425
BZ		 194{
195 u32 reg;
196
197 mutex_lock(&rt2x00dev->csr_mutex);
198
199 /*
200 * Wait until the RF becomes available, afterwards we
201 * can safely write the new data into the register.
202 */
203 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
204 reg = 0;
205 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
206 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
207 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
208 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
209
210 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
211 rt2x00_rf_write(rt2x00dev, word, value);
212 }
213
214 mutex_unlock(&rt2x00dev->csr_mutex);
215}
89297425
BZ		 216
217void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
218 const u8 command, const u8 token,
219 const u8 arg0, const u8 arg1)
220{
221 u32 reg;
222
ee303e54 223 /*
cea90e55 224 * SOC devices don't support MCU requests.
ee303e54 225 */
cea90e55 226 if (rt2x00_is_soc(rt2x00dev))
ee303e54 227 return;
89297425
BZ		 228
229 mutex_lock(&rt2x00dev->csr_mutex);
230
231 /*
232 * Wait until the MCU becomes available, afterwards we
233 * can safely write the new data into the register.
234 */
235 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
236 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
237 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
238 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
239 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
240 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
241
242 reg = 0;
243 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
244 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
245 }
246
247 mutex_unlock(&rt2x00dev->csr_mutex);
248}
249EXPORT_SYMBOL_GPL(rt2800_mcu_request);
f4450616 250
67a4c1e2
GW		 251int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
252{
253 unsigned int i;
254 u32 reg;
255
256 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
257 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
258 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
259 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
260 return 0;
261
262 msleep(1);
263 }
264
265 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
266 return -EACCES;
267}
268EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
269
f4450616
BZ		 270#ifdef CONFIG_RT2X00_LIB_DEBUGFS
271const struct rt2x00debug rt2800_rt2x00debug = {
272 .owner = THIS_MODULE,
273 .csr = {
274 .read = rt2800_register_read,
275 .write = rt2800_register_write,
276 .flags = RT2X00DEBUGFS_OFFSET,
277 .word_base = CSR_REG_BASE,
278 .word_size = sizeof(u32),
279 .word_count = CSR_REG_SIZE / sizeof(u32),
280 },
281 .eeprom = {
282 .read = rt2x00_eeprom_read,
283 .write = rt2x00_eeprom_write,
284 .word_base = EEPROM_BASE,
285 .word_size = sizeof(u16),
286 .word_count = EEPROM_SIZE / sizeof(u16),
287 },
288 .bbp = {
289 .read = rt2800_bbp_read,
290 .write = rt2800_bbp_write,
291 .word_base = BBP_BASE,
292 .word_size = sizeof(u8),
293 .word_count = BBP_SIZE / sizeof(u8),
294 },
295 .rf = {
296 .read = rt2x00_rf_read,
297 .write = rt2800_rf_write,
298 .word_base = RF_BASE,
299 .word_size = sizeof(u32),
300 .word_count = RF_SIZE / sizeof(u32),
301 },
302};
303EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
304#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
305
306int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
307{
308 u32 reg;
309
310 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
311 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
312}
313EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
314
315#ifdef CONFIG_RT2X00_LIB_LEDS
316static void rt2800_brightness_set(struct led_classdev *led_cdev,
317 enum led_brightness brightness)
318{
319 struct rt2x00_led *led =
320 container_of(led_cdev, struct rt2x00_led, led_dev);
321 unsigned int enabled = brightness != LED_OFF;
322 unsigned int bg_mode =
323 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
324 unsigned int polarity =
325 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
326 EEPROM_FREQ_LED_POLARITY);
327 unsigned int ledmode =
328 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
329 EEPROM_FREQ_LED_MODE);
330
331 if (led->type == LED_TYPE_RADIO) {
332 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
333 enabled ? 0x20 : 0);
334 } else if (led->type == LED_TYPE_ASSOC) {
335 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
336 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
337 } else if (led->type == LED_TYPE_QUALITY) {
338 /*
339 * The brightness is divided into 6 levels (0 - 5),
340 * The specs tell us the following levels:
341 * 0, 1 ,3, 7, 15, 31
342 * to determine the level in a simple way we can simply
343 * work with bitshifting:
344 * (1 << level) - 1
345 */
346 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
347 (1 << brightness / (LED_FULL / 6)) - 1,
348 polarity);
349 }
350}
351
352static int rt2800_blink_set(struct led_classdev *led_cdev,
353 unsigned long *delay_on, unsigned long *delay_off)
354{
355 struct rt2x00_led *led =
356 container_of(led_cdev, struct rt2x00_led, led_dev);
357 u32 reg;
358
359 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
360 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
361 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
f4450616
BZ		 362 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
363
364 return 0;
365}
366
b3579d6a 367static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
f4450616
BZ		 368 struct rt2x00_led *led, enum led_type type)
369{
370 led->rt2x00dev = rt2x00dev;
371 led->type = type;
372 led->led_dev.brightness_set = rt2800_brightness_set;
373 led->led_dev.blink_set = rt2800_blink_set;
374 led->flags = LED_INITIALIZED;
375}
f4450616
BZ		 376#endif /* CONFIG_RT2X00_LIB_LEDS */
377
378/*
379 * Configuration handlers.
380 */
381static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
382 struct rt2x00lib_crypto *crypto,
383 struct ieee80211_key_conf *key)
384{
385 struct mac_wcid_entry wcid_entry;
386 struct mac_iveiv_entry iveiv_entry;
387 u32 offset;
388 u32 reg;
389
390 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
391
392 rt2800_register_read(rt2x00dev, offset, &reg);
393 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
394 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
395 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
396 (crypto->cmd == SET_KEY) * crypto->cipher);
397 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
398 (crypto->cmd == SET_KEY) * crypto->bssidx);
399 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
400 rt2800_register_write(rt2x00dev, offset, reg);
401
402 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
403
404 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
405 if ((crypto->cipher == CIPHER_TKIP) ||
406 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
407 (crypto->cipher == CIPHER_AES))
408 iveiv_entry.iv[3] |= 0x20;
409 iveiv_entry.iv[3] |= key->keyidx << 6;
410 rt2800_register_multiwrite(rt2x00dev, offset,
411 &iveiv_entry, sizeof(iveiv_entry));
412
413 offset = MAC_WCID_ENTRY(key->hw_key_idx);
414
415 memset(&wcid_entry, 0, sizeof(wcid_entry));
416 if (crypto->cmd == SET_KEY)
417 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
418 rt2800_register_multiwrite(rt2x00dev, offset,
419 &wcid_entry, sizeof(wcid_entry));
420}
421
422int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
423 struct rt2x00lib_crypto *crypto,
424 struct ieee80211_key_conf *key)
425{
426 struct hw_key_entry key_entry;
427 struct rt2x00_field32 field;
428 u32 offset;
429 u32 reg;
430
431 if (crypto->cmd == SET_KEY) {
432 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
433
434 memcpy(key_entry.key, crypto->key,
435 sizeof(key_entry.key));
436 memcpy(key_entry.tx_mic, crypto->tx_mic,
437 sizeof(key_entry.tx_mic));
438 memcpy(key_entry.rx_mic, crypto->rx_mic,
439 sizeof(key_entry.rx_mic));
440
441 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
442 rt2800_register_multiwrite(rt2x00dev, offset,
443 &key_entry, sizeof(key_entry));
444 }
445
446 /*
447 * The cipher types are stored over multiple registers
448 * starting with SHARED_KEY_MODE_BASE each word will have
449 * 32 bits and contains the cipher types for 2 bssidx each.
450 * Using the correct defines correctly will cause overhead,
451 * so just calculate the correct offset.
452 */
453 field.bit_offset = 4 * (key->hw_key_idx % 8);
454 field.bit_mask = 0x7 << field.bit_offset;
455
456 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
457
458 rt2800_register_read(rt2x00dev, offset, &reg);
459 rt2x00_set_field32(&reg, field,
460 (crypto->cmd == SET_KEY) * crypto->cipher);
461 rt2800_register_write(rt2x00dev, offset, reg);
462
463 /*
464 * Update WCID information
465 */
466 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
467
468 return 0;
469}
470EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
471
472int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
473 struct rt2x00lib_crypto *crypto,
474 struct ieee80211_key_conf *key)
475{
476 struct hw_key_entry key_entry;
477 u32 offset;
478
479 if (crypto->cmd == SET_KEY) {
480 /*
481 * 1 pairwise key is possible per AID, this means that the AID
482 * equals our hw_key_idx. Make sure the WCID starts _after_ the
483 * last possible shared key entry.
484 */
485 if (crypto->aid > (256 - 32))
486 return -ENOSPC;
487
488 key->hw_key_idx = 32 + crypto->aid;
489
490 memcpy(key_entry.key, crypto->key,
491 sizeof(key_entry.key));
492 memcpy(key_entry.tx_mic, crypto->tx_mic,
493 sizeof(key_entry.tx_mic));
494 memcpy(key_entry.rx_mic, crypto->rx_mic,
495 sizeof(key_entry.rx_mic));
496
497 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
498 rt2800_register_multiwrite(rt2x00dev, offset,
499 &key_entry, sizeof(key_entry));
500 }
501
502 /*
503 * Update WCID information
504 */
505 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
506
507 return 0;
508}
509EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
510
511void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
512 const unsigned int filter_flags)
513{
514 u32 reg;
515
516 /*
517 * Start configuration steps.
518 * Note that the version error will always be dropped
519 * and broadcast frames will always be accepted since
520 * there is no filter for it at this time.
521 */
522 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
523 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
524 !(filter_flags & FIF_FCSFAIL));
525 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
526 !(filter_flags & FIF_PLCPFAIL));
527 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
528 !(filter_flags & FIF_PROMISC_IN_BSS));
529 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
530 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
531 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
532 !(filter_flags & FIF_ALLMULTI));
533 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
534 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
535 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
536 !(filter_flags & FIF_CONTROL));
537 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
538 !(filter_flags & FIF_CONTROL));
539 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
540 !(filter_flags & FIF_CONTROL));
541 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
542 !(filter_flags & FIF_CONTROL));
543 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
544 !(filter_flags & FIF_CONTROL));
545 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
546 !(filter_flags & FIF_PSPOLL));
547 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
548 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
549 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
550 !(filter_flags & FIF_CONTROL));
551 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
552}
553EXPORT_SYMBOL_GPL(rt2800_config_filter);
554
555void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
556 struct rt2x00intf_conf *conf, const unsigned int flags)
557{
558 unsigned int beacon_base;
559 u32 reg;
560
561 if (flags & CONFIG_UPDATE_TYPE) {
562 /*
563 * Clear current synchronisation setup.
564 * For the Beacon base registers we only need to clear
565 * the first byte since that byte contains the VALID and OWNER
566 * bits which (when set to 0) will invalidate the entire beacon.
567 */
568 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
569 rt2800_register_write(rt2x00dev, beacon_base, 0);
570
571 /*
572 * Enable synchronisation.
573 */
574 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
575 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
576 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
6a62e5ef
JB		 577 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
578 (conf->sync == TSF_SYNC_BEACON));
f4450616
BZ		 579 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
580 }
581
582 if (flags & CONFIG_UPDATE_MAC) {
583 reg = le32_to_cpu(conf->mac[1]);
584 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
585 conf->mac[1] = cpu_to_le32(reg);
586
587 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
588 conf->mac, sizeof(conf->mac));
589 }
590
591 if (flags & CONFIG_UPDATE_BSSID) {
592 reg = le32_to_cpu(conf->bssid[1]);
593 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
594 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
595 conf->bssid[1] = cpu_to_le32(reg);
596
597 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
598 conf->bssid, sizeof(conf->bssid));
599 }
600}
601EXPORT_SYMBOL_GPL(rt2800_config_intf);
602
603void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
604{
605 u32 reg;
606
f4450616
BZ		 607 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
608 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
609 !!erp->short_preamble);
610 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
611 !!erp->short_preamble);
612 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
613
614 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
615 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
616 erp->cts_protection ? 2 : 0);
617 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
618
619 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
620 erp->basic_rates);
621 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
622
623 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
624 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
f4450616
BZ		 625 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
626
627 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
628 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
629 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
f4450616 630 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
f4450616
BZ		 631 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
632
633 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
634 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
635 erp->beacon_int * 16);
636 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
637}
638EXPORT_SYMBOL_GPL(rt2800_config_erp);
639
640void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
641{
642 u8 r1;
643 u8 r3;
644
645 rt2800_bbp_read(rt2x00dev, 1, &r1);
646 rt2800_bbp_read(rt2x00dev, 3, &r3);
647
648 /*
649 * Configure the TX antenna.
650 */
651 switch ((int)ant->tx) {
652 case 1:
653 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
cea90e55 654 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
f4450616
BZ		 655 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
656 break;
657 case 2:
658 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
659 break;
660 case 3:
661 /* Do nothing */
662 break;
663 }
664
665 /*
666 * Configure the RX antenna.
667 */
668 switch ((int)ant->rx) {
669 case 1:
670 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
671 break;
672 case 2:
673 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
674 break;
675 case 3:
676 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
677 break;
678 }
679
680 rt2800_bbp_write(rt2x00dev, 3, r3);
681 rt2800_bbp_write(rt2x00dev, 1, r1);
682}
683EXPORT_SYMBOL_GPL(rt2800_config_ant);
684
685static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
686 struct rt2x00lib_conf *libconf)
687{
688 u16 eeprom;
689 short lna_gain;
690
691 if (libconf->rf.channel <= 14) {
692 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
693 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
694 } else if (libconf->rf.channel <= 64) {
695 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
696 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
697 } else if (libconf->rf.channel <= 128) {
698 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
699 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
700 } else {
701 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
702 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
703 }
704
705 rt2x00dev->lna_gain = lna_gain;
706}
707
06855ef4
GW		 708static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
709 struct ieee80211_conf *conf,
710 struct rf_channel *rf,
711 struct channel_info *info)
f4450616
BZ		 712{
713 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
714
715 if (rt2x00dev->default_ant.tx == 1)
716 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
717
718 if (rt2x00dev->default_ant.rx == 1) {
719 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
720 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
721 } else if (rt2x00dev->default_ant.rx == 2)
722 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
723
724 if (rf->channel > 14) {
725 /*
726 * When TX power is below 0, we should increase it by 7 to
727 * make it a positive value (Minumum value is -7).
728 * However this means that values between 0 and 7 have
729 * double meaning, and we should set a 7DBm boost flag.
730 */
731 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
732 (info->tx_power1 >= 0));
733
734 if (info->tx_power1 < 0)
735 info->tx_power1 += 7;
736
737 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
738 TXPOWER_A_TO_DEV(info->tx_power1));
739
740 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
741 (info->tx_power2 >= 0));
742
743 if (info->tx_power2 < 0)
744 info->tx_power2 += 7;
745
746 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
747 TXPOWER_A_TO_DEV(info->tx_power2));
748 } else {
749 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
750 TXPOWER_G_TO_DEV(info->tx_power1));
751 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
752 TXPOWER_G_TO_DEV(info->tx_power2));
753 }
754
755 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
756
757 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
758 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
759 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
760 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
761
762 udelay(200);
763
764 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
765 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
766 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
767 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
768
769 udelay(200);
770
771 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
772 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
773 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
774 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
775}
776
06855ef4
GW		 777static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
778 struct ieee80211_conf *conf,
779 struct rf_channel *rf,
780 struct channel_info *info)
f4450616
BZ		 781{
782 u8 rfcsr;
783
784 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
41a26170 785 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
f4450616
BZ		 786
787 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
fab799c3 788 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
f4450616
BZ		 789 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
790
791 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
792 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
793 TXPOWER_G_TO_DEV(info->tx_power1));
794 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
795
5a673964
HS		 796 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
797 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
798 TXPOWER_G_TO_DEV(info->tx_power2));
799 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
800
f4450616
BZ		 801 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
802 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
803 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
804
805 rt2800_rfcsr_write(rt2x00dev, 24,
806 rt2x00dev->calibration[conf_is_ht40(conf)]);
807
71976907 808 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
f4450616 809 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
71976907 810 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
f4450616
BZ		 811}
812
813static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
814 struct ieee80211_conf *conf,
815 struct rf_channel *rf,
816 struct channel_info *info)
817{
818 u32 reg;
819 unsigned int tx_pin;
820 u8 bbp;
821
06855ef4
GW		 822 if (rt2x00_rf(rt2x00dev, RF2020) ||
823 rt2x00_rf(rt2x00dev, RF3020) ||
824 rt2x00_rf(rt2x00dev, RF3021) ||
825 rt2x00_rf(rt2x00dev, RF3022))
826 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
fa6f632f 827 else
06855ef4 828 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
f4450616
BZ		 829
830 /*
831 * Change BBP settings
832 */
833 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
834 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
835 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
836 rt2800_bbp_write(rt2x00dev, 86, 0);
837
838 if (rf->channel <= 14) {
839 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
840 rt2800_bbp_write(rt2x00dev, 82, 0x62);
841 rt2800_bbp_write(rt2x00dev, 75, 0x46);
842 } else {
843 rt2800_bbp_write(rt2x00dev, 82, 0x84);
844 rt2800_bbp_write(rt2x00dev, 75, 0x50);
845 }
846 } else {
847 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
848
849 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
850 rt2800_bbp_write(rt2x00dev, 75, 0x46);
851 else
852 rt2800_bbp_write(rt2x00dev, 75, 0x50);
853 }
854
855 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
856 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
857 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
858 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
859 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
860
861 tx_pin = 0;
862
863 /* Turn on unused PA or LNA when not using 1T or 1R */
864 if (rt2x00dev->default_ant.tx != 1) {
865 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
866 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
867 }
868
869 /* Turn on unused PA or LNA when not using 1T or 1R */
870 if (rt2x00dev->default_ant.rx != 1) {
871 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
872 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
873 }
874
875 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
876 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
877 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
878 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
879 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
880 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
881
882 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
883
884 rt2800_bbp_read(rt2x00dev, 4, &bbp);
885 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
886 rt2800_bbp_write(rt2x00dev, 4, bbp);
887
888 rt2800_bbp_read(rt2x00dev, 3, &bbp);
889 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
890 rt2800_bbp_write(rt2x00dev, 3, bbp);
891
8d0c9b65 892 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
f4450616
BZ		 893 if (conf_is_ht40(conf)) {
894 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
895 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
896 rt2800_bbp_write(rt2x00dev, 73, 0x16);
897 } else {
898 rt2800_bbp_write(rt2x00dev, 69, 0x16);
899 rt2800_bbp_write(rt2x00dev, 70, 0x08);
900 rt2800_bbp_write(rt2x00dev, 73, 0x11);
901 }
902 }
903
904 msleep(1);
905}
906
907static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
908 const int txpower)
909{
910 u32 reg;
911 u32 value = TXPOWER_G_TO_DEV(txpower);
912 u8 r1;
913
914 rt2800_bbp_read(rt2x00dev, 1, &r1);
915 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
916 rt2800_bbp_write(rt2x00dev, 1, r1);
917
918 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
919 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
920 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
921 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
922 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
923 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
924 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
925 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
926 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
927 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
928
929 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
930 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
931 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
932 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
933 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
934 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
935 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
936 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
937 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
938 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
939
940 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
941 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
942 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
943 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
944 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
945 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
946 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
947 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
948 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
949 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
950
951 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
952 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
953 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
954 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
955 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
956 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
957 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
958 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
959 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
960 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
961
962 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
963 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
964 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
965 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
966 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
967 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
968}
969
970static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
971 struct rt2x00lib_conf *libconf)
972{
973 u32 reg;
974
975 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
976 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
977 libconf->conf->short_frame_max_tx_count);
978 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
979 libconf->conf->long_frame_max_tx_count);
f4450616
BZ		 980 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
981}
982
983static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
984 struct rt2x00lib_conf *libconf)
985{
986 enum dev_state state =
987 (libconf->conf->flags & IEEE80211_CONF_PS) ?
988 STATE_SLEEP : STATE_AWAKE;
989 u32 reg;
990
991 if (state == STATE_SLEEP) {
992 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
993
994 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
995 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
996 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
997 libconf->conf->listen_interval - 1);
998 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
999 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1000
1001 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1002 } else {
f4450616
BZ		 1003 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1004 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1005 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1006 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1007 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5731858d
GW		 1008
1009 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
f4450616
BZ		 1010 }
1011}
1012
1013void rt2800_config(struct rt2x00_dev *rt2x00dev,
1014 struct rt2x00lib_conf *libconf,
1015 const unsigned int flags)
1016{
1017 /* Always recalculate LNA gain before changing configuration */
1018 rt2800_config_lna_gain(rt2x00dev, libconf);
1019
1020 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1021 rt2800_config_channel(rt2x00dev, libconf->conf,
1022 &libconf->rf, &libconf->channel);
1023 if (flags & IEEE80211_CONF_CHANGE_POWER)
1024 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1025 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1026 rt2800_config_retry_limit(rt2x00dev, libconf);
1027 if (flags & IEEE80211_CONF_CHANGE_PS)
1028 rt2800_config_ps(rt2x00dev, libconf);
1029}
1030EXPORT_SYMBOL_GPL(rt2800_config);
1031
1032/*
1033 * Link tuning
1034 */
1035void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1036{
1037 u32 reg;
1038
1039 /*
1040 * Update FCS error count from register.
1041 */
1042 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1043 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1044}
1045EXPORT_SYMBOL_GPL(rt2800_link_stats);
1046
1047static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1048{
1049 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
d5385bfc 1050 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1051 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1052 rt2x00_rt(rt2x00dev, RT3090) ||
1053 rt2x00_rt(rt2x00dev, RT3390))
f4450616
BZ		 1054 return 0x1c + (2 * rt2x00dev->lna_gain);
1055 else
1056 return 0x2e + rt2x00dev->lna_gain;
1057 }
1058
1059 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1060 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1061 else
1062 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1063}
1064
1065static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1066 struct link_qual *qual, u8 vgc_level)
1067{
1068 if (qual->vgc_level != vgc_level) {
1069 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1070 qual->vgc_level = vgc_level;
1071 qual->vgc_level_reg = vgc_level;
1072 }
1073}
1074
1075void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1076{
1077 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1078}
1079EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1080
1081void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1082 const u32 count)
1083{
8d0c9b65 1084 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
f4450616
BZ		 1085 return;
1086
1087 /*
1088 * When RSSI is better then -80 increase VGC level with 0x10
1089 */
1090 rt2800_set_vgc(rt2x00dev, qual,
1091 rt2800_get_default_vgc(rt2x00dev) +
1092 ((qual->rssi > -80) * 0x10));
1093}
1094EXPORT_SYMBOL_GPL(rt2800_link_tuner);
fcf51541
BZ		 1095
1096/*
1097 * Initialization functions.
1098 */
1099int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1100{
1101 u32 reg;
d5385bfc 1102 u16 eeprom;
fcf51541
BZ		 1103 unsigned int i;
1104
a9dce149
GW		 1105 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1106 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1107 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1108 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1109 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1110 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1111 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1112
cea90e55 1113 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541 1114 /*
235faf9b 1115 * Wait until BBP and RF are ready.
fcf51541
BZ		 1116 */
1117 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1118 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1119 if (reg && reg != ~0)
1120 break;
1121 msleep(1);
1122 }
1123
1124 if (i == REGISTER_BUSY_COUNT) {
1125 ERROR(rt2x00dev, "Unstable hardware.\n");
1126 return -EBUSY;
1127 }
1128
1129 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1130 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1131 reg & ~0x00002000);
a9dce149
GW		 1132 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1133 /*
1134 * Reset DMA indexes
1135 */
1136 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1137 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1138 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1139 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1140 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1141 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1142 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1143 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1144 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1145
1146 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1147 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1148
fcf51541 1149 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
a9dce149 1150 }
fcf51541
BZ		 1151
1152 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1153 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1154 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1155 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1156
cea90e55 1157 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541 1158 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
ac394917 1159#if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
fcf51541
BZ		 1160 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1161 USB_MODE_RESET, REGISTER_TIMEOUT);
1162#endif
1163 }
1164
1165 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1166
1167 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1168 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1169 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1170 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1171 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1172 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1173
1174 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1175 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1176 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1177 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1178 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1179 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1180
1181 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1182 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1183
1184 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1185
1186 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1187 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1188 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1189 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1190 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1191 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1192 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1193 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1194
a9dce149
GW		 1195 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1196
1197 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1198 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1199 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1200 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1201
64522957 1202 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1203 rt2x00_rt(rt2x00dev, RT3090) ||
1204 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 1205 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1206 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
64522957 1207 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1208 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1209 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1210 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1211 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1212 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1213 0x0000002c);
1214 else
1215 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1216 0x0000000f);
1217 } else {
1218 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1219 }
1220 rt2800_register_write(rt2x00dev, TX_SW_CFG2, reg);
1221 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
fcf51541 1222 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
8cdd15e0
GW		 1223
1224 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1225 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1226 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1227 } else {
1228 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1229 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1230 }
fcf51541
BZ		 1231 } else {
1232 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1233 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1234 }
1235
1236 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1237 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1238 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1239 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1240 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1241 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1242 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1243 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1244 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1245 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1246
1247 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1248 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
a9dce149 1249 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
fcf51541
BZ		 1250 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1251 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1252
1253 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1254 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
8d0c9b65 1255 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
49e721ec 1256 rt2x00_rt(rt2x00dev, RT2883) ||
8d0c9b65 1257 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
fcf51541
BZ		 1258 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1259 else
1260 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1261 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1262 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1263 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1264
a9dce149
GW		 1265 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1266 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1267 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1268 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1269 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1270 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1271 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1272 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1273 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1274
fcf51541
BZ		 1275 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1276
a9dce149
GW		 1277 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1278 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1279 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1280 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1281 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1282 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1283 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1284 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1285
fcf51541
BZ		 1286 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1287 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
a9dce149 1288 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
fcf51541
BZ		 1289 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1290 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
a9dce149 1291 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
fcf51541
BZ		 1292 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1293 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1294 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1295
1296 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
a9dce149 1297 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1298 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1299 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1300 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1301 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1302 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1303 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1304 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1305 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1306 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1307 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1308
1309 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
a9dce149 1310 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
fcf51541
BZ		 1311 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1312 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1313 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1314 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1315 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
a9dce149 1316 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
fcf51541 1317 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
a9dce149
GW		 1318 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1319 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
fcf51541
BZ		 1320 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1321
1322 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1323 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1324 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1325 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1326 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1327 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1328 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1329 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1330 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1331 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1332 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1333 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1334
1335 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1336 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
a9dce149
GW		 1337 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1338 !rt2x00_is_usb(rt2x00dev));
fcf51541
BZ		 1339 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1340 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1341 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1342 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1343 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1344 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1345 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1346 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1347 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1348
1349 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1350 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1351 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1352 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1353 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1354 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1355 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1356 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1357 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1358 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
a9dce149 1359 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1360 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1361
1362 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1363 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1364 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1365 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1366 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1367 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1368 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1369 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1370 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1371 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
a9dce149 1372 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
fcf51541
BZ		 1373 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1374
cea90e55 1375 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 1376 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1377
1378 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1379 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1380 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1381 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1382 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1383 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1384 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1385 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1386 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1387 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1388 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1389 }
1390
1391 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1392 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1393
1394 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1395 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1396 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1397 IEEE80211_MAX_RTS_THRESHOLD);
1398 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1399 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1400
1401 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
a9dce149
GW		 1402
1403 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1404 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 32);
1405 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 32);
1406 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1407 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1408 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1409 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1410
fcf51541
BZ		 1411 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1412
1413 /*
1414 * ASIC will keep garbage value after boot, clear encryption keys.
1415 */
1416 for (i = 0; i < 4; i++)
1417 rt2800_register_write(rt2x00dev,
1418 SHARED_KEY_MODE_ENTRY(i), 0);
1419
1420 for (i = 0; i < 256; i++) {
1421 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1422 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1423 wcid, sizeof(wcid));
1424
1425 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1426 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1427 }
1428
1429 /*
1430 * Clear all beacons
1431 * For the Beacon base registers we only need to clear
1432 * the first byte since that byte contains the VALID and OWNER
1433 * bits which (when set to 0) will invalidate the entire beacon.
1434 */
1435 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1436 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1437 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1438 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1439 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1440 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1441 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1442 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1443
cea90e55 1444 if (rt2x00_is_usb(rt2x00dev)) {
fcf51541
BZ		 1445 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1446 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1447 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1448 }
1449
1450 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1451 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1452 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1453 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1454 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1455 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1456 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1457 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1458 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1459 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1460
1461 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1462 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1463 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1464 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1465 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1466 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1467 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1468 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1469 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1470 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1471
1472 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1473 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1474 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1475 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1476 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1477 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1478 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1479 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1480 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1481 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1482
1483 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1484 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1485 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1486 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1487 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1488 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1489
1490 /*
1491 * We must clear the error counters.
1492 * These registers are cleared on read,
1493 * so we may pass a useless variable to store the value.
1494 */
1495 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1496 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1497 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1498 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1499 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1500 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1501
1502 return 0;
1503}
1504EXPORT_SYMBOL_GPL(rt2800_init_registers);
1505
1506static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1507{
1508 unsigned int i;
1509 u32 reg;
1510
1511 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1512 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1513 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1514 return 0;
1515
1516 udelay(REGISTER_BUSY_DELAY);
1517 }
1518
1519 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1520 return -EACCES;
1521}
1522
1523static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1524{
1525 unsigned int i;
1526 u8 value;
1527
1528 /*
1529 * BBP was enabled after firmware was loaded,
1530 * but we need to reactivate it now.
1531 */
1532 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1533 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1534 msleep(1);
1535
1536 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1537 rt2800_bbp_read(rt2x00dev, 0, &value);
1538 if ((value != 0xff) && (value != 0x00))
1539 return 0;
1540 udelay(REGISTER_BUSY_DELAY);
1541 }
1542
1543 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1544 return -EACCES;
1545}
1546
1547int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1548{
1549 unsigned int i;
1550 u16 eeprom;
1551 u8 reg_id;
1552 u8 value;
1553
1554 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1555 rt2800_wait_bbp_ready(rt2x00dev)))
1556 return -EACCES;
1557
1558 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1559 rt2800_bbp_write(rt2x00dev, 66, 0x38);
a9dce149
GW		 1560
1561 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1562 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1563 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1564 } else {
1565 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1566 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1567 }
1568
fcf51541 1569 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
8cdd15e0 1570
d5385bfc 1571 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957 1572 rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1573 rt2x00_rt(rt2x00dev, RT3090) ||
1574 rt2x00_rt(rt2x00dev, RT3390)) {
8cdd15e0
GW		 1575 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1576 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1577 rt2800_bbp_write(rt2x00dev, 81, 0x33);
1578 } else {
1579 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1580 }
1581
fcf51541
BZ		 1582 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1583 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
a9dce149
GW		 1584
1585 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D) ||
1586 rt2x00_rt_rev(rt2x00dev, RT2870, REV_RT2870D))
1587 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1588 else
1589 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1590
fcf51541
BZ		 1591 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1592 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1593 rt2800_bbp_write(rt2x00dev, 92, 0x00);
8cdd15e0 1594
d5385bfc 1595 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 1596 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1597 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
1598 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 1599 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1600 else
1601 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1602
fcf51541 1603 rt2800_bbp_write(rt2x00dev, 105, 0x05);
a9dce149 1604 rt2800_bbp_write(rt2x00dev, 106, 0x35);
fcf51541 1605
64522957 1606 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1607 rt2x00_rt(rt2x00dev, RT3090) ||
1608 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 1609 rt2800_bbp_read(rt2x00dev, 138, &value);
1610
1611 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1612 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1613 value |= 0x20;
1614 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1615 value &= ~0x02;
1616
1617 rt2800_bbp_write(rt2x00dev, 138, value);
1618 }
1619
e148b4c8
GW		 1620 if (rt2x00_rt(rt2x00dev, RT2872)) {
1621 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1622 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1623 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1624 }
1625
fcf51541
BZ		 1626 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1627 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1628
1629 if (eeprom != 0xffff && eeprom != 0x0000) {
1630 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1631 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1632 rt2800_bbp_write(rt2x00dev, reg_id, value);
1633 }
1634 }
1635
1636 return 0;
1637}
1638EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1639
1640static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1641 bool bw40, u8 rfcsr24, u8 filter_target)
1642{
1643 unsigned int i;
1644 u8 bbp;
1645 u8 rfcsr;
1646 u8 passband;
1647 u8 stopband;
1648 u8 overtuned = 0;
1649
1650 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1651
1652 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1653 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1654 rt2800_bbp_write(rt2x00dev, 4, bbp);
1655
1656 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1657 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1658 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1659
1660 /*
1661 * Set power & frequency of passband test tone
1662 */
1663 rt2800_bbp_write(rt2x00dev, 24, 0);
1664
1665 for (i = 0; i < 100; i++) {
1666 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1667 msleep(1);
1668
1669 rt2800_bbp_read(rt2x00dev, 55, &passband);
1670 if (passband)
1671 break;
1672 }
1673
1674 /*
1675 * Set power & frequency of stopband test tone
1676 */
1677 rt2800_bbp_write(rt2x00dev, 24, 0x06);
1678
1679 for (i = 0; i < 100; i++) {
1680 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1681 msleep(1);
1682
1683 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1684
1685 if ((passband - stopband) <= filter_target) {
1686 rfcsr24++;
1687 overtuned += ((passband - stopband) == filter_target);
1688 } else
1689 break;
1690
1691 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1692 }
1693
1694 rfcsr24 -= !!overtuned;
1695
1696 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1697 return rfcsr24;
1698}
1699
1700int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1701{
1702 u8 rfcsr;
1703 u8 bbp;
8cdd15e0
GW		 1704 u32 reg;
1705 u16 eeprom;
fcf51541 1706
d5385bfc 1707 if (!rt2x00_rt(rt2x00dev, RT3070) &&
64522957 1708 !rt2x00_rt(rt2x00dev, RT3071) &&
cc78e904 1709 !rt2x00_rt(rt2x00dev, RT3090) &&
23812383
HS		 1710 !rt2x00_rt(rt2x00dev, RT3390) &&
1711 !(rt2x00_is_soc(rt2x00dev) && rt2x00_rt(rt2x00dev, RT2872)))
fcf51541
BZ		 1712 return 0;
1713
fcf51541
BZ		 1714 /*
1715 * Init RF calibration.
1716 */
1717 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1718 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1719 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1720 msleep(1);
1721 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1722 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1723
d5385bfc 1724 if (rt2x00_rt(rt2x00dev, RT3070) ||
64522957
GW		 1725 rt2x00_rt(rt2x00dev, RT3071) ||
1726 rt2x00_rt(rt2x00dev, RT3090)) {
fcf51541
BZ		 1727 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1728 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1729 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1730 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1731 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
8cdd15e0 1732 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
fcf51541
BZ		 1733 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1734 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1735 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1736 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1737 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1738 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1739 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1740 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1741 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1742 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1743 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1744 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
fcf51541 1745 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
cc78e904
GW		 1746 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1747 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
1748 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
1749 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
1750 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
1751 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1752 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
1753 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
1754 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
1755 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1756 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1757 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
1758 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1759 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
1760 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
1761 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1762 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1763 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
1764 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
1765 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
1766 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
1767 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
1768 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
1769 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1770 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
1771 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1772 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1773 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1774 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1775 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
1776 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
1777 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
1778 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
23812383
HS		 1779 } else if (rt2x00_rt(rt2x00dev, RT2872)) {
1780 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1781 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1782 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1783 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1784 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1785 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1786 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1787 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1788 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1789 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1790 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1791 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1792 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1793 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1794 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1795 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1796 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1797 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1798 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1799 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1800 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1801 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1802 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1803 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1804 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1805 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1806 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1807 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1808 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1809 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
8cdd15e0
GW		 1810 }
1811
1812 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1813 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1814 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1815 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1816 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
64522957
GW		 1817 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1818 rt2x00_rt(rt2x00dev, RT3090)) {
d5385bfc
GW		 1819 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1820 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
1821 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1822
1823 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
1824
1825 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1826 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
64522957
GW		 1827 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1828 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
d5385bfc
GW		 1829 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1830 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1831 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1832 else
1833 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
1834 }
1835 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
cc78e904
GW		 1836 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1837 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1838 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
1839 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
fcf51541
BZ		 1840 }
1841
1842 /*
1843 * Set RX Filter calibration for 20MHz and 40MHz
1844 */
8cdd15e0
GW		 1845 if (rt2x00_rt(rt2x00dev, RT3070)) {
1846 rt2x00dev->calibration[0] =
1847 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1848 rt2x00dev->calibration[1] =
1849 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
64522957 1850 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1851 rt2x00_rt(rt2x00dev, RT3090) ||
1852 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 1853 rt2x00dev->calibration[0] =
1854 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
1855 rt2x00dev->calibration[1] =
1856 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
8cdd15e0 1857 }
fcf51541
BZ		 1858
1859 /*
1860 * Set back to initial state
1861 */
1862 rt2800_bbp_write(rt2x00dev, 24, 0);
1863
1864 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1865 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1866 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1867
1868 /*
1869 * set BBP back to BW20
1870 */
1871 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1872 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1873 rt2800_bbp_write(rt2x00dev, 4, bbp);
1874
d5385bfc 1875 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
64522957 1876 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1877 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1878 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
8cdd15e0
GW		 1879 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1880
1881 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
1882 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
1883 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
1884
1885 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1886 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
64522957 1887 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
cc78e904
GW		 1888 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1889 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
d5385bfc
GW		 1890 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1891 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1892 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
1893 }
8cdd15e0
GW		 1894 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
1895 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
1896 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
1897 rt2x00_get_field16(eeprom,
1898 EEPROM_TXMIXER_GAIN_BG_VAL));
1899 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1900
64522957
GW		 1901 if (rt2x00_rt(rt2x00dev, RT3090)) {
1902 rt2800_bbp_read(rt2x00dev, 138, &bbp);
1903
1904 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1905 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1906 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
1907 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1908 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
1909
1910 rt2800_bbp_write(rt2x00dev, 138, bbp);
1911 }
1912
1913 if (rt2x00_rt(rt2x00dev, RT3071) ||
cc78e904
GW		 1914 rt2x00_rt(rt2x00dev, RT3090) ||
1915 rt2x00_rt(rt2x00dev, RT3390)) {
d5385bfc
GW		 1916 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1917 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1918 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1919 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1920 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1921 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1922 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1923
1924 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
1925 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
1926 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
1927
1928 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
1929 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
1930 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
1931
1932 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
1933 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
1934 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
1935 }
1936
1937 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
8cdd15e0 1938 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
d5385bfc
GW		 1939 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1940 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
8cdd15e0
GW		 1941 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
1942 else
1943 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
1944 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
1945 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
1946 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
1947 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
1948 }
1949
fcf51541
BZ		 1950 return 0;
1951}
1952EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
2ce33995 1953
30e84034
BZ		 1954int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1955{
1956 u32 reg;
1957
1958 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1959
1960 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1961}
1962EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1963
1964static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1965{
1966 u32 reg;
1967
31a4cf1f
GW		 1968 mutex_lock(&rt2x00dev->csr_mutex);
1969
1970 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
30e84034
BZ		 1971 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1972 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1973 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
31a4cf1f 1974 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
30e84034
BZ		 1975
1976 /* Wait until the EEPROM has been loaded */
1977 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
1978
1979 /* Apparently the data is read from end to start */
31a4cf1f
GW		 1980 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
1981 (u32 *)&rt2x00dev->eeprom[i]);
1982 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
1983 (u32 *)&rt2x00dev->eeprom[i + 2]);
1984 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
1985 (u32 *)&rt2x00dev->eeprom[i + 4]);
1986 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
1987 (u32 *)&rt2x00dev->eeprom[i + 6]);
1988
1989 mutex_unlock(&rt2x00dev->csr_mutex);
30e84034
BZ		 1990}
1991
1992void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
1993{
1994 unsigned int i;
1995
1996 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
1997 rt2800_efuse_read(rt2x00dev, i);
1998}
1999EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2000
38bd7b8a
BZ		 2001int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2002{
2003 u16 word;
2004 u8 *mac;
2005 u8 default_lna_gain;
2006
2007 /*
2008 * Start validation of the data that has been read.
2009 */
2010 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2011 if (!is_valid_ether_addr(mac)) {
2012 random_ether_addr(mac);
2013 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2014 }
2015
2016 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2017 if (word == 0xffff) {
2018 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2019 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2020 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2021 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2022 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
49e721ec
GW		 2023 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2024 rt2x00_rt(rt2x00dev, RT2870) ||
e148b4c8 2025 rt2x00_rt(rt2x00dev, RT2872)) {
38bd7b8a
BZ		 2026 /*
2027 * There is a max of 2 RX streams for RT28x0 series
2028 */
2029 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2030 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2031 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2032 }
2033
2034 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2035 if (word == 0xffff) {
2036 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2037 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2038 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2039 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2040 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2041 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2042 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2043 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2044 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2045 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2046 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2047 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2048 }
2049
2050 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2051 if ((word & 0x00ff) == 0x00ff) {
2052 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2053 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2054 LED_MODE_TXRX_ACTIVITY);
2055 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2056 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2057 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2058 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2059 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2060 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2061 }
2062
2063 /*
2064 * During the LNA validation we are going to use
2065 * lna0 as correct value. Note that EEPROM_LNA
2066 * is never validated.
2067 */
2068 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2069 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2070
2071 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2072 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2073 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2074 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2075 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2076 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2077
2078 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2079 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2080 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2081 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2082 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2083 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2084 default_lna_gain);
2085 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2086
2087 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2088 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2089 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2090 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2091 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2092 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2093
2094 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2095 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2096 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2097 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2098 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2099 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2100 default_lna_gain);
2101 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2102
2103 return 0;
2104}
2105EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2106
2107int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2108{
2109 u32 reg;
2110 u16 value;
2111 u16 eeprom;
2112
2113 /*
2114 * Read EEPROM word for configuration.
2115 */
2116 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2117
2118 /*
2119 * Identify RF chipset.
2120 */
2121 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2122 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2123
49e721ec
GW		 2124 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2125 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2126
2127 if (!rt2x00_rt(rt2x00dev, RT2860) &&
2128 !rt2x00_rt(rt2x00dev, RT2870) &&
2129 !rt2x00_rt(rt2x00dev, RT2872) &&
49e721ec 2130 !rt2x00_rt(rt2x00dev, RT2883) &&
49e721ec
GW		 2131 !rt2x00_rt(rt2x00dev, RT3070) &&
2132 !rt2x00_rt(rt2x00dev, RT3071) &&
2133 !rt2x00_rt(rt2x00dev, RT3090) &&
2134 !rt2x00_rt(rt2x00dev, RT3390) &&
2135 !rt2x00_rt(rt2x00dev, RT3572)) {
2136 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2137 return -ENODEV;
f273fe55 2138 }
714fa663 2139
5122d898
GW		 2140 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2141 !rt2x00_rf(rt2x00dev, RF2850) &&
2142 !rt2x00_rf(rt2x00dev, RF2720) &&
2143 !rt2x00_rf(rt2x00dev, RF2750) &&
2144 !rt2x00_rf(rt2x00dev, RF3020) &&
2145 !rt2x00_rf(rt2x00dev, RF2020) &&
2146 !rt2x00_rf(rt2x00dev, RF3021) &&
6c0fe265
GW		 2147 !rt2x00_rf(rt2x00dev, RF3022) &&
2148 !rt2x00_rf(rt2x00dev, RF3052)) {
38bd7b8a
BZ		 2149 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2150 return -ENODEV;
2151 }
2152
2153 /*
2154 * Identify default antenna configuration.
2155 */
2156 rt2x00dev->default_ant.tx =
2157 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2158 rt2x00dev->default_ant.rx =
2159 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2160
2161 /*
2162 * Read frequency offset and RF programming sequence.
2163 */
2164 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2165 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2166
2167 /*
2168 * Read external LNA informations.
2169 */
2170 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2171
2172 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2173 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2174 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2175 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2176
2177 /*
2178 * Detect if this device has an hardware controlled radio.
2179 */
2180 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2181 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2182
2183 /*
2184 * Store led settings, for correct led behaviour.
2185 */
2186#ifdef CONFIG_RT2X00_LIB_LEDS
2187 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2188 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2189 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2190
2191 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2192#endif /* CONFIG_RT2X00_LIB_LEDS */
2193
2194 return 0;
2195}
2196EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2197
4da2933f
BZ		 2198/*
2199 * RF value list for rt28x0
2200 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2201 */
2202static const struct rf_channel rf_vals[] = {
2203 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2204 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2205 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2206 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2207 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2208 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2209 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2210 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2211 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2212 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2213 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2214 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2215 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2216 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2217
2218 /* 802.11 UNI / HyperLan 2 */
2219 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2220 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2221 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2222 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2223 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2224 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2225 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2226 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2227 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2228 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2229 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2230 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2231
2232 /* 802.11 HyperLan 2 */
2233 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2234 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2235 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2236 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2237 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2238 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2239 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2240 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2241 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2242 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2243 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2244 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2245 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2246 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2247 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2248 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2249
2250 /* 802.11 UNII */
2251 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2252 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2253 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2254 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2255 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2256 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2257 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2258 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2259 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2260 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2261 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2262
2263 /* 802.11 Japan */
2264 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2265 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2266 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2267 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2268 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2269 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2270 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2271};
2272
2273/*
2274 * RF value list for rt3070
2275 * Supports: 2.4 GHz
2276 */
cce5fc45 2277static const struct rf_channel rf_vals_302x[] = {
4da2933f
BZ		 2278 {1, 241, 2, 2 },
2279 {2, 241, 2, 7 },
2280 {3, 242, 2, 2 },
2281 {4, 242, 2, 7 },
2282 {5, 243, 2, 2 },
2283 {6, 243, 2, 7 },
2284 {7, 244, 2, 2 },
2285 {8, 244, 2, 7 },
2286 {9, 245, 2, 2 },
2287 {10, 245, 2, 7 },
2288 {11, 246, 2, 2 },
2289 {12, 246, 2, 7 },
2290 {13, 247, 2, 2 },
2291 {14, 248, 2, 4 },
2292};
2293
2294int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2295{
4da2933f
BZ		 2296 struct hw_mode_spec *spec = &rt2x00dev->spec;
2297 struct channel_info *info;
2298 char *tx_power1;
2299 char *tx_power2;
2300 unsigned int i;
2301 u16 eeprom;
2302
93b6bd26
GW		 2303 /*
2304 * Disable powersaving as default on PCI devices.
2305 */
cea90e55 2306 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
93b6bd26
GW		 2307 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2308
4da2933f
BZ		 2309 /*
2310 * Initialize all hw fields.
2311 */
2312 rt2x00dev->hw->flags =
2313 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2314 IEEE80211_HW_SIGNAL_DBM |
2315 IEEE80211_HW_SUPPORTS_PS |
2316 IEEE80211_HW_PS_NULLFUNC_STACK;
2317
4da2933f
BZ		 2318 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2319 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2320 rt2x00_eeprom_addr(rt2x00dev,
2321 EEPROM_MAC_ADDR_0));
2322
2323 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2324
2325 /*
2326 * Initialize hw_mode information.
2327 */
2328 spec->supported_bands = SUPPORT_BAND_2GHZ;
2329 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2330
5122d898
GW		 2331 if (rt2x00_rf(rt2x00dev, RF2820) ||
2332 rt2x00_rf(rt2x00dev, RF2720) ||
6c0fe265 2333 rt2x00_rf(rt2x00dev, RF3052)) {
4da2933f
BZ		 2334 spec->num_channels = 14;
2335 spec->channels = rf_vals;
5122d898 2336 } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) {
4da2933f
BZ		 2337 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2338 spec->num_channels = ARRAY_SIZE(rf_vals);
2339 spec->channels = rf_vals;
5122d898
GW		 2340 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2341 rt2x00_rf(rt2x00dev, RF2020) ||
2342 rt2x00_rf(rt2x00dev, RF3021) ||
2343 rt2x00_rf(rt2x00dev, RF3022)) {
cce5fc45
GW		 2344 spec->num_channels = ARRAY_SIZE(rf_vals_302x);
2345 spec->channels = rf_vals_302x;
4da2933f
BZ		 2346 }
2347
2348 /*
2349 * Initialize HT information.
2350 */
5122d898 2351 if (!rt2x00_rf(rt2x00dev, RF2020))
38a522e6
GW		 2352 spec->ht.ht_supported = true;
2353 else
2354 spec->ht.ht_supported = false;
2355
2caaa5d3
HS		 2356 /*
2357 * Don't set IEEE80211_HT_CAP_SUP_WIDTH_20_40 for now as it causes
2358 * reception problems with HT40 capable 11n APs
2359 */
4da2933f 2360 spec->ht.cap =
4da2933f
BZ		 2361 IEEE80211_HT_CAP_GRN_FLD |
2362 IEEE80211_HT_CAP_SGI_20 |
2363 IEEE80211_HT_CAP_SGI_40 |
2364 IEEE80211_HT_CAP_TX_STBC |
9a418af5 2365 IEEE80211_HT_CAP_RX_STBC;
4da2933f
BZ		 2366 spec->ht.ampdu_factor = 3;
2367 spec->ht.ampdu_density = 4;
2368 spec->ht.mcs.tx_params =
2369 IEEE80211_HT_MCS_TX_DEFINED |
2370 IEEE80211_HT_MCS_TX_RX_DIFF |
2371 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2372 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2373
2374 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2375 case 3:
2376 spec->ht.mcs.rx_mask[2] = 0xff;
2377 case 2:
2378 spec->ht.mcs.rx_mask[1] = 0xff;
2379 case 1:
2380 spec->ht.mcs.rx_mask[0] = 0xff;
2381 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2382 break;
2383 }
2384
2385 /*
2386 * Create channel information array
2387 */
2388 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2389 if (!info)
2390 return -ENOMEM;
2391
2392 spec->channels_info = info;
2393
2394 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2395 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2396
2397 for (i = 0; i < 14; i++) {
2398 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2399 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2400 }
2401
2402 if (spec->num_channels > 14) {
2403 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2404 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2405
2406 for (i = 14; i < spec->num_channels; i++) {
2407 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2408 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2409 }
2410 }
2411
2412 return 0;
2413}
2414EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2415
2ce33995
BZ		 2416/*
2417 * IEEE80211 stack callback functions.
2418 */
2419static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2420 u32 *iv32, u16 *iv16)
2421{
2422 struct rt2x00_dev *rt2x00dev = hw->priv;
2423 struct mac_iveiv_entry iveiv_entry;
2424 u32 offset;
2425
2426 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2427 rt2800_register_multiread(rt2x00dev, offset,
2428 &iveiv_entry, sizeof(iveiv_entry));
2429
855da5e0
JL		 2430 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2431 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2ce33995
BZ		 2432}
2433
2434static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2435{
2436 struct rt2x00_dev *rt2x00dev = hw->priv;
2437 u32 reg;
2438 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2439
2440 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2441 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2442 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2443
2444 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2445 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2446 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2447
2448 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2449 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2450 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2451
2452 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2453 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2454 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2455
2456 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2457 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2458 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2459
2460 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2461 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2462 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2463
2464 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2465 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2466 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2467
2468 return 0;
2469}
2470
2471static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2472 const struct ieee80211_tx_queue_params *params)
2473{
2474 struct rt2x00_dev *rt2x00dev = hw->priv;
2475 struct data_queue *queue;
2476 struct rt2x00_field32 field;
2477 int retval;
2478 u32 reg;
2479 u32 offset;
2480
2481 /*
2482 * First pass the configuration through rt2x00lib, that will
2483 * update the queue settings and validate the input. After that
2484 * we are free to update the registers based on the value
2485 * in the queue parameter.
2486 */
2487 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2488 if (retval)
2489 return retval;
2490
2491 /*
2492 * We only need to perform additional register initialization
2493 * for WMM queues/
2494 */
2495 if (queue_idx >= 4)
2496 return 0;
2497
2498 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2499
2500 /* Update WMM TXOP register */
2501 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2502 field.bit_offset = (queue_idx & 1) * 16;
2503 field.bit_mask = 0xffff << field.bit_offset;
2504
2505 rt2800_register_read(rt2x00dev, offset, &reg);
2506 rt2x00_set_field32(&reg, field, queue->txop);
2507 rt2800_register_write(rt2x00dev, offset, reg);
2508
2509 /* Update WMM registers */
2510 field.bit_offset = queue_idx * 4;
2511 field.bit_mask = 0xf << field.bit_offset;
2512
2513 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2514 rt2x00_set_field32(&reg, field, queue->aifs);
2515 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2516
2517 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2518 rt2x00_set_field32(&reg, field, queue->cw_min);
2519 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2520
2521 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2522 rt2x00_set_field32(&reg, field, queue->cw_max);
2523 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2524
2525 /* Update EDCA registers */
2526 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2527
2528 rt2800_register_read(rt2x00dev, offset, &reg);
2529 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2530 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2531 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2532 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2533 rt2800_register_write(rt2x00dev, offset, reg);
2534
2535 return 0;
2536}
2537
2538static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2539{
2540 struct rt2x00_dev *rt2x00dev = hw->priv;
2541 u64 tsf;
2542 u32 reg;
2543
2544 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2545 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2546 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2547 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2548
2549 return tsf;
2550}
2551
2552const struct ieee80211_ops rt2800_mac80211_ops = {
2553 .tx = rt2x00mac_tx,
2554 .start = rt2x00mac_start,
2555 .stop = rt2x00mac_stop,
2556 .add_interface = rt2x00mac_add_interface,
2557 .remove_interface = rt2x00mac_remove_interface,
2558 .config = rt2x00mac_config,
2559 .configure_filter = rt2x00mac_configure_filter,
2560 .set_tim = rt2x00mac_set_tim,
2561 .set_key = rt2x00mac_set_key,
2562 .get_stats = rt2x00mac_get_stats,
2563 .get_tkip_seq = rt2800_get_tkip_seq,
2564 .set_rts_threshold = rt2800_set_rts_threshold,
2565 .bss_info_changed = rt2x00mac_bss_info_changed,
2566 .conf_tx = rt2800_conf_tx,
2ce33995
BZ		 2567 .get_tsf = rt2800_get_tsf,
2568 .rfkill_poll = rt2x00mac_rfkill_poll,
2569};
2570EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);
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