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[net-next-2.6.git] / drivers / net / wireless / p54 / p54common.c
CommitLineData
eff1a59c
MW
1/*
2 * Common code for mac80211 Prism54 drivers
3 *
4 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
5 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
c12abae3 6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
eff1a59c 7 *
27df605e
JL
8 * Based on:
9 * - the islsm (softmac prism54) driver, which is:
10 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
11 * - stlc45xx driver
9483407d 12 * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
eff1a59c
MW
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/init.h>
20#include <linux/firmware.h>
21#include <linux/etherdevice.h>
22
23#include <net/mac80211.h>
d8cd7eff 24#ifdef CONFIG_P54_LEDS
d0b45aef 25#include <linux/leds.h>
d8cd7eff 26#endif /* CONFIG_P54_LEDS */
eff1a59c
MW
27
28#include "p54.h"
29#include "p54common.h"
30
25900ef0
CL
31static int modparam_nohwcrypt;
32module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
33MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
eff1a59c
MW
34MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
35MODULE_DESCRIPTION("Softmac Prism54 common code");
36MODULE_LICENSE("GPL");
37MODULE_ALIAS("prism54common");
38
1b997534 39static struct ieee80211_rate p54_bgrates[] = {
8318d78a
JB
40 { .bitrate = 10, .hw_value = 0, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
41 { .bitrate = 20, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
42 { .bitrate = 55, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
43 { .bitrate = 110, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
44 { .bitrate = 60, .hw_value = 4, },
45 { .bitrate = 90, .hw_value = 5, },
46 { .bitrate = 120, .hw_value = 6, },
47 { .bitrate = 180, .hw_value = 7, },
48 { .bitrate = 240, .hw_value = 8, },
49 { .bitrate = 360, .hw_value = 9, },
50 { .bitrate = 480, .hw_value = 10, },
51 { .bitrate = 540, .hw_value = 11, },
52};
53
1b997534 54static struct ieee80211_channel p54_bgchannels[] = {
8318d78a
JB
55 { .center_freq = 2412, .hw_value = 1, },
56 { .center_freq = 2417, .hw_value = 2, },
57 { .center_freq = 2422, .hw_value = 3, },
58 { .center_freq = 2427, .hw_value = 4, },
59 { .center_freq = 2432, .hw_value = 5, },
60 { .center_freq = 2437, .hw_value = 6, },
61 { .center_freq = 2442, .hw_value = 7, },
62 { .center_freq = 2447, .hw_value = 8, },
63 { .center_freq = 2452, .hw_value = 9, },
64 { .center_freq = 2457, .hw_value = 10, },
65 { .center_freq = 2462, .hw_value = 11, },
66 { .center_freq = 2467, .hw_value = 12, },
67 { .center_freq = 2472, .hw_value = 13, },
68 { .center_freq = 2484, .hw_value = 14, },
69};
70
c2976ab0 71static struct ieee80211_supported_band band_2GHz = {
1b997534
CL
72 .channels = p54_bgchannels,
73 .n_channels = ARRAY_SIZE(p54_bgchannels),
74 .bitrates = p54_bgrates,
75 .n_bitrates = ARRAY_SIZE(p54_bgrates),
76};
77
78static struct ieee80211_rate p54_arates[] = {
79 { .bitrate = 60, .hw_value = 4, },
80 { .bitrate = 90, .hw_value = 5, },
81 { .bitrate = 120, .hw_value = 6, },
82 { .bitrate = 180, .hw_value = 7, },
83 { .bitrate = 240, .hw_value = 8, },
84 { .bitrate = 360, .hw_value = 9, },
85 { .bitrate = 480, .hw_value = 10, },
86 { .bitrate = 540, .hw_value = 11, },
87};
88
89static struct ieee80211_channel p54_achannels[] = {
90 { .center_freq = 4920 },
91 { .center_freq = 4940 },
92 { .center_freq = 4960 },
93 { .center_freq = 4980 },
94 { .center_freq = 5040 },
95 { .center_freq = 5060 },
96 { .center_freq = 5080 },
97 { .center_freq = 5170 },
98 { .center_freq = 5180 },
99 { .center_freq = 5190 },
100 { .center_freq = 5200 },
101 { .center_freq = 5210 },
102 { .center_freq = 5220 },
103 { .center_freq = 5230 },
104 { .center_freq = 5240 },
105 { .center_freq = 5260 },
106 { .center_freq = 5280 },
107 { .center_freq = 5300 },
108 { .center_freq = 5320 },
109 { .center_freq = 5500 },
110 { .center_freq = 5520 },
111 { .center_freq = 5540 },
112 { .center_freq = 5560 },
113 { .center_freq = 5580 },
114 { .center_freq = 5600 },
115 { .center_freq = 5620 },
116 { .center_freq = 5640 },
117 { .center_freq = 5660 },
118 { .center_freq = 5680 },
119 { .center_freq = 5700 },
120 { .center_freq = 5745 },
121 { .center_freq = 5765 },
122 { .center_freq = 5785 },
123 { .center_freq = 5805 },
124 { .center_freq = 5825 },
125};
126
127static struct ieee80211_supported_band band_5GHz = {
128 .channels = p54_achannels,
129 .n_channels = ARRAY_SIZE(p54_achannels),
130 .bitrates = p54_arates,
131 .n_bitrates = ARRAY_SIZE(p54_arates),
8318d78a
JB
132};
133
4e416a6f 134int p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
eff1a59c
MW
135{
136 struct p54_common *priv = dev->priv;
137 struct bootrec_exp_if *exp_if;
138 struct bootrec *bootrec;
139 u32 *data = (u32 *)fw->data;
140 u32 *end_data = (u32 *)fw->data + (fw->size >> 2);
141 u8 *fw_version = NULL;
142 size_t len;
143 int i;
51fb80fe 144 int maxlen;
eff1a59c
MW
145
146 if (priv->rx_start)
4e416a6f 147 return 0;
eff1a59c
MW
148
149 while (data < end_data && *data)
150 data++;
151
152 while (data < end_data && !*data)
153 data++;
154
155 bootrec = (struct bootrec *) data;
156
157 while (bootrec->data <= end_data &&
158 (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) {
159 u32 code = le32_to_cpu(bootrec->code);
160 switch (code) {
161 case BR_CODE_COMPONENT_ID:
1f1c0e33
LF
162 priv->fw_interface = be32_to_cpup((__be32 *)
163 bootrec->data);
2b80848e 164 switch (priv->fw_interface) {
eff1a59c 165 case FW_LM86:
02e37ba1
CL
166 case FW_LM20:
167 case FW_LM87: {
168 char *iftype = (char *)bootrec->data;
169 printk(KERN_INFO "%s: p54 detected a LM%c%c "
170 "firmware\n",
171 wiphy_name(dev->wiphy),
172 iftype[2], iftype[3]);
eff1a59c 173 break;
02e37ba1
CL
174 }
175 case FW_FMAC:
eff1a59c 176 default:
02e37ba1
CL
177 printk(KERN_ERR "%s: unsupported firmware\n",
178 wiphy_name(dev->wiphy));
179 return -ENODEV;
eff1a59c
MW
180 }
181 break;
182 case BR_CODE_COMPONENT_VERSION:
183 /* 24 bytes should be enough for all firmwares */
184 if (strnlen((unsigned char*)bootrec->data, 24) < 24)
185 fw_version = (unsigned char*)bootrec->data;
186 break;
4e416a6f
CL
187 case BR_CODE_DESCR: {
188 struct bootrec_desc *desc =
189 (struct bootrec_desc *)bootrec->data;
190 priv->rx_start = le32_to_cpu(desc->rx_start);
eff1a59c 191 /* FIXME add sanity checking */
4e416a6f
CL
192 priv->rx_end = le32_to_cpu(desc->rx_end) - 0x3500;
193 priv->headroom = desc->headroom;
194 priv->tailroom = desc->tailroom;
25900ef0
CL
195 priv->privacy_caps = desc->privacy_caps;
196 priv->rx_keycache_size = desc->rx_keycache_size;
1f1c0e33 197 if (le32_to_cpu(bootrec->len) == 11)
2e20cc39 198 priv->rx_mtu = le16_to_cpu(desc->rx_mtu);
4e416a6f
CL
199 else
200 priv->rx_mtu = (size_t)
201 0x620 - priv->tx_hdr_len;
51fb80fe
LF
202 maxlen = priv->tx_hdr_len + /* USB devices */
203 sizeof(struct p54_rx_data) +
204 4 + /* rx alignment */
205 IEEE80211_MAX_FRAG_THRESHOLD;
206 if (priv->rx_mtu > maxlen && PAGE_SIZE == 4096) {
207 printk(KERN_INFO "p54: rx_mtu reduced from %d "
208 "to %d\n", priv->rx_mtu,
209 maxlen);
210 priv->rx_mtu = maxlen;
211 }
eff1a59c 212 break;
4e416a6f 213 }
eff1a59c
MW
214 case BR_CODE_EXPOSED_IF:
215 exp_if = (struct bootrec_exp_if *) bootrec->data;
216 for (i = 0; i < (len * sizeof(*exp_if) / 4); i++)
dc73c623 217 if (exp_if[i].if_id == cpu_to_le16(0x1a))
eff1a59c
MW
218 priv->fw_var = le16_to_cpu(exp_if[i].variant);
219 break;
220 case BR_CODE_DEPENDENT_IF:
221 break;
222 case BR_CODE_END_OF_BRA:
223 case LEGACY_BR_CODE_END_OF_BRA:
224 end_data = NULL;
225 break;
226 default:
227 break;
228 }
229 bootrec = (struct bootrec *)&bootrec->data[len];
230 }
231
232 if (fw_version)
02e37ba1
CL
233 printk(KERN_INFO "%s: FW rev %s - Softmac protocol %x.%x\n",
234 wiphy_name(dev->wiphy), fw_version,
235 priv->fw_var >> 8, priv->fw_var & 0xff);
eff1a59c 236
9a8675d7 237 if (priv->fw_var < 0x500)
02e37ba1 238 printk(KERN_INFO "%s: you are using an obsolete firmware. "
9a8675d7 239 "visit http://wireless.kernel.org/en/users/Drivers/p54 "
02e37ba1
CL
240 "and grab one for \"kernel >= 2.6.28\"!\n",
241 wiphy_name(dev->wiphy));
9a8675d7 242
eff1a59c
MW
243 if (priv->fw_var >= 0x300) {
244 /* Firmware supports QoS, use it! */
a15bd005
CL
245 priv->tx_stats[P54_QUEUE_AC_VO].limit = 3;
246 priv->tx_stats[P54_QUEUE_AC_VI].limit = 4;
247 priv->tx_stats[P54_QUEUE_AC_BE].limit = 3;
248 priv->tx_stats[P54_QUEUE_AC_BK].limit = 2;
249 dev->queues = P54_QUEUE_AC_NUM;
eff1a59c 250 }
4e416a6f 251
6dfe9a88 252 if (!modparam_nohwcrypt) {
25900ef0
CL
253 printk(KERN_INFO "%s: cryptographic accelerator "
254 "WEP:%s, TKIP:%s, CCMP:%s\n",
255 wiphy_name(dev->wiphy),
256 (priv->privacy_caps & BR_DESC_PRIV_CAP_WEP) ? "YES" :
257 "no", (priv->privacy_caps & (BR_DESC_PRIV_CAP_TKIP |
258 BR_DESC_PRIV_CAP_MICHAEL)) ? "YES" : "no",
259 (priv->privacy_caps & BR_DESC_PRIV_CAP_AESCCMP) ?
260 "YES" : "no");
261
6dfe9a88
CL
262 if (priv->rx_keycache_size) {
263 /*
264 * NOTE:
265 *
266 * The firmware provides at most 255 (0 - 254) slots
267 * for keys which are then used to offload decryption.
268 * As a result the 255 entry (aka 0xff) can be used
269 * safely by the driver to mark keys that didn't fit
270 * into the full cache. This trick saves us from
271 * keeping a extra list for uploaded keys.
272 */
273
274 priv->used_rxkeys = kzalloc(BITS_TO_LONGS(
275 priv->rx_keycache_size), GFP_KERNEL);
276
277 if (!priv->used_rxkeys)
278 return -ENOMEM;
279 }
280 }
281
4e416a6f 282 return 0;
eff1a59c
MW
283}
284EXPORT_SYMBOL_GPL(p54_parse_firmware);
285
154e3af1
CL
286static int p54_convert_rev0(struct ieee80211_hw *dev,
287 struct pda_pa_curve_data *curve_data)
eff1a59c
MW
288{
289 struct p54_common *priv = dev->priv;
154e3af1
CL
290 struct p54_pa_curve_data_sample *dst;
291 struct pda_pa_curve_data_sample_rev0 *src;
eff1a59c 292 size_t cd_len = sizeof(*curve_data) +
154e3af1 293 (curve_data->points_per_channel*sizeof(*dst) + 2) *
eff1a59c
MW
294 curve_data->channels;
295 unsigned int i, j;
296 void *source, *target;
297
83cf1b6e
CL
298 priv->curve_data = kmalloc(sizeof(*priv->curve_data) + cd_len,
299 GFP_KERNEL);
eff1a59c
MW
300 if (!priv->curve_data)
301 return -ENOMEM;
302
83cf1b6e
CL
303 priv->curve_data->entries = curve_data->channels;
304 priv->curve_data->entry_size = sizeof(__le16) +
305 sizeof(*dst) * curve_data->points_per_channel;
306 priv->curve_data->offset = offsetof(struct pda_pa_curve_data, data);
307 priv->curve_data->len = cd_len;
308 memcpy(priv->curve_data->data, curve_data, sizeof(*curve_data));
eff1a59c 309 source = curve_data->data;
83cf1b6e 310 target = ((struct pda_pa_curve_data *) priv->curve_data->data)->data;
eff1a59c
MW
311 for (i = 0; i < curve_data->channels; i++) {
312 __le16 *freq = source;
313 source += sizeof(__le16);
314 *((__le16 *)target) = *freq;
315 target += sizeof(__le16);
316 for (j = 0; j < curve_data->points_per_channel; j++) {
154e3af1
CL
317 dst = target;
318 src = source;
eff1a59c 319
154e3af1
CL
320 dst->rf_power = src->rf_power;
321 dst->pa_detector = src->pa_detector;
322 dst->data_64qam = src->pcv;
eff1a59c
MW
323 /* "invent" the points for the other modulations */
324#define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y)
154e3af1
CL
325 dst->data_16qam = SUB(src->pcv, 12);
326 dst->data_qpsk = SUB(dst->data_16qam, 12);
327 dst->data_bpsk = SUB(dst->data_qpsk, 12);
328 dst->data_barker = SUB(dst->data_bpsk, 14);
eff1a59c 329#undef SUB
154e3af1
CL
330 target += sizeof(*dst);
331 source += sizeof(*src);
eff1a59c
MW
332 }
333 }
334
335 return 0;
336}
337
154e3af1
CL
338static int p54_convert_rev1(struct ieee80211_hw *dev,
339 struct pda_pa_curve_data *curve_data)
340{
341 struct p54_common *priv = dev->priv;
342 struct p54_pa_curve_data_sample *dst;
343 struct pda_pa_curve_data_sample_rev1 *src;
344 size_t cd_len = sizeof(*curve_data) +
345 (curve_data->points_per_channel*sizeof(*dst) + 2) *
346 curve_data->channels;
347 unsigned int i, j;
348 void *source, *target;
349
83cf1b6e
CL
350 priv->curve_data = kzalloc(cd_len + sizeof(*priv->curve_data),
351 GFP_KERNEL);
154e3af1
CL
352 if (!priv->curve_data)
353 return -ENOMEM;
354
83cf1b6e
CL
355 priv->curve_data->entries = curve_data->channels;
356 priv->curve_data->entry_size = sizeof(__le16) +
357 sizeof(*dst) * curve_data->points_per_channel;
358 priv->curve_data->offset = offsetof(struct pda_pa_curve_data, data);
359 priv->curve_data->len = cd_len;
360 memcpy(priv->curve_data->data, curve_data, sizeof(*curve_data));
154e3af1 361 source = curve_data->data;
83cf1b6e 362 target = ((struct pda_pa_curve_data *) priv->curve_data->data)->data;
154e3af1
CL
363 for (i = 0; i < curve_data->channels; i++) {
364 __le16 *freq = source;
365 source += sizeof(__le16);
366 *((__le16 *)target) = *freq;
367 target += sizeof(__le16);
368 for (j = 0; j < curve_data->points_per_channel; j++) {
369 memcpy(target, source, sizeof(*src));
370
371 target += sizeof(*dst);
372 source += sizeof(*src);
373 }
374 source++;
375 }
376
377 return 0;
378}
379
4cc683c9
CL
380static const char *p54_rf_chips[] = { "NULL", "Duette3", "Duette2",
381 "Frisbee", "Xbow", "Longbow", "NULL", "NULL" };
1b997534 382static int p54_init_xbow_synth(struct ieee80211_hw *dev);
7cb77072 383
69ba3e5d
CL
384static void p54_parse_rssical(struct ieee80211_hw *dev, void *data, int len,
385 u16 type)
386{
387 struct p54_common *priv = dev->priv;
388 int offset = (type == PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED) ? 2 : 0;
389 int entry_size = sizeof(struct pda_rssi_cal_entry) + offset;
390 int num_entries = (type == PDR_RSSI_LINEAR_APPROXIMATION) ? 1 : 2;
391 int i;
392
393 if (len != (entry_size * num_entries)) {
394 printk(KERN_ERR "%s: unknown rssi calibration data packing "
395 " type:(%x) len:%d.\n",
396 wiphy_name(dev->wiphy), type, len);
397
398 print_hex_dump_bytes("rssical:", DUMP_PREFIX_NONE,
399 data, len);
400
401 printk(KERN_ERR "%s: please report this issue.\n",
402 wiphy_name(dev->wiphy));
403 return;
404 }
405
406 for (i = 0; i < num_entries; i++) {
407 struct pda_rssi_cal_entry *cal = data +
408 (offset + i * entry_size);
409 priv->rssical_db[i].mul = (s16) le16_to_cpu(cal->mul);
410 priv->rssical_db[i].add = (s16) le16_to_cpu(cal->add);
411 }
412}
413
98a8d1a8
CL
414static void p54_parse_default_country(struct ieee80211_hw *dev,
415 void *data, int len)
416{
417 struct pda_country *country;
418
419 if (len != sizeof(*country)) {
420 printk(KERN_ERR "%s: found possible invalid default country "
421 "eeprom entry. (entry size: %d)\n",
422 wiphy_name(dev->wiphy), len);
423
424 print_hex_dump_bytes("country:", DUMP_PREFIX_NONE,
425 data, len);
426
427 printk(KERN_ERR "%s: please report this issue.\n",
428 wiphy_name(dev->wiphy));
429 return;
430 }
431
432 country = (struct pda_country *) data;
433 if (country->flags == PDR_COUNTRY_CERT_CODE_PSEUDO)
434 regulatory_hint(dev->wiphy, country->alpha2);
435 else {
436 /* TODO:
437 * write a shared/common function that converts
438 * "Regulatory domain codes" (802.11-2007 14.8.2.2)
439 * into ISO/IEC 3166-1 alpha2 for regulatory_hint.
440 */
441 }
442}
443
83cf1b6e
CL
444static int p54_convert_output_limits(struct ieee80211_hw *dev,
445 u8 *data, size_t len)
446{
447 struct p54_common *priv = dev->priv;
448
449 if (len < 2)
450 return -EINVAL;
451
452 if (data[0] != 0) {
453 printk(KERN_ERR "%s: unknown output power db revision:%x\n",
454 wiphy_name(dev->wiphy), data[0]);
455 return -EINVAL;
456 }
457
458 if (2 + data[1] * sizeof(struct pda_channel_output_limit) > len)
459 return -EINVAL;
460
461 priv->output_limit = kmalloc(data[1] *
462 sizeof(struct pda_channel_output_limit) +
463 sizeof(*priv->output_limit), GFP_KERNEL);
464
465 if (!priv->output_limit)
466 return -ENOMEM;
467
468 priv->output_limit->offset = 0;
469 priv->output_limit->entries = data[1];
470 priv->output_limit->entry_size =
471 sizeof(struct pda_channel_output_limit);
472 priv->output_limit->len = priv->output_limit->entry_size *
473 priv->output_limit->entries +
474 priv->output_limit->offset;
475
476 memcpy(priv->output_limit->data, &data[2],
477 data[1] * sizeof(struct pda_channel_output_limit));
478
479 return 0;
480}
481
482static struct p54_cal_database *p54_convert_db(struct pda_custom_wrapper *src,
483 size_t total_len)
484{
485 struct p54_cal_database *dst;
486 size_t payload_len, entries, entry_size, offset;
487
488 payload_len = le16_to_cpu(src->len);
489 entries = le16_to_cpu(src->entries);
490 entry_size = le16_to_cpu(src->entry_size);
491 offset = le16_to_cpu(src->offset);
492 if (((entries * entry_size + offset) != payload_len) ||
493 (payload_len + sizeof(*src) != total_len))
494 return NULL;
495
496 dst = kmalloc(sizeof(*dst) + payload_len, GFP_KERNEL);
497 if (!dst)
498 return NULL;
499
500 dst->entries = entries;
501 dst->entry_size = entry_size;
502 dst->offset = offset;
503 dst->len = payload_len;
504
505 memcpy(dst->data, src->data, payload_len);
506 return dst;
507}
508
cd8d3d32 509int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
eff1a59c
MW
510{
511 struct p54_common *priv = dev->priv;
512 struct eeprom_pda_wrap *wrap = NULL;
513 struct pda_entry *entry;
eff1a59c
MW
514 unsigned int data_len, entry_len;
515 void *tmp;
516 int err;
c2f2d3a0 517 u8 *end = (u8 *)eeprom + len;
f2c2e255 518 u16 synth = 0;
eff1a59c
MW
519
520 wrap = (struct eeprom_pda_wrap *) eeprom;
8c28293f 521 entry = (void *)wrap->data + le16_to_cpu(wrap->len);
c2f2d3a0
JB
522
523 /* verify that at least the entry length/code fits */
524 while ((u8 *)entry <= end - sizeof(*entry)) {
eff1a59c
MW
525 entry_len = le16_to_cpu(entry->len);
526 data_len = ((entry_len - 1) << 1);
c2f2d3a0
JB
527
528 /* abort if entry exceeds whole structure */
529 if ((u8 *)entry + sizeof(*entry) + data_len > end)
530 break;
531
eff1a59c
MW
532 switch (le16_to_cpu(entry->code)) {
533 case PDR_MAC_ADDRESS:
83cf1b6e
CL
534 if (data_len != ETH_ALEN)
535 break;
eff1a59c
MW
536 SET_IEEE80211_PERM_ADDR(dev, entry->data);
537 break;
538 case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS:
83cf1b6e
CL
539 if (priv->output_limit)
540 break;
541 err = p54_convert_output_limits(dev, entry->data,
542 data_len);
543 if (err)
eff1a59c 544 goto err;
eff1a59c 545 break;
154e3af1
CL
546 case PDR_PRISM_PA_CAL_CURVE_DATA: {
547 struct pda_pa_curve_data *curve_data =
548 (struct pda_pa_curve_data *)entry->data;
549 if (data_len < sizeof(*curve_data)) {
eff1a59c
MW
550 err = -EINVAL;
551 goto err;
552 }
553
154e3af1
CL
554 switch (curve_data->cal_method_rev) {
555 case 0:
556 err = p54_convert_rev0(dev, curve_data);
557 break;
558 case 1:
559 err = p54_convert_rev1(dev, curve_data);
560 break;
561 default:
02e37ba1 562 printk(KERN_ERR "%s: unknown curve data "
154e3af1 563 "revision %d\n",
02e37ba1 564 wiphy_name(dev->wiphy),
154e3af1
CL
565 curve_data->cal_method_rev);
566 err = -ENODEV;
567 break;
eff1a59c 568 }
154e3af1
CL
569 if (err)
570 goto err;
40ab73cc
C
571 }
572 break;
eff1a59c
MW
573 case PDR_PRISM_ZIF_TX_IQ_CALIBRATION:
574 priv->iq_autocal = kmalloc(data_len, GFP_KERNEL);
575 if (!priv->iq_autocal) {
576 err = -ENOMEM;
577 goto err;
578 }
579
580 memcpy(priv->iq_autocal, entry->data, data_len);
581 priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry);
582 break;
98a8d1a8
CL
583 case PDR_DEFAULT_COUNTRY:
584 p54_parse_default_country(dev, entry->data, data_len);
585 break;
eff1a59c
MW
586 case PDR_INTERFACE_LIST:
587 tmp = entry->data;
588 while ((u8 *)tmp < entry->data + data_len) {
589 struct bootrec_exp_if *exp_if = tmp;
4cc683c9
CL
590 if (le16_to_cpu(exp_if->if_id) == 0xf)
591 synth = le16_to_cpu(exp_if->variant);
eff1a59c
MW
592 tmp += sizeof(struct bootrec_exp_if);
593 }
594 break;
595 case PDR_HARDWARE_PLATFORM_COMPONENT_ID:
83cf1b6e
CL
596 if (data_len < 2)
597 break;
eff1a59c
MW
598 priv->version = *(u8 *)(entry->data + 1);
599 break;
69ba3e5d
CL
600 case PDR_RSSI_LINEAR_APPROXIMATION:
601 case PDR_RSSI_LINEAR_APPROXIMATION_DUAL_BAND:
602 case PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED:
603 p54_parse_rssical(dev, entry->data, data_len,
604 le16_to_cpu(entry->code));
605 break;
83cf1b6e
CL
606 case PDR_RSSI_LINEAR_APPROXIMATION_CUSTOM: {
607 __le16 *src = (void *) entry->data;
608 s16 *dst = (void *) &priv->rssical_db;
609 int i;
610
611 if (data_len != sizeof(priv->rssical_db)) {
612 err = -EINVAL;
613 goto err;
614 }
615 for (i = 0; i < sizeof(priv->rssical_db) /
616 sizeof(*src); i++)
617 *(dst++) = (s16) le16_to_cpu(*(src++));
618 }
619 break;
620 case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS_CUSTOM: {
621 struct pda_custom_wrapper *pda = (void *) entry->data;
622 if (priv->output_limit || data_len < sizeof(*pda))
623 break;
624 priv->output_limit = p54_convert_db(pda, data_len);
625 }
626 break;
627 case PDR_PRISM_PA_CAL_CURVE_DATA_CUSTOM: {
628 struct pda_custom_wrapper *pda = (void *) entry->data;
629 if (priv->curve_data || data_len < sizeof(*pda))
630 break;
631 priv->curve_data = p54_convert_db(pda, data_len);
632 }
633 break;
eff1a59c 634 case PDR_END:
c2f2d3a0
JB
635 /* make it overrun */
636 entry_len = len;
eff1a59c 637 break;
c8034c44
PR
638 case PDR_MANUFACTURING_PART_NUMBER:
639 case PDR_PDA_VERSION:
640 case PDR_NIC_SERIAL_NUMBER:
641 case PDR_REGULATORY_DOMAIN_LIST:
642 case PDR_TEMPERATURE_TYPE:
643 case PDR_PRISM_PCI_IDENTIFIER:
644 case PDR_COUNTRY_INFORMATION:
645 case PDR_OEM_NAME:
646 case PDR_PRODUCT_NAME:
647 case PDR_UTF8_OEM_NAME:
648 case PDR_UTF8_PRODUCT_NAME:
649 case PDR_COUNTRY_LIST:
c8034c44
PR
650 case PDR_ANTENNA_GAIN:
651 case PDR_PRISM_INDIGO_PA_CALIBRATION_DATA:
c8034c44 652 case PDR_REGULATORY_POWER_LIMITS:
c8034c44
PR
653 case PDR_RADIATED_TRANSMISSION_CORRECTION:
654 case PDR_PRISM_TX_IQ_CALIBRATION:
655 case PDR_BASEBAND_REGISTERS:
656 case PDR_PER_CHANNEL_BASEBAND_REGISTERS:
657 break;
58e30739 658 default:
02e37ba1
CL
659 printk(KERN_INFO "%s: unknown eeprom code : 0x%x\n",
660 wiphy_name(dev->wiphy),
58e30739
FF
661 le16_to_cpu(entry->code));
662 break;
eff1a59c
MW
663 }
664
665 entry = (void *)entry + (entry_len + 1)*2;
eff1a59c
MW
666 }
667
f2c2e255
CL
668 if (!synth || !priv->iq_autocal || !priv->output_limit ||
669 !priv->curve_data) {
02e37ba1
CL
670 printk(KERN_ERR "%s: not all required entries found in eeprom!\n",
671 wiphy_name(dev->wiphy));
eff1a59c
MW
672 err = -EINVAL;
673 goto err;
674 }
675
9e7f3f8e 676 priv->rxhw = synth & PDR_SYNTH_FRONTEND_MASK;
6917f506 677 if (priv->rxhw == PDR_SYNTH_FRONTEND_XBOW)
1b997534 678 p54_init_xbow_synth(dev);
9e7f3f8e 679 if (!(synth & PDR_SYNTH_24_GHZ_DISABLED))
1b997534 680 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band_2GHz;
9e7f3f8e 681 if (!(synth & PDR_SYNTH_5_GHZ_DISABLED))
4cc683c9 682 dev->wiphy->bands[IEEE80211_BAND_5GHZ] = &band_5GHz;
78eb7484
CL
683 if ((synth & PDR_SYNTH_RX_DIV_MASK) == PDR_SYNTH_RX_DIV_SUPPORTED)
684 priv->rx_diversity_mask = 3;
685 if ((synth & PDR_SYNTH_TX_DIV_MASK) == PDR_SYNTH_TX_DIV_SUPPORTED)
686 priv->tx_diversity_mask = 3;
7cb77072
CL
687
688 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
689 u8 perm_addr[ETH_ALEN];
690
691 printk(KERN_WARNING "%s: Invalid hwaddr! Using randomly generated MAC addr\n",
692 wiphy_name(dev->wiphy));
693 random_ether_addr(perm_addr);
694 SET_IEEE80211_PERM_ADDR(dev, perm_addr);
695 }
696
e174961c 697 printk(KERN_INFO "%s: hwaddr %pM, MAC:isl38%02x RF:%s\n",
7cb77072 698 wiphy_name(dev->wiphy),
e174961c 699 dev->wiphy->perm_addr,
7cb77072
CL
700 priv->version, p54_rf_chips[priv->rxhw]);
701
eff1a59c
MW
702 return 0;
703
704 err:
705 if (priv->iq_autocal) {
706 kfree(priv->iq_autocal);
707 priv->iq_autocal = NULL;
708 }
709
710 if (priv->output_limit) {
711 kfree(priv->output_limit);
712 priv->output_limit = NULL;
713 }
714
715 if (priv->curve_data) {
716 kfree(priv->curve_data);
717 priv->curve_data = NULL;
718 }
719
02e37ba1
CL
720 printk(KERN_ERR "%s: eeprom parse failed!\n",
721 wiphy_name(dev->wiphy));
eff1a59c
MW
722 return err;
723}
cd8d3d32 724EXPORT_SYMBOL_GPL(p54_parse_eeprom);
eff1a59c 725
cc6de669
CL
726static int p54_rssi_to_dbm(struct ieee80211_hw *dev, int rssi)
727{
69ba3e5d
CL
728 struct p54_common *priv = dev->priv;
729 int band = dev->conf.channel->band;
730
6917f506
CL
731 if (priv->rxhw != PDR_SYNTH_FRONTEND_LONGBOW)
732 return ((rssi * priv->rssical_db[band].mul) / 64 +
733 priv->rssical_db[band].add) / 4;
734 else
735 /*
736 * TODO: find the correct formula
737 */
738 return ((rssi * priv->rssical_db[band].mul) / 64 +
69ba3e5d 739 priv->rssical_db[band].add) / 4;
cc6de669
CL
740}
741
19c19d54 742static int p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 743{
a0db663f 744 struct p54_common *priv = dev->priv;
27df605e 745 struct p54_rx_data *hdr = (struct p54_rx_data *) skb->data;
eff1a59c
MW
746 struct ieee80211_rx_status rx_status = {0};
747 u16 freq = le16_to_cpu(hdr->freq);
19c19d54 748 size_t header_len = sizeof(*hdr);
a0db663f 749 u32 tsf32;
124b68e7 750 u8 rate = hdr->rate & 0xf;
eff1a59c 751
59651e89
CL
752 /*
753 * If the device is in a unspecified state we have to
754 * ignore all data frames. Else we could end up with a
755 * nasty crash.
756 */
757 if (unlikely(priv->mode == NL80211_IFTYPE_UNSPECIFIED))
758 return 0;
759
27df605e 760 if (!(hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_IN_FCS_GOOD))) {
346de732 761 return 0;
78d57eb2
CL
762 }
763
25900ef0
CL
764 if (hdr->decrypt_status == P54_DECRYPT_OK)
765 rx_status.flag |= RX_FLAG_DECRYPTED;
766 if ((hdr->decrypt_status == P54_DECRYPT_FAIL_MICHAEL) ||
767 (hdr->decrypt_status == P54_DECRYPT_FAIL_TKIP))
768 rx_status.flag |= RX_FLAG_MMIC_ERROR;
769
cc6de669
CL
770 rx_status.signal = p54_rssi_to_dbm(dev, hdr->rssi);
771 rx_status.noise = priv->noise;
ffed7858
CL
772 if (hdr->rate & 0x10)
773 rx_status.flag |= RX_FLAG_SHORTPRE;
124b68e7
CL
774 if (dev->conf.channel->band == IEEE80211_BAND_5GHZ)
775 rx_status.rate_idx = (rate < 4) ? 0 : rate - 4;
776 else
777 rx_status.rate_idx = rate;
778
eff1a59c 779 rx_status.freq = freq;
cf3e74c2 780 rx_status.band = dev->conf.channel->band;
eff1a59c 781 rx_status.antenna = hdr->antenna;
a0db663f
CL
782
783 tsf32 = le32_to_cpu(hdr->tsf32);
784 if (tsf32 < priv->tsf_low32)
785 priv->tsf_high32++;
786 rx_status.mactime = ((u64)priv->tsf_high32) << 32 | tsf32;
787 priv->tsf_low32 = tsf32;
788
03bffc13 789 rx_status.flag |= RX_FLAG_TSFT;
eff1a59c 790
27df605e 791 if (hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_ALIGN))
19c19d54
CL
792 header_len += hdr->align[0];
793
794 skb_pull(skb, header_len);
eff1a59c
MW
795 skb_trim(skb, le16_to_cpu(hdr->len));
796
797 ieee80211_rx_irqsafe(dev, skb, &rx_status);
19c19d54 798
54fdb040
CL
799 queue_delayed_work(dev->workqueue, &priv->work,
800 msecs_to_jiffies(P54_STATISTICS_UPDATE));
801
19c19d54 802 return -1;
eff1a59c
MW
803}
804
805static void inline p54_wake_free_queues(struct ieee80211_hw *dev)
806{
807 struct p54_common *priv = dev->priv;
808 int i;
809
b92f30d6
CL
810 if (priv->mode == NL80211_IFTYPE_UNSPECIFIED)
811 return ;
812
eff1a59c 813 for (i = 0; i < dev->queues; i++)
a15bd005
CL
814 if (priv->tx_stats[i + P54_QUEUE_DATA].len <
815 priv->tx_stats[i + P54_QUEUE_DATA].limit)
eff1a59c
MW
816 ieee80211_wake_queue(dev, i);
817}
818
b92f30d6
CL
819void p54_free_skb(struct ieee80211_hw *dev, struct sk_buff *skb)
820{
821 struct p54_common *priv = dev->priv;
822 struct ieee80211_tx_info *info;
3cd08b38 823 struct p54_tx_info *range;
b92f30d6 824 unsigned long flags;
b92f30d6 825
0ca1b08e 826 if (unlikely(!skb || !dev || !skb_queue_len(&priv->tx_queue)))
b92f30d6
CL
827 return;
828
0ca1b08e
DM
829 /*
830 * don't try to free an already unlinked skb
59651e89 831 */
0ca1b08e
DM
832 if (unlikely((!skb->next) || (!skb->prev)))
833 return;
59651e89 834
b92f30d6
CL
835 spin_lock_irqsave(&priv->tx_queue.lock, flags);
836 info = IEEE80211_SKB_CB(skb);
837 range = (void *)info->rate_driver_data;
0ca1b08e 838 if (skb->prev != (struct sk_buff *)&priv->tx_queue) {
b92f30d6 839 struct ieee80211_tx_info *ni;
3cd08b38 840 struct p54_tx_info *mr;
b92f30d6 841
0ca1b08e 842 ni = IEEE80211_SKB_CB(skb->prev);
3cd08b38 843 mr = (struct p54_tx_info *)ni->rate_driver_data;
b92f30d6 844 }
0ca1b08e 845 if (skb->next != (struct sk_buff *)&priv->tx_queue) {
b92f30d6 846 struct ieee80211_tx_info *ni;
3cd08b38 847 struct p54_tx_info *mr;
b92f30d6 848
0ca1b08e 849 ni = IEEE80211_SKB_CB(skb->next);
3cd08b38 850 mr = (struct p54_tx_info *)ni->rate_driver_data;
7c5a189d 851 }
b92f30d6
CL
852 __skb_unlink(skb, &priv->tx_queue);
853 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
0a5ec96a 854 dev_kfree_skb_any(skb);
7c5a189d 855 p54_wake_free_queues(dev);
b92f30d6
CL
856}
857EXPORT_SYMBOL_GPL(p54_free_skb);
858
54fdb040
CL
859static struct sk_buff *p54_find_tx_entry(struct ieee80211_hw *dev,
860 __le32 req_id)
861{
862 struct p54_common *priv = dev->priv;
c0350024 863 struct sk_buff *entry;
54fdb040
CL
864 unsigned long flags;
865
866 spin_lock_irqsave(&priv->tx_queue.lock, flags);
0ca1b08e
DM
867 entry = priv->tx_queue.next;
868 while (entry != (struct sk_buff *)&priv->tx_queue) {
54fdb040
CL
869 struct p54_hdr *hdr = (struct p54_hdr *) entry->data;
870
871 if (hdr->req_id == req_id) {
872 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
873 return entry;
874 }
0ca1b08e 875 entry = entry->next;
54fdb040
CL
876 }
877 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
878 return NULL;
879}
880
eff1a59c
MW
881static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
882{
883 struct p54_common *priv = dev->priv;
27df605e
JL
884 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
885 struct p54_frame_sent *payload = (struct p54_frame_sent *) hdr->data;
c0350024 886 struct sk_buff *entry;
4e416a6f 887 u32 addr = le32_to_cpu(hdr->req_id) - priv->headroom;
3cd08b38 888 struct p54_tx_info *range = NULL;
031d10ee 889 unsigned long flags;
c12abae3 890 int count, idx;
eff1a59c 891
031d10ee 892 spin_lock_irqsave(&priv->tx_queue.lock, flags);
0ca1b08e
DM
893 entry = (struct sk_buff *) priv->tx_queue.next;
894 while (entry != (struct sk_buff *)&priv->tx_queue) {
552fe53f 895 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
27df605e
JL
896 struct p54_hdr *entry_hdr;
897 struct p54_tx_data *entry_data;
12da401e 898 unsigned int pad = 0, frame_len;
eff1a59c 899
9de5776f 900 range = (void *)info->rate_driver_data;
0ca1b08e
DM
901 if (range->start_addr != addr) {
902 entry = entry->next;
9de5776f 903 continue;
0ca1b08e 904 }
552fe53f 905
0ca1b08e 906 if (entry->next != (struct sk_buff *)&priv->tx_queue) {
9de5776f 907 struct ieee80211_tx_info *ni;
3cd08b38 908 struct p54_tx_info *mr;
eff1a59c 909
0ca1b08e 910 ni = IEEE80211_SKB_CB(entry->next);
3cd08b38 911 mr = (struct p54_tx_info *)ni->rate_driver_data;
7c5a189d 912 }
9de5776f 913
9de5776f 914 __skb_unlink(entry, &priv->tx_queue);
9de5776f 915
12da401e 916 frame_len = entry->len;
c772a08b
CL
917 entry_hdr = (struct p54_hdr *) entry->data;
918 entry_data = (struct p54_tx_data *) entry_hdr->data;
47ab3840
LF
919 if (priv->tx_stats[entry_data->hw_queue].len)
920 priv->tx_stats[entry_data->hw_queue].len--;
ee370ced 921 priv->stats.dot11ACKFailureCount += payload->tries - 1;
47ab3840 922 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
c772a08b 923
29701e5a
CL
924 /*
925 * Frames in P54_QUEUE_FWSCAN and P54_QUEUE_BEACON are
926 * generated by the driver. Therefore tx_status is bogus
927 * and we don't want to confuse the mac80211 stack.
928 */
929 if (unlikely(entry_data->hw_queue < P54_QUEUE_FWSCAN)) {
930 if (entry_data->hw_queue == P54_QUEUE_BEACON)
931 priv->cached_beacon = NULL;
932
e5ea92a7 933 kfree_skb(entry);
e5ea92a7
CL
934 goto out;
935 }
936
9de5776f
CL
937 /*
938 * Clear manually, ieee80211_tx_info_clear_status would
939 * clear the counts too and we need them.
940 */
941 memset(&info->status.ampdu_ack_len, 0,
942 sizeof(struct ieee80211_tx_info) -
943 offsetof(struct ieee80211_tx_info, status.ampdu_ack_len));
944 BUILD_BUG_ON(offsetof(struct ieee80211_tx_info,
945 status.ampdu_ack_len) != 23);
946
27df605e 947 if (entry_hdr->flags & cpu_to_le16(P54_HDR_FLAG_DATA_ALIGN))
9de5776f
CL
948 pad = entry_data->align[0];
949
950 /* walk through the rates array and adjust the counts */
27df605e 951 count = payload->tries;
9de5776f
CL
952 for (idx = 0; idx < 4; idx++) {
953 if (count >= info->status.rates[idx].count) {
954 count -= info->status.rates[idx].count;
955 } else if (count > 0) {
956 info->status.rates[idx].count = count;
957 count = 0;
958 } else {
959 info->status.rates[idx].idx = -1;
960 info->status.rates[idx].count = 0;
eff1a59c 961 }
9de5776f 962 }
c12abae3 963
9de5776f
CL
964 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
965 (!payload->status))
966 info->flags |= IEEE80211_TX_STAT_ACK;
9e7f3f8e 967 if (payload->status & P54_TX_PSM_CANCELLED)
9de5776f
CL
968 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
969 info->status.ack_signal = p54_rssi_to_dbm(dev,
27df605e 970 (int)payload->ack_rssi);
c1d34c1d 971
12da401e
CL
972 /* Undo all changes to the frame. */
973 switch (entry_data->key_type) {
974 case P54_CRYPTO_TKIPMICHAEL: {
c1d34c1d 975 u8 *iv = (u8 *)(entry_data->align + pad +
12da401e 976 entry_data->crypt_offset);
c1d34c1d
CL
977
978 /* Restore the original TKIP IV. */
979 iv[2] = iv[0];
980 iv[0] = iv[1];
981 iv[1] = (iv[0] | 0x20) & 0x7f; /* WEPSeed - 8.3.2.2 */
12da401e
CL
982
983 frame_len -= 12; /* remove TKIP_MMIC + TKIP_ICV */
984 break;
985 }
986 case P54_CRYPTO_AESCCMP:
987 frame_len -= 8; /* remove CCMP_MIC */
988 break;
989 case P54_CRYPTO_WEP:
990 frame_len -= 4; /* remove WEP_ICV */
991 break;
c1d34c1d 992 }
12da401e 993 skb_trim(entry, frame_len);
9de5776f
CL
994 skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data));
995 ieee80211_tx_status_irqsafe(dev, entry);
996 goto out;
eff1a59c 997 }
031d10ee 998 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
eff1a59c 999
031d10ee 1000out:
7c5a189d 1001 p54_wake_free_queues(dev);
eff1a59c
MW
1002}
1003
7cb77072
CL
1004static void p54_rx_eeprom_readback(struct ieee80211_hw *dev,
1005 struct sk_buff *skb)
1006{
27df605e 1007 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
7cb77072
CL
1008 struct p54_eeprom_lm86 *eeprom = (struct p54_eeprom_lm86 *) hdr->data;
1009 struct p54_common *priv = dev->priv;
1010
1011 if (!priv->eeprom)
1012 return ;
1013
64c354dd
CL
1014 if (priv->fw_var >= 0x509) {
1015 memcpy(priv->eeprom, eeprom->v2.data,
1016 le16_to_cpu(eeprom->v2.len));
1017 } else {
1018 memcpy(priv->eeprom, eeprom->v1.data,
1019 le16_to_cpu(eeprom->v1.len));
1020 }
7cb77072
CL
1021
1022 complete(&priv->eeprom_comp);
1023}
1024
cc6de669
CL
1025static void p54_rx_stats(struct ieee80211_hw *dev, struct sk_buff *skb)
1026{
1027 struct p54_common *priv = dev->priv;
27df605e 1028 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
cc6de669 1029 struct p54_statistics *stats = (struct p54_statistics *) hdr->data;
54fdb040
CL
1030 u32 tsf32;
1031
1032 if (unlikely(priv->mode == NL80211_IFTYPE_UNSPECIFIED))
1033 return ;
cc6de669 1034
54fdb040 1035 tsf32 = le32_to_cpu(stats->tsf32);
cc6de669
CL
1036 if (tsf32 < priv->tsf_low32)
1037 priv->tsf_high32++;
1038 priv->tsf_low32 = tsf32;
1039
1040 priv->stats.dot11RTSFailureCount = le32_to_cpu(stats->rts_fail);
1041 priv->stats.dot11RTSSuccessCount = le32_to_cpu(stats->rts_success);
1042 priv->stats.dot11FCSErrorCount = le32_to_cpu(stats->rx_bad_fcs);
1043
1044 priv->noise = p54_rssi_to_dbm(dev, le32_to_cpu(stats->noise));
cc6de669 1045
54fdb040 1046 p54_free_skb(dev, p54_find_tx_entry(dev, hdr->req_id));
cc6de669
CL
1047}
1048
e5ea92a7
CL
1049static void p54_rx_trap(struct ieee80211_hw *dev, struct sk_buff *skb)
1050{
f13027af 1051 struct p54_common *priv = dev->priv;
e5ea92a7
CL
1052 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
1053 struct p54_trap *trap = (struct p54_trap *) hdr->data;
1054 u16 event = le16_to_cpu(trap->event);
1055 u16 freq = le16_to_cpu(trap->frequency);
1056
1057 switch (event) {
1058 case P54_TRAP_BEACON_TX:
1059 break;
1060 case P54_TRAP_RADAR:
1061 printk(KERN_INFO "%s: radar (freq:%d MHz)\n",
1062 wiphy_name(dev->wiphy), freq);
1063 break;
1064 case P54_TRAP_NO_BEACON:
f13027af
CL
1065 if (priv->vif)
1066 ieee80211_beacon_loss(priv->vif);
e5ea92a7
CL
1067 break;
1068 case P54_TRAP_SCAN:
1069 break;
1070 case P54_TRAP_TBTT:
1071 break;
1072 case P54_TRAP_TIMER:
1073 break;
1074 default:
1075 printk(KERN_INFO "%s: received event:%x freq:%d\n",
1076 wiphy_name(dev->wiphy), event, freq);
1077 break;
1078 }
1079}
1080
19c19d54 1081static int p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 1082{
27df605e 1083 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
eff1a59c
MW
1084
1085 switch (le16_to_cpu(hdr->type)) {
1086 case P54_CONTROL_TYPE_TXDONE:
1087 p54_rx_frame_sent(dev, skb);
1088 break;
e5ea92a7
CL
1089 case P54_CONTROL_TYPE_TRAP:
1090 p54_rx_trap(dev, skb);
1091 break;
eff1a59c
MW
1092 case P54_CONTROL_TYPE_BBP:
1093 break;
cc6de669
CL
1094 case P54_CONTROL_TYPE_STAT_READBACK:
1095 p54_rx_stats(dev, skb);
1096 break;
7cb77072
CL
1097 case P54_CONTROL_TYPE_EEPROM_READBACK:
1098 p54_rx_eeprom_readback(dev, skb);
1099 break;
eff1a59c
MW
1100 default:
1101 printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n",
1102 wiphy_name(dev->wiphy), le16_to_cpu(hdr->type));
1103 break;
1104 }
19c19d54
CL
1105
1106 return 0;
eff1a59c
MW
1107}
1108
1109/* returns zero if skb can be reused */
1110int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb)
1111{
9e7f3f8e 1112 u16 type = le16_to_cpu(*((__le16 *)skb->data));
19c19d54 1113
9e7f3f8e 1114 if (type & P54_HDR_FLAG_CONTROL)
19c19d54
CL
1115 return p54_rx_control(dev, skb);
1116 else
1117 return p54_rx_data(dev, skb);
eff1a59c
MW
1118}
1119EXPORT_SYMBOL_GPL(p54_rx);
1120
1121/*
1122 * So, the firmware is somewhat stupid and doesn't know what places in its
1123 * memory incoming data should go to. By poking around in the firmware, we
1124 * can find some unused memory to upload our packets to. However, data that we
1125 * want the card to TX needs to stay intact until the card has told us that
1126 * it is done with it. This function finds empty places we can upload to and
3cd08b38
CL
1127 * marks allocated areas as reserved if necessary. p54_rx_frame_sent or
1128 * p54_free_skb frees allocated areas.
eff1a59c 1129 */
b92f30d6 1130static int p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
27df605e 1131 struct p54_hdr *data, u32 len)
eff1a59c
MW
1132{
1133 struct p54_common *priv = dev->priv;
c0350024 1134 struct sk_buff *entry;
eff1a59c 1135 struct sk_buff *target_skb = NULL;
b92f30d6 1136 struct ieee80211_tx_info *info;
3cd08b38 1137 struct p54_tx_info *range;
eff1a59c
MW
1138 u32 last_addr = priv->rx_start;
1139 u32 largest_hole = 0;
1140 u32 target_addr = priv->rx_start;
1141 unsigned long flags;
1142 unsigned int left;
4e416a6f 1143 len = (len + priv->headroom + priv->tailroom + 3) & ~0x3;
eff1a59c 1144
b92f30d6
CL
1145 if (!skb)
1146 return -EINVAL;
1147
eff1a59c 1148 spin_lock_irqsave(&priv->tx_queue.lock, flags);
39ca5bb7 1149
eff1a59c 1150 left = skb_queue_len(&priv->tx_queue);
39ca5bb7
CL
1151 if (unlikely(left >= 28)) {
1152 /*
1153 * The tx_queue is nearly full!
1154 * We have throttle normal data traffic, because we must
1155 * have a few spare slots for control frames left.
1156 */
1157 ieee80211_stop_queues(dev);
54fdb040
CL
1158 queue_delayed_work(dev->workqueue, &priv->work,
1159 msecs_to_jiffies(P54_TX_TIMEOUT));
39ca5bb7
CL
1160
1161 if (unlikely(left == 32)) {
1162 /*
1163 * The tx_queue is now really full.
1164 *
1165 * TODO: check if the device has crashed and reset it.
1166 */
1167 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
1168 return -ENOSPC;
1169 }
1170 }
1171
0ca1b08e
DM
1172 entry = priv->tx_queue.next;
1173 while (left--) {
eff1a59c 1174 u32 hole_size;
b92f30d6
CL
1175 info = IEEE80211_SKB_CB(entry);
1176 range = (void *)info->rate_driver_data;
eff1a59c
MW
1177 hole_size = range->start_addr - last_addr;
1178 if (!target_skb && hole_size >= len) {
0ca1b08e 1179 target_skb = entry->prev;
eff1a59c
MW
1180 hole_size -= len;
1181 target_addr = last_addr;
1182 }
1183 largest_hole = max(largest_hole, hole_size);
1184 last_addr = range->end_addr;
0ca1b08e 1185 entry = entry->next;
eff1a59c
MW
1186 }
1187 if (!target_skb && priv->rx_end - last_addr >= len) {
0ca1b08e 1188 target_skb = priv->tx_queue.prev;
eff1a59c
MW
1189 largest_hole = max(largest_hole, priv->rx_end - last_addr - len);
1190 if (!skb_queue_empty(&priv->tx_queue)) {
b92f30d6
CL
1191 info = IEEE80211_SKB_CB(target_skb);
1192 range = (void *)info->rate_driver_data;
eff1a59c
MW
1193 target_addr = range->end_addr;
1194 }
1195 } else
1196 largest_hole = max(largest_hole, priv->rx_end - last_addr);
1197
b92f30d6
CL
1198 if (!target_skb) {
1199 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
1200 ieee80211_stop_queues(dev);
39ca5bb7 1201 return -ENOSPC;
eff1a59c 1202 }
b92f30d6
CL
1203
1204 info = IEEE80211_SKB_CB(skb);
1205 range = (void *)info->rate_driver_data;
1206 range->start_addr = target_addr;
1207 range->end_addr = target_addr + len;
1208 __skb_queue_after(&priv->tx_queue, target_skb, skb);
eff1a59c
MW
1209 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
1210
27df605e 1211 if (largest_hole < priv->headroom + sizeof(struct p54_hdr) +
b92f30d6
CL
1212 48 + IEEE80211_MAX_RTS_THRESHOLD + priv->tailroom)
1213 ieee80211_stop_queues(dev);
1214
4e416a6f 1215 data->req_id = cpu_to_le32(target_addr + priv->headroom);
b92f30d6
CL
1216 return 0;
1217}
1218
63f2dc9f
CL
1219static struct sk_buff *p54_alloc_skb(struct ieee80211_hw *dev, u16 hdr_flags,
1220 u16 payload_len, u16 type, gfp_t memflags)
b92f30d6
CL
1221{
1222 struct p54_common *priv = dev->priv;
27df605e 1223 struct p54_hdr *hdr;
b92f30d6 1224 struct sk_buff *skb;
63f2dc9f 1225 size_t frame_len = sizeof(*hdr) + payload_len;
b92f30d6 1226
63f2dc9f
CL
1227 if (frame_len > P54_MAX_CTRL_FRAME_LEN)
1228 return NULL;
1229
1230 skb = __dev_alloc_skb(priv->tx_hdr_len + frame_len, memflags);
b92f30d6
CL
1231 if (!skb)
1232 return NULL;
1233 skb_reserve(skb, priv->tx_hdr_len);
1234
27df605e
JL
1235 hdr = (struct p54_hdr *) skb_put(skb, sizeof(*hdr));
1236 hdr->flags = cpu_to_le16(hdr_flags);
63f2dc9f 1237 hdr->len = cpu_to_le16(payload_len);
b92f30d6 1238 hdr->type = cpu_to_le16(type);
27df605e 1239 hdr->tries = hdr->rts_tries = 0;
b92f30d6 1240
63f2dc9f 1241 if (p54_assign_address(dev, skb, hdr, frame_len)) {
b92f30d6
CL
1242 kfree_skb(skb);
1243 return NULL;
1244 }
1245 return skb;
eff1a59c
MW
1246}
1247
7cb77072
CL
1248int p54_read_eeprom(struct ieee80211_hw *dev)
1249{
1250 struct p54_common *priv = dev->priv;
7cb77072 1251 struct p54_eeprom_lm86 *eeprom_hdr;
b92f30d6 1252 struct sk_buff *skb;
64c354dd 1253 size_t eeprom_size = 0x2020, offset = 0, blocksize, maxblocksize;
7cb77072
CL
1254 int ret = -ENOMEM;
1255 void *eeprom = NULL;
1256
64c354dd
CL
1257 maxblocksize = EEPROM_READBACK_LEN;
1258 if (priv->fw_var >= 0x509)
1259 maxblocksize -= 0xc;
1260 else
1261 maxblocksize -= 0x4;
1262
63f2dc9f
CL
1263 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL, sizeof(*eeprom_hdr) +
1264 maxblocksize, P54_CONTROL_TYPE_EEPROM_READBACK,
1265 GFP_KERNEL);
b92f30d6 1266 if (!skb)
7cb77072 1267 goto free;
7cb77072
CL
1268 priv->eeprom = kzalloc(EEPROM_READBACK_LEN, GFP_KERNEL);
1269 if (!priv->eeprom)
1270 goto free;
7cb77072
CL
1271 eeprom = kzalloc(eeprom_size, GFP_KERNEL);
1272 if (!eeprom)
1273 goto free;
1274
b92f30d6 1275 eeprom_hdr = (struct p54_eeprom_lm86 *) skb_put(skb,
64c354dd 1276 sizeof(*eeprom_hdr) + maxblocksize);
7cb77072
CL
1277
1278 while (eeprom_size) {
64c354dd
CL
1279 blocksize = min(eeprom_size, maxblocksize);
1280 if (priv->fw_var < 0x509) {
1281 eeprom_hdr->v1.offset = cpu_to_le16(offset);
1282 eeprom_hdr->v1.len = cpu_to_le16(blocksize);
1283 } else {
1284 eeprom_hdr->v2.offset = cpu_to_le32(offset);
1285 eeprom_hdr->v2.len = cpu_to_le16(blocksize);
1286 eeprom_hdr->v2.magic2 = 0xf;
1287 memcpy(eeprom_hdr->v2.magic, (const char *)"LOCK", 4);
1288 }
0a5ec96a 1289 priv->tx(dev, skb);
7cb77072
CL
1290
1291 if (!wait_for_completion_interruptible_timeout(&priv->eeprom_comp, HZ)) {
1292 printk(KERN_ERR "%s: device does not respond!\n",
1293 wiphy_name(dev->wiphy));
1294 ret = -EBUSY;
1295 goto free;
1296 }
1297
1298 memcpy(eeprom + offset, priv->eeprom, blocksize);
1299 offset += blocksize;
1300 eeprom_size -= blocksize;
1301 }
1302
1303 ret = p54_parse_eeprom(dev, eeprom, offset);
1304free:
1305 kfree(priv->eeprom);
1306 priv->eeprom = NULL;
b92f30d6 1307 p54_free_skb(dev, skb);
7cb77072
CL
1308 kfree(eeprom);
1309
1310 return ret;
1311}
1312EXPORT_SYMBOL_GPL(p54_read_eeprom);
1313
e5ea92a7
CL
1314static int p54_set_tim(struct ieee80211_hw *dev, struct ieee80211_sta *sta,
1315 bool set)
1316{
1317 struct p54_common *priv = dev->priv;
1318 struct sk_buff *skb;
1319 struct p54_tim *tim;
1320
63f2dc9f
CL
1321 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*tim),
1322 P54_CONTROL_TYPE_TIM, GFP_ATOMIC);
e5ea92a7
CL
1323 if (!skb)
1324 return -ENOMEM;
1325
1326 tim = (struct p54_tim *) skb_put(skb, sizeof(*tim));
1327 tim->count = 1;
1328 tim->entry[0] = cpu_to_le16(set ? (sta->aid | 0x8000) : sta->aid);
0a5ec96a 1329 priv->tx(dev, skb);
e5ea92a7
CL
1330 return 0;
1331}
1332
1333static int p54_sta_unlock(struct ieee80211_hw *dev, u8 *addr)
1334{
1335 struct p54_common *priv = dev->priv;
1336 struct sk_buff *skb;
1337 struct p54_sta_unlock *sta;
1338
63f2dc9f
CL
1339 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*sta),
1340 P54_CONTROL_TYPE_PSM_STA_UNLOCK, GFP_ATOMIC);
e5ea92a7
CL
1341 if (!skb)
1342 return -ENOMEM;
1343
1344 sta = (struct p54_sta_unlock *)skb_put(skb, sizeof(*sta));
1345 memcpy(sta->addr, addr, ETH_ALEN);
0a5ec96a 1346 priv->tx(dev, skb);
e5ea92a7
CL
1347 return 0;
1348}
1349
c772a08b
CL
1350static void p54_sta_notify(struct ieee80211_hw *dev, struct ieee80211_vif *vif,
1351 enum sta_notify_cmd notify_cmd,
1352 struct ieee80211_sta *sta)
1353{
1354 switch (notify_cmd) {
1355 case STA_NOTIFY_ADD:
1356 case STA_NOTIFY_REMOVE:
1357 /*
1358 * Notify the firmware that we don't want or we don't
1359 * need to buffer frames for this station anymore.
1360 */
1361
89fad578
CL
1362 p54_sta_unlock(dev, sta->addr);
1363 break;
1364 case STA_NOTIFY_AWAKE:
1365 /* update the firmware's filter table */
c772a08b
CL
1366 p54_sta_unlock(dev, sta->addr);
1367 break;
1368 default:
1369 break;
1370 }
1371}
1372
e5ea92a7
CL
1373static int p54_tx_cancel(struct ieee80211_hw *dev, struct sk_buff *entry)
1374{
1375 struct p54_common *priv = dev->priv;
1376 struct sk_buff *skb;
1377 struct p54_hdr *hdr;
1378 struct p54_txcancel *cancel;
1379
63f2dc9f
CL
1380 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*cancel),
1381 P54_CONTROL_TYPE_TXCANCEL, GFP_ATOMIC);
e5ea92a7
CL
1382 if (!skb)
1383 return -ENOMEM;
1384
1385 hdr = (void *)entry->data;
1386 cancel = (struct p54_txcancel *)skb_put(skb, sizeof(*cancel));
1387 cancel->req_id = hdr->req_id;
0a5ec96a 1388 priv->tx(dev, skb);
e5ea92a7
CL
1389 return 0;
1390}
1391
94585b09
CL
1392static int p54_tx_fill(struct ieee80211_hw *dev, struct sk_buff *skb,
1393 struct ieee80211_tx_info *info, u8 *queue, size_t *extra_len,
1394 u16 *flags, u16 *aid)
1395{
1396 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1397 struct p54_common *priv = dev->priv;
29701e5a 1398 int ret = 1;
94585b09
CL
1399
1400 switch (priv->mode) {
29701e5a
CL
1401 case NL80211_IFTYPE_MONITOR:
1402 /*
1403 * We have to set P54_HDR_FLAG_DATA_OUT_PROMISC for
1404 * every frame in promiscuous/monitor mode.
1405 * see STSW45x0C LMAC API - page 12.
1406 */
1407 *aid = 0;
1408 *flags = P54_HDR_FLAG_DATA_OUT_PROMISC;
1409 *queue += P54_QUEUE_DATA;
1410 break;
94585b09
CL
1411 case NL80211_IFTYPE_STATION:
1412 *aid = 1;
29701e5a
CL
1413 if (unlikely(ieee80211_is_mgmt(hdr->frame_control))) {
1414 *queue = P54_QUEUE_MGMT;
1415 ret = 0;
1416 } else
1417 *queue += P54_QUEUE_DATA;
94585b09
CL
1418 break;
1419 case NL80211_IFTYPE_AP:
1420 case NL80211_IFTYPE_ADHOC:
d131bb59 1421 case NL80211_IFTYPE_MESH_POINT:
94585b09
CL
1422 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1423 *aid = 0;
a15bd005 1424 *queue = P54_QUEUE_CAB;
94585b09
CL
1425 return 0;
1426 }
29701e5a
CL
1427
1428 if (unlikely(ieee80211_is_mgmt(hdr->frame_control))) {
1429 if (ieee80211_is_probe_resp(hdr->frame_control)) {
1430 *aid = 0;
1431 *queue = P54_QUEUE_MGMT;
1432 *flags = P54_HDR_FLAG_DATA_OUT_TIMESTAMP |
1433 P54_HDR_FLAG_DATA_OUT_NOCANCEL;
1434 return 0;
1435 } else if (ieee80211_is_beacon(hdr->frame_control)) {
1436 *aid = 0;
1437
1438 if (info->flags & IEEE80211_TX_CTL_INJECTED) {
1439 /*
1440 * Injecting beacons on top of a AP is
1441 * not a good idea... nevertheless,
1442 * it should be doable.
1443 */
1444
1445 *queue += P54_QUEUE_DATA;
1446 return 1;
1447 }
1448
1449 *flags = P54_HDR_FLAG_DATA_OUT_TIMESTAMP;
1450 *queue = P54_QUEUE_BEACON;
1451 *extra_len = IEEE80211_MAX_TIM_LEN;
1452 return 0;
1453 } else {
1454 *queue = P54_QUEUE_MGMT;
1455 ret = 0;
1456 }
1457 } else
1458 *queue += P54_QUEUE_DATA;
1459
94585b09
CL
1460 if (info->control.sta)
1461 *aid = info->control.sta->aid;
d577e7cd
CL
1462
1463 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
c772a08b 1464 *flags |= P54_HDR_FLAG_DATA_OUT_NOCANCEL;
29701e5a 1465 break;
94585b09
CL
1466 }
1467 return ret;
1468}
1469
25900ef0
CL
1470static u8 p54_convert_algo(enum ieee80211_key_alg alg)
1471{
1472 switch (alg) {
1473 case ALG_WEP:
1474 return P54_CRYPTO_WEP;
1475 case ALG_TKIP:
1476 return P54_CRYPTO_TKIPMICHAEL;
1477 case ALG_CCMP:
1478 return P54_CRYPTO_AESCCMP;
1479 default:
1480 return 0;
1481 }
1482}
1483
e039fa4a 1484static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 1485{
e039fa4a 1486 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
a15bd005 1487 struct ieee80211_tx_queue_stats *current_queue;
eff1a59c 1488 struct p54_common *priv = dev->priv;
27df605e
JL
1489 struct p54_hdr *hdr;
1490 struct p54_tx_data *txhdr;
db4186cf 1491 size_t padding, len, tim_len = 0;
c772a08b 1492 int i, j, ridx, ret;
94585b09 1493 u16 hdr_flags = 0, aid = 0;
25900ef0 1494 u8 rate, queue, crypt_offset = 0;
aaa15535 1495 u8 cts_rate = 0x20;
e6a9854b 1496 u8 rc_flags;
c12abae3
JB
1497 u8 calculated_tries[4];
1498 u8 nrates = 0, nremaining = 8;
eff1a59c 1499
94585b09
CL
1500 queue = skb_get_queue_mapping(skb);
1501
c772a08b
CL
1502 ret = p54_tx_fill(dev, skb, info, &queue, &tim_len, &hdr_flags, &aid);
1503 current_queue = &priv->tx_stats[queue];
1504 if (unlikely((current_queue->len > current_queue->limit) && ret))
1505 return NETDEV_TX_BUSY;
1506 current_queue->len++;
1507 current_queue->count++;
1508 if ((current_queue->len == current_queue->limit) && ret)
1509 ieee80211_stop_queue(dev, skb_get_queue_mapping(skb));
eff1a59c
MW
1510
1511 padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3;
1512 len = skb->len;
1513
25900ef0
CL
1514 if (info->control.hw_key) {
1515 crypt_offset = ieee80211_get_hdrlen_from_skb(skb);
1516 if (info->control.hw_key->alg == ALG_TKIP) {
1517 u8 *iv = (u8 *)(skb->data + crypt_offset);
1518 /*
1519 * The firmware excepts that the IV has to have
1520 * this special format
1521 */
1522 iv[1] = iv[0];
1523 iv[0] = iv[2];
1524 iv[2] = 0;
1525 }
1526 }
1527
27df605e
JL
1528 txhdr = (struct p54_tx_data *) skb_push(skb, sizeof(*txhdr) + padding);
1529 hdr = (struct p54_hdr *) skb_push(skb, sizeof(*hdr));
eff1a59c
MW
1530
1531 if (padding)
9e7f3f8e 1532 hdr_flags |= P54_HDR_FLAG_DATA_ALIGN;
94585b09 1533 hdr->type = cpu_to_le16(aid);
27df605e 1534 hdr->rts_tries = info->control.rates[0].count;
c12abae3
JB
1535
1536 /*
1537 * we register the rates in perfect order, and
1538 * RTS/CTS won't happen on 5 GHz
1539 */
1540 cts_rate = info->control.rts_cts_rate_idx;
1541
1542 memset(&txhdr->rateset, 0, sizeof(txhdr->rateset));
1543
1544 /* see how many rates got used */
1545 for (i = 0; i < 4; i++) {
1546 if (info->control.rates[i].idx < 0)
1547 break;
1548 nrates++;
1549 }
1550
1551 /* limit tries to 8/nrates per rate */
1552 for (i = 0; i < nrates; i++) {
1553 /*
1554 * The magic expression here is equivalent to 8/nrates for
1555 * all values that matter, but avoids division and jumps.
1556 * Note that nrates can only take the values 1 through 4.
1557 */
1558 calculated_tries[i] = min_t(int, ((15 >> nrates) | 1) + 1,
1559 info->control.rates[i].count);
1560 nremaining -= calculated_tries[i];
aaa15535 1561 }
c12abae3
JB
1562
1563 /* if there are tries left, distribute from back to front */
1564 for (i = nrates - 1; nremaining > 0 && i >= 0; i--) {
1565 int tmp = info->control.rates[i].count - calculated_tries[i];
1566
1567 if (tmp <= 0)
1568 continue;
1569 /* RC requested more tries at this rate */
1570
1571 tmp = min_t(int, tmp, nremaining);
1572 calculated_tries[i] += tmp;
1573 nremaining -= tmp;
aaa15535 1574 }
c12abae3
JB
1575
1576 ridx = 0;
1577 for (i = 0; i < nrates && ridx < 8; i++) {
1578 /* we register the rates in perfect order */
1579 rate = info->control.rates[i].idx;
1580 if (info->band == IEEE80211_BAND_5GHZ)
1581 rate += 4;
1582
1583 /* store the count we actually calculated for TX status */
1584 info->control.rates[i].count = calculated_tries[i];
1585
1586 rc_flags = info->control.rates[i].flags;
1587 if (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) {
1588 rate |= 0x10;
1589 cts_rate |= 0x10;
1590 }
1591 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
1592 rate |= 0x40;
1593 else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1594 rate |= 0x20;
1595 for (j = 0; j < calculated_tries[i] && ridx < 8; j++) {
1596 txhdr->rateset[ridx] = rate;
1597 ridx++;
1598 }
1599 }
9e7f3f8e
CL
1600
1601 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
1602 hdr_flags |= P54_HDR_FLAG_DATA_OUT_SEQNR;
1603
1604 /* TODO: enable bursting */
1605 hdr->flags = cpu_to_le16(hdr_flags);
27df605e 1606 hdr->tries = ridx;
27df605e 1607 txhdr->rts_rate_idx = 0;
25900ef0 1608 if (info->control.hw_key) {
25900ef0
CL
1609 txhdr->key_type = p54_convert_algo(info->control.hw_key->alg);
1610 txhdr->key_len = min((u8)16, info->control.hw_key->keylen);
1611 memcpy(txhdr->key, info->control.hw_key->key, txhdr->key_len);
1612 if (info->control.hw_key->alg == ALG_TKIP) {
1613 if (unlikely(skb_tailroom(skb) < 12))
1614 goto err;
1615 /* reserve space for the MIC key */
1616 len += 8;
1617 memcpy(skb_put(skb, 8), &(info->control.hw_key->key
1618 [NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY]), 8);
1619 }
1620 /* reserve some space for ICV */
1621 len += info->control.hw_key->icv_len;
c1d34c1d
CL
1622 memset(skb_put(skb, info->control.hw_key->icv_len), 0,
1623 info->control.hw_key->icv_len);
25900ef0
CL
1624 } else {
1625 txhdr->key_type = 0;
1626 txhdr->key_len = 0;
1627 }
1628 txhdr->crypt_offset = crypt_offset;
94585b09 1629 txhdr->hw_queue = queue;
a15bd005 1630 txhdr->backlog = current_queue->len;
27df605e 1631 memset(txhdr->durations, 0, sizeof(txhdr->durations));
78eb7484
CL
1632 txhdr->tx_antenna = ((info->antenna_sel_tx == 0) ?
1633 2 : info->antenna_sel_tx - 1) & priv->tx_diversity_mask;
6917f506
CL
1634 if (priv->rxhw == PDR_SYNTH_FRONTEND_LONGBOW) {
1635 txhdr->longbow.cts_rate = cts_rate;
1636 txhdr->longbow.output_power = cpu_to_le16(priv->output_power);
1637 } else {
1638 txhdr->normal.output_power = priv->output_power;
1639 txhdr->normal.cts_rate = cts_rate;
1640 }
eff1a59c
MW
1641 if (padding)
1642 txhdr->align[0] = padding;
1643
25900ef0 1644 hdr->len = cpu_to_le16(len);
e039fa4a 1645 /* modifies skb->cb and with it info, so must be last! */
25900ef0
CL
1646 if (unlikely(p54_assign_address(dev, skb, hdr, skb->len + tim_len)))
1647 goto err;
0a5ec96a 1648 priv->tx(dev, skb);
54fdb040
CL
1649
1650 queue_delayed_work(dev->workqueue, &priv->work,
1651 msecs_to_jiffies(P54_TX_FRAME_LIFETIME));
1652
acbaf32e 1653 return NETDEV_TX_OK;
25900ef0
CL
1654
1655 err:
1656 skb_pull(skb, sizeof(*hdr) + sizeof(*txhdr) + padding);
a15bd005
CL
1657 current_queue->len--;
1658 current_queue->count--;
25900ef0 1659 return NETDEV_TX_BUSY;
eff1a59c
MW
1660}
1661
b2023ddc 1662static int p54_setup_mac(struct ieee80211_hw *dev)
eff1a59c
MW
1663{
1664 struct p54_common *priv = dev->priv;
b92f30d6 1665 struct sk_buff *skb;
5e73444e 1666 struct p54_setup_mac *setup;
b2023ddc 1667 u16 mode;
eff1a59c 1668
63f2dc9f
CL
1669 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*setup),
1670 P54_CONTROL_TYPE_SETUP, GFP_ATOMIC);
b92f30d6
CL
1671 if (!skb)
1672 return -ENOMEM;
eff1a59c 1673
5e73444e 1674 setup = (struct p54_setup_mac *) skb_put(skb, sizeof(*setup));
b2023ddc
CL
1675 if (dev->conf.radio_enabled) {
1676 switch (priv->mode) {
1677 case NL80211_IFTYPE_STATION:
1678 mode = P54_FILTER_TYPE_STATION;
1679 break;
1680 case NL80211_IFTYPE_AP:
1681 mode = P54_FILTER_TYPE_AP;
1682 break;
1683 case NL80211_IFTYPE_ADHOC:
1684 case NL80211_IFTYPE_MESH_POINT:
1685 mode = P54_FILTER_TYPE_IBSS;
1686 break;
29701e5a
CL
1687 case NL80211_IFTYPE_MONITOR:
1688 mode = P54_FILTER_TYPE_PROMISCUOUS;
1689 break;
b2023ddc 1690 default:
efeada2c 1691 mode = P54_FILTER_TYPE_HIBERNATE;
b2023ddc
CL
1692 break;
1693 }
29701e5a
CL
1694
1695 /*
1696 * "TRANSPARENT and PROMISCUOUS are mutually exclusive"
1697 * STSW45X0C LMAC API - page 12
1698 */
51eed992
CL
1699 if (((priv->filter_flags & FIF_PROMISC_IN_BSS) ||
1700 (priv->filter_flags & FIF_OTHER_BSS)) &&
29701e5a 1701 (mode != P54_FILTER_TYPE_PROMISCUOUS))
b2023ddc
CL
1702 mode |= P54_FILTER_TYPE_TRANSPARENT;
1703 } else
efeada2c 1704 mode = P54_FILTER_TYPE_HIBERNATE;
b2023ddc 1705
5e73444e
CL
1706 setup->mac_mode = cpu_to_le16(mode);
1707 memcpy(setup->mac_addr, priv->mac_addr, ETH_ALEN);
b2023ddc 1708 memcpy(setup->bssid, priv->bssid, ETH_ALEN);
78eb7484 1709 setup->rx_antenna = 2 & priv->rx_diversity_mask; /* automatic */
9483407d 1710 setup->rx_align = 0;
19c19d54 1711 if (priv->fw_var < 0x500) {
ced09574 1712 setup->v1.basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
9483407d 1713 memset(setup->v1.rts_rates, 0, 8);
5e73444e
CL
1714 setup->v1.rx_addr = cpu_to_le32(priv->rx_end);
1715 setup->v1.max_rx = cpu_to_le16(priv->rx_mtu);
1716 setup->v1.rxhw = cpu_to_le16(priv->rxhw);
ced09574 1717 setup->v1.wakeup_timer = cpu_to_le16(priv->wakeup_timer);
5e73444e 1718 setup->v1.unalloc0 = cpu_to_le16(0);
19c19d54 1719 } else {
5e73444e
CL
1720 setup->v2.rx_addr = cpu_to_le32(priv->rx_end);
1721 setup->v2.max_rx = cpu_to_le16(priv->rx_mtu);
1722 setup->v2.rxhw = cpu_to_le16(priv->rxhw);
ced09574 1723 setup->v2.timer = cpu_to_le16(priv->wakeup_timer);
5e73444e 1724 setup->v2.truncate = cpu_to_le16(48896);
ced09574 1725 setup->v2.basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
5e73444e
CL
1726 setup->v2.sbss_offset = 0;
1727 setup->v2.mcast_window = 0;
1728 setup->v2.rx_rssi_threshold = 0;
1729 setup->v2.rx_ed_threshold = 0;
1730 setup->v2.ref_clock = cpu_to_le32(644245094);
1731 setup->v2.lpf_bandwidth = cpu_to_le16(65535);
1732 setup->v2.osc_start_delay = cpu_to_le16(65535);
19c19d54 1733 }
0a5ec96a 1734 priv->tx(dev, skb);
eff1a59c
MW
1735 return 0;
1736}
1737
69ba3e5d 1738static int p54_scan(struct ieee80211_hw *dev, u16 mode, u16 dwell)
eff1a59c
MW
1739{
1740 struct p54_common *priv = dev->priv;
b92f30d6 1741 struct sk_buff *skb;
6917f506
CL
1742 struct p54_hdr *hdr;
1743 struct p54_scan_head *head;
1744 struct p54_iq_autocal_entry *iq_autocal;
1745 union p54_scan_body_union *body;
1746 struct p54_scan_tail_rate *rate;
1747 struct pda_rssi_cal_entry *rssi;
eff1a59c 1748 unsigned int i;
eff1a59c 1749 void *entry;
69ba3e5d 1750 int band = dev->conf.channel->band;
83cf1b6e 1751 __le16 freq = cpu_to_le16(dev->conf.channel->center_freq);
eff1a59c 1752
6917f506
CL
1753 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*head) +
1754 2 + sizeof(*iq_autocal) + sizeof(*body) +
1755 sizeof(*rate) + 2 * sizeof(*rssi),
63f2dc9f 1756 P54_CONTROL_TYPE_SCAN, GFP_ATOMIC);
b92f30d6 1757 if (!skb)
eff1a59c
MW
1758 return -ENOMEM;
1759
6917f506
CL
1760 head = (struct p54_scan_head *) skb_put(skb, sizeof(*head));
1761 memset(head->scan_params, 0, sizeof(head->scan_params));
1762 head->mode = cpu_to_le16(mode);
1763 head->dwell = cpu_to_le16(dwell);
1764 head->freq = freq;
eff1a59c 1765
6917f506
CL
1766 if (priv->rxhw == PDR_SYNTH_FRONTEND_LONGBOW) {
1767 __le16 *pa_power_points = (__le16 *) skb_put(skb, 2);
1768 *pa_power_points = cpu_to_le16(0x0c);
1769 }
1770
1771 iq_autocal = (void *) skb_put(skb, sizeof(*iq_autocal));
eff1a59c
MW
1772 for (i = 0; i < priv->iq_autocal_len; i++) {
1773 if (priv->iq_autocal[i].freq != freq)
1774 continue;
1775
6917f506
CL
1776 memcpy(iq_autocal, &priv->iq_autocal[i].params,
1777 sizeof(struct p54_iq_autocal_entry));
eff1a59c
MW
1778 break;
1779 }
1780 if (i == priv->iq_autocal_len)
1781 goto err;
1782
6917f506
CL
1783 if (priv->rxhw == PDR_SYNTH_FRONTEND_LONGBOW)
1784 body = (void *) skb_put(skb, sizeof(body->longbow));
1785 else
1786 body = (void *) skb_put(skb, sizeof(body->normal));
1787
83cf1b6e 1788 for (i = 0; i < priv->output_limit->entries; i++) {
83cf1b6e 1789 __le16 *entry_freq = (void *) (priv->output_limit->data +
6917f506 1790 priv->output_limit->entry_size * i);
83cf1b6e
CL
1791
1792 if (*entry_freq != freq)
eff1a59c
MW
1793 continue;
1794
6917f506
CL
1795 if (priv->rxhw == PDR_SYNTH_FRONTEND_LONGBOW) {
1796 memcpy(&body->longbow.power_limits,
1797 (void *) entry_freq + sizeof(__le16),
1798 priv->output_limit->entry_size);
1799 } else {
1800 struct pda_channel_output_limit *limits =
1801 (void *) entry_freq;
1802
1803 body->normal.val_barker = 0x38;
1804 body->normal.val_bpsk = body->normal.dup_bpsk =
1805 limits->val_bpsk;
1806 body->normal.val_qpsk = body->normal.dup_qpsk =
1807 limits->val_qpsk;
1808 body->normal.val_16qam = body->normal.dup_16qam =
1809 limits->val_16qam;
1810 body->normal.val_64qam = body->normal.dup_64qam =
1811 limits->val_64qam;
1812 }
eff1a59c
MW
1813 break;
1814 }
83cf1b6e 1815 if (i == priv->output_limit->entries)
eff1a59c
MW
1816 goto err;
1817
83cf1b6e
CL
1818 entry = (void *)(priv->curve_data->data + priv->curve_data->offset);
1819 for (i = 0; i < priv->curve_data->entries; i++) {
eff1a59c 1820 if (*((__le16 *)entry) != freq) {
83cf1b6e 1821 entry += priv->curve_data->entry_size;
eff1a59c
MW
1822 continue;
1823 }
1824
6917f506
CL
1825 if (priv->rxhw == PDR_SYNTH_FRONTEND_LONGBOW) {
1826 memcpy(&body->longbow.curve_data,
1827 (void *) entry + sizeof(__le16),
1828 priv->curve_data->entry_size);
1829 } else {
1830 struct p54_scan_body *chan = &body->normal;
1831 struct pda_pa_curve_data *curve_data =
1832 (void *) priv->curve_data->data;
1833
1834 entry += sizeof(__le16);
1835 chan->pa_points_per_curve = 8;
1836 memset(chan->curve_data, 0, sizeof(*chan->curve_data));
1837 memcpy(chan->curve_data, entry,
1838 sizeof(struct p54_pa_curve_data_sample) *
1839 min((u8)8, curve_data->points_per_channel));
1840 }
eff1a59c
MW
1841 break;
1842 }
83cf1b6e
CL
1843 if (i == priv->curve_data->entries)
1844 goto err;
eff1a59c 1845
6917f506
CL
1846 if ((priv->fw_var >= 0x500) && (priv->fw_var < 0x509)) {
1847 rate = (void *) skb_put(skb, sizeof(*rate));
1848 rate->basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
1849 for (i = 0; i < sizeof(rate->rts_rates); i++)
1850 rate->rts_rates[i] = i;
19c19d54 1851 }
6917f506
CL
1852
1853 rssi = (struct pda_rssi_cal_entry *) skb_put(skb, sizeof(*rssi));
1854 rssi->mul = cpu_to_le16(priv->rssical_db[band].mul);
1855 rssi->add = cpu_to_le16(priv->rssical_db[band].add);
1856 if (priv->rxhw == PDR_SYNTH_FRONTEND_LONGBOW) {
1857 /* Longbow frontend needs ever more */
1858 rssi = (void *) skb_put(skb, sizeof(*rssi));
1859 rssi->mul = cpu_to_le16(priv->rssical_db[band].longbow_unkn);
1860 rssi->add = cpu_to_le16(priv->rssical_db[band].longbow_unk2);
1861 }
1862
1863 if (priv->fw_var >= 0x509) {
1864 rate = (void *) skb_put(skb, sizeof(*rate));
1865 rate->basic_rate_mask = cpu_to_le32(priv->basic_rate_mask);
1866 for (i = 0; i < sizeof(rate->rts_rates); i++)
1867 rate->rts_rates[i] = i;
1868 }
1869
1870 hdr = (struct p54_hdr *) skb->data;
1871 hdr->len = cpu_to_le16(skb->len - sizeof(*hdr));
1872
0a5ec96a 1873 priv->tx(dev, skb);
eff1a59c
MW
1874 return 0;
1875
1876 err:
1877 printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy));
ef15aa49 1878 p54_free_skb(dev, skb);
eff1a59c
MW
1879 return -EINVAL;
1880}
1881
d0b45aef 1882static int p54_set_leds(struct ieee80211_hw *dev)
eff1a59c
MW
1883{
1884 struct p54_common *priv = dev->priv;
b92f30d6 1885 struct sk_buff *skb;
27df605e 1886 struct p54_led *led;
eff1a59c 1887
63f2dc9f
CL
1888 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*led),
1889 P54_CONTROL_TYPE_LED, GFP_ATOMIC);
b92f30d6 1890 if (!skb)
eff1a59c
MW
1891 return -ENOMEM;
1892
d0b45aef
CL
1893 led = (struct p54_led *) skb_put(skb, sizeof(*led));
1894 led->flags = cpu_to_le16(0x0003);
1895 led->mask[0] = led->mask[1] = cpu_to_le16(priv->softled_state);
1896 led->delay[0] = cpu_to_le16(1);
1897 led->delay[1] = cpu_to_le16(0);
0a5ec96a 1898 priv->tx(dev, skb);
eff1a59c
MW
1899 return 0;
1900}
1901
3330d7be 1902#define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, _txop) \
eff1a59c
MW
1903do { \
1904 queue.aifs = cpu_to_le16(ai_fs); \
1905 queue.cwmin = cpu_to_le16(cw_min); \
1906 queue.cwmax = cpu_to_le16(cw_max); \
3330d7be 1907 queue.txop = cpu_to_le16(_txop); \
eff1a59c
MW
1908} while(0)
1909
0fdd7c5d 1910static int p54_set_edcf(struct ieee80211_hw *dev)
eff1a59c
MW
1911{
1912 struct p54_common *priv = dev->priv;
b92f30d6 1913 struct sk_buff *skb;
0fdd7c5d 1914 struct p54_edcf *edcf;
eff1a59c 1915
63f2dc9f
CL
1916 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*edcf),
1917 P54_CONTROL_TYPE_DCFINIT, GFP_ATOMIC);
b92f30d6 1918 if (!skb)
0fdd7c5d
CL
1919 return -ENOMEM;
1920
b92f30d6 1921 edcf = (struct p54_edcf *)skb_put(skb, sizeof(*edcf));
40333e4f 1922 if (priv->use_short_slot) {
0fdd7c5d
CL
1923 edcf->slottime = 9;
1924 edcf->sifs = 0x10;
1925 edcf->eofpad = 0x00;
eff1a59c 1926 } else {
0fdd7c5d
CL
1927 edcf->slottime = 20;
1928 edcf->sifs = 0x0a;
1929 edcf->eofpad = 0x06;
eff1a59c 1930 }
eff1a59c 1931 /* (see prism54/isl_oid.h for further details) */
0fdd7c5d
CL
1932 edcf->frameburst = cpu_to_le16(0);
1933 edcf->round_trip_delay = cpu_to_le16(0);
9483407d 1934 edcf->flags = 0;
0fdd7c5d
CL
1935 memset(edcf->mapping, 0, sizeof(edcf->mapping));
1936 memcpy(edcf->queue, priv->qos_params, sizeof(edcf->queue));
0a5ec96a 1937 priv->tx(dev, skb);
0fdd7c5d 1938 return 0;
eff1a59c
MW
1939}
1940
2b8d4e2e
CL
1941static int p54_set_ps(struct ieee80211_hw *dev)
1942{
1943 struct p54_common *priv = dev->priv;
1944 struct sk_buff *skb;
1945 struct p54_psm *psm;
1946 u16 mode;
1947 int i;
1948
1949 if (dev->conf.flags & IEEE80211_CONF_PS)
f13027af
CL
1950 mode = P54_PSM | P54_PSM_BEACON_TIMEOUT | P54_PSM_DTIM |
1951 P54_PSM_CHECKSUM | P54_PSM_MCBC;
2b8d4e2e
CL
1952 else
1953 mode = P54_PSM_CAM;
1954
63f2dc9f
CL
1955 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*psm),
1956 P54_CONTROL_TYPE_PSM, GFP_ATOMIC);
2b8d4e2e
CL
1957 if (!skb)
1958 return -ENOMEM;
1959
1960 psm = (struct p54_psm *)skb_put(skb, sizeof(*psm));
1961 psm->mode = cpu_to_le16(mode);
1962 psm->aid = cpu_to_le16(priv->aid);
1963 for (i = 0; i < ARRAY_SIZE(psm->intervals); i++) {
1964 psm->intervals[i].interval =
1965 cpu_to_le16(dev->conf.listen_interval);
acbaf32e 1966 psm->intervals[i].periods = cpu_to_le16(1);
2b8d4e2e
CL
1967 }
1968
f13027af 1969 psm->beacon_rssi_skip_max = 200;
2b8d4e2e 1970 psm->rssi_delta_threshold = 0;
f13027af
CL
1971 psm->nr = 10;
1972 psm->exclude[0] = 0;
2b8d4e2e
CL
1973
1974 priv->tx(dev, skb);
1975
1976 return 0;
1977}
1978
e5ea92a7
CL
1979static int p54_beacon_tim(struct sk_buff *skb)
1980{
1981 /*
1982 * the good excuse for this mess is ... the firmware.
1983 * The dummy TIM MUST be at the end of the beacon frame,
1984 * because it'll be overwritten!
1985 */
1986
1987 struct ieee80211_mgmt *mgmt = (void *)skb->data;
1988 u8 *pos, *end;
1989
02e37ba1 1990 if (skb->len <= sizeof(mgmt))
e5ea92a7 1991 return -EINVAL;
e5ea92a7
CL
1992
1993 pos = (u8 *)mgmt->u.beacon.variable;
1994 end = skb->data + skb->len;
1995 while (pos < end) {
02e37ba1 1996 if (pos + 2 + pos[1] > end)
e5ea92a7 1997 return -EINVAL;
e5ea92a7
CL
1998
1999 if (pos[0] == WLAN_EID_TIM) {
2000 u8 dtim_len = pos[1];
2001 u8 dtim_period = pos[3];
2002 u8 *next = pos + 2 + dtim_len;
2003
02e37ba1 2004 if (dtim_len < 3)
e5ea92a7 2005 return -EINVAL;
02e37ba1 2006
e5ea92a7
CL
2007 memmove(pos, next, end - next);
2008
2009 if (dtim_len > 3)
2010 skb_trim(skb, skb->len - (dtim_len - 3));
2011
2012 pos = end - (dtim_len + 2);
2013
2014 /* add the dummy at the end */
2015 pos[0] = WLAN_EID_TIM;
2016 pos[1] = 3;
2017 pos[2] = 0;
2018 pos[3] = dtim_period;
2019 pos[4] = 0;
2020 return 0;
2021 }
2022 pos += 2 + pos[1];
2023 }
2024 return 0;
2025}
2026
2027static int p54_beacon_update(struct ieee80211_hw *dev,
2028 struct ieee80211_vif *vif)
2029{
2030 struct p54_common *priv = dev->priv;
2031 struct sk_buff *beacon;
2032 int ret;
2033
2034 if (priv->cached_beacon) {
2035 p54_tx_cancel(dev, priv->cached_beacon);
2036 /* wait for the last beacon the be freed */
2037 msleep(10);
2038 }
2039
2040 beacon = ieee80211_beacon_get(dev, vif);
2041 if (!beacon)
2042 return -ENOMEM;
2043 ret = p54_beacon_tim(beacon);
2044 if (ret)
2045 return ret;
2046 ret = p54_tx(dev, beacon);
2047 if (ret)
2048 return ret;
2049 priv->cached_beacon = beacon;
2050 priv->tsf_high32 = 0;
2051 priv->tsf_low32 = 0;
2052
2053 return 0;
2054}
2055
0f1be978
CL
2056static int p54_start(struct ieee80211_hw *dev)
2057{
2058 struct p54_common *priv = dev->priv;
2059 int err;
cc6de669 2060
9e7f3f8e 2061 mutex_lock(&priv->conf_mutex);
4150c572 2062 err = priv->open(dev);
40db0b22
CL
2063 if (err)
2064 goto out;
0fdd7c5d
CL
2065 P54_SET_QUEUE(priv->qos_params[0], 0x0002, 0x0003, 0x0007, 47);
2066 P54_SET_QUEUE(priv->qos_params[1], 0x0002, 0x0007, 0x000f, 94);
2067 P54_SET_QUEUE(priv->qos_params[2], 0x0003, 0x000f, 0x03ff, 0);
2068 P54_SET_QUEUE(priv->qos_params[3], 0x0007, 0x000f, 0x03ff, 0);
2069 err = p54_set_edcf(dev);
40db0b22
CL
2070 if (err)
2071 goto out;
b2023ddc
CL
2072
2073 memset(priv->bssid, ~0, ETH_ALEN);
40db0b22 2074 priv->mode = NL80211_IFTYPE_MONITOR;
b2023ddc
CL
2075 err = p54_setup_mac(dev);
2076 if (err) {
2077 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
2078 goto out;
2079 }
4150c572 2080
54fdb040
CL
2081 queue_delayed_work(dev->workqueue, &priv->work, 0);
2082
d0b45aef
CL
2083 priv->softled_state = 0;
2084 err = p54_set_leds(dev);
2085
40db0b22 2086out:
9e7f3f8e 2087 mutex_unlock(&priv->conf_mutex);
4150c572
JB
2088 return err;
2089}
2090
2091static void p54_stop(struct ieee80211_hw *dev)
2092{
2093 struct p54_common *priv = dev->priv;
0ca1b08e 2094 struct sk_buff *skb;
cc6de669 2095
9e7f3f8e 2096 mutex_lock(&priv->conf_mutex);
59651e89 2097 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
d0b45aef
CL
2098 priv->softled_state = 0;
2099 p54_set_leds(dev);
2100
dce07258
CL
2101#ifdef CONFIG_P54_LEDS
2102 cancel_delayed_work_sync(&priv->led_work);
2103#endif /* CONFIG_P54_LEDS */
54fdb040 2104 cancel_delayed_work_sync(&priv->work);
e5ea92a7
CL
2105 if (priv->cached_beacon)
2106 p54_tx_cancel(dev, priv->cached_beacon);
2107
59651e89 2108 priv->stop(dev);
0ca1b08e
DM
2109 while ((skb = skb_dequeue(&priv->tx_queue)))
2110 kfree_skb(skb);
e5ea92a7 2111 priv->cached_beacon = NULL;
a0db663f 2112 priv->tsf_high32 = priv->tsf_low32 = 0;
9e7f3f8e 2113 mutex_unlock(&priv->conf_mutex);
4150c572
JB
2114}
2115
eff1a59c
MW
2116static int p54_add_interface(struct ieee80211_hw *dev,
2117 struct ieee80211_if_init_conf *conf)
2118{
2119 struct p54_common *priv = dev->priv;
eff1a59c 2120
9e7f3f8e
CL
2121 mutex_lock(&priv->conf_mutex);
2122 if (priv->mode != NL80211_IFTYPE_MONITOR) {
2123 mutex_unlock(&priv->conf_mutex);
4150c572 2124 return -EOPNOTSUPP;
9e7f3f8e 2125 }
eff1a59c 2126
f13027af
CL
2127 priv->vif = conf->vif;
2128
eff1a59c 2129 switch (conf->type) {
05c914fe 2130 case NL80211_IFTYPE_STATION:
e5ea92a7
CL
2131 case NL80211_IFTYPE_ADHOC:
2132 case NL80211_IFTYPE_AP:
d131bb59 2133 case NL80211_IFTYPE_MESH_POINT:
eff1a59c
MW
2134 priv->mode = conf->type;
2135 break;
2136 default:
9e7f3f8e 2137 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW
2138 return -EOPNOTSUPP;
2139 }
2140
4150c572 2141 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
b2023ddc 2142 p54_setup_mac(dev);
9e7f3f8e 2143 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW
2144 return 0;
2145}
2146
2147static void p54_remove_interface(struct ieee80211_hw *dev,
2148 struct ieee80211_if_init_conf *conf)
2149{
2150 struct p54_common *priv = dev->priv;
9e7f3f8e
CL
2151
2152 mutex_lock(&priv->conf_mutex);
f13027af 2153 priv->vif = NULL;
e5ea92a7
CL
2154 if (priv->cached_beacon)
2155 p54_tx_cancel(dev, priv->cached_beacon);
05c914fe 2156 priv->mode = NL80211_IFTYPE_MONITOR;
4150c572 2157 memset(priv->mac_addr, 0, ETH_ALEN);
b2023ddc
CL
2158 memset(priv->bssid, 0, ETH_ALEN);
2159 p54_setup_mac(dev);
9e7f3f8e 2160 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW
2161}
2162
e8975581 2163static int p54_config(struct ieee80211_hw *dev, u32 changed)
eff1a59c 2164{
26d1597c 2165 int ret = 0;
6041e2a0 2166 struct p54_common *priv = dev->priv;
e8975581 2167 struct ieee80211_conf *conf = &dev->conf;
eff1a59c 2168
6041e2a0 2169 mutex_lock(&priv->conf_mutex);
b2023ddc
CL
2170 if (changed & IEEE80211_CONF_CHANGE_POWER)
2171 priv->output_power = conf->power_level << 2;
2172 if (changed & IEEE80211_CONF_CHANGE_RADIO_ENABLED) {
2173 ret = p54_setup_mac(dev);
2174 if (ret)
2175 goto out;
2176 }
2177 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
69ba3e5d 2178 ret = p54_scan(dev, P54_SCAN_EXIT, 0);
b2023ddc
CL
2179 if (ret)
2180 goto out;
2181 }
2b8d4e2e
CL
2182 if (changed & IEEE80211_CONF_CHANGE_PS) {
2183 ret = p54_set_ps(dev);
2184 if (ret)
2185 goto out;
2186 }
b2023ddc
CL
2187
2188out:
6041e2a0 2189 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW
2190 return ret;
2191}
2192
4150c572
JB
2193static void p54_configure_filter(struct ieee80211_hw *dev,
2194 unsigned int changed_flags,
2195 unsigned int *total_flags,
2196 int mc_count, struct dev_mc_list *mclist)
2197{
2198 struct p54_common *priv = dev->priv;
2199
b2023ddc 2200 *total_flags &= FIF_PROMISC_IN_BSS |
346de732 2201 FIF_OTHER_BSS;
78d57eb2
CL
2202
2203 priv->filter_flags = *total_flags;
4150c572 2204
51eed992 2205 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
b2023ddc 2206 p54_setup_mac(dev);
4150c572
JB
2207}
2208
e100bb64 2209static int p54_conf_tx(struct ieee80211_hw *dev, u16 queue,
eff1a59c
MW
2210 const struct ieee80211_tx_queue_params *params)
2211{
2212 struct p54_common *priv = dev->priv;
9e7f3f8e 2213 int ret;
eff1a59c 2214
9e7f3f8e 2215 mutex_lock(&priv->conf_mutex);
3df5ee60 2216 if ((params) && !(queue > 4)) {
0fdd7c5d 2217 P54_SET_QUEUE(priv->qos_params[queue], params->aifs,
3330d7be 2218 params->cw_min, params->cw_max, params->txop);
b50563a6 2219 ret = p54_set_edcf(dev);
eff1a59c 2220 } else
9e7f3f8e 2221 ret = -EINVAL;
9e7f3f8e
CL
2222 mutex_unlock(&priv->conf_mutex);
2223 return ret;
eff1a59c
MW
2224}
2225
1b997534
CL
2226static int p54_init_xbow_synth(struct ieee80211_hw *dev)
2227{
2228 struct p54_common *priv = dev->priv;
b92f30d6 2229 struct sk_buff *skb;
27df605e 2230 struct p54_xbow_synth *xbow;
1b997534 2231
63f2dc9f
CL
2232 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*xbow),
2233 P54_CONTROL_TYPE_XBOW_SYNTH_CFG, GFP_KERNEL);
b92f30d6 2234 if (!skb)
1b997534
CL
2235 return -ENOMEM;
2236
27df605e 2237 xbow = (struct p54_xbow_synth *)skb_put(skb, sizeof(*xbow));
1b997534
CL
2238 xbow->magic1 = cpu_to_le16(0x1);
2239 xbow->magic2 = cpu_to_le16(0x2);
2240 xbow->freq = cpu_to_le16(5390);
b92f30d6 2241 memset(xbow->padding, 0, sizeof(xbow->padding));
0a5ec96a 2242 priv->tx(dev, skb);
1b997534
CL
2243 return 0;
2244}
2245
54fdb040 2246static void p54_work(struct work_struct *work)
cc6de669 2247{
54fdb040
CL
2248 struct p54_common *priv = container_of(work, struct p54_common,
2249 work.work);
2250 struct ieee80211_hw *dev = priv->hw;
2251 struct sk_buff *skb;
2252
2253 if (unlikely(priv->mode == NL80211_IFTYPE_UNSPECIFIED))
2254 return ;
2255
2256 /*
2257 * TODO: walk through tx_queue and do the following tasks
2258 * 1. initiate bursts.
2259 * 2. cancel stuck frames / reset the device if necessary.
2260 */
cc6de669 2261
63f2dc9f 2262 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL,
54fdb040
CL
2263 sizeof(struct p54_statistics),
2264 P54_CONTROL_TYPE_STAT_READBACK, GFP_KERNEL);
2265 if (!skb)
2266 return ;
cc6de669 2267
0a5ec96a 2268 priv->tx(dev, skb);
cc6de669
CL
2269}
2270
eff1a59c
MW
2271static int p54_get_stats(struct ieee80211_hw *dev,
2272 struct ieee80211_low_level_stats *stats)
2273{
cc6de669
CL
2274 struct p54_common *priv = dev->priv;
2275
cc6de669 2276 memcpy(stats, &priv->stats, sizeof(*stats));
eff1a59c
MW
2277 return 0;
2278}
2279
2280static int p54_get_tx_stats(struct ieee80211_hw *dev,
2281 struct ieee80211_tx_queue_stats *stats)
2282{
2283 struct p54_common *priv = dev->priv;
eff1a59c 2284
a15bd005
CL
2285 memcpy(stats, &priv->tx_stats[P54_QUEUE_DATA],
2286 sizeof(stats[0]) * dev->queues);
eff1a59c
MW
2287 return 0;
2288}
2289
40333e4f
CL
2290static void p54_bss_info_changed(struct ieee80211_hw *dev,
2291 struct ieee80211_vif *vif,
2292 struct ieee80211_bss_conf *info,
2293 u32 changed)
2294{
2295 struct p54_common *priv = dev->priv;
2d0ddec5
JB
2296 int ret;
2297
2298 mutex_lock(&priv->conf_mutex);
2299 if (changed & BSS_CHANGED_BSSID) {
2300 memcpy(priv->bssid, info->bssid, ETH_ALEN);
2301 ret = p54_setup_mac(dev);
2302 if (ret)
2303 goto out;
2304 }
2305
2306 if (changed & BSS_CHANGED_BEACON) {
2307 ret = p54_scan(dev, P54_SCAN_EXIT, 0);
2308 if (ret)
2309 goto out;
2310 ret = p54_setup_mac(dev);
2311 if (ret)
2312 goto out;
2313 ret = p54_beacon_update(dev, vif);
2314 if (ret)
2315 goto out;
2316 }
2317 /* XXX: this mimics having two callbacks... clean up */
2318 out:
2319 mutex_unlock(&priv->conf_mutex);
40333e4f 2320
2d0ddec5 2321 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_BEACON)) {
40333e4f 2322 priv->use_short_slot = info->use_short_slot;
0fdd7c5d 2323 p54_set_edcf(dev);
40333e4f 2324 }
ced09574
CL
2325 if (changed & BSS_CHANGED_BASIC_RATES) {
2326 if (dev->conf.channel->band == IEEE80211_BAND_5GHZ)
2327 priv->basic_rate_mask = (info->basic_rates << 4);
2328 else
2329 priv->basic_rate_mask = info->basic_rates;
b2023ddc 2330 p54_setup_mac(dev);
ced09574 2331 if (priv->fw_var >= 0x500)
69ba3e5d 2332 p54_scan(dev, P54_SCAN_EXIT, 0);
ced09574
CL
2333 }
2334 if (changed & BSS_CHANGED_ASSOC) {
2335 if (info->assoc) {
2336 priv->aid = info->aid;
2337 priv->wakeup_timer = info->beacon_int *
2338 info->dtim_period * 5;
b2023ddc 2339 p54_setup_mac(dev);
ced09574
CL
2340 }
2341 }
40333e4f
CL
2342}
2343
25900ef0 2344static int p54_set_key(struct ieee80211_hw *dev, enum set_key_cmd cmd,
dc822b5d 2345 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
25900ef0
CL
2346 struct ieee80211_key_conf *key)
2347{
2348 struct p54_common *priv = dev->priv;
2349 struct sk_buff *skb;
2350 struct p54_keycache *rxkey;
6dfe9a88 2351 int slot, ret = 0;
25900ef0
CL
2352 u8 algo = 0;
2353
2354 if (modparam_nohwcrypt)
2355 return -EOPNOTSUPP;
2356
6dfe9a88
CL
2357 mutex_lock(&priv->conf_mutex);
2358 if (cmd == SET_KEY) {
25900ef0
CL
2359 switch (key->alg) {
2360 case ALG_TKIP:
2361 if (!(priv->privacy_caps & (BR_DESC_PRIV_CAP_MICHAEL |
6dfe9a88
CL
2362 BR_DESC_PRIV_CAP_TKIP))) {
2363 ret = -EOPNOTSUPP;
2364 goto out_unlock;
2365 }
25900ef0
CL
2366 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2367 algo = P54_CRYPTO_TKIPMICHAEL;
2368 break;
2369 case ALG_WEP:
6dfe9a88
CL
2370 if (!(priv->privacy_caps & BR_DESC_PRIV_CAP_WEP)) {
2371 ret = -EOPNOTSUPP;
2372 goto out_unlock;
2373 }
25900ef0
CL
2374 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2375 algo = P54_CRYPTO_WEP;
2376 break;
2377 case ALG_CCMP:
6dfe9a88
CL
2378 if (!(priv->privacy_caps & BR_DESC_PRIV_CAP_AESCCMP)) {
2379 ret = -EOPNOTSUPP;
2380 goto out_unlock;
2381 }
25900ef0
CL
2382 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2383 algo = P54_CRYPTO_AESCCMP;
2384 break;
2385 default:
6dfe9a88
CL
2386 ret = -EOPNOTSUPP;
2387 goto out_unlock;
25900ef0 2388 }
6dfe9a88
CL
2389 slot = bitmap_find_free_region(priv->used_rxkeys,
2390 priv->rx_keycache_size, 0);
25900ef0 2391
6dfe9a88
CL
2392 if (slot < 0) {
2393 /*
2394 * The device supports the choosen algorithm, but the
2395 * firmware does not provide enough key slots to store
2396 * all of them.
2397 * But encryption offload for outgoing frames is always
2398 * possible, so we just pretend that the upload was
2399 * successful and do the decryption in software.
2400 */
25900ef0 2401
6dfe9a88
CL
2402 /* mark the key as invalid. */
2403 key->hw_key_idx = 0xff;
2404 goto out_unlock;
2405 }
2406 } else {
2407 slot = key->hw_key_idx;
2408
2409 if (slot == 0xff) {
2410 /* This key was not uploaded into the rx key cache. */
2411
2412 goto out_unlock;
2413 }
2414
2415 bitmap_release_region(priv->used_rxkeys, slot, 0);
2416 algo = 0;
25900ef0
CL
2417 }
2418
63f2dc9f 2419 skb = p54_alloc_skb(dev, P54_HDR_FLAG_CONTROL_OPSET, sizeof(*rxkey),
6dfe9a88 2420 P54_CONTROL_TYPE_RX_KEYCACHE, GFP_KERNEL);
25900ef0 2421 if (!skb) {
6dfe9a88
CL
2422 bitmap_release_region(priv->used_rxkeys, slot, 0);
2423 ret = -ENOSPC;
2424 goto out_unlock;
25900ef0
CL
2425 }
2426
25900ef0 2427 rxkey = (struct p54_keycache *)skb_put(skb, sizeof(*rxkey));
6dfe9a88 2428 rxkey->entry = slot;
25900ef0
CL
2429 rxkey->key_id = key->keyidx;
2430 rxkey->key_type = algo;
dc822b5d
JB
2431 if (sta)
2432 memcpy(rxkey->mac, sta->addr, ETH_ALEN);
25900ef0
CL
2433 else
2434 memset(rxkey->mac, ~0, ETH_ALEN);
2435 if (key->alg != ALG_TKIP) {
2436 rxkey->key_len = min((u8)16, key->keylen);
2437 memcpy(rxkey->key, key->key, rxkey->key_len);
2438 } else {
2439 rxkey->key_len = 24;
2440 memcpy(rxkey->key, key->key, 16);
2441 memcpy(&(rxkey->key[16]), &(key->key
2442 [NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]), 8);
2443 }
2444
0a5ec96a 2445 priv->tx(dev, skb);
6dfe9a88
CL
2446 key->hw_key_idx = slot;
2447
2448out_unlock:
25900ef0 2449 mutex_unlock(&priv->conf_mutex);
6dfe9a88 2450 return ret;
25900ef0
CL
2451}
2452
d8cd7eff 2453#ifdef CONFIG_P54_LEDS
dce07258
CL
2454static void p54_update_leds(struct work_struct *work)
2455{
2456 struct p54_common *priv = container_of(work, struct p54_common,
2457 led_work.work);
2458 int err, i, tmp, blink_delay = 400;
2459 bool rerun = false;
2460
2461 /* Don't toggle the LED, when the device is down. */
2462 if (priv->mode == NL80211_IFTYPE_UNSPECIFIED)
2463 return ;
2464
2465 for (i = 0; i < ARRAY_SIZE(priv->leds); i++)
2466 if (priv->leds[i].toggled) {
2467 priv->softled_state |= BIT(i);
2468
2469 tmp = 70 + 200 / (priv->leds[i].toggled);
2470 if (tmp < blink_delay)
2471 blink_delay = tmp;
2472
2473 if (priv->leds[i].led_dev.brightness == LED_OFF)
2474 rerun = true;
2475
2476 priv->leds[i].toggled =
2477 !!priv->leds[i].led_dev.brightness;
2478 } else
2479 priv->softled_state &= ~BIT(i);
2480
2481 err = p54_set_leds(priv->hw);
2482 if (err && net_ratelimit())
2483 printk(KERN_ERR "%s: failed to update LEDs.\n",
2484 wiphy_name(priv->hw->wiphy));
2485
2486 if (rerun)
2487 queue_delayed_work(priv->hw->workqueue, &priv->led_work,
2488 msecs_to_jiffies(blink_delay));
2489}
2490
d0b45aef
CL
2491static void p54_led_brightness_set(struct led_classdev *led_dev,
2492 enum led_brightness brightness)
2493{
2494 struct p54_led_dev *led = container_of(led_dev, struct p54_led_dev,
2495 led_dev);
2496 struct ieee80211_hw *dev = led->hw_dev;
2497 struct p54_common *priv = dev->priv;
d0b45aef 2498
d0b45aef
CL
2499 if (priv->mode == NL80211_IFTYPE_UNSPECIFIED)
2500 return ;
2501
dce07258
CL
2502 if (brightness) {
2503 led->toggled++;
2504 queue_delayed_work(priv->hw->workqueue, &priv->led_work,
2505 HZ/10);
2506 }
d0b45aef
CL
2507}
2508
2509static int p54_register_led(struct ieee80211_hw *dev,
d0b45aef
CL
2510 unsigned int led_index,
2511 char *name, char *trigger)
2512{
dce07258
CL
2513 struct p54_common *priv = dev->priv;
2514 struct p54_led_dev *led = &priv->leds[led_index];
d0b45aef
CL
2515 int err;
2516
2517 if (led->registered)
2518 return -EEXIST;
2519
2520 snprintf(led->name, sizeof(led->name), "p54-%s::%s",
2521 wiphy_name(dev->wiphy), name);
2522 led->hw_dev = dev;
2523 led->index = led_index;
2524 led->led_dev.name = led->name;
2525 led->led_dev.default_trigger = trigger;
2526 led->led_dev.brightness_set = p54_led_brightness_set;
2527
2528 err = led_classdev_register(wiphy_dev(dev->wiphy), &led->led_dev);
2529 if (err)
2530 printk(KERN_ERR "%s: Failed to register %s LED.\n",
2531 wiphy_name(dev->wiphy), name);
2532 else
2533 led->registered = 1;
2534
2535 return err;
2536}
2537
2538static int p54_init_leds(struct ieee80211_hw *dev)
2539{
2540 struct p54_common *priv = dev->priv;
2541 int err;
2542
2543 /*
2544 * TODO:
2545 * Figure out if the EEPROM contains some hints about the number
2546 * of available/programmable LEDs of the device.
d0b45aef
CL
2547 */
2548
dce07258
CL
2549 INIT_DELAYED_WORK(&priv->led_work, p54_update_leds);
2550
2551 err = p54_register_led(dev, 0, "assoc",
d0b45aef
CL
2552 ieee80211_get_assoc_led_name(dev));
2553 if (err)
2554 return err;
2555
dce07258 2556 err = p54_register_led(dev, 1, "tx",
d0b45aef
CL
2557 ieee80211_get_tx_led_name(dev));
2558 if (err)
2559 return err;
2560
dce07258
CL
2561 err = p54_register_led(dev, 2, "rx",
2562 ieee80211_get_rx_led_name(dev));
2563 if (err)
2564 return err;
2565
2566 err = p54_register_led(dev, 3, "radio",
2567 ieee80211_get_radio_led_name(dev));
2568 if (err)
2569 return err;
2570
d0b45aef
CL
2571 err = p54_set_leds(dev);
2572 return err;
2573}
2574
2575static void p54_unregister_leds(struct ieee80211_hw *dev)
2576{
2577 struct p54_common *priv = dev->priv;
dce07258 2578 int i;
d0b45aef 2579
dce07258
CL
2580 for (i = 0; i < ARRAY_SIZE(priv->leds); i++)
2581 if (priv->leds[i].registered)
2582 led_classdev_unregister(&priv->leds[i].led_dev);
d0b45aef 2583}
d8cd7eff 2584#endif /* CONFIG_P54_LEDS */
d0b45aef 2585
eff1a59c
MW
2586static const struct ieee80211_ops p54_ops = {
2587 .tx = p54_tx,
4150c572
JB
2588 .start = p54_start,
2589 .stop = p54_stop,
eff1a59c
MW
2590 .add_interface = p54_add_interface,
2591 .remove_interface = p54_remove_interface,
e5ea92a7 2592 .set_tim = p54_set_tim,
c772a08b 2593 .sta_notify = p54_sta_notify,
25900ef0 2594 .set_key = p54_set_key,
eff1a59c 2595 .config = p54_config,
40333e4f 2596 .bss_info_changed = p54_bss_info_changed,
4150c572 2597 .configure_filter = p54_configure_filter,
eff1a59c
MW
2598 .conf_tx = p54_conf_tx,
2599 .get_stats = p54_get_stats,
2600 .get_tx_stats = p54_get_tx_stats
2601};
2602
2603struct ieee80211_hw *p54_init_common(size_t priv_data_len)
2604{
2605 struct ieee80211_hw *dev;
2606 struct p54_common *priv;
eff1a59c
MW
2607
2608 dev = ieee80211_alloc_hw(priv_data_len, &p54_ops);
2609 if (!dev)
2610 return NULL;
2611
2612 priv = dev->priv;
54fdb040 2613 priv->hw = dev;
05c914fe 2614 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
ced09574 2615 priv->basic_rate_mask = 0x15f;
eff1a59c 2616 skb_queue_head_init(&priv->tx_queue);
94585b09 2617 dev->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cc6de669 2618 IEEE80211_HW_SIGNAL_DBM |
fade5db4 2619 IEEE80211_HW_NOISE_DBM;
f59ac048 2620
d131bb59
CL
2621 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
2622 BIT(NL80211_IFTYPE_ADHOC) |
2623 BIT(NL80211_IFTYPE_AP) |
2624 BIT(NL80211_IFTYPE_MESH_POINT);
f59ac048 2625
eff1a59c 2626 dev->channel_change_time = 1000; /* TODO: find actual value */
a15bd005
CL
2627 priv->tx_stats[P54_QUEUE_BEACON].limit = 1;
2628 priv->tx_stats[P54_QUEUE_FWSCAN].limit = 1;
2629 priv->tx_stats[P54_QUEUE_MGMT].limit = 3;
2630 priv->tx_stats[P54_QUEUE_CAB].limit = 3;
2631 priv->tx_stats[P54_QUEUE_DATA].limit = 5;
eff1a59c 2632 dev->queues = 1;
cc6de669 2633 priv->noise = -94;
c12abae3
JB
2634 /*
2635 * We support at most 8 tries no matter which rate they're at,
2636 * we cannot support max_rates * max_rate_tries as we set it
2637 * here, but setting it correctly to 4/2 or so would limit us
2638 * artificially if the RC algorithm wants just two rates, so
2639 * let's say 4/7, we'll redistribute it at TX time, see the
2640 * comments there.
2641 */
2642 dev->max_rates = 4;
2643 dev->max_rate_tries = 7;
27df605e
JL
2644 dev->extra_tx_headroom = sizeof(struct p54_hdr) + 4 +
2645 sizeof(struct p54_tx_data);
eff1a59c 2646
6041e2a0 2647 mutex_init(&priv->conf_mutex);
7cb77072 2648 init_completion(&priv->eeprom_comp);
54fdb040 2649 INIT_DELAYED_WORK(&priv->work, p54_work);
eff1a59c 2650
eff1a59c
MW
2651 return dev;
2652}
2653EXPORT_SYMBOL_GPL(p54_init_common);
2654
2ac71072
CL
2655int p54_register_common(struct ieee80211_hw *dev, struct device *pdev)
2656{
2657 int err;
2658
2659 err = ieee80211_register_hw(dev);
2660 if (err) {
2661 dev_err(pdev, "Cannot register device (%d).\n", err);
2662 return err;
2663 }
2664
d8cd7eff 2665#ifdef CONFIG_P54_LEDS
d0b45aef
CL
2666 err = p54_init_leds(dev);
2667 if (err)
2668 return err;
d8cd7eff 2669#endif /* CONFIG_P54_LEDS */
d0b45aef 2670
2ac71072
CL
2671 dev_info(pdev, "is registered as '%s'\n", wiphy_name(dev->wiphy));
2672 return 0;
2673}
2674EXPORT_SYMBOL_GPL(p54_register_common);
2675
eff1a59c
MW
2676void p54_free_common(struct ieee80211_hw *dev)
2677{
2678 struct p54_common *priv = dev->priv;
2679 kfree(priv->iq_autocal);
2680 kfree(priv->output_limit);
2681 kfree(priv->curve_data);
6dfe9a88 2682 kfree(priv->used_rxkeys);
d0b45aef 2683
d8cd7eff 2684#ifdef CONFIG_P54_LEDS
d0b45aef 2685 p54_unregister_leds(dev);
d8cd7eff 2686#endif /* CONFIG_P54_LEDS */
eff1a59c
MW
2687}
2688EXPORT_SYMBOL_GPL(p54_free_common);