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p54: Fix compilation problem on PPC
[net-next-2.6.git] / drivers / net / wireless / p54 / p54common.c
CommitLineData
eff1a59c
MW
1
2/*
3 * Common code for mac80211 Prism54 drivers
4 *
5 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
6 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
7 *
8 * Based on the islsm (softmac prism54) driver, which is:
9 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/firmware.h>
18#include <linux/etherdevice.h>
19
20#include <net/mac80211.h>
21
22#include "p54.h"
23#include "p54common.h"
24
25MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
26MODULE_DESCRIPTION("Softmac Prism54 common code");
27MODULE_LICENSE("GPL");
28MODULE_ALIAS("prism54common");
29
1b997534 30static struct ieee80211_rate p54_bgrates[] = {
8318d78a
JB
31 { .bitrate = 10, .hw_value = 0, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
32 { .bitrate = 20, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
33 { .bitrate = 55, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
34 { .bitrate = 110, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
35 { .bitrate = 60, .hw_value = 4, },
36 { .bitrate = 90, .hw_value = 5, },
37 { .bitrate = 120, .hw_value = 6, },
38 { .bitrate = 180, .hw_value = 7, },
39 { .bitrate = 240, .hw_value = 8, },
40 { .bitrate = 360, .hw_value = 9, },
41 { .bitrate = 480, .hw_value = 10, },
42 { .bitrate = 540, .hw_value = 11, },
43};
44
1b997534 45static struct ieee80211_channel p54_bgchannels[] = {
8318d78a
JB
46 { .center_freq = 2412, .hw_value = 1, },
47 { .center_freq = 2417, .hw_value = 2, },
48 { .center_freq = 2422, .hw_value = 3, },
49 { .center_freq = 2427, .hw_value = 4, },
50 { .center_freq = 2432, .hw_value = 5, },
51 { .center_freq = 2437, .hw_value = 6, },
52 { .center_freq = 2442, .hw_value = 7, },
53 { .center_freq = 2447, .hw_value = 8, },
54 { .center_freq = 2452, .hw_value = 9, },
55 { .center_freq = 2457, .hw_value = 10, },
56 { .center_freq = 2462, .hw_value = 11, },
57 { .center_freq = 2467, .hw_value = 12, },
58 { .center_freq = 2472, .hw_value = 13, },
59 { .center_freq = 2484, .hw_value = 14, },
60};
61
c2976ab0 62static struct ieee80211_supported_band band_2GHz = {
1b997534
CL
63 .channels = p54_bgchannels,
64 .n_channels = ARRAY_SIZE(p54_bgchannels),
65 .bitrates = p54_bgrates,
66 .n_bitrates = ARRAY_SIZE(p54_bgrates),
67};
68
69static struct ieee80211_rate p54_arates[] = {
70 { .bitrate = 60, .hw_value = 4, },
71 { .bitrate = 90, .hw_value = 5, },
72 { .bitrate = 120, .hw_value = 6, },
73 { .bitrate = 180, .hw_value = 7, },
74 { .bitrate = 240, .hw_value = 8, },
75 { .bitrate = 360, .hw_value = 9, },
76 { .bitrate = 480, .hw_value = 10, },
77 { .bitrate = 540, .hw_value = 11, },
78};
79
80static struct ieee80211_channel p54_achannels[] = {
81 { .center_freq = 4920 },
82 { .center_freq = 4940 },
83 { .center_freq = 4960 },
84 { .center_freq = 4980 },
85 { .center_freq = 5040 },
86 { .center_freq = 5060 },
87 { .center_freq = 5080 },
88 { .center_freq = 5170 },
89 { .center_freq = 5180 },
90 { .center_freq = 5190 },
91 { .center_freq = 5200 },
92 { .center_freq = 5210 },
93 { .center_freq = 5220 },
94 { .center_freq = 5230 },
95 { .center_freq = 5240 },
96 { .center_freq = 5260 },
97 { .center_freq = 5280 },
98 { .center_freq = 5300 },
99 { .center_freq = 5320 },
100 { .center_freq = 5500 },
101 { .center_freq = 5520 },
102 { .center_freq = 5540 },
103 { .center_freq = 5560 },
104 { .center_freq = 5580 },
105 { .center_freq = 5600 },
106 { .center_freq = 5620 },
107 { .center_freq = 5640 },
108 { .center_freq = 5660 },
109 { .center_freq = 5680 },
110 { .center_freq = 5700 },
111 { .center_freq = 5745 },
112 { .center_freq = 5765 },
113 { .center_freq = 5785 },
114 { .center_freq = 5805 },
115 { .center_freq = 5825 },
116};
117
118static struct ieee80211_supported_band band_5GHz = {
119 .channels = p54_achannels,
120 .n_channels = ARRAY_SIZE(p54_achannels),
121 .bitrates = p54_arates,
122 .n_bitrates = ARRAY_SIZE(p54_arates),
8318d78a
JB
123};
124
4e416a6f 125int p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
eff1a59c
MW
126{
127 struct p54_common *priv = dev->priv;
128 struct bootrec_exp_if *exp_if;
129 struct bootrec *bootrec;
130 u32 *data = (u32 *)fw->data;
131 u32 *end_data = (u32 *)fw->data + (fw->size >> 2);
132 u8 *fw_version = NULL;
133 size_t len;
134 int i;
135
136 if (priv->rx_start)
4e416a6f 137 return 0;
eff1a59c
MW
138
139 while (data < end_data && *data)
140 data++;
141
142 while (data < end_data && !*data)
143 data++;
144
145 bootrec = (struct bootrec *) data;
146
147 while (bootrec->data <= end_data &&
148 (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) {
149 u32 code = le32_to_cpu(bootrec->code);
150 switch (code) {
151 case BR_CODE_COMPONENT_ID:
1f1c0e33
LF
152 priv->fw_interface = be32_to_cpup((__be32 *)
153 bootrec->data);
2b80848e 154 switch (priv->fw_interface) {
eff1a59c
MW
155 case FW_FMAC:
156 printk(KERN_INFO "p54: FreeMAC firmware\n");
157 break;
158 case FW_LM20:
159 printk(KERN_INFO "p54: LM20 firmware\n");
160 break;
161 case FW_LM86:
162 printk(KERN_INFO "p54: LM86 firmware\n");
163 break;
164 case FW_LM87:
2b80848e 165 printk(KERN_INFO "p54: LM87 firmware\n");
eff1a59c
MW
166 break;
167 default:
168 printk(KERN_INFO "p54: unknown firmware\n");
169 break;
170 }
171 break;
172 case BR_CODE_COMPONENT_VERSION:
173 /* 24 bytes should be enough for all firmwares */
174 if (strnlen((unsigned char*)bootrec->data, 24) < 24)
175 fw_version = (unsigned char*)bootrec->data;
176 break;
4e416a6f
CL
177 case BR_CODE_DESCR: {
178 struct bootrec_desc *desc =
179 (struct bootrec_desc *)bootrec->data;
180 priv->rx_start = le32_to_cpu(desc->rx_start);
eff1a59c 181 /* FIXME add sanity checking */
4e416a6f
CL
182 priv->rx_end = le32_to_cpu(desc->rx_end) - 0x3500;
183 priv->headroom = desc->headroom;
184 priv->tailroom = desc->tailroom;
1f1c0e33
LF
185 if (le32_to_cpu(bootrec->len) == 11)
186 priv->rx_mtu = le16_to_cpu(bootrec->rx_mtu);
4e416a6f
CL
187 else
188 priv->rx_mtu = (size_t)
189 0x620 - priv->tx_hdr_len;
eff1a59c 190 break;
4e416a6f 191 }
eff1a59c
MW
192 case BR_CODE_EXPOSED_IF:
193 exp_if = (struct bootrec_exp_if *) bootrec->data;
194 for (i = 0; i < (len * sizeof(*exp_if) / 4); i++)
dc73c623 195 if (exp_if[i].if_id == cpu_to_le16(0x1a))
eff1a59c
MW
196 priv->fw_var = le16_to_cpu(exp_if[i].variant);
197 break;
198 case BR_CODE_DEPENDENT_IF:
199 break;
200 case BR_CODE_END_OF_BRA:
201 case LEGACY_BR_CODE_END_OF_BRA:
202 end_data = NULL;
203 break;
204 default:
205 break;
206 }
207 bootrec = (struct bootrec *)&bootrec->data[len];
208 }
209
210 if (fw_version)
211 printk(KERN_INFO "p54: FW rev %s - Softmac protocol %x.%x\n",
212 fw_version, priv->fw_var >> 8, priv->fw_var & 0xff);
213
214 if (priv->fw_var >= 0x300) {
215 /* Firmware supports QoS, use it! */
84df3ed3
C
216 priv->tx_stats[4].limit = 3;
217 priv->tx_stats[5].limit = 4;
218 priv->tx_stats[6].limit = 3;
219 priv->tx_stats[7].limit = 1;
eff1a59c
MW
220 dev->queues = 4;
221 }
4e416a6f
CL
222
223 return 0;
eff1a59c
MW
224}
225EXPORT_SYMBOL_GPL(p54_parse_firmware);
226
154e3af1
CL
227static int p54_convert_rev0(struct ieee80211_hw *dev,
228 struct pda_pa_curve_data *curve_data)
eff1a59c
MW
229{
230 struct p54_common *priv = dev->priv;
154e3af1
CL
231 struct p54_pa_curve_data_sample *dst;
232 struct pda_pa_curve_data_sample_rev0 *src;
eff1a59c 233 size_t cd_len = sizeof(*curve_data) +
154e3af1 234 (curve_data->points_per_channel*sizeof(*dst) + 2) *
eff1a59c
MW
235 curve_data->channels;
236 unsigned int i, j;
237 void *source, *target;
238
239 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
240 if (!priv->curve_data)
241 return -ENOMEM;
242
243 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
244 source = curve_data->data;
245 target = priv->curve_data->data;
246 for (i = 0; i < curve_data->channels; i++) {
247 __le16 *freq = source;
248 source += sizeof(__le16);
249 *((__le16 *)target) = *freq;
250 target += sizeof(__le16);
251 for (j = 0; j < curve_data->points_per_channel; j++) {
154e3af1
CL
252 dst = target;
253 src = source;
eff1a59c 254
154e3af1
CL
255 dst->rf_power = src->rf_power;
256 dst->pa_detector = src->pa_detector;
257 dst->data_64qam = src->pcv;
eff1a59c
MW
258 /* "invent" the points for the other modulations */
259#define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y)
154e3af1
CL
260 dst->data_16qam = SUB(src->pcv, 12);
261 dst->data_qpsk = SUB(dst->data_16qam, 12);
262 dst->data_bpsk = SUB(dst->data_qpsk, 12);
263 dst->data_barker = SUB(dst->data_bpsk, 14);
eff1a59c 264#undef SUB
154e3af1
CL
265 target += sizeof(*dst);
266 source += sizeof(*src);
eff1a59c
MW
267 }
268 }
269
270 return 0;
271}
272
154e3af1
CL
273static int p54_convert_rev1(struct ieee80211_hw *dev,
274 struct pda_pa_curve_data *curve_data)
275{
276 struct p54_common *priv = dev->priv;
277 struct p54_pa_curve_data_sample *dst;
278 struct pda_pa_curve_data_sample_rev1 *src;
279 size_t cd_len = sizeof(*curve_data) +
280 (curve_data->points_per_channel*sizeof(*dst) + 2) *
281 curve_data->channels;
282 unsigned int i, j;
283 void *source, *target;
284
285 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
286 if (!priv->curve_data)
287 return -ENOMEM;
288
289 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
290 source = curve_data->data;
291 target = priv->curve_data->data;
292 for (i = 0; i < curve_data->channels; i++) {
293 __le16 *freq = source;
294 source += sizeof(__le16);
295 *((__le16 *)target) = *freq;
296 target += sizeof(__le16);
297 for (j = 0; j < curve_data->points_per_channel; j++) {
298 memcpy(target, source, sizeof(*src));
299
300 target += sizeof(*dst);
301 source += sizeof(*src);
302 }
303 source++;
304 }
305
306 return 0;
307}
308
1f1c0e33 309static const char *p54_rf_chips[] = { "NULL", "Indigo?", "Duette",
7cb77072 310 "Frisbee", "Xbow", "Longbow" };
1b997534 311static int p54_init_xbow_synth(struct ieee80211_hw *dev);
7cb77072 312
1f1c0e33 313static int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
eff1a59c
MW
314{
315 struct p54_common *priv = dev->priv;
316 struct eeprom_pda_wrap *wrap = NULL;
317 struct pda_entry *entry;
eff1a59c
MW
318 unsigned int data_len, entry_len;
319 void *tmp;
320 int err;
c2f2d3a0 321 u8 *end = (u8 *)eeprom + len;
7cb77072 322 DECLARE_MAC_BUF(mac);
eff1a59c
MW
323
324 wrap = (struct eeprom_pda_wrap *) eeprom;
8c28293f 325 entry = (void *)wrap->data + le16_to_cpu(wrap->len);
c2f2d3a0
JB
326
327 /* verify that at least the entry length/code fits */
328 while ((u8 *)entry <= end - sizeof(*entry)) {
eff1a59c
MW
329 entry_len = le16_to_cpu(entry->len);
330 data_len = ((entry_len - 1) << 1);
c2f2d3a0
JB
331
332 /* abort if entry exceeds whole structure */
333 if ((u8 *)entry + sizeof(*entry) + data_len > end)
334 break;
335
eff1a59c
MW
336 switch (le16_to_cpu(entry->code)) {
337 case PDR_MAC_ADDRESS:
338 SET_IEEE80211_PERM_ADDR(dev, entry->data);
339 break;
340 case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS:
341 if (data_len < 2) {
342 err = -EINVAL;
343 goto err;
344 }
345
346 if (2 + entry->data[1]*sizeof(*priv->output_limit) > data_len) {
347 err = -EINVAL;
348 goto err;
349 }
350
351 priv->output_limit = kmalloc(entry->data[1] *
352 sizeof(*priv->output_limit), GFP_KERNEL);
353
354 if (!priv->output_limit) {
355 err = -ENOMEM;
356 goto err;
357 }
358
359 memcpy(priv->output_limit, &entry->data[2],
360 entry->data[1]*sizeof(*priv->output_limit));
361 priv->output_limit_len = entry->data[1];
362 break;
154e3af1
CL
363 case PDR_PRISM_PA_CAL_CURVE_DATA: {
364 struct pda_pa_curve_data *curve_data =
365 (struct pda_pa_curve_data *)entry->data;
366 if (data_len < sizeof(*curve_data)) {
eff1a59c
MW
367 err = -EINVAL;
368 goto err;
369 }
370
154e3af1
CL
371 switch (curve_data->cal_method_rev) {
372 case 0:
373 err = p54_convert_rev0(dev, curve_data);
374 break;
375 case 1:
376 err = p54_convert_rev1(dev, curve_data);
377 break;
378 default:
379 printk(KERN_ERR "p54: unknown curve data "
380 "revision %d\n",
381 curve_data->cal_method_rev);
382 err = -ENODEV;
383 break;
eff1a59c 384 }
154e3af1
CL
385 if (err)
386 goto err;
eff1a59c 387
154e3af1 388 }
eff1a59c
MW
389 case PDR_PRISM_ZIF_TX_IQ_CALIBRATION:
390 priv->iq_autocal = kmalloc(data_len, GFP_KERNEL);
391 if (!priv->iq_autocal) {
392 err = -ENOMEM;
393 goto err;
394 }
395
396 memcpy(priv->iq_autocal, entry->data, data_len);
397 priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry);
398 break;
399 case PDR_INTERFACE_LIST:
400 tmp = entry->data;
401 while ((u8 *)tmp < entry->data + data_len) {
402 struct bootrec_exp_if *exp_if = tmp;
403 if (le16_to_cpu(exp_if->if_id) == 0xF)
7cb77072 404 priv->rxhw = le16_to_cpu(exp_if->variant) & 0x07;
eff1a59c
MW
405 tmp += sizeof(struct bootrec_exp_if);
406 }
407 break;
408 case PDR_HARDWARE_PLATFORM_COMPONENT_ID:
409 priv->version = *(u8 *)(entry->data + 1);
410 break;
411 case PDR_END:
c2f2d3a0
JB
412 /* make it overrun */
413 entry_len = len;
eff1a59c 414 break;
58e30739
FF
415 default:
416 printk(KERN_INFO "p54: unknown eeprom code : 0x%x\n",
417 le16_to_cpu(entry->code));
418 break;
eff1a59c
MW
419 }
420
421 entry = (void *)entry + (entry_len + 1)*2;
eff1a59c
MW
422 }
423
424 if (!priv->iq_autocal || !priv->output_limit || !priv->curve_data) {
425 printk(KERN_ERR "p54: not all required entries found in eeprom!\n");
426 err = -EINVAL;
427 goto err;
428 }
429
7cb77072 430 switch (priv->rxhw) {
1b997534
CL
431 case 4: /* XBow */
432 p54_init_xbow_synth(dev);
433 case 1: /* Indigo? */
434 case 2: /* Duette */
435 dev->wiphy->bands[IEEE80211_BAND_5GHZ] = &band_5GHz;
436 case 3: /* Frisbee */
437 case 5: /* Longbow */
438 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band_2GHz;
439 break;
440 default:
441 printk(KERN_ERR "%s: unsupported RF-Chip\n",
442 wiphy_name(dev->wiphy));
443 err = -EINVAL;
444 goto err;
7cb77072
CL
445 }
446
447 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
448 u8 perm_addr[ETH_ALEN];
449
450 printk(KERN_WARNING "%s: Invalid hwaddr! Using randomly generated MAC addr\n",
451 wiphy_name(dev->wiphy));
452 random_ether_addr(perm_addr);
453 SET_IEEE80211_PERM_ADDR(dev, perm_addr);
454 }
455
456 printk(KERN_INFO "%s: hwaddr %s, MAC:isl38%02x RF:%s\n",
457 wiphy_name(dev->wiphy),
458 print_mac(mac, dev->wiphy->perm_addr),
459 priv->version, p54_rf_chips[priv->rxhw]);
460
eff1a59c
MW
461 return 0;
462
463 err:
464 if (priv->iq_autocal) {
465 kfree(priv->iq_autocal);
466 priv->iq_autocal = NULL;
467 }
468
469 if (priv->output_limit) {
470 kfree(priv->output_limit);
471 priv->output_limit = NULL;
472 }
473
474 if (priv->curve_data) {
475 kfree(priv->curve_data);
476 priv->curve_data = NULL;
477 }
478
479 printk(KERN_ERR "p54: eeprom parse failed!\n");
480 return err;
481}
eff1a59c 482
cc6de669
CL
483static int p54_rssi_to_dbm(struct ieee80211_hw *dev, int rssi)
484{
485 /* TODO: get the rssi_add & rssi_mul data from the eeprom */
486 return ((rssi * 0x83) / 64 - 400) / 4;
487}
488
19c19d54 489static int p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 490{
a0db663f 491 struct p54_common *priv = dev->priv;
eff1a59c
MW
492 struct p54_rx_hdr *hdr = (struct p54_rx_hdr *) skb->data;
493 struct ieee80211_rx_status rx_status = {0};
494 u16 freq = le16_to_cpu(hdr->freq);
19c19d54 495 size_t header_len = sizeof(*hdr);
a0db663f 496 u32 tsf32;
eff1a59c 497
78d57eb2
CL
498 if (!(hdr->magic & cpu_to_le16(0x0001))) {
499 if (priv->filter_flags & FIF_FCSFAIL)
500 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
501 else
502 return 0;
503 }
504
cc6de669
CL
505 rx_status.signal = p54_rssi_to_dbm(dev, hdr->rssi);
506 rx_status.noise = priv->noise;
8318d78a 507 /* XX correct? */
18d72605 508 rx_status.qual = (100 * hdr->rssi) / 127;
cf3e74c2
CL
509 rx_status.rate_idx = (dev->conf.channel->band == IEEE80211_BAND_2GHZ ?
510 hdr->rate : (hdr->rate - 4)) & 0xf;
eff1a59c 511 rx_status.freq = freq;
cf3e74c2 512 rx_status.band = dev->conf.channel->band;
eff1a59c 513 rx_status.antenna = hdr->antenna;
a0db663f
CL
514
515 tsf32 = le32_to_cpu(hdr->tsf32);
516 if (tsf32 < priv->tsf_low32)
517 priv->tsf_high32++;
518 rx_status.mactime = ((u64)priv->tsf_high32) << 32 | tsf32;
519 priv->tsf_low32 = tsf32;
520
03bffc13 521 rx_status.flag |= RX_FLAG_TSFT;
eff1a59c 522
19c19d54
CL
523 if (hdr->magic & cpu_to_le16(0x4000))
524 header_len += hdr->align[0];
525
526 skb_pull(skb, header_len);
eff1a59c
MW
527 skb_trim(skb, le16_to_cpu(hdr->len));
528
529 ieee80211_rx_irqsafe(dev, skb, &rx_status);
19c19d54
CL
530
531 return -1;
eff1a59c
MW
532}
533
534static void inline p54_wake_free_queues(struct ieee80211_hw *dev)
535{
536 struct p54_common *priv = dev->priv;
537 int i;
538
eff1a59c 539 for (i = 0; i < dev->queues; i++)
84df3ed3 540 if (priv->tx_stats[i + 4].len < priv->tx_stats[i + 4].limit)
eff1a59c
MW
541 ieee80211_wake_queue(dev, i);
542}
543
544static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
545{
546 struct p54_common *priv = dev->priv;
547 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
548 struct p54_frame_sent_hdr *payload = (struct p54_frame_sent_hdr *) hdr->data;
549 struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next;
4e416a6f 550 u32 addr = le32_to_cpu(hdr->req_id) - priv->headroom;
eff1a59c
MW
551 struct memrecord *range = NULL;
552 u32 freed = 0;
553 u32 last_addr = priv->rx_start;
031d10ee 554 unsigned long flags;
eff1a59c 555
031d10ee 556 spin_lock_irqsave(&priv->tx_queue.lock, flags);
eff1a59c 557 while (entry != (struct sk_buff *)&priv->tx_queue) {
552fe53f
JB
558 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
559 range = (void *)info->driver_data;
eff1a59c 560 if (range->start_addr == addr) {
eff1a59c
MW
561 struct p54_control_hdr *entry_hdr;
562 struct p54_tx_control_allocdata *entry_data;
563 int pad = 0;
564
552fe53f
JB
565 if (entry->next != (struct sk_buff *)&priv->tx_queue) {
566 struct ieee80211_tx_info *ni;
567 struct memrecord *mr;
568
569 ni = IEEE80211_SKB_CB(entry->next);
570 mr = (struct memrecord *)ni->driver_data;
571 freed = mr->start_addr - last_addr;
572 } else
eff1a59c
MW
573 freed = priv->rx_end - last_addr;
574
575 last_addr = range->end_addr;
576 __skb_unlink(entry, &priv->tx_queue);
031d10ee
C
577 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
578
e039fa4a 579 memset(&info->status, 0, sizeof(info->status));
eff1a59c
MW
580 entry_hdr = (struct p54_control_hdr *) entry->data;
581 entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data;
582 if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0)
583 pad = entry_data->align[0];
584
84df3ed3 585 priv->tx_stats[entry_data->hw_queue].len--;
e039fa4a 586 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
eff1a59c 587 if (!(payload->status & 0x01))
e039fa4a 588 info->flags |= IEEE80211_TX_STAT_ACK;
eff1a59c 589 else
e039fa4a 590 info->status.excessive_retries = 1;
eff1a59c 591 }
e039fa4a 592 info->status.retry_count = payload->retries - 1;
cc6de669
CL
593 info->status.ack_signal = p54_rssi_to_dbm(dev,
594 le16_to_cpu(payload->ack_rssi));
eff1a59c 595 skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data));
e039fa4a 596 ieee80211_tx_status_irqsafe(dev, entry);
031d10ee 597 goto out;
eff1a59c
MW
598 } else
599 last_addr = range->end_addr;
600 entry = entry->next;
601 }
031d10ee 602 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
eff1a59c 603
031d10ee 604out:
eff1a59c
MW
605 if (freed >= IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
606 sizeof(struct p54_control_hdr))
607 p54_wake_free_queues(dev);
608}
609
7cb77072
CL
610static void p54_rx_eeprom_readback(struct ieee80211_hw *dev,
611 struct sk_buff *skb)
612{
613 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
614 struct p54_eeprom_lm86 *eeprom = (struct p54_eeprom_lm86 *) hdr->data;
615 struct p54_common *priv = dev->priv;
616
617 if (!priv->eeprom)
618 return ;
619
1f1c0e33 620 memcpy(priv->eeprom, eeprom->data, le16_to_cpu(eeprom->len));
7cb77072
CL
621
622 complete(&priv->eeprom_comp);
623}
624
cc6de669
CL
625static void p54_rx_stats(struct ieee80211_hw *dev, struct sk_buff *skb)
626{
627 struct p54_common *priv = dev->priv;
628 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
629 struct p54_statistics *stats = (struct p54_statistics *) hdr->data;
630 u32 tsf32 = le32_to_cpu(stats->tsf32);
631
632 if (tsf32 < priv->tsf_low32)
633 priv->tsf_high32++;
634 priv->tsf_low32 = tsf32;
635
636 priv->stats.dot11RTSFailureCount = le32_to_cpu(stats->rts_fail);
637 priv->stats.dot11RTSSuccessCount = le32_to_cpu(stats->rts_success);
638 priv->stats.dot11FCSErrorCount = le32_to_cpu(stats->rx_bad_fcs);
639
640 priv->noise = p54_rssi_to_dbm(dev, le32_to_cpu(stats->noise));
641 complete(&priv->stats_comp);
642
643 mod_timer(&priv->stats_timer, jiffies + 5 * HZ);
644}
645
19c19d54 646static int p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c
MW
647{
648 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
649
650 switch (le16_to_cpu(hdr->type)) {
651 case P54_CONTROL_TYPE_TXDONE:
652 p54_rx_frame_sent(dev, skb);
653 break;
654 case P54_CONTROL_TYPE_BBP:
655 break;
cc6de669
CL
656 case P54_CONTROL_TYPE_STAT_READBACK:
657 p54_rx_stats(dev, skb);
658 break;
7cb77072
CL
659 case P54_CONTROL_TYPE_EEPROM_READBACK:
660 p54_rx_eeprom_readback(dev, skb);
661 break;
eff1a59c
MW
662 default:
663 printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n",
664 wiphy_name(dev->wiphy), le16_to_cpu(hdr->type));
665 break;
666 }
19c19d54
CL
667
668 return 0;
eff1a59c
MW
669}
670
671/* returns zero if skb can be reused */
672int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb)
673{
674 u8 type = le16_to_cpu(*((__le16 *)skb->data)) >> 8;
19c19d54
CL
675
676 if (type == 0x80)
677 return p54_rx_control(dev, skb);
678 else
679 return p54_rx_data(dev, skb);
eff1a59c
MW
680}
681EXPORT_SYMBOL_GPL(p54_rx);
682
683/*
684 * So, the firmware is somewhat stupid and doesn't know what places in its
685 * memory incoming data should go to. By poking around in the firmware, we
686 * can find some unused memory to upload our packets to. However, data that we
687 * want the card to TX needs to stay intact until the card has told us that
688 * it is done with it. This function finds empty places we can upload to and
689 * marks allocated areas as reserved if necessary. p54_rx_frame_sent frees
690 * allocated areas.
691 */
692static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
e039fa4a 693 struct p54_control_hdr *data, u32 len)
eff1a59c
MW
694{
695 struct p54_common *priv = dev->priv;
696 struct sk_buff *entry = priv->tx_queue.next;
697 struct sk_buff *target_skb = NULL;
eff1a59c
MW
698 u32 last_addr = priv->rx_start;
699 u32 largest_hole = 0;
700 u32 target_addr = priv->rx_start;
701 unsigned long flags;
702 unsigned int left;
4e416a6f 703 len = (len + priv->headroom + priv->tailroom + 3) & ~0x3;
eff1a59c
MW
704
705 spin_lock_irqsave(&priv->tx_queue.lock, flags);
706 left = skb_queue_len(&priv->tx_queue);
707 while (left--) {
708 u32 hole_size;
e039fa4a
JB
709 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
710 struct memrecord *range = (void *)info->driver_data;
eff1a59c
MW
711 hole_size = range->start_addr - last_addr;
712 if (!target_skb && hole_size >= len) {
713 target_skb = entry->prev;
714 hole_size -= len;
715 target_addr = last_addr;
716 }
717 largest_hole = max(largest_hole, hole_size);
718 last_addr = range->end_addr;
719 entry = entry->next;
720 }
721 if (!target_skb && priv->rx_end - last_addr >= len) {
722 target_skb = priv->tx_queue.prev;
723 largest_hole = max(largest_hole, priv->rx_end - last_addr - len);
724 if (!skb_queue_empty(&priv->tx_queue)) {
e039fa4a
JB
725 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(target_skb);
726 struct memrecord *range = (void *)info->driver_data;
eff1a59c
MW
727 target_addr = range->end_addr;
728 }
729 } else
730 largest_hole = max(largest_hole, priv->rx_end - last_addr);
731
732 if (skb) {
e039fa4a
JB
733 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
734 struct memrecord *range = (void *)info->driver_data;
eff1a59c
MW
735 range->start_addr = target_addr;
736 range->end_addr = target_addr + len;
eff1a59c 737 __skb_queue_after(&priv->tx_queue, target_skb, skb);
4e416a6f
CL
738 if (largest_hole < priv->rx_mtu + priv->headroom +
739 priv->tailroom +
eff1a59c
MW
740 sizeof(struct p54_control_hdr))
741 ieee80211_stop_queues(dev);
742 }
743 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
744
4e416a6f 745 data->req_id = cpu_to_le32(target_addr + priv->headroom);
eff1a59c
MW
746}
747
7cb77072
CL
748int p54_read_eeprom(struct ieee80211_hw *dev)
749{
750 struct p54_common *priv = dev->priv;
751 struct p54_control_hdr *hdr = NULL;
752 struct p54_eeprom_lm86 *eeprom_hdr;
753 size_t eeprom_size = 0x2020, offset = 0, blocksize;
754 int ret = -ENOMEM;
755 void *eeprom = NULL;
756
757 hdr = (struct p54_control_hdr *)kzalloc(sizeof(*hdr) +
758 sizeof(*eeprom_hdr) + EEPROM_READBACK_LEN, GFP_KERNEL);
759 if (!hdr)
760 goto free;
761
762 priv->eeprom = kzalloc(EEPROM_READBACK_LEN, GFP_KERNEL);
763 if (!priv->eeprom)
764 goto free;
765
766 eeprom = kzalloc(eeprom_size, GFP_KERNEL);
767 if (!eeprom)
768 goto free;
769
770 hdr->magic1 = cpu_to_le16(0x8000);
771 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_EEPROM_READBACK);
772 hdr->retry1 = hdr->retry2 = 0;
773 eeprom_hdr = (struct p54_eeprom_lm86 *) hdr->data;
774
775 while (eeprom_size) {
776 blocksize = min(eeprom_size, (size_t)EEPROM_READBACK_LEN);
777 hdr->len = cpu_to_le16(blocksize + sizeof(*eeprom_hdr));
778 eeprom_hdr->offset = cpu_to_le16(offset);
779 eeprom_hdr->len = cpu_to_le16(blocksize);
1f1c0e33
LF
780 p54_assign_address(dev, NULL, hdr, le16_to_cpu(hdr->len) +
781 sizeof(*hdr));
782 priv->tx(dev, hdr, le16_to_cpu(hdr->len) + sizeof(*hdr), 0);
7cb77072
CL
783
784 if (!wait_for_completion_interruptible_timeout(&priv->eeprom_comp, HZ)) {
785 printk(KERN_ERR "%s: device does not respond!\n",
786 wiphy_name(dev->wiphy));
787 ret = -EBUSY;
788 goto free;
789 }
790
791 memcpy(eeprom + offset, priv->eeprom, blocksize);
792 offset += blocksize;
793 eeprom_size -= blocksize;
794 }
795
796 ret = p54_parse_eeprom(dev, eeprom, offset);
797free:
798 kfree(priv->eeprom);
799 priv->eeprom = NULL;
800 kfree(hdr);
801 kfree(eeprom);
802
803 return ret;
804}
805EXPORT_SYMBOL_GPL(p54_read_eeprom);
806
e039fa4a 807static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 808{
e039fa4a 809 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
57ffc589 810 struct ieee80211_tx_queue_stats *current_queue;
eff1a59c
MW
811 struct p54_common *priv = dev->priv;
812 struct p54_control_hdr *hdr;
eda0c003 813 struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr *)skb->data;
eff1a59c 814 struct p54_tx_control_allocdata *txhdr;
eff1a59c
MW
815 size_t padding, len;
816 u8 rate;
aaa15535 817 u8 cts_rate = 0x20;
eff1a59c 818
84df3ed3 819 current_queue = &priv->tx_stats[skb_get_queue_mapping(skb) + 4];
eff1a59c
MW
820 if (unlikely(current_queue->len > current_queue->limit))
821 return NETDEV_TX_BUSY;
822 current_queue->len++;
823 current_queue->count++;
824 if (current_queue->len == current_queue->limit)
e2530083 825 ieee80211_stop_queue(dev, skb_get_queue_mapping(skb));
eff1a59c
MW
826
827 padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3;
828 len = skb->len;
829
eff1a59c
MW
830 txhdr = (struct p54_tx_control_allocdata *)
831 skb_push(skb, sizeof(*txhdr) + padding);
832 hdr = (struct p54_control_hdr *) skb_push(skb, sizeof(*hdr));
833
834 if (padding)
835 hdr->magic1 = cpu_to_le16(0x4010);
836 else
837 hdr->magic1 = cpu_to_le16(0x0010);
838 hdr->len = cpu_to_le16(len);
e039fa4a
JB
839 hdr->type = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? 0 : cpu_to_le16(1);
840 hdr->retry1 = hdr->retry2 = info->control.retry_limit;
eff1a59c 841
eff1a59c 842 /* TODO: add support for alternate retry TX rates */
e039fa4a 843 rate = ieee80211_get_tx_rate(dev, info)->hw_value;
aaa15535 844 if (info->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE) {
8318d78a 845 rate |= 0x10;
aaa15535
CL
846 cts_rate |= 0x10;
847 }
848 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
eff1a59c 849 rate |= 0x40;
aaa15535
CL
850 cts_rate |= ieee80211_get_rts_cts_rate(dev, info)->hw_value;
851 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
eff1a59c 852 rate |= 0x20;
aaa15535
CL
853 cts_rate |= ieee80211_get_rts_cts_rate(dev, info)->hw_value;
854 }
eff1a59c 855 memset(txhdr->rateset, rate, 8);
aaa15535
CL
856 txhdr->key_type = 0;
857 txhdr->key_len = 0;
858 txhdr->hw_queue = skb_get_queue_mapping(skb) + 4;
859 txhdr->tx_antenna = (info->antenna_sel_tx == 0) ?
e039fa4a 860 2 : info->antenna_sel_tx - 1;
09adf284 861 txhdr->output_power = priv->output_power;
aaa15535
CL
862 txhdr->cts_rate = (info->flags & IEEE80211_TX_CTL_NO_ACK) ?
863 0 : cts_rate;
eff1a59c
MW
864 if (padding)
865 txhdr->align[0] = padding;
866
eda0c003
LF
867 /* FIXME: The sequence that follows is needed for this driver to
868 * work with mac80211 since "mac80211: fix TX sequence numbers".
869 * As with the temporary code in rt2x00, changes will be needed
870 * to get proper sequence numbers on beacons. In addition, this
871 * patch places the sequence number in the hardware state, which
872 * limits us to a single virtual state.
873 */
874 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
875 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
876 priv->seqno += 0x10;
877 ieee80211hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
878 ieee80211hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
879 }
e039fa4a
JB
880 /* modifies skb->cb and with it info, so must be last! */
881 p54_assign_address(dev, skb, hdr, skb->len);
882
eff1a59c
MW
883 priv->tx(dev, hdr, skb->len, 0);
884 return 0;
885}
886
887static int p54_set_filter(struct ieee80211_hw *dev, u16 filter_type,
e0a58eac 888 const u8 *bssid)
eff1a59c
MW
889{
890 struct p54_common *priv = dev->priv;
891 struct p54_control_hdr *hdr;
892 struct p54_tx_control_filter *filter;
19c19d54 893 size_t data_len;
eff1a59c
MW
894
895 hdr = kzalloc(sizeof(*hdr) + sizeof(*filter) +
ba8007ce 896 priv->tx_hdr_len, GFP_ATOMIC);
eff1a59c
MW
897 if (!hdr)
898 return -ENOMEM;
899
900 hdr = (void *)hdr + priv->tx_hdr_len;
901
902 filter = (struct p54_tx_control_filter *) hdr->data;
903 hdr->magic1 = cpu_to_le16(0x8001);
eff1a59c
MW
904 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_FILTER_SET);
905
e0a58eac
CL
906 priv->filter_type = filter->filter_type = cpu_to_le16(filter_type);
907 memcpy(filter->mac_addr, priv->mac_addr, ETH_ALEN);
908 if (!bssid)
909 memset(filter->bssid, ~0, ETH_ALEN);
eff1a59c 910 else
e0a58eac
CL
911 memcpy(filter->bssid, bssid, ETH_ALEN);
912
913 filter->rx_antenna = priv->rx_antenna;
eff1a59c 914
19c19d54
CL
915 if (priv->fw_var < 0x500) {
916 data_len = P54_TX_CONTROL_FILTER_V1_LEN;
917 filter->v1.basic_rate_mask = cpu_to_le32(0x15F);
918 filter->v1.rx_addr = cpu_to_le32(priv->rx_end);
919 filter->v1.max_rx = cpu_to_le16(priv->rx_mtu);
920 filter->v1.rxhw = cpu_to_le16(priv->rxhw);
921 filter->v1.wakeup_timer = cpu_to_le16(500);
922 } else {
923 data_len = P54_TX_CONTROL_FILTER_V2_LEN;
924 filter->v2.rx_addr = cpu_to_le32(priv->rx_end);
925 filter->v2.max_rx = cpu_to_le16(priv->rx_mtu);
926 filter->v2.rxhw = cpu_to_le16(priv->rxhw);
927 filter->v2.timer = cpu_to_le16(1000);
928 }
929
930 hdr->len = cpu_to_le16(data_len);
931 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + data_len);
932 priv->tx(dev, hdr, sizeof(*hdr) + data_len, 1);
eff1a59c
MW
933 return 0;
934}
935
936static int p54_set_freq(struct ieee80211_hw *dev, __le16 freq)
937{
938 struct p54_common *priv = dev->priv;
939 struct p54_control_hdr *hdr;
940 struct p54_tx_control_channel *chan;
941 unsigned int i;
19c19d54 942 size_t data_len;
eff1a59c
MW
943 void *entry;
944
154e3af1 945 hdr = kzalloc(sizeof(*hdr) + sizeof(*chan) +
eff1a59c
MW
946 priv->tx_hdr_len, GFP_KERNEL);
947 if (!hdr)
948 return -ENOMEM;
949
950 hdr = (void *)hdr + priv->tx_hdr_len;
951
952 chan = (struct p54_tx_control_channel *) hdr->data;
953
954 hdr->magic1 = cpu_to_le16(0x8001);
19c19d54 955
eff1a59c 956 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_CHANNEL_CHANGE);
eff1a59c 957
154e3af1
CL
958 chan->flags = cpu_to_le16(0x1);
959 chan->dwell = cpu_to_le16(0x0);
eff1a59c
MW
960
961 for (i = 0; i < priv->iq_autocal_len; i++) {
962 if (priv->iq_autocal[i].freq != freq)
963 continue;
964
965 memcpy(&chan->iq_autocal, &priv->iq_autocal[i],
966 sizeof(*priv->iq_autocal));
967 break;
968 }
969 if (i == priv->iq_autocal_len)
970 goto err;
971
972 for (i = 0; i < priv->output_limit_len; i++) {
973 if (priv->output_limit[i].freq != freq)
974 continue;
975
976 chan->val_barker = 0x38;
154e3af1
CL
977 chan->val_bpsk = chan->dup_bpsk =
978 priv->output_limit[i].val_bpsk;
979 chan->val_qpsk = chan->dup_qpsk =
980 priv->output_limit[i].val_qpsk;
981 chan->val_16qam = chan->dup_16qam =
982 priv->output_limit[i].val_16qam;
983 chan->val_64qam = chan->dup_64qam =
984 priv->output_limit[i].val_64qam;
eff1a59c
MW
985 break;
986 }
987 if (i == priv->output_limit_len)
988 goto err;
989
eff1a59c
MW
990 entry = priv->curve_data->data;
991 for (i = 0; i < priv->curve_data->channels; i++) {
992 if (*((__le16 *)entry) != freq) {
993 entry += sizeof(__le16);
154e3af1
CL
994 entry += sizeof(struct p54_pa_curve_data_sample) *
995 priv->curve_data->points_per_channel;
eff1a59c
MW
996 continue;
997 }
998
999 entry += sizeof(__le16);
154e3af1
CL
1000 chan->pa_points_per_curve =
1001 min(priv->curve_data->points_per_channel, (u8) 8);
1002
eff1a59c
MW
1003 memcpy(chan->curve_data, entry, sizeof(*chan->curve_data) *
1004 chan->pa_points_per_curve);
1005 break;
1006 }
1007
19c19d54
CL
1008 if (priv->fw_var < 0x500) {
1009 data_len = P54_TX_CONTROL_CHANNEL_V1_LEN;
1010 chan->v1.rssical_mul = cpu_to_le16(130);
1011 chan->v1.rssical_add = cpu_to_le16(0xfe70);
1012 } else {
1013 data_len = P54_TX_CONTROL_CHANNEL_V2_LEN;
1014 chan->v2.rssical_mul = cpu_to_le16(130);
1015 chan->v2.rssical_add = cpu_to_le16(0xfe70);
1016 chan->v2.basic_rate_mask = cpu_to_le32(0x15f);
1017 }
eff1a59c 1018
19c19d54
CL
1019 hdr->len = cpu_to_le16(data_len);
1020 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + data_len);
1021 priv->tx(dev, hdr, sizeof(*hdr) + data_len, 1);
eff1a59c
MW
1022 return 0;
1023
1024 err:
1025 printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy));
1026 kfree(hdr);
1027 return -EINVAL;
1028}
1029
1030static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act)
1031{
1032 struct p54_common *priv = dev->priv;
1033 struct p54_control_hdr *hdr;
1034 struct p54_tx_control_led *led;
1035
1036 hdr = kzalloc(sizeof(*hdr) + sizeof(*led) +
1037 priv->tx_hdr_len, GFP_KERNEL);
1038 if (!hdr)
1039 return -ENOMEM;
1040
1041 hdr = (void *)hdr + priv->tx_hdr_len;
1042 hdr->magic1 = cpu_to_le16(0x8001);
1043 hdr->len = cpu_to_le16(sizeof(*led));
1044 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_LED);
e039fa4a 1045 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*led));
eff1a59c
MW
1046
1047 led = (struct p54_tx_control_led *) hdr->data;
1048 led->mode = cpu_to_le16(mode);
1049 led->led_permanent = cpu_to_le16(link);
1050 led->led_temporary = cpu_to_le16(act);
1051 led->duration = cpu_to_le16(1000);
1052
1053 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*led), 1);
1054
1055 return 0;
1056}
1057
3330d7be 1058#define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, _txop) \
eff1a59c
MW
1059do { \
1060 queue.aifs = cpu_to_le16(ai_fs); \
1061 queue.cwmin = cpu_to_le16(cw_min); \
1062 queue.cwmax = cpu_to_le16(cw_max); \
3330d7be 1063 queue.txop = cpu_to_le16(_txop); \
eff1a59c
MW
1064} while(0)
1065
1066static void p54_init_vdcf(struct ieee80211_hw *dev)
1067{
1068 struct p54_common *priv = dev->priv;
1069 struct p54_control_hdr *hdr;
1070 struct p54_tx_control_vdcf *vdcf;
1071
1072 /* all USB V1 adapters need a extra headroom */
1073 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
1074 hdr->magic1 = cpu_to_le16(0x8001);
1075 hdr->len = cpu_to_le16(sizeof(*vdcf));
1076 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_DCFINIT);
1077 hdr->req_id = cpu_to_le32(priv->rx_start);
1078
1079 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
1080
3330d7be
JB
1081 P54_SET_QUEUE(vdcf->queue[0], 0x0002, 0x0003, 0x0007, 47);
1082 P54_SET_QUEUE(vdcf->queue[1], 0x0002, 0x0007, 0x000f, 94);
5200e8cd 1083 P54_SET_QUEUE(vdcf->queue[2], 0x0003, 0x000f, 0x03ff, 0);
3330d7be 1084 P54_SET_QUEUE(vdcf->queue[3], 0x0007, 0x000f, 0x03ff, 0);
eff1a59c
MW
1085}
1086
1087static void p54_set_vdcf(struct ieee80211_hw *dev)
1088{
1089 struct p54_common *priv = dev->priv;
1090 struct p54_control_hdr *hdr;
1091 struct p54_tx_control_vdcf *vdcf;
1092
1093 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
1094
e039fa4a 1095 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*vdcf));
eff1a59c
MW
1096
1097 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
1098
1099 if (dev->conf.flags & IEEE80211_CONF_SHORT_SLOT_TIME) {
1100 vdcf->slottime = 9;
5423b2ed
CL
1101 vdcf->magic1 = 0x10;
1102 vdcf->magic2 = 0x00;
eff1a59c
MW
1103 } else {
1104 vdcf->slottime = 20;
1105 vdcf->magic1 = 0x0a;
1106 vdcf->magic2 = 0x06;
1107 }
1108
1109 /* (see prism54/isl_oid.h for further details) */
1110 vdcf->frameburst = cpu_to_le16(0);
1111
1112 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*vdcf), 0);
1113}
1114
4150c572
JB
1115static int p54_start(struct ieee80211_hw *dev)
1116{
1117 struct p54_common *priv = dev->priv;
1118 int err;
1119
69bbc7dc
CL
1120 if (!priv->cached_vdcf) {
1121 priv->cached_vdcf = kzalloc(sizeof(struct p54_tx_control_vdcf)+
1122 priv->tx_hdr_len + sizeof(struct p54_control_hdr),
1123 GFP_KERNEL);
1124
1125 if (!priv->cached_vdcf)
1126 return -ENOMEM;
1127 }
1128
cc6de669
CL
1129 if (!priv->cached_stats) {
1130 priv->cached_stats = kzalloc(sizeof(struct p54_statistics) +
1131 priv->tx_hdr_len + sizeof(struct p54_control_hdr),
1132 GFP_KERNEL);
1133
1134 if (!priv->cached_stats) {
1135 kfree(priv->cached_vdcf);
1136 priv->cached_vdcf = NULL;
1137 return -ENOMEM;
1138 }
1139 }
1140
4150c572
JB
1141 err = priv->open(dev);
1142 if (!err)
05c914fe 1143 priv->mode = NL80211_IFTYPE_MONITOR;
4150c572 1144
69bbc7dc
CL
1145 p54_init_vdcf(dev);
1146
cc6de669 1147 mod_timer(&priv->stats_timer, jiffies + HZ);
4150c572
JB
1148 return err;
1149}
1150
1151static void p54_stop(struct ieee80211_hw *dev)
1152{
1153 struct p54_common *priv = dev->priv;
1154 struct sk_buff *skb;
cc6de669
CL
1155
1156 del_timer(&priv->stats_timer);
e039fa4a 1157 while ((skb = skb_dequeue(&priv->tx_queue)))
4150c572 1158 kfree_skb(skb);
4150c572 1159 priv->stop(dev);
a0db663f 1160 priv->tsf_high32 = priv->tsf_low32 = 0;
05c914fe 1161 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
4150c572
JB
1162}
1163
eff1a59c
MW
1164static int p54_add_interface(struct ieee80211_hw *dev,
1165 struct ieee80211_if_init_conf *conf)
1166{
1167 struct p54_common *priv = dev->priv;
eff1a59c 1168
05c914fe 1169 if (priv->mode != NL80211_IFTYPE_MONITOR)
4150c572 1170 return -EOPNOTSUPP;
eff1a59c
MW
1171
1172 switch (conf->type) {
05c914fe 1173 case NL80211_IFTYPE_STATION:
eff1a59c
MW
1174 priv->mode = conf->type;
1175 break;
1176 default:
1177 return -EOPNOTSUPP;
1178 }
1179
4150c572 1180 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
eff1a59c 1181
e0a58eac 1182 p54_set_filter(dev, 0, NULL);
eff1a59c
MW
1183
1184 switch (conf->type) {
05c914fe 1185 case NL80211_IFTYPE_STATION:
e0a58eac 1186 p54_set_filter(dev, 1, NULL);
eff1a59c 1187 break;
4150c572
JB
1188 default:
1189 BUG(); /* impossible */
1190 break;
eff1a59c
MW
1191 }
1192
1193 p54_set_leds(dev, 1, 0, 0);
1194
1195 return 0;
1196}
1197
1198static void p54_remove_interface(struct ieee80211_hw *dev,
1199 struct ieee80211_if_init_conf *conf)
1200{
1201 struct p54_common *priv = dev->priv;
05c914fe 1202 priv->mode = NL80211_IFTYPE_MONITOR;
4150c572 1203 memset(priv->mac_addr, 0, ETH_ALEN);
e0a58eac 1204 p54_set_filter(dev, 0, NULL);
eff1a59c
MW
1205}
1206
1207static int p54_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
1208{
1209 int ret;
6041e2a0 1210 struct p54_common *priv = dev->priv;
eff1a59c 1211
6041e2a0 1212 mutex_lock(&priv->conf_mutex);
e0a58eac
CL
1213 priv->rx_antenna = (conf->antenna_sel_rx == 0) ?
1214 2 : conf->antenna_sel_tx - 1;
09adf284 1215 priv->output_power = conf->power_level << 2;
8318d78a 1216 ret = p54_set_freq(dev, cpu_to_le16(conf->channel->center_freq));
eff1a59c 1217 p54_set_vdcf(dev);
6041e2a0 1218 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW
1219 return ret;
1220}
1221
32bfd35d
JB
1222static int p54_config_interface(struct ieee80211_hw *dev,
1223 struct ieee80211_vif *vif,
eff1a59c
MW
1224 struct ieee80211_if_conf *conf)
1225{
1226 struct p54_common *priv = dev->priv;
1227
6041e2a0 1228 mutex_lock(&priv->conf_mutex);
e0a58eac 1229 p54_set_filter(dev, 0, conf->bssid);
eff1a59c 1230 p54_set_leds(dev, 1, !is_multicast_ether_addr(conf->bssid), 0);
4150c572 1231 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6041e2a0 1232 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW
1233 return 0;
1234}
1235
4150c572
JB
1236static void p54_configure_filter(struct ieee80211_hw *dev,
1237 unsigned int changed_flags,
1238 unsigned int *total_flags,
1239 int mc_count, struct dev_mc_list *mclist)
1240{
1241 struct p54_common *priv = dev->priv;
1242
78d57eb2
CL
1243 *total_flags &= FIF_BCN_PRBRESP_PROMISC |
1244 FIF_PROMISC_IN_BSS |
1245 FIF_FCSFAIL;
1246
1247 priv->filter_flags = *total_flags;
4150c572
JB
1248
1249 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1250 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1f1c0e33
LF
1251 p54_set_filter(dev, le16_to_cpu(priv->filter_type),
1252 NULL);
78d57eb2 1253 else
1f1c0e33
LF
1254 p54_set_filter(dev, le16_to_cpu(priv->filter_type),
1255 priv->bssid);
78d57eb2
CL
1256 }
1257
1258 if (changed_flags & FIF_PROMISC_IN_BSS) {
1259 if (*total_flags & FIF_PROMISC_IN_BSS)
1f1c0e33
LF
1260 p54_set_filter(dev, le16_to_cpu(priv->filter_type) |
1261 0x8, NULL);
4150c572 1262 else
1f1c0e33
LF
1263 p54_set_filter(dev, le16_to_cpu(priv->filter_type) &
1264 ~0x8, priv->bssid);
4150c572
JB
1265 }
1266}
1267
e100bb64 1268static int p54_conf_tx(struct ieee80211_hw *dev, u16 queue,
eff1a59c
MW
1269 const struct ieee80211_tx_queue_params *params)
1270{
1271 struct p54_common *priv = dev->priv;
1272 struct p54_tx_control_vdcf *vdcf;
1273
1274 vdcf = (struct p54_tx_control_vdcf *)(((struct p54_control_hdr *)
1275 ((void *)priv->cached_vdcf + priv->tx_hdr_len))->data);
1276
3df5ee60 1277 if ((params) && !(queue > 4)) {
eff1a59c 1278 P54_SET_QUEUE(vdcf->queue[queue], params->aifs,
3330d7be 1279 params->cw_min, params->cw_max, params->txop);
eff1a59c
MW
1280 } else
1281 return -EINVAL;
1282
1283 p54_set_vdcf(dev);
1284
1285 return 0;
1286}
1287
1b997534
CL
1288static int p54_init_xbow_synth(struct ieee80211_hw *dev)
1289{
1290 struct p54_common *priv = dev->priv;
1291 struct p54_control_hdr *hdr;
1292 struct p54_tx_control_xbow_synth *xbow;
1293
1294 hdr = kzalloc(sizeof(*hdr) + sizeof(*xbow) +
1295 priv->tx_hdr_len, GFP_KERNEL);
1296 if (!hdr)
1297 return -ENOMEM;
1298
1299 hdr = (void *)hdr + priv->tx_hdr_len;
1300 hdr->magic1 = cpu_to_le16(0x8001);
1301 hdr->len = cpu_to_le16(sizeof(*xbow));
1302 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_XBOW_SYNTH_CFG);
1303 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*xbow));
1304
1305 xbow = (struct p54_tx_control_xbow_synth *) hdr->data;
1306 xbow->magic1 = cpu_to_le16(0x1);
1307 xbow->magic2 = cpu_to_le16(0x2);
1308 xbow->freq = cpu_to_le16(5390);
1309
1310 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*xbow), 1);
1311
1312 return 0;
1313}
1314
cc6de669
CL
1315static void p54_statistics_timer(unsigned long data)
1316{
1317 struct ieee80211_hw *dev = (struct ieee80211_hw *) data;
1318 struct p54_common *priv = dev->priv;
1319 struct p54_control_hdr *hdr;
1320 struct p54_statistics *stats;
1321
1322 BUG_ON(!priv->cached_stats);
1323
1324 hdr = (void *)priv->cached_stats + priv->tx_hdr_len;
1325 hdr->magic1 = cpu_to_le16(0x8000);
1326 hdr->len = cpu_to_le16(sizeof(*stats));
1327 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_STAT_READBACK);
1328 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*stats));
1329
1330 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*stats), 0);
1331}
1332
eff1a59c
MW
1333static int p54_get_stats(struct ieee80211_hw *dev,
1334 struct ieee80211_low_level_stats *stats)
1335{
cc6de669
CL
1336 struct p54_common *priv = dev->priv;
1337
1338 del_timer(&priv->stats_timer);
1339 p54_statistics_timer((unsigned long)dev);
1340
1341 if (!wait_for_completion_interruptible_timeout(&priv->stats_comp, HZ)) {
1342 printk(KERN_ERR "%s: device does not respond!\n",
1343 wiphy_name(dev->wiphy));
1344 return -EBUSY;
1345 }
1346
1347 memcpy(stats, &priv->stats, sizeof(*stats));
1348
eff1a59c
MW
1349 return 0;
1350}
1351
1352static int p54_get_tx_stats(struct ieee80211_hw *dev,
1353 struct ieee80211_tx_queue_stats *stats)
1354{
1355 struct p54_common *priv = dev->priv;
eff1a59c 1356
84df3ed3 1357 memcpy(stats, &priv->tx_stats[4], sizeof(stats[0]) * dev->queues);
eff1a59c
MW
1358
1359 return 0;
1360}
1361
1362static const struct ieee80211_ops p54_ops = {
1363 .tx = p54_tx,
4150c572
JB
1364 .start = p54_start,
1365 .stop = p54_stop,
eff1a59c
MW
1366 .add_interface = p54_add_interface,
1367 .remove_interface = p54_remove_interface,
1368 .config = p54_config,
1369 .config_interface = p54_config_interface,
4150c572 1370 .configure_filter = p54_configure_filter,
eff1a59c
MW
1371 .conf_tx = p54_conf_tx,
1372 .get_stats = p54_get_stats,
1373 .get_tx_stats = p54_get_tx_stats
1374};
1375
1376struct ieee80211_hw *p54_init_common(size_t priv_data_len)
1377{
1378 struct ieee80211_hw *dev;
1379 struct p54_common *priv;
eff1a59c
MW
1380
1381 dev = ieee80211_alloc_hw(priv_data_len, &p54_ops);
1382 if (!dev)
1383 return NULL;
1384
1385 priv = dev->priv;
05c914fe 1386 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
eff1a59c 1387 skb_queue_head_init(&priv->tx_queue);
eff1a59c 1388 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | /* not sure */
566bfe5a 1389 IEEE80211_HW_RX_INCLUDES_FCS |
cc6de669
CL
1390 IEEE80211_HW_SIGNAL_DBM |
1391 IEEE80211_HW_NOISE_DBM;
f59ac048
LR
1392
1393 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1394
eff1a59c 1395 dev->channel_change_time = 1000; /* TODO: find actual value */
eff1a59c 1396
84df3ed3
C
1397 priv->tx_stats[0].limit = 1;
1398 priv->tx_stats[1].limit = 1;
1399 priv->tx_stats[2].limit = 1;
1400 priv->tx_stats[3].limit = 1;
1401 priv->tx_stats[4].limit = 5;
eff1a59c 1402 dev->queues = 1;
cc6de669 1403 priv->noise = -94;
eff1a59c
MW
1404 dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 +
1405 sizeof(struct p54_tx_control_allocdata);
1406
6041e2a0 1407 mutex_init(&priv->conf_mutex);
7cb77072 1408 init_completion(&priv->eeprom_comp);
cc6de669
CL
1409 init_completion(&priv->stats_comp);
1410 setup_timer(&priv->stats_timer, p54_statistics_timer,
1411 (unsigned long)dev);
eff1a59c 1412
eff1a59c
MW
1413 return dev;
1414}
1415EXPORT_SYMBOL_GPL(p54_init_common);
1416
1417void p54_free_common(struct ieee80211_hw *dev)
1418{
1419 struct p54_common *priv = dev->priv;
cc6de669 1420 kfree(priv->cached_stats);
eff1a59c
MW
1421 kfree(priv->iq_autocal);
1422 kfree(priv->output_limit);
1423 kfree(priv->curve_data);
1424 kfree(priv->cached_vdcf);
1425}
1426EXPORT_SYMBOL_GPL(p54_free_common);
1427
1428static int __init p54_init(void)
1429{
1430 return 0;
1431}
1432
1433static void __exit p54_exit(void)
1434{
1435}
1436
1437module_init(p54_init);
1438module_exit(p54_exit);