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drivers/net: Remove unnecessary returns from void function()s
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
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32#include <linux/init.h>
33#include <linux/pci.h>
5a0e3ad6 34#include <linux/slab.h>
b481de9c
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35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
d43c36dc 37#include <linux/sched.h>
b481de9c
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38#include <linux/skbuff.h>
39#include <linux/netdevice.h>
40#include <linux/wireless.h>
41#include <linux/firmware.h>
b481de9c
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42#include <linux/etherdevice.h>
43#include <linux/if_arp.h>
44
45#include <net/ieee80211_radiotap.h>
46#include <net/mac80211.h>
47
48#include <asm/div64.h>
49
a3139c59
SO
50#define DRV_NAME "iwl3945"
51
dbb6654c
WT
52#include "iwl-fh.h"
53#include "iwl-3945-fh.h"
600c0e11 54#include "iwl-commands.h"
17f841cd 55#include "iwl-sta.h"
b481de9c 56#include "iwl-3945.h"
5747d47f 57#include "iwl-core.h"
4a6547c7 58#include "iwl-helpers.h"
d20b3c65 59#include "iwl-dev.h"
81963d68 60#include "iwl-spectrum.h"
b481de9c 61
b481de9c
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62/*
63 * module name, copyright, version, etc.
b481de9c
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64 */
65
66#define DRV_DESCRIPTION \
67"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
68
d08853a3 69#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
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70#define VD "d"
71#else
72#define VD
73#endif
74
81963d68
RC
75/*
76 * add "s" to indicate spectrum measurement included.
77 * we add it here to be consistent with previous releases in which
78 * this was configurable.
79 */
80#define DRV_VERSION IWLWIFI_VERSION VD "s"
1f447808 81#define DRV_COPYRIGHT "Copyright(c) 2003-2010 Intel Corporation"
a7b75207 82#define DRV_AUTHOR "<ilw@linux.intel.com>"
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83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c
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87MODULE_LICENSE("GPL");
88
df878d8f
KA
89 /* module parameters */
90struct iwl_mod_params iwl3945_mod_params = {
9c74d9fb 91 .sw_crypto = 1,
af48d048 92 .restart_fw = 1,
df878d8f
KA
93 /* the rest are 0 by default */
94};
95
7e4bca5e
SO
96/**
97 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
98 * @priv: eeprom and antenna fields are used to determine antenna flags
99 *
100 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
101 * iwl3945_mod_params.antenna specifies the antenna diversity mode:
102 *
103 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
104 * IWL_ANTENNA_MAIN - Force MAIN antenna
105 * IWL_ANTENNA_AUX - Force AUX antenna
106 */
107__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
108{
109 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
110
111 switch (iwl3945_mod_params.antenna) {
112 case IWL_ANTENNA_DIVERSITY:
113 return 0;
114
115 case IWL_ANTENNA_MAIN:
116 if (eeprom->antenna_switch_type)
117 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
118 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
119
120 case IWL_ANTENNA_AUX:
121 if (eeprom->antenna_switch_type)
122 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
123 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
124 }
125
126 /* bad antenna selector value */
127 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
128 iwl3945_mod_params.antenna);
129
130 return 0; /* "diversity" is default if error */
131}
132
6e21f15c 133static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
b481de9c
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134 struct ieee80211_key_conf *keyconf,
135 u8 sta_id)
136{
137 unsigned long flags;
138 __le16 key_flags = 0;
6e21f15c
AK
139 int ret;
140
141 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
142 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
143
144 if (sta_id == priv->hw_params.bcast_sta_id)
145 key_flags |= STA_KEY_MULTICAST_MSK;
146
147 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
148 keyconf->hw_key_idx = keyconf->keyidx;
149 key_flags &= ~STA_KEY_FLG_INVALID;
b481de9c 150
b481de9c 151 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
152 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
153 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
154 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
b481de9c
ZY
155 keyconf->keylen);
156
c587de0b 157 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
b481de9c 158 keyconf->keylen);
6e21f15c 159
c587de0b 160 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
6e21f15c 161 == STA_KEY_FLG_NO_ENC)
c587de0b 162 priv->stations[sta_id].sta.key.key_offset =
6e21f15c
AK
163 iwl_get_free_ucode_key_index(priv);
164 /* else, we are overriding an existing key => no need to allocated room
165 * in uCode. */
166
c587de0b 167 WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
6e21f15c
AK
168 "no space for a new key");
169
c587de0b
TW
170 priv->stations[sta_id].sta.key.key_flags = key_flags;
171 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
172 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c 173
6e21f15c
AK
174 IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
175
c587de0b 176 ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
6e21f15c 177
b481de9c
ZY
178 spin_unlock_irqrestore(&priv->sta_lock, flags);
179
6e21f15c
AK
180 return ret;
181}
182
183static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
184 struct ieee80211_key_conf *keyconf,
185 u8 sta_id)
186{
187 return -EOPNOTSUPP;
188}
189
190static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
191 struct ieee80211_key_conf *keyconf,
192 u8 sta_id)
193{
194 return -EOPNOTSUPP;
b481de9c
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195}
196
4a8a4322 197static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
b481de9c
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198{
199 unsigned long flags;
200
201 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
202 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
203 memset(&priv->stations[sta_id].sta.key, 0,
4c897253 204 sizeof(struct iwl4965_keyinfo));
c587de0b
TW
205 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
206 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
207 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c
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208 spin_unlock_irqrestore(&priv->sta_lock, flags);
209
e1623446 210 IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
c587de0b 211 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, 0);
b481de9c
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212 return 0;
213}
214
fa11d525 215static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
6e21f15c
AK
216 struct ieee80211_key_conf *keyconf, u8 sta_id)
217{
218 int ret = 0;
219
220 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
221
222 switch (keyconf->alg) {
223 case ALG_CCMP:
224 ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
225 break;
226 case ALG_TKIP:
227 ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
228 break;
229 case ALG_WEP:
230 ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
231 break;
232 default:
1e680233 233 IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg);
6e21f15c
AK
234 ret = -EINVAL;
235 }
236
237 IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n",
238 keyconf->alg, keyconf->keylen, keyconf->keyidx,
239 sta_id, ret);
240
241 return ret;
242}
243
244static int iwl3945_remove_static_key(struct iwl_priv *priv)
245{
246 int ret = -EOPNOTSUPP;
247
248 return ret;
249}
250
251static int iwl3945_set_static_key(struct iwl_priv *priv,
252 struct ieee80211_key_conf *key)
253{
254 if (key->alg == ALG_WEP)
255 return -EOPNOTSUPP;
256
257 IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg);
258 return -EINVAL;
259}
260
4a8a4322 261static void iwl3945_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY
262{
263 struct list_head *element;
264
e1623446 265 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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266 priv->frames_count);
267
268 while (!list_empty(&priv->free_frames)) {
269 element = priv->free_frames.next;
270 list_del(element);
bb8c093b 271 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
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272 priv->frames_count--;
273 }
274
275 if (priv->frames_count) {
39aadf8c 276 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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277 priv->frames_count);
278 priv->frames_count = 0;
279 }
280}
281
4a8a4322 282static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
b481de9c 283{
bb8c093b 284 struct iwl3945_frame *frame;
b481de9c
ZY
285 struct list_head *element;
286 if (list_empty(&priv->free_frames)) {
287 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
288 if (!frame) {
15b1687c 289 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
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290 return NULL;
291 }
292
293 priv->frames_count++;
294 return frame;
295 }
296
297 element = priv->free_frames.next;
298 list_del(element);
bb8c093b 299 return list_entry(element, struct iwl3945_frame, list);
b481de9c
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300}
301
4a8a4322 302static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
b481de9c
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303{
304 memset(frame, 0, sizeof(*frame));
305 list_add(&frame->list, &priv->free_frames);
306}
307
4a8a4322 308unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
b481de9c 309 struct ieee80211_hdr *hdr,
73ec1cc2 310 int left)
b481de9c
ZY
311{
312
8ccde88a 313 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
314 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
315 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY
316 return 0;
317
318 if (priv->ibss_beacon->len > left)
319 return 0;
320
321 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
322
323 return priv->ibss_beacon->len;
324}
325
4a8a4322 326static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 327{
bb8c093b 328 struct iwl3945_frame *frame;
b481de9c
ZY
329 unsigned int frame_size;
330 int rc;
331 u8 rate;
332
bb8c093b 333 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY
334
335 if (!frame) {
15b1687c 336 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY
337 "command.\n");
338 return -ENOMEM;
339 }
340
8ccde88a 341 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 342
bb8c093b 343 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 344
518099a8 345 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
346 &frame->u.cmd[0]);
347
bb8c093b 348 iwl3945_free_frame(priv, frame);
b481de9c
ZY
349
350 return rc;
351}
352
4a8a4322 353static void iwl3945_unset_hw_params(struct iwl_priv *priv)
b481de9c 354{
ee525d13 355 if (priv->_3945.shared_virt)
f36d04ab
SG
356 dma_free_coherent(&priv->pci_dev->dev,
357 sizeof(struct iwl3945_shared),
ee525d13
JB
358 priv->_3945.shared_virt,
359 priv->_3945.shared_phys);
b481de9c
ZY
360}
361
4a8a4322 362static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
e039fa4a 363 struct ieee80211_tx_info *info,
c2acea8e 364 struct iwl_device_cmd *cmd,
b481de9c 365 struct sk_buff *skb_frag,
6e21f15c 366 int sta_id)
b481de9c 367{
9744c91f 368 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
c587de0b 369 struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
b481de9c
ZY
370
371 switch (keyinfo->alg) {
372 case ALG_CCMP:
9744c91f
AK
373 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
374 memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
e1623446 375 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
b481de9c
ZY
376 break;
377
378 case ALG_TKIP:
b481de9c
ZY
379 break;
380
381 case ALG_WEP:
9744c91f 382 tx_cmd->sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 383 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY
384
385 if (keyinfo->keylen == 13)
9744c91f 386 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
b481de9c 387
9744c91f 388 memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
b481de9c 389
e1623446 390 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
e039fa4a 391 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY
392 break;
393
b481de9c 394 default:
978785a3 395 IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
b481de9c
ZY
396 break;
397 }
398}
399
400/*
401 * handle build REPLY_TX command notification.
402 */
4a8a4322 403static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
c2acea8e 404 struct iwl_device_cmd *cmd,
e039fa4a 405 struct ieee80211_tx_info *info,
e52119c5 406 struct ieee80211_hdr *hdr, u8 std_id)
b481de9c 407{
9744c91f
AK
408 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
409 __le32 tx_flags = tx_cmd->tx_flags;
fd7c8a40 410 __le16 fc = hdr->frame_control;
b481de9c 411
9744c91f 412 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 413 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 414 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 415 if (ieee80211_is_mgmt(fc))
b481de9c 416 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 417 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY
418 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
419 tx_flags |= TX_CMD_FLG_TSF_MSK;
420 } else {
421 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
422 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
423 }
424
9744c91f 425 tx_cmd->sta_id = std_id;
8b7b1e05 426 if (ieee80211_has_morefrags(fc))
b481de9c
ZY
427 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
428
fd7c8a40
HH
429 if (ieee80211_is_data_qos(fc)) {
430 u8 *qc = ieee80211_get_qos_ctl(hdr);
9744c91f 431 tx_cmd->tid_tspec = qc[0] & 0xf;
b481de9c 432 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 433 } else {
b481de9c 434 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 435 }
b481de9c 436
37dc70fe 437 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
b481de9c
ZY
438
439 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
440 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
441
442 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH
443 if (ieee80211_is_mgmt(fc)) {
444 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
9744c91f 445 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 446 else
9744c91f 447 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 448 } else {
9744c91f 449 tx_cmd->timeout.pm_frame_timeout = 0;
ab53d8af 450 }
b481de9c 451
9744c91f
AK
452 tx_cmd->driver_txop = 0;
453 tx_cmd->tx_flags = tx_flags;
454 tx_cmd->next_frame_len = 0;
b481de9c
ZY
455}
456
b481de9c
ZY
457/*
458 * start REPLY_TX command process
459 */
4a8a4322 460static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
b481de9c
ZY
461{
462 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 463 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
9744c91f 464 struct iwl3945_tx_cmd *tx_cmd;
188cf6c7 465 struct iwl_tx_queue *txq = NULL;
d20b3c65 466 struct iwl_queue *q = NULL;
c2acea8e
JB
467 struct iwl_device_cmd *out_cmd;
468 struct iwl_cmd_meta *out_meta;
b481de9c
ZY
469 dma_addr_t phys_addr;
470 dma_addr_t txcmd_phys;
e52119c5 471 int txq_id = skb_get_queue_mapping(skb);
df833b1d 472 u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
54dbb525
TW
473 u8 id;
474 u8 unicast;
b481de9c 475 u8 sta_id;
54dbb525 476 u8 tid = 0;
b481de9c 477 u16 seq_number = 0;
fd7c8a40 478 __le16 fc;
b481de9c 479 u8 wait_write_ptr = 0;
54dbb525 480 u8 *qc = NULL;
b481de9c 481 unsigned long flags;
b481de9c
ZY
482
483 spin_lock_irqsave(&priv->lock, flags);
775a6e27 484 if (iwl_is_rfkill(priv)) {
e1623446 485 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
b481de9c
ZY
486 goto drop_unlock;
487 }
488
e039fa4a 489 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
15b1687c 490 IWL_ERR(priv, "ERROR: No TX rate available.\n");
b481de9c
ZY
491 goto drop_unlock;
492 }
493
494 unicast = !is_multicast_ether_addr(hdr->addr1);
495 id = 0;
496
fd7c8a40 497 fc = hdr->frame_control;
b481de9c 498
d08853a3 499#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c 500 if (ieee80211_is_auth(fc))
e1623446 501 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
fd7c8a40 502 else if (ieee80211_is_assoc_req(fc))
e1623446 503 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
fd7c8a40 504 else if (ieee80211_is_reassoc_req(fc))
e1623446 505 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
b481de9c
ZY
506#endif
507
b481de9c
ZY
508 spin_unlock_irqrestore(&priv->lock, flags);
509
7294ec95 510 hdr_len = ieee80211_hdrlen(fc);
6440adb5
BC
511
512 /* Find (or create) index into station table for destination station */
aa065263
GS
513 if (info->flags & IEEE80211_TX_CTL_INJECTED)
514 sta_id = priv->hw_params.bcast_sta_id;
515 else
516 sta_id = iwl_get_sta_id(priv, hdr);
b481de9c 517 if (sta_id == IWL_INVALID_STATION) {
e1623446 518 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
e174961c 519 hdr->addr1);
b481de9c
ZY
520 goto drop;
521 }
522
e1623446 523 IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
b481de9c 524
fd7c8a40
HH
525 if (ieee80211_is_data_qos(fc)) {
526 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 527 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
e6a6cf4c
RC
528 if (unlikely(tid >= MAX_TID_COUNT))
529 goto drop;
c587de0b 530 seq_number = priv->stations[sta_id].tid[tid].seq_number &
b481de9c
ZY
531 IEEE80211_SCTL_SEQ;
532 hdr->seq_ctrl = cpu_to_le16(seq_number) |
533 (hdr->seq_ctrl &
c1b4aa3f 534 cpu_to_le16(IEEE80211_SCTL_FRAG));
b481de9c
ZY
535 seq_number += 0x10;
536 }
6440adb5
BC
537
538 /* Descriptor for chosen Tx queue */
188cf6c7 539 txq = &priv->txq[txq_id];
b481de9c
ZY
540 q = &txq->q;
541
dc57a303
ZY
542 if ((iwl_queue_space(q) < q->high_mark))
543 goto drop;
544
b481de9c
ZY
545 spin_lock_irqsave(&priv->lock, flags);
546
fc4b6853 547 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 548
6440adb5 549 /* Set up driver data for this TFD */
dbb6654c 550 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
fc4b6853 551 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
BC
552
553 /* Init first empty entry in queue's array of Tx/cmd buffers */
188cf6c7 554 out_cmd = txq->cmd[idx];
c2acea8e 555 out_meta = &txq->meta[idx];
9744c91f 556 tx_cmd = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
b481de9c 557 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
9744c91f 558 memset(tx_cmd, 0, sizeof(*tx_cmd));
6440adb5
BC
559
560 /*
561 * Set up the Tx-command (not MAC!) header.
562 * Store the chosen Tx queue and TFD index within the sequence field;
563 * after Tx, uCode's Tx response will return this value so driver can
564 * locate the frame within the tx queue and do post-tx processing.
565 */
b481de9c
ZY
566 out_cmd->hdr.cmd = REPLY_TX;
567 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 568 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
BC
569
570 /* Copy MAC header from skb into command buffer */
9744c91f 571 memcpy(tx_cmd->hdr, hdr, hdr_len);
b481de9c 572
df833b1d
RC
573
574 if (info->control.hw_key)
575 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
576
577 /* TODO need this for burst mode later on */
578 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
579
580 /* set is_hcca to 0; it probably will never be implemented */
581 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
582
583 /* Total # bytes to be transmitted */
584 len = (u16)skb->len;
9744c91f 585 tx_cmd->len = cpu_to_le16(len);
df833b1d 586
20594eb0 587 iwl_dbg_log_tx_data_frame(priv, len, hdr);
22fdf3c9 588 iwl_update_stats(priv, true, fc, len);
9744c91f
AK
589 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
590 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
df833b1d
RC
591
592 if (!ieee80211_has_morefrags(hdr->frame_control)) {
593 txq->need_update = 1;
594 if (qc)
c587de0b 595 priv->stations[sta_id].tid[tid].seq_number = seq_number;
df833b1d
RC
596 } else {
597 wait_write_ptr = 1;
598 txq->need_update = 0;
599 }
600
91dd6c27 601 IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
df833b1d 602 le16_to_cpu(out_cmd->hdr.sequence));
91dd6c27 603 IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
9744c91f
AK
604 iwl_print_hex_dump(priv, IWL_DL_TX, tx_cmd, sizeof(*tx_cmd));
605 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr,
df833b1d
RC
606 ieee80211_hdrlen(fc));
607
6440adb5
BC
608 /*
609 * Use the first empty entry in this queue's command buffer array
610 * to contain the Tx command and MAC header concatenated together
611 * (payload data will be in another buffer).
612 * Size of this varies, due to varying MAC header length.
613 * If end is not dword aligned, we'll have 2 extra bytes at the end
614 * of the MAC header (device reads on dword boundaries).
615 * We'll tell device about this padding later.
616 */
3832ec9d 617 len = sizeof(struct iwl3945_tx_cmd) +
4c897253 618 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY
619
620 len_org = len;
621 len = (len + 3) & ~3;
622
623 if (len_org != len)
624 len_org = 1;
625 else
626 len_org = 0;
627
6440adb5
BC
628 /* Physical address of this Tx command's header (not MAC header!),
629 * within command buffer array. */
df833b1d
RC
630 txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
631 len, PCI_DMA_TODEVICE);
632 /* we do not map meta data ... so we can safely access address to
633 * provide to unmap command*/
c2acea8e
JB
634 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
635 pci_unmap_len_set(out_meta, len, len);
b481de9c 636
6440adb5
BC
637 /* Add buffer containing Tx command and MAC(!) header to TFD's
638 * first entry */
7aaa1d79
SO
639 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
640 txcmd_phys, len, 1, 0);
b481de9c 641
b481de9c 642
6440adb5
BC
643 /* Set up TFD's 2nd entry to point directly to remainder of skb,
644 * if any (802.11 null frames have no payload). */
b481de9c
ZY
645 len = skb->len - hdr_len;
646 if (len) {
647 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
648 len, PCI_DMA_TODEVICE);
7aaa1d79
SO
649 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
650 phys_addr, len,
651 0, U32_PAD(len));
b481de9c
ZY
652 }
653
b481de9c 654
6440adb5 655 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 656 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
7bfedc59 657 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
658 spin_unlock_irqrestore(&priv->lock, flags);
659
d20b3c65 660 if ((iwl_queue_space(q) < q->high_mark)
b481de9c
ZY
661 && priv->mac80211_registered) {
662 if (wait_write_ptr) {
663 spin_lock_irqsave(&priv->lock, flags);
664 txq->need_update = 1;
4f3602c8 665 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
666 spin_unlock_irqrestore(&priv->lock, flags);
667 }
668
e4e72fb4 669 iwl_stop_queue(priv, skb_get_queue_mapping(skb));
b481de9c
ZY
670 }
671
672 return 0;
673
674drop_unlock:
675 spin_unlock_irqrestore(&priv->lock, flags);
676drop:
677 return -1;
678}
679
b481de9c
ZY
680#define BEACON_TIME_MASK_LOW 0x00FFFFFF
681#define BEACON_TIME_MASK_HIGH 0xFF000000
682#define TIME_UNIT 1024
683
684/*
685 * extended beacon time format
686 * time in usec will be changed into a 32-bit value in 8:24 format
687 * the high 1 byte is the beacon counts
688 * the lower 3 bytes is the time in usec within one beacon interval
689 */
690
bb8c093b 691static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
692{
693 u32 quot;
694 u32 rem;
695 u32 interval = beacon_interval * 1024;
696
697 if (!interval || !usec)
698 return 0;
699
700 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
701 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
702
703 return (quot << 24) + rem;
704}
705
706/* base is usually what we get from ucode with each received frame,
707 * the same as HW timer counter counting down
708 */
709
bb8c093b 710static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
711{
712 u32 base_low = base & BEACON_TIME_MASK_LOW;
713 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
714 u32 interval = beacon_interval * TIME_UNIT;
715 u32 res = (base & BEACON_TIME_MASK_HIGH) +
716 (addon & BEACON_TIME_MASK_HIGH);
717
718 if (base_low > addon_low)
719 res += base_low - addon_low;
720 else if (base_low < addon_low) {
721 res += interval + base_low - addon_low;
722 res += (1 << 24);
723 } else
724 res += (1 << 24);
725
726 return cpu_to_le32(res);
727}
728
4a8a4322 729static int iwl3945_get_measurement(struct iwl_priv *priv,
b481de9c
ZY
730 struct ieee80211_measurement_params *params,
731 u8 type)
732{
600c0e11 733 struct iwl_spectrum_cmd spectrum;
2f301227 734 struct iwl_rx_packet *pkt;
c2d79b48 735 struct iwl_host_cmd cmd = {
b481de9c
ZY
736 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
737 .data = (void *)&spectrum,
c2acea8e 738 .flags = CMD_WANT_SKB,
b481de9c
ZY
739 };
740 u32 add_time = le64_to_cpu(params->start_time);
741 int rc;
742 int spectrum_resp_status;
743 int duration = le16_to_cpu(params->duration);
744
8ccde88a 745 if (iwl_is_associated(priv))
b481de9c 746 add_time =
bb8c093b 747 iwl3945_usecs_to_beacons(
e99f168c 748 le64_to_cpu(params->start_time) - priv->_3945.last_tsf,
b481de9c
ZY
749 le16_to_cpu(priv->rxon_timing.beacon_interval));
750
751 memset(&spectrum, 0, sizeof(spectrum));
752
753 spectrum.channel_count = cpu_to_le16(1);
754 spectrum.flags =
755 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
756 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
757 cmd.len = sizeof(spectrum);
758 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
759
8ccde88a 760 if (iwl_is_associated(priv))
b481de9c 761 spectrum.start_time =
e99f168c 762 iwl3945_add_beacon_time(priv->_3945.last_beacon_time,
b481de9c
ZY
763 add_time,
764 le16_to_cpu(priv->rxon_timing.beacon_interval));
765 else
766 spectrum.start_time = 0;
767
768 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
769 spectrum.channels[0].channel = params->channel;
770 spectrum.channels[0].type = type;
8ccde88a 771 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
b481de9c
ZY
772 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
773 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
774
518099a8 775 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
776 if (rc)
777 return rc;
778
2f301227
ZY
779 pkt = (struct iwl_rx_packet *)cmd.reply_page;
780 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 781 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
b481de9c
ZY
782 rc = -EIO;
783 }
784
2f301227 785 spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
b481de9c
ZY
786 switch (spectrum_resp_status) {
787 case 0: /* Command will be handled */
2f301227 788 if (pkt->u.spectrum.id != 0xff) {
e1623446 789 IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
2f301227 790 pkt->u.spectrum.id);
b481de9c
ZY
791 priv->measurement_status &= ~MEASUREMENT_READY;
792 }
793 priv->measurement_status |= MEASUREMENT_ACTIVE;
794 rc = 0;
795 break;
796
797 case 1: /* Command will not be handled */
798 rc = -EAGAIN;
799 break;
800 }
801
64a76b50 802 iwl_free_pages(priv, cmd.reply_page);
b481de9c
ZY
803
804 return rc;
805}
b481de9c 806
4a8a4322 807static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
6100b588 808 struct iwl_rx_mem_buffer *rxb)
b481de9c 809{
2f301227 810 struct iwl_rx_packet *pkt = rxb_addr(rxb);
3d24a9f7 811 struct iwl_alive_resp *palive;
b481de9c
ZY
812 struct delayed_work *pwork;
813
814 palive = &pkt->u.alive_frame;
815
e1623446 816 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
817 "0x%01X 0x%01X\n",
818 palive->is_valid, palive->ver_type,
819 palive->ver_subtype);
820
821 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 822 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
3d24a9f7
TW
823 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
824 sizeof(struct iwl_alive_resp));
b481de9c
ZY
825 pwork = &priv->init_alive_start;
826 } else {
e1623446 827 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 828 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 829 sizeof(struct iwl_alive_resp));
b481de9c 830 pwork = &priv->alive_start;
bb8c093b 831 iwl3945_disable_events(priv);
b481de9c
ZY
832 }
833
834 /* We delay the ALIVE response by 5ms to
835 * give the HW RF Kill time to activate... */
836 if (palive->is_valid == UCODE_VALID_OK)
837 queue_delayed_work(priv->workqueue, pwork,
838 msecs_to_jiffies(5));
839 else
39aadf8c 840 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
841}
842
4a8a4322 843static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
6100b588 844 struct iwl_rx_mem_buffer *rxb)
b481de9c 845{
c7e035a9 846#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 847 struct iwl_rx_packet *pkt = rxb_addr(rxb);
c7e035a9 848#endif
b481de9c 849
e1623446 850 IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
b481de9c
ZY
851}
852
bb8c093b 853static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 854{
4a8a4322
AK
855 struct iwl_priv *priv =
856 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
857 struct sk_buff *beacon;
858
859 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 860 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
861
862 if (!beacon) {
15b1687c 863 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
864 return;
865 }
866
867 mutex_lock(&priv->mutex);
868 /* new beacon skb is allocated every time; dispose previous.*/
869 if (priv->ibss_beacon)
870 dev_kfree_skb(priv->ibss_beacon);
871
872 priv->ibss_beacon = beacon;
873 mutex_unlock(&priv->mutex);
874
bb8c093b 875 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
876}
877
4a8a4322 878static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
6100b588 879 struct iwl_rx_mem_buffer *rxb)
b481de9c 880{
d08853a3 881#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 882 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b 883 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
884 u8 rate = beacon->beacon_notify_hdr.rate;
885
e1623446 886 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c
ZY
887 "tsf %d %d rate %d\n",
888 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
889 beacon->beacon_notify_hdr.failure_frame,
890 le32_to_cpu(beacon->ibss_mgr_status),
891 le32_to_cpu(beacon->high_tsf),
892 le32_to_cpu(beacon->low_tsf), rate);
893#endif
894
05c914fe 895 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
896 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
897 queue_work(priv->workqueue, &priv->beacon_update);
898}
899
b481de9c
ZY
900/* Handle notification from uCode that card's power state is changing
901 * due to software, hardware, or critical temperature RFKILL */
4a8a4322 902static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
6100b588 903 struct iwl_rx_mem_buffer *rxb)
b481de9c 904{
2f301227 905 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
906 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
907 unsigned long status = priv->status;
908
4c423a2b 909 IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
910 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
911 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
912
5d49f498 913 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
914 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
915
916 if (flags & HW_CARD_DISABLED)
917 set_bit(STATUS_RF_KILL_HW, &priv->status);
918 else
919 clear_bit(STATUS_RF_KILL_HW, &priv->status);
920
921
af0053d6 922 iwl_scan_cancel(priv);
b481de9c
ZY
923
924 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
925 test_bit(STATUS_RF_KILL_HW, &priv->status)))
926 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
927 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
928 else
929 wake_up_interruptible(&priv->wait_command_queue);
930}
931
932/**
bb8c093b 933 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
934 *
935 * Setup the RX handlers for each of the reply types sent from the uCode
936 * to the host.
937 *
938 * This function chains into the hardware specific files for them to setup
939 * any hardware specific handlers as well.
940 */
4a8a4322 941static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 942{
bb8c093b
CH
943 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
944 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
261b9c33 945 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
8ccde88a 946 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC
947 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
948 iwl_rx_spectrum_measure_notif;
030f05ed 949 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 950 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
030f05ed 951 iwl_rx_pm_debug_statistics_notif;
bb8c093b 952 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 953
9fbab516
BC
954 /*
955 * The same handler is used for both the REPLY to a discrete
956 * statistics request from the host as well as for the periodic
957 * statistics notifications (after received beacons) from the uCode.
b481de9c 958 */
17f36fc6 959 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_reply_statistics;
bb8c093b 960 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 961
cade0eb2 962 iwl_setup_rx_scan_handlers(priv);
bb8c093b 963 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 964
9fbab516 965 /* Set up hardware specific Rx handlers */
bb8c093b 966 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
967}
968
b481de9c
ZY
969/************************** RX-FUNCTIONS ****************************/
970/*
971 * Rx theory of operation
972 *
973 * The host allocates 32 DMA target addresses and passes the host address
974 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
975 * 0 to 31
976 *
977 * Rx Queue Indexes
978 * The host/firmware share two index registers for managing the Rx buffers.
979 *
980 * The READ index maps to the first position that the firmware may be writing
981 * to -- the driver can read up to (but not including) this position and get
982 * good data.
983 * The READ index is managed by the firmware once the card is enabled.
984 *
985 * The WRITE index maps to the last position the driver has read from -- the
986 * position preceding WRITE is the last slot the firmware can place a packet.
987 *
988 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
989 * WRITE = READ.
990 *
9fbab516 991 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
992 * INDEX position, and WRITE to the last (READ - 1 wrapped)
993 *
9fbab516 994 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
995 * and fire the RX interrupt. The driver can then query the READ index and
996 * process as many packets as possible, moving the WRITE index forward as it
997 * resets the Rx queue buffers with new memory.
998 *
999 * The management in the driver is as follows:
1000 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
1001 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 1002 * to replenish the iwl->rxq->rx_free.
bb8c093b 1003 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
1004 * iwl->rxq is replenished and the READ INDEX is updated (updating the
1005 * 'processed' and 'read' driver indexes as well)
1006 * + A received packet is processed and handed to the kernel network stack,
1007 * detached from the iwl->rxq. The driver 'processed' index is updated.
1008 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
1009 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
1010 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
1011 * were enough free buffers and RX_STALLED is set it is cleared.
1012 *
1013 *
1014 * Driver sequence:
1015 *
9fbab516 1016 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 1017 * iwl3945_rx_queue_restock
9fbab516 1018 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
1019 * queue, updates firmware pointers, and updates
1020 * the WRITE index. If insufficient rx_free buffers
bb8c093b 1021 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
1022 *
1023 * -- enable interrupts --
6100b588 1024 * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
b481de9c
ZY
1025 * READ INDEX, detaching the SKB from the pool.
1026 * Moves the packet buffer from queue to rx_used.
bb8c093b 1027 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
1028 * slots.
1029 * ...
1030 *
1031 */
1032
b481de9c 1033/**
9fbab516 1034 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 1035 */
4a8a4322 1036static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY
1037 dma_addr_t dma_addr)
1038{
1039 return cpu_to_le32((u32)dma_addr);
1040}
1041
1042/**
bb8c093b 1043 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 1044 *
9fbab516 1045 * If there are slots in the RX queue that need to be restocked,
b481de9c 1046 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 1047 * as we can, pulling from rx_free.
b481de9c
ZY
1048 *
1049 * This moves the 'write' index forward to catch up with 'processed', and
1050 * also updates the memory address in the firmware to reference the new
1051 * target buffer.
1052 */
7bfedc59 1053static void iwl3945_rx_queue_restock(struct iwl_priv *priv)
b481de9c 1054{
cc2f362c 1055 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1056 struct list_head *element;
6100b588 1057 struct iwl_rx_mem_buffer *rxb;
b481de9c 1058 unsigned long flags;
7bfedc59 1059 int write;
b481de9c
ZY
1060
1061 spin_lock_irqsave(&rxq->lock, flags);
1062 write = rxq->write & ~0x7;
37d68317 1063 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 1064 /* Get next free Rx buffer, remove from free list */
b481de9c 1065 element = rxq->rx_free.next;
6100b588 1066 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
b481de9c 1067 list_del(element);
6440adb5
BC
1068
1069 /* Point to Rx buffer via next RBD in circular buffer */
2f301227 1070 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->page_dma);
b481de9c
ZY
1071 rxq->queue[rxq->write] = rxb;
1072 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
1073 rxq->free_count--;
1074 }
1075 spin_unlock_irqrestore(&rxq->lock, flags);
1076 /* If the pre-allocated buffer pool is dropping low, schedule to
1077 * refill it */
1078 if (rxq->free_count <= RX_LOW_WATERMARK)
1079 queue_work(priv->workqueue, &priv->rx_replenish);
1080
1081
6440adb5
BC
1082 /* If we've added more space for the firmware to place data, tell it.
1083 * Increment device's write pointer in multiples of 8. */
d14d4440 1084 if ((rxq->write_actual != (rxq->write & ~0x7))
b481de9c
ZY
1085 || (abs(rxq->write - rxq->read) > 7)) {
1086 spin_lock_irqsave(&rxq->lock, flags);
1087 rxq->need_update = 1;
1088 spin_unlock_irqrestore(&rxq->lock, flags);
7bfedc59 1089 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c 1090 }
b481de9c
ZY
1091}
1092
1093/**
bb8c093b 1094 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
1095 *
1096 * When moving to rx_free an SKB is allocated for the slot.
1097 *
bb8c093b 1098 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 1099 * This is called as a scheduled work item (except for during initialization)
b481de9c 1100 */
d14d4440 1101static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
b481de9c 1102{
cc2f362c 1103 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1104 struct list_head *element;
6100b588 1105 struct iwl_rx_mem_buffer *rxb;
2f301227 1106 struct page *page;
b481de9c 1107 unsigned long flags;
29b1b268 1108 gfp_t gfp_mask = priority;
72240498
AK
1109
1110 while (1) {
1111 spin_lock_irqsave(&rxq->lock, flags);
1112
1113 if (list_empty(&rxq->rx_used)) {
1114 spin_unlock_irqrestore(&rxq->lock, flags);
1115 return;
1116 }
72240498 1117 spin_unlock_irqrestore(&rxq->lock, flags);
6440adb5 1118
f82a924c 1119 if (rxq->free_count > RX_LOW_WATERMARK)
29b1b268 1120 gfp_mask |= __GFP_NOWARN;
2f301227
ZY
1121
1122 if (priv->hw_params.rx_page_order > 0)
29b1b268 1123 gfp_mask |= __GFP_COMP;
2f301227 1124
6440adb5 1125 /* Alloc a new receive buffer */
29b1b268 1126 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
2f301227 1127 if (!page) {
b481de9c 1128 if (net_ratelimit())
f82a924c
RC
1129 IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
1130 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
1131 net_ratelimit())
1132 IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
1133 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
1134 rxq->free_count);
b481de9c
ZY
1135 /* We don't reschedule replenish work here -- we will
1136 * call the restock method and if it still needs
1137 * more buffers it will schedule replenish */
1138 break;
1139 }
12342c47 1140
de0bd508
RC
1141 spin_lock_irqsave(&rxq->lock, flags);
1142 if (list_empty(&rxq->rx_used)) {
1143 spin_unlock_irqrestore(&rxq->lock, flags);
2f301227 1144 __free_pages(page, priv->hw_params.rx_page_order);
de0bd508
RC
1145 return;
1146 }
1147 element = rxq->rx_used.next;
1148 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
1149 list_del(element);
1150 spin_unlock_irqrestore(&rxq->lock, flags);
1151
2f301227 1152 rxb->page = page;
6440adb5 1153 /* Get physical address of RB/SKB */
2f301227
ZY
1154 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
1155 PAGE_SIZE << priv->hw_params.rx_page_order,
1156 PCI_DMA_FROMDEVICE);
72240498
AK
1157
1158 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1159
b481de9c
ZY
1160 list_add_tail(&rxb->list, &rxq->rx_free);
1161 rxq->free_count++;
2f301227
ZY
1162 priv->alloc_rxb_page++;
1163
72240498 1164 spin_unlock_irqrestore(&rxq->lock, flags);
b481de9c 1165 }
5c0eef96
MA
1166}
1167
df833b1d
RC
1168void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1169{
1170 unsigned long flags;
1171 int i;
1172 spin_lock_irqsave(&rxq->lock, flags);
1173 INIT_LIST_HEAD(&rxq->rx_free);
1174 INIT_LIST_HEAD(&rxq->rx_used);
1175 /* Fill the rx_used queue with _all_ of the Rx buffers */
1176 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1177 /* In the reset function, these buffers may have been allocated
1178 * to an SKB, so we need to unmap and free potential storage */
2f301227
ZY
1179 if (rxq->pool[i].page != NULL) {
1180 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
1181 PAGE_SIZE << priv->hw_params.rx_page_order,
1182 PCI_DMA_FROMDEVICE);
64a76b50 1183 __iwl_free_pages(priv, rxq->pool[i].page);
2f301227 1184 rxq->pool[i].page = NULL;
df833b1d
RC
1185 }
1186 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1187 }
1188
1189 /* Set us so that we have processed and used all buffers, but have
1190 * not restocked the Rx queue with fresh buffers */
1191 rxq->read = rxq->write = 0;
d14d4440 1192 rxq->write_actual = 0;
2f301227 1193 rxq->free_count = 0;
df833b1d
RC
1194 spin_unlock_irqrestore(&rxq->lock, flags);
1195}
df833b1d 1196
5c0eef96
MA
1197void iwl3945_rx_replenish(void *data)
1198{
4a8a4322 1199 struct iwl_priv *priv = data;
5c0eef96
MA
1200 unsigned long flags;
1201
d14d4440 1202 iwl3945_rx_allocate(priv, GFP_KERNEL);
b481de9c
ZY
1203
1204 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1205 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1206 spin_unlock_irqrestore(&priv->lock, flags);
1207}
1208
d14d4440
AK
1209static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
1210{
1211 iwl3945_rx_allocate(priv, GFP_ATOMIC);
1212
1213 iwl3945_rx_queue_restock(priv);
1214}
1215
1216
df833b1d
RC
1217/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1218 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1219 * This free routine walks the list of POOL entries and if SKB is set to
1220 * non NULL it is unmapped and freed
1221 */
1222static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1223{
1224 int i;
1225 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
2f301227
ZY
1226 if (rxq->pool[i].page != NULL) {
1227 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
1228 PAGE_SIZE << priv->hw_params.rx_page_order,
1229 PCI_DMA_FROMDEVICE);
64a76b50 1230 __iwl_free_pages(priv, rxq->pool[i].page);
2f301227 1231 rxq->pool[i].page = NULL;
df833b1d
RC
1232 }
1233 }
1234
f36d04ab
SG
1235 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1236 rxq->dma_addr);
1237 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
1238 rxq->rb_stts, rxq->rb_stts_dma);
df833b1d
RC
1239 rxq->bd = NULL;
1240 rxq->rb_stts = NULL;
1241}
df833b1d
RC
1242
1243
b481de9c
ZY
1244/* Convert linear signal-to-noise ratio into dB */
1245static u8 ratio2dB[100] = {
1246/* 0 1 2 3 4 5 6 7 8 9 */
1247 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1248 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1249 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1250 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1251 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1252 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1253 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1254 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1255 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1256 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
1257};
1258
1259/* Calculates a relative dB value from a ratio of linear
1260 * (i.e. not dB) signal levels.
1261 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 1262int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 1263{
221c80cf
AB
1264 /* 1000:1 or higher just report as 60 dB */
1265 if (sig_ratio >= 1000)
b481de9c
ZY
1266 return 60;
1267
221c80cf 1268 /* 100:1 or higher, divide by 10 and use table,
b481de9c 1269 * add 20 dB to make up for divide by 10 */
221c80cf 1270 if (sig_ratio >= 100)
3ac7f146 1271 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY
1272
1273 /* We shouldn't see this */
1274 if (sig_ratio < 1)
1275 return 0;
1276
1277 /* Use table for ratios 1:1 - 99:1 */
1278 return (int)ratio2dB[sig_ratio];
1279}
1280
b481de9c 1281/**
9fbab516 1282 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
1283 *
1284 * Uses the priv->rx_handlers callback function array to invoke
1285 * the appropriate handlers, including command responses,
1286 * frame-received notifications, and other notifications.
1287 */
4a8a4322 1288static void iwl3945_rx_handle(struct iwl_priv *priv)
b481de9c 1289{
6100b588 1290 struct iwl_rx_mem_buffer *rxb;
3d24a9f7 1291 struct iwl_rx_packet *pkt;
cc2f362c 1292 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
1293 u32 r, i;
1294 int reclaim;
1295 unsigned long flags;
5c0eef96 1296 u8 fill_rx = 0;
d68ab680 1297 u32 count = 8;
d14d4440 1298 int total_empty = 0;
b481de9c 1299
6440adb5
BC
1300 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1301 * buffer that the driver may process (last buffer filled by ucode). */
8cd812bc 1302 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
1303 i = rxq->read;
1304
d14d4440 1305 /* calculate total frames need to be restock after handling RX */
7300515d 1306 total_empty = r - rxq->write_actual;
d14d4440
AK
1307 if (total_empty < 0)
1308 total_empty += RX_QUEUE_SIZE;
1309
1310 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96 1311 fill_rx = 1;
b481de9c
ZY
1312 /* Rx interrupt, but nothing sent from uCode */
1313 if (i == r)
af472a95 1314 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c
ZY
1315
1316 while (i != r) {
1317 rxb = rxq->queue[i];
1318
9fbab516 1319 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
1320 * then a bug has been introduced in the queue refilling
1321 * routines -- catch it here */
1322 BUG_ON(rxb == NULL);
1323
1324 rxq->queue[i] = NULL;
1325
2f301227
ZY
1326 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1327 PAGE_SIZE << priv->hw_params.rx_page_order,
1328 PCI_DMA_FROMDEVICE);
1329 pkt = rxb_addr(rxb);
b481de9c 1330
be1a71a1
JB
1331 trace_iwlwifi_dev_rx(priv, pkt,
1332 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
1333
b481de9c
ZY
1334 /* Reclaim a command buffer only if this packet is a response
1335 * to a (driver-originated) command.
1336 * If the packet (e.g. Rx frame) originated from uCode,
1337 * there is no command buffer to reclaim.
1338 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1339 * but apparently a few don't get set; catch them here. */
1340 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1341 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1342 (pkt->hdr.cmd != REPLY_TX);
1343
1344 /* Based on type of command response or notification,
1345 * handle those that need handling via function in
bb8c093b 1346 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c 1347 if (priv->rx_handlers[pkt->hdr.cmd]) {
af472a95 1348 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i,
b481de9c 1349 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
86ddbf62 1350 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 1351 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
1352 } else {
1353 /* No handling needed */
2f301227
ZY
1354 IWL_DEBUG_RX(priv,
1355 "r %d i %d No handler needed for %s, 0x%02x\n",
b481de9c
ZY
1356 r, i, get_cmd_string(pkt->hdr.cmd),
1357 pkt->hdr.cmd);
1358 }
1359
29b1b268
ZY
1360 /*
1361 * XXX: After here, we should always check rxb->page
1362 * against NULL before touching it or its virtual
1363 * memory (pkt). Because some rx_handler might have
1364 * already taken or freed the pages.
1365 */
1366
b481de9c 1367 if (reclaim) {
2f301227
ZY
1368 /* Invoke any callbacks, transfer the buffer to caller,
1369 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1370 * as we reclaim the driver command queue */
29b1b268 1371 if (rxb->page)
732587ab 1372 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1373 else
39aadf8c 1374 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
1375 }
1376
7300515d
ZY
1377 /* Reuse the page if possible. For notification packets and
1378 * SKBs that fail to Rx correctly, add them back into the
1379 * rx_free list for reuse later. */
1380 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1381 if (rxb->page != NULL) {
7300515d
ZY
1382 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1383 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1384 PCI_DMA_FROMDEVICE);
1385 list_add_tail(&rxb->list, &rxq->rx_free);
1386 rxq->free_count++;
1387 } else
1388 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1389
b481de9c 1390 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1391
b481de9c 1392 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1393 /* If there are a lot of unused frames,
1394 * restock the Rx queue so ucode won't assert. */
1395 if (fill_rx) {
1396 count++;
1397 if (count >= 8) {
7300515d 1398 rxq->read = i;
d14d4440 1399 iwl3945_rx_replenish_now(priv);
5c0eef96
MA
1400 count = 0;
1401 }
1402 }
b481de9c
ZY
1403 }
1404
1405 /* Backtrack one entry */
7300515d 1406 rxq->read = i;
d14d4440
AK
1407 if (fill_rx)
1408 iwl3945_rx_replenish_now(priv);
1409 else
1410 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1411}
1412
0359facc 1413/* call this function to flush any scheduled tasklet */
4a8a4322 1414static inline void iwl_synchronize_irq(struct iwl_priv *priv)
0359facc 1415{
a96a27f9 1416 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1417 synchronize_irq(priv->pci_dev->irq);
1418 tasklet_kill(&priv->irq_tasklet);
1419}
1420
b481de9c
ZY
1421static const char *desc_lookup(int i)
1422{
1423 switch (i) {
1424 case 1:
1425 return "FAIL";
1426 case 2:
1427 return "BAD_PARAM";
1428 case 3:
1429 return "BAD_CHECKSUM";
1430 case 4:
1431 return "NMI_INTERRUPT";
1432 case 5:
1433 return "SYSASSERT";
1434 case 6:
1435 return "FATAL_ERROR";
1436 }
1437
1438 return "UNKNOWN";
1439}
1440
1441#define ERROR_START_OFFSET (1 * sizeof(u32))
1442#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1443
b7a79404 1444void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY
1445{
1446 u32 i;
1447 u32 desc, time, count, base, data1;
1448 u32 blink1, blink2, ilink1, ilink2;
b481de9c
ZY
1449
1450 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1451
bb8c093b 1452 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1453 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
b481de9c
ZY
1454 return;
1455 }
1456
b481de9c 1457
5d49f498 1458 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY
1459
1460 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT
1461 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1462 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1463 priv->status, count);
b481de9c
ZY
1464 }
1465
15b1687c 1466 IWL_ERR(priv, "Desc Time asrtPC blink2 "
b481de9c
ZY
1467 "ilink1 nmiPC Line\n");
1468 for (i = ERROR_START_OFFSET;
1469 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1470 i += ERROR_ELEM_SIZE) {
5d49f498 1471 desc = iwl_read_targ_mem(priv, base + i);
b481de9c 1472 time =
5d49f498 1473 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 1474 blink1 =
5d49f498 1475 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 1476 blink2 =
5d49f498 1477 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 1478 ilink1 =
5d49f498 1479 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 1480 ilink2 =
5d49f498 1481 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 1482 data1 =
5d49f498 1483 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c 1484
15b1687c
WT
1485 IWL_ERR(priv,
1486 "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1487 desc_lookup(desc), desc, time, blink1, blink2,
1488 ilink1, ilink2, data1);
be1a71a1
JB
1489 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, 0,
1490 0, blink1, blink2, ilink1, ilink2);
b481de9c 1491 }
b481de9c
ZY
1492}
1493
f58177b9 1494#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
1495
1496/**
bb8c093b 1497 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 1498 *
b481de9c 1499 */
b03d7d0f
WYG
1500static int iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
1501 u32 num_events, u32 mode,
1502 int pos, char **buf, size_t bufsz)
b481de9c
ZY
1503{
1504 u32 i;
1505 u32 base; /* SRAM byte address of event log header */
1506 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1507 u32 ptr; /* SRAM byte address of log data */
1508 u32 ev, time, data; /* event log data */
e5854471 1509 unsigned long reg_flags;
b481de9c
ZY
1510
1511 if (num_events == 0)
b03d7d0f 1512 return pos;
b481de9c
ZY
1513
1514 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1515
1516 if (mode == 0)
1517 event_size = 2 * sizeof(u32);
1518 else
1519 event_size = 3 * sizeof(u32);
1520
1521 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1522
e5854471
BC
1523 /* Make sure device is powered up for SRAM reads */
1524 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1525 iwl_grab_nic_access(priv);
1526
1527 /* Set starting address; reads will auto-increment */
1528 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1529 rmb();
1530
b481de9c
ZY
1531 /* "time" is actually "data" for mode 0 (no timestamp).
1532 * place event id # at far right for easier visual parsing. */
1533 for (i = 0; i < num_events; i++) {
e5854471
BC
1534 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1535 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
15b1687c
WT
1536 if (mode == 0) {
1537 /* data, ev */
b03d7d0f
WYG
1538 if (bufsz) {
1539 pos += scnprintf(*buf + pos, bufsz - pos,
1540 "0x%08x:%04u\n",
1541 time, ev);
1542 } else {
1543 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
1544 trace_iwlwifi_dev_ucode_event(priv, 0,
1545 time, ev);
1546 }
15b1687c 1547 } else {
e5854471 1548 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG
1549 if (bufsz) {
1550 pos += scnprintf(*buf + pos, bufsz - pos,
1551 "%010u:0x%08x:%04u\n",
1552 time, data, ev);
1553 } else {
1554 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n",
1555 time, data, ev);
1556 trace_iwlwifi_dev_ucode_event(priv, time,
1557 data, ev);
1558 }
b481de9c
ZY
1559 }
1560 }
e5854471
BC
1561
1562 /* Allow device to power down */
1563 iwl_release_nic_access(priv);
1564 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 1565 return pos;
b481de9c
ZY
1566}
1567
c341ddb2
WYG
1568/**
1569 * iwl3945_print_last_event_logs - Dump the newest # of event log to syslog
1570 */
b03d7d0f 1571static int iwl3945_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
c341ddb2 1572 u32 num_wraps, u32 next_entry,
b03d7d0f
WYG
1573 u32 size, u32 mode,
1574 int pos, char **buf, size_t bufsz)
c341ddb2
WYG
1575{
1576 /*
1577 * display the newest DEFAULT_LOG_ENTRIES entries
1578 * i.e the entries just before the next ont that uCode would fill.
1579 */
1580 if (num_wraps) {
1581 if (next_entry < size) {
b03d7d0f
WYG
1582 pos = iwl3945_print_event_log(priv,
1583 capacity - (size - next_entry),
1584 size - next_entry, mode,
1585 pos, buf, bufsz);
1586 pos = iwl3945_print_event_log(priv, 0,
1587 next_entry, mode,
1588 pos, buf, bufsz);
c341ddb2 1589 } else
b03d7d0f
WYG
1590 pos = iwl3945_print_event_log(priv, next_entry - size,
1591 size, mode,
1592 pos, buf, bufsz);
c341ddb2
WYG
1593 } else {
1594 if (next_entry < size)
b03d7d0f
WYG
1595 pos = iwl3945_print_event_log(priv, 0,
1596 next_entry, mode,
1597 pos, buf, bufsz);
c341ddb2 1598 else
b03d7d0f
WYG
1599 pos = iwl3945_print_event_log(priv, next_entry - size,
1600 size, mode,
1601 pos, buf, bufsz);
c341ddb2 1602 }
b03d7d0f 1603 return pos;
c341ddb2
WYG
1604}
1605
c341ddb2
WYG
1606#define DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES (20)
1607
b03d7d0f
WYG
1608int iwl3945_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
1609 char **buf, bool display)
b481de9c 1610{
b481de9c
ZY
1611 u32 base; /* SRAM byte address of event log header */
1612 u32 capacity; /* event log capacity in # entries */
1613 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1614 u32 num_wraps; /* # times uCode wrapped to top of log */
1615 u32 next_entry; /* index of next entry to be written by uCode */
1616 u32 size; /* # entries that we'll print */
b03d7d0f
WYG
1617 int pos = 0;
1618 size_t bufsz = 0;
b481de9c
ZY
1619
1620 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 1621 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1622 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
937c397e 1623 return -EINVAL;
b481de9c
ZY
1624 }
1625
b481de9c 1626 /* event log header */
5d49f498
AK
1627 capacity = iwl_read_targ_mem(priv, base);
1628 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1629 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1630 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c 1631
678b385d 1632 if (capacity > priv->cfg->max_event_log_size) {
84c40692 1633 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
678b385d
WYG
1634 capacity, priv->cfg->max_event_log_size);
1635 capacity = priv->cfg->max_event_log_size;
84c40692
BC
1636 }
1637
678b385d 1638 if (next_entry > priv->cfg->max_event_log_size) {
84c40692 1639 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
678b385d
WYG
1640 next_entry, priv->cfg->max_event_log_size);
1641 next_entry = priv->cfg->max_event_log_size;
84c40692
BC
1642 }
1643
b481de9c
ZY
1644 size = num_wraps ? capacity : next_entry;
1645
1646 /* bail out if nothing in log */
1647 if (size == 0) {
15b1687c 1648 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 1649 return pos;
b481de9c
ZY
1650 }
1651
c341ddb2 1652#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 1653 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG
1654 size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
1655 ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
1656#else
1657 size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
1658 ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
1659#endif
1660
1661 IWL_ERR(priv, "Start IWL Event Log Dump: display last %d count\n",
1662 size);
b481de9c 1663
c341ddb2 1664#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG
1665 if (display) {
1666 if (full_log)
1667 bufsz = capacity * 48;
1668 else
1669 bufsz = size * 48;
1670 *buf = kmalloc(bufsz, GFP_KERNEL);
1671 if (!*buf)
937c397e 1672 return -ENOMEM;
b03d7d0f 1673 }
c341ddb2
WYG
1674 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
1675 /* if uCode has wrapped back to top of log,
1676 * start at the oldest entry,
1677 * i.e the next one that uCode would fill.
1678 */
1679 if (num_wraps)
b03d7d0f
WYG
1680 pos = iwl3945_print_event_log(priv, next_entry,
1681 capacity - next_entry, mode,
1682 pos, buf, bufsz);
c341ddb2
WYG
1683
1684 /* (then/else) start at top of log */
b03d7d0f
WYG
1685 pos = iwl3945_print_event_log(priv, 0, next_entry, mode,
1686 pos, buf, bufsz);
c341ddb2 1687 } else
b03d7d0f
WYG
1688 pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
1689 next_entry, size, mode,
1690 pos, buf, bufsz);
b7a79404 1691#else
b03d7d0f
WYG
1692 pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
1693 next_entry, size, mode,
1694 pos, buf, bufsz);
c341ddb2 1695#endif
b03d7d0f 1696 return pos;
b7a79404
RC
1697}
1698
4a8a4322 1699static void iwl3945_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
1700{
1701 u32 inta, handled = 0;
1702 u32 inta_fh;
1703 unsigned long flags;
d08853a3 1704#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1705 u32 inta_mask;
1706#endif
1707
1708 spin_lock_irqsave(&priv->lock, flags);
1709
1710 /* Ack/clear/reset pending uCode interrupts.
1711 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1712 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
5d49f498
AK
1713 inta = iwl_read32(priv, CSR_INT);
1714 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1715
1716 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1717 * Any new interrupts that happen after this, either while we're
1718 * in this tasklet, or later, will show up in next ISR/tasklet. */
5d49f498
AK
1719 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1720 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1721
d08853a3 1722#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1723 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1724 /* just for debug */
5d49f498 1725 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1726 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1727 inta, inta_mask, inta_fh);
1728 }
1729#endif
1730
2f301227
ZY
1731 spin_unlock_irqrestore(&priv->lock, flags);
1732
b481de9c
ZY
1733 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1734 * atomic, make sure that inta covers all the interrupts that
1735 * we've discovered, even if FH interrupt came in just after
1736 * reading CSR_INT. */
6f83eaa1 1737 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 1738 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1739 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY
1740 inta |= CSR_INT_BIT_FH_TX;
1741
1742 /* Now service all interrupt bits discovered above. */
1743 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1744 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
1745
1746 /* Tell the device to stop sending interrupts */
ed3b932e 1747 iwl_disable_interrupts(priv);
b481de9c 1748
86ddbf62 1749 priv->isr_stats.hw++;
8ccde88a 1750 iwl_irq_handle_error(priv);
b481de9c
ZY
1751
1752 handled |= CSR_INT_BIT_HW_ERR;
1753
b481de9c
ZY
1754 return;
1755 }
1756
d08853a3 1757#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1758 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1759 /* NIC fires this, but we don't use it, redundant with WAKEUP */
86ddbf62 1760 if (inta & CSR_INT_BIT_SCD) {
e1623446 1761 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1762 "the frame/frames.\n");
86ddbf62
AK
1763 priv->isr_stats.sch++;
1764 }
b481de9c
ZY
1765
1766 /* Alive notification via Rx interrupt will do the real work */
86ddbf62 1767 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1768 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
86ddbf62
AK
1769 priv->isr_stats.alive++;
1770 }
b481de9c
ZY
1771 }
1772#endif
1773 /* Safely ignore these bits for debug checks below */
25c03d8e 1774 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1775
b481de9c
ZY
1776 /* Error detected by uCode */
1777 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1778 IWL_ERR(priv, "Microcode SW error detected. "
1779 "Restarting 0x%X.\n", inta);
86ddbf62
AK
1780 priv->isr_stats.sw++;
1781 priv->isr_stats.sw_err = inta;
8ccde88a 1782 iwl_irq_handle_error(priv);
b481de9c
ZY
1783 handled |= CSR_INT_BIT_SW_ERR;
1784 }
1785
1786 /* uCode wakes up after power-down sleep */
1787 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1788 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
141c43a3 1789 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
4f3602c8
SO
1790 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1791 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1792 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1793 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1794 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1795 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1796
86ddbf62 1797 priv->isr_stats.wakeup++;
b481de9c
ZY
1798 handled |= CSR_INT_BIT_WAKEUP;
1799 }
1800
1801 /* All uCode command responses, including Tx command responses,
1802 * Rx "responses" (frame-received notification), and other
1803 * notifications from uCode come through here*/
1804 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 1805 iwl3945_rx_handle(priv);
86ddbf62 1806 priv->isr_stats.rx++;
b481de9c
ZY
1807 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1808 }
1809
1810 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1811 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
86ddbf62 1812 priv->isr_stats.tx++;
b481de9c 1813
5d49f498 1814 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
a8b50a0a
MA
1815 iwl_write_direct32(priv, FH39_TCSR_CREDIT
1816 (FH39_SRVC_CHNL), 0x0);
b481de9c
ZY
1817 handled |= CSR_INT_BIT_FH_TX;
1818 }
1819
86ddbf62 1820 if (inta & ~handled) {
15b1687c 1821 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
86ddbf62
AK
1822 priv->isr_stats.unhandled++;
1823 }
b481de9c 1824
40cefda9 1825 if (inta & ~priv->inta_mask) {
39aadf8c 1826 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1827 inta & ~priv->inta_mask);
39aadf8c 1828 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1829 }
1830
1831 /* Re-enable all interrupts */
0359facc
MA
1832 /* only Re-enable if disabled by irq */
1833 if (test_bit(STATUS_INT_ENABLED, &priv->status))
ed3b932e 1834 iwl_enable_interrupts(priv);
b481de9c 1835
d08853a3 1836#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1837 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
5d49f498
AK
1838 inta = iwl_read32(priv, CSR_INT);
1839 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1840 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1841 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1842 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1843 }
1844#endif
b481de9c
ZY
1845}
1846
4a8a4322 1847static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 1848 enum ieee80211_band band,
f9340520 1849 u8 is_active, u8 n_probes,
bb8c093b 1850 struct iwl3945_scan_channel *scan_ch)
b481de9c 1851{
4e05c234 1852 struct ieee80211_channel *chan;
8318d78a 1853 const struct ieee80211_supported_band *sband;
d20b3c65 1854 const struct iwl_channel_info *ch_info;
b481de9c
ZY
1855 u16 passive_dwell = 0;
1856 u16 active_dwell = 0;
1857 int added, i;
1858
cbba18c6 1859 sband = iwl_get_hw_mode(priv, band);
8318d78a 1860 if (!sband)
b481de9c
ZY
1861 return 0;
1862
77fecfb8
SO
1863 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1864 passive_dwell = iwl_get_passive_dwell_time(priv, band);
b481de9c 1865
8f4807a1
AK
1866 if (passive_dwell <= active_dwell)
1867 passive_dwell = active_dwell + 1;
1868
4e05c234
JB
1869 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1870 chan = priv->scan_request->channels[i];
1871
1872 if (chan->band != band)
182e2e66
JB
1873 continue;
1874
4e05c234 1875 scan_ch->channel = chan->hw_value;
b481de9c 1876
e6148917 1877 ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
b481de9c 1878 if (!is_channel_valid(ch_info)) {
e1623446 1879 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
b481de9c
ZY
1880 scan_ch->channel);
1881 continue;
1882 }
1883
011a0330
AK
1884 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1885 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1886 /* If passive , set up for auto-switch
1887 * and use long active_dwell time.
1888 */
b481de9c 1889 if (!is_active || is_channel_passive(ch_info) ||
4e05c234 1890 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 1891 scan_ch->type = 0; /* passive */
011a0330
AK
1892 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1893 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
1894 } else {
b481de9c 1895 scan_ch->type = 1; /* active */
011a0330 1896 }
b481de9c 1897
011a0330
AK
1898 /* Set direct probe bits. These may be used both for active
1899 * scan channels (probes gets sent right away),
1900 * or for passive channels (probes get se sent only after
1901 * hearing clear Rx packet).*/
1902 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
1903 if (n_probes)
0d21044e 1904 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330
AK
1905 } else {
1906 /* uCode v1 does not allow setting direct probe bits on
1907 * passive channel. */
1908 if ((scan_ch->type & 1) && n_probes)
0d21044e 1909 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330 1910 }
b481de9c 1911
9fbab516 1912 /* Set txpower levels to defaults */
b481de9c
ZY
1913 scan_ch->tpc.dsp_atten = 110;
1914 /* scan_pwr_info->tpc.dsp_atten; */
1915
1916 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 1917 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
1918 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1919 else {
1920 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1921 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 1922 * power level:
8a1b0245 1923 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
1924 */
1925 }
1926
e1623446 1927 IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
b481de9c
ZY
1928 scan_ch->channel,
1929 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1930 (scan_ch->type & 1) ?
1931 active_dwell : passive_dwell);
1932
1933 scan_ch++;
1934 added++;
1935 }
1936
91dd6c27 1937 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
b481de9c
ZY
1938 return added;
1939}
1940
4a8a4322 1941static void iwl3945_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY
1942 struct ieee80211_rate *rates)
1943{
1944 int i;
1945
8e1a53c6 1946 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
8318d78a
JB
1947 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
1948 rates[i].hw_value = i; /* Rate scaling will work on indexes */
1949 rates[i].hw_value_short = i;
1950 rates[i].flags = 0;
d9829a67 1951 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 1952 /*
8318d78a 1953 * If CCK != 1M then set short preamble rate flag.
b481de9c 1954 */
bb8c093b 1955 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 1956 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 1957 }
b481de9c
ZY
1958 }
1959}
1960
b481de9c
ZY
1961/******************************************************************************
1962 *
1963 * uCode download functions
1964 *
1965 ******************************************************************************/
1966
4a8a4322 1967static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1968{
98c92211
TW
1969 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1970 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1971 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1972 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1973 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1974 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1975}
1976
1977/**
bb8c093b 1978 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
1979 * looking at all data.
1980 */
4a8a4322 1981static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
1982{
1983 u32 val;
1984 u32 save_len = len;
1985 int rc = 0;
1986 u32 errcnt;
1987
e1623446 1988 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 1989
5d49f498 1990 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1991 IWL39_RTC_INST_LOWER_BOUND);
b481de9c
ZY
1992
1993 errcnt = 0;
1994 for (; len > 0; len -= sizeof(u32), image++) {
1995 /* read data comes through single port, auto-incr addr */
1996 /* NOTE: Use the debugless read so we don't flood kernel log
1997 * if IWL_DL_IO is set */
5d49f498 1998 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c 1999 if (val != le32_to_cpu(*image)) {
15b1687c 2000 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
2001 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2002 save_len - len, val, le32_to_cpu(*image));
2003 rc = -EIO;
2004 errcnt++;
2005 if (errcnt >= 20)
2006 break;
2007 }
2008 }
2009
b481de9c
ZY
2010
2011 if (!errcnt)
e1623446
TW
2012 IWL_DEBUG_INFO(priv,
2013 "ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
2014
2015 return rc;
2016}
2017
2018
2019/**
bb8c093b 2020 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
2021 * using sample data 100 bytes apart. If these sample points are good,
2022 * it's a pretty good bet that everything between them is good, too.
2023 */
4a8a4322 2024static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
2025{
2026 u32 val;
2027 int rc = 0;
2028 u32 errcnt = 0;
2029 u32 i;
2030
e1623446 2031 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 2032
b481de9c
ZY
2033 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2034 /* read data comes through single port, auto-incr addr */
2035 /* NOTE: Use the debugless read so we don't flood kernel log
2036 * if IWL_DL_IO is set */
5d49f498 2037 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2038 i + IWL39_RTC_INST_LOWER_BOUND);
5d49f498 2039 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
2040 if (val != le32_to_cpu(*image)) {
2041#if 0 /* Enable this if you want to see details */
15b1687c 2042 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
2043 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2044 i, val, *image);
2045#endif
2046 rc = -EIO;
2047 errcnt++;
2048 if (errcnt >= 3)
2049 break;
2050 }
2051 }
2052
b481de9c
ZY
2053 return rc;
2054}
2055
2056
2057/**
bb8c093b 2058 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
2059 * and verify its contents
2060 */
4a8a4322 2061static int iwl3945_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY
2062{
2063 __le32 *image;
2064 u32 len;
2065 int rc = 0;
2066
2067 /* Try bootstrap */
2068 image = (__le32 *)priv->ucode_boot.v_addr;
2069 len = priv->ucode_boot.len;
bb8c093b 2070 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2071 if (rc == 0) {
e1623446 2072 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b481de9c
ZY
2073 return 0;
2074 }
2075
2076 /* Try initialize */
2077 image = (__le32 *)priv->ucode_init.v_addr;
2078 len = priv->ucode_init.len;
bb8c093b 2079 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2080 if (rc == 0) {
e1623446 2081 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b481de9c
ZY
2082 return 0;
2083 }
2084
2085 /* Try runtime/protocol */
2086 image = (__le32 *)priv->ucode_code.v_addr;
2087 len = priv->ucode_code.len;
bb8c093b 2088 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2089 if (rc == 0) {
e1623446 2090 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b481de9c
ZY
2091 return 0;
2092 }
2093
15b1687c 2094 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b481de9c 2095
9fbab516
BC
2096 /* Since nothing seems to match, show first several data entries in
2097 * instruction SRAM, so maybe visual inspection will give a clue.
2098 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
2099 image = (__le32 *)priv->ucode_boot.v_addr;
2100 len = priv->ucode_boot.len;
bb8c093b 2101 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
2102
2103 return rc;
2104}
2105
4a8a4322 2106static void iwl3945_nic_start(struct iwl_priv *priv)
b481de9c
ZY
2107{
2108 /* Remove all resets to allow NIC to operate */
5d49f498 2109 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY
2110}
2111
2112/**
bb8c093b 2113 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
2114 *
2115 * Copy into buffers for card to fetch via bus-mastering
2116 */
4a8a4322 2117static int iwl3945_read_ucode(struct iwl_priv *priv)
b481de9c 2118{
cc0f555d 2119 const struct iwl_ucode_header *ucode;
a0987a8d 2120 int ret = -EINVAL, index;
b481de9c
ZY
2121 const struct firmware *ucode_raw;
2122 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC
2123 const char *name_pre = priv->cfg->fw_name_pre;
2124 const unsigned int api_max = priv->cfg->ucode_api_max;
2125 const unsigned int api_min = priv->cfg->ucode_api_min;
2126 char buf[25];
b481de9c
ZY
2127 u8 *src;
2128 size_t len;
a0987a8d 2129 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
2130
2131 /* Ask kernel firmware_class module to get the boot firmware off disk.
2132 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
2133 for (index = api_max; index >= api_min; index--) {
2134 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
2135 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
2136 if (ret < 0) {
15b1687c 2137 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
2138 buf, ret);
2139 if (ret == -ENOENT)
2140 continue;
2141 else
2142 goto error;
2143 } else {
2144 if (index < api_max)
15b1687c
WT
2145 IWL_ERR(priv, "Loaded firmware %s, "
2146 "which is deprecated. "
2147 " Please use API v%u instead.\n",
a0987a8d 2148 buf, api_max);
e1623446
TW
2149 IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
2150 "(%zd bytes) from disk\n",
a0987a8d
RC
2151 buf, ucode_raw->size);
2152 break;
2153 }
b481de9c
ZY
2154 }
2155
a0987a8d
RC
2156 if (ret < 0)
2157 goto error;
b481de9c
ZY
2158
2159 /* Make sure that we got at least our header! */
cc0f555d 2160 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 2161 IWL_ERR(priv, "File size way too small!\n");
90e759d1 2162 ret = -EINVAL;
b481de9c
ZY
2163 goto err_release;
2164 }
2165
2166 /* Data from ucode file: header followed by uCode images */
cc0f555d 2167 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2168
c02b3acd 2169 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 2170 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
2171 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
2172 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
2173 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
2174 init_data_size =
2175 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
2176 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
2177 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 2178
a0987a8d
RC
2179 /* api_ver should match the api version forming part of the
2180 * firmware filename ... but we don't check for that and only rely
877d0310 2181 * on the API version read from firmware header from here on forward */
a0987a8d
RC
2182
2183 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2184 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
2185 "Driver supports v%u, firmware is v%u.\n",
2186 api_max, api_ver);
2187 priv->ucode_ver = 0;
2188 ret = -EINVAL;
2189 goto err_release;
2190 }
2191 if (api_ver != api_max)
15b1687c 2192 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
a0987a8d
RC
2193 "got %u. New firmware can be obtained "
2194 "from http://www.intellinuxwireless.org.\n",
2195 api_max, api_ver);
2196
978785a3
TW
2197 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
2198 IWL_UCODE_MAJOR(priv->ucode_ver),
2199 IWL_UCODE_MINOR(priv->ucode_ver),
2200 IWL_UCODE_API(priv->ucode_ver),
2201 IWL_UCODE_SERIAL(priv->ucode_ver));
2202
5ebeb5a6
RC
2203 snprintf(priv->hw->wiphy->fw_version,
2204 sizeof(priv->hw->wiphy->fw_version),
2205 "%u.%u.%u.%u",
2206 IWL_UCODE_MAJOR(priv->ucode_ver),
2207 IWL_UCODE_MINOR(priv->ucode_ver),
2208 IWL_UCODE_API(priv->ucode_ver),
2209 IWL_UCODE_SERIAL(priv->ucode_ver));
2210
e1623446 2211 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 2212 priv->ucode_ver);
e1623446
TW
2213 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
2214 inst_size);
2215 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
2216 data_size);
2217 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
2218 init_size);
2219 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
2220 init_data_size);
2221 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
2222 boot_size);
b481de9c 2223
a0987a8d 2224
b481de9c 2225 /* Verify size of file vs. image size info in file's header */
cc0f555d 2226 if (ucode_raw->size != priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
2227 inst_size + data_size + init_size +
2228 init_data_size + boot_size) {
2229
cc0f555d
JS
2230 IWL_DEBUG_INFO(priv,
2231 "uCode file size %zd does not match expected size\n",
2232 ucode_raw->size);
90e759d1 2233 ret = -EINVAL;
b481de9c
ZY
2234 goto err_release;
2235 }
2236
2237 /* Verify that uCode images will fit in card's SRAM */
250bdd21 2238 if (inst_size > IWL39_MAX_INST_SIZE) {
e1623446 2239 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
2240 inst_size);
2241 ret = -EINVAL;
b481de9c
ZY
2242 goto err_release;
2243 }
2244
250bdd21 2245 if (data_size > IWL39_MAX_DATA_SIZE) {
e1623446 2246 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
2247 data_size);
2248 ret = -EINVAL;
b481de9c
ZY
2249 goto err_release;
2250 }
250bdd21 2251 if (init_size > IWL39_MAX_INST_SIZE) {
e1623446
TW
2252 IWL_DEBUG_INFO(priv,
2253 "uCode init instr len %d too large to fit in\n",
90e759d1
TW
2254 init_size);
2255 ret = -EINVAL;
b481de9c
ZY
2256 goto err_release;
2257 }
250bdd21 2258 if (init_data_size > IWL39_MAX_DATA_SIZE) {
e1623446
TW
2259 IWL_DEBUG_INFO(priv,
2260 "uCode init data len %d too large to fit in\n",
90e759d1
TW
2261 init_data_size);
2262 ret = -EINVAL;
b481de9c
ZY
2263 goto err_release;
2264 }
250bdd21 2265 if (boot_size > IWL39_MAX_BSM_SIZE) {
e1623446
TW
2266 IWL_DEBUG_INFO(priv,
2267 "uCode boot instr len %d too large to fit in\n",
90e759d1
TW
2268 boot_size);
2269 ret = -EINVAL;
b481de9c
ZY
2270 goto err_release;
2271 }
2272
2273 /* Allocate ucode buffers for card's bus-master loading ... */
2274
2275 /* Runtime instructions and 2 copies of data:
2276 * 1) unmodified from disk
2277 * 2) backup cache for save/restore during power-downs */
2278 priv->ucode_code.len = inst_size;
98c92211 2279 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
2280
2281 priv->ucode_data.len = data_size;
98c92211 2282 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
2283
2284 priv->ucode_data_backup.len = data_size;
98c92211 2285 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2286
90e759d1
TW
2287 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2288 !priv->ucode_data_backup.v_addr)
2289 goto err_pci_alloc;
b481de9c
ZY
2290
2291 /* Initialization instructions and data */
90e759d1
TW
2292 if (init_size && init_data_size) {
2293 priv->ucode_init.len = init_size;
98c92211 2294 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
2295
2296 priv->ucode_init_data.len = init_data_size;
98c92211 2297 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
2298
2299 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2300 goto err_pci_alloc;
2301 }
b481de9c
ZY
2302
2303 /* Bootstrap (instructions only, no data) */
90e759d1
TW
2304 if (boot_size) {
2305 priv->ucode_boot.len = boot_size;
98c92211 2306 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2307
90e759d1
TW
2308 if (!priv->ucode_boot.v_addr)
2309 goto err_pci_alloc;
2310 }
b481de9c
ZY
2311
2312 /* Copy images into buffers for card's bus-master reads ... */
2313
2314 /* Runtime instructions (first block of data in file) */
cc0f555d 2315 len = inst_size;
e1623446
TW
2316 IWL_DEBUG_INFO(priv,
2317 "Copying (but not loading) uCode instr len %zd\n", len);
b481de9c 2318 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
2319 src += len;
2320
e1623446 2321 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
2322 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2323
2324 /* Runtime data (2nd block)
bb8c093b 2325 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
cc0f555d 2326 len = data_size;
e1623446
TW
2327 IWL_DEBUG_INFO(priv,
2328 "Copying (but not loading) uCode data len %zd\n", len);
b481de9c
ZY
2329 memcpy(priv->ucode_data.v_addr, src, len);
2330 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 2331 src += len;
b481de9c
ZY
2332
2333 /* Initialization instructions (3rd block) */
2334 if (init_size) {
cc0f555d 2335 len = init_size;
e1623446
TW
2336 IWL_DEBUG_INFO(priv,
2337 "Copying (but not loading) init instr len %zd\n", len);
b481de9c 2338 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 2339 src += len;
b481de9c
ZY
2340 }
2341
2342 /* Initialization data (4th block) */
2343 if (init_data_size) {
cc0f555d 2344 len = init_data_size;
e1623446
TW
2345 IWL_DEBUG_INFO(priv,
2346 "Copying (but not loading) init data len %zd\n", len);
b481de9c 2347 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 2348 src += len;
b481de9c
ZY
2349 }
2350
2351 /* Bootstrap instructions (5th block) */
cc0f555d 2352 len = boot_size;
e1623446
TW
2353 IWL_DEBUG_INFO(priv,
2354 "Copying (but not loading) boot instr len %zd\n", len);
b481de9c
ZY
2355 memcpy(priv->ucode_boot.v_addr, src, len);
2356
2357 /* We have our copies now, allow OS release its copies */
2358 release_firmware(ucode_raw);
2359 return 0;
2360
2361 err_pci_alloc:
15b1687c 2362 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 2363 ret = -ENOMEM;
bb8c093b 2364 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
2365
2366 err_release:
2367 release_firmware(ucode_raw);
2368
2369 error:
90e759d1 2370 return ret;
b481de9c
ZY
2371}
2372
2373
2374/**
bb8c093b 2375 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
2376 *
2377 * Tell initialization uCode where to find runtime uCode.
2378 *
2379 * BSM registers initially contain pointers to initialization uCode.
2380 * We need to replace them to load runtime uCode inst and data,
2381 * and to save runtime data when powering down.
2382 */
4a8a4322 2383static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY
2384{
2385 dma_addr_t pinst;
2386 dma_addr_t pdata;
b481de9c
ZY
2387
2388 /* bits 31:0 for 3945 */
2389 pinst = priv->ucode_code.p_addr;
2390 pdata = priv->ucode_data_backup.p_addr;
2391
b481de9c 2392 /* Tell bootstrap uCode where to find image to load */
5d49f498
AK
2393 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2394 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2395 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
2396 priv->ucode_data.len);
2397
a96a27f9 2398 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 2399 * that all new ptr/size info is in place */
5d49f498 2400 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
2401 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
2402
e1623446 2403 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
b481de9c 2404
a8b50a0a 2405 return 0;
b481de9c
ZY
2406}
2407
2408/**
bb8c093b 2409 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
2410 *
2411 * Called after REPLY_ALIVE notification received from "initialize" uCode.
2412 *
b481de9c 2413 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 2414 */
4a8a4322 2415static void iwl3945_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY
2416{
2417 /* Check alive response for "valid" sign from uCode */
2418 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
2419 /* We had an error bringing up the hardware, so take it
2420 * all the way back down so we can try again */
e1623446 2421 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
b481de9c
ZY
2422 goto restart;
2423 }
2424
2425 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2426 * This is a paranoid check, because we would not have gotten the
2427 * "initialize" alive if code weren't properly loaded. */
bb8c093b 2428 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2429 /* Runtime instruction load was bad;
2430 * take it all the way back down so we can try again */
e1623446 2431 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
b481de9c
ZY
2432 goto restart;
2433 }
2434
2435 /* Send pointers to protocol/runtime uCode image ... init code will
2436 * load and launch runtime uCode, which will send us another "Alive"
2437 * notification. */
e1623446 2438 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
bb8c093b 2439 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
2440 /* Runtime instruction load won't happen;
2441 * take it all the way back down so we can try again */
e1623446 2442 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
b481de9c
ZY
2443 goto restart;
2444 }
2445 return;
2446
2447 restart:
2448 queue_work(priv->workqueue, &priv->restart);
2449}
2450
b481de9c 2451/**
bb8c093b 2452 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 2453 * from protocol/runtime uCode (initialization uCode's
bb8c093b 2454 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 2455 */
4a8a4322 2456static void iwl3945_alive_start(struct iwl_priv *priv)
b481de9c 2457{
b481de9c
ZY
2458 int thermal_spin = 0;
2459 u32 rfkill;
2460
e1623446 2461 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2462
2463 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2464 /* We had an error bringing up the hardware, so take it
2465 * all the way back down so we can try again */
e1623446 2466 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2467 goto restart;
2468 }
2469
2470 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2471 * This is a paranoid check, because we would not have gotten the
2472 * "runtime" alive if code weren't properly loaded. */
bb8c093b 2473 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2474 /* Runtime instruction load was bad;
2475 * take it all the way back down so we can try again */
e1623446 2476 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2477 goto restart;
2478 }
2479
5d49f498 2480 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
e1623446 2481 IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
b481de9c
ZY
2482
2483 if (rfkill & 0x1) {
2484 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 2485 /* if RFKILL is not on, then wait for thermal
b481de9c 2486 * sensor in adapter to kick in */
bb8c093b 2487 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
2488 thermal_spin++;
2489 udelay(10);
2490 }
2491
2492 if (thermal_spin)
e1623446 2493 IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
b481de9c
ZY
2494 thermal_spin * 10);
2495 } else
2496 set_bit(STATUS_RF_KILL_HW, &priv->status);
2497
9fbab516 2498 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
2499 set_bit(STATUS_ALIVE, &priv->status);
2500
b74e31a9
WYG
2501 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2502 /* Enable timer to monitor the driver queues */
2503 mod_timer(&priv->monitor_recover,
2504 jiffies +
2505 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2506 }
2507
775a6e27 2508 if (iwl_is_rfkill(priv))
b481de9c
ZY
2509 return;
2510
36d6825b 2511 ieee80211_wake_queues(priv->hw);
b481de9c 2512
470ab2dd 2513 priv->active_rate = IWL_RATES_MASK;
b481de9c 2514
4d6ccbf5 2515 iwl_power_update_mode(priv, true);
b481de9c 2516
8ccde88a 2517 if (iwl_is_associated(priv)) {
bb8c093b 2518 struct iwl3945_rxon_cmd *active_rxon =
8ccde88a 2519 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c 2520
8a9b9926 2521 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2522 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2523 } else {
2524 /* Initialize our rx_config data */
8ccde88a 2525 iwl_connection_init_rx_config(priv, priv->iw_mode);
b481de9c
ZY
2526 }
2527
9fbab516 2528 /* Configure Bluetooth device coexistence support */
65b52bde 2529 priv->cfg->ops->hcmd->send_bt_config(priv);
b481de9c
ZY
2530
2531 /* Configure the adapter for unassociated operation */
e0158e61 2532 iwlcore_commit_rxon(priv);
b481de9c 2533
b481de9c
ZY
2534 iwl3945_reg_txpower_periodic(priv);
2535
e932a609 2536 iwl_leds_init(priv);
fe00b5a5 2537
e1623446 2538 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2539 set_bit(STATUS_READY, &priv->status);
5a66926a 2540 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2541
b481de9c
ZY
2542 return;
2543
2544 restart:
2545 queue_work(priv->workqueue, &priv->restart);
2546}
2547
4a8a4322 2548static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2549
4a8a4322 2550static void __iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2551{
2552 unsigned long flags;
2553 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2554 struct ieee80211_conf *conf = NULL;
2555
e1623446 2556 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c
ZY
2557
2558 conf = ieee80211_get_hw_conf(priv->hw);
2559
2560 if (!exit_pending)
2561 set_bit(STATUS_EXIT_PENDING, &priv->status);
2562
7e246191
RC
2563 /* Station information will now be cleared in device */
2564 iwl_clear_ucode_stations(priv, true);
b481de9c
ZY
2565
2566 /* Unblock any waiting calls */
2567 wake_up_interruptible_all(&priv->wait_command_queue);
2568
b481de9c
ZY
2569 /* Wipe out the EXIT_PENDING status bit if we are not actually
2570 * exiting the module */
2571 if (!exit_pending)
2572 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2573
2574 /* stop and reset the on-board processor */
5d49f498 2575 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2576
2577 /* tell the device to stop sending interrupts */
0359facc 2578 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 2579 iwl_disable_interrupts(priv);
0359facc
MA
2580 spin_unlock_irqrestore(&priv->lock, flags);
2581 iwl_synchronize_irq(priv);
b481de9c
ZY
2582
2583 if (priv->mac80211_registered)
2584 ieee80211_stop_queues(priv->hw);
2585
bb8c093b 2586 /* If we have not previously called iwl3945_init() then
6da3a13e 2587 * clear all bits but the RF Kill bits and return */
775a6e27 2588 if (!iwl_is_init(priv)) {
b481de9c
ZY
2589 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2590 STATUS_RF_KILL_HW |
9788864e
RC
2591 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2592 STATUS_GEO_CONFIGURED |
ebef2008
AK
2593 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2594 STATUS_EXIT_PENDING;
b481de9c
ZY
2595 goto exit;
2596 }
2597
6da3a13e 2598 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2599 * bit and continue taking the NIC down. */
b481de9c
ZY
2600 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2601 STATUS_RF_KILL_HW |
9788864e
RC
2602 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2603 STATUS_GEO_CONFIGURED |
b481de9c 2604 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK
2605 STATUS_FW_ERROR |
2606 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2607 STATUS_EXIT_PENDING;
b481de9c 2608
bb8c093b
CH
2609 iwl3945_hw_txq_ctx_stop(priv);
2610 iwl3945_hw_rxq_stop(priv);
b481de9c 2611
309e731a
BC
2612 /* Power-down device's busmaster DMA clocks */
2613 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2614 udelay(5);
2615
4d2ccdb9
BC
2616 /* Stop the device, and put it in low power state */
2617 priv->cfg->ops->lib->apm_ops.stop(priv);
e9414b6b 2618
b481de9c 2619 exit:
3d24a9f7 2620 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2621
2622 if (priv->ibss_beacon)
2623 dev_kfree_skb(priv->ibss_beacon);
2624 priv->ibss_beacon = NULL;
2625
2626 /* clear out any free frames */
bb8c093b 2627 iwl3945_clear_free_frames(priv);
b481de9c
ZY
2628}
2629
4a8a4322 2630static void iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2631{
2632 mutex_lock(&priv->mutex);
bb8c093b 2633 __iwl3945_down(priv);
b481de9c 2634 mutex_unlock(&priv->mutex);
b24d22b1 2635
bb8c093b 2636 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
2637}
2638
2639#define MAX_HW_RESTARTS 5
2640
4a8a4322 2641static int __iwl3945_up(struct iwl_priv *priv)
b481de9c
ZY
2642{
2643 int rc, i;
2644
2645 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2646 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2647 return -EIO;
2648 }
2649
e903fbd4 2650 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2651 IWL_ERR(priv, "ucode not available for device bring up\n");
e903fbd4
RC
2652 return -EIO;
2653 }
2654
e655b9f0 2655 /* If platform's RF_KILL switch is NOT set to KILL */
5d49f498 2656 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY
2657 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2658 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2659 else {
2660 set_bit(STATUS_RF_KILL_HW, &priv->status);
6da3a13e
WYG
2661 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2662 return -ENODEV;
b481de9c 2663 }
80fcc9e2 2664
5d49f498 2665 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2666
bb8c093b 2667 rc = iwl3945_hw_nic_init(priv);
b481de9c 2668 if (rc) {
15b1687c 2669 IWL_ERR(priv, "Unable to int nic\n");
b481de9c
ZY
2670 return rc;
2671 }
2672
2673 /* make sure rfkill handshake bits are cleared */
5d49f498
AK
2674 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2675 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2676 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2677
2678 /* clear (again), then enable host interrupts */
5d49f498 2679 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
ed3b932e 2680 iwl_enable_interrupts(priv);
b481de9c
ZY
2681
2682 /* really make sure rfkill handshake bits are cleared */
5d49f498
AK
2683 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2684 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2685
2686 /* Copy original ucode data image from disk into backup cache.
2687 * This will be used to initialize the on-board processor's
2688 * data SRAM for a clean start when the runtime program first loads. */
2689 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2690 priv->ucode_data.len);
b481de9c 2691
e655b9f0
ZY
2692 /* We return success when we resume from suspend and rf_kill is on. */
2693 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
2694 return 0;
2695
b481de9c
ZY
2696 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2697
b481de9c
ZY
2698 /* load bootstrap state machine,
2699 * load bootstrap program into processor's memory,
2700 * prepare to load the "initialize" uCode */
75a9a926 2701 rc = priv->cfg->ops->lib->load_ucode(priv);
b481de9c
ZY
2702
2703 if (rc) {
15b1687c
WT
2704 IWL_ERR(priv,
2705 "Unable to set up bootstrap uCode: %d\n", rc);
b481de9c
ZY
2706 continue;
2707 }
2708
2709 /* start card; "initialize" will load runtime ucode */
bb8c093b 2710 iwl3945_nic_start(priv);
b481de9c 2711
e1623446 2712 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2713
2714 return 0;
2715 }
2716
2717 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 2718 __iwl3945_down(priv);
ebef2008 2719 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2720
2721 /* tried to restart and config the device for as long as our
2722 * patience could withstand */
15b1687c 2723 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2724 return -EIO;
2725}
2726
2727
2728/*****************************************************************************
2729 *
2730 * Workqueue callbacks
2731 *
2732 *****************************************************************************/
2733
bb8c093b 2734static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 2735{
4a8a4322
AK
2736 struct iwl_priv *priv =
2737 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2738
2739 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2740 return;
2741
2742 mutex_lock(&priv->mutex);
bb8c093b 2743 iwl3945_init_alive_start(priv);
b481de9c
ZY
2744 mutex_unlock(&priv->mutex);
2745}
2746
bb8c093b 2747static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 2748{
4a8a4322
AK
2749 struct iwl_priv *priv =
2750 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2751
2752 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2753 return;
2754
2755 mutex_lock(&priv->mutex);
bb8c093b 2756 iwl3945_alive_start(priv);
b481de9c
ZY
2757 mutex_unlock(&priv->mutex);
2758}
2759
743cdf1b
BC
2760/*
2761 * 3945 cannot interrupt driver when hardware rf kill switch toggles;
2762 * driver must poll CSR_GP_CNTRL_REG register for change. This register
2763 * *is* readable even when device has been SW_RESET into low power mode
2764 * (e.g. during RF KILL).
2765 */
2663516d
HS
2766static void iwl3945_rfkill_poll(struct work_struct *data)
2767{
2768 struct iwl_priv *priv =
ee525d13 2769 container_of(data, struct iwl_priv, _3945.rfkill_poll.work);
743cdf1b
BC
2770 bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &priv->status);
2771 bool new_rfkill = !(iwl_read32(priv, CSR_GP_CNTRL)
2772 & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
2663516d 2773
743cdf1b
BC
2774 if (new_rfkill != old_rfkill) {
2775 if (new_rfkill)
2776 set_bit(STATUS_RF_KILL_HW, &priv->status);
2777 else
2778 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2663516d 2779
743cdf1b
BC
2780 wiphy_rfkill_set_hw_state(priv->hw->wiphy, new_rfkill);
2781
2782 IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
2783 new_rfkill ? "disable radio" : "enable radio");
2784 }
2663516d 2785
743cdf1b
BC
2786 /* Keep this running, even if radio now enabled. This will be
2787 * cancelled in mac_start() if system decides to start again */
ee525d13 2788 queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
2663516d
HS
2789 round_jiffies_relative(2 * HZ));
2790
2791}
2792
b6e4c55a 2793void iwl3945_request_scan(struct iwl_priv *priv)
b481de9c 2794{
c2d79b48 2795 struct iwl_host_cmd cmd = {
b481de9c 2796 .id = REPLY_SCAN_CMD,
bb8c093b 2797 .len = sizeof(struct iwl3945_scan_cmd),
c2acea8e 2798 .flags = CMD_SIZE_HUGE,
b481de9c 2799 };
bb8c093b 2800 struct iwl3945_scan_cmd *scan;
b481de9c 2801 struct ieee80211_conf *conf = NULL;
1ecf9fc1 2802 u8 n_probes = 0;
8318d78a 2803 enum ieee80211_band band;
1ecf9fc1 2804 bool is_active = false;
b481de9c
ZY
2805
2806 conf = ieee80211_get_hw_conf(priv->hw);
2807
fbc9f97b
RC
2808 cancel_delayed_work(&priv->scan_check);
2809
775a6e27 2810 if (!iwl_is_ready(priv)) {
39aadf8c 2811 IWL_WARN(priv, "request scan called when driver not ready.\n");
b481de9c
ZY
2812 goto done;
2813 }
2814
a96a27f9 2815 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY
2816 * was given the chance to run... */
2817 if (!test_bit(STATUS_SCANNING, &priv->status))
2818 goto done;
2819
2820 /* This should never be called or scheduled if there is currently
2821 * a scan active in the hardware. */
2822 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
e1623446
TW
2823 IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests "
2824 "Ignoring second request.\n");
b481de9c
ZY
2825 goto done;
2826 }
2827
2828 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 2829 IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
b481de9c
ZY
2830 goto done;
2831 }
2832
2833 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
e1623446
TW
2834 IWL_DEBUG_HC(priv,
2835 "Scan request while abort pending. Queuing.\n");
b481de9c
ZY
2836 goto done;
2837 }
2838
775a6e27 2839 if (iwl_is_rfkill(priv)) {
e1623446 2840 IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
b481de9c
ZY
2841 goto done;
2842 }
2843
2844 if (!test_bit(STATUS_READY, &priv->status)) {
e1623446
TW
2845 IWL_DEBUG_HC(priv,
2846 "Scan request while uninitialized. Queuing.\n");
b481de9c
ZY
2847 goto done;
2848 }
2849
811ecc99
JB
2850 if (!priv->scan_cmd) {
2851 priv->scan_cmd = kmalloc(sizeof(struct iwl3945_scan_cmd) +
2852 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
2853 if (!priv->scan_cmd) {
4f4d4088 2854 IWL_DEBUG_SCAN(priv, "Fail to allocate scan memory\n");
b481de9c
ZY
2855 goto done;
2856 }
2857 }
811ecc99 2858 scan = priv->scan_cmd;
bb8c093b 2859 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
2860
2861 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
2862 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
2863
8ccde88a 2864 if (iwl_is_associated(priv)) {
b481de9c
ZY
2865 u16 interval = 0;
2866 u32 extra;
2867 u32 suspend_time = 100;
2868 u32 scan_suspend_time = 100;
2869 unsigned long flags;
2870
e1623446 2871 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
b481de9c
ZY
2872
2873 spin_lock_irqsave(&priv->lock, flags);
2874 interval = priv->beacon_int;
2875 spin_unlock_irqrestore(&priv->lock, flags);
2876
2877 scan->suspend_time = 0;
15e869d8 2878 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
2879 if (!interval)
2880 interval = suspend_time;
2881 /*
2882 * suspend time format:
2883 * 0-19: beacon interval in usec (time before exec.)
2884 * 20-23: 0
2885 * 24-31: number of beacons (suspend between channels)
2886 */
2887
2888 extra = (suspend_time / interval) << 24;
2889 scan_suspend_time = 0xFF0FFFFF &
2890 (extra | ((suspend_time % interval) * 1024));
2891
2892 scan->suspend_time = cpu_to_le32(scan_suspend_time);
e1623446 2893 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
b481de9c
ZY
2894 scan_suspend_time, interval);
2895 }
2896
4f4d4088
WYG
2897 if (priv->is_internal_short_scan) {
2898 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
2899 } else if (priv->scan_request->n_ssids) {
1ecf9fc1
JB
2900 int i, p = 0;
2901 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
2902 for (i = 0; i < priv->scan_request->n_ssids; i++) {
2903 /* always does wildcard anyway */
2904 if (!priv->scan_request->ssids[i].ssid_len)
2905 continue;
2906 scan->direct_scan[p].id = WLAN_EID_SSID;
2907 scan->direct_scan[p].len =
2908 priv->scan_request->ssids[i].ssid_len;
2909 memcpy(scan->direct_scan[p].ssid,
2910 priv->scan_request->ssids[i].ssid,
2911 priv->scan_request->ssids[i].ssid_len);
2912 n_probes++;
2913 p++;
2914 }
2915 is_active = true;
f9340520 2916 } else
1ecf9fc1 2917 IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
b481de9c
ZY
2918
2919 /* We don't build a direct scan probe request; the uCode will do
2920 * that based on the direct_mask added to each channel entry */
b481de9c 2921 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
3832ec9d 2922 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY
2923 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2924
2925 /* flags + rate selection */
2926
00700ee0
JB
2927 switch (priv->scan_band) {
2928 case IEEE80211_BAND_2GHZ:
b481de9c
ZY
2929 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2930 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
2931 scan->good_CRC_th = 0;
8318d78a 2932 band = IEEE80211_BAND_2GHZ;
00700ee0
JB
2933 break;
2934 case IEEE80211_BAND_5GHZ:
b481de9c 2935 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
b097ad29
JB
2936 /*
2937 * If active scaning is requested but a certain channel
2938 * is marked passive, we can do active scanning if we
2939 * detect transmissions.
2940 */
96ff5641
JB
2941 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
2942 IWL_GOOD_CRC_TH_DISABLED;
8318d78a 2943 band = IEEE80211_BAND_5GHZ;
00700ee0
JB
2944 break;
2945 default:
2946 IWL_WARN(priv, "Invalid scan band\n");
b481de9c
ZY
2947 goto done;
2948 }
2949
4f4d4088
WYG
2950 if (!priv->is_internal_short_scan) {
2951 scan->tx_cmd.len = cpu_to_le16(
1ecf9fc1
JB
2952 iwl_fill_probe_req(priv,
2953 (struct ieee80211_mgmt *)scan->data,
2954 priv->scan_request->ie,
2955 priv->scan_request->ie_len,
2956 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
4f4d4088
WYG
2957 } else {
2958 scan->tx_cmd.len = cpu_to_le16(
2959 iwl_fill_probe_req(priv,
2960 (struct ieee80211_mgmt *)scan->data,
2961 NULL, 0,
2962 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
2963 }
b481de9c
ZY
2964 /* select Rx antennas */
2965 scan->flags |= iwl3945_get_antenna_flags(priv);
2966
f9340520 2967 scan->channel_count =
1ecf9fc1 2968 iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
f9340520 2969 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 2970
14b54336 2971 if (scan->channel_count == 0) {
e1623446 2972 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
14b54336
RC
2973 goto done;
2974 }
2975
b481de9c 2976 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 2977 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
2978 cmd.data = scan;
2979 scan->len = cpu_to_le16(cmd.len);
2980
2981 set_bit(STATUS_SCAN_HW, &priv->status);
4f4d4088 2982 if (iwl_send_cmd_sync(priv, &cmd))
b481de9c
ZY
2983 goto done;
2984
2985 queue_delayed_work(priv->workqueue, &priv->scan_check,
2986 IWL_SCAN_CHECK_WATCHDOG);
2987
b481de9c
ZY
2988 return;
2989
2990 done:
2420ebc1
MA
2991 /* can not perform scan make sure we clear scanning
2992 * bits from status so next scan request can be performed.
2993 * if we dont clear scanning status bit here all next scan
2994 * will fail
2995 */
2996 clear_bit(STATUS_SCAN_HW, &priv->status);
2997 clear_bit(STATUS_SCANNING, &priv->status);
2998
01ebd063 2999 /* inform mac80211 scan aborted */
b481de9c 3000 queue_work(priv->workqueue, &priv->scan_completed);
b481de9c
ZY
3001}
3002
bb8c093b 3003static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 3004{
4a8a4322 3005 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
3006
3007 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3008 return;
3009
19cc1087
JB
3010 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3011 mutex_lock(&priv->mutex);
3012 priv->vif = NULL;
3013 priv->is_open = 0;
3014 mutex_unlock(&priv->mutex);
3015 iwl3945_down(priv);
3016 ieee80211_restart_hw(priv->hw);
3017 } else {
3018 iwl3945_down(priv);
80676518
JB
3019
3020 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3021 return;
3022
3023 mutex_lock(&priv->mutex);
3024 __iwl3945_up(priv);
3025 mutex_unlock(&priv->mutex);
19cc1087 3026 }
b481de9c
ZY
3027}
3028
bb8c093b 3029static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 3030{
4a8a4322
AK
3031 struct iwl_priv *priv =
3032 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
3033
3034 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3035 return;
3036
3037 mutex_lock(&priv->mutex);
bb8c093b 3038 iwl3945_rx_replenish(priv);
b481de9c
ZY
3039 mutex_unlock(&priv->mutex);
3040}
3041
5bbe233b 3042void iwl3945_post_associate(struct iwl_priv *priv)
b481de9c 3043{
b481de9c
ZY
3044 int rc = 0;
3045 struct ieee80211_conf *conf = NULL;
3046
05c914fe 3047 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 3048 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
3049 return;
3050 }
3051
3052
e1623446 3053 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
8ccde88a 3054 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
3055
3056 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3057 return;
3058
322a9811 3059 if (!priv->vif || !priv->is_open)
6ef89d0a 3060 return;
322a9811 3061
af0053d6 3062 iwl_scan_cancel_timeout(priv, 200);
15e869d8 3063
b481de9c
ZY
3064 conf = ieee80211_get_hw_conf(priv->hw);
3065
8ccde88a 3066 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3067 iwlcore_commit_rxon(priv);
b481de9c 3068
28afaf91 3069 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3070 iwl_setup_rxon_timing(priv);
518099a8 3071 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
3072 sizeof(priv->rxon_timing), &priv->rxon_timing);
3073 if (rc)
39aadf8c 3074 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3075 "Attempting to continue.\n");
3076
8ccde88a 3077 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3078
8ccde88a 3079 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3080
e1623446 3081 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
3082 priv->assoc_id, priv->beacon_int);
3083
3084 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3085 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3086 else
8ccde88a 3087 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3088
8ccde88a 3089 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c 3090 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3091 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3092 else
8ccde88a 3093 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3094
05c914fe 3095 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3096 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY
3097
3098 }
3099
e0158e61 3100 iwlcore_commit_rxon(priv);
b481de9c
ZY
3101
3102 switch (priv->iw_mode) {
05c914fe 3103 case NL80211_IFTYPE_STATION:
bb8c093b 3104 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
3105 break;
3106
05c914fe 3107 case NL80211_IFTYPE_ADHOC:
b481de9c 3108
ce546fd2 3109 priv->assoc_id = 1;
fe6b23dd 3110 iwl_add_local_station(priv, priv->bssid, false);
b481de9c 3111 iwl3945_sync_sta(priv, IWL_STA_ID,
fe6b23dd
RC
3112 (priv->band == IEEE80211_BAND_5GHZ) ?
3113 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
b481de9c 3114 CMD_ASYNC);
bb8c093b 3115 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
fe6b23dd 3116
bb8c093b 3117 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3118
3119 break;
3120
3121 default:
15b1687c 3122 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 3123 __func__, priv->iw_mode);
b481de9c
ZY
3124 break;
3125 }
cd56d331
AK
3126}
3127
b481de9c
ZY
3128/*****************************************************************************
3129 *
3130 * mac80211 entry point functions
3131 *
3132 *****************************************************************************/
3133
5a66926a
ZY
3134#define UCODE_READY_TIMEOUT (2 * HZ)
3135
bb8c093b 3136static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 3137{
4a8a4322 3138 struct iwl_priv *priv = hw->priv;
5a66926a 3139 int ret;
b481de9c 3140
e1623446 3141 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
3142
3143 /* we should be verifying the device is ready to be opened */
3144 mutex_lock(&priv->mutex);
3145
5a66926a
ZY
3146 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
3147 * ucode filename and max sizes are card-specific. */
3148
3149 if (!priv->ucode_code.len) {
3150 ret = iwl3945_read_ucode(priv);
3151 if (ret) {
15b1687c 3152 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a
ZY
3153 mutex_unlock(&priv->mutex);
3154 goto out_release_irq;
3155 }
3156 }
b481de9c 3157
e655b9f0 3158 ret = __iwl3945_up(priv);
b481de9c
ZY
3159
3160 mutex_unlock(&priv->mutex);
5a66926a 3161
e655b9f0
ZY
3162 if (ret)
3163 goto out_release_irq;
3164
e1623446 3165 IWL_DEBUG_INFO(priv, "Start UP work.\n");
e655b9f0 3166
5a66926a
ZY
3167 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
3168 * mac80211 will not be run successfully. */
3169 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3170 test_bit(STATUS_READY, &priv->status),
3171 UCODE_READY_TIMEOUT);
3172 if (!ret) {
3173 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c
WT
3174 IWL_ERR(priv,
3175 "Wait for START_ALIVE timeout after %dms.\n",
3176 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5a66926a
ZY
3177 ret = -ETIMEDOUT;
3178 goto out_release_irq;
3179 }
3180 }
3181
2663516d
HS
3182 /* ucode is running and will send rfkill notifications,
3183 * no need to poll the killswitch state anymore */
ee525d13 3184 cancel_delayed_work(&priv->_3945.rfkill_poll);
2663516d 3185
e932a609
JB
3186 iwl_led_start(priv);
3187
e655b9f0 3188 priv->is_open = 1;
e1623446 3189 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3190 return 0;
5a66926a
ZY
3191
3192out_release_irq:
e655b9f0 3193 priv->is_open = 0;
e1623446 3194 IWL_DEBUG_MAC80211(priv, "leave - failed\n");
5a66926a 3195 return ret;
b481de9c
ZY
3196}
3197
bb8c093b 3198static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 3199{
4a8a4322 3200 struct iwl_priv *priv = hw->priv;
b481de9c 3201
e1623446 3202 IWL_DEBUG_MAC80211(priv, "enter\n");
6ef89d0a 3203
e655b9f0 3204 if (!priv->is_open) {
e1623446 3205 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
e655b9f0
ZY
3206 return;
3207 }
3208
b481de9c 3209 priv->is_open = 0;
5a66926a 3210
775a6e27 3211 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
3212 /* stop mac, cancel any scan request and clear
3213 * RXON_FILTER_ASSOC_MSK BIT
3214 */
5a66926a 3215 mutex_lock(&priv->mutex);
af0053d6 3216 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3217 mutex_unlock(&priv->mutex);
fde3571f
MA
3218 }
3219
5a66926a
ZY
3220 iwl3945_down(priv);
3221
3222 flush_workqueue(priv->workqueue);
2663516d
HS
3223
3224 /* start polling the killswitch state again */
ee525d13 3225 queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
2663516d 3226 round_jiffies_relative(2 * HZ));
6ef89d0a 3227
e1623446 3228 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
3229}
3230
e039fa4a 3231static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3232{
4a8a4322 3233 struct iwl_priv *priv = hw->priv;
b481de9c 3234
e1623446 3235 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3236
e1623446 3237 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3238 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3239
e039fa4a 3240 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY
3241 dev_kfree_skb_any(skb);
3242
e1623446 3243 IWL_DEBUG_MAC80211(priv, "leave\n");
637f8837 3244 return NETDEV_TX_OK;
b481de9c
ZY
3245}
3246
60690a6a 3247void iwl3945_config_ap(struct iwl_priv *priv)
b481de9c
ZY
3248{
3249 int rc = 0;
3250
d986bcd1 3251 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
3252 return;
3253
3254 /* The following should be done only at AP bring up */
8ccde88a 3255 if (!(iwl_is_associated(priv))) {
b481de9c
ZY
3256
3257 /* RXON - unassoc (to set timing command) */
8ccde88a 3258 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3259 iwlcore_commit_rxon(priv);
b481de9c
ZY
3260
3261 /* RXON Timing */
28afaf91 3262 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3263 iwl_setup_rxon_timing(priv);
518099a8
SO
3264 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3265 sizeof(priv->rxon_timing),
3266 &priv->rxon_timing);
b481de9c 3267 if (rc)
39aadf8c 3268 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3269 "Attempting to continue.\n");
3270
3271 /* FIXME: what should be the assoc_id for AP? */
8ccde88a 3272 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3273 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3274 priv->staging_rxon.flags |=
b481de9c
ZY
3275 RXON_FLG_SHORT_PREAMBLE_MSK;
3276 else
8ccde88a 3277 priv->staging_rxon.flags &=
b481de9c
ZY
3278 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3279
8ccde88a 3280 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c
ZY
3281 if (priv->assoc_capability &
3282 WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3283 priv->staging_rxon.flags |=
b481de9c
ZY
3284 RXON_FLG_SHORT_SLOT_MSK;
3285 else
8ccde88a 3286 priv->staging_rxon.flags &=
b481de9c
ZY
3287 ~RXON_FLG_SHORT_SLOT_MSK;
3288
05c914fe 3289 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3290 priv->staging_rxon.flags &=
b481de9c
ZY
3291 ~RXON_FLG_SHORT_SLOT_MSK;
3292 }
3293 /* restore RXON assoc */
8ccde88a 3294 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3295 iwlcore_commit_rxon(priv);
fe6b23dd 3296 iwl_add_local_station(priv, iwl_bcast_addr, false);
556f8db7 3297 }
bb8c093b 3298 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3299
3300 /* FIXME - we need to add code here to detect a totally new
3301 * configuration, reset the AP, unassoc, rxon timing, assoc,
3302 * clear sta table, add BCAST sta... */
3303}
3304
bb8c093b 3305static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
3306 struct ieee80211_vif *vif,
3307 struct ieee80211_sta *sta,
3308 struct ieee80211_key_conf *key)
b481de9c 3309{
4a8a4322 3310 struct iwl_priv *priv = hw->priv;
dc822b5d 3311 const u8 *addr;
6e21f15c
AK
3312 int ret = 0;
3313 u8 sta_id = IWL_INVALID_STATION;
3314 u8 static_key;
b481de9c 3315
e1623446 3316 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3317
df878d8f 3318 if (iwl3945_mod_params.sw_crypto) {
e1623446 3319 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
3320 return -EOPNOTSUPP;
3321 }
3322
42986796 3323 addr = sta ? sta->addr : iwl_bcast_addr;
6e21f15c
AK
3324 static_key = !iwl_is_associated(priv);
3325
3326 if (!static_key) {
c587de0b 3327 sta_id = iwl_find_station(priv, addr);
6e21f15c 3328 if (sta_id == IWL_INVALID_STATION) {
12514396 3329 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
6e21f15c
AK
3330 addr);
3331 return -EINVAL;
3332 }
b481de9c
ZY
3333 }
3334
3335 mutex_lock(&priv->mutex);
af0053d6 3336 iwl_scan_cancel_timeout(priv, 100);
15e869d8 3337
b481de9c 3338 switch (cmd) {
6e21f15c
AK
3339 case SET_KEY:
3340 if (static_key)
3341 ret = iwl3945_set_static_key(priv, key);
3342 else
3343 ret = iwl3945_set_dynamic_key(priv, key, sta_id);
3344 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
3345 break;
3346 case DISABLE_KEY:
6e21f15c
AK
3347 if (static_key)
3348 ret = iwl3945_remove_static_key(priv);
3349 else
3350 ret = iwl3945_clear_sta_key_info(priv, sta_id);
3351 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
3352 break;
3353 default:
42986796 3354 ret = -EINVAL;
b481de9c
ZY
3355 }
3356
72e15d71 3357 mutex_unlock(&priv->mutex);
e1623446 3358 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3359
42986796 3360 return ret;
b481de9c
ZY
3361}
3362
fe6b23dd
RC
3363static int iwl3945_mac_sta_add(struct ieee80211_hw *hw,
3364 struct ieee80211_vif *vif,
3365 struct ieee80211_sta *sta)
3366{
3367 struct iwl_priv *priv = hw->priv;
3368 int ret;
3369 bool is_ap = priv->iw_mode == NL80211_IFTYPE_STATION;
3370 u8 sta_id;
3371
3372 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3373 sta->addr);
3374
3375 ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
3376 &sta_id);
3377 if (ret) {
3378 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3379 sta->addr, ret);
3380 /* Should we return success if return code is EEXIST ? */
3381 return ret;
3382 }
3383
3384 /* Initialize rate scaling */
91dd6c27 3385 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC
3386 sta->addr);
3387 iwl3945_rs_rate_init(priv, sta, sta_id);
3388
3389 return 0;
3390
3391
3392
3393 return ret;
3394}
b481de9c
ZY
3395/*****************************************************************************
3396 *
3397 * sysfs attributes
3398 *
3399 *****************************************************************************/
3400
d08853a3 3401#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3402
3403/*
3404 * The following adds a new attribute to the sysfs representation
3405 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3406 * used for controlling the debug level.
3407 *
3408 * See the level definitions in iwl for details.
a562a9dd 3409 *
3d816c77
RC
3410 * The debug_level being managed using sysfs below is a per device debug
3411 * level that is used instead of the global debug level if it (the per
3412 * device debug level) is set.
b481de9c 3413 */
40b8ec0b
SO
3414static ssize_t show_debug_level(struct device *d,
3415 struct device_attribute *attr, char *buf)
b481de9c 3416{
3d816c77
RC
3417 struct iwl_priv *priv = dev_get_drvdata(d);
3418 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3419}
40b8ec0b
SO
3420static ssize_t store_debug_level(struct device *d,
3421 struct device_attribute *attr,
b481de9c
ZY
3422 const char *buf, size_t count)
3423{
928841b1 3424 struct iwl_priv *priv = dev_get_drvdata(d);
40b8ec0b
SO
3425 unsigned long val;
3426 int ret;
b481de9c 3427
40b8ec0b
SO
3428 ret = strict_strtoul(buf, 0, &val);
3429 if (ret)
978785a3 3430 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 3431 else {
3d816c77 3432 priv->debug_level = val;
20594eb0
WYG
3433 if (iwl_alloc_traffic_mem(priv))
3434 IWL_ERR(priv,
3435 "Not enough memory to generate traffic log\n");
3436 }
b481de9c
ZY
3437 return strnlen(buf, count);
3438}
3439
40b8ec0b
SO
3440static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3441 show_debug_level, store_debug_level);
b481de9c 3442
d08853a3 3443#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3444
b481de9c
ZY
3445static ssize_t show_temperature(struct device *d,
3446 struct device_attribute *attr, char *buf)
3447{
928841b1 3448 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3449
775a6e27 3450 if (!iwl_is_alive(priv))
b481de9c
ZY
3451 return -EAGAIN;
3452
bb8c093b 3453 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
3454}
3455
3456static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3457
b481de9c
ZY
3458static ssize_t show_tx_power(struct device *d,
3459 struct device_attribute *attr, char *buf)
3460{
928841b1 3461 struct iwl_priv *priv = dev_get_drvdata(d);
62ea9c5b 3462 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3463}
3464
3465static ssize_t store_tx_power(struct device *d,
3466 struct device_attribute *attr,
3467 const char *buf, size_t count)
3468{
928841b1 3469 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3470 char *p = (char *)buf;
3471 u32 val;
3472
3473 val = simple_strtoul(p, &p, 10);
3474 if (p == buf)
978785a3 3475 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
b481de9c 3476 else
bb8c093b 3477 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
3478
3479 return count;
3480}
3481
3482static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3483
3484static ssize_t show_flags(struct device *d,
3485 struct device_attribute *attr, char *buf)
3486{
928841b1 3487 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3488
8ccde88a 3489 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
b481de9c
ZY
3490}
3491
3492static ssize_t store_flags(struct device *d,
3493 struct device_attribute *attr,
3494 const char *buf, size_t count)
3495{
928841b1 3496 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3497 u32 flags = simple_strtoul(buf, NULL, 0);
3498
3499 mutex_lock(&priv->mutex);
8ccde88a 3500 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
b481de9c 3501 /* Cancel any currently running scans... */
af0053d6 3502 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3503 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3504 else {
e1623446 3505 IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
b481de9c 3506 flags);
8ccde88a 3507 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 3508 iwlcore_commit_rxon(priv);
b481de9c
ZY
3509 }
3510 }
3511 mutex_unlock(&priv->mutex);
3512
3513 return count;
3514}
3515
3516static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3517
3518static ssize_t show_filter_flags(struct device *d,
3519 struct device_attribute *attr, char *buf)
3520{
928841b1 3521 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3522
3523 return sprintf(buf, "0x%04X\n",
8ccde88a 3524 le32_to_cpu(priv->active_rxon.filter_flags));
b481de9c
ZY
3525}
3526
3527static ssize_t store_filter_flags(struct device *d,
3528 struct device_attribute *attr,
3529 const char *buf, size_t count)
3530{
928841b1 3531 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3532 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3533
3534 mutex_lock(&priv->mutex);
8ccde88a 3535 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
b481de9c 3536 /* Cancel any currently running scans... */
af0053d6 3537 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3538 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3539 else {
e1623446 3540 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c 3541 "0x%04X\n", filter_flags);
8ccde88a 3542 priv->staging_rxon.filter_flags =
b481de9c 3543 cpu_to_le32(filter_flags);
e0158e61 3544 iwlcore_commit_rxon(priv);
b481de9c
ZY
3545 }
3546 }
3547 mutex_unlock(&priv->mutex);
3548
3549 return count;
3550}
3551
3552static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3553 store_filter_flags);
3554
b481de9c
ZY
3555static ssize_t show_measurement(struct device *d,
3556 struct device_attribute *attr, char *buf)
3557{
4a8a4322 3558 struct iwl_priv *priv = dev_get_drvdata(d);
600c0e11 3559 struct iwl_spectrum_notification measure_report;
b481de9c 3560 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 3561 u8 *data = (u8 *)&measure_report;
b481de9c
ZY
3562 unsigned long flags;
3563
3564 spin_lock_irqsave(&priv->lock, flags);
3565 if (!(priv->measurement_status & MEASUREMENT_READY)) {
3566 spin_unlock_irqrestore(&priv->lock, flags);
3567 return 0;
3568 }
3569 memcpy(&measure_report, &priv->measure_report, size);
3570 priv->measurement_status = 0;
3571 spin_unlock_irqrestore(&priv->lock, flags);
3572
3573 while (size && (PAGE_SIZE - len)) {
3574 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3575 PAGE_SIZE - len, 1);
3576 len = strlen(buf);
3577 if (PAGE_SIZE - len)
3578 buf[len++] = '\n';
3579
3580 ofs += 16;
3581 size -= min(size, 16U);
3582 }
3583
3584 return len;
3585}
3586
3587static ssize_t store_measurement(struct device *d,
3588 struct device_attribute *attr,
3589 const char *buf, size_t count)
3590{
4a8a4322 3591 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3592 struct ieee80211_measurement_params params = {
8ccde88a 3593 .channel = le16_to_cpu(priv->active_rxon.channel),
e99f168c 3594 .start_time = cpu_to_le64(priv->_3945.last_tsf),
b481de9c
ZY
3595 .duration = cpu_to_le16(1),
3596 };
3597 u8 type = IWL_MEASURE_BASIC;
3598 u8 buffer[32];
3599 u8 channel;
3600
3601 if (count) {
3602 char *p = buffer;
3603 strncpy(buffer, buf, min(sizeof(buffer), count));
3604 channel = simple_strtoul(p, NULL, 0);
3605 if (channel)
3606 params.channel = channel;
3607
3608 p = buffer;
3609 while (*p && *p != ' ')
3610 p++;
3611 if (*p)
3612 type = simple_strtoul(p + 1, NULL, 0);
3613 }
3614
e1623446 3615 IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
b481de9c 3616 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 3617 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
3618
3619 return count;
3620}
3621
3622static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
3623 show_measurement, store_measurement);
b481de9c 3624
b481de9c
ZY
3625static ssize_t store_retry_rate(struct device *d,
3626 struct device_attribute *attr,
3627 const char *buf, size_t count)
3628{
4a8a4322 3629 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3630
3631 priv->retry_rate = simple_strtoul(buf, NULL, 0);
3632 if (priv->retry_rate <= 0)
3633 priv->retry_rate = 1;
3634
3635 return count;
3636}
3637
3638static ssize_t show_retry_rate(struct device *d,
3639 struct device_attribute *attr, char *buf)
3640{
4a8a4322 3641 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3642 return sprintf(buf, "%d", priv->retry_rate);
3643}
3644
3645static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
3646 store_retry_rate);
3647
d25aabb0 3648
b481de9c
ZY
3649static ssize_t show_channels(struct device *d,
3650 struct device_attribute *attr, char *buf)
3651{
8318d78a
JB
3652 /* all this shit doesn't belong into sysfs anyway */
3653 return 0;
b481de9c
ZY
3654}
3655
3656static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
3657
b481de9c
ZY
3658static ssize_t show_antenna(struct device *d,
3659 struct device_attribute *attr, char *buf)
3660{
4a8a4322 3661 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3662
775a6e27 3663 if (!iwl_is_alive(priv))
b481de9c
ZY
3664 return -EAGAIN;
3665
7e4bca5e 3666 return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
b481de9c
ZY
3667}
3668
3669static ssize_t store_antenna(struct device *d,
3670 struct device_attribute *attr,
3671 const char *buf, size_t count)
3672{
7530f85f 3673 struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
b481de9c 3674 int ant;
b481de9c
ZY
3675
3676 if (count == 0)
3677 return 0;
3678
3679 if (sscanf(buf, "%1i", &ant) != 1) {
e1623446 3680 IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
b481de9c
ZY
3681 return count;
3682 }
3683
3684 if ((ant >= 0) && (ant <= 2)) {
e1623446 3685 IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
7e4bca5e 3686 iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
b481de9c 3687 } else
e1623446 3688 IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
b481de9c
ZY
3689
3690
3691 return count;
3692}
3693
3694static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
3695
3696static ssize_t show_status(struct device *d,
3697 struct device_attribute *attr, char *buf)
3698{
928841b1 3699 struct iwl_priv *priv = dev_get_drvdata(d);
775a6e27 3700 if (!iwl_is_alive(priv))
b481de9c
ZY
3701 return -EAGAIN;
3702 return sprintf(buf, "0x%08x\n", (int)priv->status);
3703}
3704
3705static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
3706
3707static ssize_t dump_error_log(struct device *d,
3708 struct device_attribute *attr,
3709 const char *buf, size_t count)
3710{
928841b1 3711 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3712 char *p = (char *)buf;
3713
3714 if (p[0] == '1')
928841b1 3715 iwl3945_dump_nic_error_log(priv);
b481de9c
ZY
3716
3717 return strnlen(buf, count);
3718}
3719
3720static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
3721
b481de9c
ZY
3722/*****************************************************************************
3723 *
a96a27f9 3724 * driver setup and tear down
b481de9c
ZY
3725 *
3726 *****************************************************************************/
3727
4a8a4322 3728static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3729{
d21050c7 3730 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3731
3732 init_waitqueue_head(&priv->wait_command_queue);
3733
bb8c093b
CH
3734 INIT_WORK(&priv->restart, iwl3945_bg_restart);
3735 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
bb8c093b 3736 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH
3737 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
3738 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
ee525d13 3739 INIT_DELAYED_WORK(&priv->_3945.rfkill_poll, iwl3945_rfkill_poll);
77fecfb8 3740 INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed);
77fecfb8
SO
3741 INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan);
3742 INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check);
bb8c093b
CH
3743
3744 iwl3945_hw_setup_deferred_work(priv);
b481de9c 3745
b74e31a9
WYG
3746 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3747 init_timer(&priv->monitor_recover);
3748 priv->monitor_recover.data = (unsigned long)priv;
3749 priv->monitor_recover.function =
3750 priv->cfg->ops->lib->recover_from_tx_stall;
3751 }
3752
b481de9c 3753 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 3754 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
3755}
3756
4a8a4322 3757static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3758{
bb8c093b 3759 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 3760
e47eb6ad 3761 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3762 cancel_delayed_work(&priv->scan_check);
3763 cancel_delayed_work(&priv->alive_start);
b481de9c 3764 cancel_work_sync(&priv->beacon_update);
b74e31a9
WYG
3765 if (priv->cfg->ops->lib->recover_from_tx_stall)
3766 del_timer_sync(&priv->monitor_recover);
b481de9c
ZY
3767}
3768
bb8c093b 3769static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
3770 &dev_attr_antenna.attr,
3771 &dev_attr_channels.attr,
3772 &dev_attr_dump_errors.attr,
b481de9c
ZY
3773 &dev_attr_flags.attr,
3774 &dev_attr_filter_flags.attr,
b481de9c 3775 &dev_attr_measurement.attr,
b481de9c 3776 &dev_attr_retry_rate.attr,
b481de9c
ZY
3777 &dev_attr_status.attr,
3778 &dev_attr_temperature.attr,
b481de9c 3779 &dev_attr_tx_power.attr,
d08853a3 3780#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b
SO
3781 &dev_attr_debug_level.attr,
3782#endif
b481de9c
ZY
3783 NULL
3784};
3785
bb8c093b 3786static struct attribute_group iwl3945_attribute_group = {
b481de9c 3787 .name = NULL, /* put in device directory */
bb8c093b 3788 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
3789};
3790
bb8c093b
CH
3791static struct ieee80211_ops iwl3945_hw_ops = {
3792 .tx = iwl3945_mac_tx,
3793 .start = iwl3945_mac_start,
3794 .stop = iwl3945_mac_stop,
cbb6ab94 3795 .add_interface = iwl_mac_add_interface,
d8052319 3796 .remove_interface = iwl_mac_remove_interface,
4808368d 3797 .config = iwl_mac_config,
8ccde88a 3798 .configure_filter = iwl_configure_filter,
bb8c093b 3799 .set_key = iwl3945_mac_set_key,
488829f1 3800 .conf_tx = iwl_mac_conf_tx,
bd564261 3801 .reset_tsf = iwl_mac_reset_tsf,
5bbe233b 3802 .bss_info_changed = iwl_bss_info_changed,
fe6b23dd
RC
3803 .hw_scan = iwl_mac_hw_scan,
3804 .sta_add = iwl3945_mac_sta_add,
3805 .sta_remove = iwl_mac_sta_remove,
b481de9c
ZY
3806};
3807
e52119c5 3808static int iwl3945_init_drv(struct iwl_priv *priv)
90a30a02
KA
3809{
3810 int ret;
e6148917 3811 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
90a30a02
KA
3812
3813 priv->retry_rate = 1;
3814 priv->ibss_beacon = NULL;
3815
90a30a02
KA
3816 spin_lock_init(&priv->sta_lock);
3817 spin_lock_init(&priv->hcmd_lock);
3818
3819 INIT_LIST_HEAD(&priv->free_frames);
3820
3821 mutex_init(&priv->mutex);
d2dfe6df 3822 mutex_init(&priv->sync_cmd_mutex);
90a30a02 3823
90a30a02
KA
3824 priv->ieee_channels = NULL;
3825 priv->ieee_rates = NULL;
3826 priv->band = IEEE80211_BAND_2GHZ;
3827
3828 priv->iw_mode = NL80211_IFTYPE_STATION;
a13d276f 3829 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
90a30a02 3830
62ea9c5b 3831 priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
90a30a02 3832
e6148917
SO
3833 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3834 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
3835 eeprom->version);
3836 ret = -EINVAL;
3837 goto err;
3838 }
3839 ret = iwl_init_channel_map(priv);
90a30a02
KA
3840 if (ret) {
3841 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3842 goto err;
3843 }
3844
e6148917
SO
3845 /* Set up txpower settings in driver for all channels */
3846 if (iwl3945_txpower_set_from_eeprom(priv)) {
3847 ret = -EIO;
3848 goto err_free_channel_map;
3849 }
3850
534166de 3851 ret = iwlcore_init_geos(priv);
90a30a02
KA
3852 if (ret) {
3853 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3854 goto err_free_channel_map;
3855 }
534166de
SO
3856 iwl3945_init_hw_rates(priv, priv->ieee_rates);
3857
2a4ddaab
AK
3858 return 0;
3859
3860err_free_channel_map:
3861 iwl_free_channel_map(priv);
3862err:
3863 return ret;
3864}
3865
3866static int iwl3945_setup_mac(struct iwl_priv *priv)
3867{
3868 int ret;
3869 struct ieee80211_hw *hw = priv->hw;
3870
3871 hw->rate_control_algorithm = "iwl-3945-rs";
3872 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
3873
3874 /* Tell mac80211 our characteristics */
3875 hw->flags = IEEE80211_HW_SIGNAL_DBM |
bc45a670
RC
3876 IEEE80211_HW_SPECTRUM_MGMT;
3877
3878 if (!priv->cfg->broken_powersave)
3879 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3880 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2a4ddaab
AK
3881
3882 hw->wiphy->interface_modes =
3883 BIT(NL80211_IFTYPE_STATION) |
3884 BIT(NL80211_IFTYPE_ADHOC);
3885
f6c8f152 3886 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 3887 WIPHY_FLAG_DISABLE_BEACON_HINTS;
37184244 3888
1ecf9fc1
JB
3889 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3890 /* we create the 802.11 header and a zero-length SSID element */
3891 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
d60cc91a 3892
2a4ddaab
AK
3893 /* Default value; 4 EDCA QOS priorities */
3894 hw->queues = 4;
3895
534166de
SO
3896 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3897 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3898 &priv->bands[IEEE80211_BAND_2GHZ];
2a4ddaab 3899
534166de
SO
3900 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3901 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3902 &priv->bands[IEEE80211_BAND_5GHZ];
90a30a02 3903
2a4ddaab
AK
3904 ret = ieee80211_register_hw(priv->hw);
3905 if (ret) {
3906 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3907 return ret;
3908 }
3909 priv->mac80211_registered = 1;
90a30a02 3910
2a4ddaab 3911 return 0;
90a30a02
KA
3912}
3913
bb8c093b 3914static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3915{
3916 int err = 0;
4a8a4322 3917 struct iwl_priv *priv;
b481de9c 3918 struct ieee80211_hw *hw;
c0f20d91 3919 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
e6148917 3920 struct iwl3945_eeprom *eeprom;
0359facc 3921 unsigned long flags;
b481de9c 3922
cee53ddb
KA
3923 /***********************
3924 * 1. Allocating HW data
3925 * ********************/
3926
b481de9c
ZY
3927 /* mac80211 allocates memory for this device instance, including
3928 * space for this driver's private structure */
90a30a02 3929 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
b481de9c 3930 if (hw == NULL) {
a3139c59 3931 printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
b481de9c
ZY
3932 err = -ENOMEM;
3933 goto out;
3934 }
b481de9c 3935 priv = hw->priv;
90a30a02 3936 SET_IEEE80211_DEV(hw, &pdev->dev);
6440adb5 3937
90a30a02
KA
3938 /*
3939 * Disabling hardware scan means that mac80211 will perform scans
3940 * "the hard way", rather than using device's scan.
3941 */
df878d8f 3942 if (iwl3945_mod_params.disable_hw_scan) {
e1623446 3943 IWL_DEBUG_INFO(priv, "Disabling hw_scan\n");
40b8ec0b
SO
3944 iwl3945_hw_ops.hw_scan = NULL;
3945 }
3946
90a30a02 3947
e1623446 3948 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
90a30a02
KA
3949 priv->cfg = cfg;
3950 priv->pci_dev = pdev;
40cefda9 3951 priv->inta_mask = CSR_INI_SET_MASK;
cee53ddb 3952
d08853a3 3953#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3954 atomic_set(&priv->restrict_refcnt, 0);
3955#endif
20594eb0
WYG
3956 if (iwl_alloc_traffic_mem(priv))
3957 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3958
cee53ddb
KA
3959 /***************************
3960 * 2. Initializing PCI bus
3961 * *************************/
b481de9c
ZY
3962 if (pci_enable_device(pdev)) {
3963 err = -ENODEV;
3964 goto out_ieee80211_free_hw;
3965 }
3966
3967 pci_set_master(pdev);
3968
284901a9 3969 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 3970 if (!err)
284901a9 3971 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 3972 if (err) {
978785a3 3973 IWL_WARN(priv, "No suitable DMA available.\n");
b481de9c
ZY
3974 goto out_pci_disable_device;
3975 }
3976
3977 pci_set_drvdata(pdev, priv);
3978 err = pci_request_regions(pdev, DRV_NAME);
3979 if (err)
3980 goto out_pci_disable_device;
6440adb5 3981
cee53ddb
KA
3982 /***********************
3983 * 3. Read REV Register
3984 * ********************/
b481de9c
ZY
3985 priv->hw_base = pci_iomap(pdev, 0, 0);
3986 if (!priv->hw_base) {
3987 err = -ENODEV;
3988 goto out_pci_release_regions;
3989 }
3990
e1623446 3991 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
b481de9c 3992 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3993 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
b481de9c 3994
cee53ddb
KA
3995 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3996 * PCI Tx retries from interfering with C3 CPU state */
3997 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 3998
731a29b7 3999 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA
4000 * we should init now
4001 */
4002 spin_lock_init(&priv->reg_lock);
731a29b7 4003 spin_lock_init(&priv->lock);
a8b50a0a 4004
4843b5a7
RC
4005 /*
4006 * stop and reset the on-board processor just in case it is in a
4007 * strange state ... like being left stranded by a primary kernel
4008 * and this is now the kdump kernel trying to start up
4009 */
4010 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4011
cee53ddb
KA
4012 /***********************
4013 * 4. Read EEPROM
4014 * ********************/
90a30a02 4015
cee53ddb 4016 /* Read the EEPROM */
e6148917 4017 err = iwl_eeprom_init(priv);
cee53ddb 4018 if (err) {
15b1687c 4019 IWL_ERR(priv, "Unable to init EEPROM\n");
c8f16138 4020 goto out_iounmap;
cee53ddb
KA
4021 }
4022 /* MAC Address location in EEPROM same for 3945/4965 */
e6148917
SO
4023 eeprom = (struct iwl3945_eeprom *)priv->eeprom;
4024 memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN);
e1623446 4025 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
cee53ddb 4026 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 4027
cee53ddb
KA
4028 /***********************
4029 * 5. Setup HW Constants
4030 * ********************/
b481de9c 4031 /* Device-specific setup */
3832ec9d 4032 if (iwl3945_hw_set_hw_params(priv)) {
15b1687c 4033 IWL_ERR(priv, "failed to set hw settings\n");
c8f16138 4034 goto out_eeprom_free;
b481de9c
ZY
4035 }
4036
cee53ddb
KA
4037 /***********************
4038 * 6. Setup priv
4039 * ********************/
cee53ddb 4040
90a30a02 4041 err = iwl3945_init_drv(priv);
b481de9c 4042 if (err) {
90a30a02 4043 IWL_ERR(priv, "initializing driver failed\n");
c8f16138 4044 goto out_unset_hw_params;
b481de9c
ZY
4045 }
4046
978785a3
TW
4047 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
4048 priv->cfg->name);
cee53ddb 4049
cee53ddb 4050 /***********************
09f9bf79 4051 * 7. Setup Services
cee53ddb
KA
4052 * ********************/
4053
4054 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4055 iwl_disable_interrupts(priv);
cee53ddb
KA
4056 spin_unlock_irqrestore(&priv->lock, flags);
4057
2663516d
HS
4058 pci_enable_msi(priv->pci_dev);
4059
ef850d7c
MA
4060 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4061 IRQF_SHARED, DRV_NAME, priv);
2663516d
HS
4062 if (err) {
4063 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4064 goto out_disable_msi;
4065 }
4066
cee53ddb 4067 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 4068 if (err) {
15b1687c 4069 IWL_ERR(priv, "failed to create sysfs device attributes\n");
90a30a02 4070 goto out_release_irq;
849e0dce 4071 }
849e0dce 4072
8ccde88a
SO
4073 iwl_set_rxon_channel(priv,
4074 &priv->bands[IEEE80211_BAND_2GHZ].channels[5]);
cee53ddb
KA
4075 iwl3945_setup_deferred_work(priv);
4076 iwl3945_setup_rx_handlers(priv);
008a9e3e 4077 iwl_power_initialize(priv);
cee53ddb 4078
cee53ddb 4079 /*********************************
09f9bf79 4080 * 8. Setup and Register mac80211
cee53ddb
KA
4081 * *******************************/
4082
2a4ddaab 4083 iwl_enable_interrupts(priv);
b481de9c 4084
2a4ddaab
AK
4085 err = iwl3945_setup_mac(priv);
4086 if (err)
4087 goto out_remove_sysfs;
cee53ddb 4088
a75fbe8d
AK
4089 err = iwl_dbgfs_register(priv, DRV_NAME);
4090 if (err)
4091 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
4092
2663516d 4093 /* Start monitoring the killswitch */
ee525d13 4094 queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
2663516d
HS
4095 2 * HZ);
4096
b481de9c
ZY
4097 return 0;
4098
cee53ddb 4099 out_remove_sysfs:
c8f16138
RC
4100 destroy_workqueue(priv->workqueue);
4101 priv->workqueue = NULL;
cee53ddb 4102 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4103 out_release_irq:
2663516d 4104 free_irq(priv->pci_dev->irq, priv);
2663516d
HS
4105 out_disable_msi:
4106 pci_disable_msi(priv->pci_dev);
c8f16138
RC
4107 iwlcore_free_geos(priv);
4108 iwl_free_channel_map(priv);
4109 out_unset_hw_params:
4110 iwl3945_unset_hw_params(priv);
4111 out_eeprom_free:
4112 iwl_eeprom_free(priv);
b481de9c
ZY
4113 out_iounmap:
4114 pci_iounmap(pdev, priv->hw_base);
4115 out_pci_release_regions:
4116 pci_release_regions(pdev);
4117 out_pci_disable_device:
b481de9c 4118 pci_set_drvdata(pdev, NULL);
623d563e 4119 pci_disable_device(pdev);
b481de9c 4120 out_ieee80211_free_hw:
20594eb0 4121 iwl_free_traffic_mem(priv);
d7c76f4c 4122 ieee80211_free_hw(priv->hw);
b481de9c
ZY
4123 out:
4124 return err;
4125}
4126
c83dbf68 4127static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 4128{
4a8a4322 4129 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4130 unsigned long flags;
b481de9c
ZY
4131
4132 if (!priv)
4133 return;
4134
e1623446 4135 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4136
a75fbe8d
AK
4137 iwl_dbgfs_unregister(priv);
4138
b481de9c 4139 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 4140
d552bfb6
KA
4141 if (priv->mac80211_registered) {
4142 ieee80211_unregister_hw(priv->hw);
4143 priv->mac80211_registered = 0;
4144 } else {
4145 iwl3945_down(priv);
4146 }
b481de9c 4147
c166b25a
BC
4148 /*
4149 * Make sure device is reset to low power before unloading driver.
4150 * This may be redundant with iwl_down(), but there are paths to
4151 * run iwl_down() without calling apm_ops.stop(), and there are
4152 * paths to avoid running iwl_down() at all before leaving driver.
4153 * This (inexpensive) call *makes sure* device is reset.
4154 */
4155 priv->cfg->ops->lib->apm_ops.stop(priv);
4156
0359facc
MA
4157 /* make sure we flush any pending irq or
4158 * tasklet for the driver
4159 */
4160 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4161 iwl_disable_interrupts(priv);
0359facc
MA
4162 spin_unlock_irqrestore(&priv->lock, flags);
4163
4164 iwl_synchronize_irq(priv);
4165
bb8c093b 4166 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4167
ee525d13 4168 cancel_delayed_work_sync(&priv->_3945.rfkill_poll);
2663516d 4169
bb8c093b 4170 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
4171
4172 if (priv->rxq.bd)
df833b1d 4173 iwl3945_rx_queue_free(priv, &priv->rxq);
bb8c093b 4174 iwl3945_hw_txq_ctx_free(priv);
b481de9c 4175
3832ec9d 4176 iwl3945_unset_hw_params(priv);
b481de9c 4177
6ef89d0a
MA
4178 /*netif_stop_queue(dev); */
4179 flush_workqueue(priv->workqueue);
4180
bb8c093b 4181 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
4182 * priv->workqueue... so we can't take down the workqueue
4183 * until now... */
4184 destroy_workqueue(priv->workqueue);
4185 priv->workqueue = NULL;
20594eb0 4186 iwl_free_traffic_mem(priv);
b481de9c 4187
2663516d
HS
4188 free_irq(pdev->irq, priv);
4189 pci_disable_msi(pdev);
4190
b481de9c
ZY
4191 pci_iounmap(pdev, priv->hw_base);
4192 pci_release_regions(pdev);
4193 pci_disable_device(pdev);
4194 pci_set_drvdata(pdev, NULL);
4195
e6148917 4196 iwl_free_channel_map(priv);
534166de 4197 iwlcore_free_geos(priv);
811ecc99 4198 kfree(priv->scan_cmd);
b481de9c
ZY
4199 if (priv->ibss_beacon)
4200 dev_kfree_skb(priv->ibss_beacon);
4201
4202 ieee80211_free_hw(priv->hw);
4203}
4204
b481de9c
ZY
4205
4206/*****************************************************************************
4207 *
4208 * driver and module entry point
4209 *
4210 *****************************************************************************/
4211
bb8c093b 4212static struct pci_driver iwl3945_driver = {
b481de9c 4213 .name = DRV_NAME,
bb8c093b
CH
4214 .id_table = iwl3945_hw_card_ids,
4215 .probe = iwl3945_pci_probe,
4216 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 4217#ifdef CONFIG_PM
6da3a13e
WYG
4218 .suspend = iwl_pci_suspend,
4219 .resume = iwl_pci_resume,
b481de9c
ZY
4220#endif
4221};
4222
bb8c093b 4223static int __init iwl3945_init(void)
b481de9c
ZY
4224{
4225
4226 int ret;
4227 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4228 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC
4229
4230 ret = iwl3945_rate_control_register();
4231 if (ret) {
a3139c59
SO
4232 printk(KERN_ERR DRV_NAME
4233 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
4234 return ret;
4235 }
4236
bb8c093b 4237 ret = pci_register_driver(&iwl3945_driver);
b481de9c 4238 if (ret) {
a3139c59 4239 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 4240 goto error_register;
b481de9c 4241 }
b481de9c
ZY
4242
4243 return ret;
897e1cf2 4244
897e1cf2
RC
4245error_register:
4246 iwl3945_rate_control_unregister();
4247 return ret;
b481de9c
ZY
4248}
4249
bb8c093b 4250static void __exit iwl3945_exit(void)
b481de9c 4251{
bb8c093b 4252 pci_unregister_driver(&iwl3945_driver);
897e1cf2 4253 iwl3945_rate_control_unregister();
b481de9c
ZY
4254}
4255
a0987a8d 4256MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 4257
4e30cb69 4258module_param_named(antenna, iwl3945_mod_params.antenna, int, S_IRUGO);
b481de9c 4259MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4e30cb69 4260module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, S_IRUGO);
9c74d9fb
SO
4261MODULE_PARM_DESC(swcrypto,
4262 "using software crypto (default 1 [software])\n");
a562a9dd 4263#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4264module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
b481de9c 4265MODULE_PARM_DESC(debug, "debug output mask");
a562a9dd 4266#endif
4e30cb69
WYG
4267module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan,
4268 int, S_IRUGO);
b481de9c 4269MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4e30cb69 4270module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, S_IRUGO);
af48d048
SO
4271MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
4272
bb8c093b
CH
4273module_exit(iwl3945_exit);
4274module_init(iwl3945_init);