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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
b481de9c ZY |
35 | #include <linux/dma-mapping.h> |
36 | #include <linux/delay.h> | |
d43c36dc | 37 | #include <linux/sched.h> |
b481de9c ZY |
38 | #include <linux/skbuff.h> |
39 | #include <linux/netdevice.h> | |
40 | #include <linux/wireless.h> | |
41 | #include <linux/firmware.h> | |
b481de9c ZY |
42 | #include <linux/etherdevice.h> |
43 | #include <linux/if_arp.h> | |
44 | ||
45 | #include <net/ieee80211_radiotap.h> | |
46 | #include <net/mac80211.h> | |
47 | ||
48 | #include <asm/div64.h> | |
49 | ||
a3139c59 SO |
50 | #define DRV_NAME "iwl3945" |
51 | ||
dbb6654c WT |
52 | #include "iwl-fh.h" |
53 | #include "iwl-3945-fh.h" | |
600c0e11 | 54 | #include "iwl-commands.h" |
17f841cd | 55 | #include "iwl-sta.h" |
b481de9c | 56 | #include "iwl-3945.h" |
5747d47f | 57 | #include "iwl-core.h" |
4a6547c7 | 58 | #include "iwl-helpers.h" |
d20b3c65 | 59 | #include "iwl-dev.h" |
81963d68 | 60 | #include "iwl-spectrum.h" |
b481de9c | 61 | |
b481de9c ZY |
62 | /* |
63 | * module name, copyright, version, etc. | |
b481de9c ZY |
64 | */ |
65 | ||
66 | #define DRV_DESCRIPTION \ | |
67 | "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux" | |
68 | ||
d08853a3 | 69 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
70 | #define VD "d" |
71 | #else | |
72 | #define VD | |
73 | #endif | |
74 | ||
81963d68 RC |
75 | /* |
76 | * add "s" to indicate spectrum measurement included. | |
77 | * we add it here to be consistent with previous releases in which | |
78 | * this was configurable. | |
79 | */ | |
80 | #define DRV_VERSION IWLWIFI_VERSION VD "s" | |
1f447808 | 81 | #define DRV_COPYRIGHT "Copyright(c) 2003-2010 Intel Corporation" |
a7b75207 | 82 | #define DRV_AUTHOR "<ilw@linux.intel.com>" |
b481de9c ZY |
83 | |
84 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
85 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 86 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c ZY |
87 | MODULE_LICENSE("GPL"); |
88 | ||
df878d8f KA |
89 | /* module parameters */ |
90 | struct iwl_mod_params iwl3945_mod_params = { | |
9c74d9fb | 91 | .sw_crypto = 1, |
af48d048 | 92 | .restart_fw = 1, |
df878d8f KA |
93 | /* the rest are 0 by default */ |
94 | }; | |
95 | ||
7e4bca5e SO |
96 | /** |
97 | * iwl3945_get_antenna_flags - Get antenna flags for RXON command | |
98 | * @priv: eeprom and antenna fields are used to determine antenna flags | |
99 | * | |
100 | * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed | |
101 | * iwl3945_mod_params.antenna specifies the antenna diversity mode: | |
102 | * | |
103 | * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself | |
104 | * IWL_ANTENNA_MAIN - Force MAIN antenna | |
105 | * IWL_ANTENNA_AUX - Force AUX antenna | |
106 | */ | |
107 | __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv) | |
108 | { | |
109 | struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; | |
110 | ||
111 | switch (iwl3945_mod_params.antenna) { | |
112 | case IWL_ANTENNA_DIVERSITY: | |
113 | return 0; | |
114 | ||
115 | case IWL_ANTENNA_MAIN: | |
116 | if (eeprom->antenna_switch_type) | |
117 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
118 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
119 | ||
120 | case IWL_ANTENNA_AUX: | |
121 | if (eeprom->antenna_switch_type) | |
122 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
123 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
124 | } | |
125 | ||
126 | /* bad antenna selector value */ | |
127 | IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", | |
128 | iwl3945_mod_params.antenna); | |
129 | ||
130 | return 0; /* "diversity" is default if error */ | |
131 | } | |
132 | ||
6e21f15c | 133 | static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv, |
b481de9c ZY |
134 | struct ieee80211_key_conf *keyconf, |
135 | u8 sta_id) | |
136 | { | |
137 | unsigned long flags; | |
138 | __le16 key_flags = 0; | |
6e21f15c AK |
139 | int ret; |
140 | ||
141 | key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK); | |
142 | key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
143 | ||
144 | if (sta_id == priv->hw_params.bcast_sta_id) | |
145 | key_flags |= STA_KEY_MULTICAST_MSK; | |
146 | ||
147 | keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
148 | keyconf->hw_key_idx = keyconf->keyidx; | |
149 | key_flags &= ~STA_KEY_FLG_INVALID; | |
b481de9c | 150 | |
b481de9c | 151 | spin_lock_irqsave(&priv->sta_lock, flags); |
c587de0b TW |
152 | priv->stations[sta_id].keyinfo.alg = keyconf->alg; |
153 | priv->stations[sta_id].keyinfo.keylen = keyconf->keylen; | |
154 | memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, | |
b481de9c ZY |
155 | keyconf->keylen); |
156 | ||
c587de0b | 157 | memcpy(priv->stations[sta_id].sta.key.key, keyconf->key, |
b481de9c | 158 | keyconf->keylen); |
6e21f15c | 159 | |
c587de0b | 160 | if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK) |
6e21f15c | 161 | == STA_KEY_FLG_NO_ENC) |
c587de0b | 162 | priv->stations[sta_id].sta.key.key_offset = |
6e21f15c AK |
163 | iwl_get_free_ucode_key_index(priv); |
164 | /* else, we are overriding an existing key => no need to allocated room | |
165 | * in uCode. */ | |
166 | ||
c587de0b | 167 | WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, |
6e21f15c AK |
168 | "no space for a new key"); |
169 | ||
c587de0b TW |
170 | priv->stations[sta_id].sta.key.key_flags = key_flags; |
171 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
172 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c | 173 | |
6e21f15c AK |
174 | IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n"); |
175 | ||
c587de0b | 176 | ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC); |
6e21f15c | 177 | |
b481de9c ZY |
178 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
179 | ||
6e21f15c AK |
180 | return ret; |
181 | } | |
182 | ||
183 | static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv, | |
184 | struct ieee80211_key_conf *keyconf, | |
185 | u8 sta_id) | |
186 | { | |
187 | return -EOPNOTSUPP; | |
188 | } | |
189 | ||
190 | static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv, | |
191 | struct ieee80211_key_conf *keyconf, | |
192 | u8 sta_id) | |
193 | { | |
194 | return -EOPNOTSUPP; | |
b481de9c ZY |
195 | } |
196 | ||
4a8a4322 | 197 | static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id) |
b481de9c ZY |
198 | { |
199 | unsigned long flags; | |
200 | ||
201 | spin_lock_irqsave(&priv->sta_lock, flags); | |
c587de0b TW |
202 | memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key)); |
203 | memset(&priv->stations[sta_id].sta.key, 0, | |
4c897253 | 204 | sizeof(struct iwl4965_keyinfo)); |
c587de0b TW |
205 | priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC; |
206 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
207 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
b481de9c ZY |
208 | spin_unlock_irqrestore(&priv->sta_lock, flags); |
209 | ||
e1623446 | 210 | IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n"); |
c587de0b | 211 | iwl_send_add_sta(priv, &priv->stations[sta_id].sta, 0); |
b481de9c ZY |
212 | return 0; |
213 | } | |
214 | ||
fa11d525 | 215 | static int iwl3945_set_dynamic_key(struct iwl_priv *priv, |
6e21f15c AK |
216 | struct ieee80211_key_conf *keyconf, u8 sta_id) |
217 | { | |
218 | int ret = 0; | |
219 | ||
220 | keyconf->hw_key_idx = HW_KEY_DYNAMIC; | |
221 | ||
222 | switch (keyconf->alg) { | |
223 | case ALG_CCMP: | |
224 | ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id); | |
225 | break; | |
226 | case ALG_TKIP: | |
227 | ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id); | |
228 | break; | |
229 | case ALG_WEP: | |
230 | ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id); | |
231 | break; | |
232 | default: | |
1e680233 | 233 | IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg); |
6e21f15c AK |
234 | ret = -EINVAL; |
235 | } | |
236 | ||
237 | IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n", | |
238 | keyconf->alg, keyconf->keylen, keyconf->keyidx, | |
239 | sta_id, ret); | |
240 | ||
241 | return ret; | |
242 | } | |
243 | ||
244 | static int iwl3945_remove_static_key(struct iwl_priv *priv) | |
245 | { | |
246 | int ret = -EOPNOTSUPP; | |
247 | ||
248 | return ret; | |
249 | } | |
250 | ||
251 | static int iwl3945_set_static_key(struct iwl_priv *priv, | |
252 | struct ieee80211_key_conf *key) | |
253 | { | |
254 | if (key->alg == ALG_WEP) | |
255 | return -EOPNOTSUPP; | |
256 | ||
257 | IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg); | |
258 | return -EINVAL; | |
259 | } | |
260 | ||
4a8a4322 | 261 | static void iwl3945_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
262 | { |
263 | struct list_head *element; | |
264 | ||
e1623446 | 265 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
266 | priv->frames_count); |
267 | ||
268 | while (!list_empty(&priv->free_frames)) { | |
269 | element = priv->free_frames.next; | |
270 | list_del(element); | |
bb8c093b | 271 | kfree(list_entry(element, struct iwl3945_frame, list)); |
b481de9c ZY |
272 | priv->frames_count--; |
273 | } | |
274 | ||
275 | if (priv->frames_count) { | |
39aadf8c | 276 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
277 | priv->frames_count); |
278 | priv->frames_count = 0; | |
279 | } | |
280 | } | |
281 | ||
4a8a4322 | 282 | static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv) |
b481de9c | 283 | { |
bb8c093b | 284 | struct iwl3945_frame *frame; |
b481de9c ZY |
285 | struct list_head *element; |
286 | if (list_empty(&priv->free_frames)) { | |
287 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
288 | if (!frame) { | |
15b1687c | 289 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
290 | return NULL; |
291 | } | |
292 | ||
293 | priv->frames_count++; | |
294 | return frame; | |
295 | } | |
296 | ||
297 | element = priv->free_frames.next; | |
298 | list_del(element); | |
bb8c093b | 299 | return list_entry(element, struct iwl3945_frame, list); |
b481de9c ZY |
300 | } |
301 | ||
4a8a4322 | 302 | static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame) |
b481de9c ZY |
303 | { |
304 | memset(frame, 0, sizeof(*frame)); | |
305 | list_add(&frame->list, &priv->free_frames); | |
306 | } | |
307 | ||
4a8a4322 | 308 | unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv, |
b481de9c | 309 | struct ieee80211_hdr *hdr, |
73ec1cc2 | 310 | int left) |
b481de9c ZY |
311 | { |
312 | ||
8ccde88a | 313 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
314 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
315 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
316 | return 0; |
317 | ||
318 | if (priv->ibss_beacon->len > left) | |
319 | return 0; | |
320 | ||
321 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
322 | ||
323 | return priv->ibss_beacon->len; | |
324 | } | |
325 | ||
4a8a4322 | 326 | static int iwl3945_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 327 | { |
bb8c093b | 328 | struct iwl3945_frame *frame; |
b481de9c ZY |
329 | unsigned int frame_size; |
330 | int rc; | |
331 | u8 rate; | |
332 | ||
bb8c093b | 333 | frame = iwl3945_get_free_frame(priv); |
b481de9c ZY |
334 | |
335 | if (!frame) { | |
15b1687c | 336 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
337 | "command.\n"); |
338 | return -ENOMEM; | |
339 | } | |
340 | ||
8ccde88a | 341 | rate = iwl_rate_get_lowest_plcp(priv); |
b481de9c | 342 | |
bb8c093b | 343 | frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 344 | |
518099a8 | 345 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
346 | &frame->u.cmd[0]); |
347 | ||
bb8c093b | 348 | iwl3945_free_frame(priv, frame); |
b481de9c ZY |
349 | |
350 | return rc; | |
351 | } | |
352 | ||
4a8a4322 | 353 | static void iwl3945_unset_hw_params(struct iwl_priv *priv) |
b481de9c | 354 | { |
ee525d13 | 355 | if (priv->_3945.shared_virt) |
f36d04ab SG |
356 | dma_free_coherent(&priv->pci_dev->dev, |
357 | sizeof(struct iwl3945_shared), | |
ee525d13 JB |
358 | priv->_3945.shared_virt, |
359 | priv->_3945.shared_phys); | |
b481de9c ZY |
360 | } |
361 | ||
4a8a4322 | 362 | static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv, |
e039fa4a | 363 | struct ieee80211_tx_info *info, |
c2acea8e | 364 | struct iwl_device_cmd *cmd, |
b481de9c | 365 | struct sk_buff *skb_frag, |
6e21f15c | 366 | int sta_id) |
b481de9c | 367 | { |
9744c91f | 368 | struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
c587de0b | 369 | struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo; |
b481de9c ZY |
370 | |
371 | switch (keyinfo->alg) { | |
372 | case ALG_CCMP: | |
9744c91f AK |
373 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; |
374 | memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen); | |
e1623446 | 375 | IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n"); |
b481de9c ZY |
376 | break; |
377 | ||
378 | case ALG_TKIP: | |
b481de9c ZY |
379 | break; |
380 | ||
381 | case ALG_WEP: | |
9744c91f | 382 | tx_cmd->sec_ctl = TX_CMD_SEC_WEP | |
e039fa4a | 383 | (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT; |
b481de9c ZY |
384 | |
385 | if (keyinfo->keylen == 13) | |
9744c91f | 386 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; |
b481de9c | 387 | |
9744c91f | 388 | memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen); |
b481de9c | 389 | |
e1623446 | 390 | IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption " |
e039fa4a | 391 | "with key %d\n", info->control.hw_key->hw_key_idx); |
b481de9c ZY |
392 | break; |
393 | ||
b481de9c | 394 | default: |
978785a3 | 395 | IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg); |
b481de9c ZY |
396 | break; |
397 | } | |
398 | } | |
399 | ||
400 | /* | |
401 | * handle build REPLY_TX command notification. | |
402 | */ | |
4a8a4322 | 403 | static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv, |
c2acea8e | 404 | struct iwl_device_cmd *cmd, |
e039fa4a | 405 | struct ieee80211_tx_info *info, |
e52119c5 | 406 | struct ieee80211_hdr *hdr, u8 std_id) |
b481de9c | 407 | { |
9744c91f AK |
408 | struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
409 | __le32 tx_flags = tx_cmd->tx_flags; | |
fd7c8a40 | 410 | __le16 fc = hdr->frame_control; |
b481de9c | 411 | |
9744c91f | 412 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
e039fa4a | 413 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
b481de9c | 414 | tx_flags |= TX_CMD_FLG_ACK_MSK; |
fd7c8a40 | 415 | if (ieee80211_is_mgmt(fc)) |
b481de9c | 416 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
fd7c8a40 | 417 | if (ieee80211_is_probe_resp(fc) && |
b481de9c ZY |
418 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) |
419 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
420 | } else { | |
421 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
422 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
423 | } | |
424 | ||
9744c91f | 425 | tx_cmd->sta_id = std_id; |
8b7b1e05 | 426 | if (ieee80211_has_morefrags(fc)) |
b481de9c ZY |
427 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; |
428 | ||
fd7c8a40 HH |
429 | if (ieee80211_is_data_qos(fc)) { |
430 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
9744c91f | 431 | tx_cmd->tid_tspec = qc[0] & 0xf; |
b481de9c | 432 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 433 | } else { |
b481de9c | 434 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; |
54dbb525 | 435 | } |
b481de9c | 436 | |
37dc70fe | 437 | priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags); |
b481de9c ZY |
438 | |
439 | if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK)) | |
440 | tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
441 | ||
442 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
fd7c8a40 HH |
443 | if (ieee80211_is_mgmt(fc)) { |
444 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
9744c91f | 445 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); |
b481de9c | 446 | else |
9744c91f | 447 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); |
ab53d8af | 448 | } else { |
9744c91f | 449 | tx_cmd->timeout.pm_frame_timeout = 0; |
ab53d8af | 450 | } |
b481de9c | 451 | |
9744c91f AK |
452 | tx_cmd->driver_txop = 0; |
453 | tx_cmd->tx_flags = tx_flags; | |
454 | tx_cmd->next_frame_len = 0; | |
b481de9c ZY |
455 | } |
456 | ||
b481de9c ZY |
457 | /* |
458 | * start REPLY_TX command process | |
459 | */ | |
4a8a4322 | 460 | static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) |
b481de9c ZY |
461 | { |
462 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
e039fa4a | 463 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
9744c91f | 464 | struct iwl3945_tx_cmd *tx_cmd; |
188cf6c7 | 465 | struct iwl_tx_queue *txq = NULL; |
d20b3c65 | 466 | struct iwl_queue *q = NULL; |
c2acea8e JB |
467 | struct iwl_device_cmd *out_cmd; |
468 | struct iwl_cmd_meta *out_meta; | |
b481de9c ZY |
469 | dma_addr_t phys_addr; |
470 | dma_addr_t txcmd_phys; | |
e52119c5 | 471 | int txq_id = skb_get_queue_mapping(skb); |
df833b1d | 472 | u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */ |
54dbb525 TW |
473 | u8 id; |
474 | u8 unicast; | |
b481de9c | 475 | u8 sta_id; |
54dbb525 | 476 | u8 tid = 0; |
b481de9c | 477 | u16 seq_number = 0; |
fd7c8a40 | 478 | __le16 fc; |
b481de9c | 479 | u8 wait_write_ptr = 0; |
54dbb525 | 480 | u8 *qc = NULL; |
b481de9c | 481 | unsigned long flags; |
b481de9c ZY |
482 | |
483 | spin_lock_irqsave(&priv->lock, flags); | |
775a6e27 | 484 | if (iwl_is_rfkill(priv)) { |
e1623446 | 485 | IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n"); |
b481de9c ZY |
486 | goto drop_unlock; |
487 | } | |
488 | ||
e039fa4a | 489 | if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) { |
15b1687c | 490 | IWL_ERR(priv, "ERROR: No TX rate available.\n"); |
b481de9c ZY |
491 | goto drop_unlock; |
492 | } | |
493 | ||
494 | unicast = !is_multicast_ether_addr(hdr->addr1); | |
495 | id = 0; | |
496 | ||
fd7c8a40 | 497 | fc = hdr->frame_control; |
b481de9c | 498 | |
d08853a3 | 499 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c | 500 | if (ieee80211_is_auth(fc)) |
e1623446 | 501 | IWL_DEBUG_TX(priv, "Sending AUTH frame\n"); |
fd7c8a40 | 502 | else if (ieee80211_is_assoc_req(fc)) |
e1623446 | 503 | IWL_DEBUG_TX(priv, "Sending ASSOC frame\n"); |
fd7c8a40 | 504 | else if (ieee80211_is_reassoc_req(fc)) |
e1623446 | 505 | IWL_DEBUG_TX(priv, "Sending REASSOC frame\n"); |
b481de9c ZY |
506 | #endif |
507 | ||
b481de9c ZY |
508 | spin_unlock_irqrestore(&priv->lock, flags); |
509 | ||
7294ec95 | 510 | hdr_len = ieee80211_hdrlen(fc); |
6440adb5 | 511 | |
2a87c26b JB |
512 | /* Find index into station table for destination station */ |
513 | if (!info->control.sta) | |
aa065263 GS |
514 | sta_id = priv->hw_params.bcast_sta_id; |
515 | else | |
2a87c26b | 516 | sta_id = iwl_sta_id(info->control.sta); |
b481de9c | 517 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 518 | IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n", |
e174961c | 519 | hdr->addr1); |
b481de9c ZY |
520 | goto drop; |
521 | } | |
522 | ||
e1623446 | 523 | IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id); |
b481de9c | 524 | |
fd7c8a40 HH |
525 | if (ieee80211_is_data_qos(fc)) { |
526 | qc = ieee80211_get_qos_ctl(hdr); | |
7294ec95 | 527 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; |
e6a6cf4c RC |
528 | if (unlikely(tid >= MAX_TID_COUNT)) |
529 | goto drop; | |
c587de0b | 530 | seq_number = priv->stations[sta_id].tid[tid].seq_number & |
b481de9c ZY |
531 | IEEE80211_SCTL_SEQ; |
532 | hdr->seq_ctrl = cpu_to_le16(seq_number) | | |
533 | (hdr->seq_ctrl & | |
c1b4aa3f | 534 | cpu_to_le16(IEEE80211_SCTL_FRAG)); |
b481de9c ZY |
535 | seq_number += 0x10; |
536 | } | |
6440adb5 BC |
537 | |
538 | /* Descriptor for chosen Tx queue */ | |
188cf6c7 | 539 | txq = &priv->txq[txq_id]; |
b481de9c ZY |
540 | q = &txq->q; |
541 | ||
dc57a303 ZY |
542 | if ((iwl_queue_space(q) < q->high_mark)) |
543 | goto drop; | |
544 | ||
b481de9c ZY |
545 | spin_lock_irqsave(&priv->lock, flags); |
546 | ||
fc4b6853 | 547 | idx = get_cmd_index(q, q->write_ptr, 0); |
b481de9c | 548 | |
6440adb5 | 549 | /* Set up driver data for this TFD */ |
dbb6654c | 550 | memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info)); |
fc4b6853 | 551 | txq->txb[q->write_ptr].skb[0] = skb; |
6440adb5 BC |
552 | |
553 | /* Init first empty entry in queue's array of Tx/cmd buffers */ | |
188cf6c7 | 554 | out_cmd = txq->cmd[idx]; |
c2acea8e | 555 | out_meta = &txq->meta[idx]; |
9744c91f | 556 | tx_cmd = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload; |
b481de9c | 557 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); |
9744c91f | 558 | memset(tx_cmd, 0, sizeof(*tx_cmd)); |
6440adb5 BC |
559 | |
560 | /* | |
561 | * Set up the Tx-command (not MAC!) header. | |
562 | * Store the chosen Tx queue and TFD index within the sequence field; | |
563 | * after Tx, uCode's Tx response will return this value so driver can | |
564 | * locate the frame within the tx queue and do post-tx processing. | |
565 | */ | |
b481de9c ZY |
566 | out_cmd->hdr.cmd = REPLY_TX; |
567 | out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
fc4b6853 | 568 | INDEX_TO_SEQ(q->write_ptr))); |
6440adb5 BC |
569 | |
570 | /* Copy MAC header from skb into command buffer */ | |
9744c91f | 571 | memcpy(tx_cmd->hdr, hdr, hdr_len); |
b481de9c | 572 | |
df833b1d RC |
573 | |
574 | if (info->control.hw_key) | |
575 | iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id); | |
576 | ||
577 | /* TODO need this for burst mode later on */ | |
578 | iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id); | |
579 | ||
580 | /* set is_hcca to 0; it probably will never be implemented */ | |
581 | iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0); | |
582 | ||
583 | /* Total # bytes to be transmitted */ | |
584 | len = (u16)skb->len; | |
9744c91f | 585 | tx_cmd->len = cpu_to_le16(len); |
df833b1d | 586 | |
20594eb0 | 587 | iwl_dbg_log_tx_data_frame(priv, len, hdr); |
22fdf3c9 | 588 | iwl_update_stats(priv, true, fc, len); |
9744c91f AK |
589 | tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK; |
590 | tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK; | |
df833b1d RC |
591 | |
592 | if (!ieee80211_has_morefrags(hdr->frame_control)) { | |
593 | txq->need_update = 1; | |
594 | if (qc) | |
c587de0b | 595 | priv->stations[sta_id].tid[tid].seq_number = seq_number; |
df833b1d RC |
596 | } else { |
597 | wait_write_ptr = 1; | |
598 | txq->need_update = 0; | |
599 | } | |
600 | ||
91dd6c27 | 601 | IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n", |
df833b1d | 602 | le16_to_cpu(out_cmd->hdr.sequence)); |
91dd6c27 | 603 | IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); |
9744c91f AK |
604 | iwl_print_hex_dump(priv, IWL_DL_TX, tx_cmd, sizeof(*tx_cmd)); |
605 | iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, | |
df833b1d RC |
606 | ieee80211_hdrlen(fc)); |
607 | ||
6440adb5 BC |
608 | /* |
609 | * Use the first empty entry in this queue's command buffer array | |
610 | * to contain the Tx command and MAC header concatenated together | |
611 | * (payload data will be in another buffer). | |
612 | * Size of this varies, due to varying MAC header length. | |
613 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
614 | * of the MAC header (device reads on dword boundaries). | |
615 | * We'll tell device about this padding later. | |
616 | */ | |
3832ec9d | 617 | len = sizeof(struct iwl3945_tx_cmd) + |
4c897253 | 618 | sizeof(struct iwl_cmd_header) + hdr_len; |
b481de9c ZY |
619 | |
620 | len_org = len; | |
621 | len = (len + 3) & ~3; | |
622 | ||
623 | if (len_org != len) | |
624 | len_org = 1; | |
625 | else | |
626 | len_org = 0; | |
627 | ||
6440adb5 BC |
628 | /* Physical address of this Tx command's header (not MAC header!), |
629 | * within command buffer array. */ | |
df833b1d RC |
630 | txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr, |
631 | len, PCI_DMA_TODEVICE); | |
632 | /* we do not map meta data ... so we can safely access address to | |
633 | * provide to unmap command*/ | |
c2acea8e JB |
634 | pci_unmap_addr_set(out_meta, mapping, txcmd_phys); |
635 | pci_unmap_len_set(out_meta, len, len); | |
b481de9c | 636 | |
6440adb5 BC |
637 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
638 | * first entry */ | |
7aaa1d79 SO |
639 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
640 | txcmd_phys, len, 1, 0); | |
b481de9c | 641 | |
b481de9c | 642 | |
6440adb5 BC |
643 | /* Set up TFD's 2nd entry to point directly to remainder of skb, |
644 | * if any (802.11 null frames have no payload). */ | |
b481de9c ZY |
645 | len = skb->len - hdr_len; |
646 | if (len) { | |
647 | phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len, | |
648 | len, PCI_DMA_TODEVICE); | |
7aaa1d79 SO |
649 | priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, |
650 | phys_addr, len, | |
651 | 0, U32_PAD(len)); | |
b481de9c ZY |
652 | } |
653 | ||
b481de9c | 654 | |
6440adb5 | 655 | /* Tell device the write index *just past* this latest filled TFD */ |
c54b679d | 656 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); |
7bfedc59 | 657 | iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
658 | spin_unlock_irqrestore(&priv->lock, flags); |
659 | ||
d20b3c65 | 660 | if ((iwl_queue_space(q) < q->high_mark) |
b481de9c ZY |
661 | && priv->mac80211_registered) { |
662 | if (wait_write_ptr) { | |
663 | spin_lock_irqsave(&priv->lock, flags); | |
664 | txq->need_update = 1; | |
4f3602c8 | 665 | iwl_txq_update_write_ptr(priv, txq); |
b481de9c ZY |
666 | spin_unlock_irqrestore(&priv->lock, flags); |
667 | } | |
668 | ||
e4e72fb4 | 669 | iwl_stop_queue(priv, skb_get_queue_mapping(skb)); |
b481de9c ZY |
670 | } |
671 | ||
672 | return 0; | |
673 | ||
674 | drop_unlock: | |
675 | spin_unlock_irqrestore(&priv->lock, flags); | |
676 | drop: | |
677 | return -1; | |
678 | } | |
679 | ||
b481de9c ZY |
680 | #define BEACON_TIME_MASK_LOW 0x00FFFFFF |
681 | #define BEACON_TIME_MASK_HIGH 0xFF000000 | |
682 | #define TIME_UNIT 1024 | |
683 | ||
684 | /* | |
685 | * extended beacon time format | |
686 | * time in usec will be changed into a 32-bit value in 8:24 format | |
687 | * the high 1 byte is the beacon counts | |
688 | * the lower 3 bytes is the time in usec within one beacon interval | |
689 | */ | |
690 | ||
bb8c093b | 691 | static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval) |
b481de9c ZY |
692 | { |
693 | u32 quot; | |
694 | u32 rem; | |
695 | u32 interval = beacon_interval * 1024; | |
696 | ||
697 | if (!interval || !usec) | |
698 | return 0; | |
699 | ||
700 | quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24); | |
701 | rem = (usec % interval) & BEACON_TIME_MASK_LOW; | |
702 | ||
703 | return (quot << 24) + rem; | |
704 | } | |
705 | ||
706 | /* base is usually what we get from ucode with each received frame, | |
707 | * the same as HW timer counter counting down | |
708 | */ | |
709 | ||
bb8c093b | 710 | static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval) |
b481de9c ZY |
711 | { |
712 | u32 base_low = base & BEACON_TIME_MASK_LOW; | |
713 | u32 addon_low = addon & BEACON_TIME_MASK_LOW; | |
714 | u32 interval = beacon_interval * TIME_UNIT; | |
715 | u32 res = (base & BEACON_TIME_MASK_HIGH) + | |
716 | (addon & BEACON_TIME_MASK_HIGH); | |
717 | ||
718 | if (base_low > addon_low) | |
719 | res += base_low - addon_low; | |
720 | else if (base_low < addon_low) { | |
721 | res += interval + base_low - addon_low; | |
722 | res += (1 << 24); | |
723 | } else | |
724 | res += (1 << 24); | |
725 | ||
726 | return cpu_to_le32(res); | |
727 | } | |
728 | ||
4a8a4322 | 729 | static int iwl3945_get_measurement(struct iwl_priv *priv, |
b481de9c ZY |
730 | struct ieee80211_measurement_params *params, |
731 | u8 type) | |
732 | { | |
600c0e11 | 733 | struct iwl_spectrum_cmd spectrum; |
2f301227 | 734 | struct iwl_rx_packet *pkt; |
c2d79b48 | 735 | struct iwl_host_cmd cmd = { |
b481de9c ZY |
736 | .id = REPLY_SPECTRUM_MEASUREMENT_CMD, |
737 | .data = (void *)&spectrum, | |
c2acea8e | 738 | .flags = CMD_WANT_SKB, |
b481de9c ZY |
739 | }; |
740 | u32 add_time = le64_to_cpu(params->start_time); | |
741 | int rc; | |
742 | int spectrum_resp_status; | |
743 | int duration = le16_to_cpu(params->duration); | |
744 | ||
8ccde88a | 745 | if (iwl_is_associated(priv)) |
b481de9c | 746 | add_time = |
bb8c093b | 747 | iwl3945_usecs_to_beacons( |
e99f168c | 748 | le64_to_cpu(params->start_time) - priv->_3945.last_tsf, |
b481de9c ZY |
749 | le16_to_cpu(priv->rxon_timing.beacon_interval)); |
750 | ||
751 | memset(&spectrum, 0, sizeof(spectrum)); | |
752 | ||
753 | spectrum.channel_count = cpu_to_le16(1); | |
754 | spectrum.flags = | |
755 | RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK; | |
756 | spectrum.filter_flags = MEASUREMENT_FILTER_FLAG; | |
757 | cmd.len = sizeof(spectrum); | |
758 | spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len)); | |
759 | ||
8ccde88a | 760 | if (iwl_is_associated(priv)) |
b481de9c | 761 | spectrum.start_time = |
e99f168c | 762 | iwl3945_add_beacon_time(priv->_3945.last_beacon_time, |
b481de9c ZY |
763 | add_time, |
764 | le16_to_cpu(priv->rxon_timing.beacon_interval)); | |
765 | else | |
766 | spectrum.start_time = 0; | |
767 | ||
768 | spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT); | |
769 | spectrum.channels[0].channel = params->channel; | |
770 | spectrum.channels[0].type = type; | |
8ccde88a | 771 | if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK) |
b481de9c ZY |
772 | spectrum.flags |= RXON_FLG_BAND_24G_MSK | |
773 | RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK; | |
774 | ||
518099a8 | 775 | rc = iwl_send_cmd_sync(priv, &cmd); |
b481de9c ZY |
776 | if (rc) |
777 | return rc; | |
778 | ||
2f301227 ZY |
779 | pkt = (struct iwl_rx_packet *)cmd.reply_page; |
780 | if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { | |
15b1687c | 781 | IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n"); |
b481de9c ZY |
782 | rc = -EIO; |
783 | } | |
784 | ||
2f301227 | 785 | spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status); |
b481de9c ZY |
786 | switch (spectrum_resp_status) { |
787 | case 0: /* Command will be handled */ | |
2f301227 | 788 | if (pkt->u.spectrum.id != 0xff) { |
e1623446 | 789 | IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n", |
2f301227 | 790 | pkt->u.spectrum.id); |
b481de9c ZY |
791 | priv->measurement_status &= ~MEASUREMENT_READY; |
792 | } | |
793 | priv->measurement_status |= MEASUREMENT_ACTIVE; | |
794 | rc = 0; | |
795 | break; | |
796 | ||
797 | case 1: /* Command will not be handled */ | |
798 | rc = -EAGAIN; | |
799 | break; | |
800 | } | |
801 | ||
64a76b50 | 802 | iwl_free_pages(priv, cmd.reply_page); |
b481de9c ZY |
803 | |
804 | return rc; | |
805 | } | |
b481de9c | 806 | |
4a8a4322 | 807 | static void iwl3945_rx_reply_alive(struct iwl_priv *priv, |
6100b588 | 808 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 809 | { |
2f301227 | 810 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
3d24a9f7 | 811 | struct iwl_alive_resp *palive; |
b481de9c ZY |
812 | struct delayed_work *pwork; |
813 | ||
814 | palive = &pkt->u.alive_frame; | |
815 | ||
e1623446 | 816 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
817 | "0x%01X 0x%01X\n", |
818 | palive->is_valid, palive->ver_type, | |
819 | palive->ver_subtype); | |
820 | ||
821 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 822 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
3d24a9f7 TW |
823 | memcpy(&priv->card_alive_init, &pkt->u.alive_frame, |
824 | sizeof(struct iwl_alive_resp)); | |
b481de9c ZY |
825 | pwork = &priv->init_alive_start; |
826 | } else { | |
e1623446 | 827 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 828 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
3d24a9f7 | 829 | sizeof(struct iwl_alive_resp)); |
b481de9c | 830 | pwork = &priv->alive_start; |
bb8c093b | 831 | iwl3945_disable_events(priv); |
b481de9c ZY |
832 | } |
833 | ||
834 | /* We delay the ALIVE response by 5ms to | |
835 | * give the HW RF Kill time to activate... */ | |
836 | if (palive->is_valid == UCODE_VALID_OK) | |
837 | queue_delayed_work(priv->workqueue, pwork, | |
838 | msecs_to_jiffies(5)); | |
839 | else | |
39aadf8c | 840 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
841 | } |
842 | ||
4a8a4322 | 843 | static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv, |
6100b588 | 844 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 845 | { |
c7e035a9 | 846 | #ifdef CONFIG_IWLWIFI_DEBUG |
2f301227 | 847 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
c7e035a9 | 848 | #endif |
b481de9c | 849 | |
e1623446 | 850 | IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status); |
b481de9c ZY |
851 | } |
852 | ||
bb8c093b | 853 | static void iwl3945_bg_beacon_update(struct work_struct *work) |
b481de9c | 854 | { |
4a8a4322 AK |
855 | struct iwl_priv *priv = |
856 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
857 | struct sk_buff *beacon; |
858 | ||
859 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 860 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
861 | |
862 | if (!beacon) { | |
15b1687c | 863 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
864 | return; |
865 | } | |
866 | ||
867 | mutex_lock(&priv->mutex); | |
868 | /* new beacon skb is allocated every time; dispose previous.*/ | |
869 | if (priv->ibss_beacon) | |
870 | dev_kfree_skb(priv->ibss_beacon); | |
871 | ||
872 | priv->ibss_beacon = beacon; | |
873 | mutex_unlock(&priv->mutex); | |
874 | ||
bb8c093b | 875 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
876 | } |
877 | ||
4a8a4322 | 878 | static void iwl3945_rx_beacon_notif(struct iwl_priv *priv, |
6100b588 | 879 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 880 | { |
d08853a3 | 881 | #ifdef CONFIG_IWLWIFI_DEBUG |
2f301227 | 882 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
bb8c093b | 883 | struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status); |
b481de9c ZY |
884 | u8 rate = beacon->beacon_notify_hdr.rate; |
885 | ||
e1623446 | 886 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c ZY |
887 | "tsf %d %d rate %d\n", |
888 | le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK, | |
889 | beacon->beacon_notify_hdr.failure_frame, | |
890 | le32_to_cpu(beacon->ibss_mgr_status), | |
891 | le32_to_cpu(beacon->high_tsf), | |
892 | le32_to_cpu(beacon->low_tsf), rate); | |
893 | #endif | |
894 | ||
05c914fe | 895 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
896 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
897 | queue_work(priv->workqueue, &priv->beacon_update); | |
898 | } | |
899 | ||
b481de9c ZY |
900 | /* Handle notification from uCode that card's power state is changing |
901 | * due to software, hardware, or critical temperature RFKILL */ | |
4a8a4322 | 902 | static void iwl3945_rx_card_state_notif(struct iwl_priv *priv, |
6100b588 | 903 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 904 | { |
2f301227 | 905 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
b481de9c ZY |
906 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
907 | unsigned long status = priv->status; | |
908 | ||
4c423a2b | 909 | IWL_WARN(priv, "Card state received: HW:%s SW:%s\n", |
b481de9c ZY |
910 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
911 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
912 | ||
5d49f498 | 913 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
914 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
915 | ||
916 | if (flags & HW_CARD_DISABLED) | |
917 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
918 | else | |
919 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
920 | ||
921 | ||
af0053d6 | 922 | iwl_scan_cancel(priv); |
b481de9c ZY |
923 | |
924 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
925 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
926 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
927 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
928 | else |
929 | wake_up_interruptible(&priv->wait_command_queue); | |
930 | } | |
931 | ||
932 | /** | |
bb8c093b | 933 | * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
934 | * |
935 | * Setup the RX handlers for each of the reply types sent from the uCode | |
936 | * to the host. | |
937 | * | |
938 | * This function chains into the hardware specific files for them to setup | |
939 | * any hardware specific handlers as well. | |
940 | */ | |
4a8a4322 | 941 | static void iwl3945_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 942 | { |
bb8c093b CH |
943 | priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive; |
944 | priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta; | |
261b9c33 | 945 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
8ccde88a | 946 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; |
81963d68 RC |
947 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
948 | iwl_rx_spectrum_measure_notif; | |
030f05ed | 949 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 950 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
030f05ed | 951 | iwl_rx_pm_debug_statistics_notif; |
bb8c093b | 952 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif; |
b481de9c | 953 | |
9fbab516 BC |
954 | /* |
955 | * The same handler is used for both the REPLY to a discrete | |
956 | * statistics request from the host as well as for the periodic | |
957 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 958 | */ |
17f36fc6 | 959 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_reply_statistics; |
bb8c093b | 960 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics; |
b481de9c | 961 | |
cade0eb2 | 962 | iwl_setup_rx_scan_handlers(priv); |
bb8c093b | 963 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif; |
b481de9c | 964 | |
9fbab516 | 965 | /* Set up hardware specific Rx handlers */ |
bb8c093b | 966 | iwl3945_hw_rx_handler_setup(priv); |
b481de9c ZY |
967 | } |
968 | ||
b481de9c ZY |
969 | /************************** RX-FUNCTIONS ****************************/ |
970 | /* | |
971 | * Rx theory of operation | |
972 | * | |
973 | * The host allocates 32 DMA target addresses and passes the host address | |
974 | * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is | |
975 | * 0 to 31 | |
976 | * | |
977 | * Rx Queue Indexes | |
978 | * The host/firmware share two index registers for managing the Rx buffers. | |
979 | * | |
980 | * The READ index maps to the first position that the firmware may be writing | |
981 | * to -- the driver can read up to (but not including) this position and get | |
982 | * good data. | |
983 | * The READ index is managed by the firmware once the card is enabled. | |
984 | * | |
985 | * The WRITE index maps to the last position the driver has read from -- the | |
986 | * position preceding WRITE is the last slot the firmware can place a packet. | |
987 | * | |
988 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
989 | * WRITE = READ. | |
990 | * | |
9fbab516 | 991 | * During initialization, the host sets up the READ queue position to the first |
b481de9c ZY |
992 | * INDEX position, and WRITE to the last (READ - 1 wrapped) |
993 | * | |
9fbab516 | 994 | * When the firmware places a packet in a buffer, it will advance the READ index |
b481de9c ZY |
995 | * and fire the RX interrupt. The driver can then query the READ index and |
996 | * process as many packets as possible, moving the WRITE index forward as it | |
997 | * resets the Rx queue buffers with new memory. | |
998 | * | |
999 | * The management in the driver is as follows: | |
1000 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
1001 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
01ebd063 | 1002 | * to replenish the iwl->rxq->rx_free. |
bb8c093b | 1003 | * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the |
b481de9c ZY |
1004 | * iwl->rxq is replenished and the READ INDEX is updated (updating the |
1005 | * 'processed' and 'read' driver indexes as well) | |
1006 | * + A received packet is processed and handed to the kernel network stack, | |
1007 | * detached from the iwl->rxq. The driver 'processed' index is updated. | |
1008 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
1009 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
1010 | * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there | |
1011 | * were enough free buffers and RX_STALLED is set it is cleared. | |
1012 | * | |
1013 | * | |
1014 | * Driver sequence: | |
1015 | * | |
9fbab516 | 1016 | * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls |
bb8c093b | 1017 | * iwl3945_rx_queue_restock |
9fbab516 | 1018 | * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx |
b481de9c ZY |
1019 | * queue, updates firmware pointers, and updates |
1020 | * the WRITE index. If insufficient rx_free buffers | |
bb8c093b | 1021 | * are available, schedules iwl3945_rx_replenish |
b481de9c ZY |
1022 | * |
1023 | * -- enable interrupts -- | |
6100b588 | 1024 | * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the |
b481de9c ZY |
1025 | * READ INDEX, detaching the SKB from the pool. |
1026 | * Moves the packet buffer from queue to rx_used. | |
bb8c093b | 1027 | * Calls iwl3945_rx_queue_restock to refill any empty |
b481de9c ZY |
1028 | * slots. |
1029 | * ... | |
1030 | * | |
1031 | */ | |
1032 | ||
b481de9c | 1033 | /** |
9fbab516 | 1034 | * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr |
b481de9c | 1035 | */ |
4a8a4322 | 1036 | static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv, |
b481de9c ZY |
1037 | dma_addr_t dma_addr) |
1038 | { | |
1039 | return cpu_to_le32((u32)dma_addr); | |
1040 | } | |
1041 | ||
1042 | /** | |
bb8c093b | 1043 | * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool |
b481de9c | 1044 | * |
9fbab516 | 1045 | * If there are slots in the RX queue that need to be restocked, |
b481de9c | 1046 | * and we have free pre-allocated buffers, fill the ranks as much |
9fbab516 | 1047 | * as we can, pulling from rx_free. |
b481de9c ZY |
1048 | * |
1049 | * This moves the 'write' index forward to catch up with 'processed', and | |
1050 | * also updates the memory address in the firmware to reference the new | |
1051 | * target buffer. | |
1052 | */ | |
7bfedc59 | 1053 | static void iwl3945_rx_queue_restock(struct iwl_priv *priv) |
b481de9c | 1054 | { |
cc2f362c | 1055 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 1056 | struct list_head *element; |
6100b588 | 1057 | struct iwl_rx_mem_buffer *rxb; |
b481de9c | 1058 | unsigned long flags; |
7bfedc59 | 1059 | int write; |
b481de9c ZY |
1060 | |
1061 | spin_lock_irqsave(&rxq->lock, flags); | |
1062 | write = rxq->write & ~0x7; | |
37d68317 | 1063 | while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { |
6440adb5 | 1064 | /* Get next free Rx buffer, remove from free list */ |
b481de9c | 1065 | element = rxq->rx_free.next; |
6100b588 | 1066 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); |
b481de9c | 1067 | list_del(element); |
6440adb5 BC |
1068 | |
1069 | /* Point to Rx buffer via next RBD in circular buffer */ | |
2f301227 | 1070 | rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->page_dma); |
b481de9c ZY |
1071 | rxq->queue[rxq->write] = rxb; |
1072 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
1073 | rxq->free_count--; | |
1074 | } | |
1075 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1076 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
1077 | * refill it */ | |
1078 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
1079 | queue_work(priv->workqueue, &priv->rx_replenish); | |
1080 | ||
1081 | ||
6440adb5 BC |
1082 | /* If we've added more space for the firmware to place data, tell it. |
1083 | * Increment device's write pointer in multiples of 8. */ | |
d14d4440 | 1084 | if ((rxq->write_actual != (rxq->write & ~0x7)) |
b481de9c ZY |
1085 | || (abs(rxq->write - rxq->read) > 7)) { |
1086 | spin_lock_irqsave(&rxq->lock, flags); | |
1087 | rxq->need_update = 1; | |
1088 | spin_unlock_irqrestore(&rxq->lock, flags); | |
7bfedc59 | 1089 | iwl_rx_queue_update_write_ptr(priv, rxq); |
b481de9c | 1090 | } |
b481de9c ZY |
1091 | } |
1092 | ||
1093 | /** | |
bb8c093b | 1094 | * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free |
b481de9c ZY |
1095 | * |
1096 | * When moving to rx_free an SKB is allocated for the slot. | |
1097 | * | |
bb8c093b | 1098 | * Also restock the Rx queue via iwl3945_rx_queue_restock. |
01ebd063 | 1099 | * This is called as a scheduled work item (except for during initialization) |
b481de9c | 1100 | */ |
d14d4440 | 1101 | static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority) |
b481de9c | 1102 | { |
cc2f362c | 1103 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c | 1104 | struct list_head *element; |
6100b588 | 1105 | struct iwl_rx_mem_buffer *rxb; |
2f301227 | 1106 | struct page *page; |
b481de9c | 1107 | unsigned long flags; |
29b1b268 | 1108 | gfp_t gfp_mask = priority; |
72240498 AK |
1109 | |
1110 | while (1) { | |
1111 | spin_lock_irqsave(&rxq->lock, flags); | |
1112 | ||
1113 | if (list_empty(&rxq->rx_used)) { | |
1114 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1115 | return; | |
1116 | } | |
72240498 | 1117 | spin_unlock_irqrestore(&rxq->lock, flags); |
6440adb5 | 1118 | |
f82a924c | 1119 | if (rxq->free_count > RX_LOW_WATERMARK) |
29b1b268 | 1120 | gfp_mask |= __GFP_NOWARN; |
2f301227 ZY |
1121 | |
1122 | if (priv->hw_params.rx_page_order > 0) | |
29b1b268 | 1123 | gfp_mask |= __GFP_COMP; |
2f301227 | 1124 | |
6440adb5 | 1125 | /* Alloc a new receive buffer */ |
29b1b268 | 1126 | page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order); |
2f301227 | 1127 | if (!page) { |
b481de9c | 1128 | if (net_ratelimit()) |
f82a924c RC |
1129 | IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n"); |
1130 | if ((rxq->free_count <= RX_LOW_WATERMARK) && | |
1131 | net_ratelimit()) | |
1132 | IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n", | |
1133 | priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL", | |
1134 | rxq->free_count); | |
b481de9c ZY |
1135 | /* We don't reschedule replenish work here -- we will |
1136 | * call the restock method and if it still needs | |
1137 | * more buffers it will schedule replenish */ | |
1138 | break; | |
1139 | } | |
12342c47 | 1140 | |
de0bd508 RC |
1141 | spin_lock_irqsave(&rxq->lock, flags); |
1142 | if (list_empty(&rxq->rx_used)) { | |
1143 | spin_unlock_irqrestore(&rxq->lock, flags); | |
2f301227 | 1144 | __free_pages(page, priv->hw_params.rx_page_order); |
de0bd508 RC |
1145 | return; |
1146 | } | |
1147 | element = rxq->rx_used.next; | |
1148 | rxb = list_entry(element, struct iwl_rx_mem_buffer, list); | |
1149 | list_del(element); | |
1150 | spin_unlock_irqrestore(&rxq->lock, flags); | |
1151 | ||
2f301227 | 1152 | rxb->page = page; |
6440adb5 | 1153 | /* Get physical address of RB/SKB */ |
2f301227 ZY |
1154 | rxb->page_dma = pci_map_page(priv->pci_dev, page, 0, |
1155 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
1156 | PCI_DMA_FROMDEVICE); | |
72240498 AK |
1157 | |
1158 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 1159 | |
b481de9c ZY |
1160 | list_add_tail(&rxb->list, &rxq->rx_free); |
1161 | rxq->free_count++; | |
2f301227 ZY |
1162 | priv->alloc_rxb_page++; |
1163 | ||
72240498 | 1164 | spin_unlock_irqrestore(&rxq->lock, flags); |
b481de9c | 1165 | } |
5c0eef96 MA |
1166 | } |
1167 | ||
df833b1d RC |
1168 | void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq) |
1169 | { | |
1170 | unsigned long flags; | |
1171 | int i; | |
1172 | spin_lock_irqsave(&rxq->lock, flags); | |
1173 | INIT_LIST_HEAD(&rxq->rx_free); | |
1174 | INIT_LIST_HEAD(&rxq->rx_used); | |
1175 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
1176 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
1177 | /* In the reset function, these buffers may have been allocated | |
1178 | * to an SKB, so we need to unmap and free potential storage */ | |
2f301227 ZY |
1179 | if (rxq->pool[i].page != NULL) { |
1180 | pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma, | |
1181 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
1182 | PCI_DMA_FROMDEVICE); | |
64a76b50 | 1183 | __iwl_free_pages(priv, rxq->pool[i].page); |
2f301227 | 1184 | rxq->pool[i].page = NULL; |
df833b1d RC |
1185 | } |
1186 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
1187 | } | |
1188 | ||
1189 | /* Set us so that we have processed and used all buffers, but have | |
1190 | * not restocked the Rx queue with fresh buffers */ | |
1191 | rxq->read = rxq->write = 0; | |
d14d4440 | 1192 | rxq->write_actual = 0; |
2f301227 | 1193 | rxq->free_count = 0; |
df833b1d RC |
1194 | spin_unlock_irqrestore(&rxq->lock, flags); |
1195 | } | |
df833b1d | 1196 | |
5c0eef96 MA |
1197 | void iwl3945_rx_replenish(void *data) |
1198 | { | |
4a8a4322 | 1199 | struct iwl_priv *priv = data; |
5c0eef96 MA |
1200 | unsigned long flags; |
1201 | ||
d14d4440 | 1202 | iwl3945_rx_allocate(priv, GFP_KERNEL); |
b481de9c ZY |
1203 | |
1204 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 1205 | iwl3945_rx_queue_restock(priv); |
b481de9c ZY |
1206 | spin_unlock_irqrestore(&priv->lock, flags); |
1207 | } | |
1208 | ||
d14d4440 AK |
1209 | static void iwl3945_rx_replenish_now(struct iwl_priv *priv) |
1210 | { | |
1211 | iwl3945_rx_allocate(priv, GFP_ATOMIC); | |
1212 | ||
1213 | iwl3945_rx_queue_restock(priv); | |
1214 | } | |
1215 | ||
1216 | ||
df833b1d RC |
1217 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. |
1218 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL | |
1219 | * This free routine walks the list of POOL entries and if SKB is set to | |
1220 | * non NULL it is unmapped and freed | |
1221 | */ | |
1222 | static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |
1223 | { | |
1224 | int i; | |
1225 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
2f301227 ZY |
1226 | if (rxq->pool[i].page != NULL) { |
1227 | pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma, | |
1228 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
1229 | PCI_DMA_FROMDEVICE); | |
64a76b50 | 1230 | __iwl_free_pages(priv, rxq->pool[i].page); |
2f301227 | 1231 | rxq->pool[i].page = NULL; |
df833b1d RC |
1232 | } |
1233 | } | |
1234 | ||
f36d04ab SG |
1235 | dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd, |
1236 | rxq->dma_addr); | |
1237 | dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status), | |
1238 | rxq->rb_stts, rxq->rb_stts_dma); | |
df833b1d RC |
1239 | rxq->bd = NULL; |
1240 | rxq->rb_stts = NULL; | |
1241 | } | |
df833b1d RC |
1242 | |
1243 | ||
b481de9c ZY |
1244 | /* Convert linear signal-to-noise ratio into dB */ |
1245 | static u8 ratio2dB[100] = { | |
1246 | /* 0 1 2 3 4 5 6 7 8 9 */ | |
1247 | 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */ | |
1248 | 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */ | |
1249 | 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */ | |
1250 | 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */ | |
1251 | 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */ | |
1252 | 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */ | |
1253 | 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */ | |
1254 | 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */ | |
1255 | 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */ | |
1256 | 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */ | |
1257 | }; | |
1258 | ||
1259 | /* Calculates a relative dB value from a ratio of linear | |
1260 | * (i.e. not dB) signal levels. | |
1261 | * Conversion assumes that levels are voltages (20*log), not powers (10*log). */ | |
bb8c093b | 1262 | int iwl3945_calc_db_from_ratio(int sig_ratio) |
b481de9c | 1263 | { |
221c80cf AB |
1264 | /* 1000:1 or higher just report as 60 dB */ |
1265 | if (sig_ratio >= 1000) | |
b481de9c ZY |
1266 | return 60; |
1267 | ||
221c80cf | 1268 | /* 100:1 or higher, divide by 10 and use table, |
b481de9c | 1269 | * add 20 dB to make up for divide by 10 */ |
221c80cf | 1270 | if (sig_ratio >= 100) |
3ac7f146 | 1271 | return 20 + (int)ratio2dB[sig_ratio/10]; |
b481de9c ZY |
1272 | |
1273 | /* We shouldn't see this */ | |
1274 | if (sig_ratio < 1) | |
1275 | return 0; | |
1276 | ||
1277 | /* Use table for ratios 1:1 - 99:1 */ | |
1278 | return (int)ratio2dB[sig_ratio]; | |
1279 | } | |
1280 | ||
b481de9c | 1281 | /** |
9fbab516 | 1282 | * iwl3945_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
1283 | * |
1284 | * Uses the priv->rx_handlers callback function array to invoke | |
1285 | * the appropriate handlers, including command responses, | |
1286 | * frame-received notifications, and other notifications. | |
1287 | */ | |
4a8a4322 | 1288 | static void iwl3945_rx_handle(struct iwl_priv *priv) |
b481de9c | 1289 | { |
6100b588 | 1290 | struct iwl_rx_mem_buffer *rxb; |
3d24a9f7 | 1291 | struct iwl_rx_packet *pkt; |
cc2f362c | 1292 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
1293 | u32 r, i; |
1294 | int reclaim; | |
1295 | unsigned long flags; | |
5c0eef96 | 1296 | u8 fill_rx = 0; |
d68ab680 | 1297 | u32 count = 8; |
d14d4440 | 1298 | int total_empty = 0; |
b481de9c | 1299 | |
6440adb5 BC |
1300 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
1301 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8cd812bc | 1302 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
1303 | i = rxq->read; |
1304 | ||
d14d4440 | 1305 | /* calculate total frames need to be restock after handling RX */ |
7300515d | 1306 | total_empty = r - rxq->write_actual; |
d14d4440 AK |
1307 | if (total_empty < 0) |
1308 | total_empty += RX_QUEUE_SIZE; | |
1309 | ||
1310 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 | 1311 | fill_rx = 1; |
b481de9c ZY |
1312 | /* Rx interrupt, but nothing sent from uCode */ |
1313 | if (i == r) | |
af472a95 | 1314 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c ZY |
1315 | |
1316 | while (i != r) { | |
1317 | rxb = rxq->queue[i]; | |
1318 | ||
9fbab516 | 1319 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
1320 | * then a bug has been introduced in the queue refilling |
1321 | * routines -- catch it here */ | |
1322 | BUG_ON(rxb == NULL); | |
1323 | ||
1324 | rxq->queue[i] = NULL; | |
1325 | ||
2f301227 ZY |
1326 | pci_unmap_page(priv->pci_dev, rxb->page_dma, |
1327 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
1328 | PCI_DMA_FROMDEVICE); | |
1329 | pkt = rxb_addr(rxb); | |
b481de9c | 1330 | |
be1a71a1 JB |
1331 | trace_iwlwifi_dev_rx(priv, pkt, |
1332 | le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK); | |
1333 | ||
b481de9c ZY |
1334 | /* Reclaim a command buffer only if this packet is a response |
1335 | * to a (driver-originated) command. | |
1336 | * If the packet (e.g. Rx frame) originated from uCode, | |
1337 | * there is no command buffer to reclaim. | |
1338 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
1339 | * but apparently a few don't get set; catch them here. */ | |
1340 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
1341 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
1342 | (pkt->hdr.cmd != REPLY_TX); | |
1343 | ||
1344 | /* Based on type of command response or notification, | |
1345 | * handle those that need handling via function in | |
bb8c093b | 1346 | * rx_handlers table. See iwl3945_setup_rx_handlers() */ |
b481de9c | 1347 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
af472a95 | 1348 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i, |
b481de9c | 1349 | get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
86ddbf62 | 1350 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
29b1b268 | 1351 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
b481de9c ZY |
1352 | } else { |
1353 | /* No handling needed */ | |
2f301227 ZY |
1354 | IWL_DEBUG_RX(priv, |
1355 | "r %d i %d No handler needed for %s, 0x%02x\n", | |
b481de9c ZY |
1356 | r, i, get_cmd_string(pkt->hdr.cmd), |
1357 | pkt->hdr.cmd); | |
1358 | } | |
1359 | ||
29b1b268 ZY |
1360 | /* |
1361 | * XXX: After here, we should always check rxb->page | |
1362 | * against NULL before touching it or its virtual | |
1363 | * memory (pkt). Because some rx_handler might have | |
1364 | * already taken or freed the pages. | |
1365 | */ | |
1366 | ||
b481de9c | 1367 | if (reclaim) { |
2f301227 ZY |
1368 | /* Invoke any callbacks, transfer the buffer to caller, |
1369 | * and fire off the (possibly) blocking iwl_send_cmd() | |
b481de9c | 1370 | * as we reclaim the driver command queue */ |
29b1b268 | 1371 | if (rxb->page) |
732587ab | 1372 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 1373 | else |
39aadf8c | 1374 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
1375 | } |
1376 | ||
7300515d ZY |
1377 | /* Reuse the page if possible. For notification packets and |
1378 | * SKBs that fail to Rx correctly, add them back into the | |
1379 | * rx_free list for reuse later. */ | |
1380 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 1381 | if (rxb->page != NULL) { |
7300515d ZY |
1382 | rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page, |
1383 | 0, PAGE_SIZE << priv->hw_params.rx_page_order, | |
1384 | PCI_DMA_FROMDEVICE); | |
1385 | list_add_tail(&rxb->list, &rxq->rx_free); | |
1386 | rxq->free_count++; | |
1387 | } else | |
1388 | list_add_tail(&rxb->list, &rxq->rx_used); | |
b481de9c | 1389 | |
b481de9c | 1390 | spin_unlock_irqrestore(&rxq->lock, flags); |
7300515d | 1391 | |
b481de9c | 1392 | i = (i + 1) & RX_QUEUE_MASK; |
5c0eef96 MA |
1393 | /* If there are a lot of unused frames, |
1394 | * restock the Rx queue so ucode won't assert. */ | |
1395 | if (fill_rx) { | |
1396 | count++; | |
1397 | if (count >= 8) { | |
7300515d | 1398 | rxq->read = i; |
d14d4440 | 1399 | iwl3945_rx_replenish_now(priv); |
5c0eef96 MA |
1400 | count = 0; |
1401 | } | |
1402 | } | |
b481de9c ZY |
1403 | } |
1404 | ||
1405 | /* Backtrack one entry */ | |
7300515d | 1406 | rxq->read = i; |
d14d4440 AK |
1407 | if (fill_rx) |
1408 | iwl3945_rx_replenish_now(priv); | |
1409 | else | |
1410 | iwl3945_rx_queue_restock(priv); | |
b481de9c ZY |
1411 | } |
1412 | ||
0359facc | 1413 | /* call this function to flush any scheduled tasklet */ |
4a8a4322 | 1414 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) |
0359facc | 1415 | { |
a96a27f9 | 1416 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
1417 | synchronize_irq(priv->pci_dev->irq); |
1418 | tasklet_kill(&priv->irq_tasklet); | |
1419 | } | |
1420 | ||
b481de9c ZY |
1421 | static const char *desc_lookup(int i) |
1422 | { | |
1423 | switch (i) { | |
1424 | case 1: | |
1425 | return "FAIL"; | |
1426 | case 2: | |
1427 | return "BAD_PARAM"; | |
1428 | case 3: | |
1429 | return "BAD_CHECKSUM"; | |
1430 | case 4: | |
1431 | return "NMI_INTERRUPT"; | |
1432 | case 5: | |
1433 | return "SYSASSERT"; | |
1434 | case 6: | |
1435 | return "FATAL_ERROR"; | |
1436 | } | |
1437 | ||
1438 | return "UNKNOWN"; | |
1439 | } | |
1440 | ||
1441 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1442 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1443 | ||
b7a79404 | 1444 | void iwl3945_dump_nic_error_log(struct iwl_priv *priv) |
b481de9c ZY |
1445 | { |
1446 | u32 i; | |
1447 | u32 desc, time, count, base, data1; | |
1448 | u32 blink1, blink2, ilink1, ilink2; | |
b481de9c ZY |
1449 | |
1450 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | |
1451 | ||
bb8c093b | 1452 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 1453 | IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base); |
b481de9c ZY |
1454 | return; |
1455 | } | |
1456 | ||
b481de9c | 1457 | |
5d49f498 | 1458 | count = iwl_read_targ_mem(priv, base); |
b481de9c ZY |
1459 | |
1460 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
15b1687c WT |
1461 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); |
1462 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
1463 | priv->status, count); | |
b481de9c ZY |
1464 | } |
1465 | ||
15b1687c | 1466 | IWL_ERR(priv, "Desc Time asrtPC blink2 " |
b481de9c ZY |
1467 | "ilink1 nmiPC Line\n"); |
1468 | for (i = ERROR_START_OFFSET; | |
1469 | i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET; | |
1470 | i += ERROR_ELEM_SIZE) { | |
5d49f498 | 1471 | desc = iwl_read_targ_mem(priv, base + i); |
b481de9c | 1472 | time = |
5d49f498 | 1473 | iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32)); |
b481de9c | 1474 | blink1 = |
5d49f498 | 1475 | iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32)); |
b481de9c | 1476 | blink2 = |
5d49f498 | 1477 | iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32)); |
b481de9c | 1478 | ilink1 = |
5d49f498 | 1479 | iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32)); |
b481de9c | 1480 | ilink2 = |
5d49f498 | 1481 | iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32)); |
b481de9c | 1482 | data1 = |
5d49f498 | 1483 | iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32)); |
b481de9c | 1484 | |
15b1687c WT |
1485 | IWL_ERR(priv, |
1486 | "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n", | |
1487 | desc_lookup(desc), desc, time, blink1, blink2, | |
1488 | ilink1, ilink2, data1); | |
be1a71a1 JB |
1489 | trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, 0, |
1490 | 0, blink1, blink2, ilink1, ilink2); | |
b481de9c | 1491 | } |
b481de9c ZY |
1492 | } |
1493 | ||
f58177b9 | 1494 | #define EVENT_START_OFFSET (6 * sizeof(u32)) |
b481de9c ZY |
1495 | |
1496 | /** | |
bb8c093b | 1497 | * iwl3945_print_event_log - Dump error event log to syslog |
b481de9c | 1498 | * |
b481de9c | 1499 | */ |
b03d7d0f WYG |
1500 | static int iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx, |
1501 | u32 num_events, u32 mode, | |
1502 | int pos, char **buf, size_t bufsz) | |
b481de9c ZY |
1503 | { |
1504 | u32 i; | |
1505 | u32 base; /* SRAM byte address of event log header */ | |
1506 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1507 | u32 ptr; /* SRAM byte address of log data */ | |
1508 | u32 ev, time, data; /* event log data */ | |
e5854471 | 1509 | unsigned long reg_flags; |
b481de9c ZY |
1510 | |
1511 | if (num_events == 0) | |
b03d7d0f | 1512 | return pos; |
b481de9c ZY |
1513 | |
1514 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
1515 | ||
1516 | if (mode == 0) | |
1517 | event_size = 2 * sizeof(u32); | |
1518 | else | |
1519 | event_size = 3 * sizeof(u32); | |
1520 | ||
1521 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1522 | ||
e5854471 BC |
1523 | /* Make sure device is powered up for SRAM reads */ |
1524 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
1525 | iwl_grab_nic_access(priv); | |
1526 | ||
1527 | /* Set starting address; reads will auto-increment */ | |
1528 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
1529 | rmb(); | |
1530 | ||
b481de9c ZY |
1531 | /* "time" is actually "data" for mode 0 (no timestamp). |
1532 | * place event id # at far right for easier visual parsing. */ | |
1533 | for (i = 0; i < num_events; i++) { | |
e5854471 BC |
1534 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
1535 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
15b1687c WT |
1536 | if (mode == 0) { |
1537 | /* data, ev */ | |
b03d7d0f WYG |
1538 | if (bufsz) { |
1539 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1540 | "0x%08x:%04u\n", | |
1541 | time, ev); | |
1542 | } else { | |
1543 | IWL_ERR(priv, "0x%08x\t%04u\n", time, ev); | |
1544 | trace_iwlwifi_dev_ucode_event(priv, 0, | |
1545 | time, ev); | |
1546 | } | |
15b1687c | 1547 | } else { |
e5854471 | 1548 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b03d7d0f WYG |
1549 | if (bufsz) { |
1550 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1551 | "%010u:0x%08x:%04u\n", | |
1552 | time, data, ev); | |
1553 | } else { | |
1554 | IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", | |
1555 | time, data, ev); | |
1556 | trace_iwlwifi_dev_ucode_event(priv, time, | |
1557 | data, ev); | |
1558 | } | |
b481de9c ZY |
1559 | } |
1560 | } | |
e5854471 BC |
1561 | |
1562 | /* Allow device to power down */ | |
1563 | iwl_release_nic_access(priv); | |
1564 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
b03d7d0f | 1565 | return pos; |
b481de9c ZY |
1566 | } |
1567 | ||
c341ddb2 WYG |
1568 | /** |
1569 | * iwl3945_print_last_event_logs - Dump the newest # of event log to syslog | |
1570 | */ | |
b03d7d0f | 1571 | static int iwl3945_print_last_event_logs(struct iwl_priv *priv, u32 capacity, |
c341ddb2 | 1572 | u32 num_wraps, u32 next_entry, |
b03d7d0f WYG |
1573 | u32 size, u32 mode, |
1574 | int pos, char **buf, size_t bufsz) | |
c341ddb2 WYG |
1575 | { |
1576 | /* | |
1577 | * display the newest DEFAULT_LOG_ENTRIES entries | |
1578 | * i.e the entries just before the next ont that uCode would fill. | |
1579 | */ | |
1580 | if (num_wraps) { | |
1581 | if (next_entry < size) { | |
b03d7d0f WYG |
1582 | pos = iwl3945_print_event_log(priv, |
1583 | capacity - (size - next_entry), | |
1584 | size - next_entry, mode, | |
1585 | pos, buf, bufsz); | |
1586 | pos = iwl3945_print_event_log(priv, 0, | |
1587 | next_entry, mode, | |
1588 | pos, buf, bufsz); | |
c341ddb2 | 1589 | } else |
b03d7d0f WYG |
1590 | pos = iwl3945_print_event_log(priv, next_entry - size, |
1591 | size, mode, | |
1592 | pos, buf, bufsz); | |
c341ddb2 WYG |
1593 | } else { |
1594 | if (next_entry < size) | |
b03d7d0f WYG |
1595 | pos = iwl3945_print_event_log(priv, 0, |
1596 | next_entry, mode, | |
1597 | pos, buf, bufsz); | |
c341ddb2 | 1598 | else |
b03d7d0f WYG |
1599 | pos = iwl3945_print_event_log(priv, next_entry - size, |
1600 | size, mode, | |
1601 | pos, buf, bufsz); | |
c341ddb2 | 1602 | } |
b03d7d0f | 1603 | return pos; |
c341ddb2 WYG |
1604 | } |
1605 | ||
c341ddb2 WYG |
1606 | #define DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES (20) |
1607 | ||
b03d7d0f WYG |
1608 | int iwl3945_dump_nic_event_log(struct iwl_priv *priv, bool full_log, |
1609 | char **buf, bool display) | |
b481de9c | 1610 | { |
b481de9c ZY |
1611 | u32 base; /* SRAM byte address of event log header */ |
1612 | u32 capacity; /* event log capacity in # entries */ | |
1613 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
1614 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
1615 | u32 next_entry; /* index of next entry to be written by uCode */ | |
1616 | u32 size; /* # entries that we'll print */ | |
b03d7d0f WYG |
1617 | int pos = 0; |
1618 | size_t bufsz = 0; | |
b481de9c ZY |
1619 | |
1620 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
bb8c093b | 1621 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 1622 | IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); |
937c397e | 1623 | return -EINVAL; |
b481de9c ZY |
1624 | } |
1625 | ||
b481de9c | 1626 | /* event log header */ |
5d49f498 AK |
1627 | capacity = iwl_read_targ_mem(priv, base); |
1628 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
1629 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
1630 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
b481de9c | 1631 | |
678b385d | 1632 | if (capacity > priv->cfg->max_event_log_size) { |
84c40692 | 1633 | IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n", |
678b385d WYG |
1634 | capacity, priv->cfg->max_event_log_size); |
1635 | capacity = priv->cfg->max_event_log_size; | |
84c40692 BC |
1636 | } |
1637 | ||
678b385d | 1638 | if (next_entry > priv->cfg->max_event_log_size) { |
84c40692 | 1639 | IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n", |
678b385d WYG |
1640 | next_entry, priv->cfg->max_event_log_size); |
1641 | next_entry = priv->cfg->max_event_log_size; | |
84c40692 BC |
1642 | } |
1643 | ||
b481de9c ZY |
1644 | size = num_wraps ? capacity : next_entry; |
1645 | ||
1646 | /* bail out if nothing in log */ | |
1647 | if (size == 0) { | |
15b1687c | 1648 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); |
b03d7d0f | 1649 | return pos; |
b481de9c ZY |
1650 | } |
1651 | ||
c341ddb2 | 1652 | #ifdef CONFIG_IWLWIFI_DEBUG |
521d9bce | 1653 | if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log) |
c341ddb2 WYG |
1654 | size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES) |
1655 | ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size; | |
1656 | #else | |
1657 | size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES) | |
1658 | ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size; | |
1659 | #endif | |
1660 | ||
1661 | IWL_ERR(priv, "Start IWL Event Log Dump: display last %d count\n", | |
1662 | size); | |
b481de9c | 1663 | |
c341ddb2 | 1664 | #ifdef CONFIG_IWLWIFI_DEBUG |
b03d7d0f WYG |
1665 | if (display) { |
1666 | if (full_log) | |
1667 | bufsz = capacity * 48; | |
1668 | else | |
1669 | bufsz = size * 48; | |
1670 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
1671 | if (!*buf) | |
937c397e | 1672 | return -ENOMEM; |
b03d7d0f | 1673 | } |
c341ddb2 WYG |
1674 | if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) { |
1675 | /* if uCode has wrapped back to top of log, | |
1676 | * start at the oldest entry, | |
1677 | * i.e the next one that uCode would fill. | |
1678 | */ | |
1679 | if (num_wraps) | |
b03d7d0f WYG |
1680 | pos = iwl3945_print_event_log(priv, next_entry, |
1681 | capacity - next_entry, mode, | |
1682 | pos, buf, bufsz); | |
c341ddb2 WYG |
1683 | |
1684 | /* (then/else) start at top of log */ | |
b03d7d0f WYG |
1685 | pos = iwl3945_print_event_log(priv, 0, next_entry, mode, |
1686 | pos, buf, bufsz); | |
c341ddb2 | 1687 | } else |
b03d7d0f WYG |
1688 | pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps, |
1689 | next_entry, size, mode, | |
1690 | pos, buf, bufsz); | |
b7a79404 | 1691 | #else |
b03d7d0f WYG |
1692 | pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps, |
1693 | next_entry, size, mode, | |
1694 | pos, buf, bufsz); | |
c341ddb2 | 1695 | #endif |
b03d7d0f | 1696 | return pos; |
b7a79404 RC |
1697 | } |
1698 | ||
4a8a4322 | 1699 | static void iwl3945_irq_tasklet(struct iwl_priv *priv) |
b481de9c ZY |
1700 | { |
1701 | u32 inta, handled = 0; | |
1702 | u32 inta_fh; | |
1703 | unsigned long flags; | |
d08853a3 | 1704 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
1705 | u32 inta_mask; |
1706 | #endif | |
1707 | ||
1708 | spin_lock_irqsave(&priv->lock, flags); | |
1709 | ||
1710 | /* Ack/clear/reset pending uCode interrupts. | |
1711 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1712 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
5d49f498 AK |
1713 | inta = iwl_read32(priv, CSR_INT); |
1714 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
1715 | |
1716 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1717 | * Any new interrupts that happen after this, either while we're | |
1718 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
5d49f498 AK |
1719 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1720 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 1721 | |
d08853a3 | 1722 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1723 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
9fbab516 | 1724 | /* just for debug */ |
5d49f498 | 1725 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 1726 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
1727 | inta, inta_mask, inta_fh); |
1728 | } | |
1729 | #endif | |
1730 | ||
2f301227 ZY |
1731 | spin_unlock_irqrestore(&priv->lock, flags); |
1732 | ||
b481de9c ZY |
1733 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not |
1734 | * atomic, make sure that inta covers all the interrupts that | |
1735 | * we've discovered, even if FH interrupt came in just after | |
1736 | * reading CSR_INT. */ | |
6f83eaa1 | 1737 | if (inta_fh & CSR39_FH_INT_RX_MASK) |
b481de9c | 1738 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 1739 | if (inta_fh & CSR39_FH_INT_TX_MASK) |
b481de9c ZY |
1740 | inta |= CSR_INT_BIT_FH_TX; |
1741 | ||
1742 | /* Now service all interrupt bits discovered above. */ | |
1743 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1744 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
b481de9c ZY |
1745 | |
1746 | /* Tell the device to stop sending interrupts */ | |
ed3b932e | 1747 | iwl_disable_interrupts(priv); |
b481de9c | 1748 | |
86ddbf62 | 1749 | priv->isr_stats.hw++; |
8ccde88a | 1750 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1751 | |
1752 | handled |= CSR_INT_BIT_HW_ERR; | |
1753 | ||
b481de9c ZY |
1754 | return; |
1755 | } | |
1756 | ||
d08853a3 | 1757 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1758 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
b481de9c | 1759 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
86ddbf62 | 1760 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 1761 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 1762 | "the frame/frames.\n"); |
86ddbf62 AK |
1763 | priv->isr_stats.sch++; |
1764 | } | |
b481de9c ZY |
1765 | |
1766 | /* Alive notification via Rx interrupt will do the real work */ | |
86ddbf62 | 1767 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 1768 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
86ddbf62 AK |
1769 | priv->isr_stats.alive++; |
1770 | } | |
b481de9c ZY |
1771 | } |
1772 | #endif | |
1773 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1774 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1775 | |
b481de9c ZY |
1776 | /* Error detected by uCode */ |
1777 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1778 | IWL_ERR(priv, "Microcode SW error detected. " |
1779 | "Restarting 0x%X.\n", inta); | |
86ddbf62 AK |
1780 | priv->isr_stats.sw++; |
1781 | priv->isr_stats.sw_err = inta; | |
8ccde88a | 1782 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1783 | handled |= CSR_INT_BIT_SW_ERR; |
1784 | } | |
1785 | ||
1786 | /* uCode wakes up after power-down sleep */ | |
1787 | if (inta & CSR_INT_BIT_WAKEUP) { | |
e1623446 | 1788 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
141c43a3 | 1789 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
4f3602c8 SO |
1790 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); |
1791 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1792 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1793 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1794 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1795 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c | 1796 | |
86ddbf62 | 1797 | priv->isr_stats.wakeup++; |
b481de9c ZY |
1798 | handled |= CSR_INT_BIT_WAKEUP; |
1799 | } | |
1800 | ||
1801 | /* All uCode command responses, including Tx command responses, | |
1802 | * Rx "responses" (frame-received notification), and other | |
1803 | * notifications from uCode come through here*/ | |
1804 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
bb8c093b | 1805 | iwl3945_rx_handle(priv); |
86ddbf62 | 1806 | priv->isr_stats.rx++; |
b481de9c ZY |
1807 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1808 | } | |
1809 | ||
1810 | if (inta & CSR_INT_BIT_FH_TX) { | |
e1623446 | 1811 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); |
86ddbf62 | 1812 | priv->isr_stats.tx++; |
b481de9c | 1813 | |
5d49f498 | 1814 | iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); |
a8b50a0a MA |
1815 | iwl_write_direct32(priv, FH39_TCSR_CREDIT |
1816 | (FH39_SRVC_CHNL), 0x0); | |
b481de9c ZY |
1817 | handled |= CSR_INT_BIT_FH_TX; |
1818 | } | |
1819 | ||
86ddbf62 | 1820 | if (inta & ~handled) { |
15b1687c | 1821 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
86ddbf62 AK |
1822 | priv->isr_stats.unhandled++; |
1823 | } | |
b481de9c | 1824 | |
40cefda9 | 1825 | if (inta & ~priv->inta_mask) { |
39aadf8c | 1826 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1827 | inta & ~priv->inta_mask); |
39aadf8c | 1828 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1829 | } |
1830 | ||
1831 | /* Re-enable all interrupts */ | |
0359facc MA |
1832 | /* only Re-enable if disabled by irq */ |
1833 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
ed3b932e | 1834 | iwl_enable_interrupts(priv); |
b481de9c | 1835 | |
d08853a3 | 1836 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1837 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
5d49f498 AK |
1838 | inta = iwl_read32(priv, CSR_INT); |
1839 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1840 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1841 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1842 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1843 | } | |
1844 | #endif | |
b481de9c ZY |
1845 | } |
1846 | ||
14023641 AK |
1847 | static int iwl3945_get_single_channel_for_scan(struct iwl_priv *priv, |
1848 | struct ieee80211_vif *vif, | |
1849 | enum ieee80211_band band, | |
1850 | struct iwl3945_scan_channel *scan_ch) | |
1851 | { | |
1852 | const struct ieee80211_supported_band *sband; | |
1853 | u16 passive_dwell = 0; | |
1854 | u16 active_dwell = 0; | |
1855 | int added = 0; | |
1856 | u8 channel = 0; | |
1857 | ||
1858 | sband = iwl_get_hw_mode(priv, band); | |
1859 | if (!sband) { | |
1860 | IWL_ERR(priv, "invalid band\n"); | |
1861 | return added; | |
1862 | } | |
1863 | ||
1864 | active_dwell = iwl_get_active_dwell_time(priv, band, 0); | |
1865 | passive_dwell = iwl_get_passive_dwell_time(priv, band, vif); | |
1866 | ||
1867 | if (passive_dwell <= active_dwell) | |
1868 | passive_dwell = active_dwell + 1; | |
1869 | ||
1870 | ||
1871 | channel = iwl_get_single_channel_number(priv, band); | |
1872 | ||
1873 | if (channel) { | |
1874 | scan_ch->channel = channel; | |
1875 | scan_ch->type = 0; /* passive */ | |
1876 | scan_ch->active_dwell = cpu_to_le16(active_dwell); | |
1877 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
1878 | /* Set txpower levels to defaults */ | |
1879 | scan_ch->tpc.dsp_atten = 110; | |
1880 | if (band == IEEE80211_BAND_5GHZ) | |
1881 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; | |
1882 | else | |
1883 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
1884 | added++; | |
1885 | } else | |
1886 | IWL_ERR(priv, "no valid channel found\n"); | |
1887 | return added; | |
1888 | } | |
1889 | ||
4a8a4322 | 1890 | static int iwl3945_get_channels_for_scan(struct iwl_priv *priv, |
8318d78a | 1891 | enum ieee80211_band band, |
f9340520 | 1892 | u8 is_active, u8 n_probes, |
1dda6d28 JB |
1893 | struct iwl3945_scan_channel *scan_ch, |
1894 | struct ieee80211_vif *vif) | |
b481de9c | 1895 | { |
4e05c234 | 1896 | struct ieee80211_channel *chan; |
8318d78a | 1897 | const struct ieee80211_supported_band *sband; |
d20b3c65 | 1898 | const struct iwl_channel_info *ch_info; |
b481de9c ZY |
1899 | u16 passive_dwell = 0; |
1900 | u16 active_dwell = 0; | |
1901 | int added, i; | |
1902 | ||
cbba18c6 | 1903 | sband = iwl_get_hw_mode(priv, band); |
8318d78a | 1904 | if (!sband) |
b481de9c ZY |
1905 | return 0; |
1906 | ||
77fecfb8 | 1907 | active_dwell = iwl_get_active_dwell_time(priv, band, n_probes); |
1dda6d28 | 1908 | passive_dwell = iwl_get_passive_dwell_time(priv, band, vif); |
b481de9c | 1909 | |
8f4807a1 AK |
1910 | if (passive_dwell <= active_dwell) |
1911 | passive_dwell = active_dwell + 1; | |
1912 | ||
4e05c234 JB |
1913 | for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) { |
1914 | chan = priv->scan_request->channels[i]; | |
1915 | ||
1916 | if (chan->band != band) | |
182e2e66 JB |
1917 | continue; |
1918 | ||
4e05c234 | 1919 | scan_ch->channel = chan->hw_value; |
b481de9c | 1920 | |
e6148917 | 1921 | ch_info = iwl_get_channel_info(priv, band, scan_ch->channel); |
b481de9c | 1922 | if (!is_channel_valid(ch_info)) { |
e1623446 | 1923 | IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n", |
b481de9c ZY |
1924 | scan_ch->channel); |
1925 | continue; | |
1926 | } | |
1927 | ||
011a0330 AK |
1928 | scan_ch->active_dwell = cpu_to_le16(active_dwell); |
1929 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
1930 | /* If passive , set up for auto-switch | |
1931 | * and use long active_dwell time. | |
1932 | */ | |
b481de9c | 1933 | if (!is_active || is_channel_passive(ch_info) || |
4e05c234 | 1934 | (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) { |
b481de9c | 1935 | scan_ch->type = 0; /* passive */ |
011a0330 AK |
1936 | if (IWL_UCODE_API(priv->ucode_ver) == 1) |
1937 | scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1); | |
1938 | } else { | |
b481de9c | 1939 | scan_ch->type = 1; /* active */ |
011a0330 | 1940 | } |
b481de9c | 1941 | |
011a0330 AK |
1942 | /* Set direct probe bits. These may be used both for active |
1943 | * scan channels (probes gets sent right away), | |
1944 | * or for passive channels (probes get se sent only after | |
1945 | * hearing clear Rx packet).*/ | |
1946 | if (IWL_UCODE_API(priv->ucode_ver) >= 2) { | |
1947 | if (n_probes) | |
0d21044e | 1948 | scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes); |
011a0330 AK |
1949 | } else { |
1950 | /* uCode v1 does not allow setting direct probe bits on | |
1951 | * passive channel. */ | |
1952 | if ((scan_ch->type & 1) && n_probes) | |
0d21044e | 1953 | scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes); |
011a0330 | 1954 | } |
b481de9c | 1955 | |
9fbab516 | 1956 | /* Set txpower levels to defaults */ |
b481de9c ZY |
1957 | scan_ch->tpc.dsp_atten = 110; |
1958 | /* scan_pwr_info->tpc.dsp_atten; */ | |
1959 | ||
1960 | /*scan_pwr_info->tpc.tx_gain; */ | |
8318d78a | 1961 | if (band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
1962 | scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3; |
1963 | else { | |
1964 | scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3)); | |
1965 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
9fbab516 | 1966 | * power level: |
8a1b0245 | 1967 | * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3; |
b481de9c ZY |
1968 | */ |
1969 | } | |
1970 | ||
e1623446 | 1971 | IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n", |
b481de9c ZY |
1972 | scan_ch->channel, |
1973 | (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE", | |
1974 | (scan_ch->type & 1) ? | |
1975 | active_dwell : passive_dwell); | |
1976 | ||
1977 | scan_ch++; | |
1978 | added++; | |
1979 | } | |
1980 | ||
91dd6c27 | 1981 | IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added); |
b481de9c ZY |
1982 | return added; |
1983 | } | |
1984 | ||
4a8a4322 | 1985 | static void iwl3945_init_hw_rates(struct iwl_priv *priv, |
b481de9c ZY |
1986 | struct ieee80211_rate *rates) |
1987 | { | |
1988 | int i; | |
1989 | ||
8e1a53c6 | 1990 | for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) { |
8318d78a JB |
1991 | rates[i].bitrate = iwl3945_rates[i].ieee * 5; |
1992 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
1993 | rates[i].hw_value_short = i; | |
1994 | rates[i].flags = 0; | |
d9829a67 | 1995 | if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) { |
b481de9c | 1996 | /* |
8318d78a | 1997 | * If CCK != 1M then set short preamble rate flag. |
b481de9c | 1998 | */ |
bb8c093b | 1999 | rates[i].flags |= (iwl3945_rates[i].plcp == 10) ? |
8318d78a | 2000 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
b481de9c | 2001 | } |
b481de9c ZY |
2002 | } |
2003 | } | |
2004 | ||
b481de9c ZY |
2005 | /****************************************************************************** |
2006 | * | |
2007 | * uCode download functions | |
2008 | * | |
2009 | ******************************************************************************/ | |
2010 | ||
4a8a4322 | 2011 | static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 2012 | { |
98c92211 TW |
2013 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
2014 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
2015 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
2016 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
2017 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
2018 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
2019 | } |
2020 | ||
2021 | /** | |
bb8c093b | 2022 | * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host, |
b481de9c ZY |
2023 | * looking at all data. |
2024 | */ | |
4a8a4322 | 2025 | static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
2026 | { |
2027 | u32 val; | |
2028 | u32 save_len = len; | |
2029 | int rc = 0; | |
2030 | u32 errcnt; | |
2031 | ||
e1623446 | 2032 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b481de9c | 2033 | |
5d49f498 | 2034 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 2035 | IWL39_RTC_INST_LOWER_BOUND); |
b481de9c ZY |
2036 | |
2037 | errcnt = 0; | |
2038 | for (; len > 0; len -= sizeof(u32), image++) { | |
2039 | /* read data comes through single port, auto-incr addr */ | |
2040 | /* NOTE: Use the debugless read so we don't flood kernel log | |
2041 | * if IWL_DL_IO is set */ | |
5d49f498 | 2042 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c | 2043 | if (val != le32_to_cpu(*image)) { |
15b1687c | 2044 | IWL_ERR(priv, "uCode INST section is invalid at " |
b481de9c ZY |
2045 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
2046 | save_len - len, val, le32_to_cpu(*image)); | |
2047 | rc = -EIO; | |
2048 | errcnt++; | |
2049 | if (errcnt >= 20) | |
2050 | break; | |
2051 | } | |
2052 | } | |
2053 | ||
b481de9c ZY |
2054 | |
2055 | if (!errcnt) | |
e1623446 TW |
2056 | IWL_DEBUG_INFO(priv, |
2057 | "ucode image in INSTRUCTION memory is good\n"); | |
b481de9c ZY |
2058 | |
2059 | return rc; | |
2060 | } | |
2061 | ||
2062 | ||
2063 | /** | |
bb8c093b | 2064 | * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host, |
b481de9c ZY |
2065 | * using sample data 100 bytes apart. If these sample points are good, |
2066 | * it's a pretty good bet that everything between them is good, too. | |
2067 | */ | |
4a8a4322 | 2068 | static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len) |
b481de9c ZY |
2069 | { |
2070 | u32 val; | |
2071 | int rc = 0; | |
2072 | u32 errcnt = 0; | |
2073 | u32 i; | |
2074 | ||
e1623446 | 2075 | IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); |
b481de9c | 2076 | |
b481de9c ZY |
2077 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { |
2078 | /* read data comes through single port, auto-incr addr */ | |
2079 | /* NOTE: Use the debugless read so we don't flood kernel log | |
2080 | * if IWL_DL_IO is set */ | |
5d49f498 | 2081 | iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, |
250bdd21 | 2082 | i + IWL39_RTC_INST_LOWER_BOUND); |
5d49f498 | 2083 | val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b481de9c ZY |
2084 | if (val != le32_to_cpu(*image)) { |
2085 | #if 0 /* Enable this if you want to see details */ | |
15b1687c | 2086 | IWL_ERR(priv, "uCode INST section is invalid at " |
b481de9c ZY |
2087 | "offset 0x%x, is 0x%x, s/b 0x%x\n", |
2088 | i, val, *image); | |
2089 | #endif | |
2090 | rc = -EIO; | |
2091 | errcnt++; | |
2092 | if (errcnt >= 3) | |
2093 | break; | |
2094 | } | |
2095 | } | |
2096 | ||
b481de9c ZY |
2097 | return rc; |
2098 | } | |
2099 | ||
2100 | ||
2101 | /** | |
bb8c093b | 2102 | * iwl3945_verify_ucode - determine which instruction image is in SRAM, |
b481de9c ZY |
2103 | * and verify its contents |
2104 | */ | |
4a8a4322 | 2105 | static int iwl3945_verify_ucode(struct iwl_priv *priv) |
b481de9c ZY |
2106 | { |
2107 | __le32 *image; | |
2108 | u32 len; | |
2109 | int rc = 0; | |
2110 | ||
2111 | /* Try bootstrap */ | |
2112 | image = (__le32 *)priv->ucode_boot.v_addr; | |
2113 | len = priv->ucode_boot.len; | |
bb8c093b | 2114 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2115 | if (rc == 0) { |
e1623446 | 2116 | IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n"); |
b481de9c ZY |
2117 | return 0; |
2118 | } | |
2119 | ||
2120 | /* Try initialize */ | |
2121 | image = (__le32 *)priv->ucode_init.v_addr; | |
2122 | len = priv->ucode_init.len; | |
bb8c093b | 2123 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2124 | if (rc == 0) { |
e1623446 | 2125 | IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n"); |
b481de9c ZY |
2126 | return 0; |
2127 | } | |
2128 | ||
2129 | /* Try runtime/protocol */ | |
2130 | image = (__le32 *)priv->ucode_code.v_addr; | |
2131 | len = priv->ucode_code.len; | |
bb8c093b | 2132 | rc = iwl3945_verify_inst_sparse(priv, image, len); |
b481de9c | 2133 | if (rc == 0) { |
e1623446 | 2134 | IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n"); |
b481de9c ZY |
2135 | return 0; |
2136 | } | |
2137 | ||
15b1687c | 2138 | IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); |
b481de9c | 2139 | |
9fbab516 BC |
2140 | /* Since nothing seems to match, show first several data entries in |
2141 | * instruction SRAM, so maybe visual inspection will give a clue. | |
2142 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
b481de9c ZY |
2143 | image = (__le32 *)priv->ucode_boot.v_addr; |
2144 | len = priv->ucode_boot.len; | |
bb8c093b | 2145 | rc = iwl3945_verify_inst_full(priv, image, len); |
b481de9c ZY |
2146 | |
2147 | return rc; | |
2148 | } | |
2149 | ||
4a8a4322 | 2150 | static void iwl3945_nic_start(struct iwl_priv *priv) |
b481de9c ZY |
2151 | { |
2152 | /* Remove all resets to allow NIC to operate */ | |
5d49f498 | 2153 | iwl_write32(priv, CSR_RESET, 0); |
b481de9c ZY |
2154 | } |
2155 | ||
93b1a2f9 JB |
2156 | #define IWL3945_UCODE_GET(item) \ |
2157 | static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode)\ | |
2158 | { \ | |
2159 | return le32_to_cpu(ucode->u.v1.item); \ | |
2160 | } | |
2161 | ||
2162 | static u32 iwl3945_ucode_get_header_size(u32 api_ver) | |
2163 | { | |
22adba2a | 2164 | return 24; |
93b1a2f9 JB |
2165 | } |
2166 | ||
2167 | static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode) | |
2168 | { | |
2169 | return (u8 *) ucode->u.v1.data; | |
2170 | } | |
2171 | ||
2172 | IWL3945_UCODE_GET(inst_size); | |
2173 | IWL3945_UCODE_GET(data_size); | |
2174 | IWL3945_UCODE_GET(init_size); | |
2175 | IWL3945_UCODE_GET(init_data_size); | |
2176 | IWL3945_UCODE_GET(boot_size); | |
2177 | ||
b481de9c | 2178 | /** |
bb8c093b | 2179 | * iwl3945_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
2180 | * |
2181 | * Copy into buffers for card to fetch via bus-mastering | |
2182 | */ | |
4a8a4322 | 2183 | static int iwl3945_read_ucode(struct iwl_priv *priv) |
b481de9c | 2184 | { |
cc0f555d | 2185 | const struct iwl_ucode_header *ucode; |
a0987a8d | 2186 | int ret = -EINVAL, index; |
b481de9c ZY |
2187 | const struct firmware *ucode_raw; |
2188 | /* firmware file name contains uCode/driver compatibility version */ | |
a0987a8d RC |
2189 | const char *name_pre = priv->cfg->fw_name_pre; |
2190 | const unsigned int api_max = priv->cfg->ucode_api_max; | |
2191 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
2192 | char buf[25]; | |
b481de9c ZY |
2193 | u8 *src; |
2194 | size_t len; | |
a0987a8d | 2195 | u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size; |
b481de9c ZY |
2196 | |
2197 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
2198 | * request_firmware() is synchronous, file is in memory on return. */ | |
a0987a8d RC |
2199 | for (index = api_max; index >= api_min; index--) { |
2200 | sprintf(buf, "%s%u%s", name_pre, index, ".ucode"); | |
2201 | ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); | |
2202 | if (ret < 0) { | |
15b1687c | 2203 | IWL_ERR(priv, "%s firmware file req failed: %d\n", |
a0987a8d RC |
2204 | buf, ret); |
2205 | if (ret == -ENOENT) | |
2206 | continue; | |
2207 | else | |
2208 | goto error; | |
2209 | } else { | |
2210 | if (index < api_max) | |
15b1687c WT |
2211 | IWL_ERR(priv, "Loaded firmware %s, " |
2212 | "which is deprecated. " | |
2213 | " Please use API v%u instead.\n", | |
a0987a8d | 2214 | buf, api_max); |
e1623446 TW |
2215 | IWL_DEBUG_INFO(priv, "Got firmware '%s' file " |
2216 | "(%zd bytes) from disk\n", | |
a0987a8d RC |
2217 | buf, ucode_raw->size); |
2218 | break; | |
2219 | } | |
b481de9c ZY |
2220 | } |
2221 | ||
a0987a8d RC |
2222 | if (ret < 0) |
2223 | goto error; | |
b481de9c ZY |
2224 | |
2225 | /* Make sure that we got at least our header! */ | |
93b1a2f9 | 2226 | if (ucode_raw->size < iwl3945_ucode_get_header_size(1)) { |
15b1687c | 2227 | IWL_ERR(priv, "File size way too small!\n"); |
90e759d1 | 2228 | ret = -EINVAL; |
b481de9c ZY |
2229 | goto err_release; |
2230 | } | |
2231 | ||
2232 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 2233 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 2234 | |
c02b3acd | 2235 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 2236 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
93b1a2f9 JB |
2237 | inst_size = iwl3945_ucode_get_inst_size(ucode); |
2238 | data_size = iwl3945_ucode_get_data_size(ucode); | |
2239 | init_size = iwl3945_ucode_get_init_size(ucode); | |
2240 | init_data_size = iwl3945_ucode_get_init_data_size(ucode); | |
2241 | boot_size = iwl3945_ucode_get_boot_size(ucode); | |
2242 | src = iwl3945_ucode_get_data(ucode); | |
b481de9c | 2243 | |
a0987a8d RC |
2244 | /* api_ver should match the api version forming part of the |
2245 | * firmware filename ... but we don't check for that and only rely | |
877d0310 | 2246 | * on the API version read from firmware header from here on forward */ |
a0987a8d RC |
2247 | |
2248 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 2249 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
2250 | "Driver supports v%u, firmware is v%u.\n", |
2251 | api_max, api_ver); | |
2252 | priv->ucode_ver = 0; | |
2253 | ret = -EINVAL; | |
2254 | goto err_release; | |
2255 | } | |
2256 | if (api_ver != api_max) | |
15b1687c | 2257 | IWL_ERR(priv, "Firmware has old API version. Expected %u, " |
a0987a8d RC |
2258 | "got %u. New firmware can be obtained " |
2259 | "from http://www.intellinuxwireless.org.\n", | |
2260 | api_max, api_ver); | |
2261 | ||
978785a3 TW |
2262 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
2263 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
2264 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2265 | IWL_UCODE_API(priv->ucode_ver), | |
2266 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
2267 | ||
5ebeb5a6 RC |
2268 | snprintf(priv->hw->wiphy->fw_version, |
2269 | sizeof(priv->hw->wiphy->fw_version), | |
2270 | "%u.%u.%u.%u", | |
2271 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
2272 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2273 | IWL_UCODE_API(priv->ucode_ver), | |
2274 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
2275 | ||
e1623446 | 2276 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
a0987a8d | 2277 | priv->ucode_ver); |
e1623446 TW |
2278 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n", |
2279 | inst_size); | |
2280 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n", | |
2281 | data_size); | |
2282 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n", | |
2283 | init_size); | |
2284 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n", | |
2285 | init_data_size); | |
2286 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n", | |
2287 | boot_size); | |
b481de9c | 2288 | |
a0987a8d | 2289 | |
b481de9c | 2290 | /* Verify size of file vs. image size info in file's header */ |
93b1a2f9 | 2291 | if (ucode_raw->size != iwl3945_ucode_get_header_size(api_ver) + |
b481de9c ZY |
2292 | inst_size + data_size + init_size + |
2293 | init_data_size + boot_size) { | |
2294 | ||
cc0f555d JS |
2295 | IWL_DEBUG_INFO(priv, |
2296 | "uCode file size %zd does not match expected size\n", | |
2297 | ucode_raw->size); | |
90e759d1 | 2298 | ret = -EINVAL; |
b481de9c ZY |
2299 | goto err_release; |
2300 | } | |
2301 | ||
2302 | /* Verify that uCode images will fit in card's SRAM */ | |
250bdd21 | 2303 | if (inst_size > IWL39_MAX_INST_SIZE) { |
e1623446 | 2304 | IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n", |
90e759d1 TW |
2305 | inst_size); |
2306 | ret = -EINVAL; | |
b481de9c ZY |
2307 | goto err_release; |
2308 | } | |
2309 | ||
250bdd21 | 2310 | if (data_size > IWL39_MAX_DATA_SIZE) { |
e1623446 | 2311 | IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n", |
90e759d1 TW |
2312 | data_size); |
2313 | ret = -EINVAL; | |
b481de9c ZY |
2314 | goto err_release; |
2315 | } | |
250bdd21 | 2316 | if (init_size > IWL39_MAX_INST_SIZE) { |
e1623446 TW |
2317 | IWL_DEBUG_INFO(priv, |
2318 | "uCode init instr len %d too large to fit in\n", | |
90e759d1 TW |
2319 | init_size); |
2320 | ret = -EINVAL; | |
b481de9c ZY |
2321 | goto err_release; |
2322 | } | |
250bdd21 | 2323 | if (init_data_size > IWL39_MAX_DATA_SIZE) { |
e1623446 TW |
2324 | IWL_DEBUG_INFO(priv, |
2325 | "uCode init data len %d too large to fit in\n", | |
90e759d1 TW |
2326 | init_data_size); |
2327 | ret = -EINVAL; | |
b481de9c ZY |
2328 | goto err_release; |
2329 | } | |
250bdd21 | 2330 | if (boot_size > IWL39_MAX_BSM_SIZE) { |
e1623446 TW |
2331 | IWL_DEBUG_INFO(priv, |
2332 | "uCode boot instr len %d too large to fit in\n", | |
90e759d1 TW |
2333 | boot_size); |
2334 | ret = -EINVAL; | |
b481de9c ZY |
2335 | goto err_release; |
2336 | } | |
2337 | ||
2338 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
2339 | ||
2340 | /* Runtime instructions and 2 copies of data: | |
2341 | * 1) unmodified from disk | |
2342 | * 2) backup cache for save/restore during power-downs */ | |
2343 | priv->ucode_code.len = inst_size; | |
98c92211 | 2344 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
2345 | |
2346 | priv->ucode_data.len = data_size; | |
98c92211 | 2347 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
2348 | |
2349 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 2350 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 2351 | |
90e759d1 TW |
2352 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
2353 | !priv->ucode_data_backup.v_addr) | |
2354 | goto err_pci_alloc; | |
b481de9c ZY |
2355 | |
2356 | /* Initialization instructions and data */ | |
90e759d1 TW |
2357 | if (init_size && init_data_size) { |
2358 | priv->ucode_init.len = init_size; | |
98c92211 | 2359 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
2360 | |
2361 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 2362 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
2363 | |
2364 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
2365 | goto err_pci_alloc; | |
2366 | } | |
b481de9c ZY |
2367 | |
2368 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
2369 | if (boot_size) { |
2370 | priv->ucode_boot.len = boot_size; | |
98c92211 | 2371 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 2372 | |
90e759d1 TW |
2373 | if (!priv->ucode_boot.v_addr) |
2374 | goto err_pci_alloc; | |
2375 | } | |
b481de9c ZY |
2376 | |
2377 | /* Copy images into buffers for card's bus-master reads ... */ | |
2378 | ||
2379 | /* Runtime instructions (first block of data in file) */ | |
cc0f555d | 2380 | len = inst_size; |
e1623446 TW |
2381 | IWL_DEBUG_INFO(priv, |
2382 | "Copying (but not loading) uCode instr len %zd\n", len); | |
b481de9c | 2383 | memcpy(priv->ucode_code.v_addr, src, len); |
cc0f555d JS |
2384 | src += len; |
2385 | ||
e1623446 | 2386 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
2387 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
2388 | ||
2389 | /* Runtime data (2nd block) | |
bb8c093b | 2390 | * NOTE: Copy into backup buffer will be done in iwl3945_up() */ |
cc0f555d | 2391 | len = data_size; |
e1623446 TW |
2392 | IWL_DEBUG_INFO(priv, |
2393 | "Copying (but not loading) uCode data len %zd\n", len); | |
b481de9c ZY |
2394 | memcpy(priv->ucode_data.v_addr, src, len); |
2395 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
cc0f555d | 2396 | src += len; |
b481de9c ZY |
2397 | |
2398 | /* Initialization instructions (3rd block) */ | |
2399 | if (init_size) { | |
cc0f555d | 2400 | len = init_size; |
e1623446 TW |
2401 | IWL_DEBUG_INFO(priv, |
2402 | "Copying (but not loading) init instr len %zd\n", len); | |
b481de9c | 2403 | memcpy(priv->ucode_init.v_addr, src, len); |
cc0f555d | 2404 | src += len; |
b481de9c ZY |
2405 | } |
2406 | ||
2407 | /* Initialization data (4th block) */ | |
2408 | if (init_data_size) { | |
cc0f555d | 2409 | len = init_data_size; |
e1623446 TW |
2410 | IWL_DEBUG_INFO(priv, |
2411 | "Copying (but not loading) init data len %zd\n", len); | |
b481de9c | 2412 | memcpy(priv->ucode_init_data.v_addr, src, len); |
cc0f555d | 2413 | src += len; |
b481de9c ZY |
2414 | } |
2415 | ||
2416 | /* Bootstrap instructions (5th block) */ | |
cc0f555d | 2417 | len = boot_size; |
e1623446 TW |
2418 | IWL_DEBUG_INFO(priv, |
2419 | "Copying (but not loading) boot instr len %zd\n", len); | |
b481de9c ZY |
2420 | memcpy(priv->ucode_boot.v_addr, src, len); |
2421 | ||
2422 | /* We have our copies now, allow OS release its copies */ | |
2423 | release_firmware(ucode_raw); | |
2424 | return 0; | |
2425 | ||
2426 | err_pci_alloc: | |
15b1687c | 2427 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
90e759d1 | 2428 | ret = -ENOMEM; |
bb8c093b | 2429 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
2430 | |
2431 | err_release: | |
2432 | release_firmware(ucode_raw); | |
2433 | ||
2434 | error: | |
90e759d1 | 2435 | return ret; |
b481de9c ZY |
2436 | } |
2437 | ||
2438 | ||
2439 | /** | |
bb8c093b | 2440 | * iwl3945_set_ucode_ptrs - Set uCode address location |
b481de9c ZY |
2441 | * |
2442 | * Tell initialization uCode where to find runtime uCode. | |
2443 | * | |
2444 | * BSM registers initially contain pointers to initialization uCode. | |
2445 | * We need to replace them to load runtime uCode inst and data, | |
2446 | * and to save runtime data when powering down. | |
2447 | */ | |
4a8a4322 | 2448 | static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv) |
b481de9c ZY |
2449 | { |
2450 | dma_addr_t pinst; | |
2451 | dma_addr_t pdata; | |
b481de9c ZY |
2452 | |
2453 | /* bits 31:0 for 3945 */ | |
2454 | pinst = priv->ucode_code.p_addr; | |
2455 | pdata = priv->ucode_data_backup.p_addr; | |
2456 | ||
b481de9c | 2457 | /* Tell bootstrap uCode where to find image to load */ |
5d49f498 AK |
2458 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); |
2459 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
2460 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
b481de9c ZY |
2461 | priv->ucode_data.len); |
2462 | ||
a96a27f9 | 2463 | /* Inst byte count must be last to set up, bit 31 signals uCode |
b481de9c | 2464 | * that all new ptr/size info is in place */ |
5d49f498 | 2465 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, |
b481de9c ZY |
2466 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); |
2467 | ||
e1623446 | 2468 | IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n"); |
b481de9c | 2469 | |
a8b50a0a | 2470 | return 0; |
b481de9c ZY |
2471 | } |
2472 | ||
2473 | /** | |
bb8c093b | 2474 | * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received |
b481de9c ZY |
2475 | * |
2476 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
2477 | * | |
b481de9c | 2478 | * Tell "initialize" uCode to go ahead and load the runtime uCode. |
9fbab516 | 2479 | */ |
4a8a4322 | 2480 | static void iwl3945_init_alive_start(struct iwl_priv *priv) |
b481de9c ZY |
2481 | { |
2482 | /* Check alive response for "valid" sign from uCode */ | |
2483 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
2484 | /* We had an error bringing up the hardware, so take it | |
2485 | * all the way back down so we can try again */ | |
e1623446 | 2486 | IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n"); |
b481de9c ZY |
2487 | goto restart; |
2488 | } | |
2489 | ||
2490 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
2491 | * This is a paranoid check, because we would not have gotten the | |
2492 | * "initialize" alive if code weren't properly loaded. */ | |
bb8c093b | 2493 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
2494 | /* Runtime instruction load was bad; |
2495 | * take it all the way back down so we can try again */ | |
e1623446 | 2496 | IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n"); |
b481de9c ZY |
2497 | goto restart; |
2498 | } | |
2499 | ||
2500 | /* Send pointers to protocol/runtime uCode image ... init code will | |
2501 | * load and launch runtime uCode, which will send us another "Alive" | |
2502 | * notification. */ | |
e1623446 | 2503 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
bb8c093b | 2504 | if (iwl3945_set_ucode_ptrs(priv)) { |
b481de9c ZY |
2505 | /* Runtime instruction load won't happen; |
2506 | * take it all the way back down so we can try again */ | |
e1623446 | 2507 | IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n"); |
b481de9c ZY |
2508 | goto restart; |
2509 | } | |
2510 | return; | |
2511 | ||
2512 | restart: | |
2513 | queue_work(priv->workqueue, &priv->restart); | |
2514 | } | |
2515 | ||
b481de9c | 2516 | /** |
bb8c093b | 2517 | * iwl3945_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 2518 | * from protocol/runtime uCode (initialization uCode's |
bb8c093b | 2519 | * Alive gets handled by iwl3945_init_alive_start()). |
b481de9c | 2520 | */ |
4a8a4322 | 2521 | static void iwl3945_alive_start(struct iwl_priv *priv) |
b481de9c | 2522 | { |
b481de9c ZY |
2523 | int thermal_spin = 0; |
2524 | u32 rfkill; | |
2525 | ||
e1623446 | 2526 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
2527 | |
2528 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
2529 | /* We had an error bringing up the hardware, so take it | |
2530 | * all the way back down so we can try again */ | |
e1623446 | 2531 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
2532 | goto restart; |
2533 | } | |
2534 | ||
2535 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
2536 | * This is a paranoid check, because we would not have gotten the | |
2537 | * "runtime" alive if code weren't properly loaded. */ | |
bb8c093b | 2538 | if (iwl3945_verify_ucode(priv)) { |
b481de9c ZY |
2539 | /* Runtime instruction load was bad; |
2540 | * take it all the way back down so we can try again */ | |
e1623446 | 2541 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
2542 | goto restart; |
2543 | } | |
2544 | ||
5d49f498 | 2545 | rfkill = iwl_read_prph(priv, APMG_RFKILL_REG); |
e1623446 | 2546 | IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill); |
b481de9c ZY |
2547 | |
2548 | if (rfkill & 0x1) { | |
2549 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a96a27f9 | 2550 | /* if RFKILL is not on, then wait for thermal |
b481de9c | 2551 | * sensor in adapter to kick in */ |
bb8c093b | 2552 | while (iwl3945_hw_get_temperature(priv) == 0) { |
b481de9c ZY |
2553 | thermal_spin++; |
2554 | udelay(10); | |
2555 | } | |
2556 | ||
2557 | if (thermal_spin) | |
e1623446 | 2558 | IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n", |
b481de9c ZY |
2559 | thermal_spin * 10); |
2560 | } else | |
2561 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
2562 | ||
9fbab516 | 2563 | /* After the ALIVE response, we can send commands to 3945 uCode */ |
b481de9c ZY |
2564 | set_bit(STATUS_ALIVE, &priv->status); |
2565 | ||
b74e31a9 WYG |
2566 | if (priv->cfg->ops->lib->recover_from_tx_stall) { |
2567 | /* Enable timer to monitor the driver queues */ | |
2568 | mod_timer(&priv->monitor_recover, | |
2569 | jiffies + | |
2570 | msecs_to_jiffies(priv->cfg->monitor_recover_period)); | |
2571 | } | |
2572 | ||
775a6e27 | 2573 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
2574 | return; |
2575 | ||
36d6825b | 2576 | ieee80211_wake_queues(priv->hw); |
b481de9c | 2577 | |
470ab2dd | 2578 | priv->active_rate = IWL_RATES_MASK; |
b481de9c | 2579 | |
4d6ccbf5 | 2580 | iwl_power_update_mode(priv, true); |
b481de9c | 2581 | |
8ccde88a | 2582 | if (iwl_is_associated(priv)) { |
bb8c093b | 2583 | struct iwl3945_rxon_cmd *active_rxon = |
8ccde88a | 2584 | (struct iwl3945_rxon_cmd *)(&priv->active_rxon); |
b481de9c | 2585 | |
8a9b9926 | 2586 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c ZY |
2587 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2588 | } else { | |
2589 | /* Initialize our rx_config data */ | |
1dda6d28 | 2590 | iwl_connection_init_rx_config(priv, NULL); |
b481de9c ZY |
2591 | } |
2592 | ||
9fbab516 | 2593 | /* Configure Bluetooth device coexistence support */ |
65b52bde | 2594 | priv->cfg->ops->hcmd->send_bt_config(priv); |
b481de9c ZY |
2595 | |
2596 | /* Configure the adapter for unassociated operation */ | |
e0158e61 | 2597 | iwlcore_commit_rxon(priv); |
b481de9c | 2598 | |
b481de9c ZY |
2599 | iwl3945_reg_txpower_periodic(priv); |
2600 | ||
e932a609 | 2601 | iwl_leds_init(priv); |
fe00b5a5 | 2602 | |
e1623446 | 2603 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 2604 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 2605 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 2606 | |
b481de9c ZY |
2607 | return; |
2608 | ||
2609 | restart: | |
2610 | queue_work(priv->workqueue, &priv->restart); | |
2611 | } | |
2612 | ||
4a8a4322 | 2613 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2614 | |
4a8a4322 | 2615 | static void __iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
2616 | { |
2617 | unsigned long flags; | |
2618 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
2619 | struct ieee80211_conf *conf = NULL; | |
2620 | ||
e1623446 | 2621 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c ZY |
2622 | |
2623 | conf = ieee80211_get_hw_conf(priv->hw); | |
2624 | ||
2625 | if (!exit_pending) | |
2626 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
2627 | ||
7e246191 | 2628 | /* Station information will now be cleared in device */ |
2c810ccd JB |
2629 | iwl_clear_ucode_stations(priv); |
2630 | iwl_dealloc_bcast_station(priv); | |
db125c78 | 2631 | iwl_clear_driver_stations(priv); |
b481de9c ZY |
2632 | |
2633 | /* Unblock any waiting calls */ | |
2634 | wake_up_interruptible_all(&priv->wait_command_queue); | |
2635 | ||
b481de9c ZY |
2636 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2637 | * exiting the module */ | |
2638 | if (!exit_pending) | |
2639 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2640 | ||
2641 | /* stop and reset the on-board processor */ | |
5d49f498 | 2642 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
2643 | |
2644 | /* tell the device to stop sending interrupts */ | |
0359facc | 2645 | spin_lock_irqsave(&priv->lock, flags); |
ed3b932e | 2646 | iwl_disable_interrupts(priv); |
0359facc MA |
2647 | spin_unlock_irqrestore(&priv->lock, flags); |
2648 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
2649 | |
2650 | if (priv->mac80211_registered) | |
2651 | ieee80211_stop_queues(priv->hw); | |
2652 | ||
bb8c093b | 2653 | /* If we have not previously called iwl3945_init() then |
6da3a13e | 2654 | * clear all bits but the RF Kill bits and return */ |
775a6e27 | 2655 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
2656 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2657 | STATUS_RF_KILL_HW | | |
9788864e RC |
2658 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2659 | STATUS_GEO_CONFIGURED | | |
ebef2008 AK |
2660 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
2661 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
2662 | goto exit; |
2663 | } | |
2664 | ||
6da3a13e | 2665 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 2666 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
2667 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2668 | STATUS_RF_KILL_HW | | |
9788864e RC |
2669 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2670 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2671 | test_bit(STATUS_FW_ERROR, &priv->status) << |
ebef2008 AK |
2672 | STATUS_FW_ERROR | |
2673 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2674 | STATUS_EXIT_PENDING; | |
b481de9c | 2675 | |
bb8c093b CH |
2676 | iwl3945_hw_txq_ctx_stop(priv); |
2677 | iwl3945_hw_rxq_stop(priv); | |
b481de9c | 2678 | |
309e731a BC |
2679 | /* Power-down device's busmaster DMA clocks */ |
2680 | iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
2681 | udelay(5); |
2682 | ||
4d2ccdb9 BC |
2683 | /* Stop the device, and put it in low power state */ |
2684 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
e9414b6b | 2685 | |
b481de9c | 2686 | exit: |
3d24a9f7 | 2687 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
2688 | |
2689 | if (priv->ibss_beacon) | |
2690 | dev_kfree_skb(priv->ibss_beacon); | |
2691 | priv->ibss_beacon = NULL; | |
2692 | ||
2693 | /* clear out any free frames */ | |
bb8c093b | 2694 | iwl3945_clear_free_frames(priv); |
b481de9c ZY |
2695 | } |
2696 | ||
4a8a4322 | 2697 | static void iwl3945_down(struct iwl_priv *priv) |
b481de9c ZY |
2698 | { |
2699 | mutex_lock(&priv->mutex); | |
bb8c093b | 2700 | __iwl3945_down(priv); |
b481de9c | 2701 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2702 | |
bb8c093b | 2703 | iwl3945_cancel_deferred_work(priv); |
b481de9c ZY |
2704 | } |
2705 | ||
2706 | #define MAX_HW_RESTARTS 5 | |
2707 | ||
4a8a4322 | 2708 | static int __iwl3945_up(struct iwl_priv *priv) |
b481de9c ZY |
2709 | { |
2710 | int rc, i; | |
2711 | ||
2c810ccd JB |
2712 | rc = iwl_alloc_bcast_station(priv, false); |
2713 | if (rc) | |
2714 | return rc; | |
2715 | ||
b481de9c | 2716 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { |
39aadf8c | 2717 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2718 | return -EIO; |
2719 | } | |
2720 | ||
e903fbd4 | 2721 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 2722 | IWL_ERR(priv, "ucode not available for device bring up\n"); |
e903fbd4 RC |
2723 | return -EIO; |
2724 | } | |
2725 | ||
e655b9f0 | 2726 | /* If platform's RF_KILL switch is NOT set to KILL */ |
5d49f498 | 2727 | if (iwl_read32(priv, CSR_GP_CNTRL) & |
e655b9f0 ZY |
2728 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
2729 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2730 | else { | |
2731 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6da3a13e WYG |
2732 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
2733 | return -ENODEV; | |
b481de9c | 2734 | } |
80fcc9e2 | 2735 | |
5d49f498 | 2736 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 2737 | |
bb8c093b | 2738 | rc = iwl3945_hw_nic_init(priv); |
b481de9c | 2739 | if (rc) { |
15b1687c | 2740 | IWL_ERR(priv, "Unable to int nic\n"); |
b481de9c ZY |
2741 | return rc; |
2742 | } | |
2743 | ||
2744 | /* make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
2745 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2746 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
2747 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2748 | ||
2749 | /* clear (again), then enable host interrupts */ | |
5d49f498 | 2750 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
ed3b932e | 2751 | iwl_enable_interrupts(priv); |
b481de9c ZY |
2752 | |
2753 | /* really make sure rfkill handshake bits are cleared */ | |
5d49f498 AK |
2754 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2755 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
2756 | |
2757 | /* Copy original ucode data image from disk into backup cache. | |
2758 | * This will be used to initialize the on-board processor's | |
2759 | * data SRAM for a clean start when the runtime program first loads. */ | |
2760 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 2761 | priv->ucode_data.len); |
b481de9c | 2762 | |
e655b9f0 ZY |
2763 | /* We return success when we resume from suspend and rf_kill is on. */ |
2764 | if (test_bit(STATUS_RF_KILL_HW, &priv->status)) | |
2765 | return 0; | |
2766 | ||
b481de9c ZY |
2767 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2768 | ||
b481de9c ZY |
2769 | /* load bootstrap state machine, |
2770 | * load bootstrap program into processor's memory, | |
2771 | * prepare to load the "initialize" uCode */ | |
75a9a926 | 2772 | rc = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c ZY |
2773 | |
2774 | if (rc) { | |
15b1687c WT |
2775 | IWL_ERR(priv, |
2776 | "Unable to set up bootstrap uCode: %d\n", rc); | |
b481de9c ZY |
2777 | continue; |
2778 | } | |
2779 | ||
2780 | /* start card; "initialize" will load runtime ucode */ | |
bb8c093b | 2781 | iwl3945_nic_start(priv); |
b481de9c | 2782 | |
e1623446 | 2783 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
2784 | |
2785 | return 0; | |
2786 | } | |
2787 | ||
2788 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
bb8c093b | 2789 | __iwl3945_down(priv); |
ebef2008 | 2790 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
2791 | |
2792 | /* tried to restart and config the device for as long as our | |
2793 | * patience could withstand */ | |
15b1687c | 2794 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
2795 | return -EIO; |
2796 | } | |
2797 | ||
2798 | ||
2799 | /***************************************************************************** | |
2800 | * | |
2801 | * Workqueue callbacks | |
2802 | * | |
2803 | *****************************************************************************/ | |
2804 | ||
bb8c093b | 2805 | static void iwl3945_bg_init_alive_start(struct work_struct *data) |
b481de9c | 2806 | { |
4a8a4322 AK |
2807 | struct iwl_priv *priv = |
2808 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
2809 | |
2810 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2811 | return; | |
2812 | ||
2813 | mutex_lock(&priv->mutex); | |
bb8c093b | 2814 | iwl3945_init_alive_start(priv); |
b481de9c ZY |
2815 | mutex_unlock(&priv->mutex); |
2816 | } | |
2817 | ||
bb8c093b | 2818 | static void iwl3945_bg_alive_start(struct work_struct *data) |
b481de9c | 2819 | { |
4a8a4322 AK |
2820 | struct iwl_priv *priv = |
2821 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
2822 | |
2823 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2824 | return; | |
2825 | ||
2826 | mutex_lock(&priv->mutex); | |
bb8c093b | 2827 | iwl3945_alive_start(priv); |
b481de9c ZY |
2828 | mutex_unlock(&priv->mutex); |
2829 | } | |
2830 | ||
743cdf1b BC |
2831 | /* |
2832 | * 3945 cannot interrupt driver when hardware rf kill switch toggles; | |
2833 | * driver must poll CSR_GP_CNTRL_REG register for change. This register | |
2834 | * *is* readable even when device has been SW_RESET into low power mode | |
2835 | * (e.g. during RF KILL). | |
2836 | */ | |
2663516d HS |
2837 | static void iwl3945_rfkill_poll(struct work_struct *data) |
2838 | { | |
2839 | struct iwl_priv *priv = | |
ee525d13 | 2840 | container_of(data, struct iwl_priv, _3945.rfkill_poll.work); |
743cdf1b BC |
2841 | bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &priv->status); |
2842 | bool new_rfkill = !(iwl_read32(priv, CSR_GP_CNTRL) | |
2843 | & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); | |
2663516d | 2844 | |
743cdf1b BC |
2845 | if (new_rfkill != old_rfkill) { |
2846 | if (new_rfkill) | |
2847 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
2848 | else | |
2849 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
2663516d | 2850 | |
743cdf1b BC |
2851 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, new_rfkill); |
2852 | ||
2853 | IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n", | |
2854 | new_rfkill ? "disable radio" : "enable radio"); | |
2855 | } | |
2663516d | 2856 | |
743cdf1b BC |
2857 | /* Keep this running, even if radio now enabled. This will be |
2858 | * cancelled in mac_start() if system decides to start again */ | |
ee525d13 | 2859 | queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll, |
2663516d HS |
2860 | round_jiffies_relative(2 * HZ)); |
2861 | ||
2862 | } | |
2863 | ||
1dda6d28 | 2864 | void iwl3945_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif) |
b481de9c | 2865 | { |
c2d79b48 | 2866 | struct iwl_host_cmd cmd = { |
b481de9c | 2867 | .id = REPLY_SCAN_CMD, |
bb8c093b | 2868 | .len = sizeof(struct iwl3945_scan_cmd), |
c2acea8e | 2869 | .flags = CMD_SIZE_HUGE, |
b481de9c | 2870 | }; |
bb8c093b | 2871 | struct iwl3945_scan_cmd *scan; |
b481de9c | 2872 | struct ieee80211_conf *conf = NULL; |
1ecf9fc1 | 2873 | u8 n_probes = 0; |
8318d78a | 2874 | enum ieee80211_band band; |
1ecf9fc1 | 2875 | bool is_active = false; |
b481de9c ZY |
2876 | |
2877 | conf = ieee80211_get_hw_conf(priv->hw); | |
2878 | ||
fbc9f97b RC |
2879 | cancel_delayed_work(&priv->scan_check); |
2880 | ||
775a6e27 | 2881 | if (!iwl_is_ready(priv)) { |
39aadf8c | 2882 | IWL_WARN(priv, "request scan called when driver not ready.\n"); |
b481de9c ZY |
2883 | goto done; |
2884 | } | |
2885 | ||
a96a27f9 | 2886 | /* Make sure the scan wasn't canceled before this queued work |
b481de9c ZY |
2887 | * was given the chance to run... */ |
2888 | if (!test_bit(STATUS_SCANNING, &priv->status)) | |
2889 | goto done; | |
2890 | ||
2891 | /* This should never be called or scheduled if there is currently | |
2892 | * a scan active in the hardware. */ | |
2893 | if (test_bit(STATUS_SCAN_HW, &priv->status)) { | |
e1623446 TW |
2894 | IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests " |
2895 | "Ignoring second request.\n"); | |
b481de9c ZY |
2896 | goto done; |
2897 | } | |
2898 | ||
2899 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
e1623446 | 2900 | IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n"); |
b481de9c ZY |
2901 | goto done; |
2902 | } | |
2903 | ||
2904 | if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { | |
e1623446 TW |
2905 | IWL_DEBUG_HC(priv, |
2906 | "Scan request while abort pending. Queuing.\n"); | |
b481de9c ZY |
2907 | goto done; |
2908 | } | |
2909 | ||
775a6e27 | 2910 | if (iwl_is_rfkill(priv)) { |
e1623446 | 2911 | IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n"); |
b481de9c ZY |
2912 | goto done; |
2913 | } | |
2914 | ||
2915 | if (!test_bit(STATUS_READY, &priv->status)) { | |
e1623446 TW |
2916 | IWL_DEBUG_HC(priv, |
2917 | "Scan request while uninitialized. Queuing.\n"); | |
b481de9c ZY |
2918 | goto done; |
2919 | } | |
2920 | ||
811ecc99 JB |
2921 | if (!priv->scan_cmd) { |
2922 | priv->scan_cmd = kmalloc(sizeof(struct iwl3945_scan_cmd) + | |
2923 | IWL_MAX_SCAN_SIZE, GFP_KERNEL); | |
2924 | if (!priv->scan_cmd) { | |
4f4d4088 | 2925 | IWL_DEBUG_SCAN(priv, "Fail to allocate scan memory\n"); |
b481de9c ZY |
2926 | goto done; |
2927 | } | |
2928 | } | |
811ecc99 | 2929 | scan = priv->scan_cmd; |
bb8c093b | 2930 | memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE); |
b481de9c ZY |
2931 | |
2932 | scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; | |
2933 | scan->quiet_time = IWL_ACTIVE_QUIET_TIME; | |
2934 | ||
8ccde88a | 2935 | if (iwl_is_associated(priv)) { |
b481de9c ZY |
2936 | u16 interval = 0; |
2937 | u32 extra; | |
2938 | u32 suspend_time = 100; | |
2939 | u32 scan_suspend_time = 100; | |
2940 | unsigned long flags; | |
2941 | ||
e1623446 | 2942 | IWL_DEBUG_INFO(priv, "Scanning while associated...\n"); |
b481de9c ZY |
2943 | |
2944 | spin_lock_irqsave(&priv->lock, flags); | |
1dda6d28 | 2945 | interval = vif ? vif->bss_conf.beacon_int : 0; |
b481de9c ZY |
2946 | spin_unlock_irqrestore(&priv->lock, flags); |
2947 | ||
2948 | scan->suspend_time = 0; | |
15e869d8 | 2949 | scan->max_out_time = cpu_to_le32(200 * 1024); |
b481de9c ZY |
2950 | if (!interval) |
2951 | interval = suspend_time; | |
2952 | /* | |
2953 | * suspend time format: | |
2954 | * 0-19: beacon interval in usec (time before exec.) | |
2955 | * 20-23: 0 | |
2956 | * 24-31: number of beacons (suspend between channels) | |
2957 | */ | |
2958 | ||
2959 | extra = (suspend_time / interval) << 24; | |
2960 | scan_suspend_time = 0xFF0FFFFF & | |
2961 | (extra | ((suspend_time % interval) * 1024)); | |
2962 | ||
2963 | scan->suspend_time = cpu_to_le32(scan_suspend_time); | |
e1623446 | 2964 | IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n", |
b481de9c ZY |
2965 | scan_suspend_time, interval); |
2966 | } | |
2967 | ||
4f4d4088 WYG |
2968 | if (priv->is_internal_short_scan) { |
2969 | IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n"); | |
2970 | } else if (priv->scan_request->n_ssids) { | |
1ecf9fc1 JB |
2971 | int i, p = 0; |
2972 | IWL_DEBUG_SCAN(priv, "Kicking off active scan\n"); | |
2973 | for (i = 0; i < priv->scan_request->n_ssids; i++) { | |
2974 | /* always does wildcard anyway */ | |
2975 | if (!priv->scan_request->ssids[i].ssid_len) | |
2976 | continue; | |
2977 | scan->direct_scan[p].id = WLAN_EID_SSID; | |
2978 | scan->direct_scan[p].len = | |
2979 | priv->scan_request->ssids[i].ssid_len; | |
2980 | memcpy(scan->direct_scan[p].ssid, | |
2981 | priv->scan_request->ssids[i].ssid, | |
2982 | priv->scan_request->ssids[i].ssid_len); | |
2983 | n_probes++; | |
2984 | p++; | |
2985 | } | |
2986 | is_active = true; | |
f9340520 | 2987 | } else |
1ecf9fc1 | 2988 | IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n"); |
b481de9c ZY |
2989 | |
2990 | /* We don't build a direct scan probe request; the uCode will do | |
2991 | * that based on the direct_mask added to each channel entry */ | |
b481de9c | 2992 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; |
3832ec9d | 2993 | scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id; |
b481de9c ZY |
2994 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
2995 | ||
2996 | /* flags + rate selection */ | |
2997 | ||
00700ee0 JB |
2998 | switch (priv->scan_band) { |
2999 | case IEEE80211_BAND_2GHZ: | |
b481de9c ZY |
3000 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; |
3001 | scan->tx_cmd.rate = IWL_RATE_1M_PLCP; | |
3002 | scan->good_CRC_th = 0; | |
8318d78a | 3003 | band = IEEE80211_BAND_2GHZ; |
00700ee0 JB |
3004 | break; |
3005 | case IEEE80211_BAND_5GHZ: | |
b481de9c | 3006 | scan->tx_cmd.rate = IWL_RATE_6M_PLCP; |
b097ad29 JB |
3007 | /* |
3008 | * If active scaning is requested but a certain channel | |
3009 | * is marked passive, we can do active scanning if we | |
3010 | * detect transmissions. | |
3011 | */ | |
96ff5641 JB |
3012 | scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT : |
3013 | IWL_GOOD_CRC_TH_DISABLED; | |
8318d78a | 3014 | band = IEEE80211_BAND_5GHZ; |
00700ee0 JB |
3015 | break; |
3016 | default: | |
3017 | IWL_WARN(priv, "Invalid scan band\n"); | |
b481de9c ZY |
3018 | goto done; |
3019 | } | |
3020 | ||
4f4d4088 WYG |
3021 | if (!priv->is_internal_short_scan) { |
3022 | scan->tx_cmd.len = cpu_to_le16( | |
1ecf9fc1 JB |
3023 | iwl_fill_probe_req(priv, |
3024 | (struct ieee80211_mgmt *)scan->data, | |
3025 | priv->scan_request->ie, | |
3026 | priv->scan_request->ie_len, | |
3027 | IWL_MAX_SCAN_SIZE - sizeof(*scan))); | |
4f4d4088 WYG |
3028 | } else { |
3029 | scan->tx_cmd.len = cpu_to_le16( | |
3030 | iwl_fill_probe_req(priv, | |
3031 | (struct ieee80211_mgmt *)scan->data, | |
3032 | NULL, 0, | |
3033 | IWL_MAX_SCAN_SIZE - sizeof(*scan))); | |
3034 | } | |
b481de9c ZY |
3035 | /* select Rx antennas */ |
3036 | scan->flags |= iwl3945_get_antenna_flags(priv); | |
3037 | ||
14023641 AK |
3038 | if (priv->is_internal_short_scan) { |
3039 | scan->channel_count = | |
3040 | iwl3945_get_single_channel_for_scan(priv, vif, band, | |
3041 | (void *)&scan->data[le16_to_cpu( | |
3042 | scan->tx_cmd.len)]); | |
3043 | } else { | |
3044 | scan->channel_count = | |
3045 | iwl3945_get_channels_for_scan(priv, band, is_active, n_probes, | |
3046 | (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)], vif); | |
3047 | } | |
b481de9c | 3048 | |
14b54336 | 3049 | if (scan->channel_count == 0) { |
e1623446 | 3050 | IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count); |
14b54336 RC |
3051 | goto done; |
3052 | } | |
3053 | ||
b481de9c | 3054 | cmd.len += le16_to_cpu(scan->tx_cmd.len) + |
bb8c093b | 3055 | scan->channel_count * sizeof(struct iwl3945_scan_channel); |
b481de9c ZY |
3056 | cmd.data = scan; |
3057 | scan->len = cpu_to_le16(cmd.len); | |
3058 | ||
3059 | set_bit(STATUS_SCAN_HW, &priv->status); | |
4f4d4088 | 3060 | if (iwl_send_cmd_sync(priv, &cmd)) |
b481de9c ZY |
3061 | goto done; |
3062 | ||
3063 | queue_delayed_work(priv->workqueue, &priv->scan_check, | |
3064 | IWL_SCAN_CHECK_WATCHDOG); | |
3065 | ||
b481de9c ZY |
3066 | return; |
3067 | ||
3068 | done: | |
2420ebc1 MA |
3069 | /* can not perform scan make sure we clear scanning |
3070 | * bits from status so next scan request can be performed. | |
3071 | * if we dont clear scanning status bit here all next scan | |
3072 | * will fail | |
3073 | */ | |
3074 | clear_bit(STATUS_SCAN_HW, &priv->status); | |
3075 | clear_bit(STATUS_SCANNING, &priv->status); | |
3076 | ||
01ebd063 | 3077 | /* inform mac80211 scan aborted */ |
b481de9c | 3078 | queue_work(priv->workqueue, &priv->scan_completed); |
b481de9c ZY |
3079 | } |
3080 | ||
bb8c093b | 3081 | static void iwl3945_bg_restart(struct work_struct *data) |
b481de9c | 3082 | { |
4a8a4322 | 3083 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
3084 | |
3085 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3086 | return; | |
3087 | ||
19cc1087 JB |
3088 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
3089 | mutex_lock(&priv->mutex); | |
3090 | priv->vif = NULL; | |
3091 | priv->is_open = 0; | |
3092 | mutex_unlock(&priv->mutex); | |
3093 | iwl3945_down(priv); | |
3094 | ieee80211_restart_hw(priv->hw); | |
3095 | } else { | |
3096 | iwl3945_down(priv); | |
80676518 JB |
3097 | |
3098 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3099 | return; | |
3100 | ||
3101 | mutex_lock(&priv->mutex); | |
3102 | __iwl3945_up(priv); | |
3103 | mutex_unlock(&priv->mutex); | |
19cc1087 | 3104 | } |
b481de9c ZY |
3105 | } |
3106 | ||
bb8c093b | 3107 | static void iwl3945_bg_rx_replenish(struct work_struct *data) |
b481de9c | 3108 | { |
4a8a4322 AK |
3109 | struct iwl_priv *priv = |
3110 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
3111 | |
3112 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3113 | return; | |
3114 | ||
3115 | mutex_lock(&priv->mutex); | |
bb8c093b | 3116 | iwl3945_rx_replenish(priv); |
b481de9c ZY |
3117 | mutex_unlock(&priv->mutex); |
3118 | } | |
3119 | ||
1dda6d28 | 3120 | void iwl3945_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif) |
b481de9c | 3121 | { |
b481de9c ZY |
3122 | int rc = 0; |
3123 | struct ieee80211_conf *conf = NULL; | |
3124 | ||
1dda6d28 JB |
3125 | if (!vif || !priv->is_open) |
3126 | return; | |
3127 | ||
3128 | if (vif->type == NL80211_IFTYPE_AP) { | |
15b1687c | 3129 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
3130 | return; |
3131 | } | |
3132 | ||
e1623446 | 3133 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
1dda6d28 | 3134 | vif->bss_conf.aid, priv->active_rxon.bssid_addr); |
b481de9c ZY |
3135 | |
3136 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3137 | return; | |
3138 | ||
af0053d6 | 3139 | iwl_scan_cancel_timeout(priv, 200); |
15e869d8 | 3140 | |
b481de9c ZY |
3141 | conf = ieee80211_get_hw_conf(priv->hw); |
3142 | ||
8ccde88a | 3143 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3144 | iwlcore_commit_rxon(priv); |
b481de9c | 3145 | |
28afaf91 | 3146 | memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
1dda6d28 | 3147 | iwl_setup_rxon_timing(priv, vif); |
518099a8 | 3148 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c ZY |
3149 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
3150 | if (rc) | |
39aadf8c | 3151 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3152 | "Attempting to continue.\n"); |
3153 | ||
8ccde88a | 3154 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c | 3155 | |
1dda6d28 | 3156 | priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid); |
b481de9c | 3157 | |
e1623446 | 3158 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
1dda6d28 | 3159 | vif->bss_conf.aid, vif->bss_conf.beacon_int); |
b481de9c | 3160 | |
1dda6d28 | 3161 | if (vif->bss_conf.assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) |
8ccde88a | 3162 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 3163 | else |
8ccde88a | 3164 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
b481de9c | 3165 | |
8ccde88a | 3166 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { |
1dda6d28 | 3167 | if (vif->bss_conf.assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) |
8ccde88a | 3168 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 3169 | else |
8ccde88a | 3170 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c | 3171 | |
1dda6d28 | 3172 | if (vif->type == NL80211_IFTYPE_ADHOC) |
8ccde88a | 3173 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c ZY |
3174 | } |
3175 | ||
e0158e61 | 3176 | iwlcore_commit_rxon(priv); |
b481de9c | 3177 | |
1dda6d28 | 3178 | switch (vif->type) { |
05c914fe | 3179 | case NL80211_IFTYPE_STATION: |
bb8c093b | 3180 | iwl3945_rate_scale_init(priv->hw, IWL_AP_ID); |
b481de9c | 3181 | break; |
05c914fe | 3182 | case NL80211_IFTYPE_ADHOC: |
bb8c093b | 3183 | iwl3945_send_beacon_cmd(priv); |
b481de9c | 3184 | break; |
b481de9c | 3185 | default: |
1dda6d28 JB |
3186 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3187 | __func__, vif->type); | |
b481de9c ZY |
3188 | break; |
3189 | } | |
cd56d331 AK |
3190 | } |
3191 | ||
b481de9c ZY |
3192 | /***************************************************************************** |
3193 | * | |
3194 | * mac80211 entry point functions | |
3195 | * | |
3196 | *****************************************************************************/ | |
3197 | ||
5a66926a ZY |
3198 | #define UCODE_READY_TIMEOUT (2 * HZ) |
3199 | ||
bb8c093b | 3200 | static int iwl3945_mac_start(struct ieee80211_hw *hw) |
b481de9c | 3201 | { |
4a8a4322 | 3202 | struct iwl_priv *priv = hw->priv; |
5a66926a | 3203 | int ret; |
b481de9c | 3204 | |
e1623446 | 3205 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
3206 | |
3207 | /* we should be verifying the device is ready to be opened */ | |
3208 | mutex_lock(&priv->mutex); | |
3209 | ||
5a66926a ZY |
3210 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... |
3211 | * ucode filename and max sizes are card-specific. */ | |
3212 | ||
3213 | if (!priv->ucode_code.len) { | |
3214 | ret = iwl3945_read_ucode(priv); | |
3215 | if (ret) { | |
15b1687c | 3216 | IWL_ERR(priv, "Could not read microcode: %d\n", ret); |
5a66926a ZY |
3217 | mutex_unlock(&priv->mutex); |
3218 | goto out_release_irq; | |
3219 | } | |
3220 | } | |
b481de9c | 3221 | |
e655b9f0 | 3222 | ret = __iwl3945_up(priv); |
b481de9c ZY |
3223 | |
3224 | mutex_unlock(&priv->mutex); | |
5a66926a | 3225 | |
e655b9f0 ZY |
3226 | if (ret) |
3227 | goto out_release_irq; | |
3228 | ||
e1623446 | 3229 | IWL_DEBUG_INFO(priv, "Start UP work.\n"); |
e655b9f0 | 3230 | |
5a66926a ZY |
3231 | /* Wait for START_ALIVE from ucode. Otherwise callbacks from |
3232 | * mac80211 will not be run successfully. */ | |
3233 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
3234 | test_bit(STATUS_READY, &priv->status), | |
3235 | UCODE_READY_TIMEOUT); | |
3236 | if (!ret) { | |
3237 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c WT |
3238 | IWL_ERR(priv, |
3239 | "Wait for START_ALIVE timeout after %dms.\n", | |
3240 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); | |
5a66926a ZY |
3241 | ret = -ETIMEDOUT; |
3242 | goto out_release_irq; | |
3243 | } | |
3244 | } | |
3245 | ||
2663516d HS |
3246 | /* ucode is running and will send rfkill notifications, |
3247 | * no need to poll the killswitch state anymore */ | |
ee525d13 | 3248 | cancel_delayed_work(&priv->_3945.rfkill_poll); |
2663516d | 3249 | |
e932a609 JB |
3250 | iwl_led_start(priv); |
3251 | ||
e655b9f0 | 3252 | priv->is_open = 1; |
e1623446 | 3253 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3254 | return 0; |
5a66926a ZY |
3255 | |
3256 | out_release_irq: | |
e655b9f0 | 3257 | priv->is_open = 0; |
e1623446 | 3258 | IWL_DEBUG_MAC80211(priv, "leave - failed\n"); |
5a66926a | 3259 | return ret; |
b481de9c ZY |
3260 | } |
3261 | ||
bb8c093b | 3262 | static void iwl3945_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 3263 | { |
4a8a4322 | 3264 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3265 | |
e1623446 | 3266 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
6ef89d0a | 3267 | |
e655b9f0 | 3268 | if (!priv->is_open) { |
e1623446 | 3269 | IWL_DEBUG_MAC80211(priv, "leave - skip\n"); |
e655b9f0 ZY |
3270 | return; |
3271 | } | |
3272 | ||
b481de9c | 3273 | priv->is_open = 0; |
5a66926a | 3274 | |
775a6e27 | 3275 | if (iwl_is_ready_rf(priv)) { |
e655b9f0 ZY |
3276 | /* stop mac, cancel any scan request and clear |
3277 | * RXON_FILTER_ASSOC_MSK BIT | |
3278 | */ | |
5a66926a | 3279 | mutex_lock(&priv->mutex); |
af0053d6 | 3280 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 3281 | mutex_unlock(&priv->mutex); |
fde3571f MA |
3282 | } |
3283 | ||
5a66926a ZY |
3284 | iwl3945_down(priv); |
3285 | ||
3286 | flush_workqueue(priv->workqueue); | |
2663516d HS |
3287 | |
3288 | /* start polling the killswitch state again */ | |
ee525d13 | 3289 | queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll, |
2663516d | 3290 | round_jiffies_relative(2 * HZ)); |
6ef89d0a | 3291 | |
e1623446 | 3292 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
3293 | } |
3294 | ||
e039fa4a | 3295 | static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 3296 | { |
4a8a4322 | 3297 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3298 | |
e1623446 | 3299 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3300 | |
e1623446 | 3301 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 3302 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 3303 | |
e039fa4a | 3304 | if (iwl3945_tx_skb(priv, skb)) |
b481de9c ZY |
3305 | dev_kfree_skb_any(skb); |
3306 | ||
e1623446 | 3307 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
637f8837 | 3308 | return NETDEV_TX_OK; |
b481de9c ZY |
3309 | } |
3310 | ||
1dda6d28 | 3311 | void iwl3945_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif) |
b481de9c ZY |
3312 | { |
3313 | int rc = 0; | |
3314 | ||
d986bcd1 | 3315 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
3316 | return; |
3317 | ||
3318 | /* The following should be done only at AP bring up */ | |
8ccde88a | 3319 | if (!(iwl_is_associated(priv))) { |
b481de9c ZY |
3320 | |
3321 | /* RXON - unassoc (to set timing command) */ | |
8ccde88a | 3322 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3323 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3324 | |
3325 | /* RXON Timing */ | |
28afaf91 | 3326 | memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd)); |
1dda6d28 | 3327 | iwl_setup_rxon_timing(priv, vif); |
518099a8 SO |
3328 | rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
3329 | sizeof(priv->rxon_timing), | |
3330 | &priv->rxon_timing); | |
b481de9c | 3331 | if (rc) |
39aadf8c | 3332 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3333 | "Attempting to continue.\n"); |
3334 | ||
1dda6d28 JB |
3335 | priv->staging_rxon.assoc_id = 0; |
3336 | ||
3337 | if (vif->bss_conf.assoc_capability & | |
3338 | WLAN_CAPABILITY_SHORT_PREAMBLE) | |
8ccde88a | 3339 | priv->staging_rxon.flags |= |
b481de9c ZY |
3340 | RXON_FLG_SHORT_PREAMBLE_MSK; |
3341 | else | |
8ccde88a | 3342 | priv->staging_rxon.flags &= |
b481de9c ZY |
3343 | ~RXON_FLG_SHORT_PREAMBLE_MSK; |
3344 | ||
8ccde88a | 3345 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { |
1dda6d28 JB |
3346 | if (vif->bss_conf.assoc_capability & |
3347 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
8ccde88a | 3348 | priv->staging_rxon.flags |= |
b481de9c ZY |
3349 | RXON_FLG_SHORT_SLOT_MSK; |
3350 | else | |
8ccde88a | 3351 | priv->staging_rxon.flags &= |
b481de9c ZY |
3352 | ~RXON_FLG_SHORT_SLOT_MSK; |
3353 | ||
1dda6d28 | 3354 | if (vif->type == NL80211_IFTYPE_ADHOC) |
8ccde88a | 3355 | priv->staging_rxon.flags &= |
b481de9c ZY |
3356 | ~RXON_FLG_SHORT_SLOT_MSK; |
3357 | } | |
3358 | /* restore RXON assoc */ | |
8ccde88a | 3359 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; |
e0158e61 | 3360 | iwlcore_commit_rxon(priv); |
556f8db7 | 3361 | } |
bb8c093b | 3362 | iwl3945_send_beacon_cmd(priv); |
b481de9c ZY |
3363 | |
3364 | /* FIXME - we need to add code here to detect a totally new | |
3365 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
3366 | * clear sta table, add BCAST sta... */ | |
3367 | } | |
3368 | ||
bb8c093b | 3369 | static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
3370 | struct ieee80211_vif *vif, |
3371 | struct ieee80211_sta *sta, | |
3372 | struct ieee80211_key_conf *key) | |
b481de9c | 3373 | { |
4a8a4322 | 3374 | struct iwl_priv *priv = hw->priv; |
6e21f15c AK |
3375 | int ret = 0; |
3376 | u8 sta_id = IWL_INVALID_STATION; | |
3377 | u8 static_key; | |
b481de9c | 3378 | |
e1623446 | 3379 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3380 | |
df878d8f | 3381 | if (iwl3945_mod_params.sw_crypto) { |
e1623446 | 3382 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
3383 | return -EOPNOTSUPP; |
3384 | } | |
3385 | ||
6e21f15c AK |
3386 | static_key = !iwl_is_associated(priv); |
3387 | ||
3388 | if (!static_key) { | |
2a87c26b JB |
3389 | if (!sta) { |
3390 | sta_id = priv->hw_params.bcast_sta_id; | |
3391 | } else { | |
3392 | sta_id = iwl_sta_id(sta); | |
3393 | if (sta_id == IWL_INVALID_STATION) { | |
3394 | IWL_DEBUG_MAC80211(priv, | |
3395 | "leave - %pM not in station map.\n", | |
3396 | sta->addr); | |
3397 | return -EINVAL; | |
3398 | } | |
6e21f15c | 3399 | } |
b481de9c ZY |
3400 | } |
3401 | ||
3402 | mutex_lock(&priv->mutex); | |
af0053d6 | 3403 | iwl_scan_cancel_timeout(priv, 100); |
15e869d8 | 3404 | |
b481de9c | 3405 | switch (cmd) { |
6e21f15c AK |
3406 | case SET_KEY: |
3407 | if (static_key) | |
3408 | ret = iwl3945_set_static_key(priv, key); | |
3409 | else | |
3410 | ret = iwl3945_set_dynamic_key(priv, key, sta_id); | |
3411 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); | |
b481de9c ZY |
3412 | break; |
3413 | case DISABLE_KEY: | |
6e21f15c AK |
3414 | if (static_key) |
3415 | ret = iwl3945_remove_static_key(priv); | |
3416 | else | |
3417 | ret = iwl3945_clear_sta_key_info(priv, sta_id); | |
3418 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); | |
b481de9c ZY |
3419 | break; |
3420 | default: | |
42986796 | 3421 | ret = -EINVAL; |
b481de9c ZY |
3422 | } |
3423 | ||
72e15d71 | 3424 | mutex_unlock(&priv->mutex); |
e1623446 | 3425 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3426 | |
42986796 | 3427 | return ret; |
b481de9c ZY |
3428 | } |
3429 | ||
fe6b23dd RC |
3430 | static int iwl3945_mac_sta_add(struct ieee80211_hw *hw, |
3431 | struct ieee80211_vif *vif, | |
3432 | struct ieee80211_sta *sta) | |
3433 | { | |
3434 | struct iwl_priv *priv = hw->priv; | |
fd1af15d | 3435 | struct iwl3945_sta_priv *sta_priv = (void *)sta->drv_priv; |
fe6b23dd | 3436 | int ret; |
fd1af15d | 3437 | bool is_ap = vif->type == NL80211_IFTYPE_STATION; |
fe6b23dd RC |
3438 | u8 sta_id; |
3439 | ||
3440 | IWL_DEBUG_INFO(priv, "received request to add station %pM\n", | |
3441 | sta->addr); | |
da5ae1cf RC |
3442 | mutex_lock(&priv->mutex); |
3443 | IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n", | |
3444 | sta->addr); | |
3445 | sta_priv->common.sta_id = IWL_INVALID_STATION; | |
3446 | ||
fe6b23dd RC |
3447 | |
3448 | ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap, | |
3449 | &sta_id); | |
3450 | if (ret) { | |
3451 | IWL_ERR(priv, "Unable to add station %pM (%d)\n", | |
3452 | sta->addr, ret); | |
3453 | /* Should we return success if return code is EEXIST ? */ | |
da5ae1cf | 3454 | mutex_unlock(&priv->mutex); |
fe6b23dd RC |
3455 | return ret; |
3456 | } | |
3457 | ||
fd1af15d JB |
3458 | sta_priv->common.sta_id = sta_id; |
3459 | ||
fe6b23dd | 3460 | /* Initialize rate scaling */ |
91dd6c27 | 3461 | IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n", |
fe6b23dd RC |
3462 | sta->addr); |
3463 | iwl3945_rs_rate_init(priv, sta, sta_id); | |
da5ae1cf | 3464 | mutex_unlock(&priv->mutex); |
fe6b23dd RC |
3465 | |
3466 | return 0; | |
fe6b23dd | 3467 | } |
b481de9c ZY |
3468 | /***************************************************************************** |
3469 | * | |
3470 | * sysfs attributes | |
3471 | * | |
3472 | *****************************************************************************/ | |
3473 | ||
d08853a3 | 3474 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
3475 | |
3476 | /* | |
3477 | * The following adds a new attribute to the sysfs representation | |
3478 | * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/) | |
3479 | * used for controlling the debug level. | |
3480 | * | |
3481 | * See the level definitions in iwl for details. | |
a562a9dd | 3482 | * |
3d816c77 RC |
3483 | * The debug_level being managed using sysfs below is a per device debug |
3484 | * level that is used instead of the global debug level if it (the per | |
3485 | * device debug level) is set. | |
b481de9c | 3486 | */ |
40b8ec0b SO |
3487 | static ssize_t show_debug_level(struct device *d, |
3488 | struct device_attribute *attr, char *buf) | |
b481de9c | 3489 | { |
3d816c77 RC |
3490 | struct iwl_priv *priv = dev_get_drvdata(d); |
3491 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
b481de9c | 3492 | } |
40b8ec0b SO |
3493 | static ssize_t store_debug_level(struct device *d, |
3494 | struct device_attribute *attr, | |
b481de9c ZY |
3495 | const char *buf, size_t count) |
3496 | { | |
928841b1 | 3497 | struct iwl_priv *priv = dev_get_drvdata(d); |
40b8ec0b SO |
3498 | unsigned long val; |
3499 | int ret; | |
b481de9c | 3500 | |
40b8ec0b SO |
3501 | ret = strict_strtoul(buf, 0, &val); |
3502 | if (ret) | |
978785a3 | 3503 | IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf); |
20594eb0 | 3504 | else { |
3d816c77 | 3505 | priv->debug_level = val; |
20594eb0 WYG |
3506 | if (iwl_alloc_traffic_mem(priv)) |
3507 | IWL_ERR(priv, | |
3508 | "Not enough memory to generate traffic log\n"); | |
3509 | } | |
b481de9c ZY |
3510 | return strnlen(buf, count); |
3511 | } | |
3512 | ||
40b8ec0b SO |
3513 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
3514 | show_debug_level, store_debug_level); | |
b481de9c | 3515 | |
d08853a3 | 3516 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 3517 | |
b481de9c ZY |
3518 | static ssize_t show_temperature(struct device *d, |
3519 | struct device_attribute *attr, char *buf) | |
3520 | { | |
928841b1 | 3521 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3522 | |
775a6e27 | 3523 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3524 | return -EAGAIN; |
3525 | ||
bb8c093b | 3526 | return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv)); |
b481de9c ZY |
3527 | } |
3528 | ||
3529 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
3530 | ||
b481de9c ZY |
3531 | static ssize_t show_tx_power(struct device *d, |
3532 | struct device_attribute *attr, char *buf) | |
3533 | { | |
928841b1 | 3534 | struct iwl_priv *priv = dev_get_drvdata(d); |
62ea9c5b | 3535 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); |
b481de9c ZY |
3536 | } |
3537 | ||
3538 | static ssize_t store_tx_power(struct device *d, | |
3539 | struct device_attribute *attr, | |
3540 | const char *buf, size_t count) | |
3541 | { | |
928841b1 | 3542 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3543 | char *p = (char *)buf; |
3544 | u32 val; | |
3545 | ||
3546 | val = simple_strtoul(p, &p, 10); | |
3547 | if (p == buf) | |
978785a3 | 3548 | IWL_INFO(priv, ": %s is not in decimal form.\n", buf); |
b481de9c | 3549 | else |
bb8c093b | 3550 | iwl3945_hw_reg_set_txpower(priv, val); |
b481de9c ZY |
3551 | |
3552 | return count; | |
3553 | } | |
3554 | ||
3555 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
3556 | ||
3557 | static ssize_t show_flags(struct device *d, | |
3558 | struct device_attribute *attr, char *buf) | |
3559 | { | |
928841b1 | 3560 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3561 | |
8ccde88a | 3562 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); |
b481de9c ZY |
3563 | } |
3564 | ||
3565 | static ssize_t store_flags(struct device *d, | |
3566 | struct device_attribute *attr, | |
3567 | const char *buf, size_t count) | |
3568 | { | |
928841b1 | 3569 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3570 | u32 flags = simple_strtoul(buf, NULL, 0); |
3571 | ||
3572 | mutex_lock(&priv->mutex); | |
8ccde88a | 3573 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { |
b481de9c | 3574 | /* Cancel any currently running scans... */ |
af0053d6 | 3575 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3576 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3577 | else { |
e1623446 | 3578 | IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n", |
b481de9c | 3579 | flags); |
8ccde88a | 3580 | priv->staging_rxon.flags = cpu_to_le32(flags); |
e0158e61 | 3581 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3582 | } |
3583 | } | |
3584 | mutex_unlock(&priv->mutex); | |
3585 | ||
3586 | return count; | |
3587 | } | |
3588 | ||
3589 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
3590 | ||
3591 | static ssize_t show_filter_flags(struct device *d, | |
3592 | struct device_attribute *attr, char *buf) | |
3593 | { | |
928841b1 | 3594 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3595 | |
3596 | return sprintf(buf, "0x%04X\n", | |
8ccde88a | 3597 | le32_to_cpu(priv->active_rxon.filter_flags)); |
b481de9c ZY |
3598 | } |
3599 | ||
3600 | static ssize_t store_filter_flags(struct device *d, | |
3601 | struct device_attribute *attr, | |
3602 | const char *buf, size_t count) | |
3603 | { | |
928841b1 | 3604 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3605 | u32 filter_flags = simple_strtoul(buf, NULL, 0); |
3606 | ||
3607 | mutex_lock(&priv->mutex); | |
8ccde88a | 3608 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { |
b481de9c | 3609 | /* Cancel any currently running scans... */ |
af0053d6 | 3610 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 3611 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 3612 | else { |
e1623446 | 3613 | IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = " |
b481de9c | 3614 | "0x%04X\n", filter_flags); |
8ccde88a | 3615 | priv->staging_rxon.filter_flags = |
b481de9c | 3616 | cpu_to_le32(filter_flags); |
e0158e61 | 3617 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3618 | } |
3619 | } | |
3620 | mutex_unlock(&priv->mutex); | |
3621 | ||
3622 | return count; | |
3623 | } | |
3624 | ||
3625 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
3626 | store_filter_flags); | |
3627 | ||
b481de9c ZY |
3628 | static ssize_t show_measurement(struct device *d, |
3629 | struct device_attribute *attr, char *buf) | |
3630 | { | |
4a8a4322 | 3631 | struct iwl_priv *priv = dev_get_drvdata(d); |
600c0e11 | 3632 | struct iwl_spectrum_notification measure_report; |
b481de9c | 3633 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
3ac7f146 | 3634 | u8 *data = (u8 *)&measure_report; |
b481de9c ZY |
3635 | unsigned long flags; |
3636 | ||
3637 | spin_lock_irqsave(&priv->lock, flags); | |
3638 | if (!(priv->measurement_status & MEASUREMENT_READY)) { | |
3639 | spin_unlock_irqrestore(&priv->lock, flags); | |
3640 | return 0; | |
3641 | } | |
3642 | memcpy(&measure_report, &priv->measure_report, size); | |
3643 | priv->measurement_status = 0; | |
3644 | spin_unlock_irqrestore(&priv->lock, flags); | |
3645 | ||
3646 | while (size && (PAGE_SIZE - len)) { | |
3647 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
3648 | PAGE_SIZE - len, 1); | |
3649 | len = strlen(buf); | |
3650 | if (PAGE_SIZE - len) | |
3651 | buf[len++] = '\n'; | |
3652 | ||
3653 | ofs += 16; | |
3654 | size -= min(size, 16U); | |
3655 | } | |
3656 | ||
3657 | return len; | |
3658 | } | |
3659 | ||
3660 | static ssize_t store_measurement(struct device *d, | |
3661 | struct device_attribute *attr, | |
3662 | const char *buf, size_t count) | |
3663 | { | |
4a8a4322 | 3664 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3665 | struct ieee80211_measurement_params params = { |
8ccde88a | 3666 | .channel = le16_to_cpu(priv->active_rxon.channel), |
e99f168c | 3667 | .start_time = cpu_to_le64(priv->_3945.last_tsf), |
b481de9c ZY |
3668 | .duration = cpu_to_le16(1), |
3669 | }; | |
3670 | u8 type = IWL_MEASURE_BASIC; | |
3671 | u8 buffer[32]; | |
3672 | u8 channel; | |
3673 | ||
3674 | if (count) { | |
3675 | char *p = buffer; | |
3676 | strncpy(buffer, buf, min(sizeof(buffer), count)); | |
3677 | channel = simple_strtoul(p, NULL, 0); | |
3678 | if (channel) | |
3679 | params.channel = channel; | |
3680 | ||
3681 | p = buffer; | |
3682 | while (*p && *p != ' ') | |
3683 | p++; | |
3684 | if (*p) | |
3685 | type = simple_strtoul(p + 1, NULL, 0); | |
3686 | } | |
3687 | ||
e1623446 | 3688 | IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on " |
b481de9c | 3689 | "channel %d (for '%s')\n", type, params.channel, buf); |
bb8c093b | 3690 | iwl3945_get_measurement(priv, ¶ms, type); |
b481de9c ZY |
3691 | |
3692 | return count; | |
3693 | } | |
3694 | ||
3695 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | |
3696 | show_measurement, store_measurement); | |
b481de9c | 3697 | |
b481de9c ZY |
3698 | static ssize_t store_retry_rate(struct device *d, |
3699 | struct device_attribute *attr, | |
3700 | const char *buf, size_t count) | |
3701 | { | |
4a8a4322 | 3702 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3703 | |
3704 | priv->retry_rate = simple_strtoul(buf, NULL, 0); | |
3705 | if (priv->retry_rate <= 0) | |
3706 | priv->retry_rate = 1; | |
3707 | ||
3708 | return count; | |
3709 | } | |
3710 | ||
3711 | static ssize_t show_retry_rate(struct device *d, | |
3712 | struct device_attribute *attr, char *buf) | |
3713 | { | |
4a8a4322 | 3714 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3715 | return sprintf(buf, "%d", priv->retry_rate); |
3716 | } | |
3717 | ||
3718 | static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate, | |
3719 | store_retry_rate); | |
3720 | ||
d25aabb0 | 3721 | |
b481de9c ZY |
3722 | static ssize_t show_channels(struct device *d, |
3723 | struct device_attribute *attr, char *buf) | |
3724 | { | |
8318d78a JB |
3725 | /* all this shit doesn't belong into sysfs anyway */ |
3726 | return 0; | |
b481de9c ZY |
3727 | } |
3728 | ||
3729 | static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL); | |
3730 | ||
b481de9c ZY |
3731 | static ssize_t show_antenna(struct device *d, |
3732 | struct device_attribute *attr, char *buf) | |
3733 | { | |
4a8a4322 | 3734 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3735 | |
775a6e27 | 3736 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3737 | return -EAGAIN; |
3738 | ||
7e4bca5e | 3739 | return sprintf(buf, "%d\n", iwl3945_mod_params.antenna); |
b481de9c ZY |
3740 | } |
3741 | ||
3742 | static ssize_t store_antenna(struct device *d, | |
3743 | struct device_attribute *attr, | |
3744 | const char *buf, size_t count) | |
3745 | { | |
7530f85f | 3746 | struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d); |
b481de9c | 3747 | int ant; |
b481de9c ZY |
3748 | |
3749 | if (count == 0) | |
3750 | return 0; | |
3751 | ||
3752 | if (sscanf(buf, "%1i", &ant) != 1) { | |
e1623446 | 3753 | IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n"); |
b481de9c ZY |
3754 | return count; |
3755 | } | |
3756 | ||
3757 | if ((ant >= 0) && (ant <= 2)) { | |
e1623446 | 3758 | IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant); |
7e4bca5e | 3759 | iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant; |
b481de9c | 3760 | } else |
e1623446 | 3761 | IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant); |
b481de9c ZY |
3762 | |
3763 | ||
3764 | return count; | |
3765 | } | |
3766 | ||
3767 | static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna); | |
3768 | ||
3769 | static ssize_t show_status(struct device *d, | |
3770 | struct device_attribute *attr, char *buf) | |
3771 | { | |
928841b1 | 3772 | struct iwl_priv *priv = dev_get_drvdata(d); |
775a6e27 | 3773 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3774 | return -EAGAIN; |
3775 | return sprintf(buf, "0x%08x\n", (int)priv->status); | |
3776 | } | |
3777 | ||
3778 | static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); | |
3779 | ||
3780 | static ssize_t dump_error_log(struct device *d, | |
3781 | struct device_attribute *attr, | |
3782 | const char *buf, size_t count) | |
3783 | { | |
928841b1 | 3784 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
3785 | char *p = (char *)buf; |
3786 | ||
3787 | if (p[0] == '1') | |
928841b1 | 3788 | iwl3945_dump_nic_error_log(priv); |
b481de9c ZY |
3789 | |
3790 | return strnlen(buf, count); | |
3791 | } | |
3792 | ||
3793 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | |
3794 | ||
b481de9c ZY |
3795 | /***************************************************************************** |
3796 | * | |
a96a27f9 | 3797 | * driver setup and tear down |
b481de9c ZY |
3798 | * |
3799 | *****************************************************************************/ | |
3800 | ||
4a8a4322 | 3801 | static void iwl3945_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 3802 | { |
d21050c7 | 3803 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
3804 | |
3805 | init_waitqueue_head(&priv->wait_command_queue); | |
3806 | ||
bb8c093b CH |
3807 | INIT_WORK(&priv->restart, iwl3945_bg_restart); |
3808 | INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish); | |
bb8c093b | 3809 | INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update); |
bb8c093b CH |
3810 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start); |
3811 | INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start); | |
ee525d13 | 3812 | INIT_DELAYED_WORK(&priv->_3945.rfkill_poll, iwl3945_rfkill_poll); |
77fecfb8 | 3813 | INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed); |
77fecfb8 | 3814 | INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan); |
1e460535 | 3815 | INIT_WORK(&priv->start_internal_scan, iwl_bg_start_internal_scan); |
77fecfb8 | 3816 | INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check); |
bb8c093b CH |
3817 | |
3818 | iwl3945_hw_setup_deferred_work(priv); | |
b481de9c | 3819 | |
b74e31a9 WYG |
3820 | if (priv->cfg->ops->lib->recover_from_tx_stall) { |
3821 | init_timer(&priv->monitor_recover); | |
3822 | priv->monitor_recover.data = (unsigned long)priv; | |
3823 | priv->monitor_recover.function = | |
3824 | priv->cfg->ops->lib->recover_from_tx_stall; | |
3825 | } | |
3826 | ||
b481de9c | 3827 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) |
bb8c093b | 3828 | iwl3945_irq_tasklet, (unsigned long)priv); |
b481de9c ZY |
3829 | } |
3830 | ||
4a8a4322 | 3831 | static void iwl3945_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3832 | { |
bb8c093b | 3833 | iwl3945_hw_cancel_deferred_work(priv); |
b481de9c | 3834 | |
e47eb6ad | 3835 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
3836 | cancel_delayed_work(&priv->scan_check); |
3837 | cancel_delayed_work(&priv->alive_start); | |
1e460535 | 3838 | cancel_work_sync(&priv->start_internal_scan); |
b481de9c | 3839 | cancel_work_sync(&priv->beacon_update); |
b74e31a9 WYG |
3840 | if (priv->cfg->ops->lib->recover_from_tx_stall) |
3841 | del_timer_sync(&priv->monitor_recover); | |
b481de9c ZY |
3842 | } |
3843 | ||
bb8c093b | 3844 | static struct attribute *iwl3945_sysfs_entries[] = { |
b481de9c ZY |
3845 | &dev_attr_antenna.attr, |
3846 | &dev_attr_channels.attr, | |
3847 | &dev_attr_dump_errors.attr, | |
b481de9c ZY |
3848 | &dev_attr_flags.attr, |
3849 | &dev_attr_filter_flags.attr, | |
b481de9c | 3850 | &dev_attr_measurement.attr, |
b481de9c | 3851 | &dev_attr_retry_rate.attr, |
b481de9c ZY |
3852 | &dev_attr_status.attr, |
3853 | &dev_attr_temperature.attr, | |
b481de9c | 3854 | &dev_attr_tx_power.attr, |
d08853a3 | 3855 | #ifdef CONFIG_IWLWIFI_DEBUG |
40b8ec0b SO |
3856 | &dev_attr_debug_level.attr, |
3857 | #endif | |
b481de9c ZY |
3858 | NULL |
3859 | }; | |
3860 | ||
bb8c093b | 3861 | static struct attribute_group iwl3945_attribute_group = { |
b481de9c | 3862 | .name = NULL, /* put in device directory */ |
bb8c093b | 3863 | .attrs = iwl3945_sysfs_entries, |
b481de9c ZY |
3864 | }; |
3865 | ||
bb8c093b CH |
3866 | static struct ieee80211_ops iwl3945_hw_ops = { |
3867 | .tx = iwl3945_mac_tx, | |
3868 | .start = iwl3945_mac_start, | |
3869 | .stop = iwl3945_mac_stop, | |
cbb6ab94 | 3870 | .add_interface = iwl_mac_add_interface, |
d8052319 | 3871 | .remove_interface = iwl_mac_remove_interface, |
4808368d | 3872 | .config = iwl_mac_config, |
8ccde88a | 3873 | .configure_filter = iwl_configure_filter, |
bb8c093b | 3874 | .set_key = iwl3945_mac_set_key, |
488829f1 | 3875 | .conf_tx = iwl_mac_conf_tx, |
bd564261 | 3876 | .reset_tsf = iwl_mac_reset_tsf, |
5bbe233b | 3877 | .bss_info_changed = iwl_bss_info_changed, |
fe6b23dd RC |
3878 | .hw_scan = iwl_mac_hw_scan, |
3879 | .sta_add = iwl3945_mac_sta_add, | |
3880 | .sta_remove = iwl_mac_sta_remove, | |
b481de9c ZY |
3881 | }; |
3882 | ||
e52119c5 | 3883 | static int iwl3945_init_drv(struct iwl_priv *priv) |
90a30a02 KA |
3884 | { |
3885 | int ret; | |
e6148917 | 3886 | struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; |
90a30a02 KA |
3887 | |
3888 | priv->retry_rate = 1; | |
3889 | priv->ibss_beacon = NULL; | |
3890 | ||
90a30a02 KA |
3891 | spin_lock_init(&priv->sta_lock); |
3892 | spin_lock_init(&priv->hcmd_lock); | |
3893 | ||
3894 | INIT_LIST_HEAD(&priv->free_frames); | |
3895 | ||
3896 | mutex_init(&priv->mutex); | |
d2dfe6df | 3897 | mutex_init(&priv->sync_cmd_mutex); |
90a30a02 | 3898 | |
90a30a02 KA |
3899 | priv->ieee_channels = NULL; |
3900 | priv->ieee_rates = NULL; | |
3901 | priv->band = IEEE80211_BAND_2GHZ; | |
3902 | ||
3903 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
a13d276f | 3904 | priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; |
90a30a02 | 3905 | |
62ea9c5b | 3906 | priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER; |
90a30a02 | 3907 | |
e6148917 SO |
3908 | if (eeprom->version < EEPROM_3945_EEPROM_VERSION) { |
3909 | IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n", | |
3910 | eeprom->version); | |
3911 | ret = -EINVAL; | |
3912 | goto err; | |
3913 | } | |
3914 | ret = iwl_init_channel_map(priv); | |
90a30a02 KA |
3915 | if (ret) { |
3916 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
3917 | goto err; | |
3918 | } | |
3919 | ||
e6148917 SO |
3920 | /* Set up txpower settings in driver for all channels */ |
3921 | if (iwl3945_txpower_set_from_eeprom(priv)) { | |
3922 | ret = -EIO; | |
3923 | goto err_free_channel_map; | |
3924 | } | |
3925 | ||
534166de | 3926 | ret = iwlcore_init_geos(priv); |
90a30a02 KA |
3927 | if (ret) { |
3928 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
3929 | goto err_free_channel_map; | |
3930 | } | |
534166de SO |
3931 | iwl3945_init_hw_rates(priv, priv->ieee_rates); |
3932 | ||
2a4ddaab AK |
3933 | return 0; |
3934 | ||
3935 | err_free_channel_map: | |
3936 | iwl_free_channel_map(priv); | |
3937 | err: | |
3938 | return ret; | |
3939 | } | |
3940 | ||
dd7a2509 JB |
3941 | #define IWL3945_MAX_PROBE_REQUEST 200 |
3942 | ||
2a4ddaab AK |
3943 | static int iwl3945_setup_mac(struct iwl_priv *priv) |
3944 | { | |
3945 | int ret; | |
3946 | struct ieee80211_hw *hw = priv->hw; | |
3947 | ||
3948 | hw->rate_control_algorithm = "iwl-3945-rs"; | |
3949 | hw->sta_data_size = sizeof(struct iwl3945_sta_priv); | |
fd1af15d | 3950 | hw->vif_data_size = sizeof(struct iwl_vif_priv); |
2a4ddaab AK |
3951 | |
3952 | /* Tell mac80211 our characteristics */ | |
3953 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
bc45a670 RC |
3954 | IEEE80211_HW_SPECTRUM_MGMT; |
3955 | ||
3956 | if (!priv->cfg->broken_powersave) | |
3957 | hw->flags |= IEEE80211_HW_SUPPORTS_PS | | |
3958 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | |
2a4ddaab AK |
3959 | |
3960 | hw->wiphy->interface_modes = | |
3961 | BIT(NL80211_IFTYPE_STATION) | | |
3962 | BIT(NL80211_IFTYPE_ADHOC); | |
3963 | ||
f6c8f152 | 3964 | hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY | |
5be83de5 | 3965 | WIPHY_FLAG_DISABLE_BEACON_HINTS; |
37184244 | 3966 | |
1ecf9fc1 JB |
3967 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945; |
3968 | /* we create the 802.11 header and a zero-length SSID element */ | |
dd7a2509 | 3969 | hw->wiphy->max_scan_ie_len = IWL3945_MAX_PROBE_REQUEST - 24 - 2; |
d60cc91a | 3970 | |
2a4ddaab AK |
3971 | /* Default value; 4 EDCA QOS priorities */ |
3972 | hw->queues = 4; | |
3973 | ||
534166de SO |
3974 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
3975 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
3976 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
2a4ddaab | 3977 | |
534166de SO |
3978 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) |
3979 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
3980 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
90a30a02 | 3981 | |
2a4ddaab AK |
3982 | ret = ieee80211_register_hw(priv->hw); |
3983 | if (ret) { | |
3984 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
3985 | return ret; | |
3986 | } | |
3987 | priv->mac80211_registered = 1; | |
90a30a02 | 3988 | |
2a4ddaab | 3989 | return 0; |
90a30a02 KA |
3990 | } |
3991 | ||
bb8c093b | 3992 | static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
3993 | { |
3994 | int err = 0; | |
4a8a4322 | 3995 | struct iwl_priv *priv; |
b481de9c | 3996 | struct ieee80211_hw *hw; |
c0f20d91 | 3997 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
e6148917 | 3998 | struct iwl3945_eeprom *eeprom; |
0359facc | 3999 | unsigned long flags; |
b481de9c | 4000 | |
cee53ddb KA |
4001 | /*********************** |
4002 | * 1. Allocating HW data | |
4003 | * ********************/ | |
4004 | ||
b481de9c ZY |
4005 | /* mac80211 allocates memory for this device instance, including |
4006 | * space for this driver's private structure */ | |
90a30a02 | 4007 | hw = iwl_alloc_all(cfg, &iwl3945_hw_ops); |
b481de9c | 4008 | if (hw == NULL) { |
a3139c59 | 4009 | printk(KERN_ERR DRV_NAME "Can not allocate network device\n"); |
b481de9c ZY |
4010 | err = -ENOMEM; |
4011 | goto out; | |
4012 | } | |
b481de9c | 4013 | priv = hw->priv; |
90a30a02 | 4014 | SET_IEEE80211_DEV(hw, &pdev->dev); |
6440adb5 | 4015 | |
90a30a02 KA |
4016 | /* |
4017 | * Disabling hardware scan means that mac80211 will perform scans | |
4018 | * "the hard way", rather than using device's scan. | |
4019 | */ | |
df878d8f | 4020 | if (iwl3945_mod_params.disable_hw_scan) { |
e1623446 | 4021 | IWL_DEBUG_INFO(priv, "Disabling hw_scan\n"); |
40b8ec0b SO |
4022 | iwl3945_hw_ops.hw_scan = NULL; |
4023 | } | |
4024 | ||
90a30a02 | 4025 | |
e1623446 | 4026 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
90a30a02 KA |
4027 | priv->cfg = cfg; |
4028 | priv->pci_dev = pdev; | |
40cefda9 | 4029 | priv->inta_mask = CSR_INI_SET_MASK; |
cee53ddb | 4030 | |
d08853a3 | 4031 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
4032 | atomic_set(&priv->restrict_refcnt, 0); |
4033 | #endif | |
20594eb0 WYG |
4034 | if (iwl_alloc_traffic_mem(priv)) |
4035 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 4036 | |
cee53ddb KA |
4037 | /*************************** |
4038 | * 2. Initializing PCI bus | |
4039 | * *************************/ | |
b481de9c ZY |
4040 | if (pci_enable_device(pdev)) { |
4041 | err = -ENODEV; | |
4042 | goto out_ieee80211_free_hw; | |
4043 | } | |
4044 | ||
4045 | pci_set_master(pdev); | |
4046 | ||
284901a9 | 4047 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
b481de9c | 4048 | if (!err) |
284901a9 | 4049 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
b481de9c | 4050 | if (err) { |
978785a3 | 4051 | IWL_WARN(priv, "No suitable DMA available.\n"); |
b481de9c ZY |
4052 | goto out_pci_disable_device; |
4053 | } | |
4054 | ||
4055 | pci_set_drvdata(pdev, priv); | |
4056 | err = pci_request_regions(pdev, DRV_NAME); | |
4057 | if (err) | |
4058 | goto out_pci_disable_device; | |
6440adb5 | 4059 | |
cee53ddb KA |
4060 | /*********************** |
4061 | * 3. Read REV Register | |
4062 | * ********************/ | |
b481de9c ZY |
4063 | priv->hw_base = pci_iomap(pdev, 0, 0); |
4064 | if (!priv->hw_base) { | |
4065 | err = -ENODEV; | |
4066 | goto out_pci_release_regions; | |
4067 | } | |
4068 | ||
e1623446 | 4069 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
b481de9c | 4070 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 4071 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
b481de9c | 4072 | |
cee53ddb KA |
4073 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
4074 | * PCI Tx retries from interfering with C3 CPU state */ | |
4075 | pci_write_config_byte(pdev, 0x41, 0x00); | |
b481de9c | 4076 | |
731a29b7 | 4077 | /* these spin locks will be used in apm_ops.init and EEPROM access |
a8b50a0a MA |
4078 | * we should init now |
4079 | */ | |
4080 | spin_lock_init(&priv->reg_lock); | |
731a29b7 | 4081 | spin_lock_init(&priv->lock); |
a8b50a0a | 4082 | |
4843b5a7 RC |
4083 | /* |
4084 | * stop and reset the on-board processor just in case it is in a | |
4085 | * strange state ... like being left stranded by a primary kernel | |
4086 | * and this is now the kdump kernel trying to start up | |
4087 | */ | |
4088 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
4089 | ||
cee53ddb KA |
4090 | /*********************** |
4091 | * 4. Read EEPROM | |
4092 | * ********************/ | |
90a30a02 | 4093 | |
cee53ddb | 4094 | /* Read the EEPROM */ |
e6148917 | 4095 | err = iwl_eeprom_init(priv); |
cee53ddb | 4096 | if (err) { |
15b1687c | 4097 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
c8f16138 | 4098 | goto out_iounmap; |
cee53ddb KA |
4099 | } |
4100 | /* MAC Address location in EEPROM same for 3945/4965 */ | |
e6148917 SO |
4101 | eeprom = (struct iwl3945_eeprom *)priv->eeprom; |
4102 | memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN); | |
e1623446 | 4103 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr); |
cee53ddb | 4104 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); |
b481de9c | 4105 | |
cee53ddb KA |
4106 | /*********************** |
4107 | * 5. Setup HW Constants | |
4108 | * ********************/ | |
b481de9c | 4109 | /* Device-specific setup */ |
3832ec9d | 4110 | if (iwl3945_hw_set_hw_params(priv)) { |
15b1687c | 4111 | IWL_ERR(priv, "failed to set hw settings\n"); |
c8f16138 | 4112 | goto out_eeprom_free; |
b481de9c ZY |
4113 | } |
4114 | ||
cee53ddb KA |
4115 | /*********************** |
4116 | * 6. Setup priv | |
4117 | * ********************/ | |
cee53ddb | 4118 | |
90a30a02 | 4119 | err = iwl3945_init_drv(priv); |
b481de9c | 4120 | if (err) { |
90a30a02 | 4121 | IWL_ERR(priv, "initializing driver failed\n"); |
c8f16138 | 4122 | goto out_unset_hw_params; |
b481de9c ZY |
4123 | } |
4124 | ||
978785a3 TW |
4125 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n", |
4126 | priv->cfg->name); | |
cee53ddb | 4127 | |
cee53ddb | 4128 | /*********************** |
09f9bf79 | 4129 | * 7. Setup Services |
cee53ddb KA |
4130 | * ********************/ |
4131 | ||
4132 | spin_lock_irqsave(&priv->lock, flags); | |
ed3b932e | 4133 | iwl_disable_interrupts(priv); |
cee53ddb KA |
4134 | spin_unlock_irqrestore(&priv->lock, flags); |
4135 | ||
2663516d HS |
4136 | pci_enable_msi(priv->pci_dev); |
4137 | ||
ef850d7c MA |
4138 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr, |
4139 | IRQF_SHARED, DRV_NAME, priv); | |
2663516d HS |
4140 | if (err) { |
4141 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
4142 | goto out_disable_msi; | |
4143 | } | |
4144 | ||
cee53ddb | 4145 | err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
849e0dce | 4146 | if (err) { |
15b1687c | 4147 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
90a30a02 | 4148 | goto out_release_irq; |
849e0dce | 4149 | } |
849e0dce | 4150 | |
8ccde88a SO |
4151 | iwl_set_rxon_channel(priv, |
4152 | &priv->bands[IEEE80211_BAND_2GHZ].channels[5]); | |
cee53ddb KA |
4153 | iwl3945_setup_deferred_work(priv); |
4154 | iwl3945_setup_rx_handlers(priv); | |
008a9e3e | 4155 | iwl_power_initialize(priv); |
cee53ddb | 4156 | |
cee53ddb | 4157 | /********************************* |
09f9bf79 | 4158 | * 8. Setup and Register mac80211 |
cee53ddb KA |
4159 | * *******************************/ |
4160 | ||
2a4ddaab | 4161 | iwl_enable_interrupts(priv); |
b481de9c | 4162 | |
2a4ddaab AK |
4163 | err = iwl3945_setup_mac(priv); |
4164 | if (err) | |
4165 | goto out_remove_sysfs; | |
cee53ddb | 4166 | |
a75fbe8d AK |
4167 | err = iwl_dbgfs_register(priv, DRV_NAME); |
4168 | if (err) | |
4169 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
4170 | ||
2663516d | 4171 | /* Start monitoring the killswitch */ |
ee525d13 | 4172 | queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll, |
2663516d HS |
4173 | 2 * HZ); |
4174 | ||
b481de9c ZY |
4175 | return 0; |
4176 | ||
cee53ddb | 4177 | out_remove_sysfs: |
c8f16138 RC |
4178 | destroy_workqueue(priv->workqueue); |
4179 | priv->workqueue = NULL; | |
cee53ddb | 4180 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 4181 | out_release_irq: |
2663516d | 4182 | free_irq(priv->pci_dev->irq, priv); |
2663516d HS |
4183 | out_disable_msi: |
4184 | pci_disable_msi(priv->pci_dev); | |
c8f16138 RC |
4185 | iwlcore_free_geos(priv); |
4186 | iwl_free_channel_map(priv); | |
4187 | out_unset_hw_params: | |
4188 | iwl3945_unset_hw_params(priv); | |
4189 | out_eeprom_free: | |
4190 | iwl_eeprom_free(priv); | |
b481de9c ZY |
4191 | out_iounmap: |
4192 | pci_iounmap(pdev, priv->hw_base); | |
4193 | out_pci_release_regions: | |
4194 | pci_release_regions(pdev); | |
4195 | out_pci_disable_device: | |
b481de9c | 4196 | pci_set_drvdata(pdev, NULL); |
623d563e | 4197 | pci_disable_device(pdev); |
b481de9c | 4198 | out_ieee80211_free_hw: |
20594eb0 | 4199 | iwl_free_traffic_mem(priv); |
d7c76f4c | 4200 | ieee80211_free_hw(priv->hw); |
b481de9c ZY |
4201 | out: |
4202 | return err; | |
4203 | } | |
4204 | ||
c83dbf68 | 4205 | static void __devexit iwl3945_pci_remove(struct pci_dev *pdev) |
b481de9c | 4206 | { |
4a8a4322 | 4207 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 4208 | unsigned long flags; |
b481de9c ZY |
4209 | |
4210 | if (!priv) | |
4211 | return; | |
4212 | ||
e1623446 | 4213 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 4214 | |
a75fbe8d AK |
4215 | iwl_dbgfs_unregister(priv); |
4216 | ||
b481de9c | 4217 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
b24d22b1 | 4218 | |
d552bfb6 KA |
4219 | if (priv->mac80211_registered) { |
4220 | ieee80211_unregister_hw(priv->hw); | |
4221 | priv->mac80211_registered = 0; | |
4222 | } else { | |
4223 | iwl3945_down(priv); | |
4224 | } | |
b481de9c | 4225 | |
c166b25a BC |
4226 | /* |
4227 | * Make sure device is reset to low power before unloading driver. | |
4228 | * This may be redundant with iwl_down(), but there are paths to | |
4229 | * run iwl_down() without calling apm_ops.stop(), and there are | |
4230 | * paths to avoid running iwl_down() at all before leaving driver. | |
4231 | * This (inexpensive) call *makes sure* device is reset. | |
4232 | */ | |
4233 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
4234 | ||
0359facc MA |
4235 | /* make sure we flush any pending irq or |
4236 | * tasklet for the driver | |
4237 | */ | |
4238 | spin_lock_irqsave(&priv->lock, flags); | |
ed3b932e | 4239 | iwl_disable_interrupts(priv); |
0359facc MA |
4240 | spin_unlock_irqrestore(&priv->lock, flags); |
4241 | ||
4242 | iwl_synchronize_irq(priv); | |
4243 | ||
bb8c093b | 4244 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
b481de9c | 4245 | |
ee525d13 | 4246 | cancel_delayed_work_sync(&priv->_3945.rfkill_poll); |
2663516d | 4247 | |
bb8c093b | 4248 | iwl3945_dealloc_ucode_pci(priv); |
b481de9c ZY |
4249 | |
4250 | if (priv->rxq.bd) | |
df833b1d | 4251 | iwl3945_rx_queue_free(priv, &priv->rxq); |
bb8c093b | 4252 | iwl3945_hw_txq_ctx_free(priv); |
b481de9c | 4253 | |
3832ec9d | 4254 | iwl3945_unset_hw_params(priv); |
b481de9c | 4255 | |
6ef89d0a MA |
4256 | /*netif_stop_queue(dev); */ |
4257 | flush_workqueue(priv->workqueue); | |
4258 | ||
bb8c093b | 4259 | /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes |
b481de9c ZY |
4260 | * priv->workqueue... so we can't take down the workqueue |
4261 | * until now... */ | |
4262 | destroy_workqueue(priv->workqueue); | |
4263 | priv->workqueue = NULL; | |
20594eb0 | 4264 | iwl_free_traffic_mem(priv); |
b481de9c | 4265 | |
2663516d HS |
4266 | free_irq(pdev->irq, priv); |
4267 | pci_disable_msi(pdev); | |
4268 | ||
b481de9c ZY |
4269 | pci_iounmap(pdev, priv->hw_base); |
4270 | pci_release_regions(pdev); | |
4271 | pci_disable_device(pdev); | |
4272 | pci_set_drvdata(pdev, NULL); | |
4273 | ||
e6148917 | 4274 | iwl_free_channel_map(priv); |
534166de | 4275 | iwlcore_free_geos(priv); |
811ecc99 | 4276 | kfree(priv->scan_cmd); |
b481de9c ZY |
4277 | if (priv->ibss_beacon) |
4278 | dev_kfree_skb(priv->ibss_beacon); | |
4279 | ||
4280 | ieee80211_free_hw(priv->hw); | |
4281 | } | |
4282 | ||
b481de9c ZY |
4283 | |
4284 | /***************************************************************************** | |
4285 | * | |
4286 | * driver and module entry point | |
4287 | * | |
4288 | *****************************************************************************/ | |
4289 | ||
bb8c093b | 4290 | static struct pci_driver iwl3945_driver = { |
b481de9c | 4291 | .name = DRV_NAME, |
bb8c093b CH |
4292 | .id_table = iwl3945_hw_card_ids, |
4293 | .probe = iwl3945_pci_probe, | |
4294 | .remove = __devexit_p(iwl3945_pci_remove), | |
b481de9c | 4295 | #ifdef CONFIG_PM |
6da3a13e WYG |
4296 | .suspend = iwl_pci_suspend, |
4297 | .resume = iwl_pci_resume, | |
b481de9c ZY |
4298 | #endif |
4299 | }; | |
4300 | ||
bb8c093b | 4301 | static int __init iwl3945_init(void) |
b481de9c ZY |
4302 | { |
4303 | ||
4304 | int ret; | |
4305 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
4306 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 RC |
4307 | |
4308 | ret = iwl3945_rate_control_register(); | |
4309 | if (ret) { | |
a3139c59 SO |
4310 | printk(KERN_ERR DRV_NAME |
4311 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
4312 | return ret; |
4313 | } | |
4314 | ||
bb8c093b | 4315 | ret = pci_register_driver(&iwl3945_driver); |
b481de9c | 4316 | if (ret) { |
a3139c59 | 4317 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 4318 | goto error_register; |
b481de9c | 4319 | } |
b481de9c ZY |
4320 | |
4321 | return ret; | |
897e1cf2 | 4322 | |
897e1cf2 RC |
4323 | error_register: |
4324 | iwl3945_rate_control_unregister(); | |
4325 | return ret; | |
b481de9c ZY |
4326 | } |
4327 | ||
bb8c093b | 4328 | static void __exit iwl3945_exit(void) |
b481de9c | 4329 | { |
bb8c093b | 4330 | pci_unregister_driver(&iwl3945_driver); |
897e1cf2 | 4331 | iwl3945_rate_control_unregister(); |
b481de9c ZY |
4332 | } |
4333 | ||
a0987a8d | 4334 | MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX)); |
25cb6cad | 4335 | |
4e30cb69 | 4336 | module_param_named(antenna, iwl3945_mod_params.antenna, int, S_IRUGO); |
b481de9c | 4337 | MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])"); |
4e30cb69 | 4338 | module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, S_IRUGO); |
9c74d9fb SO |
4339 | MODULE_PARM_DESC(swcrypto, |
4340 | "using software crypto (default 1 [software])\n"); | |
a562a9dd | 4341 | #ifdef CONFIG_IWLWIFI_DEBUG |
4e30cb69 | 4342 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
b481de9c | 4343 | MODULE_PARM_DESC(debug, "debug output mask"); |
a562a9dd | 4344 | #endif |
4e30cb69 WYG |
4345 | module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, |
4346 | int, S_IRUGO); | |
b481de9c | 4347 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); |
4e30cb69 | 4348 | module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, S_IRUGO); |
af48d048 SO |
4349 | MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error"); |
4350 | ||
bb8c093b CH |
4351 | module_exit(iwl3945_exit); |
4352 | module_init(iwl3945_init); |