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iwlwifi: use the results from disconnected antenna algorithm
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-tx.c
CommitLineData
1053d35f
RR		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
fd4abac5 30#include <linux/etherdevice.h>
1053d35f
RR		 31#include <net/mac80211.h>
32#include "iwl-eeprom.h"
33#include "iwl-dev.h"
34#include "iwl-core.h"
35#include "iwl-sta.h"
36#include "iwl-io.h"
37#include "iwl-helpers.h"
38
30e553e3
TW		 39static const u16 default_tid_to_tx_fifo[] = {
40 IWL_TX_FIFO_AC1,
41 IWL_TX_FIFO_AC0,
42 IWL_TX_FIFO_AC0,
43 IWL_TX_FIFO_AC1,
44 IWL_TX_FIFO_AC2,
45 IWL_TX_FIFO_AC2,
46 IWL_TX_FIFO_AC3,
47 IWL_TX_FIFO_AC3,
48 IWL_TX_FIFO_NONE,
49 IWL_TX_FIFO_NONE,
50 IWL_TX_FIFO_NONE,
51 IWL_TX_FIFO_NONE,
52 IWL_TX_FIFO_NONE,
53 IWL_TX_FIFO_NONE,
54 IWL_TX_FIFO_NONE,
55 IWL_TX_FIFO_NONE,
56 IWL_TX_FIFO_AC3
57};
58
30e553e3 59
1053d35f
RR		 60/**
61 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
62 *
63 * Does NOT advance any TFD circular buffer read/write indexes
64 * Does NOT free the TFD itself (which is within circular buffer)
65 */
16466903 66int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
1053d35f
RR		 67{
68 struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0];
69 struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
70 struct pci_dev *dev = priv->pci_dev;
71 int i;
72 int counter = 0;
73 int index, is_odd;
74
75 /* Host command buffers stay mapped in memory, nothing to clean */
76 if (txq->q.id == IWL_CMD_QUEUE_NUM)
77 return 0;
78
79 /* Sanity check on number of chunks */
80 counter = IWL_GET_BITS(*bd, num_tbs);
81 if (counter > MAX_NUM_OF_TBS) {
82 IWL_ERROR("Too many chunks: %i\n", counter);
83 /* @todo issue fatal error, it is quite serious situation */
84 return 0;
85 }
86
87 /* Unmap chunks, if any.
88 * TFD info for odd chunks is different format than for even chunks. */
89 for (i = 0; i < counter; i++) {
90 index = i / 2;
91 is_odd = i & 0x1;
92
93 if (is_odd)
94 pci_unmap_single(
95 dev,
96 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
97 (IWL_GET_BITS(bd->pa[index],
98 tb2_addr_hi20) << 16),
99 IWL_GET_BITS(bd->pa[index], tb2_len),
100 PCI_DMA_TODEVICE);
101
102 else if (i > 0)
103 pci_unmap_single(dev,
104 le32_to_cpu(bd->pa[index].tb1_addr),
105 IWL_GET_BITS(bd->pa[index], tb1_len),
106 PCI_DMA_TODEVICE);
107
108 /* Free SKB, if any, for this chunk */
109 if (txq->txb[txq->q.read_ptr].skb[i]) {
110 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
111
112 dev_kfree_skb(skb);
113 txq->txb[txq->q.read_ptr].skb[i] = NULL;
114 }
115 }
116 return 0;
117}
118EXPORT_SYMBOL(iwl_hw_txq_free_tfd);
119
fd4abac5
TW		 120
121int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
122 dma_addr_t addr, u16 len)
123{
124 int index, is_odd;
125 struct iwl_tfd_frame *tfd = ptr;
126 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
127
128 /* Each TFD can point to a maximum 20 Tx buffers */
73ae98a1 129 if (num_tbs >= MAX_NUM_OF_TBS) {
fd4abac5
TW		 130 IWL_ERROR("Error can not send more than %d chunks\n",
131 MAX_NUM_OF_TBS);
132 return -EINVAL;
133 }
134
135 index = num_tbs / 2;
136 is_odd = num_tbs & 0x1;
137
138 if (!is_odd) {
139 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
140 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
141 iwl_get_dma_hi_address(addr));
142 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
143 } else {
144 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
145 (u32) (addr & 0xffff));
146 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
147 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
148 }
149
150 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
151
152 return 0;
153}
154EXPORT_SYMBOL(iwl_hw_txq_attach_buf_to_tfd);
155
156/**
157 * iwl_txq_update_write_ptr - Send new write index to hardware
158 */
159int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
160{
161 u32 reg = 0;
162 int ret = 0;
163 int txq_id = txq->q.id;
164
165 if (txq->need_update == 0)
166 return ret;
167
168 /* if we're trying to save power */
169 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
170 /* wake up nic if it's powered down ...
171 * uCode will wake up, and interrupt us again, so next
172 * time we'll skip this part. */
173 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
174
175 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
176 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
177 iwl_set_bit(priv, CSR_GP_CNTRL,
178 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
179 return ret;
180 }
181
182 /* restore this queue's parameters in nic hardware. */
183 ret = iwl_grab_nic_access(priv);
184 if (ret)
185 return ret;
186 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
187 txq->q.write_ptr | (txq_id << 8));
188 iwl_release_nic_access(priv);
189
190 /* else not in power-save mode, uCode will never sleep when we're
191 * trying to tx (during RFKILL, we're not trying to tx). */
192 } else
193 iwl_write32(priv, HBUS_TARG_WRPTR,
194 txq->q.write_ptr | (txq_id << 8));
195
196 txq->need_update = 0;
197
198 return ret;
199}
200EXPORT_SYMBOL(iwl_txq_update_write_ptr);
201
202
1053d35f
RR		 203/**
204 * iwl_tx_queue_free - Deallocate DMA queue.
205 * @txq: Transmit queue to deallocate.
206 *
207 * Empty queue by removing and destroying all BD's.
208 * Free all buffers.
209 * 0-fill, but do not free "txq" descriptor structure.
210 */
da99c4b6 211static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
1053d35f 212{
da99c4b6 213 struct iwl_tx_queue *txq = &priv->txq[txq_id];
443cfd45 214 struct iwl_queue *q = &txq->q;
1053d35f 215 struct pci_dev *dev = priv->pci_dev;
da99c4b6 216 int i, slots_num, len;
1053d35f
RR		 217
218 if (q->n_bd == 0)
219 return;
220
221 /* first, empty all BD's */
222 for (; q->write_ptr != q->read_ptr;
223 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
224 iwl_hw_txq_free_tfd(priv, txq);
225
226 len = sizeof(struct iwl_cmd) * q->n_window;
227 if (q->id == IWL_CMD_QUEUE_NUM)
228 len += IWL_MAX_SCAN_SIZE;
229
230 /* De-alloc array of command/tx buffers */
da99c4b6
GG		 231 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
232 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
233 for (i = 0; i < slots_num; i++)
234 kfree(txq->cmd[i]);
235 if (txq_id == IWL_CMD_QUEUE_NUM)
236 kfree(txq->cmd[slots_num]);
1053d35f
RR		 237
238 /* De-alloc circular buffer of TFDs */
239 if (txq->q.n_bd)
240 pci_free_consistent(dev, sizeof(struct iwl_tfd_frame) *
241 txq->q.n_bd, txq->bd, txq->q.dma_addr);
242
243 /* De-alloc array of per-TFD driver data */
244 kfree(txq->txb);
245 txq->txb = NULL;
246
247 /* 0-fill queue descriptor structure */
248 memset(txq, 0, sizeof(*txq));
249}
250
fd4abac5
TW		 251/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
252 * DMA services
253 *
254 * Theory of operation
255 *
256 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
257 * of buffer descriptors, each of which points to one or more data buffers for
258 * the device to read from or fill. Driver and device exchange status of each
259 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
260 * entries in each circular buffer, to protect against confusing empty and full
261 * queue states.
262 *
263 * The device reads or writes the data in the queues via the device's several
264 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
265 *
266 * For Tx queue, there are low mark and high mark limits. If, after queuing
267 * the packet for Tx, free space become < low mark, Tx queue stopped. When
268 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
269 * Tx queue resumed.
270 *
271 * See more detailed info in iwl-4965-hw.h.
272 ***************************************************/
273
274int iwl_queue_space(const struct iwl_queue *q)
275{
276 int s = q->read_ptr - q->write_ptr;
277
278 if (q->read_ptr > q->write_ptr)
279 s -= q->n_bd;
280
281 if (s <= 0)
282 s += q->n_window;
283 /* keep some reserve to not confuse empty and full situations */
284 s -= 2;
285 if (s < 0)
286 s = 0;
287 return s;
288}
289EXPORT_SYMBOL(iwl_queue_space);
290
291
1053d35f
RR		 292/**
293 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
294 */
443cfd45 295static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
1053d35f
RR		 296 int count, int slots_num, u32 id)
297{
298 q->n_bd = count;
299 q->n_window = slots_num;
300 q->id = id;
301
302 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
303 * and iwl_queue_dec_wrap are broken. */
304 BUG_ON(!is_power_of_2(count));
305
306 /* slots_num must be power-of-two size, otherwise
307 * get_cmd_index is broken. */
308 BUG_ON(!is_power_of_2(slots_num));
309
310 q->low_mark = q->n_window / 4;
311 if (q->low_mark < 4)
312 q->low_mark = 4;
313
314 q->high_mark = q->n_window / 8;
315 if (q->high_mark < 2)
316 q->high_mark = 2;
317
318 q->write_ptr = q->read_ptr = 0;
319
320 return 0;
321}
322
323/**
324 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
325 */
326static int iwl_tx_queue_alloc(struct iwl_priv *priv,
16466903 327 struct iwl_tx_queue *txq, u32 id)
1053d35f
RR		 328{
329 struct pci_dev *dev = priv->pci_dev;
330
331 /* Driver private data, only for Tx (not command) queues,
332 * not shared with device. */
333 if (id != IWL_CMD_QUEUE_NUM) {
334 txq->txb = kmalloc(sizeof(txq->txb[0]) *
335 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
336 if (!txq->txb) {
337 IWL_ERROR("kmalloc for auxiliary BD "
338 "structures failed\n");
339 goto error;
340 }
341 } else
342 txq->txb = NULL;
343
344 /* Circular buffer of transmit frame descriptors (TFDs),
345 * shared with device */
346 txq->bd = pci_alloc_consistent(dev,
347 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
348 &txq->q.dma_addr);
349
350 if (!txq->bd) {
351 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
352 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
353 goto error;
354 }
355 txq->q.id = id;
356
357 return 0;
358
359 error:
360 kfree(txq->txb);
361 txq->txb = NULL;
362
363 return -ENOMEM;
364}
365
366/*
367 * Tell nic where to find circular buffer of Tx Frame Descriptors for
368 * given Tx queue, and enable the DMA channel used for that queue.
369 *
370 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
371 * channels supported in hardware.
372 */
373static int iwl_hw_tx_queue_init(struct iwl_priv *priv,
16466903 374 struct iwl_tx_queue *txq)
1053d35f
RR		 375{
376 int rc;
377 unsigned long flags;
378 int txq_id = txq->q.id;
379
380 spin_lock_irqsave(&priv->lock, flags);
381 rc = iwl_grab_nic_access(priv);
382 if (rc) {
383 spin_unlock_irqrestore(&priv->lock, flags);
384 return rc;
385 }
386
387 /* Circular buffer (TFD queue in DRAM) physical base address */
388 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
389 txq->q.dma_addr >> 8);
390
391 /* Enable DMA channel, using same id as for TFD queue */
392 iwl_write_direct32(
393 priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
394 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
395 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
396 iwl_release_nic_access(priv);
397 spin_unlock_irqrestore(&priv->lock, flags);
398
399 return 0;
400}
401
402/**
403 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
404 */
73b7d742 405static int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
1053d35f
RR		 406 int slots_num, u32 txq_id)
407{
da99c4b6 408 int i, len;
73b7d742 409 int ret;
1053d35f
RR		 410
411 /*
412 * Alloc buffer array for commands (Tx or other types of commands).
413 * For the command queue (#4), allocate command space + one big
414 * command for scan, since scan command is very huge; the system will
415 * not have two scans at the same time, so only one is needed.
416 * For normal Tx queues (all other queues), no super-size command
417 * space is needed.
418 */
da99c4b6
GG		 419 len = sizeof(struct iwl_cmd);
420 for (i = 0; i <= slots_num; i++) {
421 if (i == slots_num) {
422 if (txq_id == IWL_CMD_QUEUE_NUM)
423 len += IWL_MAX_SCAN_SIZE;
424 else
425 continue;
426 }
427
49898852 428 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
da99c4b6 429 if (!txq->cmd[i])
73b7d742 430 goto err;
da99c4b6 431 }
1053d35f
RR		 432
433 /* Alloc driver data array and TFD circular buffer */
73b7d742
TW		 434 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
435 if (ret)
436 goto err;
1053d35f 437
1053d35f
RR		 438 txq->need_update = 0;
439
440 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
441 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
442 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
443
444 /* Initialize queue's high/low-water marks, and head/tail indexes */
445 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
446
447 /* Tell device where to find queue */
448 iwl_hw_tx_queue_init(priv, txq);
449
450 return 0;
73b7d742
TW		 451err:
452 for (i = 0; i < slots_num; i++) {
453 kfree(txq->cmd[i]);
454 txq->cmd[i] = NULL;
455 }
456
457 if (txq_id == IWL_CMD_QUEUE_NUM) {
458 kfree(txq->cmd[slots_num]);
459 txq->cmd[slots_num] = NULL;
460 }
461 return -ENOMEM;
1053d35f 462}
da1bc453
TW		 463/**
464 * iwl_hw_txq_ctx_free - Free TXQ Context
465 *
466 * Destroy all TX DMA queues and structures
467 */
468void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
469{
470 int txq_id;
471
472 /* Tx queues */
473 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
da99c4b6 474 iwl_tx_queue_free(priv, txq_id);
da1bc453
TW		 475
476 /* Keep-warm buffer */
477 iwl_kw_free(priv);
478}
479EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
480
1053d35f
RR		 481
482/**
483 * iwl_txq_ctx_reset - Reset TX queue context
484 * Destroys all DMA structures and initialise them again
485 *
486 * @param priv
487 * @return error code
488 */
489int iwl_txq_ctx_reset(struct iwl_priv *priv)
490{
491 int ret = 0;
492 int txq_id, slots_num;
da1bc453 493 unsigned long flags;
1053d35f
RR		 494
495 iwl_kw_free(priv);
496
497 /* Free all tx/cmd queues and keep-warm buffer */
498 iwl_hw_txq_ctx_free(priv);
499
500 /* Alloc keep-warm buffer */
501 ret = iwl_kw_alloc(priv);
502 if (ret) {
6f147926 503 IWL_ERROR("Keep Warm allocation failed\n");
1053d35f
RR		 504 goto error_kw;
505 }
da1bc453
TW		 506 spin_lock_irqsave(&priv->lock, flags);
507 ret = iwl_grab_nic_access(priv);
508 if (unlikely(ret)) {
509 spin_unlock_irqrestore(&priv->lock, flags);
510 goto error_reset;
511 }
1053d35f
RR		 512
513 /* Turn off all Tx DMA fifos */
da1bc453
TW		 514 priv->cfg->ops->lib->txq_set_sched(priv, 0);
515
516 iwl_release_nic_access(priv);
517 spin_unlock_irqrestore(&priv->lock, flags);
518
1053d35f
RR		 519
520 /* Tell nic where to find the keep-warm buffer */
521 ret = iwl_kw_init(priv);
522 if (ret) {
523 IWL_ERROR("kw_init failed\n");
524 goto error_reset;
525 }
526
da1bc453 527 /* Alloc and init all Tx queues, including the command queue (#4) */
1053d35f
RR		 528 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
529 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
530 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
531 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
532 txq_id);
533 if (ret) {
534 IWL_ERROR("Tx %d queue init failed\n", txq_id);
535 goto error;
536 }
537 }
538
539 return ret;
540
541 error:
542 iwl_hw_txq_ctx_free(priv);
543 error_reset:
544 iwl_kw_free(priv);
545 error_kw:
546 return ret;
547}
da1bc453
TW		 548/**
549 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
550 */
551void iwl_txq_ctx_stop(struct iwl_priv *priv)
552{
553
554 int txq_id;
555 unsigned long flags;
556
557
558 /* Turn off all Tx DMA fifos */
559 spin_lock_irqsave(&priv->lock, flags);
560 if (iwl_grab_nic_access(priv)) {
561 spin_unlock_irqrestore(&priv->lock, flags);
562 return;
563 }
564
565 priv->cfg->ops->lib->txq_set_sched(priv, 0);
566
567 /* Stop each Tx DMA channel, and wait for it to be idle */
568 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
569 iwl_write_direct32(priv,
570 FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
571 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
572 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
573 (txq_id), 200);
574 }
575 iwl_release_nic_access(priv);
576 spin_unlock_irqrestore(&priv->lock, flags);
577
578 /* Deallocate memory for all Tx queues */
579 iwl_hw_txq_ctx_free(priv);
580}
581EXPORT_SYMBOL(iwl_txq_ctx_stop);
fd4abac5
TW		 582
583/*
584 * handle build REPLY_TX command notification.
585 */
586static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
587 struct iwl_tx_cmd *tx_cmd,
e039fa4a 588 struct ieee80211_tx_info *info,
fd4abac5
TW		 589 struct ieee80211_hdr *hdr,
590 int is_unicast, u8 std_id)
591{
fd7c8a40 592 __le16 fc = hdr->frame_control;
fd4abac5
TW		 593 __le32 tx_flags = tx_cmd->tx_flags;
594
595 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 596 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
fd4abac5 597 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 598 if (ieee80211_is_mgmt(fc))
fd4abac5 599 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 600 if (ieee80211_is_probe_resp(fc) &&
fd4abac5
TW		 601 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
602 tx_flags |= TX_CMD_FLG_TSF_MSK;
603 } else {
604 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
605 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
606 }
607
fd7c8a40 608 if (ieee80211_is_back_req(fc))
fd4abac5
TW		 609 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
610
611
612 tx_cmd->sta_id = std_id;
8b7b1e05 613 if (ieee80211_has_morefrags(fc))
fd4abac5
TW		 614 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
615
fd7c8a40
HH		 616 if (ieee80211_is_data_qos(fc)) {
617 u8 *qc = ieee80211_get_qos_ctl(hdr);
fd4abac5
TW		 618 tx_cmd->tid_tspec = qc[0] & 0xf;
619 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
620 } else {
621 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
622 }
623
a326a5d0 624 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
fd4abac5
TW		 625
626 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
627 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
628
629 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH		 630 if (ieee80211_is_mgmt(fc)) {
631 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
fd4abac5
TW		 632 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
633 else
634 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
635 } else {
636 tx_cmd->timeout.pm_frame_timeout = 0;
637 }
638
639 tx_cmd->driver_txop = 0;
640 tx_cmd->tx_flags = tx_flags;
641 tx_cmd->next_frame_len = 0;
642}
643
644#define RTS_HCCA_RETRY_LIMIT 3
645#define RTS_DFAULT_RETRY_LIMIT 60
646
647static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
648 struct iwl_tx_cmd *tx_cmd,
e039fa4a 649 struct ieee80211_tx_info *info,
fd7c8a40 650 __le16 fc, int sta_id,
fd4abac5
TW		 651 int is_hcca)
652{
653 u8 rts_retry_limit = 0;
654 u8 data_retry_limit = 0;
655 u8 rate_plcp;
656 u16 rate_flags = 0;
2e92e6f2
JB		 657 int rate_idx;
658
e039fa4a 659 rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff,
2e92e6f2 660 IWL_RATE_COUNT - 1);
fd4abac5
TW		 661
662 rate_plcp = iwl_rates[rate_idx].plcp;
663
664 rts_retry_limit = (is_hcca) ?
665 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
666
667 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
668 rate_flags |= RATE_MCS_CCK_MSK;
669
670
fd7c8a40 671 if (ieee80211_is_probe_resp(fc)) {
fd4abac5
TW		 672 data_retry_limit = 3;
673 if (data_retry_limit < rts_retry_limit)
674 rts_retry_limit = data_retry_limit;
675 } else
676 data_retry_limit = IWL_DEFAULT_TX_RETRY;
677
678 if (priv->data_retry_limit != -1)
679 data_retry_limit = priv->data_retry_limit;
680
681
682 if (ieee80211_is_data(fc)) {
683 tx_cmd->initial_rate_index = 0;
684 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
685 } else {
fd7c8a40
HH		 686 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
687 case cpu_to_le16(IEEE80211_STYPE_AUTH):
688 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
689 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
690 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
fd4abac5
TW		 691 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
692 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
693 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
694 }
695 break;
696 default:
697 break;
698 }
699
700 /* Alternate between antenna A and B for successive frames */
701 if (priv->use_ant_b_for_management_frame) {
702 priv->use_ant_b_for_management_frame = 0;
703 rate_flags |= RATE_MCS_ANT_B_MSK;
704 } else {
705 priv->use_ant_b_for_management_frame = 1;
706 rate_flags |= RATE_MCS_ANT_A_MSK;
707 }
708 }
709
710 tx_cmd->rts_retry_limit = rts_retry_limit;
711 tx_cmd->data_retry_limit = data_retry_limit;
e7d326ac 712 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
fd4abac5
TW		 713}
714
715static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
e039fa4a 716 struct ieee80211_tx_info *info,
fd4abac5
TW		 717 struct iwl_tx_cmd *tx_cmd,
718 struct sk_buff *skb_frag,
719 int sta_id)
720{
e039fa4a 721 struct ieee80211_key_conf *keyconf = info->control.hw_key;
fd4abac5 722
ccc038ab 723 switch (keyconf->alg) {
fd4abac5
TW		 724 case ALG_CCMP:
725 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
ccc038ab 726 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
e039fa4a 727 if (info->flags & IEEE80211_TX_CTL_AMPDU)
fd4abac5
TW		 728 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
729 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
730 break;
731
732 case ALG_TKIP:
733 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
ccc038ab 734 ieee80211_get_tkip_key(keyconf, skb_frag,
fd4abac5
TW		 735 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
736 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
737 break;
738
739 case ALG_WEP:
fd4abac5 740 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
ccc038ab
EG		 741 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
742
743 if (keyconf->keylen == WEP_KEY_LEN_128)
744 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
745
746 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
fd4abac5
TW		 747
748 IWL_DEBUG_TX("Configuring packet for WEP encryption "
ccc038ab 749 "with key %d\n", keyconf->keyidx);
fd4abac5
TW		 750 break;
751
752 default:
ccc038ab 753 printk(KERN_ERR "Unknown encode alg %d\n", keyconf->alg);
fd4abac5
TW		 754 break;
755 }
756}
757
758static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
759{
760 /* 0 - mgmt, 1 - cnt, 2 - data */
761 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
762 priv->tx_stats[idx].cnt++;
763 priv->tx_stats[idx].bytes += len;
764}
765
766/*
767 * start REPLY_TX command process
768 */
e039fa4a 769int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
fd4abac5
TW		 770{
771 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 772 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fd4abac5 773 struct iwl_tfd_frame *tfd;
f3674227
TW		 774 struct iwl_tx_queue *txq;
775 struct iwl_queue *q;
776 struct iwl_cmd *out_cmd;
777 struct iwl_tx_cmd *tx_cmd;
778 int swq_id, txq_id;
fd4abac5
TW		 779 dma_addr_t phys_addr;
780 dma_addr_t txcmd_phys;
781 dma_addr_t scratch_phys;
fd4abac5
TW		 782 u16 len, idx, len_org;
783 u16 seq_number = 0;
fd7c8a40 784 __le16 fc;
f3674227
TW		 785 u8 hdr_len, unicast;
786 u8 sta_id;
fd4abac5
TW		 787 u8 wait_write_ptr = 0;
788 u8 tid = 0;
789 u8 *qc = NULL;
790 unsigned long flags;
791 int ret;
792
793 spin_lock_irqsave(&priv->lock, flags);
794 if (iwl_is_rfkill(priv)) {
795 IWL_DEBUG_DROP("Dropping - RF KILL\n");
796 goto drop_unlock;
797 }
798
e039fa4a 799 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) ==
2e92e6f2 800 IWL_INVALID_RATE) {
fd4abac5
TW		 801 IWL_ERROR("ERROR: No TX rate available.\n");
802 goto drop_unlock;
803 }
804
805 unicast = !is_multicast_ether_addr(hdr->addr1);
fd4abac5 806
fd7c8a40 807 fc = hdr->frame_control;
fd4abac5
TW		 808
809#ifdef CONFIG_IWLWIFI_DEBUG
810 if (ieee80211_is_auth(fc))
811 IWL_DEBUG_TX("Sending AUTH frame\n");
fd7c8a40 812 else if (ieee80211_is_assoc_req(fc))
fd4abac5 813 IWL_DEBUG_TX("Sending ASSOC frame\n");
fd7c8a40 814 else if (ieee80211_is_reassoc_req(fc))
fd4abac5
TW		 815 IWL_DEBUG_TX("Sending REASSOC frame\n");
816#endif
817
818 /* drop all data frame if we are not associated */
fd7c8a40 819 if (ieee80211_is_data(fc) &&
d10c4ec8
SG		 820 (priv->iw_mode != IEEE80211_IF_TYPE_MNTR ||
821 !(info->flags & IEEE80211_TX_CTL_INJECTED)) && /* packet injection */
822 (!iwl_is_associated(priv) ||
823 ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id) ||
824 !priv->assoc_station_added)) {
fd4abac5
TW		 825 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
826 goto drop_unlock;
827 }
828
829 spin_unlock_irqrestore(&priv->lock, flags);
830
7294ec95 831 hdr_len = ieee80211_hdrlen(fc);
fd4abac5
TW		 832
833 /* Find (or create) index into station table for destination station */
834 sta_id = iwl_get_sta_id(priv, hdr);
835 if (sta_id == IWL_INVALID_STATION) {
836 DECLARE_MAC_BUF(mac);
837
838 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
839 print_mac(mac, hdr->addr1));
840 goto drop;
841 }
842
843 IWL_DEBUG_TX("station Id %d\n", sta_id);
844
f3674227
TW		 845 swq_id = skb_get_queue_mapping(skb);
846 txq_id = swq_id;
fd7c8a40
HH		 847 if (ieee80211_is_data_qos(fc)) {
848 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 849 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
f3674227
TW		 850 seq_number = priv->stations[sta_id].tid[tid].seq_number;
851 seq_number &= IEEE80211_SCTL_SEQ;
852 hdr->seq_ctrl = hdr->seq_ctrl &
853 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG);
854 hdr->seq_ctrl |= cpu_to_le16(seq_number);
fd4abac5 855 seq_number += 0x10;
fd4abac5 856 /* aggregation is on for this <sta,tid> */
e039fa4a 857 if (info->flags & IEEE80211_TX_CTL_AMPDU)
fd4abac5
TW		 858 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
859 priv->stations[sta_id].tid[tid].tfds_in_queue++;
fd4abac5
TW		 860 }
861
862 /* Descriptor for chosen Tx queue */
863 txq = &priv->txq[txq_id];
864 q = &txq->q;
865
866 spin_lock_irqsave(&priv->lock, flags);
867
868 /* Set up first empty TFD within this queue's circular TFD buffer */
869 tfd = &txq->bd[q->write_ptr];
870 memset(tfd, 0, sizeof(*tfd));
fd4abac5
TW		 871 idx = get_cmd_index(q, q->write_ptr, 0);
872
873 /* Set up driver data for this TFD */
874 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
875 txq->txb[q->write_ptr].skb[0] = skb;
fd4abac5
TW		 876
877 /* Set up first empty entry in queue's array of Tx/cmd buffers */
da99c4b6 878 out_cmd = txq->cmd[idx];
fd4abac5
TW		 879 tx_cmd = &out_cmd->cmd.tx;
880 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
881 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
882
883 /*
884 * Set up the Tx-command (not MAC!) header.
885 * Store the chosen Tx queue and TFD index within the sequence field;
886 * after Tx, uCode's Tx response will return this value so driver can
887 * locate the frame within the tx queue and do post-tx processing.
888 */
889 out_cmd->hdr.cmd = REPLY_TX;
890 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
891 INDEX_TO_SEQ(q->write_ptr)));
892
893 /* Copy MAC header from skb into command buffer */
894 memcpy(tx_cmd->hdr, hdr, hdr_len);
895
896 /*
897 * Use the first empty entry in this queue's command buffer array
898 * to contain the Tx command and MAC header concatenated together
899 * (payload data will be in another buffer).
900 * Size of this varies, due to varying MAC header length.
901 * If end is not dword aligned, we'll have 2 extra bytes at the end
902 * of the MAC header (device reads on dword boundaries).
903 * We'll tell device about this padding later.
904 */
905 len = sizeof(struct iwl_tx_cmd) +
906 sizeof(struct iwl_cmd_header) + hdr_len;
907
908 len_org = len;
909 len = (len + 3) & ~3;
910
911 if (len_org != len)
912 len_org = 1;
913 else
914 len_org = 0;
915
916 /* Physical address of this Tx command's header (not MAC header!),
917 * within command buffer array. */
da99c4b6
GG		 918 txcmd_phys = pci_map_single(priv->pci_dev, out_cmd,
919 sizeof(struct iwl_cmd), PCI_DMA_TODEVICE);
920 txcmd_phys += offsetof(struct iwl_cmd, hdr);
fd4abac5
TW		 921
922 /* Add buffer containing Tx command and MAC(!) header to TFD's
923 * first entry */
924 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
925
d0f09804 926 if (info->control.hw_key)
e039fa4a 927 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
fd4abac5
TW		 928
929 /* Set up TFD's 2nd entry to point directly to remainder of skb,
930 * if any (802.11 null frames have no payload). */
931 len = skb->len - hdr_len;
932 if (len) {
933 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
934 len, PCI_DMA_TODEVICE);
935 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
936 }
937
938 /* Tell NIC about any 2-byte padding after MAC header */
939 if (len_org)
940 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
941
942 /* Total # bytes to be transmitted */
943 len = (u16)skb->len;
944 tx_cmd->len = cpu_to_le16(len);
945 /* TODO need this for burst mode later on */
e039fa4a 946 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, unicast, sta_id);
fd4abac5
TW		 947
948 /* set is_hcca to 0; it probably will never be implemented */
e039fa4a 949 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
fd4abac5 950
fd7c8a40 951 iwl_update_tx_stats(priv, le16_to_cpu(fc), len);
fd4abac5
TW		 952
953 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
954 offsetof(struct iwl_tx_cmd, scratch);
955 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
956 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys);
957
8b7b1e05 958 if (!ieee80211_has_morefrags(hdr->frame_control)) {
fd4abac5
TW		 959 txq->need_update = 1;
960 if (qc)
961 priv->stations[sta_id].tid[tid].seq_number = seq_number;
962 } else {
963 wait_write_ptr = 1;
964 txq->need_update = 0;
965 }
966
967 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
968
969 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
970
971 /* Set up entry for this TFD in Tx byte-count array */
972 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len);
973
974 /* Tell device the write index *just past* this latest filled TFD */
975 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
976 ret = iwl_txq_update_write_ptr(priv, txq);
977 spin_unlock_irqrestore(&priv->lock, flags);
978
979 if (ret)
980 return ret;
981
143b09ef 982 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
fd4abac5
TW		 983 if (wait_write_ptr) {
984 spin_lock_irqsave(&priv->lock, flags);
985 txq->need_update = 1;
986 iwl_txq_update_write_ptr(priv, txq);
987 spin_unlock_irqrestore(&priv->lock, flags);
143b09ef 988 } else {
f3674227 989 ieee80211_stop_queue(priv->hw, swq_id);
fd4abac5 990 }
fd4abac5
TW		 991 }
992
993 return 0;
994
995drop_unlock:
996 spin_unlock_irqrestore(&priv->lock, flags);
997drop:
998 return -1;
999}
1000EXPORT_SYMBOL(iwl_tx_skb);
1001
1002/*************** HOST COMMAND QUEUE FUNCTIONS *****/
1003
1004/**
1005 * iwl_enqueue_hcmd - enqueue a uCode command
1006 * @priv: device private data point
1007 * @cmd: a point to the ucode command structure
1008 *
1009 * The function returns < 0 values to indicate the operation is
1010 * failed. On success, it turns the index (> 0) of command in the
1011 * command queue.
1012 */
1013int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1014{
1015 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
1016 struct iwl_queue *q = &txq->q;
1017 struct iwl_tfd_frame *tfd;
fd4abac5 1018 struct iwl_cmd *out_cmd;
fd4abac5 1019 dma_addr_t phys_addr;
fd4abac5 1020 unsigned long flags;
f3674227
TW		 1021 int len, ret;
1022 u32 idx;
1023 u16 fix_size;
fd4abac5
TW		 1024
1025 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
1026 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
1027
1028 /* If any of the command structures end up being larger than
1029 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1030 * we will need to increase the size of the TFD entries */
1031 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
1032 !(cmd->meta.flags & CMD_SIZE_HUGE));
1033
1034 if (iwl_is_rfkill(priv)) {
1035 IWL_DEBUG_INFO("Not sending command - RF KILL");
1036 return -EIO;
1037 }
1038
1039 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
1040 IWL_ERROR("No space for Tx\n");
1041 return -ENOSPC;
1042 }
1043
1044 spin_lock_irqsave(&priv->hcmd_lock, flags);
1045
1046 tfd = &txq->bd[q->write_ptr];
1047 memset(tfd, 0, sizeof(*tfd));
1048
fd4abac5
TW		 1049
1050 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
da99c4b6 1051 out_cmd = txq->cmd[idx];
fd4abac5
TW		 1052
1053 out_cmd->hdr.cmd = cmd->id;
1054 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
1055 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1056
1057 /* At this point, the out_cmd now has all of the incoming cmd
1058 * information */
1059
1060 out_cmd->hdr.flags = 0;
1061 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1062 INDEX_TO_SEQ(q->write_ptr));
1063 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
9734cb23 1064 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
da99c4b6
GG		 1065 len = (idx == TFD_CMD_SLOTS) ?
1066 IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
1067 phys_addr = pci_map_single(priv->pci_dev, out_cmd, len,
1068 PCI_DMA_TODEVICE);
1069 phys_addr += offsetof(struct iwl_cmd, hdr);
fd4abac5
TW		 1070 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
1071
ded2ae7c
EK		 1072#ifdef CONFIG_IWLWIFI_DEBUG
1073 switch (out_cmd->hdr.cmd) {
1074 case REPLY_TX_LINK_QUALITY_CMD:
1075 case SENSITIVITY_CMD:
1076 IWL_DEBUG_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
1077 "%d bytes at %d[%d]:%d\n",
1078 get_cmd_string(out_cmd->hdr.cmd),
1079 out_cmd->hdr.cmd,
1080 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1081 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1082 break;
1083 default:
1084 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
1085 "%d bytes at %d[%d]:%d\n",
1086 get_cmd_string(out_cmd->hdr.cmd),
1087 out_cmd->hdr.cmd,
1088 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1089 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1090 }
1091#endif
fd4abac5
TW		 1092 txq->need_update = 1;
1093
1094 /* Set up entry in queue's byte count circular buffer */
1095 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1096
1097 /* Increment and update queue's write index */
1098 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1099 ret = iwl_txq_update_write_ptr(priv, txq);
1100
1101 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1102 return ret ? ret : idx;
1103}
1104
17b88929
TW		 1105int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1106{
1107 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1108 struct iwl_queue *q = &txq->q;
1109 struct iwl_tx_info *tx_info;
1110 int nfreed = 0;
1111
1112 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1113 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1114 "is out of range [0-%d] %d %d.\n", txq_id,
1115 index, q->n_bd, q->write_ptr, q->read_ptr);
1116 return 0;
1117 }
1118
1119 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
1120 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1121
1122 tx_info = &txq->txb[txq->q.read_ptr];
1123 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1124 tx_info->skb[0] = NULL;
17b88929 1125
972cf447
TW		 1126 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1127 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1128
1129 iwl_hw_txq_free_tfd(priv, txq);
17b88929
TW		 1130 nfreed++;
1131 }
1132 return nfreed;
1133}
1134EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1135
1136
1137/**
1138 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1139 *
1140 * When FW advances 'R' index, all entries between old and new 'R' index
1141 * need to be reclaimed. As result, some free space forms. If there is
1142 * enough free space (> low mark), wake the stack that feeds us.
1143 */
1144static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1145{
1146 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1147 struct iwl_queue *q = &txq->q;
da99c4b6
GG		 1148 struct iwl_tfd_frame *bd = &txq->bd[index];
1149 dma_addr_t dma_addr;
1150 int is_odd, buf_len;
17b88929
TW		 1151 int nfreed = 0;
1152
1153 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1154 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1155 "is out of range [0-%d] %d %d.\n", txq_id,
1156 index, q->n_bd, q->write_ptr, q->read_ptr);
1157 return;
1158 }
1159
1160 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
1161 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1162
1163 if (nfreed > 1) {
1164 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
1165 q->write_ptr, q->read_ptr);
1166 queue_work(priv->workqueue, &priv->restart);
1167 }
da99c4b6
GG		 1168 is_odd = (index/2) & 0x1;
1169 if (is_odd) {
1170 dma_addr = IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1171 (IWL_GET_BITS(bd->pa[index],
1172 tb2_addr_hi20) << 16);
1173 buf_len = IWL_GET_BITS(bd->pa[index], tb2_len);
1174 } else {
1175 dma_addr = le32_to_cpu(bd->pa[index].tb1_addr);
1176 buf_len = IWL_GET_BITS(bd->pa[index], tb1_len);
1177 }
1178
1179 pci_unmap_single(priv->pci_dev, dma_addr, buf_len,
1180 PCI_DMA_TODEVICE);
17b88929
TW		 1181 nfreed++;
1182 }
1183}
1184
1185/**
1186 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1187 * @rxb: Rx buffer to reclaim
1188 *
1189 * If an Rx buffer has an async callback associated with it the callback
1190 * will be executed. The attached skb (if present) will only be freed
1191 * if the callback returns 1
1192 */
1193void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1194{
1195 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1196 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1197 int txq_id = SEQ_TO_QUEUE(sequence);
1198 int index = SEQ_TO_INDEX(sequence);
17b88929 1199 int cmd_index;
9734cb23 1200 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
17b88929
TW		 1201 struct iwl_cmd *cmd;
1202
1203 /* If a Tx command is being handled and it isn't in the actual
1204 * command queue then there a command routing bug has been introduced
1205 * in the queue management code. */
1206 if (txq_id != IWL_CMD_QUEUE_NUM)
1207 IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
1208 txq_id, pkt->hdr.cmd);
1209 BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
1210
1211 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
da99c4b6 1212 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
17b88929
TW		 1213
1214 /* Input error checking is done when commands are added to queue. */
1215 if (cmd->meta.flags & CMD_WANT_SKB) {
1216 cmd->meta.source->u.skb = rxb->skb;
1217 rxb->skb = NULL;
1218 } else if (cmd->meta.u.callback &&
1219 !cmd->meta.u.callback(priv, cmd, rxb->skb))
1220 rxb->skb = NULL;
1221
1222 iwl_hcmd_queue_reclaim(priv, txq_id, index);
1223
1224 if (!(cmd->meta.flags & CMD_ASYNC)) {
1225 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1226 wake_up_interruptible(&priv->wait_command_queue);
1227 }
1228}
1229EXPORT_SYMBOL(iwl_tx_cmd_complete);
1230
30e553e3
TW		 1231/*
1232 * Find first available (lowest unused) Tx Queue, mark it "active".
1233 * Called only when finding queue for aggregation.
1234 * Should never return anything < 7, because they should already
1235 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1236 */
1237static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1238{
1239 int txq_id;
1240
1241 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1242 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1243 return txq_id;
1244 return -1;
1245}
1246
1247int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1248{
1249 int sta_id;
1250 int tx_fifo;
1251 int txq_id;
1252 int ret;
1253 unsigned long flags;
1254 struct iwl_tid_data *tid_data;
1255 DECLARE_MAC_BUF(mac);
1256
1257 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1258 tx_fifo = default_tid_to_tx_fifo[tid];
1259 else
1260 return -EINVAL;
1261
1262 IWL_WARNING("%s on ra = %s tid = %d\n",
1263 __func__, print_mac(mac, ra), tid);
1264
1265 sta_id = iwl_find_station(priv, ra);
1266 if (sta_id == IWL_INVALID_STATION)
1267 return -ENXIO;
1268
1269 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1270 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
1271 return -ENXIO;
1272 }
1273
1274 txq_id = iwl_txq_ctx_activate_free(priv);
1275 if (txq_id == -1)
1276 return -ENXIO;
1277
1278 spin_lock_irqsave(&priv->sta_lock, flags);
1279 tid_data = &priv->stations[sta_id].tid[tid];
1280 *ssn = SEQ_TO_SN(tid_data->seq_number);
1281 tid_data->agg.txq_id = txq_id;
1282 spin_unlock_irqrestore(&priv->sta_lock, flags);
1283
1284 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1285 sta_id, tid, *ssn);
1286 if (ret)
1287 return ret;
1288
1289 if (tid_data->tfds_in_queue == 0) {
1290 printk(KERN_ERR "HW queue is empty\n");
1291 tid_data->agg.state = IWL_AGG_ON;
1292 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1293 } else {
1294 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
1295 tid_data->tfds_in_queue);
1296 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1297 }
1298 return ret;
1299}
1300EXPORT_SYMBOL(iwl_tx_agg_start);
1301
1302int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1303{
1304 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1305 struct iwl_tid_data *tid_data;
1306 int ret, write_ptr, read_ptr;
1307 unsigned long flags;
1308 DECLARE_MAC_BUF(mac);
1309
1310 if (!ra) {
1311 IWL_ERROR("ra = NULL\n");
1312 return -EINVAL;
1313 }
1314
1315 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1316 tx_fifo_id = default_tid_to_tx_fifo[tid];
1317 else
1318 return -EINVAL;
1319
1320 sta_id = iwl_find_station(priv, ra);
1321
1322 if (sta_id == IWL_INVALID_STATION)
1323 return -ENXIO;
1324
1325 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1326 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
1327
1328 tid_data = &priv->stations[sta_id].tid[tid];
1329 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1330 txq_id = tid_data->agg.txq_id;
1331 write_ptr = priv->txq[txq_id].q.write_ptr;
1332 read_ptr = priv->txq[txq_id].q.read_ptr;
1333
1334 /* The queue is not empty */
1335 if (write_ptr != read_ptr) {
1336 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
1337 priv->stations[sta_id].tid[tid].agg.state =
1338 IWL_EMPTYING_HW_QUEUE_DELBA;
1339 return 0;
1340 }
1341
1342 IWL_DEBUG_HT("HW queue is empty\n");
1343 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1344
1345 spin_lock_irqsave(&priv->lock, flags);
1346 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1347 tx_fifo_id);
1348 spin_unlock_irqrestore(&priv->lock, flags);
1349
1350 if (ret)
1351 return ret;
1352
1353 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1354
1355 return 0;
1356}
1357EXPORT_SYMBOL(iwl_tx_agg_stop);
1358
1359int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1360{
1361 struct iwl_queue *q = &priv->txq[txq_id].q;
1362 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1363 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1364
1365 switch (priv->stations[sta_id].tid[tid].agg.state) {
1366 case IWL_EMPTYING_HW_QUEUE_DELBA:
1367 /* We are reclaiming the last packet of the */
1368 /* aggregated HW queue */
1369 if (txq_id == tid_data->agg.txq_id &&
1370 q->read_ptr == q->write_ptr) {
1371 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1372 int tx_fifo = default_tid_to_tx_fifo[tid];
1373 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
1374 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1375 ssn, tx_fifo);
1376 tid_data->agg.state = IWL_AGG_OFF;
1377 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1378 }
1379 break;
1380 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1381 /* We are reclaiming the last packet of the queue */
1382 if (tid_data->tfds_in_queue == 0) {
1383 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
1384 tid_data->agg.state = IWL_AGG_ON;
1385 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1386 }
1387 break;
1388 }
1389 return 0;
1390}
1391EXPORT_SYMBOL(iwl_txq_check_empty);
30e553e3 1392
653fa4a0
EG		 1393/**
1394 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1395 *
1396 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1397 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1398 */
1399static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1400 struct iwl_ht_agg *agg,
1401 struct iwl_compressed_ba_resp *ba_resp)
1402
1403{
1404 int i, sh, ack;
1405 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1406 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1407 u64 bitmap;
1408 int successes = 0;
1409 struct ieee80211_tx_info *info;
1410
1411 if (unlikely(!agg->wait_for_ba)) {
1412 IWL_ERROR("Received BA when not expected\n");
1413 return -EINVAL;
1414 }
1415
1416 /* Mark that the expected block-ack response arrived */
1417 agg->wait_for_ba = 0;
1418 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1419
1420 /* Calculate shift to align block-ack bits with our Tx window bits */
1421 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
1422 if (sh < 0) /* tbw something is wrong with indices */
1423 sh += 0x100;
1424
1425 /* don't use 64-bit values for now */
1426 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1427
1428 if (agg->frame_count > (64 - sh)) {
1429 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
1430 return -1;
1431 }
1432
1433 /* check for success or failure according to the
1434 * transmitted bitmap and block-ack bitmap */
1435 bitmap &= agg->bitmap;
1436
1437 /* For each frame attempted in aggregation,
1438 * update driver's record of tx frame's status. */
1439 for (i = 0; i < agg->frame_count ; i++) {
4aa41f12 1440 ack = bitmap & (1ULL << i);
653fa4a0
EG		 1441 successes += !!ack;
1442 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
1443 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
1444 agg->start_idx + i);
1445 }
1446
1447 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1448 memset(&info->status, 0, sizeof(info->status));
1449 info->flags = IEEE80211_TX_STAT_ACK;
1450 info->flags |= IEEE80211_TX_STAT_AMPDU;
1451 info->status.ampdu_ack_map = successes;
1452 info->status.ampdu_ack_len = agg->frame_count;
1453 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1454
1455 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
1456
1457 return 0;
1458}
1459
1460/**
1461 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1462 *
1463 * Handles block-acknowledge notification from device, which reports success
1464 * of frames sent via aggregation.
1465 */
1466void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1467 struct iwl_rx_mem_buffer *rxb)
1468{
1469 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1470 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1471 int index;
1472 struct iwl_tx_queue *txq = NULL;
1473 struct iwl_ht_agg *agg;
1474 DECLARE_MAC_BUF(mac);
1475
1476 /* "flow" corresponds to Tx queue */
1477 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1478
1479 /* "ssn" is start of block-ack Tx window, corresponds to index
1480 * (in Tx queue's circular buffer) of first TFD/frame in window */
1481 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1482
1483 if (scd_flow >= priv->hw_params.max_txq_num) {
6f147926 1484 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues\n");
653fa4a0
EG		 1485 return;
1486 }
1487
1488 txq = &priv->txq[scd_flow];
1489 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
1490
1491 /* Find index just before block-ack window */
1492 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1493
1494 /* TODO: Need to get this copy more safely - now good for debug */
1495
1496 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
1497 "sta_id = %d\n",
1498 agg->wait_for_ba,
1499 print_mac(mac, (u8 *) &ba_resp->sta_addr_lo32),
1500 ba_resp->sta_id);
1501 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1502 "%d, scd_ssn = %d\n",
1503 ba_resp->tid,
1504 ba_resp->seq_ctl,
1505 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1506 ba_resp->scd_flow,
1507 ba_resp->scd_ssn);
1508 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
1509 agg->start_idx,
1510 (unsigned long long)agg->bitmap);
1511
1512 /* Update driver's record of ACK vs. not for each frame in window */
1513 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1514
1515 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1516 * block-ack window (we assume that they've been successfully
1517 * transmitted ... if not, it's too late anyway). */
1518 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1519 /* calculate mac80211 ampdu sw queue to wake */
1520 int ampdu_q =
1521 scd_flow - priv->hw_params.first_ampdu_q + priv->hw->queues;
1522 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1523 priv->stations[ba_resp->sta_id].
1524 tid[ba_resp->tid].tfds_in_queue -= freed;
1525 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1526 priv->mac80211_registered &&
1527 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
1528 ieee80211_wake_queue(priv->hw, ampdu_q);
1529
1530 iwl_txq_check_empty(priv, ba_resp->sta_id,
1531 ba_resp->tid, scd_flow);
1532 }
1533}
1534EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1535
994d31f7 1536#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6
TW		 1537#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1538
1539const char *iwl_get_tx_fail_reason(u32 status)
1540{
1541 switch (status & TX_STATUS_MSK) {
1542 case TX_STATUS_SUCCESS:
1543 return "SUCCESS";
1544 TX_STATUS_ENTRY(SHORT_LIMIT);
1545 TX_STATUS_ENTRY(LONG_LIMIT);
1546 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1547 TX_STATUS_ENTRY(MGMNT_ABORT);
1548 TX_STATUS_ENTRY(NEXT_FRAG);
1549 TX_STATUS_ENTRY(LIFE_EXPIRE);
1550 TX_STATUS_ENTRY(DEST_PS);
1551 TX_STATUS_ENTRY(ABORTED);
1552 TX_STATUS_ENTRY(BT_RETRY);
1553 TX_STATUS_ENTRY(STA_INVALID);
1554 TX_STATUS_ENTRY(FRAG_DROPPED);
1555 TX_STATUS_ENTRY(TID_DISABLE);
1556 TX_STATUS_ENTRY(FRAME_FLUSHED);
1557 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1558 TX_STATUS_ENTRY(TX_LOCKED);
1559 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1560 }
1561
1562 return "UNKNOWN";
1563}
1564EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1565#endif /* CONFIG_IWLWIFI_DEBUG */
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