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iwlwifi: manage QoS by mac stack
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
b481de9c
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 * Please use iwl-4965-hw.h for hardware-related definitions.
30 */
31
be1f3ab6
EG
32#ifndef __iwl_dev_h__
33#define __iwl_dev_h__
b481de9c 34
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
37#include <net/ieee80211_radiotap.h>
38
6bc913bd 39#include "iwl-eeprom.h"
6f83eaa1 40#include "iwl-csr.h"
5d08cd1d 41#include "iwl-prph.h"
dbb6654c 42#include "iwl-fh.h"
0a6857e7 43#include "iwl-debug.h"
dbb6654c
WT
44#include "iwl-4965-hw.h"
45#include "iwl-3945-hw.h"
ab53d8af 46#include "iwl-led.h"
5da4b55f 47#include "iwl-power.h"
e227ceac 48#include "iwl-agn-rs.h"
5d08cd1d 49
fed9017e
RR
50/* configuration for the iwl4965 */
51extern struct iwl_cfg iwl4965_agn_cfg;
5a6a256e
TW
52extern struct iwl_cfg iwl5300_agn_cfg;
53extern struct iwl_cfg iwl5100_agn_cfg;
54extern struct iwl_cfg iwl5350_agn_cfg;
ac592574 55extern struct iwl_cfg iwl5100_bgn_cfg;
47408639 56extern struct iwl_cfg iwl5100_abg_cfg;
7100e924 57extern struct iwl_cfg iwl5150_agn_cfg;
ac592574 58extern struct iwl_cfg iwl5150_abg_cfg;
65b7998a 59extern struct iwl_cfg iwl6000i_2agn_cfg;
0b5af201 60extern struct iwl_cfg iwl6000i_g2_2agn_cfg;
5953a62e
WYG
61extern struct iwl_cfg iwl6000i_2abg_cfg;
62extern struct iwl_cfg iwl6000i_2bg_cfg;
e1228374
JS
63extern struct iwl_cfg iwl6000_3agn_cfg;
64extern struct iwl_cfg iwl6050_2agn_cfg;
5953a62e 65extern struct iwl_cfg iwl6050_2abg_cfg;
77dcb6a9 66extern struct iwl_cfg iwl1000_bgn_cfg;
4bd0914f 67extern struct iwl_cfg iwl1000_bg_cfg;
fed9017e 68
672639de
WYG
69struct iwl_tx_queue;
70
099b40b7 71/* CT-KILL constants */
672639de
WYG
72#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
73#define CT_KILL_THRESHOLD 114 /* in Celsius */
74#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 75
5d08cd1d
CH
76/* Default noise level to report when noise measurement is not available.
77 * This may be because we're:
78 * 1) Not associated (4965, no beacon statistics being sent to driver)
79 * 2) Scanning (noise measurement does not apply to associated channel)
80 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
81 * Use default noise value of -127 ... this is below the range of measurable
82 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
83 * Also, -127 works better than 0 when averaging frames with/without
84 * noise info (e.g. averaging might be done in app); measured dBm values are
85 * always negative ... using a negative value as the default keeps all
86 * averages within an s8's (used in some apps) range of negative values. */
87#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
88
5d08cd1d
CH
89/*
90 * RTS threshold here is total size [2347] minus 4 FCS bytes
91 * Per spec:
92 * a value of 0 means RTS on all data/management packets
93 * a value > max MSDU size means no RTS
94 * else RTS for data/management frames where MPDU is larger
95 * than RTS value.
96 */
97#define DEFAULT_RTS_THRESHOLD 2347U
98#define MIN_RTS_THRESHOLD 0U
99#define MAX_RTS_THRESHOLD 2347U
100#define MAX_MSDU_SIZE 2304U
101#define MAX_MPDU_SIZE 2346U
102#define DEFAULT_BEACON_INTERVAL 100U
103#define DEFAULT_SHORT_RETRY_LIMIT 7U
104#define DEFAULT_LONG_RETRY_LIMIT 4U
105
a55360e4 106struct iwl_rx_mem_buffer {
2f301227
ZY
107 dma_addr_t page_dma;
108 struct page *page;
5d08cd1d
CH
109 struct list_head list;
110};
111
2f301227
ZY
112#define rxb_addr(r) page_address(r->page)
113
c2acea8e
JB
114/* defined below */
115struct iwl_device_cmd;
116
117struct iwl_cmd_meta {
118 /* only for SYNC commands, iff the reply skb is wanted */
119 struct iwl_host_cmd *source;
120 /*
121 * only for ASYNC commands
122 * (which is somewhat stupid -- look at iwl-sta.c for instance
123 * which duplicates a bunch of code because the callback isn't
124 * invoked for SYNC commands, if it were and its result passed
125 * through it would be simpler...)
126 */
5696aea6
JB
127 void (*callback)(struct iwl_priv *priv,
128 struct iwl_device_cmd *cmd,
2f301227 129 struct iwl_rx_packet *pkt);
c2acea8e
JB
130
131 /* The CMD_SIZE_HUGE flag bit indicates that the command
132 * structure is stored at the end of the shared queue memory. */
133 u32 flags;
134
135 DECLARE_PCI_UNMAP_ADDR(mapping)
136 DECLARE_PCI_UNMAP_LEN(len)
137};
138
5d08cd1d
CH
139/*
140 * Generic queue structure
141 *
142 * Contains common data for Rx and Tx queues
143 */
443cfd45 144struct iwl_queue {
5d08cd1d
CH
145 int n_bd; /* number of BDs in this queue */
146 int write_ptr; /* 1-st empty entry (index) host_w*/
147 int read_ptr; /* last used entry (index) host_r*/
b74e31a9
WYG
148 /* use for monitoring and recovering the stuck queue */
149 int last_read_ptr; /* storing the last read_ptr */
150 /* number of time read_ptr and last_read_ptr are the same */
151 u8 repeat_same_read_ptr;
5d08cd1d
CH
152 dma_addr_t dma_addr; /* physical addr for BD's */
153 int n_window; /* safe queue window */
154 u32 id;
155 int low_mark; /* low watermark, resume queue if free
156 * space more than this */
157 int high_mark; /* high watermark, stop queue if free
158 * space less than this */
159} __attribute__ ((packed));
160
bc47279f 161/* One for each TFD */
8567c63e 162struct iwl_tx_info {
499b1883 163 struct sk_buff *skb[IWL_NUM_OF_TBS - 1];
5d08cd1d
CH
164};
165
166/**
16466903 167 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
168 * @q: generic Rx/Tx queue descriptor
169 * @bd: base of circular buffer of TFDs
c2acea8e
JB
170 * @cmd: array of command/TX buffer pointers
171 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
172 * @dma_addr_cmd: physical address of cmd/tx buffer array
173 * @txb: array of per-TFD driver data
174 * @need_update: indicates need to update read/write index
175 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 176 *
bc47279f
BC
177 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
178 * descriptors) and required locking structures.
5d08cd1d 179 */
188cf6c7
SO
180#define TFD_TX_CMD_SLOTS 256
181#define TFD_CMD_SLOTS 32
182
16466903 183struct iwl_tx_queue {
443cfd45 184 struct iwl_queue q;
59606ffa 185 void *tfds;
c2acea8e
JB
186 struct iwl_device_cmd **cmd;
187 struct iwl_cmd_meta *meta;
8567c63e 188 struct iwl_tx_info *txb;
3fd07a1e
TW
189 u8 need_update;
190 u8 sched_retry;
191 u8 active;
192 u8 swq_id;
5d08cd1d
CH
193};
194
195#define IWL_NUM_SCAN_RATES (2)
196
bb8c093b 197struct iwl4965_channel_tgd_info {
5d08cd1d
CH
198 u8 type;
199 s8 max_power;
200};
201
bb8c093b 202struct iwl4965_channel_tgh_info {
5d08cd1d
CH
203 s64 last_radar_time;
204};
205
d20b3c65
SO
206#define IWL4965_MAX_RATE (33)
207
85d41495
KA
208struct iwl3945_clip_group {
209 /* maximum power level to prevent clipping for each rate, derived by
210 * us from this band's saturation power in EEPROM */
211 const s8 clip_powers[IWL_MAX_RATES];
212};
213
d20b3c65
SO
214/* current Tx power values to use, one for each rate for each channel.
215 * requested power is limited by:
216 * -- regulatory EEPROM limits for this channel
217 * -- hardware capabilities (clip-powers)
218 * -- spectrum management
219 * -- user preference (e.g. iwconfig)
220 * when requested power is set, base power index must also be set. */
221struct iwl3945_channel_power_info {
222 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
223 s8 power_table_index; /* actual (compenst'd) index into gain table */
224 s8 base_power_index; /* gain index for power at factory temp. */
225 s8 requested_power; /* power (dBm) requested for this chnl/rate */
226};
227
228/* current scan Tx power values to use, one for each scan rate for each
229 * channel. */
230struct iwl3945_scan_power_info {
231 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
232 s8 power_table_index; /* actual (compenst'd) index into gain table */
233 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
234};
235
5d08cd1d
CH
236/*
237 * One for each channel, holds all channel setup data
238 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
239 * with one another!
240 */
bf85ea4f 241struct iwl_channel_info {
bb8c093b
CH
242 struct iwl4965_channel_tgd_info tgd;
243 struct iwl4965_channel_tgh_info tgh;
073d3f5f 244 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
245 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
246 * HT40 channel */
5d08cd1d
CH
247
248 u8 channel; /* channel number */
249 u8 flags; /* flags copied from EEPROM */
250 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 251 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
252 s8 min_power; /* always 0 */
253 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
254
255 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
256 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 257 enum ieee80211_band band;
5d08cd1d 258
7aafef1c
WYG
259 /* HT40 channel info */
260 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
261 u8 ht40_flags; /* flags copied from EEPROM */
262 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
d20b3c65
SO
263
264 /* Radio/DSP gain settings for each "normal" data Tx rate.
265 * These include, in addition to RF and DSP gain, a few fields for
266 * remembering/modifying gain settings (indexes). */
267 struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE];
268
269 /* Radio/DSP gain settings for each scan rate, for directed scans. */
270 struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
5d08cd1d
CH
271};
272
edc1a3a0
JB
273#define IWL_TX_FIFO_BK 0
274#define IWL_TX_FIFO_BE 1
275#define IWL_TX_FIFO_VI 2
276#define IWL_TX_FIFO_VO 3
277#define IWL_TX_FIFO_UNUSED -1
5d08cd1d 278
01a7e084
RC
279/* Minimum number of queues. MAX_NUM is defined in hw specific files.
280 * Set the minimum to accommodate the 4 standard TX queues, 1 command
281 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
282#define IWL_MIN_NUM_QUEUES 10
5d08cd1d 283
bd35f150 284/*
1a716557
JB
285 * Queue #4 is the command queue for 3945/4965/5x00/1000/6x00,
286 * the driver maps it into the appropriate device FIFO for the
287 * uCode.
bd35f150
WYG
288 */
289#define IWL_CMD_QUEUE_NUM 4
290
5d08cd1d
CH
291/* Power management (not Tx power) structures */
292
6f4083aa
TW
293enum iwl_pwr_src {
294 IWL_PWR_SRC_VMAIN,
295 IWL_PWR_SRC_VAUX,
296};
297
5d08cd1d
CH
298#define IEEE80211_DATA_LEN 2304
299#define IEEE80211_4ADDR_LEN 30
300#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
301#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
302
fcab423d 303struct iwl_frame {
5d08cd1d
CH
304 union {
305 struct ieee80211_hdr frame;
4bf64efd 306 struct iwl_tx_beacon_cmd beacon;
5d08cd1d
CH
307 u8 raw[IEEE80211_FRAME_LEN];
308 u8 cmd[360];
309 } u;
310 struct list_head list;
311};
312
5d08cd1d
CH
313#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
314#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
315#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
316
317enum {
c587de0b
TW
318 CMD_SYNC = 0,
319 CMD_SIZE_NORMAL = 0,
320 CMD_NO_SKB = 0,
5d08cd1d 321 CMD_SIZE_HUGE = (1 << 0),
5d08cd1d 322 CMD_ASYNC = (1 << 1),
5d08cd1d
CH
323 CMD_WANT_SKB = (1 << 2),
324};
325
c8c24872 326#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 327
bc47279f 328/**
c2acea8e 329 * struct iwl_device_cmd
bc47279f
BC
330 *
331 * For allocation of the command and tx queues, this establishes the overall
332 * size of the largest command we send to uCode, except for a scan command
333 * (which is relatively huge; space is allocated separately).
334 */
c2acea8e 335struct iwl_device_cmd {
857485c0 336 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 337 union {
5d08cd1d
CH
338 u32 flags;
339 u8 val8;
340 u16 val16;
341 u32 val32;
83d527d9 342 struct iwl_tx_cmd tx;
c8c24872
WYG
343 struct iwl6000_channel_switch_cmd chswitch;
344 u8 payload[DEF_CMD_PAYLOAD_SIZE];
5d08cd1d
CH
345 } __attribute__ ((packed)) cmd;
346} __attribute__ ((packed));
347
c2acea8e
JB
348#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
349
3257e5d4 350
857485c0 351struct iwl_host_cmd {
5d08cd1d 352 const void *data;
2f301227 353 unsigned long reply_page;
5696aea6
JB
354 void (*callback)(struct iwl_priv *priv,
355 struct iwl_device_cmd *cmd,
2f301227 356 struct iwl_rx_packet *pkt);
c2acea8e
JB
357 u32 flags;
358 u16 len;
359 u8 id;
5d08cd1d
CH
360};
361
5d08cd1d
CH
362#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
363#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
364#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
365
366/**
a55360e4 367 * struct iwl_rx_queue - Rx queue
df833b1d
RC
368 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
369 * @dma_addr: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
370 * @read: Shared index to newest available Rx buffer
371 * @write: Shared index to oldest written Rx packet
372 * @free_count: Number of pre-allocated buffers in rx_free
373 * @rx_free: list of free SKBs for use
374 * @rx_used: List of Rx buffers with no SKB
375 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
376 * @rb_stts: driver's pointer to receive buffer status
377 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 378 *
a55360e4 379 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 380 */
a55360e4 381struct iwl_rx_queue {
5d08cd1d
CH
382 __le32 *bd;
383 dma_addr_t dma_addr;
a55360e4
TW
384 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
385 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
386 u32 read;
387 u32 write;
388 u32 free_count;
4752c93c 389 u32 write_actual;
5d08cd1d
CH
390 struct list_head rx_free;
391 struct list_head rx_used;
392 int need_update;
8d86422a
WT
393 struct iwl_rb_status *rb_stts;
394 dma_addr_t rb_stts_dma;
5d08cd1d
CH
395 spinlock_t lock;
396};
397
398#define IWL_SUPPORTED_RATES_IE_LEN 8
399
5d08cd1d
CH
400#define MAX_TID_COUNT 9
401
402#define IWL_INVALID_RATE 0xFF
403#define IWL_INVALID_VALUE -1
404
bc47279f 405/**
6def9761 406 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
407 * @txq_id: Tx queue used for Tx attempt
408 * @frame_count: # frames attempted by Tx command
409 * @wait_for_ba: Expect block-ack before next Tx reply
410 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
411 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
412 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
413 * @rate_n_flags: Rate at which Tx was attempted
414 *
415 * If REPLY_TX indicates that aggregation was attempted, driver must wait
416 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
417 * until block ack arrives.
418 */
6def9761 419struct iwl_ht_agg {
5d08cd1d
CH
420 u16 txq_id;
421 u16 frame_count;
422 u16 wait_for_ba;
423 u16 start_idx;
fe01b477 424 u64 bitmap;
5d08cd1d 425 u32 rate_n_flags;
fe01b477
RR
426#define IWL_AGG_OFF 0
427#define IWL_AGG_ON 1
428#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
429#define IWL_EMPTYING_HW_QUEUE_DELBA 3
430 u8 state;
5d08cd1d 431};
fe01b477 432
5d08cd1d 433
6def9761 434struct iwl_tid_data {
5d08cd1d 435 u16 seq_number;
fe01b477 436 u16 tfds_in_queue;
6def9761 437 struct iwl_ht_agg agg;
5d08cd1d
CH
438};
439
6def9761 440struct iwl_hw_key {
5d08cd1d
CH
441 enum ieee80211_key_alg alg;
442 int keylen;
0211ddda 443 u8 keyidx;
5d08cd1d
CH
444 u8 key[32];
445};
446
a78fe754 447union iwl_ht_rate_supp {
5d08cd1d
CH
448 u16 rates;
449 struct {
450 u8 siso_rate;
451 u8 mimo_rate;
452 };
453};
454
5d08cd1d 455#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
bcc693a1
WYG
456
457/*
458 * Maximal MPDU density for TX aggregation
459 * 4 - 2us density
460 * 5 - 4us density
461 * 6 - 8us density
462 * 7 - 16us density
463 */
464#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
465#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
5d08cd1d 466
fad95bf5 467struct iwl_ht_config {
9e0cc6de 468 /* self configuration data */
c812ee24
JB
469 bool is_ht;
470 bool is_40mhz;
02bb1bea 471 bool single_chain_sufficient;
ba37a3d0 472 enum ieee80211_smps_mode smps; /* current smps mode */
9e0cc6de 473 /* BSS related data */
5d08cd1d 474 u8 extension_chan_offset;
9e0cc6de
RR
475 u8 ht_protection;
476 u8 non_GF_STA_present;
5d08cd1d 477};
5d08cd1d 478
5d08cd1d 479/* QoS structures */
1ff50bda 480struct iwl_qos_info {
5d08cd1d 481 int qos_active;
1ff50bda 482 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 483};
5d08cd1d 484
fe6b23dd
RC
485/*
486 * Structure should be accessed with sta_lock held. When station addition
487 * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only
488 * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock
489 * held.
490 */
6def9761 491struct iwl_station_entry {
133636de 492 struct iwl_addsta_cmd sta;
6def9761 493 struct iwl_tid_data tid[MAX_TID_COUNT];
5d08cd1d 494 u8 used;
6def9761 495 struct iwl_hw_key keyinfo;
fe6b23dd 496 struct iwl_link_quality_cmd *lq;
5d08cd1d
CH
497};
498
8d9698b3
RC
499/*
500 * iwl_station_priv: Driver's private station information
501 *
502 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
503 * in the structure for use by driver. This structure is places in that
504 * space.
8d9698b3
RC
505 */
506struct iwl_station_priv {
507 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
508 atomic_t pending_frames;
509 bool client;
510 bool asleep;
8d9698b3
RC
511};
512
5d08cd1d
CH
513/* one for each uCode image (inst/data, boot/init/runtime) */
514struct fw_desc {
515 void *v_addr; /* access by driver */
516 dma_addr_t p_addr; /* access by card's busmaster DMA */
517 u32 len; /* bytes */
518};
519
520/* uCode file layout */
cc0f555d
JS
521struct iwl_ucode_header {
522 __le32 ver; /* major/minor/API/serial */
523 union {
524 struct {
525 __le32 inst_size; /* bytes of runtime code */
526 __le32 data_size; /* bytes of runtime data */
527 __le32 init_size; /* bytes of init code */
528 __le32 init_data_size; /* bytes of init data */
529 __le32 boot_size; /* bytes of bootstrap code */
530 u8 data[0]; /* in same order as sizes */
531 } v1;
532 struct {
533 __le32 build; /* build number */
534 __le32 inst_size; /* bytes of runtime code */
535 __le32 data_size; /* bytes of runtime data */
536 __le32 init_size; /* bytes of init code */
537 __le32 init_data_size; /* bytes of init data */
538 __le32 boot_size; /* bytes of bootstrap code */
539 u8 data[0]; /* in same order as sizes */
540 } v2;
541 } u;
5d08cd1d 542};
cc0f555d 543#define UCODE_HEADER_SIZE(ver) ((ver) == 1 ? 24 : 28)
5d08cd1d 544
bb8c093b 545struct iwl4965_ibss_seq {
5d08cd1d
CH
546 u8 mac[ETH_ALEN];
547 u16 seq_num;
548 u16 frag_num;
549 unsigned long packet_time;
550 struct list_head list;
551};
552
f0832f13
EG
553struct iwl_sensitivity_ranges {
554 u16 min_nrg_cck;
555 u16 max_nrg_cck;
556
557 u16 nrg_th_cck;
558 u16 nrg_th_ofdm;
559
560 u16 auto_corr_min_ofdm;
561 u16 auto_corr_min_ofdm_mrc;
562 u16 auto_corr_min_ofdm_x1;
563 u16 auto_corr_min_ofdm_mrc_x1;
564
565 u16 auto_corr_max_ofdm;
566 u16 auto_corr_max_ofdm_mrc;
567 u16 auto_corr_max_ofdm_x1;
568 u16 auto_corr_max_ofdm_mrc_x1;
569
570 u16 auto_corr_max_cck;
571 u16 auto_corr_max_cck_mrc;
572 u16 auto_corr_min_cck;
573 u16 auto_corr_min_cck_mrc;
55036d66
WYG
574
575 u16 barker_corr_th_min;
576 u16 barker_corr_th_min_mrc;
577 u16 nrg_th_cca;
f0832f13
EG
578};
579
099b40b7 580
b5047f78
TW
581#define KELVIN_TO_CELSIUS(x) ((x)-273)
582#define CELSIUS_TO_KELVIN(x) ((x)+273)
583
584
bc47279f 585/**
5425e490 586 * struct iwl_hw_params
bc47279f 587 * @max_txq_num: Max # Tx queues supported
f3f911d1 588 * @dma_chnl_num: Number of Tx DMA/FIFO channels
4ddbb7d0 589 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 590 * @tfd_size: TFD size
099b40b7
RR
591 * @tx/rx_chains_num: Number of TX/RX chains
592 * @valid_tx/rx_ant: usable antennas
bc47279f 593 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 594 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 595 * @rx_page_order: Rx buffer page order
141c43a3 596 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f
BC
597 * @max_stations:
598 * @bcast_sta_id:
7aafef1c 599 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
600 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
601 * @sw_crypto: 0 for hw, 1 for sw
602 * @max_xxx_size: for ucode uses
603 * @ct_kill_threshold: temperature threshold
a96a27f9 604 * @calib_init_cfg: setup initial calibrations for the hw
f0832f13 605 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 606 */
5425e490 607struct iwl_hw_params {
f3f911d1
ZY
608 u8 max_txq_num;
609 u8 dma_chnl_num;
4ddbb7d0 610 u16 scd_bc_tbls_size;
a8e74e27 611 u32 tfd_size;
ec35cf2a
TW
612 u8 tx_chains_num;
613 u8 rx_chains_num;
614 u8 valid_tx_ant;
615 u8 valid_rx_ant;
5d08cd1d 616 u16 max_rxq_size;
ec35cf2a 617 u16 max_rxq_log;
2f301227 618 u32 rx_page_order;
141c43a3 619 u32 rx_wrt_ptr_reg;
5d08cd1d
CH
620 u8 max_stations;
621 u8 bcast_sta_id;
7aafef1c 622 u8 ht40_channel;
2c2f3b33 623 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
624 u32 max_inst_size;
625 u32 max_data_size;
626 u32 max_bsm_size;
627 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
628 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
629 /* for 1000, 6000 series and up */
be5d56ed 630 u32 calib_init_cfg;
f0832f13 631 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
632};
633
5d08cd1d 634
5d08cd1d
CH
635/******************************************************************************
636 *
a33c2f47
EG
637 * Functions implemented in core module which are forward declared here
638 * for use by iwl-[4-5].c
5d08cd1d 639 *
a33c2f47
EG
640 * NOTE: The implementation of these functions are not hardware specific
641 * which is why they are in the core module files.
5d08cd1d
CH
642 *
643 * Naming convention --
a33c2f47 644 * iwl_ <-- Is part of iwlwifi
5d08cd1d 645 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
bb8c093b
CH
646 * iwl4965_bg_ <-- Called from work queue context
647 * iwl4965_mac_ <-- mac80211 callback
5d08cd1d
CH
648 *
649 ****************************************************************************/
5b9f8cd3
EG
650extern void iwl_update_chain_flags(struct iwl_priv *priv);
651extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src);
a33c2f47 652extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 653extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 654extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 655extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
656static inline int iwl_queue_used(const struct iwl_queue *q, int i)
657{
c8106d76 658 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
659 (i >= q->read_ptr && i < q->write_ptr) :
660 !(i < q->read_ptr && i >= q->write_ptr);
661}
662
663
664static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge)
665{
c8c24872
WYG
666 /*
667 * This is for init calibration result and scan command which
668 * required buffer > TFD_MAX_PAYLOAD_SIZE,
669 * the big buffer at end of command array
670 */
fd4abac5
TW
671 if (is_huge)
672 return q->n_window; /* must be power of 2 */
673
674 /* Otherwise, use normal size buffers */
675 return index & (q->n_window - 1);
676}
677
678
4ddbb7d0
TW
679struct iwl_dma_ptr {
680 dma_addr_t dma;
681 void *addr;
b481de9c
ZY
682 size_t size;
683};
684
b481de9c
ZY
685#define IWL_OPERATION_MODE_AUTO 0
686#define IWL_OPERATION_MODE_HT_ONLY 1
687#define IWL_OPERATION_MODE_MIXED 2
688#define IWL_OPERATION_MODE_20MHZ 3
689
3195cdb7
TW
690#define IWL_TX_CRC_SIZE 4
691#define IWL_TX_DELIMITER_SIZE 4
b481de9c 692
b481de9c 693#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 694
b481de9c 695/* Sensitivity and chain noise calibration */
b481de9c 696#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a
WYG
697#define IWL4965_CAL_NUM_BEACONS 20
698#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
699#define MAXIMUM_ALLOWED_PATHLOSS 15
700
b481de9c
ZY
701#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
702
703#define MAX_FA_OFDM 50
704#define MIN_FA_OFDM 5
705#define MAX_FA_CCK 50
706#define MIN_FA_CCK 5
707
b481de9c
ZY
708#define AUTO_CORR_STEP_OFDM 1
709
b481de9c
ZY
710#define AUTO_CORR_STEP_CCK 3
711#define AUTO_CORR_MAX_TH_CCK 160
712
b481de9c
ZY
713#define NRG_DIFF 2
714#define NRG_STEP_CCK 2
715#define NRG_MARGIN 8
716#define MAX_NUMBER_CCK_NO_FA 100
717
718#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
719
720#define CHAIN_A 0
721#define CHAIN_B 1
722#define CHAIN_C 2
723#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
724#define ALL_BAND_FILTER 0xFF00
725#define IN_BAND_FILTER 0xFF
726#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
727
3195cdb7
TW
728#define NRG_NUM_PREV_STAT_L 20
729#define NUM_RX_CHAINS 3
730
bb8c093b 731enum iwl4965_false_alarm_state {
b481de9c
ZY
732 IWL_FA_TOO_MANY = 0,
733 IWL_FA_TOO_FEW = 1,
734 IWL_FA_GOOD_RANGE = 2,
735};
736
bb8c093b 737enum iwl4965_chain_noise_state {
b481de9c 738 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
739 IWL_CHAIN_NOISE_ACCUMULATE,
740 IWL_CHAIN_NOISE_CALIBRATED,
741 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
742};
743
bb8c093b 744enum iwl4965_calib_enabled_state {
b481de9c
ZY
745 IWL_CALIB_DISABLED = 0, /* must be 0 */
746 IWL_CALIB_ENABLED = 1,
747};
748
f69f42a6
TW
749
750/*
751 * enum iwl_calib
752 * defines the order in which results of initial calibrations
753 * should be sent to the runtime uCode
754 */
755enum iwl_calib {
756 IWL_CALIB_XTAL,
819500c5 757 IWL_CALIB_DC,
f69f42a6
TW
758 IWL_CALIB_LO,
759 IWL_CALIB_TX_IQ,
760 IWL_CALIB_TX_IQ_PERD,
201706ac 761 IWL_CALIB_BASE_BAND,
f69f42a6
TW
762 IWL_CALIB_MAX
763};
764
6e21f2c1
TW
765/* Opaque calibration results */
766struct iwl_calib_result {
767 void *buf;
768 size_t buf_len;
7c616cba
TW
769};
770
dbb983b7
RR
771enum ucode_type {
772 UCODE_NONE = 0,
773 UCODE_INIT,
774 UCODE_RT
775};
776
b481de9c 777/* Sensitivity calib data */
f0832f13 778struct iwl_sensitivity_data {
b481de9c
ZY
779 u32 auto_corr_ofdm;
780 u32 auto_corr_ofdm_mrc;
781 u32 auto_corr_ofdm_x1;
782 u32 auto_corr_ofdm_mrc_x1;
783 u32 auto_corr_cck;
784 u32 auto_corr_cck_mrc;
785
786 u32 last_bad_plcp_cnt_ofdm;
787 u32 last_fa_cnt_ofdm;
788 u32 last_bad_plcp_cnt_cck;
789 u32 last_fa_cnt_cck;
790
791 u32 nrg_curr_state;
792 u32 nrg_prev_state;
793 u32 nrg_value[10];
794 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
795 u32 nrg_silence_ref;
796 u32 nrg_energy_idx;
797 u32 nrg_silence_idx;
798 u32 nrg_th_cck;
799 s32 nrg_auto_corr_silence_diff;
800 u32 num_in_cck_no_fa;
801 u32 nrg_th_ofdm;
55036d66
WYG
802
803 u16 barker_corr_th_min;
804 u16 barker_corr_th_min_mrc;
805 u16 nrg_th_cca;
b481de9c
ZY
806};
807
808/* Chain noise (differential Rx gain) calib data */
f0832f13 809struct iwl_chain_noise_data {
04816448 810 u32 active_chains;
b481de9c
ZY
811 u32 chain_noise_a;
812 u32 chain_noise_b;
813 u32 chain_noise_c;
814 u32 chain_signal_a;
815 u32 chain_signal_b;
816 u32 chain_signal_c;
04816448 817 u16 beacon_count;
b481de9c
ZY
818 u8 disconn_array[NUM_RX_CHAINS];
819 u8 delta_gain_code[NUM_RX_CHAINS];
820 u8 radio_write;
04816448 821 u8 state;
b481de9c
ZY
822};
823
abceddb4
BC
824#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
825#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 826
20594eb0
WYG
827#define IWL_TRAFFIC_ENTRIES (256)
828#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 829
5d08cd1d
CH
830enum {
831 MEASUREMENT_READY = (1 << 0),
832 MEASUREMENT_ACTIVE = (1 << 1),
833};
834
0848e297
WYG
835enum iwl_nvm_type {
836 NVM_DEVICE_TYPE_EEPROM = 0,
837 NVM_DEVICE_TYPE_OTP,
838};
839
415e4993
WYG
840/*
841 * Two types of OTP memory access modes
842 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
843 * based on physical memory addressing
844 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
845 * based on logical memory addressing
846 */
847enum iwl_access_mode {
848 IWL_OTP_ACCESS_ABSOLUTE,
849 IWL_OTP_ACCESS_RELATIVE,
850};
65b7998a
WYG
851
852/**
853 * enum iwl_pa_type - Power Amplifier type
854 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
855 * @IWL_PA_INTERNAL: use Internal only
856 */
857enum iwl_pa_type {
858 IWL_PA_SYSTEM = 0,
740e7f51 859 IWL_PA_INTERNAL = 1,
65b7998a
WYG
860};
861
a83b9141
WYG
862/* interrupt statistics */
863struct isr_statistics {
864 u32 hw;
865 u32 sw;
866 u32 sw_err;
867 u32 sch;
868 u32 alive;
869 u32 rfkill;
870 u32 ctkill;
871 u32 wakeup;
872 u32 rx;
873 u32 rx_handlers[REPLY_MAX];
874 u32 tx;
875 u32 unhandled;
876};
5d08cd1d 877
22fdf3c9
WYG
878#ifdef CONFIG_IWLWIFI_DEBUGFS
879/* management statistics */
880enum iwl_mgmt_stats {
881 MANAGEMENT_ASSOC_REQ = 0,
882 MANAGEMENT_ASSOC_RESP,
883 MANAGEMENT_REASSOC_REQ,
884 MANAGEMENT_REASSOC_RESP,
885 MANAGEMENT_PROBE_REQ,
886 MANAGEMENT_PROBE_RESP,
887 MANAGEMENT_BEACON,
888 MANAGEMENT_ATIM,
889 MANAGEMENT_DISASSOC,
890 MANAGEMENT_AUTH,
891 MANAGEMENT_DEAUTH,
892 MANAGEMENT_ACTION,
893 MANAGEMENT_MAX,
894};
895/* control statistics */
896enum iwl_ctrl_stats {
897 CONTROL_BACK_REQ = 0,
898 CONTROL_BACK,
899 CONTROL_PSPOLL,
900 CONTROL_RTS,
901 CONTROL_CTS,
902 CONTROL_ACK,
903 CONTROL_CFEND,
904 CONTROL_CFENDACK,
905 CONTROL_MAX,
906};
907
908struct traffic_stats {
909 u32 mgmt[MANAGEMENT_MAX];
910 u32 ctrl[CONTROL_MAX];
911 u32 data_cnt;
912 u64 data_bytes;
913};
914#else
915struct traffic_stats {
916 u64 data_bytes;
917};
918#endif
919
0924e519
WYG
920/*
921 * iwl_switch_rxon: "channel switch" structure
922 *
923 * @ switch_in_progress: channel switch in progress
924 * @ channel: new channel
925 */
926struct iwl_switch_rxon {
927 bool switch_in_progress;
928 __le16 channel;
929};
930
a9e1cb6a
WYG
931/*
932 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
933 * to perform continuous uCode event logging operation if enabled
934 */
935#define UCODE_TRACE_PERIOD (100)
936
937/*
938 * iwl_event_log: current uCode event log position
939 *
940 * @ucode_trace: enable/disable ucode continuous trace timer
941 * @num_wraps: how many times the event buffer wraps
942 * @next_entry: the entry just before the next one that uCode would fill
943 * @non_wraps_count: counter for no wrap detected when dump ucode events
944 * @wraps_once_count: counter for wrap once detected when dump ucode events
945 * @wraps_more_count: counter for wrap more than once detected
946 * when dump ucode events
947 */
948struct iwl_event_log {
949 bool ucode_trace;
950 u32 num_wraps;
951 u32 next_entry;
952 int non_wraps_count;
953 int wraps_once_count;
954 int wraps_more_count;
955};
956
2be76703
WYG
957/*
958 * host interrupt timeout value
959 * used with setting interrupt coalescing timer
960 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
961 *
962 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
963 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
964 */
965#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
966#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
967#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
968#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
969#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
970#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
971
3e4fb5fa
TAN
972/*
973 * This is the threshold value of plcp error rate per 100mSecs. It is
974 * used to set and check for the validity of plcp_delta.
975 */
976#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (0)
977#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
978#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 979#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa
TAN
980#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
981
8a472da4
WYG
982#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
983#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
984
b74e31a9
WYG
985/* timer constants use to monitor and recover stuck tx queues in mSecs */
986#define IWL_MONITORING_PERIOD (1000)
987#define IWL_ONE_HUNDRED_MSECS (100)
988#define IWL_SIXTY_SECS (60000)
989
a93e7973
WYG
990enum iwl_reset {
991 IWL_RF_RESET = 0,
992 IWL_FW_RESET,
8a472da4
WYG
993 IWL_MAX_FORCE_RESET,
994};
995
996struct iwl_force_reset {
997 int reset_request_count;
998 int reset_success_count;
999 int reset_reject_count;
1000 unsigned long reset_duration;
1001 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1002};
1003
c79dd5b5 1004struct iwl_priv {
5d08cd1d
CH
1005
1006 /* ieee device used by generic ieee processing code */
1007 struct ieee80211_hw *hw;
1008 struct ieee80211_channel *ieee_channels;
1009 struct ieee80211_rate *ieee_rates;
82b9a121 1010 struct iwl_cfg *cfg;
5d08cd1d
CH
1011
1012 /* temporary frame storage list */
1013 struct list_head free_frames;
1014 int frames_count;
1015
8318d78a 1016 enum ieee80211_band band;
2f301227 1017 int alloc_rxb_page;
5d08cd1d 1018
c79dd5b5 1019 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1020 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1021
8318d78a 1022 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1023
5d08cd1d 1024 /* spectrum measurement report caching */
2aa6ab86 1025 struct iwl_spectrum_notification measure_report;
5d08cd1d 1026 u8 measurement_status;
81963d68 1027
5d08cd1d
CH
1028 /* ucode beacon time */
1029 u32 ucode_beacon_time;
a13d276f 1030 int missed_beacon_threshold;
5d08cd1d 1031
3e4fb5fa
TAN
1032 /* storing the jiffies when the plcp error rate is received */
1033 unsigned long plcp_jiffies;
1034
a93e7973 1035 /* force reset */
8a472da4 1036 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1037
bb8c093b 1038 /* we allocate array of iwl4965_channel_info for NIC's valid channels.
5d08cd1d 1039 * Access via channel # using indirect index array */
bf85ea4f 1040 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1041 u8 channel_count; /* # of channels */
1042
5d08cd1d
CH
1043 /* thermal calibration */
1044 s32 temperature; /* degrees Kelvin */
1045 s32 last_temperature;
1046
7c616cba 1047 /* init calibration results */
6e21f2c1 1048 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1049
5d08cd1d 1050 /* Scan related variables */
7878a5a4 1051 unsigned long next_scan_jiffies;
5d08cd1d
CH
1052 unsigned long scan_start;
1053 unsigned long scan_pass_start;
1054 unsigned long scan_start_tsf;
805cee5b 1055 void *scan;
5d08cd1d 1056 int scan_bands;
1ecf9fc1 1057 struct cfg80211_scan_request *scan_request;
afbdd69a 1058 bool is_internal_short_scan;
76eff18b
TW
1059 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1060 u8 mgmt_tx_ant;
5d08cd1d
CH
1061
1062 /* spinlock */
1063 spinlock_t lock; /* protect general shared data */
1064 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1065 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d 1066 struct mutex mutex;
d2dfe6df 1067 struct mutex sync_cmd_mutex; /* enable serialization of sync commands */
5d08cd1d
CH
1068
1069 /* basic pci-network driver stuff */
1070 struct pci_dev *pci_dev;
1071
1072 /* pci hardware address support */
1073 void __iomem *hw_base;
b661c819
TW
1074 u32 hw_rev;
1075 u32 hw_wa_rev;
1076 u8 rev_id;
5d08cd1d
CH
1077
1078 /* uCode images, save to reload in case of failure */
b08dfd04 1079 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1080 u32 ucode_ver; /* version of ucode, copy of
1081 iwl_ucode.ver */
5d08cd1d
CH
1082 struct fw_desc ucode_code; /* runtime inst */
1083 struct fw_desc ucode_data; /* runtime data original */
1084 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1085 struct fw_desc ucode_init; /* initialization inst */
1086 struct fw_desc ucode_init_data; /* initialization data */
1087 struct fw_desc ucode_boot; /* bootstrap inst */
dbb983b7
RR
1088 enum ucode_type ucode_type;
1089 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1090 char firmware_name[25];
5d08cd1d
CH
1091
1092
3195c1f3 1093 struct iwl_rxon_time_cmd rxon_timing;
5d08cd1d
CH
1094
1095 /* We declare this const so it can only be
1096 * changed via explicit cast within the
1097 * routines that actually update the physical
1098 * hardware */
c1adf9fb
GG
1099 const struct iwl_rxon_cmd active_rxon;
1100 struct iwl_rxon_cmd staging_rxon;
5d08cd1d 1101
0924e519
WYG
1102 struct iwl_switch_rxon switch_rxon;
1103
5d08cd1d
CH
1104 /* 1st responses from initialize and runtime uCode images.
1105 * 4965's initialize alive response contains some calibration data. */
885ba202
TW
1106 struct iwl_init_alive_resp card_alive_init;
1107 struct iwl_alive_resp card_alive;
5d08cd1d 1108
ab53d8af
MA
1109 unsigned long last_blink_time;
1110 u8 last_blink_rate;
1111 u8 allow_blinking;
1112 u64 led_tpt;
e932a609 1113
5d08cd1d 1114 u16 active_rate;
5d08cd1d 1115
5d08cd1d 1116 u8 start_calib;
f0832f13
EG
1117 struct iwl_sensitivity_data sensitivity_data;
1118 struct iwl_chain_noise_data chain_noise_data;
5d08cd1d 1119 __le16 sensitivity_tbl[HD_TABLE_SIZE];
5d08cd1d 1120
fad95bf5 1121 struct iwl_ht_config current_ht_config;
5d08cd1d
CH
1122 u8 last_phy_res[100];
1123
5d08cd1d 1124 /* Rate scaling data */
5d08cd1d
CH
1125 u8 retry_rate;
1126
1127 wait_queue_head_t wait_command_queue;
1128
1129 int activity_timer_active;
1130
1131 /* Rx and Tx DMA processing queues */
a55360e4 1132 struct iwl_rx_queue rxq;
88804e2b 1133 struct iwl_tx_queue *txq;
5d08cd1d 1134 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1135 struct iwl_dma_ptr kw; /* keep warm address */
1136 struct iwl_dma_ptr scd_bc_tbls;
1137
5d08cd1d
CH
1138 u32 scd_base_addr; /* scheduler sram base address */
1139
1140 unsigned long status;
5d08cd1d 1141
19758bef 1142 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1143 struct traffic_stats tx_stats;
1144 struct traffic_stats rx_stats;
19758bef 1145
a83b9141
WYG
1146 /* counts interrupts */
1147 struct isr_statistics isr_stats;
1148
5da4b55f 1149 struct iwl_power_mgr power_data;
3ad3b92a 1150 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1151
8f91aecb 1152 struct iwl_notif_statistics statistics;
92a35bda
WYG
1153#ifdef CONFIG_IWLWIFI_DEBUG
1154 struct iwl_notif_statistics accum_statistics;
e3ef2164
WYG
1155 struct iwl_notif_statistics delta_statistics;
1156 struct iwl_notif_statistics max_delta;
92a35bda 1157#endif
5d08cd1d
CH
1158
1159 /* context information */
5d08cd1d
CH
1160 u8 bssid[ETH_ALEN];
1161 u16 rts_threshold;
1162 u8 mac_addr[ETH_ALEN];
1163
1164 /*station table variables */
1165 spinlock_t sta_lock;
1166 int num_stations;
6def9761 1167 struct iwl_station_entry stations[IWL_STATION_COUNT];
72e15d71 1168 struct iwl_wep_key wep_keys[WEP_KEYS_MAX]; /* protected by mutex */
6974e363
EG
1169 u8 default_wep_key;
1170 u8 key_mapping_key;
80fb47a1 1171 unsigned long ucode_key_table;
5d08cd1d 1172
e4e72fb4
JB
1173 /* queue refcounts */
1174#define IWL_MAX_HW_QUEUES 32
1175 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1176 /* for each AC */
1177 atomic_t queue_stop_count[4];
1178
5d08cd1d 1179 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1180 u8 is_open;
5d08cd1d
CH
1181
1182 u8 mac80211_registered;
5d08cd1d 1183
af6b8ee3 1184 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1185 u8 *eeprom;
0848e297 1186 int nvm_device_type;
073d3f5f 1187 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1188
05c914fe 1189 enum nl80211_iftype iw_mode;
5d08cd1d
CH
1190
1191 struct sk_buff *ibss_beacon;
1192
1193 /* Last Rx'd beacon timestamp */
3109ece1 1194 u64 timestamp;
5d08cd1d 1195 u16 beacon_int;
32bfd35d 1196 struct ieee80211_vif *vif;
5d08cd1d 1197
ee525d13
JB
1198 union {
1199#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1200 struct {
1201 void *shared_virt;
1202 dma_addr_t shared_phys;
1203
1204 struct delayed_work thermal_periodic;
1205 struct delayed_work rfkill_poll;
1206
1207 struct iwl3945_notif_statistics statistics;
1208
1209 u32 sta_supp_rates;
e99f168c
JB
1210 int last_rx_rssi; /* From Rx packet statistics */
1211
1212 /* Rx'd packet timing information */
1213 u32 last_beacon_time;
1214 u64 last_tsf;
67d613ae
JB
1215
1216 /*
1217 * each calibration channel group in the
1218 * EEPROM has a derived clip setting for
1219 * each rate.
1220 */
1221 const struct iwl3945_clip_group clip_groups[5];
1222
ee525d13 1223 } _3945;
a4c8b2a6
JB
1224#endif
1225#if defined(CONFIG_IWLAGN) || defined(CONFIG_IWLAGN_MODULE)
1226 struct {
1227 /* INT ICT Table */
1228 __le32 *ict_tbl;
1229 void *ict_tbl_vir;
1230 dma_addr_t ict_tbl_dma;
1231 dma_addr_t aligned_ict_tbl_dma;
1232 int ict_index;
1233 u32 inta;
1234 bool use_ict;
d5a0ffa3
WYG
1235 /*
1236 * reporting the number of tids has AGG on. 0 means
1237 * no AGGREGATION
1238 */
1239 u8 agg_tids_count;
a4c8b2a6 1240 } _agn;
ee525d13
JB
1241#endif
1242 };
1243
5425e490 1244 struct iwl_hw_params hw_params;
4ddbb7d0 1245
40cefda9 1246 u32 inta_mask;
5d08cd1d
CH
1247 /* Current association information needed to configure the
1248 * hardware */
1249 u16 assoc_id;
1250 u16 assoc_capability;
5d08cd1d 1251
1ff50bda 1252 struct iwl_qos_info qos_data;
5d08cd1d
CH
1253
1254 struct workqueue_struct *workqueue;
1255
5d08cd1d 1256 struct work_struct restart;
5d08cd1d
CH
1257 struct work_struct scan_completed;
1258 struct work_struct rx_replenish;
5d08cd1d 1259 struct work_struct abort_scan;
5d08cd1d
CH
1260 struct work_struct request_scan;
1261 struct work_struct beacon_update;
a28027cd
WYG
1262 struct work_struct tt_work;
1263 struct work_struct ct_enter;
1264 struct work_struct ct_exit;
5d08cd1d
CH
1265
1266 struct tasklet_struct irq_tasklet;
1267
1268 struct delayed_work init_alive_start;
1269 struct delayed_work alive_start;
5d08cd1d 1270 struct delayed_work scan_check;
4a8a4322 1271
630fe9b6
TW
1272 /* TX Power */
1273 s8 tx_power_user_lmt;
dc1b0973 1274 s8 tx_power_device_lmt;
ae16fc3c 1275 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
5d08cd1d 1276
5d08cd1d 1277
d08853a3 1278#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1279 /* debugging info */
3d816c77
RC
1280 u32 debug_level; /* per device debugging will override global
1281 iwl_debug_level if set */
5d08cd1d
CH
1282 u32 framecnt_to_us;
1283 atomic_t restrict_refcnt;
1e4247d4 1284 bool disable_ht40;
712b6cf5
TW
1285#ifdef CONFIG_IWLWIFI_DEBUGFS
1286 /* debugfs */
20594eb0
WYG
1287 u16 tx_traffic_idx;
1288 u16 rx_traffic_idx;
1289 u8 *tx_traffic;
1290 u8 *rx_traffic;
4c84a8f1
JB
1291 struct dentry *debugfs_dir;
1292 u32 dbgfs_sram_offset, dbgfs_sram_len;
712b6cf5
TW
1293#endif /* CONFIG_IWLWIFI_DEBUGFS */
1294#endif /* CONFIG_IWLWIFI_DEBUG */
5d08cd1d
CH
1295
1296 struct work_struct txpower_work;
445c2dff
TW
1297 u32 disable_sens_cal;
1298 u32 disable_chain_noise_cal;
203566f3 1299 u32 disable_tx_power_cal;
16e727e8 1300 struct work_struct run_time_calib_work;
5d08cd1d 1301 struct timer_list statistics_periodic;
a9e1cb6a 1302 struct timer_list ucode_trace;
b74e31a9 1303 struct timer_list monitor_recover;
086ed117 1304 bool hw_ready;
a9e1cb6a
WYG
1305
1306 struct iwl_event_log event_log;
c79dd5b5 1307}; /*iwl_priv */
5d08cd1d 1308
36470749
RR
1309static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1310{
1311 set_bit(txq_id, &priv->txq_ctx_active_msk);
1312}
1313
1314static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1315{
1316 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1317}
1318
994d31f7 1319#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6 1320const char *iwl_get_tx_fail_reason(u32 status);
3d816c77
RC
1321/*
1322 * iwl_get_debug_level: Return active debug level for device
1323 *
1324 * Using sysfs it is possible to set per device debug level. This debug
1325 * level will be used if set, otherwise the global debug level which can be
1326 * set via module parameter is used.
1327 */
1328static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1329{
1330 if (priv->debug_level)
1331 return priv->debug_level;
1332 else
1333 return iwl_debug_level;
1334}
a332f8d6
TW
1335#else
1336static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; }
3d816c77
RC
1337
1338static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1339{
1340 return iwl_debug_level;
1341}
a332f8d6
TW
1342#endif
1343
1344
a332f8d6
TW
1345static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1346 int txq_id, int idx)
1347{
1348 if (priv->txq[txq_id].txb[idx].skb[0])
1349 return (struct ieee80211_hdr *)priv->txq[txq_id].
1350 txb[idx].skb[0]->data;
1351 return NULL;
1352}
a332f8d6
TW
1353
1354
3109ece1 1355static inline int iwl_is_associated(struct iwl_priv *priv)
5d08cd1d
CH
1356{
1357 return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1358}
1359
bf85ea4f 1360static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1361{
1362 if (ch_info == NULL)
1363 return 0;
1364 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1365}
1366
bf85ea4f 1367static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1368{
1369 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1370}
1371
bf85ea4f 1372static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1373{
8318d78a 1374 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1375}
1376
bf85ea4f 1377static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1378{
8318d78a 1379 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1380}
1381
bf85ea4f 1382static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1383{
1384 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1385}
1386
bf85ea4f 1387static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1388{
1389 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1390}
1391
64a76b50
ZY
1392static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1393{
1394 __free_pages(page, priv->hw_params.rx_page_order);
1395 priv->alloc_rxb_page--;
1396}
1397
1398static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1399{
1400 free_pages(page, priv->hw_params.rx_page_order);
1401 priv->alloc_rxb_page--;
1402}
be1f3ab6 1403#endif /* __iwl_dev_h__ */