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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
759ef89f | 22 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
24 | * | |
25 | *****************************************************************************/ | |
fcd427bb | 26 | /* |
3e0d4cb1 | 27 | * Please use this file (iwl-dev.h) for driver implementation definitions. |
5a36ba0e | 28 | * Please use iwl-commands.h for uCode API definitions. |
fcd427bb BC |
29 | * Please use iwl-4965-hw.h for hardware-related definitions. |
30 | */ | |
31 | ||
be1f3ab6 EG |
32 | #ifndef __iwl_dev_h__ |
33 | #define __iwl_dev_h__ | |
b481de9c | 34 | |
5d08cd1d CH |
35 | #include <linux/pci.h> /* for struct pci_device_id */ |
36 | #include <linux/kernel.h> | |
37 | #include <net/ieee80211_radiotap.h> | |
38 | ||
6bc913bd | 39 | #include "iwl-eeprom.h" |
6f83eaa1 | 40 | #include "iwl-csr.h" |
5d08cd1d | 41 | #include "iwl-prph.h" |
dbb6654c | 42 | #include "iwl-fh.h" |
0a6857e7 | 43 | #include "iwl-debug.h" |
dbb6654c WT |
44 | #include "iwl-rfkill.h" |
45 | #include "iwl-4965-hw.h" | |
46 | #include "iwl-3945-hw.h" | |
47 | #include "iwl-3945-led.h" | |
ab53d8af | 48 | #include "iwl-led.h" |
5da4b55f | 49 | #include "iwl-power.h" |
e227ceac | 50 | #include "iwl-agn-rs.h" |
5d08cd1d | 51 | |
fed9017e RR |
52 | /* configuration for the iwl4965 */ |
53 | extern struct iwl_cfg iwl4965_agn_cfg; | |
5a6a256e TW |
54 | extern struct iwl_cfg iwl5300_agn_cfg; |
55 | extern struct iwl_cfg iwl5100_agn_cfg; | |
56 | extern struct iwl_cfg iwl5350_agn_cfg; | |
47408639 EK |
57 | extern struct iwl_cfg iwl5100_bg_cfg; |
58 | extern struct iwl_cfg iwl5100_abg_cfg; | |
7100e924 | 59 | extern struct iwl_cfg iwl5150_agn_cfg; |
e1228374 JS |
60 | extern struct iwl_cfg iwl6000_2ag_cfg; |
61 | extern struct iwl_cfg iwl6000_2agn_cfg; | |
62 | extern struct iwl_cfg iwl6000_3agn_cfg; | |
63 | extern struct iwl_cfg iwl6050_2agn_cfg; | |
64 | extern struct iwl_cfg iwl6050_3agn_cfg; | |
77dcb6a9 | 65 | extern struct iwl_cfg iwl1000_bgn_cfg; |
fed9017e | 66 | |
cec2d3f3 JS |
67 | /* shared structures from iwl-5000.c */ |
68 | extern struct iwl_mod_params iwl50_mod_params; | |
69 | extern struct iwl_ops iwl5000_ops; | |
e8c00dcb JS |
70 | extern struct iwl_lib_ops iwl5000_lib; |
71 | extern struct iwl_hcmd_ops iwl5000_hcmd; | |
72 | extern struct iwl_hcmd_utils_ops iwl5000_hcmd_utils; | |
79fa455a | 73 | extern struct iwl_station_mgmt_ops iwl5000_station_mgmt; |
e8c00dcb JS |
74 | |
75 | /* shared functions from iwl-5000.c */ | |
76 | extern u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len); | |
77 | extern u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, | |
78 | u8 *data); | |
79 | extern void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, | |
80 | __le32 *tx_flags); | |
81 | extern int iwl5000_calc_rssi(struct iwl_priv *priv, | |
82 | struct iwl_rx_phy_res *rx_resp); | |
cec2d3f3 | 83 | |
099b40b7 RR |
84 | /* CT-KILL constants */ |
85 | #define CT_KILL_THRESHOLD 110 /* in Celsius */ | |
4bf775cd | 86 | |
5d08cd1d CH |
87 | /* Default noise level to report when noise measurement is not available. |
88 | * This may be because we're: | |
89 | * 1) Not associated (4965, no beacon statistics being sent to driver) | |
90 | * 2) Scanning (noise measurement does not apply to associated channel) | |
91 | * 3) Receiving CCK (3945 delivers noise info only for OFDM frames) | |
92 | * Use default noise value of -127 ... this is below the range of measurable | |
93 | * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user. | |
94 | * Also, -127 works better than 0 when averaging frames with/without | |
95 | * noise info (e.g. averaging might be done in app); measured dBm values are | |
96 | * always negative ... using a negative value as the default keeps all | |
97 | * averages within an s8's (used in some apps) range of negative values. */ | |
98 | #define IWL_NOISE_MEAS_NOT_AVAILABLE (-127) | |
99 | ||
5d08cd1d CH |
100 | /* |
101 | * RTS threshold here is total size [2347] minus 4 FCS bytes | |
102 | * Per spec: | |
103 | * a value of 0 means RTS on all data/management packets | |
104 | * a value > max MSDU size means no RTS | |
105 | * else RTS for data/management frames where MPDU is larger | |
106 | * than RTS value. | |
107 | */ | |
108 | #define DEFAULT_RTS_THRESHOLD 2347U | |
109 | #define MIN_RTS_THRESHOLD 0U | |
110 | #define MAX_RTS_THRESHOLD 2347U | |
111 | #define MAX_MSDU_SIZE 2304U | |
112 | #define MAX_MPDU_SIZE 2346U | |
113 | #define DEFAULT_BEACON_INTERVAL 100U | |
114 | #define DEFAULT_SHORT_RETRY_LIMIT 7U | |
115 | #define DEFAULT_LONG_RETRY_LIMIT 4U | |
116 | ||
a55360e4 | 117 | struct iwl_rx_mem_buffer { |
4018517a JB |
118 | dma_addr_t real_dma_addr; |
119 | dma_addr_t aligned_dma_addr; | |
5d08cd1d CH |
120 | struct sk_buff *skb; |
121 | struct list_head list; | |
122 | }; | |
123 | ||
5d08cd1d CH |
124 | /* |
125 | * Generic queue structure | |
126 | * | |
127 | * Contains common data for Rx and Tx queues | |
128 | */ | |
443cfd45 | 129 | struct iwl_queue { |
5d08cd1d CH |
130 | int n_bd; /* number of BDs in this queue */ |
131 | int write_ptr; /* 1-st empty entry (index) host_w*/ | |
132 | int read_ptr; /* last used entry (index) host_r*/ | |
133 | dma_addr_t dma_addr; /* physical addr for BD's */ | |
134 | int n_window; /* safe queue window */ | |
135 | u32 id; | |
136 | int low_mark; /* low watermark, resume queue if free | |
137 | * space more than this */ | |
138 | int high_mark; /* high watermark, stop queue if free | |
139 | * space less than this */ | |
140 | } __attribute__ ((packed)); | |
141 | ||
bc47279f | 142 | /* One for each TFD */ |
8567c63e | 143 | struct iwl_tx_info { |
499b1883 | 144 | struct sk_buff *skb[IWL_NUM_OF_TBS - 1]; |
5d08cd1d CH |
145 | }; |
146 | ||
147 | /** | |
16466903 | 148 | * struct iwl_tx_queue - Tx Queue for DMA |
bc47279f BC |
149 | * @q: generic Rx/Tx queue descriptor |
150 | * @bd: base of circular buffer of TFDs | |
151 | * @cmd: array of command/Tx buffers | |
152 | * @dma_addr_cmd: physical address of cmd/tx buffer array | |
153 | * @txb: array of per-TFD driver data | |
154 | * @need_update: indicates need to update read/write index | |
155 | * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled | |
5d08cd1d | 156 | * |
bc47279f BC |
157 | * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame |
158 | * descriptors) and required locking structures. | |
5d08cd1d | 159 | */ |
188cf6c7 SO |
160 | #define TFD_TX_CMD_SLOTS 256 |
161 | #define TFD_CMD_SLOTS 32 | |
162 | ||
16466903 | 163 | struct iwl_tx_queue { |
443cfd45 | 164 | struct iwl_queue q; |
59606ffa | 165 | void *tfds; |
da99c4b6 | 166 | struct iwl_cmd *cmd[TFD_TX_CMD_SLOTS]; |
8567c63e | 167 | struct iwl_tx_info *txb; |
3fd07a1e TW |
168 | u8 need_update; |
169 | u8 sched_retry; | |
170 | u8 active; | |
171 | u8 swq_id; | |
5d08cd1d CH |
172 | }; |
173 | ||
174 | #define IWL_NUM_SCAN_RATES (2) | |
175 | ||
bb8c093b | 176 | struct iwl4965_channel_tgd_info { |
5d08cd1d CH |
177 | u8 type; |
178 | s8 max_power; | |
179 | }; | |
180 | ||
bb8c093b | 181 | struct iwl4965_channel_tgh_info { |
5d08cd1d CH |
182 | s64 last_radar_time; |
183 | }; | |
184 | ||
d20b3c65 SO |
185 | #define IWL4965_MAX_RATE (33) |
186 | ||
85d41495 KA |
187 | struct iwl3945_clip_group { |
188 | /* maximum power level to prevent clipping for each rate, derived by | |
189 | * us from this band's saturation power in EEPROM */ | |
190 | const s8 clip_powers[IWL_MAX_RATES]; | |
191 | }; | |
192 | ||
d20b3c65 SO |
193 | /* current Tx power values to use, one for each rate for each channel. |
194 | * requested power is limited by: | |
195 | * -- regulatory EEPROM limits for this channel | |
196 | * -- hardware capabilities (clip-powers) | |
197 | * -- spectrum management | |
198 | * -- user preference (e.g. iwconfig) | |
199 | * when requested power is set, base power index must also be set. */ | |
200 | struct iwl3945_channel_power_info { | |
201 | struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */ | |
202 | s8 power_table_index; /* actual (compenst'd) index into gain table */ | |
203 | s8 base_power_index; /* gain index for power at factory temp. */ | |
204 | s8 requested_power; /* power (dBm) requested for this chnl/rate */ | |
205 | }; | |
206 | ||
207 | /* current scan Tx power values to use, one for each scan rate for each | |
208 | * channel. */ | |
209 | struct iwl3945_scan_power_info { | |
210 | struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */ | |
211 | s8 power_table_index; /* actual (compenst'd) index into gain table */ | |
212 | s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */ | |
213 | }; | |
214 | ||
5d08cd1d CH |
215 | /* |
216 | * One for each channel, holds all channel setup data | |
217 | * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant | |
218 | * with one another! | |
219 | */ | |
bf85ea4f | 220 | struct iwl_channel_info { |
bb8c093b CH |
221 | struct iwl4965_channel_tgd_info tgd; |
222 | struct iwl4965_channel_tgh_info tgh; | |
073d3f5f TW |
223 | struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */ |
224 | struct iwl_eeprom_channel fat_eeprom; /* EEPROM regulatory limit for | |
225 | * FAT channel */ | |
5d08cd1d CH |
226 | |
227 | u8 channel; /* channel number */ | |
228 | u8 flags; /* flags copied from EEPROM */ | |
229 | s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
fcd427bb | 230 | s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */ |
5d08cd1d CH |
231 | s8 min_power; /* always 0 */ |
232 | s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */ | |
233 | ||
234 | u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */ | |
235 | u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */ | |
8318d78a | 236 | enum ieee80211_band band; |
5d08cd1d | 237 | |
5d08cd1d CH |
238 | /* FAT channel info */ |
239 | s8 fat_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ | |
240 | s8 fat_curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */ | |
241 | s8 fat_min_power; /* always 0 */ | |
242 | s8 fat_scan_power; /* (dBm) eeprom, direct scans, any rate */ | |
243 | u8 fat_flags; /* flags copied from EEPROM */ | |
fcd427bb | 244 | u8 fat_extension_channel; /* HT_IE_EXT_CHANNEL_* */ |
d20b3c65 SO |
245 | |
246 | /* Radio/DSP gain settings for each "normal" data Tx rate. | |
247 | * These include, in addition to RF and DSP gain, a few fields for | |
248 | * remembering/modifying gain settings (indexes). */ | |
249 | struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE]; | |
250 | ||
251 | /* Radio/DSP gain settings for each scan rate, for directed scans. */ | |
252 | struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES]; | |
5d08cd1d CH |
253 | }; |
254 | ||
5d08cd1d CH |
255 | #define IWL_TX_FIFO_AC0 0 |
256 | #define IWL_TX_FIFO_AC1 1 | |
257 | #define IWL_TX_FIFO_AC2 2 | |
258 | #define IWL_TX_FIFO_AC3 3 | |
259 | #define IWL_TX_FIFO_HCCA_1 5 | |
260 | #define IWL_TX_FIFO_HCCA_2 6 | |
261 | #define IWL_TX_FIFO_NONE 7 | |
262 | ||
263 | /* Minimum number of queues. MAX_NUM is defined in hw specific files */ | |
264 | #define IWL_MIN_NUM_QUEUES 4 | |
265 | ||
266 | /* Power management (not Tx power) structures */ | |
267 | ||
6f4083aa TW |
268 | enum iwl_pwr_src { |
269 | IWL_PWR_SRC_VMAIN, | |
270 | IWL_PWR_SRC_VAUX, | |
271 | }; | |
272 | ||
5d08cd1d CH |
273 | #define IEEE80211_DATA_LEN 2304 |
274 | #define IEEE80211_4ADDR_LEN 30 | |
275 | #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) | |
276 | #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) | |
277 | ||
fcab423d | 278 | struct iwl_frame { |
5d08cd1d CH |
279 | union { |
280 | struct ieee80211_hdr frame; | |
4bf64efd | 281 | struct iwl_tx_beacon_cmd beacon; |
5d08cd1d CH |
282 | u8 raw[IEEE80211_FRAME_LEN]; |
283 | u8 cmd[360]; | |
284 | } u; | |
285 | struct list_head list; | |
286 | }; | |
287 | ||
5d08cd1d CH |
288 | #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) |
289 | #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) | |
290 | #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) | |
291 | ||
292 | enum { | |
293 | /* CMD_SIZE_NORMAL = 0, */ | |
294 | CMD_SIZE_HUGE = (1 << 0), | |
295 | /* CMD_SYNC = 0, */ | |
296 | CMD_ASYNC = (1 << 1), | |
297 | /* CMD_NO_SKB = 0, */ | |
298 | CMD_WANT_SKB = (1 << 2), | |
299 | }; | |
300 | ||
857485c0 | 301 | struct iwl_cmd; |
c79dd5b5 | 302 | struct iwl_priv; |
5d08cd1d | 303 | |
857485c0 TW |
304 | struct iwl_cmd_meta { |
305 | struct iwl_cmd_meta *source; | |
5d08cd1d CH |
306 | union { |
307 | struct sk_buff *skb; | |
c79dd5b5 | 308 | int (*callback)(struct iwl_priv *priv, |
857485c0 | 309 | struct iwl_cmd *cmd, struct sk_buff *skb); |
5d08cd1d CH |
310 | } __attribute__ ((packed)) u; |
311 | ||
312 | /* The CMD_SIZE_HUGE flag bit indicates that the command | |
313 | * structure is stored at the end of the shared queue memory. */ | |
314 | u32 flags; | |
499b1883 TW |
315 | DECLARE_PCI_UNMAP_ADDR(mapping) |
316 | DECLARE_PCI_UNMAP_LEN(len) | |
5d08cd1d CH |
317 | } __attribute__ ((packed)); |
318 | ||
d2f18bfd | 319 | #define IWL_CMD_MAX_PAYLOAD 320 |
bd68fb6f | 320 | |
bc47279f | 321 | /** |
857485c0 | 322 | * struct iwl_cmd |
bc47279f BC |
323 | * |
324 | * For allocation of the command and tx queues, this establishes the overall | |
325 | * size of the largest command we send to uCode, except for a scan command | |
326 | * (which is relatively huge; space is allocated separately). | |
327 | */ | |
857485c0 TW |
328 | struct iwl_cmd { |
329 | struct iwl_cmd_meta meta; /* driver data */ | |
330 | struct iwl_cmd_header hdr; /* uCode API */ | |
5d08cd1d | 331 | union { |
5d08cd1d CH |
332 | u32 flags; |
333 | u8 val8; | |
334 | u16 val16; | |
335 | u32 val32; | |
83d527d9 | 336 | struct iwl_tx_cmd tx; |
bd68fb6f | 337 | u8 payload[IWL_CMD_MAX_PAYLOAD]; |
5d08cd1d CH |
338 | } __attribute__ ((packed)) cmd; |
339 | } __attribute__ ((packed)); | |
340 | ||
3257e5d4 | 341 | |
857485c0 | 342 | struct iwl_host_cmd { |
5d08cd1d CH |
343 | u8 id; |
344 | u16 len; | |
857485c0 | 345 | struct iwl_cmd_meta meta; |
5d08cd1d CH |
346 | const void *data; |
347 | }; | |
348 | ||
857485c0 TW |
349 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \ |
350 | sizeof(struct iwl_cmd_meta)) | |
5d08cd1d CH |
351 | |
352 | /* | |
353 | * RX related structures and functions | |
354 | */ | |
355 | #define RX_FREE_BUFFERS 64 | |
356 | #define RX_LOW_WATERMARK 8 | |
357 | ||
358 | #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 | |
359 | #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 | |
360 | #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 | |
361 | ||
362 | /** | |
a55360e4 | 363 | * struct iwl_rx_queue - Rx queue |
5d08cd1d CH |
364 | * @read: Shared index to newest available Rx buffer |
365 | * @write: Shared index to oldest written Rx packet | |
366 | * @free_count: Number of pre-allocated buffers in rx_free | |
367 | * @rx_free: list of free SKBs for use | |
368 | * @rx_used: List of Rx buffers with no SKB | |
369 | * @need_update: flag to indicate we need to update read/write index | |
370 | * | |
a55360e4 | 371 | * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers |
5d08cd1d | 372 | */ |
a55360e4 | 373 | struct iwl_rx_queue { |
5d08cd1d CH |
374 | __le32 *bd; |
375 | dma_addr_t dma_addr; | |
a55360e4 TW |
376 | struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; |
377 | struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; | |
5d08cd1d CH |
378 | u32 read; |
379 | u32 write; | |
380 | u32 free_count; | |
381 | struct list_head rx_free; | |
382 | struct list_head rx_used; | |
383 | int need_update; | |
8d86422a WT |
384 | struct iwl_rb_status *rb_stts; |
385 | dma_addr_t rb_stts_dma; | |
5d08cd1d CH |
386 | spinlock_t lock; |
387 | }; | |
388 | ||
389 | #define IWL_SUPPORTED_RATES_IE_LEN 8 | |
390 | ||
5d08cd1d CH |
391 | #define MAX_TID_COUNT 9 |
392 | ||
393 | #define IWL_INVALID_RATE 0xFF | |
394 | #define IWL_INVALID_VALUE -1 | |
395 | ||
bc47279f | 396 | /** |
6def9761 | 397 | * struct iwl_ht_agg -- aggregation status while waiting for block-ack |
bc47279f BC |
398 | * @txq_id: Tx queue used for Tx attempt |
399 | * @frame_count: # frames attempted by Tx command | |
400 | * @wait_for_ba: Expect block-ack before next Tx reply | |
401 | * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window | |
402 | * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window | |
403 | * @bitmap1: High order, one bit for each frame pending ACK in Tx window | |
404 | * @rate_n_flags: Rate at which Tx was attempted | |
405 | * | |
406 | * If REPLY_TX indicates that aggregation was attempted, driver must wait | |
407 | * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info | |
408 | * until block ack arrives. | |
409 | */ | |
6def9761 | 410 | struct iwl_ht_agg { |
5d08cd1d CH |
411 | u16 txq_id; |
412 | u16 frame_count; | |
413 | u16 wait_for_ba; | |
414 | u16 start_idx; | |
fe01b477 | 415 | u64 bitmap; |
5d08cd1d | 416 | u32 rate_n_flags; |
fe01b477 RR |
417 | #define IWL_AGG_OFF 0 |
418 | #define IWL_AGG_ON 1 | |
419 | #define IWL_EMPTYING_HW_QUEUE_ADDBA 2 | |
420 | #define IWL_EMPTYING_HW_QUEUE_DELBA 3 | |
421 | u8 state; | |
5d08cd1d | 422 | }; |
fe01b477 | 423 | |
5d08cd1d | 424 | |
6def9761 | 425 | struct iwl_tid_data { |
5d08cd1d | 426 | u16 seq_number; |
fe01b477 | 427 | u16 tfds_in_queue; |
6def9761 | 428 | struct iwl_ht_agg agg; |
5d08cd1d CH |
429 | }; |
430 | ||
6def9761 | 431 | struct iwl_hw_key { |
5d08cd1d CH |
432 | enum ieee80211_key_alg alg; |
433 | int keylen; | |
0211ddda | 434 | u8 keyidx; |
5d08cd1d CH |
435 | u8 key[32]; |
436 | }; | |
437 | ||
a78fe754 | 438 | union iwl_ht_rate_supp { |
5d08cd1d CH |
439 | u16 rates; |
440 | struct { | |
441 | u8 siso_rate; | |
442 | u8 mimo_rate; | |
443 | }; | |
444 | }; | |
445 | ||
5d08cd1d | 446 | #define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3) |
5d08cd1d CH |
447 | #define CFG_HT_MPDU_DENSITY_2USEC (0x5) |
448 | #define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_2USEC | |
449 | ||
9e0cc6de RR |
450 | struct iwl_ht_info { |
451 | /* self configuration data */ | |
5d08cd1d | 452 | u8 is_ht; |
9e0cc6de | 453 | u8 supported_chan_width; |
12837be1 | 454 | u8 sm_ps; |
9e0cc6de | 455 | u8 is_green_field; |
bb54244b | 456 | u8 sgf; /* HT_SHORT_GI_* short guard interval */ |
5d08cd1d CH |
457 | u8 max_amsdu_size; |
458 | u8 ampdu_factor; | |
459 | u8 mpdu_density; | |
d9fe60de | 460 | struct ieee80211_mcs_info mcs; |
9e0cc6de | 461 | /* BSS related data */ |
5d08cd1d | 462 | u8 extension_chan_offset; |
5d08cd1d | 463 | u8 tx_chan_width; |
9e0cc6de RR |
464 | u8 ht_protection; |
465 | u8 non_GF_STA_present; | |
5d08cd1d | 466 | }; |
5d08cd1d | 467 | |
1ff50bda | 468 | union iwl_qos_capabity { |
5d08cd1d CH |
469 | struct { |
470 | u8 edca_count:4; /* bit 0-3 */ | |
471 | u8 q_ack:1; /* bit 4 */ | |
472 | u8 queue_request:1; /* bit 5 */ | |
473 | u8 txop_request:1; /* bit 6 */ | |
474 | u8 reserved:1; /* bit 7 */ | |
475 | } q_AP; | |
476 | struct { | |
477 | u8 acvo_APSD:1; /* bit 0 */ | |
478 | u8 acvi_APSD:1; /* bit 1 */ | |
479 | u8 ac_bk_APSD:1; /* bit 2 */ | |
480 | u8 ac_be_APSD:1; /* bit 3 */ | |
481 | u8 q_ack:1; /* bit 4 */ | |
482 | u8 max_len:2; /* bit 5-6 */ | |
483 | u8 more_data_ack:1; /* bit 7 */ | |
484 | } q_STA; | |
485 | u8 val; | |
486 | }; | |
487 | ||
488 | /* QoS structures */ | |
1ff50bda | 489 | struct iwl_qos_info { |
5d08cd1d | 490 | int qos_active; |
1ff50bda EG |
491 | union iwl_qos_capabity qos_cap; |
492 | struct iwl_qosparam_cmd def_qos_parm; | |
5d08cd1d | 493 | }; |
5d08cd1d CH |
494 | |
495 | #define STA_PS_STATUS_WAKE 0 | |
496 | #define STA_PS_STATUS_SLEEP 1 | |
497 | ||
85d41495 KA |
498 | struct iwl3945_tid_data { |
499 | u16 seq_number; | |
500 | }; | |
501 | ||
502 | struct iwl3945_hw_key { | |
503 | enum ieee80211_key_alg alg; | |
504 | int keylen; | |
505 | u8 key[32]; | |
506 | }; | |
507 | ||
508 | struct iwl3945_station_entry { | |
509 | struct iwl3945_addsta_cmd sta; | |
510 | struct iwl3945_tid_data tid[MAX_TID_COUNT]; | |
511 | u8 used; | |
512 | u8 ps_status; | |
513 | struct iwl3945_hw_key keyinfo; | |
514 | }; | |
515 | ||
6def9761 | 516 | struct iwl_station_entry { |
133636de | 517 | struct iwl_addsta_cmd sta; |
6def9761 | 518 | struct iwl_tid_data tid[MAX_TID_COUNT]; |
5d08cd1d CH |
519 | u8 used; |
520 | u8 ps_status; | |
6def9761 | 521 | struct iwl_hw_key keyinfo; |
5d08cd1d CH |
522 | }; |
523 | ||
524 | /* one for each uCode image (inst/data, boot/init/runtime) */ | |
525 | struct fw_desc { | |
526 | void *v_addr; /* access by driver */ | |
527 | dma_addr_t p_addr; /* access by card's busmaster DMA */ | |
528 | u32 len; /* bytes */ | |
529 | }; | |
530 | ||
531 | /* uCode file layout */ | |
14b3d338 | 532 | struct iwl_ucode { |
c02b3acd | 533 | __le32 ver; /* major/minor/API/serial */ |
5d08cd1d CH |
534 | __le32 inst_size; /* bytes of runtime instructions */ |
535 | __le32 data_size; /* bytes of runtime data */ | |
536 | __le32 init_size; /* bytes of initialization instructions */ | |
537 | __le32 init_data_size; /* bytes of initialization data */ | |
538 | __le32 boot_size; /* bytes of bootstrap instructions */ | |
539 | u8 data[0]; /* data in same order as "size" elements */ | |
540 | }; | |
541 | ||
bb8c093b | 542 | struct iwl4965_ibss_seq { |
5d08cd1d CH |
543 | u8 mac[ETH_ALEN]; |
544 | u16 seq_num; | |
545 | u16 frag_num; | |
546 | unsigned long packet_time; | |
547 | struct list_head list; | |
548 | }; | |
549 | ||
f0832f13 EG |
550 | struct iwl_sensitivity_ranges { |
551 | u16 min_nrg_cck; | |
552 | u16 max_nrg_cck; | |
553 | ||
554 | u16 nrg_th_cck; | |
555 | u16 nrg_th_ofdm; | |
556 | ||
557 | u16 auto_corr_min_ofdm; | |
558 | u16 auto_corr_min_ofdm_mrc; | |
559 | u16 auto_corr_min_ofdm_x1; | |
560 | u16 auto_corr_min_ofdm_mrc_x1; | |
561 | ||
562 | u16 auto_corr_max_ofdm; | |
563 | u16 auto_corr_max_ofdm_mrc; | |
564 | u16 auto_corr_max_ofdm_x1; | |
565 | u16 auto_corr_max_ofdm_mrc_x1; | |
566 | ||
567 | u16 auto_corr_max_cck; | |
568 | u16 auto_corr_max_cck_mrc; | |
569 | u16 auto_corr_min_cck; | |
570 | u16 auto_corr_min_cck_mrc; | |
571 | }; | |
572 | ||
099b40b7 | 573 | |
b5047f78 TW |
574 | #define KELVIN_TO_CELSIUS(x) ((x)-273) |
575 | #define CELSIUS_TO_KELVIN(x) ((x)+273) | |
576 | ||
577 | ||
bc47279f | 578 | /** |
5425e490 | 579 | * struct iwl_hw_params |
bc47279f | 580 | * @max_txq_num: Max # Tx queues supported |
f3f911d1 | 581 | * @dma_chnl_num: Number of Tx DMA/FIFO channels |
4ddbb7d0 | 582 | * @scd_bc_tbls_size: size of scheduler byte count tables |
a8e74e27 | 583 | * @tfd_size: TFD size |
099b40b7 RR |
584 | * @tx/rx_chains_num: Number of TX/RX chains |
585 | * @valid_tx/rx_ant: usable antennas | |
bc47279f | 586 | * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2) |
bc47279f | 587 | * @max_rxq_log: Log-base-2 of max_rxq_size |
099b40b7 | 588 | * @rx_buf_size: Rx buffer size |
141c43a3 | 589 | * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR |
bc47279f BC |
590 | * @max_stations: |
591 | * @bcast_sta_id: | |
099b40b7 RR |
592 | * @fat_channel: is 40MHz width possible in band 2.4 |
593 | * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ) | |
594 | * @sw_crypto: 0 for hw, 1 for sw | |
595 | * @max_xxx_size: for ucode uses | |
596 | * @ct_kill_threshold: temperature threshold | |
a96a27f9 | 597 | * @calib_init_cfg: setup initial calibrations for the hw |
f0832f13 | 598 | * @struct iwl_sensitivity_ranges: range of sensitivity values |
bc47279f | 599 | */ |
5425e490 | 600 | struct iwl_hw_params { |
f3f911d1 ZY |
601 | u8 max_txq_num; |
602 | u8 dma_chnl_num; | |
4ddbb7d0 | 603 | u16 scd_bc_tbls_size; |
a8e74e27 | 604 | u32 tfd_size; |
ec35cf2a TW |
605 | u8 tx_chains_num; |
606 | u8 rx_chains_num; | |
607 | u8 valid_tx_ant; | |
608 | u8 valid_rx_ant; | |
5d08cd1d | 609 | u16 max_rxq_size; |
ec35cf2a | 610 | u16 max_rxq_log; |
9ee1ba47 | 611 | u32 rx_buf_size; |
141c43a3 | 612 | u32 rx_wrt_ptr_reg; |
9ee1ba47 | 613 | u32 max_pkt_size; |
5d08cd1d CH |
614 | u8 max_stations; |
615 | u8 bcast_sta_id; | |
099b40b7 RR |
616 | u8 fat_channel; |
617 | u8 sw_crypto; | |
618 | u32 max_inst_size; | |
619 | u32 max_data_size; | |
620 | u32 max_bsm_size; | |
621 | u32 ct_kill_threshold; /* value in hw-dependent units */ | |
be5d56ed | 622 | u32 calib_init_cfg; |
f0832f13 | 623 | const struct iwl_sensitivity_ranges *sens; |
5d08cd1d CH |
624 | }; |
625 | ||
5d08cd1d | 626 | |
5d08cd1d CH |
627 | /****************************************************************************** |
628 | * | |
a33c2f47 EG |
629 | * Functions implemented in core module which are forward declared here |
630 | * for use by iwl-[4-5].c | |
5d08cd1d | 631 | * |
a33c2f47 EG |
632 | * NOTE: The implementation of these functions are not hardware specific |
633 | * which is why they are in the core module files. | |
5d08cd1d CH |
634 | * |
635 | * Naming convention -- | |
a33c2f47 | 636 | * iwl_ <-- Is part of iwlwifi |
5d08cd1d | 637 | * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX) |
bb8c093b CH |
638 | * iwl4965_bg_ <-- Called from work queue context |
639 | * iwl4965_mac_ <-- mac80211 callback | |
5d08cd1d CH |
640 | * |
641 | ****************************************************************************/ | |
5b9f8cd3 EG |
642 | extern void iwl_update_chain_flags(struct iwl_priv *priv); |
643 | extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src); | |
a33c2f47 | 644 | extern const u8 iwl_bcast_addr[ETH_ALEN]; |
b3bbacb7 | 645 | extern int iwl_rxq_stop(struct iwl_priv *priv); |
da1bc453 | 646 | extern void iwl_txq_ctx_stop(struct iwl_priv *priv); |
443cfd45 | 647 | extern int iwl_queue_space(const struct iwl_queue *q); |
fd4abac5 TW |
648 | static inline int iwl_queue_used(const struct iwl_queue *q, int i) |
649 | { | |
650 | return q->write_ptr > q->read_ptr ? | |
651 | (i >= q->read_ptr && i < q->write_ptr) : | |
652 | !(i < q->read_ptr && i >= q->write_ptr); | |
653 | } | |
654 | ||
655 | ||
656 | static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge) | |
657 | { | |
658 | /* This is for scan command, the big buffer at end of command array */ | |
659 | if (is_huge) | |
660 | return q->n_window; /* must be power of 2 */ | |
661 | ||
662 | /* Otherwise, use normal size buffers */ | |
663 | return index & (q->n_window - 1); | |
664 | } | |
665 | ||
666 | ||
4ddbb7d0 TW |
667 | struct iwl_dma_ptr { |
668 | dma_addr_t dma; | |
669 | void *addr; | |
b481de9c ZY |
670 | size_t size; |
671 | }; | |
672 | ||
34c22cf9 WT |
673 | #define HT_SHORT_GI_20MHZ (1 << 0) |
674 | #define HT_SHORT_GI_40MHZ (1 << 1) | |
675 | ||
b481de9c ZY |
676 | #define IWL_CHANNEL_WIDTH_20MHZ 0 |
677 | #define IWL_CHANNEL_WIDTH_40MHZ 1 | |
678 | ||
b481de9c ZY |
679 | #define IWL_OPERATION_MODE_AUTO 0 |
680 | #define IWL_OPERATION_MODE_HT_ONLY 1 | |
681 | #define IWL_OPERATION_MODE_MIXED 2 | |
682 | #define IWL_OPERATION_MODE_20MHZ 3 | |
683 | ||
3195cdb7 TW |
684 | #define IWL_TX_CRC_SIZE 4 |
685 | #define IWL_TX_DELIMITER_SIZE 4 | |
b481de9c | 686 | |
b481de9c | 687 | #define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000 |
b481de9c | 688 | |
b481de9c | 689 | /* Sensitivity and chain noise calibration */ |
b481de9c ZY |
690 | #define INITIALIZATION_VALUE 0xFFFF |
691 | #define CAL_NUM_OF_BEACONS 20 | |
692 | #define MAXIMUM_ALLOWED_PATHLOSS 15 | |
693 | ||
b481de9c ZY |
694 | #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3 |
695 | ||
696 | #define MAX_FA_OFDM 50 | |
697 | #define MIN_FA_OFDM 5 | |
698 | #define MAX_FA_CCK 50 | |
699 | #define MIN_FA_CCK 5 | |
700 | ||
b481de9c ZY |
701 | #define AUTO_CORR_STEP_OFDM 1 |
702 | ||
b481de9c ZY |
703 | #define AUTO_CORR_STEP_CCK 3 |
704 | #define AUTO_CORR_MAX_TH_CCK 160 | |
705 | ||
b481de9c ZY |
706 | #define NRG_DIFF 2 |
707 | #define NRG_STEP_CCK 2 | |
708 | #define NRG_MARGIN 8 | |
709 | #define MAX_NUMBER_CCK_NO_FA 100 | |
710 | ||
711 | #define AUTO_CORR_CCK_MIN_VAL_DEF (125) | |
712 | ||
713 | #define CHAIN_A 0 | |
714 | #define CHAIN_B 1 | |
715 | #define CHAIN_C 2 | |
716 | #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4 | |
717 | #define ALL_BAND_FILTER 0xFF00 | |
718 | #define IN_BAND_FILTER 0xFF | |
719 | #define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF | |
720 | ||
3195cdb7 TW |
721 | #define NRG_NUM_PREV_STAT_L 20 |
722 | #define NUM_RX_CHAINS 3 | |
723 | ||
bb8c093b | 724 | enum iwl4965_false_alarm_state { |
b481de9c ZY |
725 | IWL_FA_TOO_MANY = 0, |
726 | IWL_FA_TOO_FEW = 1, | |
727 | IWL_FA_GOOD_RANGE = 2, | |
728 | }; | |
729 | ||
bb8c093b | 730 | enum iwl4965_chain_noise_state { |
b481de9c | 731 | IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */ |
04816448 GE |
732 | IWL_CHAIN_NOISE_ACCUMULATE, |
733 | IWL_CHAIN_NOISE_CALIBRATED, | |
734 | IWL_CHAIN_NOISE_DONE, | |
b481de9c ZY |
735 | }; |
736 | ||
bb8c093b | 737 | enum iwl4965_calib_enabled_state { |
b481de9c ZY |
738 | IWL_CALIB_DISABLED = 0, /* must be 0 */ |
739 | IWL_CALIB_ENABLED = 1, | |
740 | }; | |
741 | ||
f69f42a6 TW |
742 | |
743 | /* | |
744 | * enum iwl_calib | |
745 | * defines the order in which results of initial calibrations | |
746 | * should be sent to the runtime uCode | |
747 | */ | |
748 | enum iwl_calib { | |
749 | IWL_CALIB_XTAL, | |
819500c5 | 750 | IWL_CALIB_DC, |
f69f42a6 TW |
751 | IWL_CALIB_LO, |
752 | IWL_CALIB_TX_IQ, | |
753 | IWL_CALIB_TX_IQ_PERD, | |
201706ac | 754 | IWL_CALIB_BASE_BAND, |
f69f42a6 TW |
755 | IWL_CALIB_MAX |
756 | }; | |
757 | ||
6e21f2c1 TW |
758 | /* Opaque calibration results */ |
759 | struct iwl_calib_result { | |
760 | void *buf; | |
761 | size_t buf_len; | |
7c616cba TW |
762 | }; |
763 | ||
dbb983b7 RR |
764 | enum ucode_type { |
765 | UCODE_NONE = 0, | |
766 | UCODE_INIT, | |
767 | UCODE_RT | |
768 | }; | |
769 | ||
b481de9c | 770 | /* Sensitivity calib data */ |
f0832f13 | 771 | struct iwl_sensitivity_data { |
b481de9c ZY |
772 | u32 auto_corr_ofdm; |
773 | u32 auto_corr_ofdm_mrc; | |
774 | u32 auto_corr_ofdm_x1; | |
775 | u32 auto_corr_ofdm_mrc_x1; | |
776 | u32 auto_corr_cck; | |
777 | u32 auto_corr_cck_mrc; | |
778 | ||
779 | u32 last_bad_plcp_cnt_ofdm; | |
780 | u32 last_fa_cnt_ofdm; | |
781 | u32 last_bad_plcp_cnt_cck; | |
782 | u32 last_fa_cnt_cck; | |
783 | ||
784 | u32 nrg_curr_state; | |
785 | u32 nrg_prev_state; | |
786 | u32 nrg_value[10]; | |
787 | u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L]; | |
788 | u32 nrg_silence_ref; | |
789 | u32 nrg_energy_idx; | |
790 | u32 nrg_silence_idx; | |
791 | u32 nrg_th_cck; | |
792 | s32 nrg_auto_corr_silence_diff; | |
793 | u32 num_in_cck_no_fa; | |
794 | u32 nrg_th_ofdm; | |
b481de9c ZY |
795 | }; |
796 | ||
797 | /* Chain noise (differential Rx gain) calib data */ | |
f0832f13 | 798 | struct iwl_chain_noise_data { |
04816448 | 799 | u32 active_chains; |
b481de9c ZY |
800 | u32 chain_noise_a; |
801 | u32 chain_noise_b; | |
802 | u32 chain_noise_c; | |
803 | u32 chain_signal_a; | |
804 | u32 chain_signal_b; | |
805 | u32 chain_signal_c; | |
04816448 | 806 | u16 beacon_count; |
b481de9c ZY |
807 | u8 disconn_array[NUM_RX_CHAINS]; |
808 | u8 delta_gain_code[NUM_RX_CHAINS]; | |
809 | u8 radio_write; | |
04816448 | 810 | u8 state; |
b481de9c ZY |
811 | }; |
812 | ||
abceddb4 BC |
813 | #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */ |
814 | #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ | |
b481de9c | 815 | |
5d08cd1d | 816 | |
5d08cd1d CH |
817 | enum { |
818 | MEASUREMENT_READY = (1 << 0), | |
819 | MEASUREMENT_ACTIVE = (1 << 1), | |
820 | }; | |
821 | ||
a83b9141 WYG |
822 | /* interrupt statistics */ |
823 | struct isr_statistics { | |
824 | u32 hw; | |
825 | u32 sw; | |
826 | u32 sw_err; | |
827 | u32 sch; | |
828 | u32 alive; | |
829 | u32 rfkill; | |
830 | u32 ctkill; | |
831 | u32 wakeup; | |
832 | u32 rx; | |
833 | u32 rx_handlers[REPLY_MAX]; | |
834 | u32 tx; | |
835 | u32 unhandled; | |
836 | }; | |
5d08cd1d | 837 | |
dfe7d458 RR |
838 | #define IWL_MAX_NUM_QUEUES 20 /* FIXME: do dynamic allocation */ |
839 | ||
c79dd5b5 | 840 | struct iwl_priv { |
5d08cd1d CH |
841 | |
842 | /* ieee device used by generic ieee processing code */ | |
843 | struct ieee80211_hw *hw; | |
844 | struct ieee80211_channel *ieee_channels; | |
845 | struct ieee80211_rate *ieee_rates; | |
82b9a121 | 846 | struct iwl_cfg *cfg; |
5d08cd1d CH |
847 | |
848 | /* temporary frame storage list */ | |
849 | struct list_head free_frames; | |
850 | int frames_count; | |
851 | ||
8318d78a | 852 | enum ieee80211_band band; |
5d08cd1d CH |
853 | int alloc_rxb_skb; |
854 | ||
c79dd5b5 | 855 | void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv, |
a55360e4 | 856 | struct iwl_rx_mem_buffer *rxb); |
5d08cd1d | 857 | |
8318d78a | 858 | struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; |
5d08cd1d | 859 | |
80bc5393 | 860 | #if defined(CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT) || defined(CONFIG_IWL3945_SPECTRUM_MEASUREMENT) |
5d08cd1d | 861 | /* spectrum measurement report caching */ |
2aa6ab86 | 862 | struct iwl_spectrum_notification measure_report; |
5d08cd1d CH |
863 | u8 measurement_status; |
864 | #endif | |
865 | /* ucode beacon time */ | |
866 | u32 ucode_beacon_time; | |
867 | ||
bb8c093b | 868 | /* we allocate array of iwl4965_channel_info for NIC's valid channels. |
5d08cd1d | 869 | * Access via channel # using indirect index array */ |
bf85ea4f | 870 | struct iwl_channel_info *channel_info; /* channel info array */ |
5d08cd1d CH |
871 | u8 channel_count; /* # of channels */ |
872 | ||
85d41495 KA |
873 | /* each calibration channel group in the EEPROM has a derived |
874 | * clip setting for each rate. 3945 only.*/ | |
875 | const struct iwl3945_clip_group clip39_groups[5]; | |
876 | ||
5d08cd1d CH |
877 | /* thermal calibration */ |
878 | s32 temperature; /* degrees Kelvin */ | |
879 | s32 last_temperature; | |
880 | ||
7c616cba | 881 | /* init calibration results */ |
6e21f2c1 | 882 | struct iwl_calib_result calib_results[IWL_CALIB_MAX]; |
7c616cba | 883 | |
5d08cd1d CH |
884 | /* Scan related variables */ |
885 | unsigned long last_scan_jiffies; | |
7878a5a4 | 886 | unsigned long next_scan_jiffies; |
5d08cd1d CH |
887 | unsigned long scan_start; |
888 | unsigned long scan_pass_start; | |
889 | unsigned long scan_start_tsf; | |
805cee5b | 890 | void *scan; |
5d08cd1d CH |
891 | int scan_bands; |
892 | int one_direct_scan; | |
893 | u8 direct_ssid_len; | |
894 | u8 direct_ssid[IW_ESSID_MAX_SIZE]; | |
76eff18b TW |
895 | u8 scan_tx_ant[IEEE80211_NUM_BANDS]; |
896 | u8 mgmt_tx_ant; | |
5d08cd1d CH |
897 | |
898 | /* spinlock */ | |
899 | spinlock_t lock; /* protect general shared data */ | |
900 | spinlock_t hcmd_lock; /* protect hcmd */ | |
901 | struct mutex mutex; | |
902 | ||
903 | /* basic pci-network driver stuff */ | |
904 | struct pci_dev *pci_dev; | |
905 | ||
906 | /* pci hardware address support */ | |
907 | void __iomem *hw_base; | |
b661c819 TW |
908 | u32 hw_rev; |
909 | u32 hw_wa_rev; | |
910 | u8 rev_id; | |
5d08cd1d CH |
911 | |
912 | /* uCode images, save to reload in case of failure */ | |
c02b3acd CR |
913 | u32 ucode_ver; /* version of ucode, copy of |
914 | iwl_ucode.ver */ | |
5d08cd1d CH |
915 | struct fw_desc ucode_code; /* runtime inst */ |
916 | struct fw_desc ucode_data; /* runtime data original */ | |
917 | struct fw_desc ucode_data_backup; /* runtime data save/restore */ | |
918 | struct fw_desc ucode_init; /* initialization inst */ | |
919 | struct fw_desc ucode_init_data; /* initialization data */ | |
920 | struct fw_desc ucode_boot; /* bootstrap inst */ | |
dbb983b7 RR |
921 | enum ucode_type ucode_type; |
922 | u8 ucode_write_complete; /* the image write is complete */ | |
5d08cd1d CH |
923 | |
924 | ||
3195c1f3 | 925 | struct iwl_rxon_time_cmd rxon_timing; |
5d08cd1d CH |
926 | |
927 | /* We declare this const so it can only be | |
928 | * changed via explicit cast within the | |
929 | * routines that actually update the physical | |
930 | * hardware */ | |
c1adf9fb GG |
931 | const struct iwl_rxon_cmd active_rxon; |
932 | struct iwl_rxon_cmd staging_rxon; | |
5d08cd1d CH |
933 | |
934 | int error_recovering; | |
c1adf9fb | 935 | struct iwl_rxon_cmd recovery_rxon; |
5d08cd1d CH |
936 | |
937 | /* 1st responses from initialize and runtime uCode images. | |
938 | * 4965's initialize alive response contains some calibration data. */ | |
885ba202 TW |
939 | struct iwl_init_alive_resp card_alive_init; |
940 | struct iwl_alive_resp card_alive; | |
80bc5393 | 941 | #if defined(CONFIG_IWLWIFI_RFKILL) |
80fcc9e2 | 942 | struct rfkill *rfkill; |
ad97edd2 | 943 | #endif |
5d08cd1d | 944 | |
5c8df2d5 | 945 | #ifdef CONFIG_IWLWIFI_LEDS |
ab53d8af MA |
946 | unsigned long last_blink_time; |
947 | u8 last_blink_rate; | |
948 | u8 allow_blinking; | |
949 | u64 led_tpt; | |
4a8a4322 | 950 | struct iwl_led led[IWL_LED_TRG_MAX]; |
4a8a4322 AK |
951 | unsigned int rxtxpackets; |
952 | #endif | |
5d08cd1d CH |
953 | u16 active_rate; |
954 | u16 active_rate_basic; | |
955 | ||
5d08cd1d | 956 | u8 assoc_station_added; |
5d08cd1d | 957 | u8 start_calib; |
f0832f13 EG |
958 | struct iwl_sensitivity_data sensitivity_data; |
959 | struct iwl_chain_noise_data chain_noise_data; | |
5d08cd1d | 960 | __le16 sensitivity_tbl[HD_TABLE_SIZE]; |
5d08cd1d | 961 | |
9e0cc6de | 962 | struct iwl_ht_info current_ht_config; |
5d08cd1d CH |
963 | u8 last_phy_res[100]; |
964 | ||
5d08cd1d CH |
965 | /* Rate scaling data */ |
966 | s8 data_retry_limit; | |
967 | u8 retry_rate; | |
968 | ||
969 | wait_queue_head_t wait_command_queue; | |
970 | ||
971 | int activity_timer_active; | |
972 | ||
973 | /* Rx and Tx DMA processing queues */ | |
a55360e4 | 974 | struct iwl_rx_queue rxq; |
16466903 | 975 | struct iwl_tx_queue txq[IWL_MAX_NUM_QUEUES]; |
5d08cd1d | 976 | unsigned long txq_ctx_active_msk; |
4ddbb7d0 TW |
977 | struct iwl_dma_ptr kw; /* keep warm address */ |
978 | struct iwl_dma_ptr scd_bc_tbls; | |
979 | ||
5d08cd1d CH |
980 | u32 scd_base_addr; /* scheduler sram base address */ |
981 | ||
982 | unsigned long status; | |
5d08cd1d | 983 | |
a96a27f9 | 984 | int last_rx_rssi; /* From Rx packet statistics */ |
5d08cd1d CH |
985 | int last_rx_noise; /* From beacon statistics */ |
986 | ||
19758bef TW |
987 | /* counts mgmt, ctl, and data packets */ |
988 | struct traffic_stats { | |
989 | u32 cnt; | |
990 | u64 bytes; | |
991 | } tx_stats[3], rx_stats[3]; | |
992 | ||
a83b9141 WYG |
993 | /* counts interrupts */ |
994 | struct isr_statistics isr_stats; | |
995 | ||
5da4b55f | 996 | struct iwl_power_mgr power_data; |
5d08cd1d | 997 | |
8f91aecb | 998 | struct iwl_notif_statistics statistics; |
5d08cd1d CH |
999 | unsigned long last_statistics_time; |
1000 | ||
1001 | /* context information */ | |
5d08cd1d CH |
1002 | u16 rates_mask; |
1003 | ||
1004 | u32 power_mode; | |
5d08cd1d CH |
1005 | u8 bssid[ETH_ALEN]; |
1006 | u16 rts_threshold; | |
1007 | u8 mac_addr[ETH_ALEN]; | |
1008 | ||
1009 | /*station table variables */ | |
1010 | spinlock_t sta_lock; | |
1011 | int num_stations; | |
6def9761 | 1012 | struct iwl_station_entry stations[IWL_STATION_COUNT]; |
6974e363 EG |
1013 | struct iwl_wep_key wep_keys[WEP_KEYS_MAX]; |
1014 | u8 default_wep_key; | |
1015 | u8 key_mapping_key; | |
80fb47a1 | 1016 | unsigned long ucode_key_table; |
5d08cd1d | 1017 | |
e4e72fb4 JB |
1018 | /* queue refcounts */ |
1019 | #define IWL_MAX_HW_QUEUES 32 | |
1020 | unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; | |
1021 | /* for each AC */ | |
1022 | atomic_t queue_stop_count[4]; | |
1023 | ||
5d08cd1d | 1024 | /* Indication if ieee80211_ops->open has been called */ |
69dc5d9d | 1025 | u8 is_open; |
5d08cd1d CH |
1026 | |
1027 | u8 mac80211_registered; | |
5d08cd1d | 1028 | |
5d08cd1d CH |
1029 | /* Rx'd packet timing information */ |
1030 | u32 last_beacon_time; | |
1031 | u64 last_tsf; | |
1032 | ||
5d08cd1d | 1033 | /* eeprom */ |
073d3f5f TW |
1034 | u8 *eeprom; |
1035 | struct iwl_eeprom_calib_info *calib_info; | |
5d08cd1d | 1036 | |
05c914fe | 1037 | enum nl80211_iftype iw_mode; |
5d08cd1d CH |
1038 | |
1039 | struct sk_buff *ibss_beacon; | |
1040 | ||
1041 | /* Last Rx'd beacon timestamp */ | |
3109ece1 | 1042 | u64 timestamp; |
5d08cd1d | 1043 | u16 beacon_int; |
32bfd35d | 1044 | struct ieee80211_vif *vif; |
5d08cd1d | 1045 | |
8cd812bc | 1046 | /*Added for 3945 */ |
3832ec9d AK |
1047 | void *shared_virt; |
1048 | dma_addr_t shared_phys; | |
1049 | /*End*/ | |
5425e490 | 1050 | struct iwl_hw_params hw_params; |
4ddbb7d0 | 1051 | |
059ff826 | 1052 | |
5d08cd1d CH |
1053 | /* Current association information needed to configure the |
1054 | * hardware */ | |
1055 | u16 assoc_id; | |
1056 | u16 assoc_capability; | |
5d08cd1d | 1057 | |
1ff50bda | 1058 | struct iwl_qos_info qos_data; |
5d08cd1d CH |
1059 | |
1060 | struct workqueue_struct *workqueue; | |
1061 | ||
1062 | struct work_struct up; | |
1063 | struct work_struct restart; | |
1064 | struct work_struct calibrated_work; | |
1065 | struct work_struct scan_completed; | |
1066 | struct work_struct rx_replenish; | |
1067 | struct work_struct rf_kill; | |
1068 | struct work_struct abort_scan; | |
1069 | struct work_struct update_link_led; | |
1070 | struct work_struct auth_work; | |
1071 | struct work_struct report_work; | |
1072 | struct work_struct request_scan; | |
1073 | struct work_struct beacon_update; | |
1074 | ||
1075 | struct tasklet_struct irq_tasklet; | |
1076 | ||
c90a74ba | 1077 | struct delayed_work set_power_save; |
5d08cd1d CH |
1078 | struct delayed_work init_alive_start; |
1079 | struct delayed_work alive_start; | |
5d08cd1d | 1080 | struct delayed_work scan_check; |
4a8a4322 AK |
1081 | |
1082 | /*For 3945 only*/ | |
1083 | struct delayed_work thermal_periodic; | |
2663516d | 1084 | struct delayed_work rfkill_poll; |
4a8a4322 | 1085 | |
630fe9b6 TW |
1086 | /* TX Power */ |
1087 | s8 tx_power_user_lmt; | |
1088 | s8 tx_power_channel_lmt; | |
5d08cd1d | 1089 | |
5d08cd1d | 1090 | |
d08853a3 | 1091 | #ifdef CONFIG_IWLWIFI_DEBUG |
5d08cd1d | 1092 | /* debugging info */ |
bf403db8 | 1093 | u32 debug_level; |
5d08cd1d CH |
1094 | u32 framecnt_to_us; |
1095 | atomic_t restrict_refcnt; | |
712b6cf5 TW |
1096 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1097 | /* debugfs */ | |
1098 | struct iwl_debugfs *dbgfs; | |
1099 | #endif /* CONFIG_IWLWIFI_DEBUGFS */ | |
1100 | #endif /* CONFIG_IWLWIFI_DEBUG */ | |
5d08cd1d CH |
1101 | |
1102 | struct work_struct txpower_work; | |
445c2dff TW |
1103 | u32 disable_sens_cal; |
1104 | u32 disable_chain_noise_cal; | |
203566f3 | 1105 | u32 disable_tx_power_cal; |
16e727e8 | 1106 | struct work_struct run_time_calib_work; |
5d08cd1d | 1107 | struct timer_list statistics_periodic; |
4a8a4322 AK |
1108 | |
1109 | /*For 3945*/ | |
1110 | #define IWL_DEFAULT_TX_POWER 0x0F | |
4a8a4322 | 1111 | |
4a8a4322 AK |
1112 | struct iwl3945_notif_statistics statistics_39; |
1113 | ||
1114 | struct iwl3945_station_entry stations_39[IWL_STATION_COUNT]; | |
1115 | ||
4a8a4322 | 1116 | u32 sta_supp_rates; |
c79dd5b5 | 1117 | }; /*iwl_priv */ |
5d08cd1d | 1118 | |
36470749 RR |
1119 | static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id) |
1120 | { | |
1121 | set_bit(txq_id, &priv->txq_ctx_active_msk); | |
1122 | } | |
1123 | ||
1124 | static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id) | |
1125 | { | |
1126 | clear_bit(txq_id, &priv->txq_ctx_active_msk); | |
1127 | } | |
1128 | ||
994d31f7 | 1129 | #ifdef CONFIG_IWLWIFI_DEBUG |
a332f8d6 TW |
1130 | const char *iwl_get_tx_fail_reason(u32 status); |
1131 | #else | |
1132 | static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; } | |
1133 | #endif | |
1134 | ||
1135 | ||
a332f8d6 TW |
1136 | static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv, |
1137 | int txq_id, int idx) | |
1138 | { | |
1139 | if (priv->txq[txq_id].txb[idx].skb[0]) | |
1140 | return (struct ieee80211_hdr *)priv->txq[txq_id]. | |
1141 | txb[idx].skb[0]->data; | |
1142 | return NULL; | |
1143 | } | |
a332f8d6 TW |
1144 | |
1145 | ||
3109ece1 | 1146 | static inline int iwl_is_associated(struct iwl_priv *priv) |
5d08cd1d CH |
1147 | { |
1148 | return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0; | |
1149 | } | |
1150 | ||
bf85ea4f | 1151 | static inline int is_channel_valid(const struct iwl_channel_info *ch_info) |
5d08cd1d CH |
1152 | { |
1153 | if (ch_info == NULL) | |
1154 | return 0; | |
1155 | return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0; | |
1156 | } | |
1157 | ||
bf85ea4f | 1158 | static inline int is_channel_radar(const struct iwl_channel_info *ch_info) |
5d08cd1d CH |
1159 | { |
1160 | return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0; | |
1161 | } | |
1162 | ||
bf85ea4f | 1163 | static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info) |
5d08cd1d | 1164 | { |
8318d78a | 1165 | return ch_info->band == IEEE80211_BAND_5GHZ; |
5d08cd1d CH |
1166 | } |
1167 | ||
bf85ea4f | 1168 | static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info) |
5d08cd1d | 1169 | { |
8318d78a | 1170 | return ch_info->band == IEEE80211_BAND_2GHZ; |
5d08cd1d CH |
1171 | } |
1172 | ||
bf85ea4f | 1173 | static inline int is_channel_passive(const struct iwl_channel_info *ch) |
5d08cd1d CH |
1174 | { |
1175 | return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0; | |
1176 | } | |
1177 | ||
bf85ea4f | 1178 | static inline int is_channel_ibss(const struct iwl_channel_info *ch) |
5d08cd1d CH |
1179 | { |
1180 | return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0; | |
1181 | } | |
1182 | ||
be1f3ab6 | 1183 | #endif /* __iwl_dev_h__ */ |