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[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
b481de9c
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 * Please use iwl-4965-hw.h for hardware-related definitions.
30 */
31
be1f3ab6
EG
32#ifndef __iwl_dev_h__
33#define __iwl_dev_h__
b481de9c 34
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
37#include <net/ieee80211_radiotap.h>
38
6bc913bd 39#include "iwl-eeprom.h"
6f83eaa1 40#include "iwl-csr.h"
5d08cd1d 41#include "iwl-prph.h"
dbb6654c 42#include "iwl-fh.h"
0a6857e7 43#include "iwl-debug.h"
dbb6654c
WT
44#include "iwl-4965-hw.h"
45#include "iwl-3945-hw.h"
b744cb79 46#include "iwl-agn-hw.h"
ab53d8af 47#include "iwl-led.h"
5da4b55f 48#include "iwl-power.h"
e227ceac 49#include "iwl-agn-rs.h"
5d08cd1d 50
672639de
WYG
51struct iwl_tx_queue;
52
099b40b7 53/* CT-KILL constants */
672639de
WYG
54#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
55#define CT_KILL_THRESHOLD 114 /* in Celsius */
56#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 57
5d08cd1d
CH
58/* Default noise level to report when noise measurement is not available.
59 * This may be because we're:
60 * 1) Not associated (4965, no beacon statistics being sent to driver)
61 * 2) Scanning (noise measurement does not apply to associated channel)
62 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
63 * Use default noise value of -127 ... this is below the range of measurable
64 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
65 * Also, -127 works better than 0 when averaging frames with/without
66 * noise info (e.g. averaging might be done in app); measured dBm values are
67 * always negative ... using a negative value as the default keeps all
68 * averages within an s8's (used in some apps) range of negative values. */
69#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
70
5d08cd1d
CH
71/*
72 * RTS threshold here is total size [2347] minus 4 FCS bytes
73 * Per spec:
74 * a value of 0 means RTS on all data/management packets
75 * a value > max MSDU size means no RTS
76 * else RTS for data/management frames where MPDU is larger
77 * than RTS value.
78 */
79#define DEFAULT_RTS_THRESHOLD 2347U
80#define MIN_RTS_THRESHOLD 0U
81#define MAX_RTS_THRESHOLD 2347U
82#define MAX_MSDU_SIZE 2304U
83#define MAX_MPDU_SIZE 2346U
84#define DEFAULT_BEACON_INTERVAL 100U
85#define DEFAULT_SHORT_RETRY_LIMIT 7U
86#define DEFAULT_LONG_RETRY_LIMIT 4U
87
a55360e4 88struct iwl_rx_mem_buffer {
2f301227
ZY
89 dma_addr_t page_dma;
90 struct page *page;
5d08cd1d
CH
91 struct list_head list;
92};
93
2f301227
ZY
94#define rxb_addr(r) page_address(r->page)
95
c2acea8e
JB
96/* defined below */
97struct iwl_device_cmd;
98
99struct iwl_cmd_meta {
100 /* only for SYNC commands, iff the reply skb is wanted */
101 struct iwl_host_cmd *source;
102 /*
103 * only for ASYNC commands
104 * (which is somewhat stupid -- look at iwl-sta.c for instance
105 * which duplicates a bunch of code because the callback isn't
106 * invoked for SYNC commands, if it were and its result passed
107 * through it would be simpler...)
108 */
5696aea6
JB
109 void (*callback)(struct iwl_priv *priv,
110 struct iwl_device_cmd *cmd,
2f301227 111 struct iwl_rx_packet *pkt);
c2acea8e
JB
112
113 /* The CMD_SIZE_HUGE flag bit indicates that the command
114 * structure is stored at the end of the shared queue memory. */
115 u32 flags;
116
2e724443
FT
117 DEFINE_DMA_UNMAP_ADDR(mapping);
118 DEFINE_DMA_UNMAP_LEN(len);
c2acea8e
JB
119};
120
5d08cd1d
CH
121/*
122 * Generic queue structure
123 *
124 * Contains common data for Rx and Tx queues
125 */
443cfd45 126struct iwl_queue {
5d08cd1d
CH
127 int n_bd; /* number of BDs in this queue */
128 int write_ptr; /* 1-st empty entry (index) host_w*/
129 int read_ptr; /* last used entry (index) host_r*/
b74e31a9
WYG
130 /* use for monitoring and recovering the stuck queue */
131 int last_read_ptr; /* storing the last read_ptr */
132 /* number of time read_ptr and last_read_ptr are the same */
133 u8 repeat_same_read_ptr;
5d08cd1d
CH
134 dma_addr_t dma_addr; /* physical addr for BD's */
135 int n_window; /* safe queue window */
136 u32 id;
137 int low_mark; /* low watermark, resume queue if free
138 * space more than this */
139 int high_mark; /* high watermark, stop queue if free
140 * space less than this */
ba2d3587 141} __packed;
5d08cd1d 142
bc47279f 143/* One for each TFD */
8567c63e 144struct iwl_tx_info {
ff0d91c3 145 struct sk_buff *skb;
5d08cd1d
CH
146};
147
148/**
16466903 149 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
150 * @q: generic Rx/Tx queue descriptor
151 * @bd: base of circular buffer of TFDs
c2acea8e
JB
152 * @cmd: array of command/TX buffer pointers
153 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
154 * @dma_addr_cmd: physical address of cmd/tx buffer array
155 * @txb: array of per-TFD driver data
156 * @need_update: indicates need to update read/write index
157 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 158 *
bc47279f
BC
159 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
160 * descriptors) and required locking structures.
5d08cd1d 161 */
188cf6c7
SO
162#define TFD_TX_CMD_SLOTS 256
163#define TFD_CMD_SLOTS 32
164
16466903 165struct iwl_tx_queue {
443cfd45 166 struct iwl_queue q;
59606ffa 167 void *tfds;
c2acea8e
JB
168 struct iwl_device_cmd **cmd;
169 struct iwl_cmd_meta *meta;
8567c63e 170 struct iwl_tx_info *txb;
3fd07a1e
TW
171 u8 need_update;
172 u8 sched_retry;
173 u8 active;
174 u8 swq_id;
5d08cd1d
CH
175};
176
177#define IWL_NUM_SCAN_RATES (2)
178
bb8c093b 179struct iwl4965_channel_tgd_info {
5d08cd1d
CH
180 u8 type;
181 s8 max_power;
182};
183
bb8c093b 184struct iwl4965_channel_tgh_info {
5d08cd1d
CH
185 s64 last_radar_time;
186};
187
d20b3c65
SO
188#define IWL4965_MAX_RATE (33)
189
85d41495
KA
190struct iwl3945_clip_group {
191 /* maximum power level to prevent clipping for each rate, derived by
192 * us from this band's saturation power in EEPROM */
193 const s8 clip_powers[IWL_MAX_RATES];
194};
195
d20b3c65
SO
196/* current Tx power values to use, one for each rate for each channel.
197 * requested power is limited by:
198 * -- regulatory EEPROM limits for this channel
199 * -- hardware capabilities (clip-powers)
200 * -- spectrum management
201 * -- user preference (e.g. iwconfig)
202 * when requested power is set, base power index must also be set. */
203struct iwl3945_channel_power_info {
204 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
205 s8 power_table_index; /* actual (compenst'd) index into gain table */
206 s8 base_power_index; /* gain index for power at factory temp. */
207 s8 requested_power; /* power (dBm) requested for this chnl/rate */
208};
209
210/* current scan Tx power values to use, one for each scan rate for each
211 * channel. */
212struct iwl3945_scan_power_info {
213 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
214 s8 power_table_index; /* actual (compenst'd) index into gain table */
215 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
216};
217
5d08cd1d
CH
218/*
219 * One for each channel, holds all channel setup data
220 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
221 * with one another!
222 */
bf85ea4f 223struct iwl_channel_info {
bb8c093b
CH
224 struct iwl4965_channel_tgd_info tgd;
225 struct iwl4965_channel_tgh_info tgh;
073d3f5f 226 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
227 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
228 * HT40 channel */
5d08cd1d
CH
229
230 u8 channel; /* channel number */
231 u8 flags; /* flags copied from EEPROM */
232 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 233 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
234 s8 min_power; /* always 0 */
235 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
236
237 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
238 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 239 enum ieee80211_band band;
5d08cd1d 240
7aafef1c
WYG
241 /* HT40 channel info */
242 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
243 u8 ht40_flags; /* flags copied from EEPROM */
244 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
d20b3c65
SO
245
246 /* Radio/DSP gain settings for each "normal" data Tx rate.
247 * These include, in addition to RF and DSP gain, a few fields for
248 * remembering/modifying gain settings (indexes). */
249 struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE];
250
251 /* Radio/DSP gain settings for each scan rate, for directed scans. */
252 struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
5d08cd1d
CH
253};
254
edc1a3a0
JB
255#define IWL_TX_FIFO_BK 0
256#define IWL_TX_FIFO_BE 1
257#define IWL_TX_FIFO_VI 2
258#define IWL_TX_FIFO_VO 3
259#define IWL_TX_FIFO_UNUSED -1
5d08cd1d 260
01a7e084
RC
261/* Minimum number of queues. MAX_NUM is defined in hw specific files.
262 * Set the minimum to accommodate the 4 standard TX queues, 1 command
263 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
264#define IWL_MIN_NUM_QUEUES 10
5d08cd1d 265
bd35f150 266/*
1a716557
JB
267 * Queue #4 is the command queue for 3945/4965/5x00/1000/6x00,
268 * the driver maps it into the appropriate device FIFO for the
269 * uCode.
bd35f150
WYG
270 */
271#define IWL_CMD_QUEUE_NUM 4
272
5d08cd1d
CH
273/* Power management (not Tx power) structures */
274
6f4083aa
TW
275enum iwl_pwr_src {
276 IWL_PWR_SRC_VMAIN,
277 IWL_PWR_SRC_VAUX,
278};
279
5d08cd1d
CH
280#define IEEE80211_DATA_LEN 2304
281#define IEEE80211_4ADDR_LEN 30
282#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
283#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
284
fcab423d 285struct iwl_frame {
5d08cd1d
CH
286 union {
287 struct ieee80211_hdr frame;
4bf64efd 288 struct iwl_tx_beacon_cmd beacon;
5d08cd1d
CH
289 u8 raw[IEEE80211_FRAME_LEN];
290 u8 cmd[360];
291 } u;
292 struct list_head list;
293};
294
5d08cd1d
CH
295#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
296#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
297#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
298
299enum {
c587de0b
TW
300 CMD_SYNC = 0,
301 CMD_SIZE_NORMAL = 0,
302 CMD_NO_SKB = 0,
5d08cd1d 303 CMD_SIZE_HUGE = (1 << 0),
5d08cd1d 304 CMD_ASYNC = (1 << 1),
5d08cd1d
CH
305 CMD_WANT_SKB = (1 << 2),
306};
307
c8c24872 308#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 309
bc47279f 310/**
c2acea8e 311 * struct iwl_device_cmd
bc47279f
BC
312 *
313 * For allocation of the command and tx queues, this establishes the overall
314 * size of the largest command we send to uCode, except for a scan command
315 * (which is relatively huge; space is allocated separately).
316 */
c2acea8e 317struct iwl_device_cmd {
857485c0 318 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 319 union {
5d08cd1d
CH
320 u32 flags;
321 u8 val8;
322 u16 val16;
323 u32 val32;
83d527d9 324 struct iwl_tx_cmd tx;
c8c24872
WYG
325 struct iwl6000_channel_switch_cmd chswitch;
326 u8 payload[DEF_CMD_PAYLOAD_SIZE];
ba2d3587
ED
327 } __packed cmd;
328} __packed;
5d08cd1d 329
c2acea8e
JB
330#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
331
3257e5d4 332
857485c0 333struct iwl_host_cmd {
5d08cd1d 334 const void *data;
2f301227 335 unsigned long reply_page;
5696aea6
JB
336 void (*callback)(struct iwl_priv *priv,
337 struct iwl_device_cmd *cmd,
2f301227 338 struct iwl_rx_packet *pkt);
c2acea8e
JB
339 u32 flags;
340 u16 len;
341 u8 id;
5d08cd1d
CH
342};
343
5d08cd1d
CH
344#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
345#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
346#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
347
348/**
a55360e4 349 * struct iwl_rx_queue - Rx queue
df833b1d 350 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
d5b25c90 351 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
352 * @read: Shared index to newest available Rx buffer
353 * @write: Shared index to oldest written Rx packet
354 * @free_count: Number of pre-allocated buffers in rx_free
355 * @rx_free: list of free SKBs for use
356 * @rx_used: List of Rx buffers with no SKB
357 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
358 * @rb_stts: driver's pointer to receive buffer status
359 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 360 *
a55360e4 361 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 362 */
a55360e4 363struct iwl_rx_queue {
5d08cd1d 364 __le32 *bd;
d5b25c90 365 dma_addr_t bd_dma;
a55360e4
TW
366 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
367 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
368 u32 read;
369 u32 write;
370 u32 free_count;
4752c93c 371 u32 write_actual;
5d08cd1d
CH
372 struct list_head rx_free;
373 struct list_head rx_used;
374 int need_update;
8d86422a
WT
375 struct iwl_rb_status *rb_stts;
376 dma_addr_t rb_stts_dma;
5d08cd1d
CH
377 spinlock_t lock;
378};
379
380#define IWL_SUPPORTED_RATES_IE_LEN 8
381
5d08cd1d
CH
382#define MAX_TID_COUNT 9
383
384#define IWL_INVALID_RATE 0xFF
385#define IWL_INVALID_VALUE -1
386
bc47279f 387/**
6def9761 388 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
389 * @txq_id: Tx queue used for Tx attempt
390 * @frame_count: # frames attempted by Tx command
391 * @wait_for_ba: Expect block-ack before next Tx reply
392 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
393 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
394 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
395 * @rate_n_flags: Rate at which Tx was attempted
396 *
397 * If REPLY_TX indicates that aggregation was attempted, driver must wait
398 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
399 * until block ack arrives.
400 */
6def9761 401struct iwl_ht_agg {
5d08cd1d
CH
402 u16 txq_id;
403 u16 frame_count;
404 u16 wait_for_ba;
405 u16 start_idx;
fe01b477 406 u64 bitmap;
5d08cd1d 407 u32 rate_n_flags;
fe01b477
RR
408#define IWL_AGG_OFF 0
409#define IWL_AGG_ON 1
410#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
411#define IWL_EMPTYING_HW_QUEUE_DELBA 3
412 u8 state;
5d08cd1d 413};
fe01b477 414
5d08cd1d 415
6def9761 416struct iwl_tid_data {
f862a236 417 u16 seq_number; /* agn only */
fe01b477 418 u16 tfds_in_queue;
6def9761 419 struct iwl_ht_agg agg;
5d08cd1d
CH
420};
421
6def9761 422struct iwl_hw_key {
5d08cd1d
CH
423 enum ieee80211_key_alg alg;
424 int keylen;
0211ddda 425 u8 keyidx;
5d08cd1d
CH
426 u8 key[32];
427};
428
a78fe754 429union iwl_ht_rate_supp {
5d08cd1d
CH
430 u16 rates;
431 struct {
432 u8 siso_rate;
433 u8 mimo_rate;
434 };
435};
436
5d08cd1d 437#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
bcc693a1
WYG
438
439/*
440 * Maximal MPDU density for TX aggregation
441 * 4 - 2us density
442 * 5 - 4us density
443 * 6 - 8us density
444 * 7 - 16us density
445 */
446#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
447#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
5d08cd1d 448
fad95bf5 449struct iwl_ht_config {
9e0cc6de 450 /* self configuration data */
c812ee24
JB
451 bool is_ht;
452 bool is_40mhz;
02bb1bea 453 bool single_chain_sufficient;
ba37a3d0 454 enum ieee80211_smps_mode smps; /* current smps mode */
9e0cc6de 455 /* BSS related data */
5d08cd1d 456 u8 extension_chan_offset;
9e0cc6de
RR
457 u8 ht_protection;
458 u8 non_GF_STA_present;
5d08cd1d 459};
5d08cd1d 460
5d08cd1d 461/* QoS structures */
1ff50bda 462struct iwl_qos_info {
5d08cd1d 463 int qos_active;
1ff50bda 464 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 465};
5d08cd1d 466
fe6b23dd
RC
467/*
468 * Structure should be accessed with sta_lock held. When station addition
469 * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only
470 * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock
471 * held.
472 */
6def9761 473struct iwl_station_entry {
133636de 474 struct iwl_addsta_cmd sta;
6def9761 475 struct iwl_tid_data tid[MAX_TID_COUNT];
5d08cd1d 476 u8 used;
6def9761 477 struct iwl_hw_key keyinfo;
fe6b23dd 478 struct iwl_link_quality_cmd *lq;
5d08cd1d
CH
479};
480
fd1af15d
JB
481struct iwl_station_priv_common {
482 u8 sta_id;
483};
484
8d9698b3
RC
485/*
486 * iwl_station_priv: Driver's private station information
487 *
488 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
489 * in the structure for use by driver. This structure is places in that
490 * space.
fd1af15d
JB
491 *
492 * The common struct MUST be first because it is shared between
493 * 3945 and agn!
8d9698b3
RC
494 */
495struct iwl_station_priv {
fd1af15d 496 struct iwl_station_priv_common common;
8d9698b3 497 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
498 atomic_t pending_frames;
499 bool client;
500 bool asleep;
8d9698b3
RC
501};
502
fd1af15d
JB
503/**
504 * struct iwl_vif_priv - driver's private per-interface information
505 *
506 * When mac80211 allocates a virtual interface, it can allocate
507 * space for us to put data into.
508 */
509struct iwl_vif_priv {
510 u8 ibss_bssid_sta_id;
511};
512
5d08cd1d
CH
513/* one for each uCode image (inst/data, boot/init/runtime) */
514struct fw_desc {
515 void *v_addr; /* access by driver */
516 dma_addr_t p_addr; /* access by card's busmaster DMA */
517 u32 len; /* bytes */
518};
519
dd7a2509 520/* v1/v2 uCode file layout */
cc0f555d
JS
521struct iwl_ucode_header {
522 __le32 ver; /* major/minor/API/serial */
523 union {
524 struct {
525 __le32 inst_size; /* bytes of runtime code */
526 __le32 data_size; /* bytes of runtime data */
527 __le32 init_size; /* bytes of init code */
528 __le32 init_data_size; /* bytes of init data */
529 __le32 boot_size; /* bytes of bootstrap code */
530 u8 data[0]; /* in same order as sizes */
531 } v1;
532 struct {
533 __le32 build; /* build number */
534 __le32 inst_size; /* bytes of runtime code */
535 __le32 data_size; /* bytes of runtime data */
536 __le32 init_size; /* bytes of init code */
537 __le32 init_data_size; /* bytes of init data */
538 __le32 boot_size; /* bytes of bootstrap code */
539 u8 data[0]; /* in same order as sizes */
540 } v2;
541 } u;
5d08cd1d
CH
542};
543
dd7a2509
JB
544/*
545 * new TLV uCode file layout
546 *
547 * The new TLV file format contains TLVs, that each specify
548 * some piece of data. To facilitate "groups", for example
549 * different instruction image with different capabilities,
550 * bundled with the same init image, an alternative mechanism
551 * is provided:
552 * When the alternative field is 0, that means that the item
553 * is always valid. When it is non-zero, then it is only
554 * valid in conjunction with items of the same alternative,
555 * in which case the driver (user) selects one alternative
556 * to use.
557 */
558
559enum iwl_ucode_tlv_type {
560 IWL_UCODE_TLV_INVALID = 0, /* unused */
561 IWL_UCODE_TLV_INST = 1,
562 IWL_UCODE_TLV_DATA = 2,
563 IWL_UCODE_TLV_INIT = 3,
564 IWL_UCODE_TLV_INIT_DATA = 4,
565 IWL_UCODE_TLV_BOOT = 5,
566 IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */
b2e640d4
JB
567 IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
568 IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
569 IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
570 IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11,
571 IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
572 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
c8312fac 573 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
6a822d06 574 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
dd7a2509
JB
575};
576
577struct iwl_ucode_tlv {
578 __le16 type; /* see above */
579 __le16 alternative; /* see comment */
580 __le32 length; /* not including type/length fields */
581 u8 data[0];
ba2d3587 582} __packed;
dd7a2509
JB
583
584#define IWL_TLV_UCODE_MAGIC 0x0a4c5749
585
586struct iwl_tlv_ucode_header {
587 /*
588 * The TLV style ucode header is distinguished from
589 * the v1/v2 style header by first four bytes being
590 * zero, as such is an invalid combination of
591 * major/minor/API/serial versions.
592 */
593 __le32 zero;
594 __le32 magic;
595 u8 human_readable[64];
596 __le32 ver; /* major/minor/API/serial */
597 __le32 build;
598 __le64 alternatives; /* bitmask of valid alternatives */
599 /*
600 * The data contained herein has a TLV layout,
601 * see above for the TLV header and types.
602 * Note that each TLV is padded to a length
603 * that is a multiple of 4 for alignment.
604 */
605 u8 data[0];
606};
607
bb8c093b 608struct iwl4965_ibss_seq {
5d08cd1d
CH
609 u8 mac[ETH_ALEN];
610 u16 seq_num;
611 u16 frag_num;
612 unsigned long packet_time;
613 struct list_head list;
614};
615
f0832f13
EG
616struct iwl_sensitivity_ranges {
617 u16 min_nrg_cck;
618 u16 max_nrg_cck;
619
620 u16 nrg_th_cck;
621 u16 nrg_th_ofdm;
622
623 u16 auto_corr_min_ofdm;
624 u16 auto_corr_min_ofdm_mrc;
625 u16 auto_corr_min_ofdm_x1;
626 u16 auto_corr_min_ofdm_mrc_x1;
627
628 u16 auto_corr_max_ofdm;
629 u16 auto_corr_max_ofdm_mrc;
630 u16 auto_corr_max_ofdm_x1;
631 u16 auto_corr_max_ofdm_mrc_x1;
632
633 u16 auto_corr_max_cck;
634 u16 auto_corr_max_cck_mrc;
635 u16 auto_corr_min_cck;
636 u16 auto_corr_min_cck_mrc;
55036d66
WYG
637
638 u16 barker_corr_th_min;
639 u16 barker_corr_th_min_mrc;
640 u16 nrg_th_cca;
f0832f13
EG
641};
642
099b40b7 643
b5047f78
TW
644#define KELVIN_TO_CELSIUS(x) ((x)-273)
645#define CELSIUS_TO_KELVIN(x) ((x)+273)
646
647
bc47279f 648/**
5425e490 649 * struct iwl_hw_params
bc47279f 650 * @max_txq_num: Max # Tx queues supported
f3f911d1 651 * @dma_chnl_num: Number of Tx DMA/FIFO channels
4ddbb7d0 652 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 653 * @tfd_size: TFD size
099b40b7
RR
654 * @tx/rx_chains_num: Number of TX/RX chains
655 * @valid_tx/rx_ant: usable antennas
bc47279f 656 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 657 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 658 * @rx_page_order: Rx buffer page order
141c43a3 659 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f
BC
660 * @max_stations:
661 * @bcast_sta_id:
7aafef1c 662 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
663 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
664 * @sw_crypto: 0 for hw, 1 for sw
665 * @max_xxx_size: for ucode uses
666 * @ct_kill_threshold: temperature threshold
a0ee74cf 667 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
a96a27f9 668 * @calib_init_cfg: setup initial calibrations for the hw
f0832f13 669 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 670 */
5425e490 671struct iwl_hw_params {
f3f911d1
ZY
672 u8 max_txq_num;
673 u8 dma_chnl_num;
4ddbb7d0 674 u16 scd_bc_tbls_size;
a8e74e27 675 u32 tfd_size;
ec35cf2a
TW
676 u8 tx_chains_num;
677 u8 rx_chains_num;
678 u8 valid_tx_ant;
679 u8 valid_rx_ant;
5d08cd1d 680 u16 max_rxq_size;
ec35cf2a 681 u16 max_rxq_log;
2f301227 682 u32 rx_page_order;
141c43a3 683 u32 rx_wrt_ptr_reg;
5d08cd1d
CH
684 u8 max_stations;
685 u8 bcast_sta_id;
7aafef1c 686 u8 ht40_channel;
2c2f3b33 687 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
688 u32 max_inst_size;
689 u32 max_data_size;
690 u32 max_bsm_size;
691 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
692 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
693 /* for 1000, 6000 series and up */
a0ee74cf 694 u16 beacon_time_tsf_bits;
be5d56ed 695 u32 calib_init_cfg;
f0832f13 696 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
697};
698
5d08cd1d 699
5d08cd1d
CH
700/******************************************************************************
701 *
a33c2f47
EG
702 * Functions implemented in core module which are forward declared here
703 * for use by iwl-[4-5].c
5d08cd1d 704 *
a33c2f47
EG
705 * NOTE: The implementation of these functions are not hardware specific
706 * which is why they are in the core module files.
5d08cd1d
CH
707 *
708 * Naming convention --
a33c2f47 709 * iwl_ <-- Is part of iwlwifi
5d08cd1d 710 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
bb8c093b
CH
711 * iwl4965_bg_ <-- Called from work queue context
712 * iwl4965_mac_ <-- mac80211 callback
5d08cd1d
CH
713 *
714 ****************************************************************************/
5b9f8cd3
EG
715extern void iwl_update_chain_flags(struct iwl_priv *priv);
716extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src);
a33c2f47 717extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 718extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 719extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 720extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
721static inline int iwl_queue_used(const struct iwl_queue *q, int i)
722{
c8106d76 723 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
724 (i >= q->read_ptr && i < q->write_ptr) :
725 !(i < q->read_ptr && i >= q->write_ptr);
726}
727
728
729static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge)
730{
c8c24872
WYG
731 /*
732 * This is for init calibration result and scan command which
733 * required buffer > TFD_MAX_PAYLOAD_SIZE,
734 * the big buffer at end of command array
735 */
fd4abac5
TW
736 if (is_huge)
737 return q->n_window; /* must be power of 2 */
738
739 /* Otherwise, use normal size buffers */
740 return index & (q->n_window - 1);
741}
742
743
4ddbb7d0
TW
744struct iwl_dma_ptr {
745 dma_addr_t dma;
746 void *addr;
b481de9c
ZY
747 size_t size;
748};
749
b481de9c
ZY
750#define IWL_OPERATION_MODE_AUTO 0
751#define IWL_OPERATION_MODE_HT_ONLY 1
752#define IWL_OPERATION_MODE_MIXED 2
753#define IWL_OPERATION_MODE_20MHZ 3
754
3195cdb7
TW
755#define IWL_TX_CRC_SIZE 4
756#define IWL_TX_DELIMITER_SIZE 4
b481de9c 757
b481de9c 758#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 759
b481de9c 760/* Sensitivity and chain noise calibration */
b481de9c 761#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a
WYG
762#define IWL4965_CAL_NUM_BEACONS 20
763#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
764#define MAXIMUM_ALLOWED_PATHLOSS 15
765
b481de9c
ZY
766#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
767
768#define MAX_FA_OFDM 50
769#define MIN_FA_OFDM 5
770#define MAX_FA_CCK 50
771#define MIN_FA_CCK 5
772
b481de9c
ZY
773#define AUTO_CORR_STEP_OFDM 1
774
b481de9c
ZY
775#define AUTO_CORR_STEP_CCK 3
776#define AUTO_CORR_MAX_TH_CCK 160
777
b481de9c
ZY
778#define NRG_DIFF 2
779#define NRG_STEP_CCK 2
780#define NRG_MARGIN 8
781#define MAX_NUMBER_CCK_NO_FA 100
782
783#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
784
785#define CHAIN_A 0
786#define CHAIN_B 1
787#define CHAIN_C 2
788#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
789#define ALL_BAND_FILTER 0xFF00
790#define IN_BAND_FILTER 0xFF
791#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
792
3195cdb7
TW
793#define NRG_NUM_PREV_STAT_L 20
794#define NUM_RX_CHAINS 3
795
bb8c093b 796enum iwl4965_false_alarm_state {
b481de9c
ZY
797 IWL_FA_TOO_MANY = 0,
798 IWL_FA_TOO_FEW = 1,
799 IWL_FA_GOOD_RANGE = 2,
800};
801
bb8c093b 802enum iwl4965_chain_noise_state {
b481de9c 803 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
804 IWL_CHAIN_NOISE_ACCUMULATE,
805 IWL_CHAIN_NOISE_CALIBRATED,
806 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
807};
808
bb8c093b 809enum iwl4965_calib_enabled_state {
b481de9c
ZY
810 IWL_CALIB_DISABLED = 0, /* must be 0 */
811 IWL_CALIB_ENABLED = 1,
812};
813
f69f42a6
TW
814
815/*
816 * enum iwl_calib
817 * defines the order in which results of initial calibrations
818 * should be sent to the runtime uCode
819 */
820enum iwl_calib {
821 IWL_CALIB_XTAL,
819500c5 822 IWL_CALIB_DC,
f69f42a6
TW
823 IWL_CALIB_LO,
824 IWL_CALIB_TX_IQ,
825 IWL_CALIB_TX_IQ_PERD,
201706ac 826 IWL_CALIB_BASE_BAND,
f69f42a6
TW
827 IWL_CALIB_MAX
828};
829
6e21f2c1
TW
830/* Opaque calibration results */
831struct iwl_calib_result {
832 void *buf;
833 size_t buf_len;
7c616cba
TW
834};
835
dbb983b7
RR
836enum ucode_type {
837 UCODE_NONE = 0,
838 UCODE_INIT,
839 UCODE_RT
840};
841
b481de9c 842/* Sensitivity calib data */
f0832f13 843struct iwl_sensitivity_data {
b481de9c
ZY
844 u32 auto_corr_ofdm;
845 u32 auto_corr_ofdm_mrc;
846 u32 auto_corr_ofdm_x1;
847 u32 auto_corr_ofdm_mrc_x1;
848 u32 auto_corr_cck;
849 u32 auto_corr_cck_mrc;
850
851 u32 last_bad_plcp_cnt_ofdm;
852 u32 last_fa_cnt_ofdm;
853 u32 last_bad_plcp_cnt_cck;
854 u32 last_fa_cnt_cck;
855
856 u32 nrg_curr_state;
857 u32 nrg_prev_state;
858 u32 nrg_value[10];
859 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
860 u32 nrg_silence_ref;
861 u32 nrg_energy_idx;
862 u32 nrg_silence_idx;
863 u32 nrg_th_cck;
864 s32 nrg_auto_corr_silence_diff;
865 u32 num_in_cck_no_fa;
866 u32 nrg_th_ofdm;
55036d66
WYG
867
868 u16 barker_corr_th_min;
869 u16 barker_corr_th_min_mrc;
870 u16 nrg_th_cca;
b481de9c
ZY
871};
872
873/* Chain noise (differential Rx gain) calib data */
f0832f13 874struct iwl_chain_noise_data {
04816448 875 u32 active_chains;
b481de9c
ZY
876 u32 chain_noise_a;
877 u32 chain_noise_b;
878 u32 chain_noise_c;
879 u32 chain_signal_a;
880 u32 chain_signal_b;
881 u32 chain_signal_c;
04816448 882 u16 beacon_count;
b481de9c
ZY
883 u8 disconn_array[NUM_RX_CHAINS];
884 u8 delta_gain_code[NUM_RX_CHAINS];
885 u8 radio_write;
04816448 886 u8 state;
b481de9c
ZY
887};
888
abceddb4
BC
889#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
890#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 891
20594eb0
WYG
892#define IWL_TRAFFIC_ENTRIES (256)
893#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 894
5d08cd1d
CH
895enum {
896 MEASUREMENT_READY = (1 << 0),
897 MEASUREMENT_ACTIVE = (1 << 1),
898};
899
0848e297
WYG
900enum iwl_nvm_type {
901 NVM_DEVICE_TYPE_EEPROM = 0,
902 NVM_DEVICE_TYPE_OTP,
903};
904
415e4993
WYG
905/*
906 * Two types of OTP memory access modes
907 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
908 * based on physical memory addressing
909 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
910 * based on logical memory addressing
911 */
912enum iwl_access_mode {
913 IWL_OTP_ACCESS_ABSOLUTE,
914 IWL_OTP_ACCESS_RELATIVE,
915};
65b7998a
WYG
916
917/**
918 * enum iwl_pa_type - Power Amplifier type
919 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
920 * @IWL_PA_INTERNAL: use Internal only
921 */
922enum iwl_pa_type {
923 IWL_PA_SYSTEM = 0,
740e7f51 924 IWL_PA_INTERNAL = 1,
65b7998a
WYG
925};
926
a83b9141
WYG
927/* interrupt statistics */
928struct isr_statistics {
929 u32 hw;
930 u32 sw;
931 u32 sw_err;
932 u32 sch;
933 u32 alive;
934 u32 rfkill;
935 u32 ctkill;
936 u32 wakeup;
937 u32 rx;
938 u32 rx_handlers[REPLY_MAX];
939 u32 tx;
940 u32 unhandled;
941};
5d08cd1d 942
22fdf3c9
WYG
943#ifdef CONFIG_IWLWIFI_DEBUGFS
944/* management statistics */
945enum iwl_mgmt_stats {
946 MANAGEMENT_ASSOC_REQ = 0,
947 MANAGEMENT_ASSOC_RESP,
948 MANAGEMENT_REASSOC_REQ,
949 MANAGEMENT_REASSOC_RESP,
950 MANAGEMENT_PROBE_REQ,
951 MANAGEMENT_PROBE_RESP,
952 MANAGEMENT_BEACON,
953 MANAGEMENT_ATIM,
954 MANAGEMENT_DISASSOC,
955 MANAGEMENT_AUTH,
956 MANAGEMENT_DEAUTH,
957 MANAGEMENT_ACTION,
958 MANAGEMENT_MAX,
959};
960/* control statistics */
961enum iwl_ctrl_stats {
962 CONTROL_BACK_REQ = 0,
963 CONTROL_BACK,
964 CONTROL_PSPOLL,
965 CONTROL_RTS,
966 CONTROL_CTS,
967 CONTROL_ACK,
968 CONTROL_CFEND,
969 CONTROL_CFENDACK,
970 CONTROL_MAX,
971};
972
973struct traffic_stats {
974 u32 mgmt[MANAGEMENT_MAX];
975 u32 ctrl[CONTROL_MAX];
976 u32 data_cnt;
977 u64 data_bytes;
978};
979#else
980struct traffic_stats {
981 u64 data_bytes;
982};
983#endif
984
0924e519
WYG
985/*
986 * iwl_switch_rxon: "channel switch" structure
987 *
988 * @ switch_in_progress: channel switch in progress
989 * @ channel: new channel
990 */
991struct iwl_switch_rxon {
992 bool switch_in_progress;
993 __le16 channel;
994};
995
a9e1cb6a
WYG
996/*
997 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
998 * to perform continuous uCode event logging operation if enabled
999 */
1000#define UCODE_TRACE_PERIOD (100)
1001
1002/*
1003 * iwl_event_log: current uCode event log position
1004 *
1005 * @ucode_trace: enable/disable ucode continuous trace timer
1006 * @num_wraps: how many times the event buffer wraps
1007 * @next_entry: the entry just before the next one that uCode would fill
1008 * @non_wraps_count: counter for no wrap detected when dump ucode events
1009 * @wraps_once_count: counter for wrap once detected when dump ucode events
1010 * @wraps_more_count: counter for wrap more than once detected
1011 * when dump ucode events
1012 */
1013struct iwl_event_log {
1014 bool ucode_trace;
1015 u32 num_wraps;
1016 u32 next_entry;
1017 int non_wraps_count;
1018 int wraps_once_count;
1019 int wraps_more_count;
1020};
1021
2be76703
WYG
1022/*
1023 * host interrupt timeout value
1024 * used with setting interrupt coalescing timer
1025 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1026 *
1027 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1028 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1029 */
1030#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
1031#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
1032#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
1033#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1034#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1035#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1036
3e4fb5fa
TAN
1037/*
1038 * This is the threshold value of plcp error rate per 100mSecs. It is
1039 * used to set and check for the validity of plcp_delta.
1040 */
680788ac 1041#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1)
3e4fb5fa
TAN
1042#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
1043#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 1044#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa 1045#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
680788ac 1046#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0)
3e4fb5fa 1047
8a472da4
WYG
1048#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
1049#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1050
b74e31a9 1051/* timer constants use to monitor and recover stuck tx queues in mSecs */
ce60659a
WYG
1052#define IWL_DEF_MONITORING_PERIOD (1000)
1053#define IWL_LONG_MONITORING_PERIOD (5000)
b74e31a9
WYG
1054#define IWL_ONE_HUNDRED_MSECS (100)
1055#define IWL_SIXTY_SECS (60000)
1056
a93e7973
WYG
1057enum iwl_reset {
1058 IWL_RF_RESET = 0,
1059 IWL_FW_RESET,
8a472da4
WYG
1060 IWL_MAX_FORCE_RESET,
1061};
1062
1063struct iwl_force_reset {
1064 int reset_request_count;
1065 int reset_success_count;
1066 int reset_reject_count;
1067 unsigned long reset_duration;
1068 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1069};
1070
a0ee74cf
WYG
1071/* extend beacon time format bit shifting */
1072/*
1073 * for _3945 devices
1074 * bits 31:24 - extended
1075 * bits 23:0 - interval
1076 */
1077#define IWL3945_EXT_BEACON_TIME_POS 24
1078/*
1079 * for _agn devices
1080 * bits 31:22 - extended
1081 * bits 21:0 - interval
1082 */
1083#define IWLAGN_EXT_BEACON_TIME_POS 22
1084
c79dd5b5 1085struct iwl_priv {
5d08cd1d
CH
1086
1087 /* ieee device used by generic ieee processing code */
1088 struct ieee80211_hw *hw;
1089 struct ieee80211_channel *ieee_channels;
1090 struct ieee80211_rate *ieee_rates;
82b9a121 1091 struct iwl_cfg *cfg;
5d08cd1d
CH
1092
1093 /* temporary frame storage list */
1094 struct list_head free_frames;
1095 int frames_count;
1096
8318d78a 1097 enum ieee80211_band band;
2f301227 1098 int alloc_rxb_page;
5d08cd1d 1099
c79dd5b5 1100 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1101 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1102
8318d78a 1103 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1104
5d08cd1d 1105 /* spectrum measurement report caching */
2aa6ab86 1106 struct iwl_spectrum_notification measure_report;
5d08cd1d 1107 u8 measurement_status;
81963d68 1108
5d08cd1d
CH
1109 /* ucode beacon time */
1110 u32 ucode_beacon_time;
a13d276f 1111 int missed_beacon_threshold;
5d08cd1d 1112
3e4fb5fa
TAN
1113 /* storing the jiffies when the plcp error rate is received */
1114 unsigned long plcp_jiffies;
1115
a93e7973 1116 /* force reset */
8a472da4 1117 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1118
5a2a780c 1119 /* we allocate array of iwl_channel_info for NIC's valid channels.
5d08cd1d 1120 * Access via channel # using indirect index array */
bf85ea4f 1121 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1122 u8 channel_count; /* # of channels */
1123
5d08cd1d
CH
1124 /* thermal calibration */
1125 s32 temperature; /* degrees Kelvin */
1126 s32 last_temperature;
1127
7c616cba 1128 /* init calibration results */
6e21f2c1 1129 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1130
5d08cd1d 1131 /* Scan related variables */
5d08cd1d 1132 unsigned long scan_start;
5d08cd1d 1133 unsigned long scan_start_tsf;
811ecc99 1134 void *scan_cmd;
00700ee0 1135 enum ieee80211_band scan_band;
1ecf9fc1 1136 struct cfg80211_scan_request *scan_request;
f84b29ec 1137 struct ieee80211_vif *scan_vif;
afbdd69a 1138 bool is_internal_short_scan;
76eff18b
TW
1139 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1140 u8 mgmt_tx_ant;
5d08cd1d
CH
1141
1142 /* spinlock */
1143 spinlock_t lock; /* protect general shared data */
1144 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1145 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d 1146 struct mutex mutex;
d2dfe6df 1147 struct mutex sync_cmd_mutex; /* enable serialization of sync commands */
5d08cd1d
CH
1148
1149 /* basic pci-network driver stuff */
1150 struct pci_dev *pci_dev;
1151
1152 /* pci hardware address support */
1153 void __iomem *hw_base;
b661c819
TW
1154 u32 hw_rev;
1155 u32 hw_wa_rev;
1156 u8 rev_id;
5d08cd1d 1157
c6fa17ed
WYG
1158 /* EEPROM MAC addresses */
1159 struct mac_address addresses[2];
1160
5d08cd1d 1161 /* uCode images, save to reload in case of failure */
b08dfd04 1162 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1163 u32 ucode_ver; /* version of ucode, copy of
1164 iwl_ucode.ver */
5d08cd1d
CH
1165 struct fw_desc ucode_code; /* runtime inst */
1166 struct fw_desc ucode_data; /* runtime data original */
1167 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1168 struct fw_desc ucode_init; /* initialization inst */
1169 struct fw_desc ucode_init_data; /* initialization data */
1170 struct fw_desc ucode_boot; /* bootstrap inst */
dbb983b7
RR
1171 enum ucode_type ucode_type;
1172 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1173 char firmware_name[25];
5d08cd1d
CH
1174
1175
3195c1f3 1176 struct iwl_rxon_time_cmd rxon_timing;
5d08cd1d
CH
1177
1178 /* We declare this const so it can only be
1179 * changed via explicit cast within the
1180 * routines that actually update the physical
1181 * hardware */
c1adf9fb
GG
1182 const struct iwl_rxon_cmd active_rxon;
1183 struct iwl_rxon_cmd staging_rxon;
5d08cd1d 1184
0924e519
WYG
1185 struct iwl_switch_rxon switch_rxon;
1186
5d08cd1d 1187 /* 1st responses from initialize and runtime uCode images.
5a2a780c 1188 * _agn's initialize alive response contains some calibration data. */
885ba202
TW
1189 struct iwl_init_alive_resp card_alive_init;
1190 struct iwl_alive_resp card_alive;
5d08cd1d 1191
ab53d8af
MA
1192 unsigned long last_blink_time;
1193 u8 last_blink_rate;
1194 u8 allow_blinking;
1195 u64 led_tpt;
e932a609 1196
5d08cd1d 1197 u16 active_rate;
5d08cd1d 1198
5d08cd1d 1199 u8 start_calib;
f0832f13
EG
1200 struct iwl_sensitivity_data sensitivity_data;
1201 struct iwl_chain_noise_data chain_noise_data;
c8312fac 1202 bool enhance_sensitivity_table;
5d08cd1d 1203 __le16 sensitivity_tbl[HD_TABLE_SIZE];
c8312fac 1204 __le16 enhance_sensitivity_tbl[ENHANCE_HD_TABLE_ENTRIES];
5d08cd1d 1205
fad95bf5 1206 struct iwl_ht_config current_ht_config;
5d08cd1d 1207
5d08cd1d 1208 /* Rate scaling data */
5d08cd1d
CH
1209 u8 retry_rate;
1210
1211 wait_queue_head_t wait_command_queue;
1212
1213 int activity_timer_active;
1214
1215 /* Rx and Tx DMA processing queues */
a55360e4 1216 struct iwl_rx_queue rxq;
88804e2b 1217 struct iwl_tx_queue *txq;
5d08cd1d 1218 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1219 struct iwl_dma_ptr kw; /* keep warm address */
1220 struct iwl_dma_ptr scd_bc_tbls;
1221
5d08cd1d
CH
1222 u32 scd_base_addr; /* scheduler sram base address */
1223
1224 unsigned long status;
5d08cd1d 1225
19758bef 1226 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1227 struct traffic_stats tx_stats;
1228 struct traffic_stats rx_stats;
19758bef 1229
a83b9141
WYG
1230 /* counts interrupts */
1231 struct isr_statistics isr_stats;
1232
5da4b55f 1233 struct iwl_power_mgr power_data;
3ad3b92a 1234 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1235
5d08cd1d 1236 /* context information */
59c02b41 1237 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
5d08cd1d 1238
9c5ac091
RC
1239 /* station table variables */
1240
1241 /* Note: if lock and sta_lock are needed, lock must be acquired first */
5d08cd1d
CH
1242 spinlock_t sta_lock;
1243 int num_stations;
6def9761 1244 struct iwl_station_entry stations[IWL_STATION_COUNT];
72e15d71 1245 struct iwl_wep_key wep_keys[WEP_KEYS_MAX]; /* protected by mutex */
6974e363 1246 u8 key_mapping_key;
80fb47a1 1247 unsigned long ucode_key_table;
5d08cd1d 1248
e4e72fb4
JB
1249 /* queue refcounts */
1250#define IWL_MAX_HW_QUEUES 32
1251 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1252 /* for each AC */
1253 atomic_t queue_stop_count[4];
1254
5d08cd1d 1255 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1256 u8 is_open;
5d08cd1d
CH
1257
1258 u8 mac80211_registered;
5d08cd1d 1259
af6b8ee3 1260 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1261 u8 *eeprom;
0848e297 1262 int nvm_device_type;
073d3f5f 1263 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1264
05c914fe 1265 enum nl80211_iftype iw_mode;
5d08cd1d
CH
1266
1267 struct sk_buff *ibss_beacon;
1268
1269 /* Last Rx'd beacon timestamp */
3109ece1 1270 u64 timestamp;
32bfd35d 1271 struct ieee80211_vif *vif;
5d08cd1d 1272
ee525d13
JB
1273 union {
1274#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1275 struct {
1276 void *shared_virt;
1277 dma_addr_t shared_phys;
1278
1279 struct delayed_work thermal_periodic;
1280 struct delayed_work rfkill_poll;
1281
1282 struct iwl3945_notif_statistics statistics;
d73e4923 1283#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK
1284 struct iwl3945_notif_statistics accum_statistics;
1285 struct iwl3945_notif_statistics delta_statistics;
1286 struct iwl3945_notif_statistics max_delta;
1287#endif
ee525d13
JB
1288
1289 u32 sta_supp_rates;
e99f168c
JB
1290 int last_rx_rssi; /* From Rx packet statistics */
1291
1292 /* Rx'd packet timing information */
1293 u32 last_beacon_time;
1294 u64 last_tsf;
67d613ae
JB
1295
1296 /*
1297 * each calibration channel group in the
1298 * EEPROM has a derived clip setting for
1299 * each rate.
1300 */
1301 const struct iwl3945_clip_group clip_groups[5];
1302
ee525d13 1303 } _3945;
a4c8b2a6
JB
1304#endif
1305#if defined(CONFIG_IWLAGN) || defined(CONFIG_IWLAGN_MODULE)
1306 struct {
1307 /* INT ICT Table */
1308 __le32 *ict_tbl;
1309 void *ict_tbl_vir;
1310 dma_addr_t ict_tbl_dma;
1311 dma_addr_t aligned_ict_tbl_dma;
1312 int ict_index;
1313 u32 inta;
1314 bool use_ict;
d5a0ffa3
WYG
1315 /*
1316 * reporting the number of tids has AGG on. 0 means
1317 * no AGGREGATION
1318 */
1319 u8 agg_tids_count;
05d57520
JB
1320
1321 struct iwl_rx_phy_res last_phy_res;
1322 bool last_phy_res_valid;
a15707d8
RC
1323
1324 struct completion firmware_loading_complete;
a2064b7a 1325
b2e640d4
JB
1326 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1327 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
f3aebeee 1328
6a822d06
WYG
1329 /*
1330 * chain noise reset and gain commands are the
1331 * two extra calibration commands follows the standard
1332 * phy calibration commands
1333 */
1334 u8 phy_calib_chain_noise_reset_cmd;
1335 u8 phy_calib_chain_noise_gain_cmd;
1336
f3aebeee 1337 struct iwl_notif_statistics statistics;
7980fba5 1338 struct iwl_bt_notif_statistics statistics_bt;
f3aebeee
WYG
1339#ifdef CONFIG_IWLWIFI_DEBUGFS
1340 struct iwl_notif_statistics accum_statistics;
1341 struct iwl_notif_statistics delta_statistics;
1342 struct iwl_notif_statistics max_delta;
7980fba5
WYG
1343 struct iwl_bt_notif_statistics accum_statistics_bt;
1344 struct iwl_bt_notif_statistics delta_statistics_bt;
1345 struct iwl_bt_notif_statistics max_delta_bt;
f3aebeee 1346#endif
a4c8b2a6 1347 } _agn;
ee525d13
JB
1348#endif
1349 };
1350
5425e490 1351 struct iwl_hw_params hw_params;
4ddbb7d0 1352
40cefda9 1353 u32 inta_mask;
5d08cd1d 1354
1ff50bda 1355 struct iwl_qos_info qos_data;
5d08cd1d
CH
1356
1357 struct workqueue_struct *workqueue;
1358
5d08cd1d 1359 struct work_struct restart;
5d08cd1d
CH
1360 struct work_struct scan_completed;
1361 struct work_struct rx_replenish;
5d08cd1d 1362 struct work_struct abort_scan;
5d08cd1d 1363 struct work_struct beacon_update;
a28027cd
WYG
1364 struct work_struct tt_work;
1365 struct work_struct ct_enter;
1366 struct work_struct ct_exit;
88be0264 1367 struct work_struct start_internal_scan;
65550636 1368 struct work_struct tx_flush;
5d08cd1d
CH
1369
1370 struct tasklet_struct irq_tasklet;
1371
1372 struct delayed_work init_alive_start;
1373 struct delayed_work alive_start;
5d08cd1d 1374 struct delayed_work scan_check;
4a8a4322 1375
630fe9b6
TW
1376 /* TX Power */
1377 s8 tx_power_user_lmt;
dc1b0973 1378 s8 tx_power_device_lmt;
ae16fc3c 1379 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
5d08cd1d 1380
5d08cd1d 1381
d08853a3 1382#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1383 /* debugging info */
3d816c77
RC
1384 u32 debug_level; /* per device debugging will override global
1385 iwl_debug_level if set */
d73e4923 1386#endif /* CONFIG_IWLWIFI_DEBUG */
712b6cf5
TW
1387#ifdef CONFIG_IWLWIFI_DEBUGFS
1388 /* debugfs */
20594eb0
WYG
1389 u16 tx_traffic_idx;
1390 u16 rx_traffic_idx;
1391 u8 *tx_traffic;
1392 u8 *rx_traffic;
4c84a8f1
JB
1393 struct dentry *debugfs_dir;
1394 u32 dbgfs_sram_offset, dbgfs_sram_len;
d73e4923 1395 bool disable_ht40;
712b6cf5 1396#endif /* CONFIG_IWLWIFI_DEBUGFS */
5d08cd1d
CH
1397
1398 struct work_struct txpower_work;
445c2dff
TW
1399 u32 disable_sens_cal;
1400 u32 disable_chain_noise_cal;
203566f3 1401 u32 disable_tx_power_cal;
16e727e8 1402 struct work_struct run_time_calib_work;
5d08cd1d 1403 struct timer_list statistics_periodic;
a9e1cb6a 1404 struct timer_list ucode_trace;
b74e31a9 1405 struct timer_list monitor_recover;
086ed117 1406 bool hw_ready;
a9e1cb6a
WYG
1407
1408 struct iwl_event_log event_log;
c79dd5b5 1409}; /*iwl_priv */
5d08cd1d 1410
36470749
RR
1411static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1412{
1413 set_bit(txq_id, &priv->txq_ctx_active_msk);
1414}
1415
1416static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1417{
1418 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1419}
1420
994d31f7 1421#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6 1422const char *iwl_get_tx_fail_reason(u32 status);
3d816c77
RC
1423/*
1424 * iwl_get_debug_level: Return active debug level for device
1425 *
1426 * Using sysfs it is possible to set per device debug level. This debug
1427 * level will be used if set, otherwise the global debug level which can be
1428 * set via module parameter is used.
1429 */
1430static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1431{
1432 if (priv->debug_level)
1433 return priv->debug_level;
1434 else
1435 return iwl_debug_level;
1436}
a332f8d6
TW
1437#else
1438static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; }
3d816c77
RC
1439
1440static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1441{
1442 return iwl_debug_level;
1443}
a332f8d6
TW
1444#endif
1445
1446
a332f8d6
TW
1447static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1448 int txq_id, int idx)
1449{
ff0d91c3 1450 if (priv->txq[txq_id].txb[idx].skb)
a332f8d6 1451 return (struct ieee80211_hdr *)priv->txq[txq_id].
ff0d91c3 1452 txb[idx].skb->data;
a332f8d6
TW
1453 return NULL;
1454}
a332f8d6
TW
1455
1456
3109ece1 1457static inline int iwl_is_associated(struct iwl_priv *priv)
5d08cd1d
CH
1458{
1459 return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1460}
1461
bf85ea4f 1462static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1463{
1464 if (ch_info == NULL)
1465 return 0;
1466 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1467}
1468
bf85ea4f 1469static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1470{
1471 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1472}
1473
bf85ea4f 1474static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1475{
8318d78a 1476 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1477}
1478
bf85ea4f 1479static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1480{
8318d78a 1481 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1482}
1483
bf85ea4f 1484static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1485{
1486 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1487}
1488
bf85ea4f 1489static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1490{
1491 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1492}
1493
64a76b50
ZY
1494static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1495{
1496 __free_pages(page, priv->hw_params.rx_page_order);
1497 priv->alloc_rxb_page--;
1498}
1499
1500static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1501{
1502 free_pages(page, priv->hw_params.rx_page_order);
1503 priv->alloc_rxb_page--;
1504}
be1f3ab6 1505#endif /* __iwl_dev_h__ */