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iwlwifi: move iwl_clear_stations_table to iwl-sta.c
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
b481de9c
ZY
1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 * Please use iwl-4965-hw.h for hardware-related definitions.
30 */
31
be1f3ab6
EG
32#ifndef __iwl_dev_h__
33#define __iwl_dev_h__
b481de9c 34
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
37#include <net/ieee80211_radiotap.h>
38
4fc22b21 39#define DRV_NAME "iwlagn"
ad97edd2 40#include "iwl-rfkill.h"
6bc913bd 41#include "iwl-eeprom.h"
5d08cd1d 42#include "iwl-4965-hw.h"
6f83eaa1 43#include "iwl-csr.h"
5d08cd1d 44#include "iwl-prph.h"
0a6857e7 45#include "iwl-debug.h"
ab53d8af 46#include "iwl-led.h"
5da4b55f 47#include "iwl-power.h"
e227ceac 48#include "iwl-agn-rs.h"
5d08cd1d 49
fed9017e
RR
50/* configuration for the iwl4965 */
51extern struct iwl_cfg iwl4965_agn_cfg;
5a6a256e
TW
52extern struct iwl_cfg iwl5300_agn_cfg;
53extern struct iwl_cfg iwl5100_agn_cfg;
54extern struct iwl_cfg iwl5350_agn_cfg;
47408639
EK
55extern struct iwl_cfg iwl5100_bg_cfg;
56extern struct iwl_cfg iwl5100_abg_cfg;
fed9017e 57
099b40b7
RR
58/* CT-KILL constants */
59#define CT_KILL_THRESHOLD 110 /* in Celsius */
4bf775cd 60
5d08cd1d
CH
61/* Default noise level to report when noise measurement is not available.
62 * This may be because we're:
63 * 1) Not associated (4965, no beacon statistics being sent to driver)
64 * 2) Scanning (noise measurement does not apply to associated channel)
65 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
66 * Use default noise value of -127 ... this is below the range of measurable
67 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
68 * Also, -127 works better than 0 when averaging frames with/without
69 * noise info (e.g. averaging might be done in app); measured dBm values are
70 * always negative ... using a negative value as the default keeps all
71 * averages within an s8's (used in some apps) range of negative values. */
72#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
73
5d08cd1d
CH
74/*
75 * RTS threshold here is total size [2347] minus 4 FCS bytes
76 * Per spec:
77 * a value of 0 means RTS on all data/management packets
78 * a value > max MSDU size means no RTS
79 * else RTS for data/management frames where MPDU is larger
80 * than RTS value.
81 */
82#define DEFAULT_RTS_THRESHOLD 2347U
83#define MIN_RTS_THRESHOLD 0U
84#define MAX_RTS_THRESHOLD 2347U
85#define MAX_MSDU_SIZE 2304U
86#define MAX_MPDU_SIZE 2346U
87#define DEFAULT_BEACON_INTERVAL 100U
88#define DEFAULT_SHORT_RETRY_LIMIT 7U
89#define DEFAULT_LONG_RETRY_LIMIT 4U
90
a55360e4 91struct iwl_rx_mem_buffer {
4018517a
JB
92 dma_addr_t real_dma_addr;
93 dma_addr_t aligned_dma_addr;
5d08cd1d
CH
94 struct sk_buff *skb;
95 struct list_head list;
96};
97
5d08cd1d
CH
98/*
99 * Generic queue structure
100 *
101 * Contains common data for Rx and Tx queues
102 */
443cfd45 103struct iwl_queue {
5d08cd1d
CH
104 int n_bd; /* number of BDs in this queue */
105 int write_ptr; /* 1-st empty entry (index) host_w*/
106 int read_ptr; /* last used entry (index) host_r*/
107 dma_addr_t dma_addr; /* physical addr for BD's */
108 int n_window; /* safe queue window */
109 u32 id;
110 int low_mark; /* low watermark, resume queue if free
111 * space more than this */
112 int high_mark; /* high watermark, stop queue if free
113 * space less than this */
114} __attribute__ ((packed));
115
bc47279f 116/* One for each TFD */
8567c63e 117struct iwl_tx_info {
499b1883 118 struct sk_buff *skb[IWL_NUM_OF_TBS - 1];
5d08cd1d
CH
119};
120
121/**
16466903 122 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
123 * @q: generic Rx/Tx queue descriptor
124 * @bd: base of circular buffer of TFDs
125 * @cmd: array of command/Tx buffers
126 * @dma_addr_cmd: physical address of cmd/tx buffer array
127 * @txb: array of per-TFD driver data
128 * @need_update: indicates need to update read/write index
129 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 130 *
bc47279f
BC
131 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
132 * descriptors) and required locking structures.
5d08cd1d 133 */
16466903 134struct iwl_tx_queue {
443cfd45 135 struct iwl_queue q;
499b1883 136 struct iwl_tfd *tfds;
da99c4b6 137 struct iwl_cmd *cmd[TFD_TX_CMD_SLOTS];
8567c63e 138 struct iwl_tx_info *txb;
3fd07a1e
TW
139 u8 need_update;
140 u8 sched_retry;
141 u8 active;
142 u8 swq_id;
5d08cd1d
CH
143};
144
145#define IWL_NUM_SCAN_RATES (2)
146
bb8c093b 147struct iwl4965_channel_tgd_info {
5d08cd1d
CH
148 u8 type;
149 s8 max_power;
150};
151
bb8c093b 152struct iwl4965_channel_tgh_info {
5d08cd1d
CH
153 s64 last_radar_time;
154};
155
5d08cd1d
CH
156/*
157 * One for each channel, holds all channel setup data
158 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
159 * with one another!
160 */
bf85ea4f 161struct iwl_channel_info {
bb8c093b
CH
162 struct iwl4965_channel_tgd_info tgd;
163 struct iwl4965_channel_tgh_info tgh;
073d3f5f
TW
164 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
165 struct iwl_eeprom_channel fat_eeprom; /* EEPROM regulatory limit for
166 * FAT channel */
5d08cd1d
CH
167
168 u8 channel; /* channel number */
169 u8 flags; /* flags copied from EEPROM */
170 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 171 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
172 s8 min_power; /* always 0 */
173 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
174
175 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
176 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 177 enum ieee80211_band band;
5d08cd1d 178
5d08cd1d
CH
179 /* FAT channel info */
180 s8 fat_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
181 s8 fat_curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) */
182 s8 fat_min_power; /* always 0 */
183 s8 fat_scan_power; /* (dBm) eeprom, direct scans, any rate */
184 u8 fat_flags; /* flags copied from EEPROM */
fcd427bb 185 u8 fat_extension_channel; /* HT_IE_EXT_CHANNEL_* */
5d08cd1d
CH
186};
187
bb8c093b 188struct iwl4965_clip_group {
5d08cd1d
CH
189 /* maximum power level to prevent clipping for each rate, derived by
190 * us from this band's saturation power in EEPROM */
191 const s8 clip_powers[IWL_MAX_RATES];
192};
193
5d08cd1d
CH
194
195#define IWL_TX_FIFO_AC0 0
196#define IWL_TX_FIFO_AC1 1
197#define IWL_TX_FIFO_AC2 2
198#define IWL_TX_FIFO_AC3 3
199#define IWL_TX_FIFO_HCCA_1 5
200#define IWL_TX_FIFO_HCCA_2 6
201#define IWL_TX_FIFO_NONE 7
202
203/* Minimum number of queues. MAX_NUM is defined in hw specific files */
204#define IWL_MIN_NUM_QUEUES 4
205
206/* Power management (not Tx power) structures */
207
6f4083aa
TW
208enum iwl_pwr_src {
209 IWL_PWR_SRC_VMAIN,
210 IWL_PWR_SRC_VAUX,
211};
212
5d08cd1d
CH
213#define IEEE80211_DATA_LEN 2304
214#define IEEE80211_4ADDR_LEN 30
215#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
216#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
217
fcab423d 218struct iwl_frame {
5d08cd1d
CH
219 union {
220 struct ieee80211_hdr frame;
4bf64efd 221 struct iwl_tx_beacon_cmd beacon;
5d08cd1d
CH
222 u8 raw[IEEE80211_FRAME_LEN];
223 u8 cmd[360];
224 } u;
225 struct list_head list;
226};
227
5d08cd1d
CH
228#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
229#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
230#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
231
232enum {
233 /* CMD_SIZE_NORMAL = 0, */
234 CMD_SIZE_HUGE = (1 << 0),
235 /* CMD_SYNC = 0, */
236 CMD_ASYNC = (1 << 1),
237 /* CMD_NO_SKB = 0, */
238 CMD_WANT_SKB = (1 << 2),
239};
240
857485c0 241struct iwl_cmd;
c79dd5b5 242struct iwl_priv;
5d08cd1d 243
857485c0
TW
244struct iwl_cmd_meta {
245 struct iwl_cmd_meta *source;
5d08cd1d
CH
246 union {
247 struct sk_buff *skb;
c79dd5b5 248 int (*callback)(struct iwl_priv *priv,
857485c0 249 struct iwl_cmd *cmd, struct sk_buff *skb);
5d08cd1d
CH
250 } __attribute__ ((packed)) u;
251
252 /* The CMD_SIZE_HUGE flag bit indicates that the command
253 * structure is stored at the end of the shared queue memory. */
254 u32 flags;
499b1883
TW
255 DECLARE_PCI_UNMAP_ADDR(mapping)
256 DECLARE_PCI_UNMAP_LEN(len)
5d08cd1d
CH
257} __attribute__ ((packed));
258
d2f18bfd 259#define IWL_CMD_MAX_PAYLOAD 320
bd68fb6f 260
bc47279f 261/**
857485c0 262 * struct iwl_cmd
bc47279f
BC
263 *
264 * For allocation of the command and tx queues, this establishes the overall
265 * size of the largest command we send to uCode, except for a scan command
266 * (which is relatively huge; space is allocated separately).
267 */
857485c0
TW
268struct iwl_cmd {
269 struct iwl_cmd_meta meta; /* driver data */
270 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 271 union {
5d08cd1d
CH
272 u32 flags;
273 u8 val8;
274 u16 val16;
275 u32 val32;
83d527d9 276 struct iwl_tx_cmd tx;
bd68fb6f 277 u8 payload[IWL_CMD_MAX_PAYLOAD];
5d08cd1d
CH
278 } __attribute__ ((packed)) cmd;
279} __attribute__ ((packed));
280
3257e5d4 281
857485c0 282struct iwl_host_cmd {
5d08cd1d
CH
283 u8 id;
284 u16 len;
857485c0 285 struct iwl_cmd_meta meta;
5d08cd1d
CH
286 const void *data;
287};
288
857485c0
TW
289#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \
290 sizeof(struct iwl_cmd_meta))
5d08cd1d
CH
291
292/*
293 * RX related structures and functions
294 */
295#define RX_FREE_BUFFERS 64
296#define RX_LOW_WATERMARK 8
297
298#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
299#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
300#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
301
302/**
a55360e4 303 * struct iwl_rx_queue - Rx queue
5d08cd1d
CH
304 * @read: Shared index to newest available Rx buffer
305 * @write: Shared index to oldest written Rx packet
306 * @free_count: Number of pre-allocated buffers in rx_free
307 * @rx_free: list of free SKBs for use
308 * @rx_used: List of Rx buffers with no SKB
309 * @need_update: flag to indicate we need to update read/write index
310 *
a55360e4 311 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 312 */
a55360e4 313struct iwl_rx_queue {
5d08cd1d
CH
314 __le32 *bd;
315 dma_addr_t dma_addr;
a55360e4
TW
316 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
317 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
318 u32 read;
319 u32 write;
320 u32 free_count;
321 struct list_head rx_free;
322 struct list_head rx_used;
323 int need_update;
8d86422a
WT
324 struct iwl_rb_status *rb_stts;
325 dma_addr_t rb_stts_dma;
5d08cd1d
CH
326 spinlock_t lock;
327};
328
329#define IWL_SUPPORTED_RATES_IE_LEN 8
330
331#define SCAN_INTERVAL 100
332
333#define MAX_A_CHANNELS 252
334#define MIN_A_CHANNELS 7
335
336#define MAX_B_CHANNELS 14
337#define MIN_B_CHANNELS 1
338
5d08cd1d
CH
339#define MAX_TID_COUNT 9
340
341#define IWL_INVALID_RATE 0xFF
342#define IWL_INVALID_VALUE -1
343
bc47279f 344/**
6def9761 345 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
346 * @txq_id: Tx queue used for Tx attempt
347 * @frame_count: # frames attempted by Tx command
348 * @wait_for_ba: Expect block-ack before next Tx reply
349 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
350 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
351 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
352 * @rate_n_flags: Rate at which Tx was attempted
353 *
354 * If REPLY_TX indicates that aggregation was attempted, driver must wait
355 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
356 * until block ack arrives.
357 */
6def9761 358struct iwl_ht_agg {
5d08cd1d
CH
359 u16 txq_id;
360 u16 frame_count;
361 u16 wait_for_ba;
362 u16 start_idx;
fe01b477 363 u64 bitmap;
5d08cd1d 364 u32 rate_n_flags;
fe01b477
RR
365#define IWL_AGG_OFF 0
366#define IWL_AGG_ON 1
367#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
368#define IWL_EMPTYING_HW_QUEUE_DELBA 3
369 u8 state;
5d08cd1d 370};
fe01b477 371
5d08cd1d 372
6def9761 373struct iwl_tid_data {
5d08cd1d 374 u16 seq_number;
fe01b477 375 u16 tfds_in_queue;
6def9761 376 struct iwl_ht_agg agg;
5d08cd1d
CH
377};
378
6def9761 379struct iwl_hw_key {
5d08cd1d
CH
380 enum ieee80211_key_alg alg;
381 int keylen;
0211ddda 382 u8 keyidx;
5d08cd1d
CH
383 u8 key[32];
384};
385
bb8c093b 386union iwl4965_ht_rate_supp {
5d08cd1d
CH
387 u16 rates;
388 struct {
389 u8 siso_rate;
390 u8 mimo_rate;
391 };
392};
393
5d08cd1d 394#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
5d08cd1d
CH
395#define CFG_HT_MPDU_DENSITY_2USEC (0x5)
396#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_2USEC
397
9e0cc6de
RR
398struct iwl_ht_info {
399 /* self configuration data */
5d08cd1d 400 u8 is_ht;
9e0cc6de 401 u8 supported_chan_width;
12837be1 402 u8 sm_ps;
9e0cc6de 403 u8 is_green_field;
bb54244b 404 u8 sgf; /* HT_SHORT_GI_* short guard interval */
5d08cd1d
CH
405 u8 max_amsdu_size;
406 u8 ampdu_factor;
407 u8 mpdu_density;
d9fe60de 408 struct ieee80211_mcs_info mcs;
9e0cc6de 409 /* BSS related data */
5d08cd1d 410 u8 extension_chan_offset;
5d08cd1d 411 u8 tx_chan_width;
9e0cc6de
RR
412 u8 ht_protection;
413 u8 non_GF_STA_present;
5d08cd1d 414};
5d08cd1d 415
1ff50bda 416union iwl_qos_capabity {
5d08cd1d
CH
417 struct {
418 u8 edca_count:4; /* bit 0-3 */
419 u8 q_ack:1; /* bit 4 */
420 u8 queue_request:1; /* bit 5 */
421 u8 txop_request:1; /* bit 6 */
422 u8 reserved:1; /* bit 7 */
423 } q_AP;
424 struct {
425 u8 acvo_APSD:1; /* bit 0 */
426 u8 acvi_APSD:1; /* bit 1 */
427 u8 ac_bk_APSD:1; /* bit 2 */
428 u8 ac_be_APSD:1; /* bit 3 */
429 u8 q_ack:1; /* bit 4 */
430 u8 max_len:2; /* bit 5-6 */
431 u8 more_data_ack:1; /* bit 7 */
432 } q_STA;
433 u8 val;
434};
435
436/* QoS structures */
1ff50bda 437struct iwl_qos_info {
5d08cd1d
CH
438 int qos_enable;
439 int qos_active;
1ff50bda
EG
440 union iwl_qos_capabity qos_cap;
441 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 442};
5d08cd1d
CH
443
444#define STA_PS_STATUS_WAKE 0
445#define STA_PS_STATUS_SLEEP 1
446
6def9761 447struct iwl_station_entry {
133636de 448 struct iwl_addsta_cmd sta;
6def9761 449 struct iwl_tid_data tid[MAX_TID_COUNT];
5d08cd1d
CH
450 u8 used;
451 u8 ps_status;
6def9761 452 struct iwl_hw_key keyinfo;
5d08cd1d
CH
453};
454
455/* one for each uCode image (inst/data, boot/init/runtime) */
456struct fw_desc {
457 void *v_addr; /* access by driver */
458 dma_addr_t p_addr; /* access by card's busmaster DMA */
459 u32 len; /* bytes */
460};
461
462/* uCode file layout */
14b3d338 463struct iwl_ucode {
5d08cd1d
CH
464 __le32 ver; /* major/minor/subminor */
465 __le32 inst_size; /* bytes of runtime instructions */
466 __le32 data_size; /* bytes of runtime data */
467 __le32 init_size; /* bytes of initialization instructions */
468 __le32 init_data_size; /* bytes of initialization data */
469 __le32 boot_size; /* bytes of bootstrap instructions */
470 u8 data[0]; /* data in same order as "size" elements */
471};
472
bb8c093b 473struct iwl4965_ibss_seq {
5d08cd1d
CH
474 u8 mac[ETH_ALEN];
475 u16 seq_num;
476 u16 frag_num;
477 unsigned long packet_time;
478 struct list_head list;
479};
480
f0832f13
EG
481struct iwl_sensitivity_ranges {
482 u16 min_nrg_cck;
483 u16 max_nrg_cck;
484
485 u16 nrg_th_cck;
486 u16 nrg_th_ofdm;
487
488 u16 auto_corr_min_ofdm;
489 u16 auto_corr_min_ofdm_mrc;
490 u16 auto_corr_min_ofdm_x1;
491 u16 auto_corr_min_ofdm_mrc_x1;
492
493 u16 auto_corr_max_ofdm;
494 u16 auto_corr_max_ofdm_mrc;
495 u16 auto_corr_max_ofdm_x1;
496 u16 auto_corr_max_ofdm_mrc_x1;
497
498 u16 auto_corr_max_cck;
499 u16 auto_corr_max_cck_mrc;
500 u16 auto_corr_min_cck;
501 u16 auto_corr_min_cck_mrc;
502};
503
099b40b7
RR
504
505#define IWL_FAT_CHANNEL_52 BIT(IEEE80211_BAND_5GHZ)
506
bc47279f 507/**
5425e490 508 * struct iwl_hw_params
bc47279f 509 * @max_txq_num: Max # Tx queues supported
4ddbb7d0 510 * @scd_bc_tbls_size: size of scheduler byte count tables
099b40b7
RR
511 * @tx/rx_chains_num: Number of TX/RX chains
512 * @valid_tx/rx_ant: usable antennas
bc47279f 513 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 514 * @max_rxq_log: Log-base-2 of max_rxq_size
099b40b7 515 * @rx_buf_size: Rx buffer size
bc47279f
BC
516 * @max_stations:
517 * @bcast_sta_id:
099b40b7
RR
518 * @fat_channel: is 40MHz width possible in band 2.4
519 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
520 * @sw_crypto: 0 for hw, 1 for sw
521 * @max_xxx_size: for ucode uses
522 * @ct_kill_threshold: temperature threshold
a96a27f9 523 * @calib_init_cfg: setup initial calibrations for the hw
f0832f13 524 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 525 */
5425e490 526struct iwl_hw_params {
5d08cd1d 527 u16 max_txq_num;
4ddbb7d0 528 u16 scd_bc_tbls_size;
ec35cf2a
TW
529 u8 tx_chains_num;
530 u8 rx_chains_num;
531 u8 valid_tx_ant;
532 u8 valid_rx_ant;
5d08cd1d 533 u16 max_rxq_size;
ec35cf2a 534 u16 max_rxq_log;
9ee1ba47
RR
535 u32 rx_buf_size;
536 u32 max_pkt_size;
5d08cd1d
CH
537 u8 max_stations;
538 u8 bcast_sta_id;
099b40b7
RR
539 u8 fat_channel;
540 u8 sw_crypto;
541 u32 max_inst_size;
542 u32 max_data_size;
543 u32 max_bsm_size;
544 u32 ct_kill_threshold; /* value in hw-dependent units */
be5d56ed 545 u32 calib_init_cfg;
f0832f13 546 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
547};
548
a9841013
EG
549#define HT_SHORT_GI_20MHZ (1 << 0)
550#define HT_SHORT_GI_40MHZ (1 << 1)
5d08cd1d
CH
551
552
bb8c093b 553#define IWL_RX_HDR(x) ((struct iwl4965_rx_frame_hdr *)(\
5d08cd1d
CH
554 x->u.rx_frame.stats.payload + \
555 x->u.rx_frame.stats.phy_count))
bb8c093b 556#define IWL_RX_END(x) ((struct iwl4965_rx_frame_end *)(\
5d08cd1d
CH
557 IWL_RX_HDR(x)->payload + \
558 le16_to_cpu(IWL_RX_HDR(x)->len)))
559#define IWL_RX_STATS(x) (&x->u.rx_frame.stats)
560#define IWL_RX_DATA(x) (IWL_RX_HDR(x)->payload)
561
5d08cd1d
CH
562/******************************************************************************
563 *
a33c2f47
EG
564 * Functions implemented in core module which are forward declared here
565 * for use by iwl-[4-5].c
5d08cd1d 566 *
a33c2f47
EG
567 * NOTE: The implementation of these functions are not hardware specific
568 * which is why they are in the core module files.
5d08cd1d
CH
569 *
570 * Naming convention --
a33c2f47 571 * iwl_ <-- Is part of iwlwifi
5d08cd1d 572 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
bb8c093b
CH
573 * iwl4965_bg_ <-- Called from work queue context
574 * iwl4965_mac_ <-- mac80211 callback
5d08cd1d
CH
575 *
576 ****************************************************************************/
5b9f8cd3
EG
577extern void iwl_update_chain_flags(struct iwl_priv *priv);
578extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src);
a33c2f47 579extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 580extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 581extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 582extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
583static inline int iwl_queue_used(const struct iwl_queue *q, int i)
584{
585 return q->write_ptr > q->read_ptr ?
586 (i >= q->read_ptr && i < q->write_ptr) :
587 !(i < q->read_ptr && i >= q->write_ptr);
588}
589
590
591static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge)
592{
593 /* This is for scan command, the big buffer at end of command array */
594 if (is_huge)
595 return q->n_window; /* must be power of 2 */
596
597 /* Otherwise, use normal size buffers */
598 return index & (q->n_window - 1);
599}
600
601
c79dd5b5 602struct iwl_priv;
b481de9c 603
78330fdd 604
4ddbb7d0
TW
605struct iwl_dma_ptr {
606 dma_addr_t dma;
607 void *addr;
b481de9c
ZY
608 size_t size;
609};
610
b481de9c
ZY
611#define IWL_CHANNEL_WIDTH_20MHZ 0
612#define IWL_CHANNEL_WIDTH_40MHZ 1
613
b481de9c
ZY
614#define IWL_OPERATION_MODE_AUTO 0
615#define IWL_OPERATION_MODE_HT_ONLY 1
616#define IWL_OPERATION_MODE_MIXED 2
617#define IWL_OPERATION_MODE_20MHZ 3
618
3195cdb7
TW
619#define IWL_TX_CRC_SIZE 4
620#define IWL_TX_DELIMITER_SIZE 4
b481de9c 621
b481de9c 622#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 623
b481de9c
ZY
624/* Sensitivity and chain noise calibration */
625#define INTERFERENCE_DATA_AVAILABLE __constant_cpu_to_le32(1)
626#define INITIALIZATION_VALUE 0xFFFF
627#define CAL_NUM_OF_BEACONS 20
628#define MAXIMUM_ALLOWED_PATHLOSS 15
629
b481de9c
ZY
630#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
631
632#define MAX_FA_OFDM 50
633#define MIN_FA_OFDM 5
634#define MAX_FA_CCK 50
635#define MIN_FA_CCK 5
636
b481de9c
ZY
637#define AUTO_CORR_STEP_OFDM 1
638
b481de9c
ZY
639#define AUTO_CORR_STEP_CCK 3
640#define AUTO_CORR_MAX_TH_CCK 160
641
b481de9c
ZY
642#define NRG_DIFF 2
643#define NRG_STEP_CCK 2
644#define NRG_MARGIN 8
645#define MAX_NUMBER_CCK_NO_FA 100
646
647#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
648
649#define CHAIN_A 0
650#define CHAIN_B 1
651#define CHAIN_C 2
652#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
653#define ALL_BAND_FILTER 0xFF00
654#define IN_BAND_FILTER 0xFF
655#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
656
3195cdb7
TW
657#define NRG_NUM_PREV_STAT_L 20
658#define NUM_RX_CHAINS 3
659
bb8c093b 660enum iwl4965_false_alarm_state {
b481de9c
ZY
661 IWL_FA_TOO_MANY = 0,
662 IWL_FA_TOO_FEW = 1,
663 IWL_FA_GOOD_RANGE = 2,
664};
665
bb8c093b 666enum iwl4965_chain_noise_state {
b481de9c 667 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
668 IWL_CHAIN_NOISE_ACCUMULATE,
669 IWL_CHAIN_NOISE_CALIBRATED,
670 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
671};
672
bb8c093b 673enum iwl4965_calib_enabled_state {
b481de9c
ZY
674 IWL_CALIB_DISABLED = 0, /* must be 0 */
675 IWL_CALIB_ENABLED = 1,
676};
677
678struct statistics_general_data {
679 u32 beacon_silence_rssi_a;
680 u32 beacon_silence_rssi_b;
681 u32 beacon_silence_rssi_c;
682 u32 beacon_energy_a;
683 u32 beacon_energy_b;
684 u32 beacon_energy_c;
685};
686
f69f42a6
TW
687
688/*
689 * enum iwl_calib
690 * defines the order in which results of initial calibrations
691 * should be sent to the runtime uCode
692 */
693enum iwl_calib {
694 IWL_CALIB_XTAL,
695 IWL_CALIB_LO,
696 IWL_CALIB_TX_IQ,
697 IWL_CALIB_TX_IQ_PERD,
698 IWL_CALIB_MAX
699};
700
6e21f2c1
TW
701/* Opaque calibration results */
702struct iwl_calib_result {
703 void *buf;
704 size_t buf_len;
7c616cba
TW
705};
706
dbb983b7
RR
707enum ucode_type {
708 UCODE_NONE = 0,
709 UCODE_INIT,
710 UCODE_RT
711};
712
b481de9c 713/* Sensitivity calib data */
f0832f13 714struct iwl_sensitivity_data {
b481de9c
ZY
715 u32 auto_corr_ofdm;
716 u32 auto_corr_ofdm_mrc;
717 u32 auto_corr_ofdm_x1;
718 u32 auto_corr_ofdm_mrc_x1;
719 u32 auto_corr_cck;
720 u32 auto_corr_cck_mrc;
721
722 u32 last_bad_plcp_cnt_ofdm;
723 u32 last_fa_cnt_ofdm;
724 u32 last_bad_plcp_cnt_cck;
725 u32 last_fa_cnt_cck;
726
727 u32 nrg_curr_state;
728 u32 nrg_prev_state;
729 u32 nrg_value[10];
730 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
731 u32 nrg_silence_ref;
732 u32 nrg_energy_idx;
733 u32 nrg_silence_idx;
734 u32 nrg_th_cck;
735 s32 nrg_auto_corr_silence_diff;
736 u32 num_in_cck_no_fa;
737 u32 nrg_th_ofdm;
b481de9c
ZY
738};
739
740/* Chain noise (differential Rx gain) calib data */
f0832f13 741struct iwl_chain_noise_data {
04816448 742 u32 active_chains;
b481de9c
ZY
743 u32 chain_noise_a;
744 u32 chain_noise_b;
745 u32 chain_noise_c;
746 u32 chain_signal_a;
747 u32 chain_signal_b;
748 u32 chain_signal_c;
04816448 749 u16 beacon_count;
b481de9c
ZY
750 u8 disconn_array[NUM_RX_CHAINS];
751 u8 delta_gain_code[NUM_RX_CHAINS];
752 u8 radio_write;
04816448 753 u8 state;
b481de9c
ZY
754};
755
abceddb4
BC
756#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
757#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 758
5d08cd1d 759
5d08cd1d
CH
760enum {
761 MEASUREMENT_READY = (1 << 0),
762 MEASUREMENT_ACTIVE = (1 << 1),
763};
764
5d08cd1d 765
dfe7d458
RR
766#define IWL_MAX_NUM_QUEUES 20 /* FIXME: do dynamic allocation */
767
c79dd5b5 768struct iwl_priv {
5d08cd1d
CH
769
770 /* ieee device used by generic ieee processing code */
771 struct ieee80211_hw *hw;
772 struct ieee80211_channel *ieee_channels;
773 struct ieee80211_rate *ieee_rates;
82b9a121 774 struct iwl_cfg *cfg;
5d08cd1d
CH
775
776 /* temporary frame storage list */
777 struct list_head free_frames;
778 int frames_count;
779
8318d78a 780 enum ieee80211_band band;
5d08cd1d
CH
781 int alloc_rxb_skb;
782
c79dd5b5 783 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 784 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 785
8318d78a 786 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 787
4fc22b21 788#ifdef CONFIG_IWLAGN_SPECTRUM_MEASUREMENT
5d08cd1d 789 /* spectrum measurement report caching */
bb8c093b 790 struct iwl4965_spectrum_notification measure_report;
5d08cd1d
CH
791 u8 measurement_status;
792#endif
793 /* ucode beacon time */
794 u32 ucode_beacon_time;
795
bb8c093b 796 /* we allocate array of iwl4965_channel_info for NIC's valid channels.
5d08cd1d 797 * Access via channel # using indirect index array */
bf85ea4f 798 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
799 u8 channel_count; /* # of channels */
800
801 /* each calibration channel group in the EEPROM has a derived
802 * clip setting for each rate. */
bb8c093b 803 const struct iwl4965_clip_group clip_groups[5];
5d08cd1d
CH
804
805 /* thermal calibration */
806 s32 temperature; /* degrees Kelvin */
807 s32 last_temperature;
808
7c616cba 809 /* init calibration results */
6e21f2c1 810 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 811
5d08cd1d
CH
812 /* Scan related variables */
813 unsigned long last_scan_jiffies;
7878a5a4 814 unsigned long next_scan_jiffies;
5d08cd1d
CH
815 unsigned long scan_start;
816 unsigned long scan_pass_start;
817 unsigned long scan_start_tsf;
76eff18b 818 struct iwl_scan_cmd *scan;
5d08cd1d
CH
819 int scan_bands;
820 int one_direct_scan;
821 u8 direct_ssid_len;
822 u8 direct_ssid[IW_ESSID_MAX_SIZE];
76eff18b
TW
823 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
824 u8 mgmt_tx_ant;
5d08cd1d
CH
825
826 /* spinlock */
827 spinlock_t lock; /* protect general shared data */
828 spinlock_t hcmd_lock; /* protect hcmd */
829 struct mutex mutex;
830
831 /* basic pci-network driver stuff */
832 struct pci_dev *pci_dev;
833
834 /* pci hardware address support */
835 void __iomem *hw_base;
b661c819
TW
836 u32 hw_rev;
837 u32 hw_wa_rev;
838 u8 rev_id;
5d08cd1d
CH
839
840 /* uCode images, save to reload in case of failure */
841 struct fw_desc ucode_code; /* runtime inst */
842 struct fw_desc ucode_data; /* runtime data original */
843 struct fw_desc ucode_data_backup; /* runtime data save/restore */
844 struct fw_desc ucode_init; /* initialization inst */
845 struct fw_desc ucode_init_data; /* initialization data */
846 struct fw_desc ucode_boot; /* bootstrap inst */
dbb983b7
RR
847 enum ucode_type ucode_type;
848 u8 ucode_write_complete; /* the image write is complete */
5d08cd1d
CH
849
850
3195c1f3 851 struct iwl_rxon_time_cmd rxon_timing;
5d08cd1d
CH
852
853 /* We declare this const so it can only be
854 * changed via explicit cast within the
855 * routines that actually update the physical
856 * hardware */
c1adf9fb
GG
857 const struct iwl_rxon_cmd active_rxon;
858 struct iwl_rxon_cmd staging_rxon;
5d08cd1d
CH
859
860 int error_recovering;
c1adf9fb 861 struct iwl_rxon_cmd recovery_rxon;
5d08cd1d
CH
862
863 /* 1st responses from initialize and runtime uCode images.
864 * 4965's initialize alive response contains some calibration data. */
885ba202
TW
865 struct iwl_init_alive_resp card_alive_init;
866 struct iwl_alive_resp card_alive;
eadd3c4b 867#ifdef CONFIG_IWLWIFI_RFKILL
80fcc9e2 868 struct rfkill *rfkill;
ad97edd2 869#endif
5d08cd1d 870
36316126 871#ifdef CONFIG_IWLWIFI_LEDS
0eee6127 872 struct iwl_led led[IWL_LED_TRG_MAX];
ab53d8af
MA
873 unsigned long last_blink_time;
874 u8 last_blink_rate;
875 u8 allow_blinking;
876 u64 led_tpt;
5d08cd1d
CH
877#endif
878
879 u16 active_rate;
880 u16 active_rate_basic;
881
5d08cd1d 882 u8 assoc_station_added;
5d08cd1d 883 u8 start_calib;
f0832f13
EG
884 struct iwl_sensitivity_data sensitivity_data;
885 struct iwl_chain_noise_data chain_noise_data;
5d08cd1d 886 __le16 sensitivity_tbl[HD_TABLE_SIZE];
5d08cd1d 887
9e0cc6de 888 struct iwl_ht_info current_ht_config;
5d08cd1d
CH
889 u8 last_phy_res[100];
890
5d08cd1d
CH
891 /* Rate scaling data */
892 s8 data_retry_limit;
893 u8 retry_rate;
894
895 wait_queue_head_t wait_command_queue;
896
897 int activity_timer_active;
898
899 /* Rx and Tx DMA processing queues */
a55360e4 900 struct iwl_rx_queue rxq;
16466903 901 struct iwl_tx_queue txq[IWL_MAX_NUM_QUEUES];
5d08cd1d 902 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
903 struct iwl_dma_ptr kw; /* keep warm address */
904 struct iwl_dma_ptr scd_bc_tbls;
905
5d08cd1d
CH
906 u32 scd_base_addr; /* scheduler sram base address */
907
908 unsigned long status;
5d08cd1d 909
a96a27f9 910 int last_rx_rssi; /* From Rx packet statistics */
5d08cd1d
CH
911 int last_rx_noise; /* From beacon statistics */
912
19758bef
TW
913 /* counts mgmt, ctl, and data packets */
914 struct traffic_stats {
915 u32 cnt;
916 u64 bytes;
917 } tx_stats[3], rx_stats[3];
918
5da4b55f 919 struct iwl_power_mgr power_data;
5d08cd1d 920
8f91aecb 921 struct iwl_notif_statistics statistics;
5d08cd1d
CH
922 unsigned long last_statistics_time;
923
924 /* context information */
5d08cd1d
CH
925 u16 rates_mask;
926
927 u32 power_mode;
928 u32 antenna;
929 u8 bssid[ETH_ALEN];
930 u16 rts_threshold;
931 u8 mac_addr[ETH_ALEN];
932
933 /*station table variables */
934 spinlock_t sta_lock;
935 int num_stations;
6def9761 936 struct iwl_station_entry stations[IWL_STATION_COUNT];
6974e363
EG
937 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
938 u8 default_wep_key;
939 u8 key_mapping_key;
80fb47a1 940 unsigned long ucode_key_table;
5d08cd1d
CH
941
942 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 943 u8 is_open;
5d08cd1d
CH
944
945 u8 mac80211_registered;
5d08cd1d 946
5d08cd1d
CH
947 /* Rx'd packet timing information */
948 u32 last_beacon_time;
949 u64 last_tsf;
950
5d08cd1d 951 /* eeprom */
073d3f5f
TW
952 u8 *eeprom;
953 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 954
05c914fe 955 enum nl80211_iftype iw_mode;
5d08cd1d
CH
956
957 struct sk_buff *ibss_beacon;
958
959 /* Last Rx'd beacon timestamp */
3109ece1 960 u64 timestamp;
5d08cd1d 961 u16 beacon_int;
32bfd35d 962 struct ieee80211_vif *vif;
5d08cd1d 963
5425e490 964 struct iwl_hw_params hw_params;
4ddbb7d0 965
059ff826 966
5d08cd1d
CH
967 /* Current association information needed to configure the
968 * hardware */
969 u16 assoc_id;
970 u16 assoc_capability;
5d08cd1d 971
1ff50bda 972 struct iwl_qos_info qos_data;
5d08cd1d
CH
973
974 struct workqueue_struct *workqueue;
975
976 struct work_struct up;
977 struct work_struct restart;
978 struct work_struct calibrated_work;
979 struct work_struct scan_completed;
980 struct work_struct rx_replenish;
981 struct work_struct rf_kill;
982 struct work_struct abort_scan;
983 struct work_struct update_link_led;
984 struct work_struct auth_work;
985 struct work_struct report_work;
986 struct work_struct request_scan;
987 struct work_struct beacon_update;
988
989 struct tasklet_struct irq_tasklet;
990
c90a74ba 991 struct delayed_work set_power_save;
5d08cd1d
CH
992 struct delayed_work init_alive_start;
993 struct delayed_work alive_start;
5d08cd1d 994 struct delayed_work scan_check;
630fe9b6
TW
995 /* TX Power */
996 s8 tx_power_user_lmt;
997 s8 tx_power_channel_lmt;
5d08cd1d
CH
998
999#ifdef CONFIG_PM
1000 u32 pm_state[16];
1001#endif
1002
0a6857e7 1003#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1004 /* debugging info */
bf403db8 1005 u32 debug_level;
5d08cd1d
CH
1006 u32 framecnt_to_us;
1007 atomic_t restrict_refcnt;
712b6cf5
TW
1008#ifdef CONFIG_IWLWIFI_DEBUGFS
1009 /* debugfs */
1010 struct iwl_debugfs *dbgfs;
1011#endif /* CONFIG_IWLWIFI_DEBUGFS */
1012#endif /* CONFIG_IWLWIFI_DEBUG */
5d08cd1d
CH
1013
1014 struct work_struct txpower_work;
445c2dff
TW
1015 u32 disable_sens_cal;
1016 u32 disable_chain_noise_cal;
203566f3 1017 u32 disable_tx_power_cal;
16e727e8 1018 struct work_struct run_time_calib_work;
5d08cd1d 1019 struct timer_list statistics_periodic;
c79dd5b5 1020}; /*iwl_priv */
5d08cd1d 1021
36470749
RR
1022static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1023{
1024 set_bit(txq_id, &priv->txq_ctx_active_msk);
1025}
1026
1027static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1028{
1029 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1030}
1031
994d31f7 1032#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6
TW
1033const char *iwl_get_tx_fail_reason(u32 status);
1034#else
1035static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; }
1036#endif
1037
1038
a332f8d6
TW
1039static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1040 int txq_id, int idx)
1041{
1042 if (priv->txq[txq_id].txb[idx].skb[0])
1043 return (struct ieee80211_hdr *)priv->txq[txq_id].
1044 txb[idx].skb[0]->data;
1045 return NULL;
1046}
a332f8d6
TW
1047
1048
3109ece1 1049static inline int iwl_is_associated(struct iwl_priv *priv)
5d08cd1d
CH
1050{
1051 return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1052}
1053
bf85ea4f 1054static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1055{
1056 if (ch_info == NULL)
1057 return 0;
1058 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1059}
1060
bf85ea4f 1061static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1062{
1063 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1064}
1065
bf85ea4f 1066static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1067{
8318d78a 1068 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1069}
1070
bf85ea4f 1071static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1072{
8318d78a 1073 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1074}
1075
bf85ea4f 1076static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1077{
1078 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1079}
1080
bf85ea4f 1081static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1082{
1083 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1084}
1085
8622e705 1086extern const struct iwl_channel_info *iwl_get_channel_info(
c79dd5b5 1087 const struct iwl_priv *priv, enum ieee80211_band band, u16 channel);
5d08cd1d 1088
c79dd5b5 1089/* Requires full declaration of iwl_priv before including */
5d08cd1d 1090
be1f3ab6 1091#endif /* __iwl_dev_h__ */