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iwlwifi: push virtual interface through
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
b481de9c
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1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 * Please use iwl-4965-hw.h for hardware-related definitions.
30 */
31
be1f3ab6
EG
32#ifndef __iwl_dev_h__
33#define __iwl_dev_h__
b481de9c 34
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
37#include <net/ieee80211_radiotap.h>
38
6bc913bd 39#include "iwl-eeprom.h"
6f83eaa1 40#include "iwl-csr.h"
5d08cd1d 41#include "iwl-prph.h"
dbb6654c 42#include "iwl-fh.h"
0a6857e7 43#include "iwl-debug.h"
dbb6654c
WT
44#include "iwl-4965-hw.h"
45#include "iwl-3945-hw.h"
b744cb79 46#include "iwl-agn-hw.h"
ab53d8af 47#include "iwl-led.h"
5da4b55f 48#include "iwl-power.h"
e227ceac 49#include "iwl-agn-rs.h"
5d08cd1d 50
fed9017e
RR
51/* configuration for the iwl4965 */
52extern struct iwl_cfg iwl4965_agn_cfg;
5a6a256e
TW
53extern struct iwl_cfg iwl5300_agn_cfg;
54extern struct iwl_cfg iwl5100_agn_cfg;
55extern struct iwl_cfg iwl5350_agn_cfg;
ac592574 56extern struct iwl_cfg iwl5100_bgn_cfg;
47408639 57extern struct iwl_cfg iwl5100_abg_cfg;
7100e924 58extern struct iwl_cfg iwl5150_agn_cfg;
ac592574 59extern struct iwl_cfg iwl5150_abg_cfg;
95b13014 60extern struct iwl_cfg iwl6000g2a_2agn_cfg;
65b7998a 61extern struct iwl_cfg iwl6000i_2agn_cfg;
5953a62e
WYG
62extern struct iwl_cfg iwl6000i_2abg_cfg;
63extern struct iwl_cfg iwl6000i_2bg_cfg;
e1228374
JS
64extern struct iwl_cfg iwl6000_3agn_cfg;
65extern struct iwl_cfg iwl6050_2agn_cfg;
5953a62e 66extern struct iwl_cfg iwl6050_2abg_cfg;
77dcb6a9 67extern struct iwl_cfg iwl1000_bgn_cfg;
4bd0914f 68extern struct iwl_cfg iwl1000_bg_cfg;
fed9017e 69
672639de
WYG
70struct iwl_tx_queue;
71
099b40b7 72/* CT-KILL constants */
672639de
WYG
73#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
74#define CT_KILL_THRESHOLD 114 /* in Celsius */
75#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 76
5d08cd1d
CH
77/* Default noise level to report when noise measurement is not available.
78 * This may be because we're:
79 * 1) Not associated (4965, no beacon statistics being sent to driver)
80 * 2) Scanning (noise measurement does not apply to associated channel)
81 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
82 * Use default noise value of -127 ... this is below the range of measurable
83 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
84 * Also, -127 works better than 0 when averaging frames with/without
85 * noise info (e.g. averaging might be done in app); measured dBm values are
86 * always negative ... using a negative value as the default keeps all
87 * averages within an s8's (used in some apps) range of negative values. */
88#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
89
5d08cd1d
CH
90/*
91 * RTS threshold here is total size [2347] minus 4 FCS bytes
92 * Per spec:
93 * a value of 0 means RTS on all data/management packets
94 * a value > max MSDU size means no RTS
95 * else RTS for data/management frames where MPDU is larger
96 * than RTS value.
97 */
98#define DEFAULT_RTS_THRESHOLD 2347U
99#define MIN_RTS_THRESHOLD 0U
100#define MAX_RTS_THRESHOLD 2347U
101#define MAX_MSDU_SIZE 2304U
102#define MAX_MPDU_SIZE 2346U
103#define DEFAULT_BEACON_INTERVAL 100U
104#define DEFAULT_SHORT_RETRY_LIMIT 7U
105#define DEFAULT_LONG_RETRY_LIMIT 4U
106
a55360e4 107struct iwl_rx_mem_buffer {
2f301227
ZY
108 dma_addr_t page_dma;
109 struct page *page;
5d08cd1d
CH
110 struct list_head list;
111};
112
2f301227
ZY
113#define rxb_addr(r) page_address(r->page)
114
c2acea8e
JB
115/* defined below */
116struct iwl_device_cmd;
117
118struct iwl_cmd_meta {
119 /* only for SYNC commands, iff the reply skb is wanted */
120 struct iwl_host_cmd *source;
121 /*
122 * only for ASYNC commands
123 * (which is somewhat stupid -- look at iwl-sta.c for instance
124 * which duplicates a bunch of code because the callback isn't
125 * invoked for SYNC commands, if it were and its result passed
126 * through it would be simpler...)
127 */
5696aea6
JB
128 void (*callback)(struct iwl_priv *priv,
129 struct iwl_device_cmd *cmd,
2f301227 130 struct iwl_rx_packet *pkt);
c2acea8e
JB
131
132 /* The CMD_SIZE_HUGE flag bit indicates that the command
133 * structure is stored at the end of the shared queue memory. */
134 u32 flags;
135
136 DECLARE_PCI_UNMAP_ADDR(mapping)
137 DECLARE_PCI_UNMAP_LEN(len)
138};
139
5d08cd1d
CH
140/*
141 * Generic queue structure
142 *
143 * Contains common data for Rx and Tx queues
144 */
443cfd45 145struct iwl_queue {
5d08cd1d
CH
146 int n_bd; /* number of BDs in this queue */
147 int write_ptr; /* 1-st empty entry (index) host_w*/
148 int read_ptr; /* last used entry (index) host_r*/
b74e31a9
WYG
149 /* use for monitoring and recovering the stuck queue */
150 int last_read_ptr; /* storing the last read_ptr */
151 /* number of time read_ptr and last_read_ptr are the same */
152 u8 repeat_same_read_ptr;
5d08cd1d
CH
153 dma_addr_t dma_addr; /* physical addr for BD's */
154 int n_window; /* safe queue window */
155 u32 id;
156 int low_mark; /* low watermark, resume queue if free
157 * space more than this */
158 int high_mark; /* high watermark, stop queue if free
159 * space less than this */
160} __attribute__ ((packed));
161
bc47279f 162/* One for each TFD */
8567c63e 163struct iwl_tx_info {
499b1883 164 struct sk_buff *skb[IWL_NUM_OF_TBS - 1];
5d08cd1d
CH
165};
166
167/**
16466903 168 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
169 * @q: generic Rx/Tx queue descriptor
170 * @bd: base of circular buffer of TFDs
c2acea8e
JB
171 * @cmd: array of command/TX buffer pointers
172 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
173 * @dma_addr_cmd: physical address of cmd/tx buffer array
174 * @txb: array of per-TFD driver data
175 * @need_update: indicates need to update read/write index
176 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 177 *
bc47279f
BC
178 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
179 * descriptors) and required locking structures.
5d08cd1d 180 */
188cf6c7
SO
181#define TFD_TX_CMD_SLOTS 256
182#define TFD_CMD_SLOTS 32
183
16466903 184struct iwl_tx_queue {
443cfd45 185 struct iwl_queue q;
59606ffa 186 void *tfds;
c2acea8e
JB
187 struct iwl_device_cmd **cmd;
188 struct iwl_cmd_meta *meta;
8567c63e 189 struct iwl_tx_info *txb;
3fd07a1e
TW
190 u8 need_update;
191 u8 sched_retry;
192 u8 active;
193 u8 swq_id;
5d08cd1d
CH
194};
195
196#define IWL_NUM_SCAN_RATES (2)
197
bb8c093b 198struct iwl4965_channel_tgd_info {
5d08cd1d
CH
199 u8 type;
200 s8 max_power;
201};
202
bb8c093b 203struct iwl4965_channel_tgh_info {
5d08cd1d
CH
204 s64 last_radar_time;
205};
206
d20b3c65
SO
207#define IWL4965_MAX_RATE (33)
208
85d41495
KA
209struct iwl3945_clip_group {
210 /* maximum power level to prevent clipping for each rate, derived by
211 * us from this band's saturation power in EEPROM */
212 const s8 clip_powers[IWL_MAX_RATES];
213};
214
d20b3c65
SO
215/* current Tx power values to use, one for each rate for each channel.
216 * requested power is limited by:
217 * -- regulatory EEPROM limits for this channel
218 * -- hardware capabilities (clip-powers)
219 * -- spectrum management
220 * -- user preference (e.g. iwconfig)
221 * when requested power is set, base power index must also be set. */
222struct iwl3945_channel_power_info {
223 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
224 s8 power_table_index; /* actual (compenst'd) index into gain table */
225 s8 base_power_index; /* gain index for power at factory temp. */
226 s8 requested_power; /* power (dBm) requested for this chnl/rate */
227};
228
229/* current scan Tx power values to use, one for each scan rate for each
230 * channel. */
231struct iwl3945_scan_power_info {
232 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
233 s8 power_table_index; /* actual (compenst'd) index into gain table */
234 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
235};
236
5d08cd1d
CH
237/*
238 * One for each channel, holds all channel setup data
239 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
240 * with one another!
241 */
bf85ea4f 242struct iwl_channel_info {
bb8c093b
CH
243 struct iwl4965_channel_tgd_info tgd;
244 struct iwl4965_channel_tgh_info tgh;
073d3f5f 245 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
246 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
247 * HT40 channel */
5d08cd1d
CH
248
249 u8 channel; /* channel number */
250 u8 flags; /* flags copied from EEPROM */
251 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 252 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
253 s8 min_power; /* always 0 */
254 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
255
256 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
257 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 258 enum ieee80211_band band;
5d08cd1d 259
7aafef1c
WYG
260 /* HT40 channel info */
261 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
262 u8 ht40_flags; /* flags copied from EEPROM */
263 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
d20b3c65
SO
264
265 /* Radio/DSP gain settings for each "normal" data Tx rate.
266 * These include, in addition to RF and DSP gain, a few fields for
267 * remembering/modifying gain settings (indexes). */
268 struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE];
269
270 /* Radio/DSP gain settings for each scan rate, for directed scans. */
271 struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
5d08cd1d
CH
272};
273
edc1a3a0
JB
274#define IWL_TX_FIFO_BK 0
275#define IWL_TX_FIFO_BE 1
276#define IWL_TX_FIFO_VI 2
277#define IWL_TX_FIFO_VO 3
278#define IWL_TX_FIFO_UNUSED -1
5d08cd1d 279
01a7e084
RC
280/* Minimum number of queues. MAX_NUM is defined in hw specific files.
281 * Set the minimum to accommodate the 4 standard TX queues, 1 command
282 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
283#define IWL_MIN_NUM_QUEUES 10
5d08cd1d 284
bd35f150 285/*
1a716557
JB
286 * Queue #4 is the command queue for 3945/4965/5x00/1000/6x00,
287 * the driver maps it into the appropriate device FIFO for the
288 * uCode.
bd35f150
WYG
289 */
290#define IWL_CMD_QUEUE_NUM 4
291
5d08cd1d
CH
292/* Power management (not Tx power) structures */
293
6f4083aa
TW
294enum iwl_pwr_src {
295 IWL_PWR_SRC_VMAIN,
296 IWL_PWR_SRC_VAUX,
297};
298
5d08cd1d
CH
299#define IEEE80211_DATA_LEN 2304
300#define IEEE80211_4ADDR_LEN 30
301#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
302#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
303
fcab423d 304struct iwl_frame {
5d08cd1d
CH
305 union {
306 struct ieee80211_hdr frame;
4bf64efd 307 struct iwl_tx_beacon_cmd beacon;
5d08cd1d
CH
308 u8 raw[IEEE80211_FRAME_LEN];
309 u8 cmd[360];
310 } u;
311 struct list_head list;
312};
313
5d08cd1d
CH
314#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
315#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
316#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
317
318enum {
c587de0b
TW
319 CMD_SYNC = 0,
320 CMD_SIZE_NORMAL = 0,
321 CMD_NO_SKB = 0,
5d08cd1d 322 CMD_SIZE_HUGE = (1 << 0),
5d08cd1d 323 CMD_ASYNC = (1 << 1),
5d08cd1d
CH
324 CMD_WANT_SKB = (1 << 2),
325};
326
c8c24872 327#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 328
bc47279f 329/**
c2acea8e 330 * struct iwl_device_cmd
bc47279f
BC
331 *
332 * For allocation of the command and tx queues, this establishes the overall
333 * size of the largest command we send to uCode, except for a scan command
334 * (which is relatively huge; space is allocated separately).
335 */
c2acea8e 336struct iwl_device_cmd {
857485c0 337 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 338 union {
5d08cd1d
CH
339 u32 flags;
340 u8 val8;
341 u16 val16;
342 u32 val32;
83d527d9 343 struct iwl_tx_cmd tx;
c8c24872
WYG
344 struct iwl6000_channel_switch_cmd chswitch;
345 u8 payload[DEF_CMD_PAYLOAD_SIZE];
5d08cd1d
CH
346 } __attribute__ ((packed)) cmd;
347} __attribute__ ((packed));
348
c2acea8e
JB
349#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
350
3257e5d4 351
857485c0 352struct iwl_host_cmd {
5d08cd1d 353 const void *data;
2f301227 354 unsigned long reply_page;
5696aea6
JB
355 void (*callback)(struct iwl_priv *priv,
356 struct iwl_device_cmd *cmd,
2f301227 357 struct iwl_rx_packet *pkt);
c2acea8e
JB
358 u32 flags;
359 u16 len;
360 u8 id;
5d08cd1d
CH
361};
362
5d08cd1d
CH
363#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
364#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
365#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
366
367/**
a55360e4 368 * struct iwl_rx_queue - Rx queue
df833b1d
RC
369 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
370 * @dma_addr: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
371 * @read: Shared index to newest available Rx buffer
372 * @write: Shared index to oldest written Rx packet
373 * @free_count: Number of pre-allocated buffers in rx_free
374 * @rx_free: list of free SKBs for use
375 * @rx_used: List of Rx buffers with no SKB
376 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
377 * @rb_stts: driver's pointer to receive buffer status
378 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 379 *
a55360e4 380 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 381 */
a55360e4 382struct iwl_rx_queue {
5d08cd1d
CH
383 __le32 *bd;
384 dma_addr_t dma_addr;
a55360e4
TW
385 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
386 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
387 u32 read;
388 u32 write;
389 u32 free_count;
4752c93c 390 u32 write_actual;
5d08cd1d
CH
391 struct list_head rx_free;
392 struct list_head rx_used;
393 int need_update;
8d86422a
WT
394 struct iwl_rb_status *rb_stts;
395 dma_addr_t rb_stts_dma;
5d08cd1d
CH
396 spinlock_t lock;
397};
398
399#define IWL_SUPPORTED_RATES_IE_LEN 8
400
5d08cd1d
CH
401#define MAX_TID_COUNT 9
402
403#define IWL_INVALID_RATE 0xFF
404#define IWL_INVALID_VALUE -1
405
bc47279f 406/**
6def9761 407 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
408 * @txq_id: Tx queue used for Tx attempt
409 * @frame_count: # frames attempted by Tx command
410 * @wait_for_ba: Expect block-ack before next Tx reply
411 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
412 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
413 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
414 * @rate_n_flags: Rate at which Tx was attempted
415 *
416 * If REPLY_TX indicates that aggregation was attempted, driver must wait
417 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
418 * until block ack arrives.
419 */
6def9761 420struct iwl_ht_agg {
5d08cd1d
CH
421 u16 txq_id;
422 u16 frame_count;
423 u16 wait_for_ba;
424 u16 start_idx;
fe01b477 425 u64 bitmap;
5d08cd1d 426 u32 rate_n_flags;
fe01b477
RR
427#define IWL_AGG_OFF 0
428#define IWL_AGG_ON 1
429#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
430#define IWL_EMPTYING_HW_QUEUE_DELBA 3
431 u8 state;
5d08cd1d 432};
fe01b477 433
5d08cd1d 434
6def9761 435struct iwl_tid_data {
5d08cd1d 436 u16 seq_number;
fe01b477 437 u16 tfds_in_queue;
6def9761 438 struct iwl_ht_agg agg;
5d08cd1d
CH
439};
440
6def9761 441struct iwl_hw_key {
5d08cd1d
CH
442 enum ieee80211_key_alg alg;
443 int keylen;
0211ddda 444 u8 keyidx;
5d08cd1d
CH
445 u8 key[32];
446};
447
a78fe754 448union iwl_ht_rate_supp {
5d08cd1d
CH
449 u16 rates;
450 struct {
451 u8 siso_rate;
452 u8 mimo_rate;
453 };
454};
455
5d08cd1d 456#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
bcc693a1
WYG
457
458/*
459 * Maximal MPDU density for TX aggregation
460 * 4 - 2us density
461 * 5 - 4us density
462 * 6 - 8us density
463 * 7 - 16us density
464 */
465#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
466#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
5d08cd1d 467
fad95bf5 468struct iwl_ht_config {
9e0cc6de 469 /* self configuration data */
c812ee24
JB
470 bool is_ht;
471 bool is_40mhz;
02bb1bea 472 bool single_chain_sufficient;
ba37a3d0 473 enum ieee80211_smps_mode smps; /* current smps mode */
9e0cc6de 474 /* BSS related data */
5d08cd1d 475 u8 extension_chan_offset;
9e0cc6de
RR
476 u8 ht_protection;
477 u8 non_GF_STA_present;
5d08cd1d 478};
5d08cd1d 479
5d08cd1d 480/* QoS structures */
1ff50bda 481struct iwl_qos_info {
5d08cd1d 482 int qos_active;
1ff50bda 483 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 484};
5d08cd1d 485
fe6b23dd
RC
486/*
487 * Structure should be accessed with sta_lock held. When station addition
488 * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only
489 * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock
490 * held.
491 */
6def9761 492struct iwl_station_entry {
133636de 493 struct iwl_addsta_cmd sta;
6def9761 494 struct iwl_tid_data tid[MAX_TID_COUNT];
5d08cd1d 495 u8 used;
6def9761 496 struct iwl_hw_key keyinfo;
fe6b23dd 497 struct iwl_link_quality_cmd *lq;
5d08cd1d
CH
498};
499
8d9698b3
RC
500/*
501 * iwl_station_priv: Driver's private station information
502 *
503 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
504 * in the structure for use by driver. This structure is places in that
505 * space.
8d9698b3
RC
506 */
507struct iwl_station_priv {
508 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
509 atomic_t pending_frames;
510 bool client;
511 bool asleep;
8d9698b3
RC
512};
513
5d08cd1d
CH
514/* one for each uCode image (inst/data, boot/init/runtime) */
515struct fw_desc {
516 void *v_addr; /* access by driver */
517 dma_addr_t p_addr; /* access by card's busmaster DMA */
518 u32 len; /* bytes */
519};
520
dd7a2509 521/* v1/v2 uCode file layout */
cc0f555d
JS
522struct iwl_ucode_header {
523 __le32 ver; /* major/minor/API/serial */
524 union {
525 struct {
526 __le32 inst_size; /* bytes of runtime code */
527 __le32 data_size; /* bytes of runtime data */
528 __le32 init_size; /* bytes of init code */
529 __le32 init_data_size; /* bytes of init data */
530 __le32 boot_size; /* bytes of bootstrap code */
531 u8 data[0]; /* in same order as sizes */
532 } v1;
533 struct {
534 __le32 build; /* build number */
535 __le32 inst_size; /* bytes of runtime code */
536 __le32 data_size; /* bytes of runtime data */
537 __le32 init_size; /* bytes of init code */
538 __le32 init_data_size; /* bytes of init data */
539 __le32 boot_size; /* bytes of bootstrap code */
540 u8 data[0]; /* in same order as sizes */
541 } v2;
542 } u;
5d08cd1d
CH
543};
544
dd7a2509
JB
545/*
546 * new TLV uCode file layout
547 *
548 * The new TLV file format contains TLVs, that each specify
549 * some piece of data. To facilitate "groups", for example
550 * different instruction image with different capabilities,
551 * bundled with the same init image, an alternative mechanism
552 * is provided:
553 * When the alternative field is 0, that means that the item
554 * is always valid. When it is non-zero, then it is only
555 * valid in conjunction with items of the same alternative,
556 * in which case the driver (user) selects one alternative
557 * to use.
558 */
559
560enum iwl_ucode_tlv_type {
561 IWL_UCODE_TLV_INVALID = 0, /* unused */
562 IWL_UCODE_TLV_INST = 1,
563 IWL_UCODE_TLV_DATA = 2,
564 IWL_UCODE_TLV_INIT = 3,
565 IWL_UCODE_TLV_INIT_DATA = 4,
566 IWL_UCODE_TLV_BOOT = 5,
567 IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */
568};
569
570struct iwl_ucode_tlv {
571 __le16 type; /* see above */
572 __le16 alternative; /* see comment */
573 __le32 length; /* not including type/length fields */
574 u8 data[0];
575} __attribute__ ((packed));
576
577#define IWL_TLV_UCODE_MAGIC 0x0a4c5749
578
579struct iwl_tlv_ucode_header {
580 /*
581 * The TLV style ucode header is distinguished from
582 * the v1/v2 style header by first four bytes being
583 * zero, as such is an invalid combination of
584 * major/minor/API/serial versions.
585 */
586 __le32 zero;
587 __le32 magic;
588 u8 human_readable[64];
589 __le32 ver; /* major/minor/API/serial */
590 __le32 build;
591 __le64 alternatives; /* bitmask of valid alternatives */
592 /*
593 * The data contained herein has a TLV layout,
594 * see above for the TLV header and types.
595 * Note that each TLV is padded to a length
596 * that is a multiple of 4 for alignment.
597 */
598 u8 data[0];
599};
600
bb8c093b 601struct iwl4965_ibss_seq {
5d08cd1d
CH
602 u8 mac[ETH_ALEN];
603 u16 seq_num;
604 u16 frag_num;
605 unsigned long packet_time;
606 struct list_head list;
607};
608
f0832f13
EG
609struct iwl_sensitivity_ranges {
610 u16 min_nrg_cck;
611 u16 max_nrg_cck;
612
613 u16 nrg_th_cck;
614 u16 nrg_th_ofdm;
615
616 u16 auto_corr_min_ofdm;
617 u16 auto_corr_min_ofdm_mrc;
618 u16 auto_corr_min_ofdm_x1;
619 u16 auto_corr_min_ofdm_mrc_x1;
620
621 u16 auto_corr_max_ofdm;
622 u16 auto_corr_max_ofdm_mrc;
623 u16 auto_corr_max_ofdm_x1;
624 u16 auto_corr_max_ofdm_mrc_x1;
625
626 u16 auto_corr_max_cck;
627 u16 auto_corr_max_cck_mrc;
628 u16 auto_corr_min_cck;
629 u16 auto_corr_min_cck_mrc;
55036d66
WYG
630
631 u16 barker_corr_th_min;
632 u16 barker_corr_th_min_mrc;
633 u16 nrg_th_cca;
f0832f13
EG
634};
635
099b40b7 636
b5047f78
TW
637#define KELVIN_TO_CELSIUS(x) ((x)-273)
638#define CELSIUS_TO_KELVIN(x) ((x)+273)
639
640
bc47279f 641/**
5425e490 642 * struct iwl_hw_params
bc47279f 643 * @max_txq_num: Max # Tx queues supported
f3f911d1 644 * @dma_chnl_num: Number of Tx DMA/FIFO channels
4ddbb7d0 645 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 646 * @tfd_size: TFD size
099b40b7
RR
647 * @tx/rx_chains_num: Number of TX/RX chains
648 * @valid_tx/rx_ant: usable antennas
bc47279f 649 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 650 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 651 * @rx_page_order: Rx buffer page order
141c43a3 652 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f
BC
653 * @max_stations:
654 * @bcast_sta_id:
7aafef1c 655 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
656 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
657 * @sw_crypto: 0 for hw, 1 for sw
658 * @max_xxx_size: for ucode uses
659 * @ct_kill_threshold: temperature threshold
a96a27f9 660 * @calib_init_cfg: setup initial calibrations for the hw
f0832f13 661 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 662 */
5425e490 663struct iwl_hw_params {
f3f911d1
ZY
664 u8 max_txq_num;
665 u8 dma_chnl_num;
4ddbb7d0 666 u16 scd_bc_tbls_size;
a8e74e27 667 u32 tfd_size;
ec35cf2a
TW
668 u8 tx_chains_num;
669 u8 rx_chains_num;
670 u8 valid_tx_ant;
671 u8 valid_rx_ant;
5d08cd1d 672 u16 max_rxq_size;
ec35cf2a 673 u16 max_rxq_log;
2f301227 674 u32 rx_page_order;
141c43a3 675 u32 rx_wrt_ptr_reg;
5d08cd1d
CH
676 u8 max_stations;
677 u8 bcast_sta_id;
7aafef1c 678 u8 ht40_channel;
2c2f3b33 679 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
680 u32 max_inst_size;
681 u32 max_data_size;
682 u32 max_bsm_size;
683 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
684 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
685 /* for 1000, 6000 series and up */
be5d56ed 686 u32 calib_init_cfg;
f0832f13 687 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
688};
689
5d08cd1d 690
5d08cd1d
CH
691/******************************************************************************
692 *
a33c2f47
EG
693 * Functions implemented in core module which are forward declared here
694 * for use by iwl-[4-5].c
5d08cd1d 695 *
a33c2f47
EG
696 * NOTE: The implementation of these functions are not hardware specific
697 * which is why they are in the core module files.
5d08cd1d
CH
698 *
699 * Naming convention --
a33c2f47 700 * iwl_ <-- Is part of iwlwifi
5d08cd1d 701 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
bb8c093b
CH
702 * iwl4965_bg_ <-- Called from work queue context
703 * iwl4965_mac_ <-- mac80211 callback
5d08cd1d
CH
704 *
705 ****************************************************************************/
5b9f8cd3
EG
706extern void iwl_update_chain_flags(struct iwl_priv *priv);
707extern int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src);
a33c2f47 708extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 709extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 710extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 711extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
712static inline int iwl_queue_used(const struct iwl_queue *q, int i)
713{
c8106d76 714 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
715 (i >= q->read_ptr && i < q->write_ptr) :
716 !(i < q->read_ptr && i >= q->write_ptr);
717}
718
719
720static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge)
721{
c8c24872
WYG
722 /*
723 * This is for init calibration result and scan command which
724 * required buffer > TFD_MAX_PAYLOAD_SIZE,
725 * the big buffer at end of command array
726 */
fd4abac5
TW
727 if (is_huge)
728 return q->n_window; /* must be power of 2 */
729
730 /* Otherwise, use normal size buffers */
731 return index & (q->n_window - 1);
732}
733
734
4ddbb7d0
TW
735struct iwl_dma_ptr {
736 dma_addr_t dma;
737 void *addr;
b481de9c
ZY
738 size_t size;
739};
740
b481de9c
ZY
741#define IWL_OPERATION_MODE_AUTO 0
742#define IWL_OPERATION_MODE_HT_ONLY 1
743#define IWL_OPERATION_MODE_MIXED 2
744#define IWL_OPERATION_MODE_20MHZ 3
745
3195cdb7
TW
746#define IWL_TX_CRC_SIZE 4
747#define IWL_TX_DELIMITER_SIZE 4
b481de9c 748
b481de9c 749#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 750
b481de9c 751/* Sensitivity and chain noise calibration */
b481de9c 752#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a
WYG
753#define IWL4965_CAL_NUM_BEACONS 20
754#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
755#define MAXIMUM_ALLOWED_PATHLOSS 15
756
b481de9c
ZY
757#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
758
759#define MAX_FA_OFDM 50
760#define MIN_FA_OFDM 5
761#define MAX_FA_CCK 50
762#define MIN_FA_CCK 5
763
b481de9c
ZY
764#define AUTO_CORR_STEP_OFDM 1
765
b481de9c
ZY
766#define AUTO_CORR_STEP_CCK 3
767#define AUTO_CORR_MAX_TH_CCK 160
768
b481de9c
ZY
769#define NRG_DIFF 2
770#define NRG_STEP_CCK 2
771#define NRG_MARGIN 8
772#define MAX_NUMBER_CCK_NO_FA 100
773
774#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
775
776#define CHAIN_A 0
777#define CHAIN_B 1
778#define CHAIN_C 2
779#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
780#define ALL_BAND_FILTER 0xFF00
781#define IN_BAND_FILTER 0xFF
782#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
783
3195cdb7
TW
784#define NRG_NUM_PREV_STAT_L 20
785#define NUM_RX_CHAINS 3
786
bb8c093b 787enum iwl4965_false_alarm_state {
b481de9c
ZY
788 IWL_FA_TOO_MANY = 0,
789 IWL_FA_TOO_FEW = 1,
790 IWL_FA_GOOD_RANGE = 2,
791};
792
bb8c093b 793enum iwl4965_chain_noise_state {
b481de9c 794 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
795 IWL_CHAIN_NOISE_ACCUMULATE,
796 IWL_CHAIN_NOISE_CALIBRATED,
797 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
798};
799
bb8c093b 800enum iwl4965_calib_enabled_state {
b481de9c
ZY
801 IWL_CALIB_DISABLED = 0, /* must be 0 */
802 IWL_CALIB_ENABLED = 1,
803};
804
f69f42a6
TW
805
806/*
807 * enum iwl_calib
808 * defines the order in which results of initial calibrations
809 * should be sent to the runtime uCode
810 */
811enum iwl_calib {
812 IWL_CALIB_XTAL,
819500c5 813 IWL_CALIB_DC,
f69f42a6
TW
814 IWL_CALIB_LO,
815 IWL_CALIB_TX_IQ,
816 IWL_CALIB_TX_IQ_PERD,
201706ac 817 IWL_CALIB_BASE_BAND,
f69f42a6
TW
818 IWL_CALIB_MAX
819};
820
6e21f2c1
TW
821/* Opaque calibration results */
822struct iwl_calib_result {
823 void *buf;
824 size_t buf_len;
7c616cba
TW
825};
826
dbb983b7
RR
827enum ucode_type {
828 UCODE_NONE = 0,
829 UCODE_INIT,
830 UCODE_RT
831};
832
b481de9c 833/* Sensitivity calib data */
f0832f13 834struct iwl_sensitivity_data {
b481de9c
ZY
835 u32 auto_corr_ofdm;
836 u32 auto_corr_ofdm_mrc;
837 u32 auto_corr_ofdm_x1;
838 u32 auto_corr_ofdm_mrc_x1;
839 u32 auto_corr_cck;
840 u32 auto_corr_cck_mrc;
841
842 u32 last_bad_plcp_cnt_ofdm;
843 u32 last_fa_cnt_ofdm;
844 u32 last_bad_plcp_cnt_cck;
845 u32 last_fa_cnt_cck;
846
847 u32 nrg_curr_state;
848 u32 nrg_prev_state;
849 u32 nrg_value[10];
850 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
851 u32 nrg_silence_ref;
852 u32 nrg_energy_idx;
853 u32 nrg_silence_idx;
854 u32 nrg_th_cck;
855 s32 nrg_auto_corr_silence_diff;
856 u32 num_in_cck_no_fa;
857 u32 nrg_th_ofdm;
55036d66
WYG
858
859 u16 barker_corr_th_min;
860 u16 barker_corr_th_min_mrc;
861 u16 nrg_th_cca;
b481de9c
ZY
862};
863
864/* Chain noise (differential Rx gain) calib data */
f0832f13 865struct iwl_chain_noise_data {
04816448 866 u32 active_chains;
b481de9c
ZY
867 u32 chain_noise_a;
868 u32 chain_noise_b;
869 u32 chain_noise_c;
870 u32 chain_signal_a;
871 u32 chain_signal_b;
872 u32 chain_signal_c;
04816448 873 u16 beacon_count;
b481de9c
ZY
874 u8 disconn_array[NUM_RX_CHAINS];
875 u8 delta_gain_code[NUM_RX_CHAINS];
876 u8 radio_write;
04816448 877 u8 state;
b481de9c
ZY
878};
879
abceddb4
BC
880#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
881#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 882
20594eb0
WYG
883#define IWL_TRAFFIC_ENTRIES (256)
884#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 885
5d08cd1d
CH
886enum {
887 MEASUREMENT_READY = (1 << 0),
888 MEASUREMENT_ACTIVE = (1 << 1),
889};
890
0848e297
WYG
891enum iwl_nvm_type {
892 NVM_DEVICE_TYPE_EEPROM = 0,
893 NVM_DEVICE_TYPE_OTP,
894};
895
415e4993
WYG
896/*
897 * Two types of OTP memory access modes
898 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
899 * based on physical memory addressing
900 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
901 * based on logical memory addressing
902 */
903enum iwl_access_mode {
904 IWL_OTP_ACCESS_ABSOLUTE,
905 IWL_OTP_ACCESS_RELATIVE,
906};
65b7998a
WYG
907
908/**
909 * enum iwl_pa_type - Power Amplifier type
910 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
911 * @IWL_PA_INTERNAL: use Internal only
912 */
913enum iwl_pa_type {
914 IWL_PA_SYSTEM = 0,
740e7f51 915 IWL_PA_INTERNAL = 1,
65b7998a
WYG
916};
917
a83b9141
WYG
918/* interrupt statistics */
919struct isr_statistics {
920 u32 hw;
921 u32 sw;
922 u32 sw_err;
923 u32 sch;
924 u32 alive;
925 u32 rfkill;
926 u32 ctkill;
927 u32 wakeup;
928 u32 rx;
929 u32 rx_handlers[REPLY_MAX];
930 u32 tx;
931 u32 unhandled;
932};
5d08cd1d 933
22fdf3c9
WYG
934#ifdef CONFIG_IWLWIFI_DEBUGFS
935/* management statistics */
936enum iwl_mgmt_stats {
937 MANAGEMENT_ASSOC_REQ = 0,
938 MANAGEMENT_ASSOC_RESP,
939 MANAGEMENT_REASSOC_REQ,
940 MANAGEMENT_REASSOC_RESP,
941 MANAGEMENT_PROBE_REQ,
942 MANAGEMENT_PROBE_RESP,
943 MANAGEMENT_BEACON,
944 MANAGEMENT_ATIM,
945 MANAGEMENT_DISASSOC,
946 MANAGEMENT_AUTH,
947 MANAGEMENT_DEAUTH,
948 MANAGEMENT_ACTION,
949 MANAGEMENT_MAX,
950};
951/* control statistics */
952enum iwl_ctrl_stats {
953 CONTROL_BACK_REQ = 0,
954 CONTROL_BACK,
955 CONTROL_PSPOLL,
956 CONTROL_RTS,
957 CONTROL_CTS,
958 CONTROL_ACK,
959 CONTROL_CFEND,
960 CONTROL_CFENDACK,
961 CONTROL_MAX,
962};
963
964struct traffic_stats {
965 u32 mgmt[MANAGEMENT_MAX];
966 u32 ctrl[CONTROL_MAX];
967 u32 data_cnt;
968 u64 data_bytes;
969};
970#else
971struct traffic_stats {
972 u64 data_bytes;
973};
974#endif
975
0924e519
WYG
976/*
977 * iwl_switch_rxon: "channel switch" structure
978 *
979 * @ switch_in_progress: channel switch in progress
980 * @ channel: new channel
981 */
982struct iwl_switch_rxon {
983 bool switch_in_progress;
984 __le16 channel;
985};
986
a9e1cb6a
WYG
987/*
988 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
989 * to perform continuous uCode event logging operation if enabled
990 */
991#define UCODE_TRACE_PERIOD (100)
992
993/*
994 * iwl_event_log: current uCode event log position
995 *
996 * @ucode_trace: enable/disable ucode continuous trace timer
997 * @num_wraps: how many times the event buffer wraps
998 * @next_entry: the entry just before the next one that uCode would fill
999 * @non_wraps_count: counter for no wrap detected when dump ucode events
1000 * @wraps_once_count: counter for wrap once detected when dump ucode events
1001 * @wraps_more_count: counter for wrap more than once detected
1002 * when dump ucode events
1003 */
1004struct iwl_event_log {
1005 bool ucode_trace;
1006 u32 num_wraps;
1007 u32 next_entry;
1008 int non_wraps_count;
1009 int wraps_once_count;
1010 int wraps_more_count;
1011};
1012
2be76703
WYG
1013/*
1014 * host interrupt timeout value
1015 * used with setting interrupt coalescing timer
1016 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1017 *
1018 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1019 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1020 */
1021#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
1022#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
1023#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
1024#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1025#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1026#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1027
3e4fb5fa
TAN
1028/*
1029 * This is the threshold value of plcp error rate per 100mSecs. It is
1030 * used to set and check for the validity of plcp_delta.
1031 */
1032#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (0)
1033#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
1034#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 1035#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa
TAN
1036#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
1037
8a472da4
WYG
1038#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
1039#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1040
b74e31a9
WYG
1041/* timer constants use to monitor and recover stuck tx queues in mSecs */
1042#define IWL_MONITORING_PERIOD (1000)
1043#define IWL_ONE_HUNDRED_MSECS (100)
1044#define IWL_SIXTY_SECS (60000)
1045
a93e7973
WYG
1046enum iwl_reset {
1047 IWL_RF_RESET = 0,
1048 IWL_FW_RESET,
8a472da4
WYG
1049 IWL_MAX_FORCE_RESET,
1050};
1051
1052struct iwl_force_reset {
1053 int reset_request_count;
1054 int reset_success_count;
1055 int reset_reject_count;
1056 unsigned long reset_duration;
1057 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1058};
1059
c79dd5b5 1060struct iwl_priv {
5d08cd1d
CH
1061
1062 /* ieee device used by generic ieee processing code */
1063 struct ieee80211_hw *hw;
1064 struct ieee80211_channel *ieee_channels;
1065 struct ieee80211_rate *ieee_rates;
82b9a121 1066 struct iwl_cfg *cfg;
5d08cd1d
CH
1067
1068 /* temporary frame storage list */
1069 struct list_head free_frames;
1070 int frames_count;
1071
8318d78a 1072 enum ieee80211_band band;
2f301227 1073 int alloc_rxb_page;
5d08cd1d 1074
c79dd5b5 1075 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1076 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1077
8318d78a 1078 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1079
5d08cd1d 1080 /* spectrum measurement report caching */
2aa6ab86 1081 struct iwl_spectrum_notification measure_report;
5d08cd1d 1082 u8 measurement_status;
81963d68 1083
5d08cd1d
CH
1084 /* ucode beacon time */
1085 u32 ucode_beacon_time;
a13d276f 1086 int missed_beacon_threshold;
5d08cd1d 1087
3e4fb5fa
TAN
1088 /* storing the jiffies when the plcp error rate is received */
1089 unsigned long plcp_jiffies;
1090
a93e7973 1091 /* force reset */
8a472da4 1092 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1093
bb8c093b 1094 /* we allocate array of iwl4965_channel_info for NIC's valid channels.
5d08cd1d 1095 * Access via channel # using indirect index array */
bf85ea4f 1096 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1097 u8 channel_count; /* # of channels */
1098
5d08cd1d
CH
1099 /* thermal calibration */
1100 s32 temperature; /* degrees Kelvin */
1101 s32 last_temperature;
1102
7c616cba 1103 /* init calibration results */
6e21f2c1 1104 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1105
5d08cd1d 1106 /* Scan related variables */
5d08cd1d 1107 unsigned long scan_start;
5d08cd1d 1108 unsigned long scan_start_tsf;
811ecc99 1109 void *scan_cmd;
00700ee0 1110 enum ieee80211_band scan_band;
1ecf9fc1 1111 struct cfg80211_scan_request *scan_request;
afbdd69a 1112 bool is_internal_short_scan;
76eff18b
TW
1113 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1114 u8 mgmt_tx_ant;
5d08cd1d
CH
1115
1116 /* spinlock */
1117 spinlock_t lock; /* protect general shared data */
1118 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1119 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d 1120 struct mutex mutex;
d2dfe6df 1121 struct mutex sync_cmd_mutex; /* enable serialization of sync commands */
5d08cd1d
CH
1122
1123 /* basic pci-network driver stuff */
1124 struct pci_dev *pci_dev;
1125
1126 /* pci hardware address support */
1127 void __iomem *hw_base;
b661c819
TW
1128 u32 hw_rev;
1129 u32 hw_wa_rev;
1130 u8 rev_id;
5d08cd1d
CH
1131
1132 /* uCode images, save to reload in case of failure */
b08dfd04 1133 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1134 u32 ucode_ver; /* version of ucode, copy of
1135 iwl_ucode.ver */
5d08cd1d
CH
1136 struct fw_desc ucode_code; /* runtime inst */
1137 struct fw_desc ucode_data; /* runtime data original */
1138 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1139 struct fw_desc ucode_init; /* initialization inst */
1140 struct fw_desc ucode_init_data; /* initialization data */
1141 struct fw_desc ucode_boot; /* bootstrap inst */
dbb983b7
RR
1142 enum ucode_type ucode_type;
1143 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1144 char firmware_name[25];
5d08cd1d
CH
1145
1146
3195c1f3 1147 struct iwl_rxon_time_cmd rxon_timing;
5d08cd1d
CH
1148
1149 /* We declare this const so it can only be
1150 * changed via explicit cast within the
1151 * routines that actually update the physical
1152 * hardware */
c1adf9fb
GG
1153 const struct iwl_rxon_cmd active_rxon;
1154 struct iwl_rxon_cmd staging_rxon;
5d08cd1d 1155
0924e519
WYG
1156 struct iwl_switch_rxon switch_rxon;
1157
5d08cd1d
CH
1158 /* 1st responses from initialize and runtime uCode images.
1159 * 4965's initialize alive response contains some calibration data. */
885ba202
TW
1160 struct iwl_init_alive_resp card_alive_init;
1161 struct iwl_alive_resp card_alive;
5d08cd1d 1162
ab53d8af
MA
1163 unsigned long last_blink_time;
1164 u8 last_blink_rate;
1165 u8 allow_blinking;
1166 u64 led_tpt;
e932a609 1167
5d08cd1d 1168 u16 active_rate;
5d08cd1d 1169
5d08cd1d 1170 u8 start_calib;
f0832f13
EG
1171 struct iwl_sensitivity_data sensitivity_data;
1172 struct iwl_chain_noise_data chain_noise_data;
5d08cd1d 1173 __le16 sensitivity_tbl[HD_TABLE_SIZE];
5d08cd1d 1174
fad95bf5 1175 struct iwl_ht_config current_ht_config;
5d08cd1d 1176
5d08cd1d 1177 /* Rate scaling data */
5d08cd1d
CH
1178 u8 retry_rate;
1179
1180 wait_queue_head_t wait_command_queue;
1181
1182 int activity_timer_active;
1183
1184 /* Rx and Tx DMA processing queues */
a55360e4 1185 struct iwl_rx_queue rxq;
88804e2b 1186 struct iwl_tx_queue *txq;
5d08cd1d 1187 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1188 struct iwl_dma_ptr kw; /* keep warm address */
1189 struct iwl_dma_ptr scd_bc_tbls;
1190
5d08cd1d
CH
1191 u32 scd_base_addr; /* scheduler sram base address */
1192
1193 unsigned long status;
5d08cd1d 1194
19758bef 1195 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1196 struct traffic_stats tx_stats;
1197 struct traffic_stats rx_stats;
19758bef 1198
a83b9141
WYG
1199 /* counts interrupts */
1200 struct isr_statistics isr_stats;
1201
5da4b55f 1202 struct iwl_power_mgr power_data;
3ad3b92a 1203 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1204
8f91aecb 1205 struct iwl_notif_statistics statistics;
92a35bda
WYG
1206#ifdef CONFIG_IWLWIFI_DEBUG
1207 struct iwl_notif_statistics accum_statistics;
e3ef2164
WYG
1208 struct iwl_notif_statistics delta_statistics;
1209 struct iwl_notif_statistics max_delta;
92a35bda 1210#endif
5d08cd1d
CH
1211
1212 /* context information */
5d08cd1d 1213 u8 bssid[ETH_ALEN];
5d08cd1d
CH
1214 u8 mac_addr[ETH_ALEN];
1215
1216 /*station table variables */
1217 spinlock_t sta_lock;
1218 int num_stations;
6def9761 1219 struct iwl_station_entry stations[IWL_STATION_COUNT];
72e15d71 1220 struct iwl_wep_key wep_keys[WEP_KEYS_MAX]; /* protected by mutex */
6974e363 1221 u8 key_mapping_key;
80fb47a1 1222 unsigned long ucode_key_table;
5d08cd1d 1223
e4e72fb4
JB
1224 /* queue refcounts */
1225#define IWL_MAX_HW_QUEUES 32
1226 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1227 /* for each AC */
1228 atomic_t queue_stop_count[4];
1229
5d08cd1d 1230 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1231 u8 is_open;
5d08cd1d
CH
1232
1233 u8 mac80211_registered;
5d08cd1d 1234
af6b8ee3 1235 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1236 u8 *eeprom;
0848e297 1237 int nvm_device_type;
073d3f5f 1238 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1239
05c914fe 1240 enum nl80211_iftype iw_mode;
5d08cd1d
CH
1241
1242 struct sk_buff *ibss_beacon;
1243
1244 /* Last Rx'd beacon timestamp */
3109ece1 1245 u64 timestamp;
32bfd35d 1246 struct ieee80211_vif *vif;
5d08cd1d 1247
ee525d13
JB
1248 union {
1249#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1250 struct {
1251 void *shared_virt;
1252 dma_addr_t shared_phys;
1253
1254 struct delayed_work thermal_periodic;
1255 struct delayed_work rfkill_poll;
1256
1257 struct iwl3945_notif_statistics statistics;
17f36fc6
AK
1258#ifdef CONFIG_IWLWIFI_DEBUG
1259 struct iwl3945_notif_statistics accum_statistics;
1260 struct iwl3945_notif_statistics delta_statistics;
1261 struct iwl3945_notif_statistics max_delta;
1262#endif
ee525d13
JB
1263
1264 u32 sta_supp_rates;
e99f168c
JB
1265 int last_rx_rssi; /* From Rx packet statistics */
1266
1267 /* Rx'd packet timing information */
1268 u32 last_beacon_time;
1269 u64 last_tsf;
67d613ae
JB
1270
1271 /*
1272 * each calibration channel group in the
1273 * EEPROM has a derived clip setting for
1274 * each rate.
1275 */
1276 const struct iwl3945_clip_group clip_groups[5];
1277
ee525d13 1278 } _3945;
a4c8b2a6
JB
1279#endif
1280#if defined(CONFIG_IWLAGN) || defined(CONFIG_IWLAGN_MODULE)
1281 struct {
1282 /* INT ICT Table */
1283 __le32 *ict_tbl;
1284 void *ict_tbl_vir;
1285 dma_addr_t ict_tbl_dma;
1286 dma_addr_t aligned_ict_tbl_dma;
1287 int ict_index;
1288 u32 inta;
1289 bool use_ict;
d5a0ffa3
WYG
1290 /*
1291 * reporting the number of tids has AGG on. 0 means
1292 * no AGGREGATION
1293 */
1294 u8 agg_tids_count;
05d57520
JB
1295
1296 struct iwl_rx_phy_res last_phy_res;
1297 bool last_phy_res_valid;
a15707d8
RC
1298
1299 struct completion firmware_loading_complete;
a4c8b2a6 1300 } _agn;
ee525d13
JB
1301#endif
1302 };
1303
5425e490 1304 struct iwl_hw_params hw_params;
4ddbb7d0 1305
40cefda9 1306 u32 inta_mask;
5d08cd1d 1307
1ff50bda 1308 struct iwl_qos_info qos_data;
5d08cd1d
CH
1309
1310 struct workqueue_struct *workqueue;
1311
5d08cd1d 1312 struct work_struct restart;
5d08cd1d
CH
1313 struct work_struct scan_completed;
1314 struct work_struct rx_replenish;
5d08cd1d 1315 struct work_struct abort_scan;
5d08cd1d 1316 struct work_struct beacon_update;
a28027cd
WYG
1317 struct work_struct tt_work;
1318 struct work_struct ct_enter;
1319 struct work_struct ct_exit;
88be0264 1320 struct work_struct start_internal_scan;
5d08cd1d
CH
1321
1322 struct tasklet_struct irq_tasklet;
1323
1324 struct delayed_work init_alive_start;
1325 struct delayed_work alive_start;
5d08cd1d 1326 struct delayed_work scan_check;
4a8a4322 1327
630fe9b6
TW
1328 /* TX Power */
1329 s8 tx_power_user_lmt;
dc1b0973 1330 s8 tx_power_device_lmt;
ae16fc3c 1331 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
5d08cd1d 1332
5d08cd1d 1333
d08853a3 1334#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1335 /* debugging info */
3d816c77
RC
1336 u32 debug_level; /* per device debugging will override global
1337 iwl_debug_level if set */
5d08cd1d
CH
1338 u32 framecnt_to_us;
1339 atomic_t restrict_refcnt;
1e4247d4 1340 bool disable_ht40;
712b6cf5
TW
1341#ifdef CONFIG_IWLWIFI_DEBUGFS
1342 /* debugfs */
20594eb0
WYG
1343 u16 tx_traffic_idx;
1344 u16 rx_traffic_idx;
1345 u8 *tx_traffic;
1346 u8 *rx_traffic;
4c84a8f1
JB
1347 struct dentry *debugfs_dir;
1348 u32 dbgfs_sram_offset, dbgfs_sram_len;
712b6cf5
TW
1349#endif /* CONFIG_IWLWIFI_DEBUGFS */
1350#endif /* CONFIG_IWLWIFI_DEBUG */
5d08cd1d
CH
1351
1352 struct work_struct txpower_work;
445c2dff
TW
1353 u32 disable_sens_cal;
1354 u32 disable_chain_noise_cal;
203566f3 1355 u32 disable_tx_power_cal;
16e727e8 1356 struct work_struct run_time_calib_work;
5d08cd1d 1357 struct timer_list statistics_periodic;
a9e1cb6a 1358 struct timer_list ucode_trace;
b74e31a9 1359 struct timer_list monitor_recover;
086ed117 1360 bool hw_ready;
a9e1cb6a
WYG
1361
1362 struct iwl_event_log event_log;
c79dd5b5 1363}; /*iwl_priv */
5d08cd1d 1364
36470749
RR
1365static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1366{
1367 set_bit(txq_id, &priv->txq_ctx_active_msk);
1368}
1369
1370static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1371{
1372 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1373}
1374
994d31f7 1375#ifdef CONFIG_IWLWIFI_DEBUG
a332f8d6 1376const char *iwl_get_tx_fail_reason(u32 status);
3d816c77
RC
1377/*
1378 * iwl_get_debug_level: Return active debug level for device
1379 *
1380 * Using sysfs it is possible to set per device debug level. This debug
1381 * level will be used if set, otherwise the global debug level which can be
1382 * set via module parameter is used.
1383 */
1384static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1385{
1386 if (priv->debug_level)
1387 return priv->debug_level;
1388 else
1389 return iwl_debug_level;
1390}
a332f8d6
TW
1391#else
1392static inline const char *iwl_get_tx_fail_reason(u32 status) { return ""; }
3d816c77
RC
1393
1394static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1395{
1396 return iwl_debug_level;
1397}
a332f8d6
TW
1398#endif
1399
1400
a332f8d6
TW
1401static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1402 int txq_id, int idx)
1403{
1404 if (priv->txq[txq_id].txb[idx].skb[0])
1405 return (struct ieee80211_hdr *)priv->txq[txq_id].
1406 txb[idx].skb[0]->data;
1407 return NULL;
1408}
a332f8d6
TW
1409
1410
3109ece1 1411static inline int iwl_is_associated(struct iwl_priv *priv)
5d08cd1d
CH
1412{
1413 return (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1414}
1415
bf85ea4f 1416static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1417{
1418 if (ch_info == NULL)
1419 return 0;
1420 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1421}
1422
bf85ea4f 1423static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1424{
1425 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1426}
1427
bf85ea4f 1428static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1429{
8318d78a 1430 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1431}
1432
bf85ea4f 1433static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1434{
8318d78a 1435 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1436}
1437
bf85ea4f 1438static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1439{
1440 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1441}
1442
bf85ea4f 1443static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1444{
1445 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1446}
1447
64a76b50
ZY
1448static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1449{
1450 __free_pages(page, priv->hw_params.rx_page_order);
1451 priv->alloc_rxb_page--;
1452}
1453
1454static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1455{
1456 free_pages(page, priv->hw_params.rx_page_order);
1457 priv->alloc_rxb_page--;
1458}
be1f3ab6 1459#endif /* __iwl_dev_h__ */