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df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
1f447808 5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
df48c323
TW		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
df48c323
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
8ccde88a 31#include <linux/etherdevice.h>
d43c36dc 32#include <linux/sched.h>
1d0a082d 33#include <net/mac80211.h>
df48c323 34
6bc913bd 35#include "iwl-eeprom.h"
3e0d4cb1 36#include "iwl-dev.h" /* FIXME: remove */
19335774 37#include "iwl-debug.h"
df48c323 38#include "iwl-core.h"
b661c819 39#include "iwl-io.h"
5da4b55f 40#include "iwl-power.h"
83dde8c9 41#include "iwl-sta.h"
ef850d7c 42#include "iwl-helpers.h"
df48c323 43
1d0a082d 44
df48c323
TW		 45MODULE_DESCRIPTION("iwl core");
46MODULE_VERSION(IWLWIFI_VERSION);
a7b75207 47MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
712b6cf5 48MODULE_LICENSE("GPL");
df48c323 49
06702a73
WYG		 50/*
51 * set bt_coex_active to true, uCode will do kill/defer
52 * every time the priority line is asserted (BT is sending signals on the
53 * priority line in the PCIx).
54 * set bt_coex_active to false, uCode will ignore the BT activity and
55 * perform the normal operation
56 *
57 * User might experience transmit issue on some platform due to WiFi/BT
58 * co-exist problem. The possible behaviors are:
59 * Able to scan and finding all the available AP
60 * Not able to associate with any AP
61 * On those platforms, WiFi communication can be restored by set
62 * "bt_coex_active" module parameter to "false"
63 *
64 * default: bt_coex_active = true (BT_COEX_ENABLE)
65 */
66static bool bt_coex_active = true;
67module_param(bt_coex_active, bool, S_IRUGO);
68MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist\n");
69
1933ac4d
WYG		 70static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
71 {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
72 0, COEX_UNASSOC_IDLE_FLAGS},
73 {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
74 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
75 {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
76 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
77 {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
78 0, COEX_CALIBRATION_FLAGS},
79 {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
80 0, COEX_PERIODIC_CALIBRATION_FLAGS},
81 {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
82 0, COEX_CONNECTION_ESTAB_FLAGS},
83 {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
84 0, COEX_ASSOCIATED_IDLE_FLAGS},
85 {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
86 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
87 {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
88 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
89 {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
90 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
91 {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
92 {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
93 {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
94 0, COEX_STAND_ALONE_DEBUG_FLAGS},
95 {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
96 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
97 {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
98 {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
99};
100
c7de35cd
RR		 101#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
102 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
103 IWL_RATE_SISO_##s##M_PLCP, \
104 IWL_RATE_MIMO2_##s##M_PLCP,\
105 IWL_RATE_MIMO3_##s##M_PLCP,\
106 IWL_RATE_##r##M_IEEE, \
107 IWL_RATE_##ip##M_INDEX, \
108 IWL_RATE_##in##M_INDEX, \
109 IWL_RATE_##rp##M_INDEX, \
110 IWL_RATE_##rn##M_INDEX, \
111 IWL_RATE_##pp##M_INDEX, \
112 IWL_RATE_##np##M_INDEX }
113
a562a9dd
RC		 114u32 iwl_debug_level;
115EXPORT_SYMBOL(iwl_debug_level);
116
ef850d7c
MA		 117static irqreturn_t iwl_isr(int irq, void *data);
118
c7de35cd
RR		 119/*
120 * Parameter order:
121 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
122 *
123 * If there isn't a valid next or previous rate then INV is used which
124 * maps to IWL_RATE_INVALID
125 *
126 */
1826dcc0 127const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 128 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
129 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
130 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
131 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
132 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
133 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
134 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
135 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
136 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
137 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
138 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
139 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
140 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
141 /* FIXME:RS: ^^ should be INV (legacy) */
142};
1826dcc0 143EXPORT_SYMBOL(iwl_rates);
c7de35cd 144
e7d326ac
TW		 145/**
146 * translate ucode response to mac80211 tx status control values
147 */
148void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 149 struct ieee80211_tx_info *info)
e7d326ac 150{
e6a9854b 151 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 152
e6a9854b 153 info->antenna_sel_tx =
e7d326ac
TW		 154 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
155 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 156 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 157 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 158 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
7aafef1c 159 if (rate_n_flags & RATE_MCS_HT40_MSK)
e6a9854b 160 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 161 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 162 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 163 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 164 r->flags |= IEEE80211_TX_RC_SHORT_GI;
31513be8 165 r->idx = iwl_hwrate_to_mac80211_idx(rate_n_flags, info->band);
e7d326ac
TW		 166}
167EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
168
169int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
170{
171 int idx = 0;
172
173 /* HT rate format */
174 if (rate_n_flags & RATE_MCS_HT_MSK) {
175 idx = (rate_n_flags & 0xff);
176
60d32215
DH		 177 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
178 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
179 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 180 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
181
182 idx += IWL_FIRST_OFDM_RATE;
183 /* skip 9M not supported in ht*/
184 if (idx >= IWL_RATE_9M_INDEX)
185 idx += 1;
186 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
187 return idx;
188
189 /* legacy rate format, search for match in table */
190 } else {
191 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
192 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
193 return idx;
194 }
195
196 return -1;
197}
198EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
199
31513be8
DH		 200int iwl_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
201{
202 int idx = 0;
203 int band_offset = 0;
204
205 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
206 if (rate_n_flags & RATE_MCS_HT_MSK) {
207 idx = (rate_n_flags & 0xff);
208 return idx;
209 /* Legacy rate format, search for match in table */
210 } else {
211 if (band == IEEE80211_BAND_5GHZ)
212 band_offset = IWL_FIRST_OFDM_RATE;
213 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
214 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
215 return idx - band_offset;
216 }
217
218 return -1;
219}
220
76eff18b
TW		 221u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
222{
223 int i;
224 u8 ind = ant;
225 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
226 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
227 if (priv->hw_params.valid_tx_ant & BIT(ind))
228 return ind;
229 }
230 return ant;
231}
47ff65c4 232EXPORT_SYMBOL(iwl_toggle_tx_ant);
57bd1bea
TW		 233
234const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
235EXPORT_SYMBOL(iwl_bcast_addr);
236
237
1d0a082d
AK		 238/* This function both allocates and initializes hw and priv. */
239struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
240 struct ieee80211_ops *hw_ops)
241{
242 struct iwl_priv *priv;
243
244 /* mac80211 allocates memory for this device instance, including
245 * space for this driver's private structure */
246 struct ieee80211_hw *hw =
247 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
248 if (hw == NULL) {
a3139c59
SO		 249 printk(KERN_ERR "%s: Can not allocate network device\n",
250 cfg->name);
1d0a082d
AK		 251 goto out;
252 }
253
254 priv = hw->priv;
255 priv->hw = hw;
256
257out:
258 return hw;
259}
260EXPORT_SYMBOL(iwl_alloc_all);
261
b661c819
TW		 262void iwl_hw_detect(struct iwl_priv *priv)
263{
264 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
265 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
266 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
267}
268EXPORT_SYMBOL(iwl_hw_detect);
269
1053d35f
RR		 270int iwl_hw_nic_init(struct iwl_priv *priv)
271{
272 unsigned long flags;
273 struct iwl_rx_queue *rxq = &priv->rxq;
274 int ret;
275
276 /* nic_init */
1053d35f 277 spin_lock_irqsave(&priv->lock, flags);
1b73af82 278 priv->cfg->ops->lib->apm_ops.init(priv);
74ba67ed 279
2be76703
WYG		 280 /* Set interrupt coalescing calibration timer to default (512 usecs) */
281 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
74ba67ed 282
1053d35f
RR		 283 spin_unlock_irqrestore(&priv->lock, flags);
284
285 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
286
287 priv->cfg->ops->lib->apm_ops.config(priv);
288
289 /* Allocate the RX queue, or reset if it is already allocated */
290 if (!rxq->bd) {
291 ret = iwl_rx_queue_alloc(priv);
292 if (ret) {
15b1687c 293 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1053d35f
RR		 294 return -ENOMEM;
295 }
296 } else
297 iwl_rx_queue_reset(priv, rxq);
298
299 iwl_rx_replenish(priv);
300
301 iwl_rx_init(priv, rxq);
302
303 spin_lock_irqsave(&priv->lock, flags);
304
305 rxq->need_update = 1;
306 iwl_rx_queue_update_write_ptr(priv, rxq);
307
308 spin_unlock_irqrestore(&priv->lock, flags);
309
310 /* Allocate and init all Tx and Command queues */
311 ret = iwl_txq_ctx_reset(priv);
312 if (ret)
313 return ret;
314
315 set_bit(STATUS_INIT, &priv->status);
316
317 return 0;
318}
319EXPORT_SYMBOL(iwl_hw_nic_init);
320
14d2aac5
AK		 321/*
322 * QoS support
323*/
324void iwl_activate_qos(struct iwl_priv *priv, u8 force)
325{
326 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
327 return;
328
329 priv->qos_data.def_qos_parm.qos_flags = 0;
330
331 if (priv->qos_data.qos_cap.q_AP.queue_request &&
332 !priv->qos_data.qos_cap.q_AP.txop_request)
333 priv->qos_data.def_qos_parm.qos_flags |=
334 QOS_PARAM_FLG_TXOP_TYPE_MSK;
335 if (priv->qos_data.qos_active)
336 priv->qos_data.def_qos_parm.qos_flags |=
337 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
338
339 if (priv->current_ht_config.is_ht)
340 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
341
342 if (force || iwl_is_associated(priv)) {
343 IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
344 priv->qos_data.qos_active,
345 priv->qos_data.def_qos_parm.qos_flags);
346
347 iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
348 sizeof(struct iwl_qosparam_cmd),
349 &priv->qos_data.def_qos_parm, NULL);
350 }
351}
352EXPORT_SYMBOL(iwl_activate_qos);
353
f2c95b04
WYG		 354/*
355 * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
356 * (802.11b) (802.11a/g)
357 * AC_BK 15 1023 7 0 0
358 * AC_BE 15 1023 3 0 0
359 * AC_VI 7 15 2 6.016ms 3.008ms
360 * AC_VO 3 7 2 3.264ms 1.504ms
361 */
c7de35cd 362void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 363{
364 u16 cw_min = 15;
365 u16 cw_max = 1023;
366 u8 aifs = 2;
30dab79e 367 bool is_legacy = false;
bf85ea4f
AK		 368 unsigned long flags;
369 int i;
370
371 spin_lock_irqsave(&priv->lock, flags);
30dab79e
WT		 372 /* QoS always active in AP and ADHOC mode
373 * In STA mode wait for association
374 */
375 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
376 priv->iw_mode == NL80211_IFTYPE_AP)
377 priv->qos_data.qos_active = 1;
378 else
379 priv->qos_data.qos_active = 0;
bf85ea4f 380
30dab79e
WT		 381 /* check for legacy mode */
382 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
383 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
384 (priv->iw_mode == NL80211_IFTYPE_STATION &&
385 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
bf85ea4f
AK		 386 cw_min = 31;
387 is_legacy = 1;
388 }
389
390 if (priv->qos_data.qos_active)
391 aifs = 3;
392
f2c95b04 393 /* AC_BE */
bf85ea4f
AK		 394 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
395 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
396 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
397 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
398 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
399
400 if (priv->qos_data.qos_active) {
f2c95b04 401 /* AC_BK */
bf85ea4f
AK		 402 i = 1;
403 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
404 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
405 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
406 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
407 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
408
f2c95b04 409 /* AC_VI */
bf85ea4f
AK		 410 i = 2;
411 priv->qos_data.def_qos_parm.ac[i].cw_min =
412 cpu_to_le16((cw_min + 1) / 2 - 1);
413 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 414 cpu_to_le16(cw_min);
bf85ea4f
AK		 415 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
416 if (is_legacy)
417 priv->qos_data.def_qos_parm.ac[i].edca_txop =
418 cpu_to_le16(6016);
419 else
420 priv->qos_data.def_qos_parm.ac[i].edca_txop =
421 cpu_to_le16(3008);
422 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
423
f2c95b04 424 /* AC_VO */
bf85ea4f
AK		 425 i = 3;
426 priv->qos_data.def_qos_parm.ac[i].cw_min =
427 cpu_to_le16((cw_min + 1) / 4 - 1);
428 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 429 cpu_to_le16((cw_min + 1) / 2 - 1);
bf85ea4f
AK		 430 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
431 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
432 if (is_legacy)
433 priv->qos_data.def_qos_parm.ac[i].edca_txop =
434 cpu_to_le16(3264);
435 else
436 priv->qos_data.def_qos_parm.ac[i].edca_txop =
437 cpu_to_le16(1504);
438 } else {
439 for (i = 1; i < 4; i++) {
440 priv->qos_data.def_qos_parm.ac[i].cw_min =
441 cpu_to_le16(cw_min);
442 priv->qos_data.def_qos_parm.ac[i].cw_max =
443 cpu_to_le16(cw_max);
444 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
445 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
446 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
447 }
448 }
e1623446 449 IWL_DEBUG_QOS(priv, "set QoS to default \n");
bf85ea4f
AK		 450
451 spin_unlock_irqrestore(&priv->lock, flags);
452}
c7de35cd
RR		 453EXPORT_SYMBOL(iwl_reset_qos);
454
d9fe60de
JB		 455#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
456#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 457static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 458 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 459 enum ieee80211_band band)
460{
39130df3
RR		 461 u16 max_bit_rate = 0;
462 u8 rx_chains_num = priv->hw_params.rx_chains_num;
463 u8 tx_chains_num = priv->hw_params.tx_chains_num;
464
c7de35cd 465 ht_info->cap = 0;
d9fe60de 466 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 467
d9fe60de 468 ht_info->ht_supported = true;
c7de35cd 469
b261793d
DH		 470 if (priv->cfg->ht_greenfield_support)
471 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
d9fe60de 472 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
39130df3 473 max_bit_rate = MAX_BIT_RATE_20_MHZ;
7aafef1c 474 if (priv->hw_params.ht40_channel & BIT(band)) {
d9fe60de
JB		 475 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
476 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
477 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 478 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 479 }
c7de35cd
RR		 480
481 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 482 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 483
484 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
485 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
486
d9fe60de 487 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 488 if (rx_chains_num >= 2)
d9fe60de 489 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 490 if (rx_chains_num >= 3)
d9fe60de 491 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 492
493 /* Highest supported Rx data rate */
494 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 495 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
496 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 497
498 /* Tx MCS capabilities */
d9fe60de 499 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 500 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 501 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
502 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
503 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 504 }
c7de35cd 505}
c7de35cd 506
c7de35cd
RR		 507/**
508 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
509 */
534166de 510int iwlcore_init_geos(struct iwl_priv *priv)
c7de35cd
RR		 511{
512 struct iwl_channel_info *ch;
513 struct ieee80211_supported_band *sband;
514 struct ieee80211_channel *channels;
515 struct ieee80211_channel *geo_ch;
516 struct ieee80211_rate *rates;
517 int i = 0;
518
519 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
520 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
e1623446 521 IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
c7de35cd
RR		 522 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
523 return 0;
524 }
525
526 channels = kzalloc(sizeof(struct ieee80211_channel) *
527 priv->channel_count, GFP_KERNEL);
528 if (!channels)
529 return -ENOMEM;
530
5027309b 531 rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY),
c7de35cd
RR		 532 GFP_KERNEL);
533 if (!rates) {
534 kfree(channels);
535 return -ENOMEM;
536 }
537
538 /* 5.2GHz channels start after the 2.4GHz channels */
539 sband = &priv->bands[IEEE80211_BAND_5GHZ];
540 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
541 /* just OFDM */
542 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
5027309b 543 sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
c7de35cd 544
49779293 545 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 546 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 547 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 548
549 sband = &priv->bands[IEEE80211_BAND_2GHZ];
550 sband->channels = channels;
551 /* OFDM & CCK */
552 sband->bitrates = rates;
5027309b 553 sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
c7de35cd 554
49779293 555 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 556 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 557 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 558
559 priv->ieee_channels = channels;
560 priv->ieee_rates = rates;
561
c7de35cd
RR		 562 for (i = 0; i < priv->channel_count; i++) {
563 ch = &priv->channel_info[i];
564
565 /* FIXME: might be removed if scan is OK */
566 if (!is_channel_valid(ch))
567 continue;
568
569 if (is_channel_a_band(ch))
570 sband = &priv->bands[IEEE80211_BAND_5GHZ];
571 else
572 sband = &priv->bands[IEEE80211_BAND_2GHZ];
573
574 geo_ch = &sband->channels[sband->n_channels++];
575
576 geo_ch->center_freq =
577 ieee80211_channel_to_frequency(ch->channel);
578 geo_ch->max_power = ch->max_power_avg;
579 geo_ch->max_antenna_gain = 0xff;
580 geo_ch->hw_value = ch->channel;
581
582 if (is_channel_valid(ch)) {
583 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
584 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
585
586 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
587 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
588
589 if (ch->flags & EEPROM_CHANNEL_RADAR)
590 geo_ch->flags |= IEEE80211_CHAN_RADAR;
591
7aafef1c 592 geo_ch->flags |= ch->ht40_extension_channel;
4d38c2e8 593
dc1b0973
WYG		 594 if (ch->max_power_avg > priv->tx_power_device_lmt)
595 priv->tx_power_device_lmt = ch->max_power_avg;
c7de35cd
RR		 596 } else {
597 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
598 }
599
e1623446 600 IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 601 ch->channel, geo_ch->center_freq,
602 is_channel_a_band(ch) ? "5.2" : "2.4",
603 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
604 "restricted" : "valid",
605 geo_ch->flags);
606 }
607
608 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
609 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW		 610 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
611 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
a3139c59
SO		 612 priv->pci_dev->device,
613 priv->pci_dev->subsystem_device);
c7de35cd
RR		 614 priv->cfg->sku &= ~IWL_SKU_A;
615 }
616
978785a3 617 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
a3139c59
SO		 618 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
619 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
c7de35cd
RR		 620
621 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
622
623 return 0;
624}
534166de 625EXPORT_SYMBOL(iwlcore_init_geos);
c7de35cd
RR		 626
627/*
628 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
629 */
534166de 630void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 631{
632 kfree(priv->ieee_channels);
633 kfree(priv->ieee_rates);
634 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
635}
534166de 636EXPORT_SYMBOL(iwlcore_free_geos);
c7de35cd 637
37dc70fe
AK		 638/*
639 * iwlcore_rts_tx_cmd_flag: Set rts/cts. 3945 and 4965 only share this
640 * function.
641 */
642void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
643 __le32 *tx_flags)
644{
645 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
646 *tx_flags |= TX_CMD_FLG_RTS_MSK;
647 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
648 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
649 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
650 *tx_flags |= TX_CMD_FLG_CTS_MSK;
651 }
652}
653EXPORT_SYMBOL(iwlcore_rts_tx_cmd_flag);
654
28a6b07a 655static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd 656{
ba37a3d0 657 return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
02bb1bea 658 priv->current_ht_config.single_chain_sufficient;
c7de35cd 659}
963f5517 660
47c5196e
TW		 661static u8 iwl_is_channel_extension(struct iwl_priv *priv,
662 enum ieee80211_band band,
663 u16 channel, u8 extension_chan_offset)
664{
665 const struct iwl_channel_info *ch_info;
666
667 ch_info = iwl_get_channel_info(priv, band, channel);
668 if (!is_channel_valid(ch_info))
669 return 0;
670
d9fe60de 671 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
7aafef1c 672 return !(ch_info->ht40_extension_channel &
689da1b3 673 IEEE80211_CHAN_NO_HT40PLUS);
d9fe60de 674 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
7aafef1c 675 return !(ch_info->ht40_extension_channel &
689da1b3 676 IEEE80211_CHAN_NO_HT40MINUS);
47c5196e
TW		 677
678 return 0;
679}
680
7aafef1c 681u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
d9fe60de 682 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e 683{
fad95bf5 684 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
47c5196e 685
fad95bf5 686 if (!ht_conf->is_ht || !ht_conf->is_40mhz)
47c5196e
TW		 687 return 0;
688
a2b0f02e
WYG		 689 /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
690 * the bit will not set if it is pure 40MHz case
691 */
47c5196e 692 if (sta_ht_inf) {
a2b0f02e 693 if (!sta_ht_inf->ht_supported)
47c5196e
TW		 694 return 0;
695 }
1e4247d4
WYG		 696#ifdef CONFIG_IWLWIFI_DEBUG
697 if (priv->disable_ht40)
698 return 0;
699#endif
611d3eb7
WYG		 700 return iwl_is_channel_extension(priv, priv->band,
701 le16_to_cpu(priv->staging_rxon.channel),
fad95bf5 702 ht_conf->extension_chan_offset);
47c5196e 703}
7aafef1c 704EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
47c5196e 705
2c2f3b33
TW		 706static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
707{
708 u16 new_val = 0;
709 u16 beacon_factor = 0;
710
711 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
712 new_val = beacon_val / beacon_factor;
713
714 if (!new_val)
715 new_val = max_beacon_val;
716
717 return new_val;
718}
719
720void iwl_setup_rxon_timing(struct iwl_priv *priv)
721{
722 u64 tsf;
723 s32 interval_tm, rem;
724 unsigned long flags;
725 struct ieee80211_conf *conf = NULL;
726 u16 beacon_int;
727
728 conf = ieee80211_get_hw_conf(priv->hw);
729
730 spin_lock_irqsave(&priv->lock, flags);
731 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
732 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
733
734 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
735 beacon_int = priv->beacon_int;
736 priv->rxon_timing.atim_window = 0;
737 } else {
738 beacon_int = priv->vif->bss_conf.beacon_int;
739
740 /* TODO: we need to get atim_window from upper stack
741 * for now we set to 0 */
742 priv->rxon_timing.atim_window = 0;
743 }
744
745 beacon_int = iwl_adjust_beacon_interval(beacon_int,
746 priv->hw_params.max_beacon_itrvl * 1024);
747 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
748
749 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
750 interval_tm = beacon_int * 1024;
751 rem = do_div(tsf, interval_tm);
752 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
753
754 spin_unlock_irqrestore(&priv->lock, flags);
755 IWL_DEBUG_ASSOC(priv,
756 "beacon interval %d beacon timer %d beacon tim %d\n",
757 le16_to_cpu(priv->rxon_timing.beacon_interval),
758 le32_to_cpu(priv->rxon_timing.beacon_init_val),
759 le16_to_cpu(priv->rxon_timing.atim_window));
760}
761EXPORT_SYMBOL(iwl_setup_rxon_timing);
762
8ccde88a
SO		 763void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
764{
765 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
766
767 if (hw_decrypt)
768 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
769 else
770 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
771
772}
773EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
774
775/**
776 * iwl_check_rxon_cmd - validate RXON structure is valid
777 *
778 * NOTE: This is really only useful during development and can eventually
779 * be #ifdef'd out once the driver is stable and folks aren't actively
780 * making changes
781 */
782int iwl_check_rxon_cmd(struct iwl_priv *priv)
783{
784 int error = 0;
785 int counter = 1;
786 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
787
788 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
789 error |= le32_to_cpu(rxon->flags &
790 (RXON_FLG_TGJ_NARROW_BAND_MSK |
791 RXON_FLG_RADAR_DETECT_MSK));
792 if (error)
793 IWL_WARN(priv, "check 24G fields %d | %d\n",
794 counter++, error);
795 } else {
796 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
797 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
798 if (error)
799 IWL_WARN(priv, "check 52 fields %d | %d\n",
800 counter++, error);
801 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
802 if (error)
803 IWL_WARN(priv, "check 52 CCK %d | %d\n",
804 counter++, error);
805 }
806 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
807 if (error)
808 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
809
810 /* make sure basic rates 6Mbps and 1Mbps are supported */
811 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
812 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
813 if (error)
814 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
815
816 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
817 if (error)
818 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
819
820 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
821 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
822 if (error)
823 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
824 counter++, error);
825
826 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
827 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
828 if (error)
829 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
830 counter++, error);
831
832 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
833 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
834 if (error)
835 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
836 counter++, error);
837
838 if (error)
839 IWL_WARN(priv, "Tuning to channel %d\n",
840 le16_to_cpu(rxon->channel));
841
842 if (error) {
843 IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
844 return -1;
845 }
846 return 0;
847}
848EXPORT_SYMBOL(iwl_check_rxon_cmd);
849
850/**
851 * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
852 * @priv: staging_rxon is compared to active_rxon
853 *
854 * If the RXON structure is changing enough to require a new tune,
855 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
856 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
857 */
858int iwl_full_rxon_required(struct iwl_priv *priv)
859{
860
861 /* These items are only settable from the full RXON command */
862 if (!(iwl_is_associated(priv)) ||
863 compare_ether_addr(priv->staging_rxon.bssid_addr,
864 priv->active_rxon.bssid_addr) ||
865 compare_ether_addr(priv->staging_rxon.node_addr,
866 priv->active_rxon.node_addr) ||
867 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
868 priv->active_rxon.wlap_bssid_addr) ||
869 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
870 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
871 (priv->staging_rxon.air_propagation !=
872 priv->active_rxon.air_propagation) ||
873 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
874 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
875 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
876 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
c2105fa7
DH		 877 (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
878 priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
8ccde88a
SO		 879 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
880 return 1;
881
882 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
883 * be updated with the RXON_ASSOC command -- however only some
884 * flag transitions are allowed using RXON_ASSOC */
885
886 /* Check if we are not switching bands */
887 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
888 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
889 return 1;
890
891 /* Check if we are switching association toggle */
892 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
893 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
894 return 1;
895
896 return 0;
897}
898EXPORT_SYMBOL(iwl_full_rxon_required);
899
900u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
901{
902 int i;
903 int rate_mask;
904
905 /* Set rate mask*/
906 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
907 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
908 else
909 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
910
911 /* Find lowest valid rate */
912 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
913 i = iwl_rates[i].next_ieee) {
914 if (rate_mask & (1 << i))
915 return iwl_rates[i].plcp;
916 }
917
918 /* No valid rate was found. Assign the lowest one */
919 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
920 return IWL_RATE_1M_PLCP;
921 else
922 return IWL_RATE_6M_PLCP;
923}
924EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
925
fad95bf5 926void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf)
47c5196e 927{
c1adf9fb 928 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e 929
fad95bf5 930 if (!ht_conf->is_ht) {
a2b0f02e 931 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
42eb7c64 932 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
7aafef1c 933 RXON_FLG_HT40_PROT_MSK |
42eb7c64 934 RXON_FLG_HT_PROT_MSK);
47c5196e 935 return;
42eb7c64 936 }
47c5196e 937
a2b0f02e
WYG		 938 /* FIXME: if the definition of ht_protection changed, the "translation"
939 * will be needed for rxon->flags
940 */
fad95bf5 941 rxon->flags |= cpu_to_le32(ht_conf->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
a2b0f02e
WYG		 942
943 /* Set up channel bandwidth:
7aafef1c 944 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
a2b0f02e
WYG		 945 /* clear the HT channel mode before set the mode */
946 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
947 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
7aafef1c
WYG		 948 if (iwl_is_ht40_tx_allowed(priv, NULL)) {
949 /* pure ht40 */
fad95bf5 950 if (ht_conf->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
a2b0f02e 951 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
508b08e7 952 /* Note: control channel is opposite of extension channel */
fad95bf5 953 switch (ht_conf->extension_chan_offset) {
508b08e7
WYG		 954 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
955 rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
956 break;
957 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
958 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
959 break;
960 }
961 } else {
a2b0f02e 962 /* Note: control channel is opposite of extension channel */
fad95bf5 963 switch (ht_conf->extension_chan_offset) {
a2b0f02e
WYG		 964 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
965 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
966 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
967 break;
968 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
969 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
970 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
971 break;
972 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
973 default:
974 /* channel location only valid if in Mixed mode */
975 IWL_ERR(priv, "invalid extension channel offset\n");
976 break;
977 }
978 }
979 } else {
980 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
47c5196e
TW		 981 }
982
45823531
AK		 983 if (priv->cfg->ops->hcmd->set_rxon_chain)
984 priv->cfg->ops->hcmd->set_rxon_chain(priv);
47c5196e 985
02bb1bea 986 IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
ae5eb026 987 "extension channel offset 0x%x\n",
fad95bf5
JB		 988 le32_to_cpu(rxon->flags), ht_conf->ht_protection,
989 ht_conf->extension_chan_offset);
47c5196e
TW		 990 return;
991}
992EXPORT_SYMBOL(iwl_set_rxon_ht);
993
9e5e6c32
TW		 994#define IWL_NUM_RX_CHAINS_MULTIPLE 3
995#define IWL_NUM_RX_CHAINS_SINGLE 2
996#define IWL_NUM_IDLE_CHAINS_DUAL 2
997#define IWL_NUM_IDLE_CHAINS_SINGLE 1
998
2b396a12
JB		 999/*
1000 * Determine how many receiver/antenna chains to use.
1001 *
1002 * More provides better reception via diversity. Fewer saves power
1003 * at the expense of throughput, but only when not in powersave to
1004 * start with.
1005 *
c7de35cd
RR		 1006 * MIMO (dual stream) requires at least 2, but works better with 3.
1007 * This does not determine *which* chains to use, just how many.
1008 */
28a6b07a 1009static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 1010{
c7de35cd 1011 /* # of Rx chains to use when expecting MIMO. */
02bb1bea 1012 if (is_single_rx_stream(priv))
9e5e6c32 1013 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 1014 else
9e5e6c32 1015 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 1016}
c7de35cd 1017
2b396a12 1018/*
3f3e0376
WYG		 1019 * When we are in power saving mode, unless device support spatial
1020 * multiplexing power save, use the active count for rx chain count.
2b396a12 1021 */
28a6b07a
TW		 1022static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
1023{
ba37a3d0
JB		 1024 /* # Rx chains when idling, depending on SMPS mode */
1025 switch (priv->current_ht_config.smps) {
1026 case IEEE80211_SMPS_STATIC:
1027 case IEEE80211_SMPS_DYNAMIC:
1028 return IWL_NUM_IDLE_CHAINS_SINGLE;
1029 case IEEE80211_SMPS_OFF:
1030 return active_cnt;
c15d20c1 1031 default:
ba37a3d0
JB		 1032 WARN(1, "invalid SMPS mode %d",
1033 priv->current_ht_config.smps);
1034 return active_cnt;
3f3e0376 1035 }
c7de35cd
RR		 1036}
1037
04816448
GE		 1038/* up to 4 chains */
1039static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
1040{
1041 u8 res;
1042 res = (chain_bitmap & BIT(0)) >> 0;
1043 res += (chain_bitmap & BIT(1)) >> 1;
1044 res += (chain_bitmap & BIT(2)) >> 2;
9bddbab3 1045 res += (chain_bitmap & BIT(3)) >> 3;
04816448
GE		 1046 return res;
1047}
1048
4c4df78f
CR		 1049/**
1050 * iwl_is_monitor_mode - Determine if interface in monitor mode
1051 *
1052 * priv->iw_mode is set in add_interface, but add_interface is
1053 * never called for monitor mode. The only way mac80211 informs us about
1054 * monitor mode is through configuring filters (call to configure_filter).
1055 */
279b05d4 1056bool iwl_is_monitor_mode(struct iwl_priv *priv)
4c4df78f
CR		 1057{
1058 return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
1059}
279b05d4 1060EXPORT_SYMBOL(iwl_is_monitor_mode);
4c4df78f 1061
c7de35cd
RR		 1062/**
1063 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1064 *
1065 * Selects how many and which Rx receivers/antennas/chains to use.
1066 * This should not be used for scan command ... it puts data in wrong place.
1067 */
1068void iwl_set_rxon_chain(struct iwl_priv *priv)
1069{
28a6b07a
TW		 1070 bool is_single = is_single_rx_stream(priv);
1071 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 1072 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1073 u32 active_chains;
28a6b07a 1074 u16 rx_chain;
c7de35cd
RR		 1075
1076 /* Tell uCode which antennas are actually connected.
1077 * Before first association, we assume all antennas are connected.
1078 * Just after first association, iwl_chain_noise_calibration()
1079 * checks which antennas actually *are* connected. */
04816448
GE		 1080 if (priv->chain_noise_data.active_chains)
1081 active_chains = priv->chain_noise_data.active_chains;
1082 else
1083 active_chains = priv->hw_params.valid_rx_ant;
1084
1085 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 1086
1087 /* How many receivers should we use? */
28a6b07a
TW		 1088 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
1089 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
1090
28a6b07a 1091
04816448
GE		 1092 /* correct rx chain count according hw settings
1093 * and chain noise calibration
1094 */
1095 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
1096 if (valid_rx_cnt < active_rx_cnt)
1097 active_rx_cnt = valid_rx_cnt;
1098
1099 if (valid_rx_cnt < idle_rx_cnt)
1100 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 1101
1102 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1103 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1104
7b841727
RF		 1105 /* copied from 'iwl_bg_request_scan()' */
1106 /* Force use of chains B and C (0x6) for Rx for 4965
1107 * Avoid A (0x1) because of its off-channel reception on A-band.
1108 * MIMO is not used here, but value is required */
1109 if (iwl_is_monitor_mode(priv) &&
1110 !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
1111 ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
fff7a434
WYG		 1112 rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
1113 rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
1114 rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1115 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
7b841727
RF		 1116 }
1117
28a6b07a
TW		 1118 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
1119
9e5e6c32 1120 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 1121 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1122 else
1123 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1124
e1623446 1125 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 1126 priv->staging_rxon.rx_chain,
1127 active_rx_cnt, idle_rx_cnt);
1128
1129 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1130 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 1131}
1132EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 1133
1134/**
17e72782 1135 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 1136 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
1137 * @channel: Any channel valid for the requested phymode
1138
1139 * In addition to setting the staging RXON, priv->phymode is also set.
1140 *
1141 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
1142 * in the staging RXON flag structure based on the phymode
1143 */
17e72782 1144int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 1145{
17e72782
TW		 1146 enum ieee80211_band band = ch->band;
1147 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
1148
8622e705 1149 if (!iwl_get_channel_info(priv, band, channel)) {
e1623446 1150 IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
bf85ea4f
AK		 1151 channel, band);
1152 return -EINVAL;
1153 }
1154
1155 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
1156 (priv->band == band))
1157 return 0;
1158
1159 priv->staging_rxon.channel = cpu_to_le16(channel);
1160 if (band == IEEE80211_BAND_5GHZ)
1161 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
1162 else
1163 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1164
1165 priv->band = band;
1166
e1623446 1167 IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
bf85ea4f
AK		 1168
1169 return 0;
1170}
c7de35cd 1171EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 1172
8ccde88a
SO		 1173void iwl_set_flags_for_band(struct iwl_priv *priv,
1174 enum ieee80211_band band)
1175{
1176 if (band == IEEE80211_BAND_5GHZ) {
1177 priv->staging_rxon.flags &=
1178 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1179 | RXON_FLG_CCK_MSK);
1180 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1181 } else {
1182 /* Copied from iwl_post_associate() */
1183 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
1184 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1185 else
1186 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1187
1188 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
1189 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1190
1191 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1192 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1193 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
1194 }
1195}
8ccde88a
SO		 1196
1197/*
1198 * initialize rxon structure with default values from eeprom
1199 */
1200void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
1201{
1202 const struct iwl_channel_info *ch_info;
1203
1204 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
1205
1206 switch (mode) {
1207 case NL80211_IFTYPE_AP:
1208 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
1209 break;
1210
1211 case NL80211_IFTYPE_STATION:
1212 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
1213 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
1214 break;
1215
1216 case NL80211_IFTYPE_ADHOC:
1217 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1218 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1219 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
1220 RXON_FILTER_ACCEPT_GRP_MSK;
1221 break;
1222
8ccde88a
SO		 1223 default:
1224 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
1225 break;
1226 }
1227
1228#if 0
1229 /* TODO: Figure out when short_preamble would be set and cache from
1230 * that */
1231 if (!hw_to_local(priv->hw)->short_preamble)
1232 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1233 else
1234 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1235#endif
1236
1237 ch_info = iwl_get_channel_info(priv, priv->band,
1238 le16_to_cpu(priv->active_rxon.channel));
1239
1240 if (!ch_info)
1241 ch_info = &priv->channel_info[0];
1242
1243 /*
1244 * in some case A channels are all non IBSS
1245 * in this case force B/G channel
1246 */
1247 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
1248 !(is_channel_ibss(ch_info)))
1249 ch_info = &priv->channel_info[0];
1250
1251 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
1252 priv->band = ch_info->band;
1253
1254 iwl_set_flags_for_band(priv, priv->band);
1255
1256 priv->staging_rxon.ofdm_basic_rates =
1257 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1258 priv->staging_rxon.cck_basic_rates =
1259 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1260
a2b0f02e
WYG		 1261 /* clear both MIX and PURE40 mode flag */
1262 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
1263 RXON_FLG_CHANNEL_MODE_PURE_40);
8ccde88a
SO		 1264 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1265 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
1266 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
1267 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
11397a65 1268 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
8ccde88a
SO		 1269}
1270EXPORT_SYMBOL(iwl_connection_init_rx_config);
1271
782571f4 1272static void iwl_set_rate(struct iwl_priv *priv)
8ccde88a
SO		 1273{
1274 const struct ieee80211_supported_band *hw = NULL;
1275 struct ieee80211_rate *rate;
1276 int i;
1277
1278 hw = iwl_get_hw_mode(priv, priv->band);
1279 if (!hw) {
1280 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
1281 return;
1282 }
1283
1284 priv->active_rate = 0;
1285 priv->active_rate_basic = 0;
1286
1287 for (i = 0; i < hw->n_bitrates; i++) {
1288 rate = &(hw->bitrates[i]);
5027309b 1289 if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
8ccde88a
SO		 1290 priv->active_rate |= (1 << rate->hw_value);
1291 }
1292
e1623446 1293 IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
8ccde88a
SO		 1294 priv->active_rate, priv->active_rate_basic);
1295
1296 /*
1297 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
1298 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
1299 * OFDM
1300 */
1301 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
1302 priv->staging_rxon.cck_basic_rates =
1303 ((priv->active_rate_basic &
1304 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
1305 else
1306 priv->staging_rxon.cck_basic_rates =
1307 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1308
1309 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
1310 priv->staging_rxon.ofdm_basic_rates =
1311 ((priv->active_rate_basic &
1312 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
1313 IWL_FIRST_OFDM_RATE) & 0xFF;
1314 else
1315 priv->staging_rxon.ofdm_basic_rates =
1316 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1317}
8ccde88a
SO		 1318
1319void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1320{
2f301227 1321 struct iwl_rx_packet *pkt = rxb_addr(rxb);
8ccde88a
SO		 1322 struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
1323 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
4a56e965 1324
0924e519
WYG		 1325 if (priv->switch_rxon.switch_in_progress) {
1326 if (!le32_to_cpu(csa->status) &&
1327 (csa->channel == priv->switch_rxon.channel)) {
1328 rxon->channel = csa->channel;
1329 priv->staging_rxon.channel = csa->channel;
1330 IWL_DEBUG_11H(priv, "CSA notif: channel %d\n",
1331 le16_to_cpu(csa->channel));
1332 } else
1333 IWL_ERR(priv, "CSA notif (fail) : channel %d\n",
1334 le16_to_cpu(csa->channel));
1335
1336 priv->switch_rxon.switch_in_progress = false;
1337 }
8ccde88a
SO		 1338}
1339EXPORT_SYMBOL(iwl_rx_csa);
1340
1341#ifdef CONFIG_IWLWIFI_DEBUG
a643565e 1342void iwl_print_rx_config_cmd(struct iwl_priv *priv)
8ccde88a
SO		 1343{
1344 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
1345
e1623446 1346 IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
3d816c77 1347 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e1623446
TW		 1348 IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
1349 IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
1350 IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
8ccde88a 1351 le32_to_cpu(rxon->filter_flags));
e1623446
TW		 1352 IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
1353 IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
8ccde88a 1354 rxon->ofdm_basic_rates);
e1623446
TW		 1355 IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
1356 IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
1357 IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
1358 IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
8ccde88a 1359}
a643565e 1360EXPORT_SYMBOL(iwl_print_rx_config_cmd);
6686d17e 1361#endif
8ccde88a
SO		 1362/**
1363 * iwl_irq_handle_error - called for HW or SW error interrupt from card
1364 */
1365void iwl_irq_handle_error(struct iwl_priv *priv)
1366{
1367 /* Set the FW error flag -- cleared on iwl_down */
1368 set_bit(STATUS_FW_ERROR, &priv->status);
1369
1370 /* Cancel currently queued command. */
1371 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1372
3a3ff72c 1373 priv->cfg->ops->lib->dump_nic_error_log(priv);
696bdee3
WYG		 1374 if (priv->cfg->ops->lib->dump_csr)
1375 priv->cfg->ops->lib->dump_csr(priv);
1b3eb823
WYG		 1376 if (priv->cfg->ops->lib->dump_fh)
1377 priv->cfg->ops->lib->dump_fh(priv, NULL, false);
b03d7d0f 1378 priv->cfg->ops->lib->dump_nic_event_log(priv, false, NULL, false);
8ccde88a 1379#ifdef CONFIG_IWLWIFI_DEBUG
c341ddb2 1380 if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS)
8ccde88a 1381 iwl_print_rx_config_cmd(priv);
8ccde88a
SO		 1382#endif
1383
1384 wake_up_interruptible(&priv->wait_command_queue);
1385
1386 /* Keep the restart process from trying to send host
1387 * commands by clearing the INIT status bit */
1388 clear_bit(STATUS_READY, &priv->status);
1389
1390 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 1391 IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
8ccde88a
SO		 1392 "Restarting adapter due to uCode error.\n");
1393
8ccde88a
SO		 1394 if (priv->cfg->mod_params->restart_fw)
1395 queue_work(priv->workqueue, &priv->restart);
1396 }
1397}
1398EXPORT_SYMBOL(iwl_irq_handle_error);
1399
d68b603c
AK		 1400int iwl_apm_stop_master(struct iwl_priv *priv)
1401{
5220af0c 1402 int ret = 0;
d68b603c 1403
5220af0c 1404 /* stop device's busmaster DMA activity */
d68b603c
AK		 1405 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1406
5220af0c 1407 ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
d68b603c 1408 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
5220af0c
BC		 1409 if (ret)
1410 IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
d68b603c 1411
d68b603c
AK		 1412 IWL_DEBUG_INFO(priv, "stop master\n");
1413
5220af0c 1414 return ret;
d68b603c
AK		 1415}
1416EXPORT_SYMBOL(iwl_apm_stop_master);
1417
1418void iwl_apm_stop(struct iwl_priv *priv)
1419{
fadb3582
BC		 1420 IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
1421
5220af0c 1422 /* Stop device's DMA activity */
d68b603c
AK		 1423 iwl_apm_stop_master(priv);
1424
5220af0c 1425 /* Reset the entire device */
d68b603c
AK		 1426 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1427
1428 udelay(10);
5220af0c
BC		 1429
1430 /*
1431 * Clear "initialization complete" bit to move adapter from
1432 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
1433 */
d68b603c 1434 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
d68b603c
AK		 1435}
1436EXPORT_SYMBOL(iwl_apm_stop);
1437
fadb3582
BC		 1438
1439/*
1440 * Start up NIC's basic functionality after it has been reset
1441 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1442 * NOTE: This does not load uCode nor start the embedded processor
1443 */
1444int iwl_apm_init(struct iwl_priv *priv)
1445{
1446 int ret = 0;
1447 u16 lctl;
1448
1449 IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
1450
1451 /*
1452 * Use "set_bit" below rather than "write", to preserve any hardware
1453 * bits already set by default after reset.
1454 */
1455
1456 /* Disable L0S exit timer (platform NMI Work/Around) */
1457 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1458 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1459
1460 /*
1461 * Disable L0s without affecting L1;
1462 * don't wait for ICH L0s (ICH bug W/A)
1463 */
1464 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1465 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1466
1467 /* Set FH wait threshold to maximum (HW error during stress W/A) */
1468 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
1469
1470 /*
1471 * Enable HAP INTA (interrupt from management bus) to
1472 * wake device's PCI Express link L1a -> L0s
1473 * NOTE: This is no-op for 3945 (non-existant bit)
1474 */
1475 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1476 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
1477
1478 /*
a6c5c731
BC		 1479 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
1480 * Check if BIOS (or OS) enabled L1-ASPM on this device.
1481 * If so (likely), disable L0S, so device moves directly L0->L1;
1482 * costs negligible amount of power savings.
1483 * If not (unlikely), enable L0S, so there is at least some
1484 * power savings, even without L1.
fadb3582
BC		 1485 */
1486 if (priv->cfg->set_l0s) {
1487 lctl = iwl_pcie_link_ctl(priv);
1488 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
1489 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
1490 /* L1-ASPM enabled; disable(!) L0S */
1491 iwl_set_bit(priv, CSR_GIO_REG,
1492 CSR_GIO_REG_VAL_L0S_ENABLED);
1493 IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
1494 } else {
1495 /* L1-ASPM disabled; enable(!) L0S */
1496 iwl_clear_bit(priv, CSR_GIO_REG,
1497 CSR_GIO_REG_VAL_L0S_ENABLED);
1498 IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
1499 }
1500 }
1501
1502 /* Configure analog phase-lock-loop before activating to D0A */
1503 if (priv->cfg->pll_cfg_val)
1504 iwl_set_bit(priv, CSR_ANA_PLL_CFG, priv->cfg->pll_cfg_val);
1505
1506 /*
1507 * Set "initialization complete" bit to move adapter from
1508 * D0U* --> D0A* (powered-up active) state.
1509 */
1510 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1511
1512 /*
1513 * Wait for clock stabilization; once stabilized, access to
1514 * device-internal resources is supported, e.g. iwl_write_prph()
1515 * and accesses to uCode SRAM.
1516 */
1517 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
1518 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1519 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1520 if (ret < 0) {
1521 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1522 goto out;
1523 }
1524
1525 /*
1526 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
1527 * BSM (Boostrap State Machine) is only in 3945 and 4965;
1528 * later devices (i.e. 5000 and later) have non-volatile SRAM,
1529 * and don't need BSM to restore data after power-saving sleep.
1530 *
1531 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
1532 * do not disable clocks. This preserves any hardware bits already
1533 * set by default in "CLK_CTRL_REG" after reset.
1534 */
1535 if (priv->cfg->use_bsm)
1536 iwl_write_prph(priv, APMG_CLK_EN_REG,
1537 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
1538 else
1539 iwl_write_prph(priv, APMG_CLK_EN_REG,
1540 APMG_CLK_VAL_DMA_CLK_RQT);
1541 udelay(20);
1542
1543 /* Disable L1-Active */
1544 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1545 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1546
1547out:
1548 return ret;
1549}
1550EXPORT_SYMBOL(iwl_apm_init);
1551
1552
1553
8ccde88a
SO		 1554void iwl_configure_filter(struct ieee80211_hw *hw,
1555 unsigned int changed_flags,
1556 unsigned int *total_flags,
3ac64bee 1557 u64 multicast)
8ccde88a
SO		 1558{
1559 struct iwl_priv *priv = hw->priv;
1560 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
1561
e1623446 1562 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
8ccde88a
SO		 1563 changed_flags, *total_flags);
1564
1565 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
1566 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
1567 *filter_flags |= RXON_FILTER_PROMISC_MSK;
1568 else
1569 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
1570 }
1571 if (changed_flags & FIF_ALLMULTI) {
1572 if (*total_flags & FIF_ALLMULTI)
1573 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
1574 else
1575 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
1576 }
1577 if (changed_flags & FIF_CONTROL) {
1578 if (*total_flags & FIF_CONTROL)
1579 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
1580 else
1581 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
1582 }
1583 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1584 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1585 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
1586 else
1587 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
1588 }
1589
1590 /* We avoid iwl_commit_rxon here to commit the new filter flags
1591 * since mac80211 will call ieee80211_hw_config immediately.
1592 * (mc_list is not supported at this time). Otherwise, we need to
1593 * queue a background iwl_commit_rxon work.
1594 */
1595
1596 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
1597 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
1598}
1599EXPORT_SYMBOL(iwl_configure_filter);
1600
da154e30
RR		 1601int iwl_set_hw_params(struct iwl_priv *priv)
1602{
da154e30
RR		 1603 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1604 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1605 if (priv->cfg->mod_params->amsdu_size_8K)
2f301227 1606 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
da154e30 1607 else
2f301227 1608 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
da154e30 1609
2c2f3b33
TW		 1610 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
1611
49779293
RR		 1612 if (priv->cfg->mod_params->disable_11n)
1613 priv->cfg->sku &= ~IWL_SKU_N;
1614
da154e30
RR		 1615 /* Device-specific setup */
1616 return priv->cfg->ops->lib->set_hw_params(priv);
1617}
1618EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956 1619
630fe9b6
TW		 1620int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1621{
1622 int ret = 0;
5eadd94b
WYG		 1623 s8 prev_tx_power = priv->tx_power_user_lmt;
1624
630fe9b6 1625 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
daf518de
WF		 1626 IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
1627 tx_power,
1628 IWL_TX_POWER_TARGET_POWER_MIN);
630fe9b6
TW		 1629 return -EINVAL;
1630 }
1631
dc1b0973 1632 if (tx_power > priv->tx_power_device_lmt) {
08f2d58d
WYG		 1633 IWL_WARN(priv,
1634 "Requested user TXPOWER %d above upper limit %d.\n",
dc1b0973 1635 tx_power, priv->tx_power_device_lmt);
630fe9b6
TW		 1636 return -EINVAL;
1637 }
1638
1639 if (priv->tx_power_user_lmt != tx_power)
1640 force = true;
1641
019fb97d 1642 /* if nic is not up don't send command */
5eadd94b
WYG		 1643 if (iwl_is_ready_rf(priv)) {
1644 priv->tx_power_user_lmt = tx_power;
1645 if (force && priv->cfg->ops->lib->send_tx_power)
1646 ret = priv->cfg->ops->lib->send_tx_power(priv);
1647 else if (!priv->cfg->ops->lib->send_tx_power)
1648 ret = -EOPNOTSUPP;
1649 /*
1650 * if fail to set tx_power, restore the orig. tx power
1651 */
1652 if (ret)
1653 priv->tx_power_user_lmt = prev_tx_power;
1654 }
630fe9b6 1655
5eadd94b
WYG		 1656 /*
1657 * Even this is an async host command, the command
1658 * will always report success from uCode
1659 * So once driver can placing the command into the queue
1660 * successfully, driver can use priv->tx_power_user_lmt
1661 * to reflect the current tx power
1662 */
630fe9b6
TW		 1663 return ret;
1664}
1665EXPORT_SYMBOL(iwl_set_tx_power);
1666
ef850d7c
MA		 1667#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1668
1669/* Free dram table */
1670void iwl_free_isr_ict(struct iwl_priv *priv)
1671{
1672 if (priv->ict_tbl_vir) {
1673 pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
1674 PAGE_SIZE, priv->ict_tbl_vir,
1675 priv->ict_tbl_dma);
1676 priv->ict_tbl_vir = NULL;
1677 }
1678}
1679EXPORT_SYMBOL(iwl_free_isr_ict);
1680
1681
1682/* allocate dram shared table it is a PAGE_SIZE aligned
1683 * also reset all data related to ICT table interrupt.
1684 */
1685int iwl_alloc_isr_ict(struct iwl_priv *priv)
1686{
1687
1688 if (priv->cfg->use_isr_legacy)
1689 return 0;
1690 /* allocate shrared data table */
1691 priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
1692 ICT_COUNT) + PAGE_SIZE,
1693 &priv->ict_tbl_dma);
1694 if (!priv->ict_tbl_vir)
1695 return -ENOMEM;
1696
1697 /* align table to PAGE_SIZE boundry */
1698 priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
1699
1700 IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1701 (unsigned long long)priv->ict_tbl_dma,
1702 (unsigned long long)priv->aligned_ict_tbl_dma,
1703 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1704
1705 priv->ict_tbl = priv->ict_tbl_vir +
1706 (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
1707
1708 IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
1709 priv->ict_tbl, priv->ict_tbl_vir,
1710 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1711
1712 /* reset table and index to all 0 */
1713 memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1714 priv->ict_index = 0;
1715
40cefda9
MA		 1716 /* add periodic RX interrupt */
1717 priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
ef850d7c
MA		 1718 return 0;
1719}
1720EXPORT_SYMBOL(iwl_alloc_isr_ict);
1721
1722/* Device is going up inform it about using ICT interrupt table,
1723 * also we need to tell the driver to start using ICT interrupt.
1724 */
1725int iwl_reset_ict(struct iwl_priv *priv)
1726{
1727 u32 val;
1728 unsigned long flags;
1729
1730 if (!priv->ict_tbl_vir)
1731 return 0;
1732
1733 spin_lock_irqsave(&priv->lock, flags);
1734 iwl_disable_interrupts(priv);
1735
1303dcfd 1736 memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
ef850d7c
MA		 1737
1738 val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
1739
1740 val |= CSR_DRAM_INT_TBL_ENABLE;
1741 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1742
1743 IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
1744 "aligned dma address %Lx\n",
1745 val, (unsigned long long)priv->aligned_ict_tbl_dma);
1746
1747 iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
1748 priv->use_ict = true;
1749 priv->ict_index = 0;
40cefda9 1750 iwl_write32(priv, CSR_INT, priv->inta_mask);
ef850d7c
MA		 1751 iwl_enable_interrupts(priv);
1752 spin_unlock_irqrestore(&priv->lock, flags);
1753
1754 return 0;
1755}
1756EXPORT_SYMBOL(iwl_reset_ict);
1757
1758/* Device is going down disable ict interrupt usage */
1759void iwl_disable_ict(struct iwl_priv *priv)
1760{
1761 unsigned long flags;
1762
1763 spin_lock_irqsave(&priv->lock, flags);
1764 priv->use_ict = false;
1765 spin_unlock_irqrestore(&priv->lock, flags);
1766}
1767EXPORT_SYMBOL(iwl_disable_ict);
1768
1769/* interrupt handler using ict table, with this interrupt driver will
1770 * stop using INTA register to get device's interrupt, reading this register
1771 * is expensive, device will write interrupts in ICT dram table, increment
1772 * index then will fire interrupt to driver, driver will OR all ICT table
1773 * entries from current index up to table entry with 0 value. the result is
1774 * the interrupt we need to service, driver will set the entries back to 0 and
1775 * set index.
1776 */
1777irqreturn_t iwl_isr_ict(int irq, void *data)
1778{
1779 struct iwl_priv *priv = data;
1780 u32 inta, inta_mask;
1781 u32 val = 0;
1782
1783 if (!priv)
1784 return IRQ_NONE;
1785
1786 /* dram interrupt table not set yet,
1787 * use legacy interrupt.
1788 */
1789 if (!priv->use_ict)
1790 return iwl_isr(irq, data);
1791
1792 spin_lock(&priv->lock);
1793
1794 /* Disable (but don't clear!) interrupts here to avoid
1795 * back-to-back ISRs and sporadic interrupts from our NIC.
1796 * If we have something to service, the tasklet will re-enable ints.
1797 * If we *don't* have something, we'll re-enable before leaving here.
1798 */
1799 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1800 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1801
1802
1803 /* Ignore interrupt if there's nothing in NIC to service.
1804 * This may be due to IRQ shared with another device,
1805 * or due to sporadic interrupts thrown from our NIC. */
1806 if (!priv->ict_tbl[priv->ict_index]) {
1807 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1808 goto none;
1809 }
1810
1811 /* read all entries that not 0 start with ict_index */
1812 while (priv->ict_tbl[priv->ict_index]) {
1813
1303dcfd 1814 val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
ef850d7c 1815 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
1303dcfd
JB		 1816 priv->ict_index,
1817 le32_to_cpu(priv->ict_tbl[priv->ict_index]));
ef850d7c
MA		 1818 priv->ict_tbl[priv->ict_index] = 0;
1819 priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
1303dcfd 1820 ICT_COUNT);
ef850d7c
MA		 1821
1822 }
1823
1824 /* We should not get this value, just ignore it. */
1825 if (val == 0xffffffff)
1826 val = 0;
1827
2a11df6e
WYG		 1828 /*
1829 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1830 * (bit 15 before shifting it to 31) to clear when using interrupt
1831 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1832 * so we use them to decide on the real state of the Rx bit.
1833 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1834 */
1835 if (val & 0xC0000)
1836 val |= 0x8000;
1837
ef850d7c
MA		 1838 inta = (0xff & val) | ((0xff00 & val) << 16);
1839 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1840 inta, inta_mask, val);
1841
40cefda9 1842 inta &= priv->inta_mask;
ef850d7c
MA		 1843 priv->inta |= inta;
1844
1845 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1846 if (likely(inta))
1847 tasklet_schedule(&priv->irq_tasklet);
1848 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
1849 /* Allow interrupt if was disabled by this handler and
1850 * no tasklet was schedules, We should not enable interrupt,
1851 * tasklet will enable it.
1852 */
1853 iwl_enable_interrupts(priv);
1854 }
1855
1856 spin_unlock(&priv->lock);
1857 return IRQ_HANDLED;
1858
1859 none:
1860 /* re-enable interrupts here since we don't have anything to service.
1861 * only Re-enable if disabled by irq.
1862 */
1863 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1864 iwl_enable_interrupts(priv);
1865
1866 spin_unlock(&priv->lock);
1867 return IRQ_NONE;
1868}
1869EXPORT_SYMBOL(iwl_isr_ict);
1870
1871
1872static irqreturn_t iwl_isr(int irq, void *data)
1873{
1874 struct iwl_priv *priv = data;
1875 u32 inta, inta_mask;
d651ae32 1876#ifdef CONFIG_IWLWIFI_DEBUG
ef850d7c 1877 u32 inta_fh;
d651ae32 1878#endif
ef850d7c
MA		 1879 if (!priv)
1880 return IRQ_NONE;
1881
1882 spin_lock(&priv->lock);
1883
1884 /* Disable (but don't clear!) interrupts here to avoid
1885 * back-to-back ISRs and sporadic interrupts from our NIC.
1886 * If we have something to service, the tasklet will re-enable ints.
1887 * If we *don't* have something, we'll re-enable before leaving here. */
1888 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1889 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1890
1891 /* Discover which interrupts are active/pending */
1892 inta = iwl_read32(priv, CSR_INT);
1893
1894 /* Ignore interrupt if there's nothing in NIC to service.
1895 * This may be due to IRQ shared with another device,
1896 * or due to sporadic interrupts thrown from our NIC. */
1897 if (!inta) {
1898 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1899 goto none;
1900 }
1901
1902 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1903 /* Hardware disappeared. It might have already raised
1904 * an interrupt */
1905 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1906 goto unplugged;
1907 }
1908
1909#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1910 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1911 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1912 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
1913 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1914 }
1915#endif
1916
1917 priv->inta |= inta;
1918 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1919 if (likely(inta))
1920 tasklet_schedule(&priv->irq_tasklet);
1921 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1922 iwl_enable_interrupts(priv);
1923
1924 unplugged:
1925 spin_unlock(&priv->lock);
1926 return IRQ_HANDLED;
1927
1928 none:
1929 /* re-enable interrupts here since we don't have anything to service. */
1930 /* only Re-enable if diabled by irq and no schedules tasklet. */
1931 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1932 iwl_enable_interrupts(priv);
1933
1934 spin_unlock(&priv->lock);
1935 return IRQ_NONE;
1936}
1937
1938irqreturn_t iwl_isr_legacy(int irq, void *data)
f17d08a6
AK		 1939{
1940 struct iwl_priv *priv = data;
1941 u32 inta, inta_mask;
1942 u32 inta_fh;
1943 if (!priv)
1944 return IRQ_NONE;
1945
1946 spin_lock(&priv->lock);
1947
1948 /* Disable (but don't clear!) interrupts here to avoid
1949 * back-to-back ISRs and sporadic interrupts from our NIC.
1950 * If we have something to service, the tasklet will re-enable ints.
1951 * If we *don't* have something, we'll re-enable before leaving here. */
1952 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1953 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1954
1955 /* Discover which interrupts are active/pending */
1956 inta = iwl_read32(priv, CSR_INT);
1957 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1958
1959 /* Ignore interrupt if there's nothing in NIC to service.
1960 * This may be due to IRQ shared with another device,
1961 * or due to sporadic interrupts thrown from our NIC. */
1962 if (!inta && !inta_fh) {
1963 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
1964 goto none;
1965 }
1966
1967 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1968 /* Hardware disappeared. It might have already raised
1969 * an interrupt */
1970 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1971 goto unplugged;
1972 }
1973
1974 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1975 inta, inta_mask, inta_fh);
1976
1977 inta &= ~CSR_INT_BIT_SCD;
1978
1979 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1980 if (likely(inta || inta_fh))
1981 tasklet_schedule(&priv->irq_tasklet);
1982
1983 unplugged:
1984 spin_unlock(&priv->lock);
1985 return IRQ_HANDLED;
1986
1987 none:
1988 /* re-enable interrupts here since we don't have anything to service. */
1989 /* only Re-enable if diabled by irq */
1990 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1991 iwl_enable_interrupts(priv);
1992 spin_unlock(&priv->lock);
1993 return IRQ_NONE;
1994}
ef850d7c 1995EXPORT_SYMBOL(iwl_isr_legacy);
f17d08a6 1996
17f841cd
SO		 1997int iwl_send_bt_config(struct iwl_priv *priv)
1998{
1999 struct iwl_bt_cmd bt_cmd = {
456d0f76
WYG		 2000 .lead_time = BT_LEAD_TIME_DEF,
2001 .max_kill = BT_MAX_KILL_DEF,
17f841cd
SO		 2002 .kill_ack_mask = 0,
2003 .kill_cts_mask = 0,
2004 };
2005
06702a73
WYG		 2006 if (!bt_coex_active)
2007 bt_cmd.flags = BT_COEX_DISABLE;
2008 else
2009 bt_cmd.flags = BT_COEX_ENABLE;
2010
2011 IWL_DEBUG_INFO(priv, "BT coex %s\n",
2012 (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
2013
17f841cd
SO		 2014 return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
2015 sizeof(struct iwl_bt_cmd), &bt_cmd);
2016}
2017EXPORT_SYMBOL(iwl_send_bt_config);
2018
ef8d5529 2019int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear)
49ea8596 2020{
ef8d5529
WYG		 2021 struct iwl_statistics_cmd statistics_cmd = {
2022 .configuration_flags =
2023 clear ? IWL_STATS_CONF_CLEAR_STATS : 0,
49ea8596 2024 };
ef8d5529
WYG		 2025
2026 if (flags & CMD_ASYNC)
2027 return iwl_send_cmd_pdu_async(priv, REPLY_STATISTICS_CMD,
2028 sizeof(struct iwl_statistics_cmd),
2029 &statistics_cmd, NULL);
2030 else
2031 return iwl_send_cmd_pdu(priv, REPLY_STATISTICS_CMD,
2032 sizeof(struct iwl_statistics_cmd),
2033 &statistics_cmd);
49ea8596
EG		 2034}
2035EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 2036
b0692f2f
EG		 2037/**
2038 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
2039 * using sample data 100 bytes apart. If these sample points are good,
2040 * it's a pretty good bet that everything between them is good, too.
2041 */
2042static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
2043{
2044 u32 val;
2045 int ret = 0;
2046 u32 errcnt = 0;
2047 u32 i;
2048
e1623446 2049 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2050
b0692f2f
EG		 2051 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2052 /* read data comes through single port, auto-incr addr */
2053 /* NOTE: Use the debugless read so we don't flood kernel log
2054 * if IWL_DL_IO is set */
2055 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2056 i + IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2057 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2058 if (val != le32_to_cpu(*image)) {
2059 ret = -EIO;
2060 errcnt++;
2061 if (errcnt >= 3)
2062 break;
2063 }
2064 }
2065
b0692f2f
EG		 2066 return ret;
2067}
2068
2069/**
2070 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
2071 * looking at all data.
2072 */
2073static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
2074 u32 len)
2075{
2076 u32 val;
2077 u32 save_len = len;
2078 int ret = 0;
2079 u32 errcnt;
2080
e1623446 2081 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2082
250bdd21
SO		 2083 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
2084 IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2085
2086 errcnt = 0;
2087 for (; len > 0; len -= sizeof(u32), image++) {
2088 /* read data comes through single port, auto-incr addr */
2089 /* NOTE: Use the debugless read so we don't flood kernel log
2090 * if IWL_DL_IO is set */
2091 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2092 if (val != le32_to_cpu(*image)) {
15b1687c 2093 IWL_ERR(priv, "uCode INST section is invalid at "
b0692f2f
EG		 2094 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2095 save_len - len, val, le32_to_cpu(*image));
2096 ret = -EIO;
2097 errcnt++;
2098 if (errcnt >= 20)
2099 break;
2100 }
2101 }
2102
b0692f2f 2103 if (!errcnt)
e1623446
TW		 2104 IWL_DEBUG_INFO(priv,
2105 "ucode image in INSTRUCTION memory is good\n");
b0692f2f
EG		 2106
2107 return ret;
2108}
2109
2110/**
2111 * iwl_verify_ucode - determine which instruction image is in SRAM,
2112 * and verify its contents
2113 */
2114int iwl_verify_ucode(struct iwl_priv *priv)
2115{
2116 __le32 *image;
2117 u32 len;
2118 int ret;
2119
2120 /* Try bootstrap */
2121 image = (__le32 *)priv->ucode_boot.v_addr;
2122 len = priv->ucode_boot.len;
2123 ret = iwlcore_verify_inst_sparse(priv, image, len);
2124 if (!ret) {
e1623446 2125 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b0692f2f
EG		 2126 return 0;
2127 }
2128
2129 /* Try initialize */
2130 image = (__le32 *)priv->ucode_init.v_addr;
2131 len = priv->ucode_init.len;
2132 ret = iwlcore_verify_inst_sparse(priv, image, len);
2133 if (!ret) {
e1623446 2134 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b0692f2f
EG		 2135 return 0;
2136 }
2137
2138 /* Try runtime/protocol */
2139 image = (__le32 *)priv->ucode_code.v_addr;
2140 len = priv->ucode_code.len;
2141 ret = iwlcore_verify_inst_sparse(priv, image, len);
2142 if (!ret) {
e1623446 2143 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b0692f2f
EG		 2144 return 0;
2145 }
2146
15b1687c 2147 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b0692f2f
EG		 2148
2149 /* Since nothing seems to match, show first several data entries in
2150 * instruction SRAM, so maybe visual inspection will give a clue.
2151 * Selection of bootstrap image (vs. other images) is arbitrary. */
2152 image = (__le32 *)priv->ucode_boot.v_addr;
2153 len = priv->ucode_boot.len;
2154 ret = iwl_verify_inst_full(priv, image, len);
2155
2156 return ret;
2157}
2158EXPORT_SYMBOL(iwl_verify_ucode);
2159
56e12615 2160
47f4a587
EG		 2161void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2162{
2163 struct iwl_ct_kill_config cmd;
672639de 2164 struct iwl_ct_kill_throttling_config adv_cmd;
47f4a587
EG		 2165 unsigned long flags;
2166 int ret = 0;
2167
2168 spin_lock_irqsave(&priv->lock, flags);
2169 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2170 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2171 spin_unlock_irqrestore(&priv->lock, flags);
3ad3b92a 2172 priv->thermal_throttle.ct_kill_toggle = false;
47f4a587 2173
480e8407 2174 if (priv->cfg->support_ct_kill_exit) {
672639de
WYG		 2175 adv_cmd.critical_temperature_enter =
2176 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2177 adv_cmd.critical_temperature_exit =
2178 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2179
2180 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2181 sizeof(adv_cmd), &adv_cmd);
d91b1ba3
WYG		 2182 if (ret)
2183 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2184 else
2185 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2186 "succeeded, "
2187 "critical temperature enter is %d,"
2188 "exit is %d\n",
2189 priv->hw_params.ct_kill_threshold,
2190 priv->hw_params.ct_kill_exit_threshold);
480e8407 2191 } else {
672639de
WYG		 2192 cmd.critical_temperature_R =
2193 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 2194
672639de
WYG		 2195 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2196 sizeof(cmd), &cmd);
d91b1ba3
WYG		 2197 if (ret)
2198 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2199 else
2200 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2201 "succeeded, "
2202 "critical temperature is %d\n",
2203 priv->hw_params.ct_kill_threshold);
672639de 2204 }
47f4a587
EG		 2205}
2206EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f 2207
0ad91a35 2208
14a08a7f
EG		 2209/*
2210 * CARD_STATE_CMD
2211 *
2212 * Use: Sets the device's internal card state to enable, disable, or halt
2213 *
2214 * When in the 'enable' state the card operates as normal.
2215 * When in the 'disable' state, the card enters into a low power mode.
2216 * When in the 'halt' state, the card is shut down and must be fully
2217 * restarted to come back on.
2218 */
c496294e 2219int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
14a08a7f
EG		 2220{
2221 struct iwl_host_cmd cmd = {
2222 .id = REPLY_CARD_STATE_CMD,
2223 .len = sizeof(u32),
2224 .data = &flags,
c2acea8e 2225 .flags = meta_flag,
14a08a7f
EG		 2226 };
2227
2228 return iwl_send_cmd(priv, &cmd);
2229}
2230
030f05ed
AK		 2231void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
2232 struct iwl_rx_mem_buffer *rxb)
2233{
2234#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 2235 struct iwl_rx_packet *pkt = rxb_addr(rxb);
030f05ed
AK		 2236 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
2237 IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
2238 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2239#endif
2240}
2241EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
2242
2243void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
2244 struct iwl_rx_mem_buffer *rxb)
2245{
2f301227 2246 struct iwl_rx_packet *pkt = rxb_addr(rxb);
396887a2 2247 u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
030f05ed 2248 IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
396887a2
DH		 2249 "notification for %s:\n", len,
2250 get_cmd_string(pkt->hdr.cmd));
2251 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len);
030f05ed
AK		 2252}
2253EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
261b9c33
AK		 2254
2255void iwl_rx_reply_error(struct iwl_priv *priv,
2256 struct iwl_rx_mem_buffer *rxb)
2257{
2f301227 2258 struct iwl_rx_packet *pkt = rxb_addr(rxb);
261b9c33
AK		 2259
2260 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
2261 "seq 0x%04X ser 0x%08X\n",
2262 le32_to_cpu(pkt->u.err_resp.error_type),
2263 get_cmd_string(pkt->u.err_resp.cmd_id),
2264 pkt->u.err_resp.cmd_id,
2265 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2266 le32_to_cpu(pkt->u.err_resp.error_info));
2267}
2268EXPORT_SYMBOL(iwl_rx_reply_error);
2269
a83b9141
WYG		 2270void iwl_clear_isr_stats(struct iwl_priv *priv)
2271{
2272 memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
2273}
a83b9141 2274
488829f1
AK		 2275int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
2276 const struct ieee80211_tx_queue_params *params)
2277{
2278 struct iwl_priv *priv = hw->priv;
2279 unsigned long flags;
2280 int q;
2281
2282 IWL_DEBUG_MAC80211(priv, "enter\n");
2283
2284 if (!iwl_is_ready_rf(priv)) {
2285 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2286 return -EIO;
2287 }
2288
2289 if (queue >= AC_NUM) {
2290 IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
2291 return 0;
2292 }
2293
2294 q = AC_NUM - 1 - queue;
2295
2296 spin_lock_irqsave(&priv->lock, flags);
2297
2298 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
2299 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
2300 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
2301 priv->qos_data.def_qos_parm.ac[q].edca_txop =
2302 cpu_to_le16((params->txop * 32));
2303
2304 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
2305 priv->qos_data.qos_active = 1;
2306
2307 if (priv->iw_mode == NL80211_IFTYPE_AP)
2308 iwl_activate_qos(priv, 1);
2309 else if (priv->assoc_id && iwl_is_associated(priv))
2310 iwl_activate_qos(priv, 0);
2311
2312 spin_unlock_irqrestore(&priv->lock, flags);
2313
2314 IWL_DEBUG_MAC80211(priv, "leave\n");
2315 return 0;
2316}
2317EXPORT_SYMBOL(iwl_mac_conf_tx);
5bbe233b
AK		 2318
2319static void iwl_ht_conf(struct iwl_priv *priv,
02bb1bea 2320 struct ieee80211_bss_conf *bss_conf)
5bbe233b 2321{
fad95bf5 2322 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
5bbe233b
AK		 2323 struct ieee80211_sta *sta;
2324
2325 IWL_DEBUG_MAC80211(priv, "enter: \n");
2326
fad95bf5 2327 if (!ht_conf->is_ht)
5bbe233b
AK		 2328 return;
2329
fad95bf5 2330 ht_conf->ht_protection =
9ed6bcce 2331 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
fad95bf5 2332 ht_conf->non_GF_STA_present =
9ed6bcce 2333 !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
5bbe233b 2334
02bb1bea
JB		 2335 ht_conf->single_chain_sufficient = false;
2336
2337 switch (priv->iw_mode) {
2338 case NL80211_IFTYPE_STATION:
2339 rcu_read_lock();
5ed176e1 2340 sta = ieee80211_find_sta(priv->vif, priv->bssid);
02bb1bea
JB		 2341 if (sta) {
2342 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
2343 int maxstreams;
2344
2345 maxstreams = (ht_cap->mcs.tx_params &
2346 IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
2347 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2348 maxstreams += 1;
2349
2350 if ((ht_cap->mcs.rx_mask[1] == 0) &&
2351 (ht_cap->mcs.rx_mask[2] == 0))
2352 ht_conf->single_chain_sufficient = true;
2353 if (maxstreams <= 1)
2354 ht_conf->single_chain_sufficient = true;
2355 } else {
2356 /*
2357 * If at all, this can only happen through a race
2358 * when the AP disconnects us while we're still
2359 * setting up the connection, in that case mac80211
2360 * will soon tell us about that.
2361 */
2362 ht_conf->single_chain_sufficient = true;
2363 }
2364 rcu_read_unlock();
2365 break;
2366 case NL80211_IFTYPE_ADHOC:
2367 ht_conf->single_chain_sufficient = true;
2368 break;
2369 default:
2370 break;
2371 }
5bbe233b
AK		 2372
2373 IWL_DEBUG_MAC80211(priv, "leave\n");
2374}
2375
c91c3efc
AK		 2376static inline void iwl_set_no_assoc(struct iwl_priv *priv)
2377{
2378 priv->assoc_id = 0;
2379 iwl_led_disassociate(priv);
2380 /*
2381 * inform the ucode that there is no longer an
2382 * association and that no more packets should be
2383 * sent
2384 */
2385 priv->staging_rxon.filter_flags &=
2386 ~RXON_FILTER_ASSOC_MSK;
2387 priv->staging_rxon.assoc_id = 0;
2388 iwlcore_commit_rxon(priv);
2389}
2390
5bbe233b
AK		 2391#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
2392void iwl_bss_info_changed(struct ieee80211_hw *hw,
2d0ddec5
JB		 2393 struct ieee80211_vif *vif,
2394 struct ieee80211_bss_conf *bss_conf,
2395 u32 changes)
5bbe233b
AK		 2396{
2397 struct iwl_priv *priv = hw->priv;
3a650292 2398 int ret;
5bbe233b
AK		 2399
2400 IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
2401
2d0ddec5
JB		 2402 if (!iwl_is_alive(priv))
2403 return;
2404
2405 mutex_lock(&priv->mutex);
2406
2407 if (changes & BSS_CHANGED_BEACON &&
2408 priv->iw_mode == NL80211_IFTYPE_AP) {
2409 dev_kfree_skb(priv->ibss_beacon);
2410 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
2411 }
2412
d7129e19
JB		 2413 if (changes & BSS_CHANGED_BEACON_INT) {
2414 priv->beacon_int = bss_conf->beacon_int;
2415 /* TODO: in AP mode, do something to make this take effect */
2416 }
2417
2418 if (changes & BSS_CHANGED_BSSID) {
2419 IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
2420
2421 /*
2422 * If there is currently a HW scan going on in the
2423 * background then we need to cancel it else the RXON
2424 * below/in post_associate will fail.
2425 */
2d0ddec5 2426 if (iwl_scan_cancel_timeout(priv, 100)) {
d7129e19 2427 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
2d0ddec5
JB		 2428 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
2429 mutex_unlock(&priv->mutex);
2430 return;
2431 }
2d0ddec5 2432
d7129e19
JB		 2433 /* mac80211 only sets assoc when in STATION mode */
2434 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
2435 bss_conf->assoc) {
2436 memcpy(priv->staging_rxon.bssid_addr,
2437 bss_conf->bssid, ETH_ALEN);
2d0ddec5 2438
d7129e19
JB		 2439 /* currently needed in a few places */
2440 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2441 } else {
2442 priv->staging_rxon.filter_flags &=
2443 ~RXON_FILTER_ASSOC_MSK;
2d0ddec5 2444 }
d7129e19 2445
2d0ddec5
JB		 2446 }
2447
d7129e19
JB		 2448 /*
2449 * This needs to be after setting the BSSID in case
2450 * mac80211 decides to do both changes at once because
2451 * it will invoke post_associate.
2452 */
2d0ddec5
JB		 2453 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2454 changes & BSS_CHANGED_BEACON) {
2455 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2456
2457 if (beacon)
2458 iwl_mac_beacon_update(hw, beacon);
2459 }
2460
5bbe233b
AK		 2461 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
2462 IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
2463 bss_conf->use_short_preamble);
2464 if (bss_conf->use_short_preamble)
2465 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2466 else
2467 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2468 }
2469
2470 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
2471 IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
2472 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
2473 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
2474 else
2475 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
2476 }
2477
d7129e19
JB		 2478 if (changes & BSS_CHANGED_BASIC_RATES) {
2479 /* XXX use this information
2480 *
2481 * To do that, remove code from iwl_set_rate() and put something
2482 * like this here:
2483 *
2484 if (A-band)
2485 priv->staging_rxon.ofdm_basic_rates =
2486 bss_conf->basic_rates;
2487 else
2488 priv->staging_rxon.ofdm_basic_rates =
2489 bss_conf->basic_rates >> 4;
2490 priv->staging_rxon.cck_basic_rates =
2491 bss_conf->basic_rates & 0xF;
2492 */
2493 }
2494
5bbe233b
AK		 2495 if (changes & BSS_CHANGED_HT) {
2496 iwl_ht_conf(priv, bss_conf);
45823531
AK		 2497
2498 if (priv->cfg->ops->hcmd->set_rxon_chain)
2499 priv->cfg->ops->hcmd->set_rxon_chain(priv);
5bbe233b
AK		 2500 }
2501
2502 if (changes & BSS_CHANGED_ASSOC) {
2503 IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
5bbe233b
AK		 2504 if (bss_conf->assoc) {
2505 priv->assoc_id = bss_conf->aid;
2506 priv->beacon_int = bss_conf->beacon_int;
5bbe233b
AK		 2507 priv->timestamp = bss_conf->timestamp;
2508 priv->assoc_capability = bss_conf->assoc_capability;
2509
e932a609
JB		 2510 iwl_led_associate(priv);
2511
d7129e19
JB		 2512 /*
2513 * We have just associated, don't start scan too early
2514 * leave time for EAPOL exchange to complete.
2515 *
2516 * XXX: do this in mac80211
5bbe233b
AK		 2517 */
2518 priv->next_scan_jiffies = jiffies +
2519 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
d7129e19
JB		 2520 if (!iwl_is_rfkill(priv))
2521 priv->cfg->ops->lib->post_associate(priv);
c91c3efc
AK		 2522 } else
2523 iwl_set_no_assoc(priv);
d7129e19
JB		 2524 }
2525
2526 if (changes && iwl_is_associated(priv) && priv->assoc_id) {
2527 IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
2528 changes);
2529 ret = iwl_send_rxon_assoc(priv);
2530 if (!ret) {
2531 /* Sync active_rxon with latest change. */
2532 memcpy((void *)&priv->active_rxon,
2533 &priv->staging_rxon,
2534 sizeof(struct iwl_rxon_cmd));
5bbe233b 2535 }
5bbe233b 2536 }
d7129e19 2537
c91c3efc
AK		 2538 if (changes & BSS_CHANGED_BEACON_ENABLED) {
2539 if (vif->bss_conf.enable_beacon) {
2540 memcpy(priv->staging_rxon.bssid_addr,
2541 bss_conf->bssid, ETH_ALEN);
2542 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2543 iwlcore_config_ap(priv);
2544 } else
2545 iwl_set_no_assoc(priv);
f513dfff
DH		 2546 }
2547
d7129e19
JB		 2548 mutex_unlock(&priv->mutex);
2549
2d0ddec5 2550 IWL_DEBUG_MAC80211(priv, "leave\n");
5bbe233b
AK		 2551}
2552EXPORT_SYMBOL(iwl_bss_info_changed);
2553
9944b938
AK		 2554int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
2555{
2556 struct iwl_priv *priv = hw->priv;
2557 unsigned long flags;
2558 __le64 timestamp;
2559
2560 IWL_DEBUG_MAC80211(priv, "enter\n");
2561
2562 if (!iwl_is_ready_rf(priv)) {
2563 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2564 return -EIO;
2565 }
2566
2567 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2568 IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
2569 return -EIO;
2570 }
2571
2572 spin_lock_irqsave(&priv->lock, flags);
2573
2574 if (priv->ibss_beacon)
2575 dev_kfree_skb(priv->ibss_beacon);
2576
2577 priv->ibss_beacon = skb;
2578
2579 priv->assoc_id = 0;
2580 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
2581 priv->timestamp = le64_to_cpu(timestamp);
2582
2583 IWL_DEBUG_MAC80211(priv, "leave\n");
2584 spin_unlock_irqrestore(&priv->lock, flags);
2585
2586 iwl_reset_qos(priv);
2587
2588 priv->cfg->ops->lib->post_associate(priv);
2589
2590
2591 return 0;
2592}
2593EXPORT_SYMBOL(iwl_mac_beacon_update);
2594
727882d6
AK		 2595int iwl_set_mode(struct iwl_priv *priv, int mode)
2596{
2597 if (mode == NL80211_IFTYPE_ADHOC) {
2598 const struct iwl_channel_info *ch_info;
2599
2600 ch_info = iwl_get_channel_info(priv,
2601 priv->band,
2602 le16_to_cpu(priv->staging_rxon.channel));
2603
2604 if (!ch_info || !is_channel_ibss(ch_info)) {
2605 IWL_ERR(priv, "channel %d not IBSS channel\n",
2606 le16_to_cpu(priv->staging_rxon.channel));
2607 return -EINVAL;
2608 }
2609 }
2610
2611 iwl_connection_init_rx_config(priv, mode);
2612
2613 if (priv->cfg->ops->hcmd->set_rxon_chain)
2614 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2615
2616 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2617
c587de0b 2618 iwl_clear_stations_table(priv);
727882d6
AK		 2619
2620 /* dont commit rxon if rf-kill is on*/
2621 if (!iwl_is_ready_rf(priv))
2622 return -EAGAIN;
2623
727882d6
AK		 2624 iwlcore_commit_rxon(priv);
2625
2626 return 0;
2627}
2628EXPORT_SYMBOL(iwl_set_mode);
2629
cbb6ab94 2630int iwl_mac_add_interface(struct ieee80211_hw *hw,
1ed32e4f 2631 struct ieee80211_vif *vif)
cbb6ab94
AK		 2632{
2633 struct iwl_priv *priv = hw->priv;
2634 unsigned long flags;
2635
1ed32e4f 2636 IWL_DEBUG_MAC80211(priv, "enter: type %d\n", vif->type);
cbb6ab94
AK		 2637
2638 if (priv->vif) {
2639 IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
2640 return -EOPNOTSUPP;
2641 }
2642
2643 spin_lock_irqsave(&priv->lock, flags);
1ed32e4f
JB		 2644 priv->vif = vif;
2645 priv->iw_mode = vif->type;
cbb6ab94
AK		 2646
2647 spin_unlock_irqrestore(&priv->lock, flags);
2648
2649 mutex_lock(&priv->mutex);
2650
1ed32e4f
JB		 2651 if (vif->addr) {
2652 IWL_DEBUG_MAC80211(priv, "Set %pM\n", vif->addr);
2653 memcpy(priv->mac_addr, vif->addr, ETH_ALEN);
cbb6ab94
AK		 2654 }
2655
1ed32e4f 2656 if (iwl_set_mode(priv, vif->type) == -EAGAIN)
cbb6ab94
AK		 2657 /* we are not ready, will run again when ready */
2658 set_bit(STATUS_MODE_PENDING, &priv->status);
2659
2660 mutex_unlock(&priv->mutex);
2661
2662 IWL_DEBUG_MAC80211(priv, "leave\n");
2663 return 0;
2664}
2665EXPORT_SYMBOL(iwl_mac_add_interface);
2666
d8052319 2667void iwl_mac_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 2668 struct ieee80211_vif *vif)
d8052319
AK		 2669{
2670 struct iwl_priv *priv = hw->priv;
2671
2672 IWL_DEBUG_MAC80211(priv, "enter\n");
2673
2674 mutex_lock(&priv->mutex);
2675
2676 if (iwl_is_ready_rf(priv)) {
2677 iwl_scan_cancel_timeout(priv, 100);
2678 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2679 iwlcore_commit_rxon(priv);
2680 }
1ed32e4f 2681 if (priv->vif == vif) {
d8052319
AK		 2682 priv->vif = NULL;
2683 memset(priv->bssid, 0, ETH_ALEN);
2684 }
2685 mutex_unlock(&priv->mutex);
2686
2687 IWL_DEBUG_MAC80211(priv, "leave\n");
2688
2689}
2690EXPORT_SYMBOL(iwl_mac_remove_interface);
2691
4808368d
AK		 2692/**
2693 * iwl_mac_config - mac80211 config callback
2694 *
2695 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
2696 * be set inappropriately and the driver currently sets the hardware up to
2697 * use it whenever needed.
2698 */
2699int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
2700{
2701 struct iwl_priv *priv = hw->priv;
2702 const struct iwl_channel_info *ch_info;
2703 struct ieee80211_conf *conf = &hw->conf;
fad95bf5 2704 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
4808368d
AK		 2705 unsigned long flags = 0;
2706 int ret = 0;
2707 u16 ch;
2708 int scan_active = 0;
2709
2710 mutex_lock(&priv->mutex);
2711
4808368d
AK		 2712 IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
2713 conf->channel->hw_value, changed);
2714
2715 if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
2716 test_bit(STATUS_SCANNING, &priv->status))) {
2717 scan_active = 1;
2718 IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
2719 }
2720
ba37a3d0
JB		 2721 if (changed & (IEEE80211_CONF_CHANGE_SMPS |
2722 IEEE80211_CONF_CHANGE_CHANNEL)) {
2723 /* mac80211 uses static for non-HT which is what we want */
2724 priv->current_ht_config.smps = conf->smps_mode;
2725
2726 /*
2727 * Recalculate chain counts.
2728 *
2729 * If monitor mode is enabled then mac80211 will
2730 * set up the SM PS mode to OFF if an HT channel is
2731 * configured.
2732 */
2733 if (priv->cfg->ops->hcmd->set_rxon_chain)
2734 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2735 }
4808368d
AK		 2736
2737 /* during scanning mac80211 will delay channel setting until
2738 * scan finish with changed = 0
2739 */
2740 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
2741 if (scan_active)
2742 goto set_ch_out;
2743
2744 ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
2745 ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
2746 if (!is_channel_valid(ch_info)) {
2747 IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
2748 ret = -EINVAL;
2749 goto set_ch_out;
2750 }
2751
2752 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2753 !is_channel_ibss(ch_info)) {
2754 IWL_ERR(priv, "channel %d in band %d not "
2755 "IBSS channel\n",
2756 conf->channel->hw_value, conf->channel->band);
2757 ret = -EINVAL;
2758 goto set_ch_out;
2759 }
2760
4808368d
AK		 2761 spin_lock_irqsave(&priv->lock, flags);
2762
28bd723b
DH		 2763 /* Configure HT40 channels */
2764 ht_conf->is_ht = conf_is_ht(conf);
2765 if (ht_conf->is_ht) {
2766 if (conf_is_ht40_minus(conf)) {
2767 ht_conf->extension_chan_offset =
2768 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
c812ee24 2769 ht_conf->is_40mhz = true;
28bd723b
DH		 2770 } else if (conf_is_ht40_plus(conf)) {
2771 ht_conf->extension_chan_offset =
2772 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
c812ee24 2773 ht_conf->is_40mhz = true;
28bd723b
DH		 2774 } else {
2775 ht_conf->extension_chan_offset =
2776 IEEE80211_HT_PARAM_CHA_SEC_NONE;
c812ee24 2777 ht_conf->is_40mhz = false;
28bd723b
DH		 2778 }
2779 } else
c812ee24 2780 ht_conf->is_40mhz = false;
28bd723b
DH		 2781 /* Default to no protection. Protection mode will later be set
2782 * from BSS config in iwl_ht_conf */
2783 ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
4808368d
AK		 2784
2785 /* if we are switching from ht to 2.4 clear flags
2786 * from any ht related info since 2.4 does not
2787 * support ht */
2788 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
2789 priv->staging_rxon.flags = 0;
2790
2791 iwl_set_rxon_channel(priv, conf->channel);
2792
2793 iwl_set_flags_for_band(priv, conf->channel->band);
2794 spin_unlock_irqrestore(&priv->lock, flags);
0924e519
WYG		 2795 if (iwl_is_associated(priv) &&
2796 (le16_to_cpu(priv->active_rxon.channel) != ch) &&
2797 priv->cfg->ops->lib->set_channel_switch) {
2798 iwl_set_rate(priv);
2799 /*
2800 * at this point, staging_rxon has the
2801 * configuration for channel switch
2802 */
2803 ret = priv->cfg->ops->lib->set_channel_switch(priv,
2804 ch);
2805 if (!ret) {
2806 iwl_print_rx_config_cmd(priv);
2807 goto out;
2808 }
2809 priv->switch_rxon.switch_in_progress = false;
2810 }
4808368d
AK		 2811 set_ch_out:
2812 /* The list of supported rates and rate mask can be different
2813 * for each band; since the band may have changed, reset
2814 * the rate mask to what mac80211 lists */
2815 iwl_set_rate(priv);
2816 }
2817
78f5fb7f
JB		 2818 if (changed & (IEEE80211_CONF_CHANGE_PS |
2819 IEEE80211_CONF_CHANGE_IDLE)) {
e312c24c 2820 ret = iwl_power_update_mode(priv, false);
4808368d 2821 if (ret)
e312c24c 2822 IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
4808368d
AK		 2823 }
2824
2825 if (changed & IEEE80211_CONF_CHANGE_POWER) {
2826 IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
2827 priv->tx_power_user_lmt, conf->power_level);
2828
2829 iwl_set_tx_power(priv, conf->power_level, false);
2830 }
2831
0cf4c01e
MA		 2832 if (!iwl_is_ready(priv)) {
2833 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2834 goto out;
2835 }
2836
4808368d
AK		 2837 if (scan_active)
2838 goto out;
2839
2840 if (memcmp(&priv->active_rxon,
2841 &priv->staging_rxon, sizeof(priv->staging_rxon)))
2842 iwlcore_commit_rxon(priv);
2843 else
2844 IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
2845
2846
2847out:
2848 IWL_DEBUG_MAC80211(priv, "leave\n");
2849 mutex_unlock(&priv->mutex);
2850 return ret;
2851}
2852EXPORT_SYMBOL(iwl_mac_config);
2853
aa89f31e
AK		 2854int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
2855 struct ieee80211_tx_queue_stats *stats)
2856{
2857 struct iwl_priv *priv = hw->priv;
2858 int i, avail;
2859 struct iwl_tx_queue *txq;
2860 struct iwl_queue *q;
2861 unsigned long flags;
2862
2863 IWL_DEBUG_MAC80211(priv, "enter\n");
2864
2865 if (!iwl_is_ready_rf(priv)) {
2866 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2867 return -EIO;
2868 }
2869
2870 spin_lock_irqsave(&priv->lock, flags);
2871
2872 for (i = 0; i < AC_NUM; i++) {
2873 txq = &priv->txq[i];
2874 q = &txq->q;
2875 avail = iwl_queue_space(q);
2876
2877 stats[i].len = q->n_window - avail;
2878 stats[i].limit = q->n_window - q->high_mark;
2879 stats[i].count = q->n_window;
2880
2881 }
2882 spin_unlock_irqrestore(&priv->lock, flags);
2883
2884 IWL_DEBUG_MAC80211(priv, "leave\n");
2885
2886 return 0;
2887}
2888EXPORT_SYMBOL(iwl_mac_get_tx_stats);
2889
bd564261
AK		 2890void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
2891{
2892 struct iwl_priv *priv = hw->priv;
2893 unsigned long flags;
2894
2895 mutex_lock(&priv->mutex);
2896 IWL_DEBUG_MAC80211(priv, "enter\n");
2897
2898 spin_lock_irqsave(&priv->lock, flags);
fad95bf5 2899 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
bd564261
AK		 2900 spin_unlock_irqrestore(&priv->lock, flags);
2901
2902 iwl_reset_qos(priv);
2903
2904 spin_lock_irqsave(&priv->lock, flags);
2905 priv->assoc_id = 0;
2906 priv->assoc_capability = 0;
2907 priv->assoc_station_added = 0;
2908
2909 /* new association get rid of ibss beacon skb */
2910 if (priv->ibss_beacon)
2911 dev_kfree_skb(priv->ibss_beacon);
2912
2913 priv->ibss_beacon = NULL;
2914
57c4d7b4 2915 priv->beacon_int = priv->vif->bss_conf.beacon_int;
bd564261
AK		 2916 priv->timestamp = 0;
2917 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
2918 priv->beacon_int = 0;
2919
2920 spin_unlock_irqrestore(&priv->lock, flags);
2921
2922 if (!iwl_is_ready_rf(priv)) {
2923 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2924 mutex_unlock(&priv->mutex);
2925 return;
2926 }
2927
2928 /* we are restarting association process
2929 * clear RXON_FILTER_ASSOC_MSK bit
2930 */
2931 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2932 iwl_scan_cancel_timeout(priv, 100);
2933 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2934 iwlcore_commit_rxon(priv);
2935 }
2936
bd564261 2937 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
bd564261
AK		 2938 IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
2939 mutex_unlock(&priv->mutex);
2940 return;
2941 }
2942
2943 iwl_set_rate(priv);
2944
2945 mutex_unlock(&priv->mutex);
2946
2947 IWL_DEBUG_MAC80211(priv, "leave\n");
2948}
2949EXPORT_SYMBOL(iwl_mac_reset_tsf);
2950
88804e2b
WYG		 2951int iwl_alloc_txq_mem(struct iwl_priv *priv)
2952{
2953 if (!priv->txq)
2954 priv->txq = kzalloc(
2955 sizeof(struct iwl_tx_queue) * priv->cfg->num_of_queues,
2956 GFP_KERNEL);
2957 if (!priv->txq) {
2958 IWL_ERR(priv, "Not enough memory for txq \n");
2959 return -ENOMEM;
2960 }
2961 return 0;
2962}
2963EXPORT_SYMBOL(iwl_alloc_txq_mem);
2964
2965void iwl_free_txq_mem(struct iwl_priv *priv)
2966{
2967 kfree(priv->txq);
2968 priv->txq = NULL;
2969}
2970EXPORT_SYMBOL(iwl_free_txq_mem);
2971
1933ac4d
WYG		 2972int iwl_send_wimax_coex(struct iwl_priv *priv)
2973{
2974 struct iwl_wimax_coex_cmd uninitialized_var(coex_cmd);
2975
2976 if (priv->cfg->support_wimax_coexist) {
2977 /* UnMask wake up src at associated sleep */
2978 coex_cmd.flags |= COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
2979
2980 /* UnMask wake up src at unassociated sleep */
2981 coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
2982 memcpy(coex_cmd.sta_prio, cu_priorities,
2983 sizeof(struct iwl_wimax_coex_event_entry) *
2984 COEX_NUM_OF_EVENTS);
2985
2986 /* enabling the coexistence feature */
2987 coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
2988
2989 /* enabling the priorities tables */
2990 coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
2991 } else {
2992 /* coexistence is disabled */
2993 memset(&coex_cmd, 0, sizeof(coex_cmd));
2994 }
2995 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
2996 sizeof(coex_cmd), &coex_cmd);
2997}
2998EXPORT_SYMBOL(iwl_send_wimax_coex);
2999
20594eb0
WYG		 3000#ifdef CONFIG_IWLWIFI_DEBUGFS
3001
3002#define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
3003
3004void iwl_reset_traffic_log(struct iwl_priv *priv)
3005{
3006 priv->tx_traffic_idx = 0;
3007 priv->rx_traffic_idx = 0;
3008 if (priv->tx_traffic)
3009 memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
3010 if (priv->rx_traffic)
3011 memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
3012}
3013
3014int iwl_alloc_traffic_mem(struct iwl_priv *priv)
3015{
3016 u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
3017
3018 if (iwl_debug_level & IWL_DL_TX) {
3019 if (!priv->tx_traffic) {
3020 priv->tx_traffic =
3021 kzalloc(traffic_size, GFP_KERNEL);
3022 if (!priv->tx_traffic)
3023 return -ENOMEM;
3024 }
3025 }
3026 if (iwl_debug_level & IWL_DL_RX) {
3027 if (!priv->rx_traffic) {
3028 priv->rx_traffic =
3029 kzalloc(traffic_size, GFP_KERNEL);
3030 if (!priv->rx_traffic)
3031 return -ENOMEM;
3032 }
3033 }
3034 iwl_reset_traffic_log(priv);
3035 return 0;
3036}
3037EXPORT_SYMBOL(iwl_alloc_traffic_mem);
3038
3039void iwl_free_traffic_mem(struct iwl_priv *priv)
3040{
3041 kfree(priv->tx_traffic);
3042 priv->tx_traffic = NULL;
3043
3044 kfree(priv->rx_traffic);
3045 priv->rx_traffic = NULL;
3046}
3047EXPORT_SYMBOL(iwl_free_traffic_mem);
3048
3049void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
3050 u16 length, struct ieee80211_hdr *header)
3051{
3052 __le16 fc;
3053 u16 len;
3054
3055 if (likely(!(iwl_debug_level & IWL_DL_TX)))
3056 return;
3057
3058 if (!priv->tx_traffic)
3059 return;
3060
3061 fc = header->frame_control;
3062 if (ieee80211_is_data(fc)) {
3063 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
3064 ? IWL_TRAFFIC_ENTRY_SIZE : length;
3065 memcpy((priv->tx_traffic +
3066 (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3067 header, len);
3068 priv->tx_traffic_idx =
3069 (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3070 }
3071}
3072EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
3073
3074void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
3075 u16 length, struct ieee80211_hdr *header)
3076{
3077 __le16 fc;
3078 u16 len;
3079
3080 if (likely(!(iwl_debug_level & IWL_DL_RX)))
3081 return;
3082
3083 if (!priv->rx_traffic)
3084 return;
3085
3086 fc = header->frame_control;
3087 if (ieee80211_is_data(fc)) {
3088 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
3089 ? IWL_TRAFFIC_ENTRY_SIZE : length;
3090 memcpy((priv->rx_traffic +
3091 (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3092 header, len);
3093 priv->rx_traffic_idx =
3094 (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3095 }
3096}
3097EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
22fdf3c9
WYG		 3098
3099const char *get_mgmt_string(int cmd)
3100{
3101 switch (cmd) {
3102 IWL_CMD(MANAGEMENT_ASSOC_REQ);
3103 IWL_CMD(MANAGEMENT_ASSOC_RESP);
3104 IWL_CMD(MANAGEMENT_REASSOC_REQ);
3105 IWL_CMD(MANAGEMENT_REASSOC_RESP);
3106 IWL_CMD(MANAGEMENT_PROBE_REQ);
3107 IWL_CMD(MANAGEMENT_PROBE_RESP);
3108 IWL_CMD(MANAGEMENT_BEACON);
3109 IWL_CMD(MANAGEMENT_ATIM);
3110 IWL_CMD(MANAGEMENT_DISASSOC);
3111 IWL_CMD(MANAGEMENT_AUTH);
3112 IWL_CMD(MANAGEMENT_DEAUTH);
3113 IWL_CMD(MANAGEMENT_ACTION);
3114 default:
3115 return "UNKNOWN";
3116
3117 }
3118}
3119
3120const char *get_ctrl_string(int cmd)
3121{
3122 switch (cmd) {
3123 IWL_CMD(CONTROL_BACK_REQ);
3124 IWL_CMD(CONTROL_BACK);
3125 IWL_CMD(CONTROL_PSPOLL);
3126 IWL_CMD(CONTROL_RTS);
3127 IWL_CMD(CONTROL_CTS);
3128 IWL_CMD(CONTROL_ACK);
3129 IWL_CMD(CONTROL_CFEND);
3130 IWL_CMD(CONTROL_CFENDACK);
3131 default:
3132 return "UNKNOWN";
3133
3134 }
3135}
3136
7163b8a4 3137void iwl_clear_traffic_stats(struct iwl_priv *priv)
22fdf3c9
WYG		 3138{
3139 memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
22fdf3c9 3140 memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
7163b8a4 3141 priv->led_tpt = 0;
22fdf3c9
WYG		 3142}
3143
3144/*
3145 * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
3146 * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
3147 * Use debugFs to display the rx/rx_statistics
3148 * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
3149 * information will be recorded, but DATA pkt still will be recorded
3150 * for the reason of iwl_led.c need to control the led blinking based on
3151 * number of tx and rx data.
3152 *
3153 */
3154void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
3155{
3156 struct traffic_stats *stats;
3157
3158 if (is_tx)
3159 stats = &priv->tx_stats;
3160 else
3161 stats = &priv->rx_stats;
3162
3163 if (ieee80211_is_mgmt(fc)) {
3164 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3165 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
3166 stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
3167 break;
3168 case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
3169 stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
3170 break;
3171 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
3172 stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
3173 break;
3174 case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
3175 stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
3176 break;
3177 case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
3178 stats->mgmt[MANAGEMENT_PROBE_REQ]++;
3179 break;
3180 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
3181 stats->mgmt[MANAGEMENT_PROBE_RESP]++;
3182 break;
3183 case cpu_to_le16(IEEE80211_STYPE_BEACON):
3184 stats->mgmt[MANAGEMENT_BEACON]++;
3185 break;
3186 case cpu_to_le16(IEEE80211_STYPE_ATIM):
3187 stats->mgmt[MANAGEMENT_ATIM]++;
3188 break;
3189 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
3190 stats->mgmt[MANAGEMENT_DISASSOC]++;
3191 break;
3192 case cpu_to_le16(IEEE80211_STYPE_AUTH):
3193 stats->mgmt[MANAGEMENT_AUTH]++;
3194 break;
3195 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
3196 stats->mgmt[MANAGEMENT_DEAUTH]++;
3197 break;
3198 case cpu_to_le16(IEEE80211_STYPE_ACTION):
3199 stats->mgmt[MANAGEMENT_ACTION]++;
3200 break;
3201 }
3202 } else if (ieee80211_is_ctl(fc)) {
3203 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3204 case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
3205 stats->ctrl[CONTROL_BACK_REQ]++;
3206 break;
3207 case cpu_to_le16(IEEE80211_STYPE_BACK):
3208 stats->ctrl[CONTROL_BACK]++;
3209 break;
3210 case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
3211 stats->ctrl[CONTROL_PSPOLL]++;
3212 break;
3213 case cpu_to_le16(IEEE80211_STYPE_RTS):
3214 stats->ctrl[CONTROL_RTS]++;
3215 break;
3216 case cpu_to_le16(IEEE80211_STYPE_CTS):
3217 stats->ctrl[CONTROL_CTS]++;
3218 break;
3219 case cpu_to_le16(IEEE80211_STYPE_ACK):
3220 stats->ctrl[CONTROL_ACK]++;
3221 break;
3222 case cpu_to_le16(IEEE80211_STYPE_CFEND):
3223 stats->ctrl[CONTROL_CFEND]++;
3224 break;
3225 case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
3226 stats->ctrl[CONTROL_CFENDACK]++;
3227 break;
3228 }
3229 } else {
3230 /* data */
3231 stats->data_cnt++;
3232 stats->data_bytes += len;
3233 }
d5f4cf71 3234 iwl_leds_background(priv);
22fdf3c9
WYG		 3235}
3236EXPORT_SYMBOL(iwl_update_stats);
20594eb0
WYG		 3237#endif
3238
696bdee3
WYG		 3239const static char *get_csr_string(int cmd)
3240{
3241 switch (cmd) {
3242 IWL_CMD(CSR_HW_IF_CONFIG_REG);
3243 IWL_CMD(CSR_INT_COALESCING);
3244 IWL_CMD(CSR_INT);
3245 IWL_CMD(CSR_INT_MASK);
3246 IWL_CMD(CSR_FH_INT_STATUS);
3247 IWL_CMD(CSR_GPIO_IN);
3248 IWL_CMD(CSR_RESET);
3249 IWL_CMD(CSR_GP_CNTRL);
3250 IWL_CMD(CSR_HW_REV);
3251 IWL_CMD(CSR_EEPROM_REG);
3252 IWL_CMD(CSR_EEPROM_GP);
3253 IWL_CMD(CSR_OTP_GP_REG);
3254 IWL_CMD(CSR_GIO_REG);
3255 IWL_CMD(CSR_GP_UCODE_REG);
3256 IWL_CMD(CSR_GP_DRIVER_REG);
3257 IWL_CMD(CSR_UCODE_DRV_GP1);
3258 IWL_CMD(CSR_UCODE_DRV_GP2);
3259 IWL_CMD(CSR_LED_REG);
3260 IWL_CMD(CSR_DRAM_INT_TBL_REG);
3261 IWL_CMD(CSR_GIO_CHICKEN_BITS);
3262 IWL_CMD(CSR_ANA_PLL_CFG);
3263 IWL_CMD(CSR_HW_REV_WA_REG);
3264 IWL_CMD(CSR_DBG_HPET_MEM_REG);
3265 default:
3266 return "UNKNOWN";
3267
3268 }
3269}
3270
3271void iwl_dump_csr(struct iwl_priv *priv)
3272{
3273 int i;
3274 u32 csr_tbl[] = {
3275 CSR_HW_IF_CONFIG_REG,
3276 CSR_INT_COALESCING,
3277 CSR_INT,
3278 CSR_INT_MASK,
3279 CSR_FH_INT_STATUS,
3280 CSR_GPIO_IN,
3281 CSR_RESET,
3282 CSR_GP_CNTRL,
3283 CSR_HW_REV,
3284 CSR_EEPROM_REG,
3285 CSR_EEPROM_GP,
3286 CSR_OTP_GP_REG,
3287 CSR_GIO_REG,
3288 CSR_GP_UCODE_REG,
3289 CSR_GP_DRIVER_REG,
3290 CSR_UCODE_DRV_GP1,
3291 CSR_UCODE_DRV_GP2,
3292 CSR_LED_REG,
3293 CSR_DRAM_INT_TBL_REG,
3294 CSR_GIO_CHICKEN_BITS,
3295 CSR_ANA_PLL_CFG,
3296 CSR_HW_REV_WA_REG,
3297 CSR_DBG_HPET_MEM_REG
3298 };
3299 IWL_ERR(priv, "CSR values:\n");
3300 IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
3301 "CSR_INT_PERIODIC_REG)\n");
3302 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
3303 IWL_ERR(priv, " %25s: 0X%08x\n",
3304 get_csr_string(csr_tbl[i]),
3305 iwl_read32(priv, csr_tbl[i]));
3306 }
3307}
3308EXPORT_SYMBOL(iwl_dump_csr);
3309
1b3eb823
WYG		 3310const static char *get_fh_string(int cmd)
3311{
3312 switch (cmd) {
3313 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
3314 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
3315 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
3316 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
3317 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
3318 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
3319 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
3320 IWL_CMD(FH_TSSR_TX_STATUS_REG);
3321 IWL_CMD(FH_TSSR_TX_ERROR_REG);
3322 default:
3323 return "UNKNOWN";
3324
3325 }
3326}
3327
3328int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
3329{
3330 int i;
3331#ifdef CONFIG_IWLWIFI_DEBUG
3332 int pos = 0;
3333 size_t bufsz = 0;
3334#endif
3335 u32 fh_tbl[] = {
3336 FH_RSCSR_CHNL0_STTS_WPTR_REG,
3337 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
3338 FH_RSCSR_CHNL0_WPTR,
3339 FH_MEM_RCSR_CHNL0_CONFIG_REG,
3340 FH_MEM_RSSR_SHARED_CTRL_REG,
3341 FH_MEM_RSSR_RX_STATUS_REG,
3342 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
3343 FH_TSSR_TX_STATUS_REG,
3344 FH_TSSR_TX_ERROR_REG
3345 };
3346#ifdef CONFIG_IWLWIFI_DEBUG
3347 if (display) {
3348 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
3349 *buf = kmalloc(bufsz, GFP_KERNEL);
3350 if (!*buf)
3351 return -ENOMEM;
3352 pos += scnprintf(*buf + pos, bufsz - pos,
3353 "FH register values:\n");
3354 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
3355 pos += scnprintf(*buf + pos, bufsz - pos,
3356 " %34s: 0X%08x\n",
3357 get_fh_string(fh_tbl[i]),
3358 iwl_read_direct32(priv, fh_tbl[i]));
3359 }
3360 return pos;
3361 }
3362#endif
3363 IWL_ERR(priv, "FH register values:\n");
3364 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
3365 IWL_ERR(priv, " %34s: 0X%08x\n",
3366 get_fh_string(fh_tbl[i]),
3367 iwl_read_direct32(priv, fh_tbl[i]));
3368 }
3369 return 0;
3370}
3371EXPORT_SYMBOL(iwl_dump_fh);
3372
afbdd69a
WYG		 3373void iwl_force_rf_reset(struct iwl_priv *priv)
3374{
3375 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3376 return;
3377
3378 if (!iwl_is_associated(priv)) {
3379 IWL_DEBUG_SCAN(priv, "force reset rejected: not associated\n");
3380 return;
3381 }
3382 /*
3383 * There is no easy and better way to force reset the radio,
3384 * the only known method is switching channel which will force to
3385 * reset and tune the radio.
3386 * Use internal short scan (single channel) operation to should
3387 * achieve this objective.
3388 * Driver should reset the radio when number of consecutive missed
3389 * beacon, or any other uCode error condition detected.
3390 */
3391 IWL_DEBUG_INFO(priv, "perform radio reset.\n");
3392 iwl_internal_short_hw_scan(priv);
3393 return;
3394}
3395EXPORT_SYMBOL(iwl_force_rf_reset);
3396
6da3a13e
WYG		 3397#ifdef CONFIG_PM
3398
3399int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
3400{
3401 struct iwl_priv *priv = pci_get_drvdata(pdev);
3402
3403 /*
3404 * This function is called when system goes into suspend state
3405 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
3406 * first but since iwl_mac_stop() has no knowledge of who the caller is,
3407 * it will not call apm_ops.stop() to stop the DMA operation.
3408 * Calling apm_ops.stop here to make sure we stop the DMA.
3409 */
3410 priv->cfg->ops->lib->apm_ops.stop(priv);
3411
3412 pci_save_state(pdev);
3413 pci_disable_device(pdev);
3414 pci_set_power_state(pdev, PCI_D3hot);
3415
3416 return 0;
3417}
3418EXPORT_SYMBOL(iwl_pci_suspend);
3419
3420int iwl_pci_resume(struct pci_dev *pdev)
3421{
3422 struct iwl_priv *priv = pci_get_drvdata(pdev);
3423 int ret;
3424
3425 pci_set_power_state(pdev, PCI_D0);
3426 ret = pci_enable_device(pdev);
3427 if (ret)
3428 return ret;
3429 pci_restore_state(pdev);
3430 iwl_enable_interrupts(priv);
3431
3432 return 0;
3433}
3434EXPORT_SYMBOL(iwl_pci_resume);
3435
3436#endif /* CONFIG_PM */
Clone of davem's net-next-2.6 tree