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iwlwifi: Tell the ucode immediately when association state changes
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
01f8162a 5 * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
df48c323
TW		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
df48c323
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
8ccde88a 31#include <linux/etherdevice.h>
1d0a082d 32#include <net/mac80211.h>
df48c323 33
6bc913bd 34#include "iwl-eeprom.h"
3e0d4cb1 35#include "iwl-dev.h" /* FIXME: remove */
19335774 36#include "iwl-debug.h"
df48c323 37#include "iwl-core.h"
b661c819 38#include "iwl-io.h"
5da4b55f 39#include "iwl-power.h"
83dde8c9 40#include "iwl-sta.h"
ef850d7c 41#include "iwl-helpers.h"
df48c323 42
1d0a082d 43
df48c323
TW		 44MODULE_DESCRIPTION("iwl core");
45MODULE_VERSION(IWLWIFI_VERSION);
a7b75207 46MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
712b6cf5 47MODULE_LICENSE("GPL");
df48c323 48
1933ac4d
WYG		 49static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
50 {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
51 0, COEX_UNASSOC_IDLE_FLAGS},
52 {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
53 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
54 {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
55 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
56 {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
57 0, COEX_CALIBRATION_FLAGS},
58 {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
59 0, COEX_PERIODIC_CALIBRATION_FLAGS},
60 {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
61 0, COEX_CONNECTION_ESTAB_FLAGS},
62 {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
63 0, COEX_ASSOCIATED_IDLE_FLAGS},
64 {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
65 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
66 {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
67 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
68 {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
69 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
70 {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
71 {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
72 {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
73 0, COEX_STAND_ALONE_DEBUG_FLAGS},
74 {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
75 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
76 {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
77 {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
78};
79
c7de35cd
RR		 80#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
81 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
82 IWL_RATE_SISO_##s##M_PLCP, \
83 IWL_RATE_MIMO2_##s##M_PLCP,\
84 IWL_RATE_MIMO3_##s##M_PLCP,\
85 IWL_RATE_##r##M_IEEE, \
86 IWL_RATE_##ip##M_INDEX, \
87 IWL_RATE_##in##M_INDEX, \
88 IWL_RATE_##rp##M_INDEX, \
89 IWL_RATE_##rn##M_INDEX, \
90 IWL_RATE_##pp##M_INDEX, \
91 IWL_RATE_##np##M_INDEX }
92
a562a9dd
RC		 93u32 iwl_debug_level;
94EXPORT_SYMBOL(iwl_debug_level);
95
ef850d7c
MA		 96static irqreturn_t iwl_isr(int irq, void *data);
97
c7de35cd
RR		 98/*
99 * Parameter order:
100 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
101 *
102 * If there isn't a valid next or previous rate then INV is used which
103 * maps to IWL_RATE_INVALID
104 *
105 */
1826dcc0 106const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 107 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
108 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
109 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
110 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
111 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
112 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
113 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
114 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
115 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
116 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
117 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
118 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
119 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
120 /* FIXME:RS: ^^ should be INV (legacy) */
121};
1826dcc0 122EXPORT_SYMBOL(iwl_rates);
c7de35cd 123
e7d326ac
TW		 124/**
125 * translate ucode response to mac80211 tx status control values
126 */
127void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 128 struct ieee80211_tx_info *info)
e7d326ac 129{
e6a9854b 130 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 131
e6a9854b 132 info->antenna_sel_tx =
e7d326ac
TW		 133 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
134 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 135 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 136 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 137 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
7aafef1c 138 if (rate_n_flags & RATE_MCS_HT40_MSK)
e6a9854b 139 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 140 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 141 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 142 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 143 r->flags |= IEEE80211_TX_RC_SHORT_GI;
31513be8 144 r->idx = iwl_hwrate_to_mac80211_idx(rate_n_flags, info->band);
e7d326ac
TW		 145}
146EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
147
148int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
149{
150 int idx = 0;
151
152 /* HT rate format */
153 if (rate_n_flags & RATE_MCS_HT_MSK) {
154 idx = (rate_n_flags & 0xff);
155
60d32215
DH		 156 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
157 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
158 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 159 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
160
161 idx += IWL_FIRST_OFDM_RATE;
162 /* skip 9M not supported in ht*/
163 if (idx >= IWL_RATE_9M_INDEX)
164 idx += 1;
165 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
166 return idx;
167
168 /* legacy rate format, search for match in table */
169 } else {
170 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
171 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
172 return idx;
173 }
174
175 return -1;
176}
177EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
178
31513be8
DH		 179int iwl_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
180{
181 int idx = 0;
182 int band_offset = 0;
183
184 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
185 if (rate_n_flags & RATE_MCS_HT_MSK) {
186 idx = (rate_n_flags & 0xff);
187 return idx;
188 /* Legacy rate format, search for match in table */
189 } else {
190 if (band == IEEE80211_BAND_5GHZ)
191 band_offset = IWL_FIRST_OFDM_RATE;
192 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
193 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
194 return idx - band_offset;
195 }
196
197 return -1;
198}
199
76eff18b
TW		 200u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
201{
202 int i;
203 u8 ind = ant;
204 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
205 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
206 if (priv->hw_params.valid_tx_ant & BIT(ind))
207 return ind;
208 }
209 return ant;
210}
47ff65c4 211EXPORT_SYMBOL(iwl_toggle_tx_ant);
57bd1bea
TW		 212
213const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
214EXPORT_SYMBOL(iwl_bcast_addr);
215
216
1d0a082d
AK		 217/* This function both allocates and initializes hw and priv. */
218struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
219 struct ieee80211_ops *hw_ops)
220{
221 struct iwl_priv *priv;
222
223 /* mac80211 allocates memory for this device instance, including
224 * space for this driver's private structure */
225 struct ieee80211_hw *hw =
226 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
227 if (hw == NULL) {
a3139c59
SO		 228 printk(KERN_ERR "%s: Can not allocate network device\n",
229 cfg->name);
1d0a082d
AK		 230 goto out;
231 }
232
233 priv = hw->priv;
234 priv->hw = hw;
235
236out:
237 return hw;
238}
239EXPORT_SYMBOL(iwl_alloc_all);
240
b661c819
TW		 241void iwl_hw_detect(struct iwl_priv *priv)
242{
243 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
244 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
245 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
246}
247EXPORT_SYMBOL(iwl_hw_detect);
248
1053d35f
RR		 249int iwl_hw_nic_init(struct iwl_priv *priv)
250{
251 unsigned long flags;
252 struct iwl_rx_queue *rxq = &priv->rxq;
253 int ret;
254
255 /* nic_init */
1053d35f 256 spin_lock_irqsave(&priv->lock, flags);
1b73af82 257 priv->cfg->ops->lib->apm_ops.init(priv);
74ba67ed
BC		 258
259 /* Set interrupt coalescing timer to 512 usecs */
260 iwl_write8(priv, CSR_INT_COALESCING, 512 / 32);
261
1053d35f
RR		 262 spin_unlock_irqrestore(&priv->lock, flags);
263
264 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
265
266 priv->cfg->ops->lib->apm_ops.config(priv);
267
268 /* Allocate the RX queue, or reset if it is already allocated */
269 if (!rxq->bd) {
270 ret = iwl_rx_queue_alloc(priv);
271 if (ret) {
15b1687c 272 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1053d35f
RR		 273 return -ENOMEM;
274 }
275 } else
276 iwl_rx_queue_reset(priv, rxq);
277
278 iwl_rx_replenish(priv);
279
280 iwl_rx_init(priv, rxq);
281
282 spin_lock_irqsave(&priv->lock, flags);
283
284 rxq->need_update = 1;
285 iwl_rx_queue_update_write_ptr(priv, rxq);
286
287 spin_unlock_irqrestore(&priv->lock, flags);
288
289 /* Allocate and init all Tx and Command queues */
290 ret = iwl_txq_ctx_reset(priv);
291 if (ret)
292 return ret;
293
294 set_bit(STATUS_INIT, &priv->status);
295
296 return 0;
297}
298EXPORT_SYMBOL(iwl_hw_nic_init);
299
14d2aac5
AK		 300/*
301 * QoS support
302*/
303void iwl_activate_qos(struct iwl_priv *priv, u8 force)
304{
305 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
306 return;
307
308 priv->qos_data.def_qos_parm.qos_flags = 0;
309
310 if (priv->qos_data.qos_cap.q_AP.queue_request &&
311 !priv->qos_data.qos_cap.q_AP.txop_request)
312 priv->qos_data.def_qos_parm.qos_flags |=
313 QOS_PARAM_FLG_TXOP_TYPE_MSK;
314 if (priv->qos_data.qos_active)
315 priv->qos_data.def_qos_parm.qos_flags |=
316 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
317
318 if (priv->current_ht_config.is_ht)
319 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
320
321 if (force || iwl_is_associated(priv)) {
322 IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
323 priv->qos_data.qos_active,
324 priv->qos_data.def_qos_parm.qos_flags);
325
326 iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
327 sizeof(struct iwl_qosparam_cmd),
328 &priv->qos_data.def_qos_parm, NULL);
329 }
330}
331EXPORT_SYMBOL(iwl_activate_qos);
332
f2c95b04
WYG		 333/*
334 * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
335 * (802.11b) (802.11a/g)
336 * AC_BK 15 1023 7 0 0
337 * AC_BE 15 1023 3 0 0
338 * AC_VI 7 15 2 6.016ms 3.008ms
339 * AC_VO 3 7 2 3.264ms 1.504ms
340 */
c7de35cd 341void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 342{
343 u16 cw_min = 15;
344 u16 cw_max = 1023;
345 u8 aifs = 2;
30dab79e 346 bool is_legacy = false;
bf85ea4f
AK		 347 unsigned long flags;
348 int i;
349
350 spin_lock_irqsave(&priv->lock, flags);
30dab79e
WT		 351 /* QoS always active in AP and ADHOC mode
352 * In STA mode wait for association
353 */
354 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
355 priv->iw_mode == NL80211_IFTYPE_AP)
356 priv->qos_data.qos_active = 1;
357 else
358 priv->qos_data.qos_active = 0;
bf85ea4f 359
30dab79e
WT		 360 /* check for legacy mode */
361 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
362 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
363 (priv->iw_mode == NL80211_IFTYPE_STATION &&
364 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
bf85ea4f
AK		 365 cw_min = 31;
366 is_legacy = 1;
367 }
368
369 if (priv->qos_data.qos_active)
370 aifs = 3;
371
f2c95b04 372 /* AC_BE */
bf85ea4f
AK		 373 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
374 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
375 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
376 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
377 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
378
379 if (priv->qos_data.qos_active) {
f2c95b04 380 /* AC_BK */
bf85ea4f
AK		 381 i = 1;
382 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
383 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
384 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
385 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
386 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
387
f2c95b04 388 /* AC_VI */
bf85ea4f
AK		 389 i = 2;
390 priv->qos_data.def_qos_parm.ac[i].cw_min =
391 cpu_to_le16((cw_min + 1) / 2 - 1);
392 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 393 cpu_to_le16(cw_min);
bf85ea4f
AK		 394 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
395 if (is_legacy)
396 priv->qos_data.def_qos_parm.ac[i].edca_txop =
397 cpu_to_le16(6016);
398 else
399 priv->qos_data.def_qos_parm.ac[i].edca_txop =
400 cpu_to_le16(3008);
401 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
402
f2c95b04 403 /* AC_VO */
bf85ea4f
AK		 404 i = 3;
405 priv->qos_data.def_qos_parm.ac[i].cw_min =
406 cpu_to_le16((cw_min + 1) / 4 - 1);
407 priv->qos_data.def_qos_parm.ac[i].cw_max =
f2c95b04 408 cpu_to_le16((cw_min + 1) / 2 - 1);
bf85ea4f
AK		 409 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
410 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
411 if (is_legacy)
412 priv->qos_data.def_qos_parm.ac[i].edca_txop =
413 cpu_to_le16(3264);
414 else
415 priv->qos_data.def_qos_parm.ac[i].edca_txop =
416 cpu_to_le16(1504);
417 } else {
418 for (i = 1; i < 4; i++) {
419 priv->qos_data.def_qos_parm.ac[i].cw_min =
420 cpu_to_le16(cw_min);
421 priv->qos_data.def_qos_parm.ac[i].cw_max =
422 cpu_to_le16(cw_max);
423 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
424 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
425 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
426 }
427 }
e1623446 428 IWL_DEBUG_QOS(priv, "set QoS to default \n");
bf85ea4f
AK		 429
430 spin_unlock_irqrestore(&priv->lock, flags);
431}
c7de35cd
RR		 432EXPORT_SYMBOL(iwl_reset_qos);
433
d9fe60de
JB		 434#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
435#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 436static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 437 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 438 enum ieee80211_band band)
439{
39130df3
RR		 440 u16 max_bit_rate = 0;
441 u8 rx_chains_num = priv->hw_params.rx_chains_num;
442 u8 tx_chains_num = priv->hw_params.tx_chains_num;
443
c7de35cd 444 ht_info->cap = 0;
d9fe60de 445 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 446
d9fe60de 447 ht_info->ht_supported = true;
c7de35cd 448
b261793d
DH		 449 if (priv->cfg->ht_greenfield_support)
450 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
d9fe60de 451 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
c15d20c1
WYG		 452 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
453 (priv->cfg->sm_ps_mode << 2));
39130df3 454 max_bit_rate = MAX_BIT_RATE_20_MHZ;
7aafef1c 455 if (priv->hw_params.ht40_channel & BIT(band)) {
d9fe60de
JB		 456 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
457 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
458 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 459 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 460 }
c7de35cd
RR		 461
462 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 463 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 464
465 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
466 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
467
d9fe60de 468 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 469 if (rx_chains_num >= 2)
d9fe60de 470 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 471 if (rx_chains_num >= 3)
d9fe60de 472 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 473
474 /* Highest supported Rx data rate */
475 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 476 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
477 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 478
479 /* Tx MCS capabilities */
d9fe60de 480 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 481 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 482 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
483 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
484 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 485 }
c7de35cd 486}
c7de35cd 487
c7de35cd
RR		 488/**
489 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
490 */
534166de 491int iwlcore_init_geos(struct iwl_priv *priv)
c7de35cd
RR		 492{
493 struct iwl_channel_info *ch;
494 struct ieee80211_supported_band *sband;
495 struct ieee80211_channel *channels;
496 struct ieee80211_channel *geo_ch;
497 struct ieee80211_rate *rates;
498 int i = 0;
499
500 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
501 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
e1623446 502 IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
c7de35cd
RR		 503 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
504 return 0;
505 }
506
507 channels = kzalloc(sizeof(struct ieee80211_channel) *
508 priv->channel_count, GFP_KERNEL);
509 if (!channels)
510 return -ENOMEM;
511
5027309b 512 rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY),
c7de35cd
RR		 513 GFP_KERNEL);
514 if (!rates) {
515 kfree(channels);
516 return -ENOMEM;
517 }
518
519 /* 5.2GHz channels start after the 2.4GHz channels */
520 sband = &priv->bands[IEEE80211_BAND_5GHZ];
521 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
522 /* just OFDM */
523 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
5027309b 524 sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
c7de35cd 525
49779293 526 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 527 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 528 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 529
530 sband = &priv->bands[IEEE80211_BAND_2GHZ];
531 sband->channels = channels;
532 /* OFDM & CCK */
533 sband->bitrates = rates;
5027309b 534 sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
c7de35cd 535
49779293 536 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 537 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 538 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 539
540 priv->ieee_channels = channels;
541 priv->ieee_rates = rates;
542
c7de35cd
RR		 543 for (i = 0; i < priv->channel_count; i++) {
544 ch = &priv->channel_info[i];
545
546 /* FIXME: might be removed if scan is OK */
547 if (!is_channel_valid(ch))
548 continue;
549
550 if (is_channel_a_band(ch))
551 sband = &priv->bands[IEEE80211_BAND_5GHZ];
552 else
553 sband = &priv->bands[IEEE80211_BAND_2GHZ];
554
555 geo_ch = &sband->channels[sband->n_channels++];
556
557 geo_ch->center_freq =
558 ieee80211_channel_to_frequency(ch->channel);
559 geo_ch->max_power = ch->max_power_avg;
560 geo_ch->max_antenna_gain = 0xff;
561 geo_ch->hw_value = ch->channel;
562
563 if (is_channel_valid(ch)) {
564 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
565 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
566
567 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
568 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
569
570 if (ch->flags & EEPROM_CHANNEL_RADAR)
571 geo_ch->flags |= IEEE80211_CHAN_RADAR;
572
7aafef1c 573 geo_ch->flags |= ch->ht40_extension_channel;
4d38c2e8 574
dc1b0973
WYG		 575 if (ch->max_power_avg > priv->tx_power_device_lmt)
576 priv->tx_power_device_lmt = ch->max_power_avg;
c7de35cd
RR		 577 } else {
578 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
579 }
580
e1623446 581 IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 582 ch->channel, geo_ch->center_freq,
583 is_channel_a_band(ch) ? "5.2" : "2.4",
584 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
585 "restricted" : "valid",
586 geo_ch->flags);
587 }
588
589 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
590 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW		 591 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
592 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
a3139c59
SO		 593 priv->pci_dev->device,
594 priv->pci_dev->subsystem_device);
c7de35cd
RR		 595 priv->cfg->sku &= ~IWL_SKU_A;
596 }
597
978785a3 598 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
a3139c59
SO		 599 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
600 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
c7de35cd
RR		 601
602 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
603
604 return 0;
605}
534166de 606EXPORT_SYMBOL(iwlcore_init_geos);
c7de35cd
RR		 607
608/*
609 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
610 */
534166de 611void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 612{
613 kfree(priv->ieee_channels);
614 kfree(priv->ieee_rates);
615 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
616}
534166de 617EXPORT_SYMBOL(iwlcore_free_geos);
c7de35cd 618
37dc70fe
AK		 619/*
620 * iwlcore_rts_tx_cmd_flag: Set rts/cts. 3945 and 4965 only share this
621 * function.
622 */
623void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
624 __le32 *tx_flags)
625{
626 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
627 *tx_flags |= TX_CMD_FLG_RTS_MSK;
628 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
629 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
630 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
631 *tx_flags |= TX_CMD_FLG_CTS_MSK;
632 }
633}
634EXPORT_SYMBOL(iwlcore_rts_tx_cmd_flag);
635
28a6b07a 636static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 637{
638 return !priv->current_ht_config.is_ht ||
02bb1bea 639 priv->current_ht_config.single_chain_sufficient;
c7de35cd 640}
963f5517 641
47c5196e
TW		 642static u8 iwl_is_channel_extension(struct iwl_priv *priv,
643 enum ieee80211_band band,
644 u16 channel, u8 extension_chan_offset)
645{
646 const struct iwl_channel_info *ch_info;
647
648 ch_info = iwl_get_channel_info(priv, band, channel);
649 if (!is_channel_valid(ch_info))
650 return 0;
651
d9fe60de 652 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
7aafef1c 653 return !(ch_info->ht40_extension_channel &
689da1b3 654 IEEE80211_CHAN_NO_HT40PLUS);
d9fe60de 655 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
7aafef1c 656 return !(ch_info->ht40_extension_channel &
689da1b3 657 IEEE80211_CHAN_NO_HT40MINUS);
47c5196e
TW		 658
659 return 0;
660}
661
7aafef1c 662u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
d9fe60de 663 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e 664{
fad95bf5 665 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
47c5196e 666
fad95bf5 667 if (!ht_conf->is_ht || !ht_conf->is_40mhz)
47c5196e
TW		 668 return 0;
669
a2b0f02e
WYG		 670 /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
671 * the bit will not set if it is pure 40MHz case
672 */
47c5196e 673 if (sta_ht_inf) {
a2b0f02e 674 if (!sta_ht_inf->ht_supported)
47c5196e
TW		 675 return 0;
676 }
1e4247d4
WYG		 677#ifdef CONFIG_IWLWIFI_DEBUG
678 if (priv->disable_ht40)
679 return 0;
680#endif
611d3eb7
WYG		 681 return iwl_is_channel_extension(priv, priv->band,
682 le16_to_cpu(priv->staging_rxon.channel),
fad95bf5 683 ht_conf->extension_chan_offset);
47c5196e 684}
7aafef1c 685EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
47c5196e 686
2c2f3b33
TW		 687static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
688{
689 u16 new_val = 0;
690 u16 beacon_factor = 0;
691
692 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
693 new_val = beacon_val / beacon_factor;
694
695 if (!new_val)
696 new_val = max_beacon_val;
697
698 return new_val;
699}
700
701void iwl_setup_rxon_timing(struct iwl_priv *priv)
702{
703 u64 tsf;
704 s32 interval_tm, rem;
705 unsigned long flags;
706 struct ieee80211_conf *conf = NULL;
707 u16 beacon_int;
708
709 conf = ieee80211_get_hw_conf(priv->hw);
710
711 spin_lock_irqsave(&priv->lock, flags);
712 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
713 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
714
715 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
716 beacon_int = priv->beacon_int;
717 priv->rxon_timing.atim_window = 0;
718 } else {
719 beacon_int = priv->vif->bss_conf.beacon_int;
720
721 /* TODO: we need to get atim_window from upper stack
722 * for now we set to 0 */
723 priv->rxon_timing.atim_window = 0;
724 }
725
726 beacon_int = iwl_adjust_beacon_interval(beacon_int,
727 priv->hw_params.max_beacon_itrvl * 1024);
728 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
729
730 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
731 interval_tm = beacon_int * 1024;
732 rem = do_div(tsf, interval_tm);
733 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
734
735 spin_unlock_irqrestore(&priv->lock, flags);
736 IWL_DEBUG_ASSOC(priv,
737 "beacon interval %d beacon timer %d beacon tim %d\n",
738 le16_to_cpu(priv->rxon_timing.beacon_interval),
739 le32_to_cpu(priv->rxon_timing.beacon_init_val),
740 le16_to_cpu(priv->rxon_timing.atim_window));
741}
742EXPORT_SYMBOL(iwl_setup_rxon_timing);
743
8ccde88a
SO		 744void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
745{
746 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
747
748 if (hw_decrypt)
749 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
750 else
751 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
752
753}
754EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
755
756/**
757 * iwl_check_rxon_cmd - validate RXON structure is valid
758 *
759 * NOTE: This is really only useful during development and can eventually
760 * be #ifdef'd out once the driver is stable and folks aren't actively
761 * making changes
762 */
763int iwl_check_rxon_cmd(struct iwl_priv *priv)
764{
765 int error = 0;
766 int counter = 1;
767 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
768
769 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
770 error |= le32_to_cpu(rxon->flags &
771 (RXON_FLG_TGJ_NARROW_BAND_MSK |
772 RXON_FLG_RADAR_DETECT_MSK));
773 if (error)
774 IWL_WARN(priv, "check 24G fields %d | %d\n",
775 counter++, error);
776 } else {
777 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
778 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
779 if (error)
780 IWL_WARN(priv, "check 52 fields %d | %d\n",
781 counter++, error);
782 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
783 if (error)
784 IWL_WARN(priv, "check 52 CCK %d | %d\n",
785 counter++, error);
786 }
787 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
788 if (error)
789 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
790
791 /* make sure basic rates 6Mbps and 1Mbps are supported */
792 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
793 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
794 if (error)
795 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
796
797 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
798 if (error)
799 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
800
801 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
802 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
803 if (error)
804 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
805 counter++, error);
806
807 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
808 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
809 if (error)
810 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
811 counter++, error);
812
813 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
814 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
815 if (error)
816 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
817 counter++, error);
818
819 if (error)
820 IWL_WARN(priv, "Tuning to channel %d\n",
821 le16_to_cpu(rxon->channel));
822
823 if (error) {
824 IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
825 return -1;
826 }
827 return 0;
828}
829EXPORT_SYMBOL(iwl_check_rxon_cmd);
830
831/**
832 * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
833 * @priv: staging_rxon is compared to active_rxon
834 *
835 * If the RXON structure is changing enough to require a new tune,
836 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
837 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
838 */
839int iwl_full_rxon_required(struct iwl_priv *priv)
840{
841
842 /* These items are only settable from the full RXON command */
843 if (!(iwl_is_associated(priv)) ||
844 compare_ether_addr(priv->staging_rxon.bssid_addr,
845 priv->active_rxon.bssid_addr) ||
846 compare_ether_addr(priv->staging_rxon.node_addr,
847 priv->active_rxon.node_addr) ||
848 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
849 priv->active_rxon.wlap_bssid_addr) ||
850 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
851 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
852 (priv->staging_rxon.air_propagation !=
853 priv->active_rxon.air_propagation) ||
854 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
855 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
856 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
857 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
c2105fa7
DH		 858 (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
859 priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
8ccde88a
SO		 860 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
861 return 1;
862
863 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
864 * be updated with the RXON_ASSOC command -- however only some
865 * flag transitions are allowed using RXON_ASSOC */
866
867 /* Check if we are not switching bands */
868 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
869 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
870 return 1;
871
872 /* Check if we are switching association toggle */
873 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
874 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
875 return 1;
876
877 return 0;
878}
879EXPORT_SYMBOL(iwl_full_rxon_required);
880
881u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
882{
883 int i;
884 int rate_mask;
885
886 /* Set rate mask*/
887 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
888 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
889 else
890 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
891
892 /* Find lowest valid rate */
893 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
894 i = iwl_rates[i].next_ieee) {
895 if (rate_mask & (1 << i))
896 return iwl_rates[i].plcp;
897 }
898
899 /* No valid rate was found. Assign the lowest one */
900 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
901 return IWL_RATE_1M_PLCP;
902 else
903 return IWL_RATE_6M_PLCP;
904}
905EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
906
fad95bf5 907void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf)
47c5196e 908{
c1adf9fb 909 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e 910
fad95bf5 911 if (!ht_conf->is_ht) {
a2b0f02e 912 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
42eb7c64 913 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
7aafef1c 914 RXON_FLG_HT40_PROT_MSK |
42eb7c64 915 RXON_FLG_HT_PROT_MSK);
47c5196e 916 return;
42eb7c64 917 }
47c5196e 918
a2b0f02e
WYG		 919 /* FIXME: if the definition of ht_protection changed, the "translation"
920 * will be needed for rxon->flags
921 */
fad95bf5 922 rxon->flags |= cpu_to_le32(ht_conf->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
a2b0f02e
WYG		 923
924 /* Set up channel bandwidth:
7aafef1c 925 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
a2b0f02e
WYG		 926 /* clear the HT channel mode before set the mode */
927 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
928 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
7aafef1c
WYG		 929 if (iwl_is_ht40_tx_allowed(priv, NULL)) {
930 /* pure ht40 */
fad95bf5 931 if (ht_conf->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
a2b0f02e 932 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
508b08e7 933 /* Note: control channel is opposite of extension channel */
fad95bf5 934 switch (ht_conf->extension_chan_offset) {
508b08e7
WYG		 935 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
936 rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
937 break;
938 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
939 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
940 break;
941 }
942 } else {
a2b0f02e 943 /* Note: control channel is opposite of extension channel */
fad95bf5 944 switch (ht_conf->extension_chan_offset) {
a2b0f02e
WYG		 945 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
946 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
947 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
948 break;
949 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
950 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
951 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
952 break;
953 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
954 default:
955 /* channel location only valid if in Mixed mode */
956 IWL_ERR(priv, "invalid extension channel offset\n");
957 break;
958 }
959 }
960 } else {
961 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
47c5196e
TW		 962 }
963
45823531
AK		 964 if (priv->cfg->ops->hcmd->set_rxon_chain)
965 priv->cfg->ops->hcmd->set_rxon_chain(priv);
47c5196e 966
02bb1bea 967 IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
ae5eb026 968 "extension channel offset 0x%x\n",
fad95bf5
JB		 969 le32_to_cpu(rxon->flags), ht_conf->ht_protection,
970 ht_conf->extension_chan_offset);
47c5196e
TW		 971 return;
972}
973EXPORT_SYMBOL(iwl_set_rxon_ht);
974
9e5e6c32
TW		 975#define IWL_NUM_RX_CHAINS_MULTIPLE 3
976#define IWL_NUM_RX_CHAINS_SINGLE 2
977#define IWL_NUM_IDLE_CHAINS_DUAL 2
978#define IWL_NUM_IDLE_CHAINS_SINGLE 1
979
2b396a12
JB		 980/*
981 * Determine how many receiver/antenna chains to use.
982 *
983 * More provides better reception via diversity. Fewer saves power
984 * at the expense of throughput, but only when not in powersave to
985 * start with.
986 *
c7de35cd
RR		 987 * MIMO (dual stream) requires at least 2, but works better with 3.
988 * This does not determine *which* chains to use, just how many.
989 */
28a6b07a 990static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 991{
c7de35cd 992 /* # of Rx chains to use when expecting MIMO. */
02bb1bea 993 if (is_single_rx_stream(priv))
9e5e6c32 994 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 995 else
9e5e6c32 996 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 997}
c7de35cd 998
2b396a12 999/*
3f3e0376
WYG		 1000 * When we are in power saving mode, unless device support spatial
1001 * multiplexing power save, use the active count for rx chain count.
2b396a12 1002 */
28a6b07a
TW		 1003static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
1004{
3f3e0376
WYG		 1005 int idle_cnt = active_cnt;
1006 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
1007
c15d20c1
WYG		 1008 /* # Rx chains when idling and maybe trying to save power */
1009 switch (priv->cfg->sm_ps_mode) {
1010 case WLAN_HT_CAP_SM_PS_STATIC:
1011 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
1012 break;
1013 case WLAN_HT_CAP_SM_PS_DYNAMIC:
1014 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
1015 IWL_NUM_IDLE_CHAINS_SINGLE;
1016 break;
1017 case WLAN_HT_CAP_SM_PS_DISABLED:
1018 break;
1019 case WLAN_HT_CAP_SM_PS_INVALID:
1020 default:
1021 IWL_ERR(priv, "invalid sm_ps mode %u\n",
1022 priv->cfg->sm_ps_mode);
1023 WARN_ON(1);
1024 break;
3f3e0376
WYG		 1025 }
1026 return idle_cnt;
c7de35cd
RR		 1027}
1028
04816448
GE		 1029/* up to 4 chains */
1030static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
1031{
1032 u8 res;
1033 res = (chain_bitmap & BIT(0)) >> 0;
1034 res += (chain_bitmap & BIT(1)) >> 1;
1035 res += (chain_bitmap & BIT(2)) >> 2;
9bddbab3 1036 res += (chain_bitmap & BIT(3)) >> 3;
04816448
GE		 1037 return res;
1038}
1039
4c4df78f
CR		 1040/**
1041 * iwl_is_monitor_mode - Determine if interface in monitor mode
1042 *
1043 * priv->iw_mode is set in add_interface, but add_interface is
1044 * never called for monitor mode. The only way mac80211 informs us about
1045 * monitor mode is through configuring filters (call to configure_filter).
1046 */
279b05d4 1047bool iwl_is_monitor_mode(struct iwl_priv *priv)
4c4df78f
CR		 1048{
1049 return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
1050}
279b05d4 1051EXPORT_SYMBOL(iwl_is_monitor_mode);
4c4df78f 1052
c7de35cd
RR		 1053/**
1054 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1055 *
1056 * Selects how many and which Rx receivers/antennas/chains to use.
1057 * This should not be used for scan command ... it puts data in wrong place.
1058 */
1059void iwl_set_rxon_chain(struct iwl_priv *priv)
1060{
28a6b07a
TW		 1061 bool is_single = is_single_rx_stream(priv);
1062 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 1063 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1064 u32 active_chains;
28a6b07a 1065 u16 rx_chain;
c7de35cd
RR		 1066
1067 /* Tell uCode which antennas are actually connected.
1068 * Before first association, we assume all antennas are connected.
1069 * Just after first association, iwl_chain_noise_calibration()
1070 * checks which antennas actually *are* connected. */
04816448
GE		 1071 if (priv->chain_noise_data.active_chains)
1072 active_chains = priv->chain_noise_data.active_chains;
1073 else
1074 active_chains = priv->hw_params.valid_rx_ant;
1075
1076 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 1077
1078 /* How many receivers should we use? */
28a6b07a
TW		 1079 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
1080 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
1081
28a6b07a 1082
04816448
GE		 1083 /* correct rx chain count according hw settings
1084 * and chain noise calibration
1085 */
1086 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
1087 if (valid_rx_cnt < active_rx_cnt)
1088 active_rx_cnt = valid_rx_cnt;
1089
1090 if (valid_rx_cnt < idle_rx_cnt)
1091 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 1092
1093 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1094 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1095
7b841727
RF		 1096 /* copied from 'iwl_bg_request_scan()' */
1097 /* Force use of chains B and C (0x6) for Rx for 4965
1098 * Avoid A (0x1) because of its off-channel reception on A-band.
1099 * MIMO is not used here, but value is required */
1100 if (iwl_is_monitor_mode(priv) &&
1101 !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
1102 ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
fff7a434
WYG		 1103 rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
1104 rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
1105 rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1106 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
7b841727
RF		 1107 }
1108
28a6b07a
TW		 1109 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
1110
9e5e6c32 1111 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 1112 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1113 else
1114 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1115
e1623446 1116 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 1117 priv->staging_rxon.rx_chain,
1118 active_rx_cnt, idle_rx_cnt);
1119
1120 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1121 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 1122}
1123EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 1124
1125/**
17e72782 1126 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 1127 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
1128 * @channel: Any channel valid for the requested phymode
1129
1130 * In addition to setting the staging RXON, priv->phymode is also set.
1131 *
1132 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
1133 * in the staging RXON flag structure based on the phymode
1134 */
17e72782 1135int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 1136{
17e72782
TW		 1137 enum ieee80211_band band = ch->band;
1138 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
1139
8622e705 1140 if (!iwl_get_channel_info(priv, band, channel)) {
e1623446 1141 IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
bf85ea4f
AK		 1142 channel, band);
1143 return -EINVAL;
1144 }
1145
1146 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
1147 (priv->band == band))
1148 return 0;
1149
1150 priv->staging_rxon.channel = cpu_to_le16(channel);
1151 if (band == IEEE80211_BAND_5GHZ)
1152 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
1153 else
1154 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1155
1156 priv->band = band;
1157
e1623446 1158 IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
bf85ea4f
AK		 1159
1160 return 0;
1161}
c7de35cd 1162EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 1163
8ccde88a
SO		 1164void iwl_set_flags_for_band(struct iwl_priv *priv,
1165 enum ieee80211_band band)
1166{
1167 if (band == IEEE80211_BAND_5GHZ) {
1168 priv->staging_rxon.flags &=
1169 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
1170 | RXON_FLG_CCK_MSK);
1171 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1172 } else {
1173 /* Copied from iwl_post_associate() */
1174 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
1175 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
1176 else
1177 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1178
1179 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
1180 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1181
1182 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1183 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1184 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
1185 }
1186}
8ccde88a
SO		 1187
1188/*
1189 * initialize rxon structure with default values from eeprom
1190 */
1191void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
1192{
1193 const struct iwl_channel_info *ch_info;
1194
1195 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
1196
1197 switch (mode) {
1198 case NL80211_IFTYPE_AP:
1199 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
1200 break;
1201
1202 case NL80211_IFTYPE_STATION:
1203 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
1204 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
1205 break;
1206
1207 case NL80211_IFTYPE_ADHOC:
1208 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1209 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1210 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
1211 RXON_FILTER_ACCEPT_GRP_MSK;
1212 break;
1213
8ccde88a
SO		 1214 default:
1215 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
1216 break;
1217 }
1218
1219#if 0
1220 /* TODO: Figure out when short_preamble would be set and cache from
1221 * that */
1222 if (!hw_to_local(priv->hw)->short_preamble)
1223 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1224 else
1225 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1226#endif
1227
1228 ch_info = iwl_get_channel_info(priv, priv->band,
1229 le16_to_cpu(priv->active_rxon.channel));
1230
1231 if (!ch_info)
1232 ch_info = &priv->channel_info[0];
1233
1234 /*
1235 * in some case A channels are all non IBSS
1236 * in this case force B/G channel
1237 */
1238 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
1239 !(is_channel_ibss(ch_info)))
1240 ch_info = &priv->channel_info[0];
1241
1242 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
1243 priv->band = ch_info->band;
1244
1245 iwl_set_flags_for_band(priv, priv->band);
1246
1247 priv->staging_rxon.ofdm_basic_rates =
1248 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1249 priv->staging_rxon.cck_basic_rates =
1250 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1251
a2b0f02e
WYG		 1252 /* clear both MIX and PURE40 mode flag */
1253 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
1254 RXON_FLG_CHANNEL_MODE_PURE_40);
8ccde88a
SO		 1255 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1256 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
1257 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
1258 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
11397a65 1259 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
8ccde88a
SO		 1260}
1261EXPORT_SYMBOL(iwl_connection_init_rx_config);
1262
782571f4 1263static void iwl_set_rate(struct iwl_priv *priv)
8ccde88a
SO		 1264{
1265 const struct ieee80211_supported_band *hw = NULL;
1266 struct ieee80211_rate *rate;
1267 int i;
1268
1269 hw = iwl_get_hw_mode(priv, priv->band);
1270 if (!hw) {
1271 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
1272 return;
1273 }
1274
1275 priv->active_rate = 0;
1276 priv->active_rate_basic = 0;
1277
1278 for (i = 0; i < hw->n_bitrates; i++) {
1279 rate = &(hw->bitrates[i]);
5027309b 1280 if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
8ccde88a
SO		 1281 priv->active_rate |= (1 << rate->hw_value);
1282 }
1283
e1623446 1284 IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
8ccde88a
SO		 1285 priv->active_rate, priv->active_rate_basic);
1286
1287 /*
1288 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
1289 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
1290 * OFDM
1291 */
1292 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
1293 priv->staging_rxon.cck_basic_rates =
1294 ((priv->active_rate_basic &
1295 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
1296 else
1297 priv->staging_rxon.cck_basic_rates =
1298 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1299
1300 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
1301 priv->staging_rxon.ofdm_basic_rates =
1302 ((priv->active_rate_basic &
1303 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
1304 IWL_FIRST_OFDM_RATE) & 0xFF;
1305 else
1306 priv->staging_rxon.ofdm_basic_rates =
1307 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1308}
8ccde88a
SO		 1309
1310void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1311{
2f301227 1312 struct iwl_rx_packet *pkt = rxb_addr(rxb);
8ccde88a
SO		 1313 struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
1314 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
4a56e965 1315
0924e519
WYG		 1316 if (priv->switch_rxon.switch_in_progress) {
1317 if (!le32_to_cpu(csa->status) &&
1318 (csa->channel == priv->switch_rxon.channel)) {
1319 rxon->channel = csa->channel;
1320 priv->staging_rxon.channel = csa->channel;
1321 IWL_DEBUG_11H(priv, "CSA notif: channel %d\n",
1322 le16_to_cpu(csa->channel));
1323 } else
1324 IWL_ERR(priv, "CSA notif (fail) : channel %d\n",
1325 le16_to_cpu(csa->channel));
1326
1327 priv->switch_rxon.switch_in_progress = false;
1328 }
8ccde88a
SO		 1329}
1330EXPORT_SYMBOL(iwl_rx_csa);
1331
1332#ifdef CONFIG_IWLWIFI_DEBUG
a643565e 1333void iwl_print_rx_config_cmd(struct iwl_priv *priv)
8ccde88a
SO		 1334{
1335 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
1336
e1623446 1337 IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
3d816c77 1338 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e1623446
TW		 1339 IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
1340 IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
1341 IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
8ccde88a 1342 le32_to_cpu(rxon->filter_flags));
e1623446
TW		 1343 IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
1344 IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
8ccde88a 1345 rxon->ofdm_basic_rates);
e1623446
TW		 1346 IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
1347 IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
1348 IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
1349 IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
8ccde88a 1350}
a643565e 1351EXPORT_SYMBOL(iwl_print_rx_config_cmd);
6686d17e 1352#endif
8ccde88a
SO		 1353/**
1354 * iwl_irq_handle_error - called for HW or SW error interrupt from card
1355 */
1356void iwl_irq_handle_error(struct iwl_priv *priv)
1357{
1358 /* Set the FW error flag -- cleared on iwl_down */
1359 set_bit(STATUS_FW_ERROR, &priv->status);
1360
1361 /* Cancel currently queued command. */
1362 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1363
3a3ff72c 1364 priv->cfg->ops->lib->dump_nic_error_log(priv);
8ccde88a 1365#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1366 if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) {
b7a79404 1367 priv->cfg->ops->lib->dump_nic_event_log(priv);
8ccde88a
SO		 1368 iwl_print_rx_config_cmd(priv);
1369 }
1370#endif
1371
1372 wake_up_interruptible(&priv->wait_command_queue);
1373
1374 /* Keep the restart process from trying to send host
1375 * commands by clearing the INIT status bit */
1376 clear_bit(STATUS_READY, &priv->status);
1377
1378 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 1379 IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
8ccde88a
SO		 1380 "Restarting adapter due to uCode error.\n");
1381
8ccde88a
SO		 1382 if (priv->cfg->mod_params->restart_fw)
1383 queue_work(priv->workqueue, &priv->restart);
1384 }
1385}
1386EXPORT_SYMBOL(iwl_irq_handle_error);
1387
d68b603c
AK		 1388int iwl_apm_stop_master(struct iwl_priv *priv)
1389{
5220af0c 1390 int ret = 0;
d68b603c 1391
5220af0c 1392 /* stop device's busmaster DMA activity */
d68b603c
AK		 1393 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1394
5220af0c 1395 ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
d68b603c 1396 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
5220af0c
BC		 1397 if (ret)
1398 IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
d68b603c 1399
d68b603c
AK		 1400 IWL_DEBUG_INFO(priv, "stop master\n");
1401
5220af0c 1402 return ret;
d68b603c
AK		 1403}
1404EXPORT_SYMBOL(iwl_apm_stop_master);
1405
1406void iwl_apm_stop(struct iwl_priv *priv)
1407{
fadb3582
BC		 1408 IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
1409
5220af0c 1410 /* Stop device's DMA activity */
d68b603c
AK		 1411 iwl_apm_stop_master(priv);
1412
5220af0c 1413 /* Reset the entire device */
d68b603c
AK		 1414 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1415
1416 udelay(10);
5220af0c
BC		 1417
1418 /*
1419 * Clear "initialization complete" bit to move adapter from
1420 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
1421 */
d68b603c 1422 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
d68b603c
AK		 1423}
1424EXPORT_SYMBOL(iwl_apm_stop);
1425
fadb3582
BC		 1426
1427/*
1428 * Start up NIC's basic functionality after it has been reset
1429 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1430 * NOTE: This does not load uCode nor start the embedded processor
1431 */
1432int iwl_apm_init(struct iwl_priv *priv)
1433{
1434 int ret = 0;
1435 u16 lctl;
1436
1437 IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
1438
1439 /*
1440 * Use "set_bit" below rather than "write", to preserve any hardware
1441 * bits already set by default after reset.
1442 */
1443
1444 /* Disable L0S exit timer (platform NMI Work/Around) */
1445 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1446 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1447
1448 /*
1449 * Disable L0s without affecting L1;
1450 * don't wait for ICH L0s (ICH bug W/A)
1451 */
1452 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1453 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1454
1455 /* Set FH wait threshold to maximum (HW error during stress W/A) */
1456 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
1457
1458 /*
1459 * Enable HAP INTA (interrupt from management bus) to
1460 * wake device's PCI Express link L1a -> L0s
1461 * NOTE: This is no-op for 3945 (non-existant bit)
1462 */
1463 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1464 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
1465
1466 /*
a6c5c731
BC		 1467 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
1468 * Check if BIOS (or OS) enabled L1-ASPM on this device.
1469 * If so (likely), disable L0S, so device moves directly L0->L1;
1470 * costs negligible amount of power savings.
1471 * If not (unlikely), enable L0S, so there is at least some
1472 * power savings, even without L1.
fadb3582
BC		 1473 */
1474 if (priv->cfg->set_l0s) {
1475 lctl = iwl_pcie_link_ctl(priv);
1476 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
1477 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
1478 /* L1-ASPM enabled; disable(!) L0S */
1479 iwl_set_bit(priv, CSR_GIO_REG,
1480 CSR_GIO_REG_VAL_L0S_ENABLED);
1481 IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
1482 } else {
1483 /* L1-ASPM disabled; enable(!) L0S */
1484 iwl_clear_bit(priv, CSR_GIO_REG,
1485 CSR_GIO_REG_VAL_L0S_ENABLED);
1486 IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
1487 }
1488 }
1489
1490 /* Configure analog phase-lock-loop before activating to D0A */
1491 if (priv->cfg->pll_cfg_val)
1492 iwl_set_bit(priv, CSR_ANA_PLL_CFG, priv->cfg->pll_cfg_val);
1493
1494 /*
1495 * Set "initialization complete" bit to move adapter from
1496 * D0U* --> D0A* (powered-up active) state.
1497 */
1498 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1499
1500 /*
1501 * Wait for clock stabilization; once stabilized, access to
1502 * device-internal resources is supported, e.g. iwl_write_prph()
1503 * and accesses to uCode SRAM.
1504 */
1505 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
1506 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1507 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1508 if (ret < 0) {
1509 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1510 goto out;
1511 }
1512
1513 /*
1514 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
1515 * BSM (Boostrap State Machine) is only in 3945 and 4965;
1516 * later devices (i.e. 5000 and later) have non-volatile SRAM,
1517 * and don't need BSM to restore data after power-saving sleep.
1518 *
1519 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
1520 * do not disable clocks. This preserves any hardware bits already
1521 * set by default in "CLK_CTRL_REG" after reset.
1522 */
1523 if (priv->cfg->use_bsm)
1524 iwl_write_prph(priv, APMG_CLK_EN_REG,
1525 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
1526 else
1527 iwl_write_prph(priv, APMG_CLK_EN_REG,
1528 APMG_CLK_VAL_DMA_CLK_RQT);
1529 udelay(20);
1530
1531 /* Disable L1-Active */
1532 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1533 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1534
1535out:
1536 return ret;
1537}
1538EXPORT_SYMBOL(iwl_apm_init);
1539
1540
1541
8ccde88a
SO		 1542void iwl_configure_filter(struct ieee80211_hw *hw,
1543 unsigned int changed_flags,
1544 unsigned int *total_flags,
3ac64bee 1545 u64 multicast)
8ccde88a
SO		 1546{
1547 struct iwl_priv *priv = hw->priv;
1548 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
1549
e1623446 1550 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
8ccde88a
SO		 1551 changed_flags, *total_flags);
1552
1553 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
1554 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
1555 *filter_flags |= RXON_FILTER_PROMISC_MSK;
1556 else
1557 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
1558 }
1559 if (changed_flags & FIF_ALLMULTI) {
1560 if (*total_flags & FIF_ALLMULTI)
1561 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
1562 else
1563 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
1564 }
1565 if (changed_flags & FIF_CONTROL) {
1566 if (*total_flags & FIF_CONTROL)
1567 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
1568 else
1569 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
1570 }
1571 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1572 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1573 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
1574 else
1575 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
1576 }
1577
1578 /* We avoid iwl_commit_rxon here to commit the new filter flags
1579 * since mac80211 will call ieee80211_hw_config immediately.
1580 * (mc_list is not supported at this time). Otherwise, we need to
1581 * queue a background iwl_commit_rxon work.
1582 */
1583
1584 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
1585 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
1586}
1587EXPORT_SYMBOL(iwl_configure_filter);
1588
da154e30
RR		 1589int iwl_set_hw_params(struct iwl_priv *priv)
1590{
da154e30
RR		 1591 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1592 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1593 if (priv->cfg->mod_params->amsdu_size_8K)
2f301227 1594 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
da154e30 1595 else
2f301227 1596 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
da154e30 1597
2c2f3b33
TW		 1598 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
1599
49779293
RR		 1600 if (priv->cfg->mod_params->disable_11n)
1601 priv->cfg->sku &= ~IWL_SKU_N;
1602
da154e30
RR		 1603 /* Device-specific setup */
1604 return priv->cfg->ops->lib->set_hw_params(priv);
1605}
1606EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956 1607
630fe9b6
TW		 1608int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1609{
1610 int ret = 0;
5eadd94b
WYG		 1611 s8 prev_tx_power = priv->tx_power_user_lmt;
1612
630fe9b6 1613 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
daf518de
WF		 1614 IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
1615 tx_power,
1616 IWL_TX_POWER_TARGET_POWER_MIN);
630fe9b6
TW		 1617 return -EINVAL;
1618 }
1619
dc1b0973 1620 if (tx_power > priv->tx_power_device_lmt) {
08f2d58d
WYG		 1621 IWL_WARN(priv,
1622 "Requested user TXPOWER %d above upper limit %d.\n",
dc1b0973 1623 tx_power, priv->tx_power_device_lmt);
630fe9b6
TW		 1624 return -EINVAL;
1625 }
1626
1627 if (priv->tx_power_user_lmt != tx_power)
1628 force = true;
1629
019fb97d 1630 /* if nic is not up don't send command */
5eadd94b
WYG		 1631 if (iwl_is_ready_rf(priv)) {
1632 priv->tx_power_user_lmt = tx_power;
1633 if (force && priv->cfg->ops->lib->send_tx_power)
1634 ret = priv->cfg->ops->lib->send_tx_power(priv);
1635 else if (!priv->cfg->ops->lib->send_tx_power)
1636 ret = -EOPNOTSUPP;
1637 /*
1638 * if fail to set tx_power, restore the orig. tx power
1639 */
1640 if (ret)
1641 priv->tx_power_user_lmt = prev_tx_power;
1642 }
630fe9b6 1643
5eadd94b
WYG		 1644 /*
1645 * Even this is an async host command, the command
1646 * will always report success from uCode
1647 * So once driver can placing the command into the queue
1648 * successfully, driver can use priv->tx_power_user_lmt
1649 * to reflect the current tx power
1650 */
630fe9b6
TW		 1651 return ret;
1652}
1653EXPORT_SYMBOL(iwl_set_tx_power);
1654
ef850d7c
MA		 1655#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1656
1657/* Free dram table */
1658void iwl_free_isr_ict(struct iwl_priv *priv)
1659{
1660 if (priv->ict_tbl_vir) {
1661 pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
1662 PAGE_SIZE, priv->ict_tbl_vir,
1663 priv->ict_tbl_dma);
1664 priv->ict_tbl_vir = NULL;
1665 }
1666}
1667EXPORT_SYMBOL(iwl_free_isr_ict);
1668
1669
1670/* allocate dram shared table it is a PAGE_SIZE aligned
1671 * also reset all data related to ICT table interrupt.
1672 */
1673int iwl_alloc_isr_ict(struct iwl_priv *priv)
1674{
1675
1676 if (priv->cfg->use_isr_legacy)
1677 return 0;
1678 /* allocate shrared data table */
1679 priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
1680 ICT_COUNT) + PAGE_SIZE,
1681 &priv->ict_tbl_dma);
1682 if (!priv->ict_tbl_vir)
1683 return -ENOMEM;
1684
1685 /* align table to PAGE_SIZE boundry */
1686 priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
1687
1688 IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1689 (unsigned long long)priv->ict_tbl_dma,
1690 (unsigned long long)priv->aligned_ict_tbl_dma,
1691 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1692
1693 priv->ict_tbl = priv->ict_tbl_vir +
1694 (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
1695
1696 IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
1697 priv->ict_tbl, priv->ict_tbl_vir,
1698 (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
1699
1700 /* reset table and index to all 0 */
1701 memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1702 priv->ict_index = 0;
1703
40cefda9
MA		 1704 /* add periodic RX interrupt */
1705 priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
ef850d7c
MA		 1706 return 0;
1707}
1708EXPORT_SYMBOL(iwl_alloc_isr_ict);
1709
1710/* Device is going up inform it about using ICT interrupt table,
1711 * also we need to tell the driver to start using ICT interrupt.
1712 */
1713int iwl_reset_ict(struct iwl_priv *priv)
1714{
1715 u32 val;
1716 unsigned long flags;
1717
1718 if (!priv->ict_tbl_vir)
1719 return 0;
1720
1721 spin_lock_irqsave(&priv->lock, flags);
1722 iwl_disable_interrupts(priv);
1723
1303dcfd 1724 memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
ef850d7c
MA		 1725
1726 val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
1727
1728 val |= CSR_DRAM_INT_TBL_ENABLE;
1729 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1730
1731 IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
1732 "aligned dma address %Lx\n",
1733 val, (unsigned long long)priv->aligned_ict_tbl_dma);
1734
1735 iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
1736 priv->use_ict = true;
1737 priv->ict_index = 0;
40cefda9 1738 iwl_write32(priv, CSR_INT, priv->inta_mask);
ef850d7c
MA		 1739 iwl_enable_interrupts(priv);
1740 spin_unlock_irqrestore(&priv->lock, flags);
1741
1742 return 0;
1743}
1744EXPORT_SYMBOL(iwl_reset_ict);
1745
1746/* Device is going down disable ict interrupt usage */
1747void iwl_disable_ict(struct iwl_priv *priv)
1748{
1749 unsigned long flags;
1750
1751 spin_lock_irqsave(&priv->lock, flags);
1752 priv->use_ict = false;
1753 spin_unlock_irqrestore(&priv->lock, flags);
1754}
1755EXPORT_SYMBOL(iwl_disable_ict);
1756
1757/* interrupt handler using ict table, with this interrupt driver will
1758 * stop using INTA register to get device's interrupt, reading this register
1759 * is expensive, device will write interrupts in ICT dram table, increment
1760 * index then will fire interrupt to driver, driver will OR all ICT table
1761 * entries from current index up to table entry with 0 value. the result is
1762 * the interrupt we need to service, driver will set the entries back to 0 and
1763 * set index.
1764 */
1765irqreturn_t iwl_isr_ict(int irq, void *data)
1766{
1767 struct iwl_priv *priv = data;
1768 u32 inta, inta_mask;
1769 u32 val = 0;
1770
1771 if (!priv)
1772 return IRQ_NONE;
1773
1774 /* dram interrupt table not set yet,
1775 * use legacy interrupt.
1776 */
1777 if (!priv->use_ict)
1778 return iwl_isr(irq, data);
1779
1780 spin_lock(&priv->lock);
1781
1782 /* Disable (but don't clear!) interrupts here to avoid
1783 * back-to-back ISRs and sporadic interrupts from our NIC.
1784 * If we have something to service, the tasklet will re-enable ints.
1785 * If we *don't* have something, we'll re-enable before leaving here.
1786 */
1787 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1788 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1789
1790
1791 /* Ignore interrupt if there's nothing in NIC to service.
1792 * This may be due to IRQ shared with another device,
1793 * or due to sporadic interrupts thrown from our NIC. */
1794 if (!priv->ict_tbl[priv->ict_index]) {
1795 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1796 goto none;
1797 }
1798
1799 /* read all entries that not 0 start with ict_index */
1800 while (priv->ict_tbl[priv->ict_index]) {
1801
1303dcfd 1802 val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
ef850d7c 1803 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
1303dcfd
JB		 1804 priv->ict_index,
1805 le32_to_cpu(priv->ict_tbl[priv->ict_index]));
ef850d7c
MA		 1806 priv->ict_tbl[priv->ict_index] = 0;
1807 priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
1303dcfd 1808 ICT_COUNT);
ef850d7c
MA		 1809
1810 }
1811
1812 /* We should not get this value, just ignore it. */
1813 if (val == 0xffffffff)
1814 val = 0;
1815
1816 inta = (0xff & val) | ((0xff00 & val) << 16);
1817 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1818 inta, inta_mask, val);
1819
40cefda9 1820 inta &= priv->inta_mask;
ef850d7c
MA		 1821 priv->inta |= inta;
1822
1823 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1824 if (likely(inta))
1825 tasklet_schedule(&priv->irq_tasklet);
1826 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
1827 /* Allow interrupt if was disabled by this handler and
1828 * no tasklet was schedules, We should not enable interrupt,
1829 * tasklet will enable it.
1830 */
1831 iwl_enable_interrupts(priv);
1832 }
1833
1834 spin_unlock(&priv->lock);
1835 return IRQ_HANDLED;
1836
1837 none:
1838 /* re-enable interrupts here since we don't have anything to service.
1839 * only Re-enable if disabled by irq.
1840 */
1841 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1842 iwl_enable_interrupts(priv);
1843
1844 spin_unlock(&priv->lock);
1845 return IRQ_NONE;
1846}
1847EXPORT_SYMBOL(iwl_isr_ict);
1848
1849
1850static irqreturn_t iwl_isr(int irq, void *data)
1851{
1852 struct iwl_priv *priv = data;
1853 u32 inta, inta_mask;
d651ae32 1854#ifdef CONFIG_IWLWIFI_DEBUG
ef850d7c 1855 u32 inta_fh;
d651ae32 1856#endif
ef850d7c
MA		 1857 if (!priv)
1858 return IRQ_NONE;
1859
1860 spin_lock(&priv->lock);
1861
1862 /* Disable (but don't clear!) interrupts here to avoid
1863 * back-to-back ISRs and sporadic interrupts from our NIC.
1864 * If we have something to service, the tasklet will re-enable ints.
1865 * If we *don't* have something, we'll re-enable before leaving here. */
1866 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1867 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1868
1869 /* Discover which interrupts are active/pending */
1870 inta = iwl_read32(priv, CSR_INT);
1871
1872 /* Ignore interrupt if there's nothing in NIC to service.
1873 * This may be due to IRQ shared with another device,
1874 * or due to sporadic interrupts thrown from our NIC. */
1875 if (!inta) {
1876 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
1877 goto none;
1878 }
1879
1880 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1881 /* Hardware disappeared. It might have already raised
1882 * an interrupt */
1883 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1884 goto unplugged;
1885 }
1886
1887#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1888 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1889 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1890 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
1891 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1892 }
1893#endif
1894
1895 priv->inta |= inta;
1896 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1897 if (likely(inta))
1898 tasklet_schedule(&priv->irq_tasklet);
1899 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1900 iwl_enable_interrupts(priv);
1901
1902 unplugged:
1903 spin_unlock(&priv->lock);
1904 return IRQ_HANDLED;
1905
1906 none:
1907 /* re-enable interrupts here since we don't have anything to service. */
1908 /* only Re-enable if diabled by irq and no schedules tasklet. */
1909 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
1910 iwl_enable_interrupts(priv);
1911
1912 spin_unlock(&priv->lock);
1913 return IRQ_NONE;
1914}
1915
1916irqreturn_t iwl_isr_legacy(int irq, void *data)
f17d08a6
AK		 1917{
1918 struct iwl_priv *priv = data;
1919 u32 inta, inta_mask;
1920 u32 inta_fh;
1921 if (!priv)
1922 return IRQ_NONE;
1923
1924 spin_lock(&priv->lock);
1925
1926 /* Disable (but don't clear!) interrupts here to avoid
1927 * back-to-back ISRs and sporadic interrupts from our NIC.
1928 * If we have something to service, the tasklet will re-enable ints.
1929 * If we *don't* have something, we'll re-enable before leaving here. */
1930 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1931 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1932
1933 /* Discover which interrupts are active/pending */
1934 inta = iwl_read32(priv, CSR_INT);
1935 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1936
1937 /* Ignore interrupt if there's nothing in NIC to service.
1938 * This may be due to IRQ shared with another device,
1939 * or due to sporadic interrupts thrown from our NIC. */
1940 if (!inta && !inta_fh) {
1941 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
1942 goto none;
1943 }
1944
1945 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1946 /* Hardware disappeared. It might have already raised
1947 * an interrupt */
1948 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1949 goto unplugged;
1950 }
1951
1952 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1953 inta, inta_mask, inta_fh);
1954
1955 inta &= ~CSR_INT_BIT_SCD;
1956
1957 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1958 if (likely(inta || inta_fh))
1959 tasklet_schedule(&priv->irq_tasklet);
1960
1961 unplugged:
1962 spin_unlock(&priv->lock);
1963 return IRQ_HANDLED;
1964
1965 none:
1966 /* re-enable interrupts here since we don't have anything to service. */
1967 /* only Re-enable if diabled by irq */
1968 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1969 iwl_enable_interrupts(priv);
1970 spin_unlock(&priv->lock);
1971 return IRQ_NONE;
1972}
ef850d7c 1973EXPORT_SYMBOL(iwl_isr_legacy);
f17d08a6 1974
17f841cd
SO		 1975int iwl_send_bt_config(struct iwl_priv *priv)
1976{
1977 struct iwl_bt_cmd bt_cmd = {
456d0f76
WYG		 1978 .flags = BT_COEX_MODE_4W,
1979 .lead_time = BT_LEAD_TIME_DEF,
1980 .max_kill = BT_MAX_KILL_DEF,
17f841cd
SO		 1981 .kill_ack_mask = 0,
1982 .kill_cts_mask = 0,
1983 };
1984
1985 return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1986 sizeof(struct iwl_bt_cmd), &bt_cmd);
1987}
1988EXPORT_SYMBOL(iwl_send_bt_config);
1989
ef8d5529 1990int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear)
49ea8596 1991{
ef8d5529
WYG		 1992 struct iwl_statistics_cmd statistics_cmd = {
1993 .configuration_flags =
1994 clear ? IWL_STATS_CONF_CLEAR_STATS : 0,
49ea8596 1995 };
ef8d5529
WYG		 1996
1997 if (flags & CMD_ASYNC)
1998 return iwl_send_cmd_pdu_async(priv, REPLY_STATISTICS_CMD,
1999 sizeof(struct iwl_statistics_cmd),
2000 &statistics_cmd, NULL);
2001 else
2002 return iwl_send_cmd_pdu(priv, REPLY_STATISTICS_CMD,
2003 sizeof(struct iwl_statistics_cmd),
2004 &statistics_cmd);
49ea8596
EG		 2005}
2006EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 2007
b0692f2f
EG		 2008/**
2009 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
2010 * using sample data 100 bytes apart. If these sample points are good,
2011 * it's a pretty good bet that everything between them is good, too.
2012 */
2013static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
2014{
2015 u32 val;
2016 int ret = 0;
2017 u32 errcnt = 0;
2018 u32 i;
2019
e1623446 2020 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2021
b0692f2f
EG		 2022 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2023 /* read data comes through single port, auto-incr addr */
2024 /* NOTE: Use the debugless read so we don't flood kernel log
2025 * if IWL_DL_IO is set */
2026 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2027 i + IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2028 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2029 if (val != le32_to_cpu(*image)) {
2030 ret = -EIO;
2031 errcnt++;
2032 if (errcnt >= 3)
2033 break;
2034 }
2035 }
2036
b0692f2f
EG		 2037 return ret;
2038}
2039
2040/**
2041 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
2042 * looking at all data.
2043 */
2044static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
2045 u32 len)
2046{
2047 u32 val;
2048 u32 save_len = len;
2049 int ret = 0;
2050 u32 errcnt;
2051
e1623446 2052 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f 2053
250bdd21
SO		 2054 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
2055 IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 2056
2057 errcnt = 0;
2058 for (; len > 0; len -= sizeof(u32), image++) {
2059 /* read data comes through single port, auto-incr addr */
2060 /* NOTE: Use the debugless read so we don't flood kernel log
2061 * if IWL_DL_IO is set */
2062 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2063 if (val != le32_to_cpu(*image)) {
15b1687c 2064 IWL_ERR(priv, "uCode INST section is invalid at "
b0692f2f
EG		 2065 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2066 save_len - len, val, le32_to_cpu(*image));
2067 ret = -EIO;
2068 errcnt++;
2069 if (errcnt >= 20)
2070 break;
2071 }
2072 }
2073
b0692f2f 2074 if (!errcnt)
e1623446
TW		 2075 IWL_DEBUG_INFO(priv,
2076 "ucode image in INSTRUCTION memory is good\n");
b0692f2f
EG		 2077
2078 return ret;
2079}
2080
2081/**
2082 * iwl_verify_ucode - determine which instruction image is in SRAM,
2083 * and verify its contents
2084 */
2085int iwl_verify_ucode(struct iwl_priv *priv)
2086{
2087 __le32 *image;
2088 u32 len;
2089 int ret;
2090
2091 /* Try bootstrap */
2092 image = (__le32 *)priv->ucode_boot.v_addr;
2093 len = priv->ucode_boot.len;
2094 ret = iwlcore_verify_inst_sparse(priv, image, len);
2095 if (!ret) {
e1623446 2096 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b0692f2f
EG		 2097 return 0;
2098 }
2099
2100 /* Try initialize */
2101 image = (__le32 *)priv->ucode_init.v_addr;
2102 len = priv->ucode_init.len;
2103 ret = iwlcore_verify_inst_sparse(priv, image, len);
2104 if (!ret) {
e1623446 2105 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b0692f2f
EG		 2106 return 0;
2107 }
2108
2109 /* Try runtime/protocol */
2110 image = (__le32 *)priv->ucode_code.v_addr;
2111 len = priv->ucode_code.len;
2112 ret = iwlcore_verify_inst_sparse(priv, image, len);
2113 if (!ret) {
e1623446 2114 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b0692f2f
EG		 2115 return 0;
2116 }
2117
15b1687c 2118 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b0692f2f
EG		 2119
2120 /* Since nothing seems to match, show first several data entries in
2121 * instruction SRAM, so maybe visual inspection will give a clue.
2122 * Selection of bootstrap image (vs. other images) is arbitrary. */
2123 image = (__le32 *)priv->ucode_boot.v_addr;
2124 len = priv->ucode_boot.len;
2125 ret = iwl_verify_inst_full(priv, image, len);
2126
2127 return ret;
2128}
2129EXPORT_SYMBOL(iwl_verify_ucode);
2130
56e12615 2131
47f4a587
EG		 2132void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2133{
2134 struct iwl_ct_kill_config cmd;
672639de 2135 struct iwl_ct_kill_throttling_config adv_cmd;
47f4a587
EG		 2136 unsigned long flags;
2137 int ret = 0;
2138
2139 spin_lock_irqsave(&priv->lock, flags);
2140 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2141 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2142 spin_unlock_irqrestore(&priv->lock, flags);
3ad3b92a 2143 priv->thermal_throttle.ct_kill_toggle = false;
47f4a587 2144
480e8407 2145 if (priv->cfg->support_ct_kill_exit) {
672639de
WYG		 2146 adv_cmd.critical_temperature_enter =
2147 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2148 adv_cmd.critical_temperature_exit =
2149 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2150
2151 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2152 sizeof(adv_cmd), &adv_cmd);
d91b1ba3
WYG		 2153 if (ret)
2154 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2155 else
2156 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2157 "succeeded, "
2158 "critical temperature enter is %d,"
2159 "exit is %d\n",
2160 priv->hw_params.ct_kill_threshold,
2161 priv->hw_params.ct_kill_exit_threshold);
480e8407 2162 } else {
672639de
WYG		 2163 cmd.critical_temperature_R =
2164 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 2165
672639de
WYG		 2166 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2167 sizeof(cmd), &cmd);
d91b1ba3
WYG		 2168 if (ret)
2169 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2170 else
2171 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2172 "succeeded, "
2173 "critical temperature is %d\n",
2174 priv->hw_params.ct_kill_threshold);
672639de 2175 }
47f4a587
EG		 2176}
2177EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f 2178
0ad91a35 2179
14a08a7f
EG		 2180/*
2181 * CARD_STATE_CMD
2182 *
2183 * Use: Sets the device's internal card state to enable, disable, or halt
2184 *
2185 * When in the 'enable' state the card operates as normal.
2186 * When in the 'disable' state, the card enters into a low power mode.
2187 * When in the 'halt' state, the card is shut down and must be fully
2188 * restarted to come back on.
2189 */
c496294e 2190int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
14a08a7f
EG		 2191{
2192 struct iwl_host_cmd cmd = {
2193 .id = REPLY_CARD_STATE_CMD,
2194 .len = sizeof(u32),
2195 .data = &flags,
c2acea8e 2196 .flags = meta_flag,
14a08a7f
EG		 2197 };
2198
2199 return iwl_send_cmd(priv, &cmd);
2200}
2201
030f05ed
AK		 2202void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
2203 struct iwl_rx_mem_buffer *rxb)
2204{
2205#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 2206 struct iwl_rx_packet *pkt = rxb_addr(rxb);
030f05ed
AK		 2207 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
2208 IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
2209 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
2210#endif
2211}
2212EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
2213
2214void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
2215 struct iwl_rx_mem_buffer *rxb)
2216{
2f301227 2217 struct iwl_rx_packet *pkt = rxb_addr(rxb);
396887a2 2218 u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
030f05ed 2219 IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
396887a2
DH		 2220 "notification for %s:\n", len,
2221 get_cmd_string(pkt->hdr.cmd));
2222 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len);
030f05ed
AK		 2223}
2224EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
261b9c33
AK		 2225
2226void iwl_rx_reply_error(struct iwl_priv *priv,
2227 struct iwl_rx_mem_buffer *rxb)
2228{
2f301227 2229 struct iwl_rx_packet *pkt = rxb_addr(rxb);
261b9c33
AK		 2230
2231 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
2232 "seq 0x%04X ser 0x%08X\n",
2233 le32_to_cpu(pkt->u.err_resp.error_type),
2234 get_cmd_string(pkt->u.err_resp.cmd_id),
2235 pkt->u.err_resp.cmd_id,
2236 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
2237 le32_to_cpu(pkt->u.err_resp.error_info));
2238}
2239EXPORT_SYMBOL(iwl_rx_reply_error);
2240
a83b9141
WYG		 2241void iwl_clear_isr_stats(struct iwl_priv *priv)
2242{
2243 memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
2244}
a83b9141 2245
488829f1
AK		 2246int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
2247 const struct ieee80211_tx_queue_params *params)
2248{
2249 struct iwl_priv *priv = hw->priv;
2250 unsigned long flags;
2251 int q;
2252
2253 IWL_DEBUG_MAC80211(priv, "enter\n");
2254
2255 if (!iwl_is_ready_rf(priv)) {
2256 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2257 return -EIO;
2258 }
2259
2260 if (queue >= AC_NUM) {
2261 IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
2262 return 0;
2263 }
2264
2265 q = AC_NUM - 1 - queue;
2266
2267 spin_lock_irqsave(&priv->lock, flags);
2268
2269 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
2270 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
2271 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
2272 priv->qos_data.def_qos_parm.ac[q].edca_txop =
2273 cpu_to_le16((params->txop * 32));
2274
2275 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
2276 priv->qos_data.qos_active = 1;
2277
2278 if (priv->iw_mode == NL80211_IFTYPE_AP)
2279 iwl_activate_qos(priv, 1);
2280 else if (priv->assoc_id && iwl_is_associated(priv))
2281 iwl_activate_qos(priv, 0);
2282
2283 spin_unlock_irqrestore(&priv->lock, flags);
2284
2285 IWL_DEBUG_MAC80211(priv, "leave\n");
2286 return 0;
2287}
2288EXPORT_SYMBOL(iwl_mac_conf_tx);
5bbe233b
AK		 2289
2290static void iwl_ht_conf(struct iwl_priv *priv,
02bb1bea 2291 struct ieee80211_bss_conf *bss_conf)
5bbe233b 2292{
fad95bf5 2293 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
5bbe233b
AK		 2294 struct ieee80211_sta *sta;
2295
2296 IWL_DEBUG_MAC80211(priv, "enter: \n");
2297
fad95bf5 2298 if (!ht_conf->is_ht)
5bbe233b
AK		 2299 return;
2300
fad95bf5 2301 ht_conf->ht_protection =
9ed6bcce 2302 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
fad95bf5 2303 ht_conf->non_GF_STA_present =
9ed6bcce 2304 !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
5bbe233b 2305
02bb1bea
JB		 2306 ht_conf->single_chain_sufficient = false;
2307
2308 switch (priv->iw_mode) {
2309 case NL80211_IFTYPE_STATION:
2310 rcu_read_lock();
5ed176e1 2311 sta = ieee80211_find_sta(priv->vif, priv->bssid);
02bb1bea
JB		 2312 if (sta) {
2313 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
2314 int maxstreams;
2315
2316 maxstreams = (ht_cap->mcs.tx_params &
2317 IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
2318 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2319 maxstreams += 1;
2320
2321 if ((ht_cap->mcs.rx_mask[1] == 0) &&
2322 (ht_cap->mcs.rx_mask[2] == 0))
2323 ht_conf->single_chain_sufficient = true;
2324 if (maxstreams <= 1)
2325 ht_conf->single_chain_sufficient = true;
2326 } else {
2327 /*
2328 * If at all, this can only happen through a race
2329 * when the AP disconnects us while we're still
2330 * setting up the connection, in that case mac80211
2331 * will soon tell us about that.
2332 */
2333 ht_conf->single_chain_sufficient = true;
2334 }
2335 rcu_read_unlock();
2336 break;
2337 case NL80211_IFTYPE_ADHOC:
2338 ht_conf->single_chain_sufficient = true;
2339 break;
2340 default:
2341 break;
2342 }
5bbe233b
AK		 2343
2344 IWL_DEBUG_MAC80211(priv, "leave\n");
2345}
2346
2347#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
2348void iwl_bss_info_changed(struct ieee80211_hw *hw,
2d0ddec5
JB		 2349 struct ieee80211_vif *vif,
2350 struct ieee80211_bss_conf *bss_conf,
2351 u32 changes)
5bbe233b
AK		 2352{
2353 struct iwl_priv *priv = hw->priv;
3a650292 2354 int ret;
5bbe233b
AK		 2355
2356 IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
2357
2d0ddec5
JB		 2358 if (!iwl_is_alive(priv))
2359 return;
2360
2361 mutex_lock(&priv->mutex);
2362
2363 if (changes & BSS_CHANGED_BEACON &&
2364 priv->iw_mode == NL80211_IFTYPE_AP) {
2365 dev_kfree_skb(priv->ibss_beacon);
2366 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
2367 }
2368
d7129e19
JB		 2369 if (changes & BSS_CHANGED_BEACON_INT) {
2370 priv->beacon_int = bss_conf->beacon_int;
2371 /* TODO: in AP mode, do something to make this take effect */
2372 }
2373
2374 if (changes & BSS_CHANGED_BSSID) {
2375 IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
2376
2377 /*
2378 * If there is currently a HW scan going on in the
2379 * background then we need to cancel it else the RXON
2380 * below/in post_associate will fail.
2381 */
2d0ddec5 2382 if (iwl_scan_cancel_timeout(priv, 100)) {
d7129e19 2383 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
2d0ddec5
JB		 2384 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
2385 mutex_unlock(&priv->mutex);
2386 return;
2387 }
2d0ddec5 2388
d7129e19
JB		 2389 /* mac80211 only sets assoc when in STATION mode */
2390 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
2391 bss_conf->assoc) {
2392 memcpy(priv->staging_rxon.bssid_addr,
2393 bss_conf->bssid, ETH_ALEN);
2d0ddec5 2394
d7129e19
JB		 2395 /* currently needed in a few places */
2396 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2397 } else {
2398 priv->staging_rxon.filter_flags &=
2399 ~RXON_FILTER_ASSOC_MSK;
2d0ddec5 2400 }
d7129e19 2401
2d0ddec5
JB		 2402 }
2403
d7129e19
JB		 2404 /*
2405 * This needs to be after setting the BSSID in case
2406 * mac80211 decides to do both changes at once because
2407 * it will invoke post_associate.
2408 */
2d0ddec5
JB		 2409 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2410 changes & BSS_CHANGED_BEACON) {
2411 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2412
2413 if (beacon)
2414 iwl_mac_beacon_update(hw, beacon);
2415 }
2416
5bbe233b
AK		 2417 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
2418 IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
2419 bss_conf->use_short_preamble);
2420 if (bss_conf->use_short_preamble)
2421 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2422 else
2423 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2424 }
2425
2426 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
2427 IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
2428 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
2429 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
2430 else
2431 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
2432 }
2433
d7129e19
JB		 2434 if (changes & BSS_CHANGED_BASIC_RATES) {
2435 /* XXX use this information
2436 *
2437 * To do that, remove code from iwl_set_rate() and put something
2438 * like this here:
2439 *
2440 if (A-band)
2441 priv->staging_rxon.ofdm_basic_rates =
2442 bss_conf->basic_rates;
2443 else
2444 priv->staging_rxon.ofdm_basic_rates =
2445 bss_conf->basic_rates >> 4;
2446 priv->staging_rxon.cck_basic_rates =
2447 bss_conf->basic_rates & 0xF;
2448 */
2449 }
2450
5bbe233b
AK		 2451 if (changes & BSS_CHANGED_HT) {
2452 iwl_ht_conf(priv, bss_conf);
45823531
AK		 2453
2454 if (priv->cfg->ops->hcmd->set_rxon_chain)
2455 priv->cfg->ops->hcmd->set_rxon_chain(priv);
5bbe233b
AK		 2456 }
2457
2458 if (changes & BSS_CHANGED_ASSOC) {
2459 IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
5bbe233b
AK		 2460 if (bss_conf->assoc) {
2461 priv->assoc_id = bss_conf->aid;
2462 priv->beacon_int = bss_conf->beacon_int;
5bbe233b
AK		 2463 priv->timestamp = bss_conf->timestamp;
2464 priv->assoc_capability = bss_conf->assoc_capability;
2465
e932a609
JB		 2466 iwl_led_associate(priv);
2467
d7129e19
JB		 2468 /*
2469 * We have just associated, don't start scan too early
2470 * leave time for EAPOL exchange to complete.
2471 *
2472 * XXX: do this in mac80211
5bbe233b
AK		 2473 */
2474 priv->next_scan_jiffies = jiffies +
2475 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
d7129e19
JB		 2476 if (!iwl_is_rfkill(priv))
2477 priv->cfg->ops->lib->post_associate(priv);
e932a609 2478 } else {
5bbe233b 2479 priv->assoc_id = 0;
e932a609 2480 iwl_led_disassociate(priv);
644c77f0
JS		 2481
2482 /*
2483 * inform the ucode that there is no longer an
2484 * association and that no more packets should be
2485 * send
2486 */
2487 priv->staging_rxon.filter_flags &=
2488 ~RXON_FILTER_ASSOC_MSK;
2489 priv->staging_rxon.assoc_id = 0;
2490 iwlcore_commit_rxon(priv);
e932a609 2491 }
d7129e19
JB		 2492 }
2493
2494 if (changes && iwl_is_associated(priv) && priv->assoc_id) {
2495 IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
2496 changes);
2497 ret = iwl_send_rxon_assoc(priv);
2498 if (!ret) {
2499 /* Sync active_rxon with latest change. */
2500 memcpy((void *)&priv->active_rxon,
2501 &priv->staging_rxon,
2502 sizeof(struct iwl_rxon_cmd));
5bbe233b 2503 }
5bbe233b 2504 }
d7129e19 2505
f513dfff
DH		 2506 if ((changes & BSS_CHANGED_BEACON_ENABLED) &&
2507 vif->bss_conf.enable_beacon) {
2508 memcpy(priv->staging_rxon.bssid_addr,
2509 bss_conf->bssid, ETH_ALEN);
2510 memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
2511 iwlcore_config_ap(priv);
2512 }
2513
d7129e19
JB		 2514 mutex_unlock(&priv->mutex);
2515
2d0ddec5 2516 IWL_DEBUG_MAC80211(priv, "leave\n");
5bbe233b
AK		 2517}
2518EXPORT_SYMBOL(iwl_bss_info_changed);
2519
9944b938
AK		 2520int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
2521{
2522 struct iwl_priv *priv = hw->priv;
2523 unsigned long flags;
2524 __le64 timestamp;
2525
2526 IWL_DEBUG_MAC80211(priv, "enter\n");
2527
2528 if (!iwl_is_ready_rf(priv)) {
2529 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2530 return -EIO;
2531 }
2532
2533 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2534 IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
2535 return -EIO;
2536 }
2537
2538 spin_lock_irqsave(&priv->lock, flags);
2539
2540 if (priv->ibss_beacon)
2541 dev_kfree_skb(priv->ibss_beacon);
2542
2543 priv->ibss_beacon = skb;
2544
2545 priv->assoc_id = 0;
2546 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
2547 priv->timestamp = le64_to_cpu(timestamp);
2548
2549 IWL_DEBUG_MAC80211(priv, "leave\n");
2550 spin_unlock_irqrestore(&priv->lock, flags);
2551
2552 iwl_reset_qos(priv);
2553
2554 priv->cfg->ops->lib->post_associate(priv);
2555
2556
2557 return 0;
2558}
2559EXPORT_SYMBOL(iwl_mac_beacon_update);
2560
727882d6
AK		 2561int iwl_set_mode(struct iwl_priv *priv, int mode)
2562{
2563 if (mode == NL80211_IFTYPE_ADHOC) {
2564 const struct iwl_channel_info *ch_info;
2565
2566 ch_info = iwl_get_channel_info(priv,
2567 priv->band,
2568 le16_to_cpu(priv->staging_rxon.channel));
2569
2570 if (!ch_info || !is_channel_ibss(ch_info)) {
2571 IWL_ERR(priv, "channel %d not IBSS channel\n",
2572 le16_to_cpu(priv->staging_rxon.channel));
2573 return -EINVAL;
2574 }
2575 }
2576
2577 iwl_connection_init_rx_config(priv, mode);
2578
2579 if (priv->cfg->ops->hcmd->set_rxon_chain)
2580 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2581
2582 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2583
c587de0b 2584 iwl_clear_stations_table(priv);
727882d6
AK		 2585
2586 /* dont commit rxon if rf-kill is on*/
2587 if (!iwl_is_ready_rf(priv))
2588 return -EAGAIN;
2589
727882d6
AK		 2590 iwlcore_commit_rxon(priv);
2591
2592 return 0;
2593}
2594EXPORT_SYMBOL(iwl_set_mode);
2595
cbb6ab94
AK		 2596int iwl_mac_add_interface(struct ieee80211_hw *hw,
2597 struct ieee80211_if_init_conf *conf)
2598{
2599 struct iwl_priv *priv = hw->priv;
2600 unsigned long flags;
2601
2602 IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
2603
2604 if (priv->vif) {
2605 IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
2606 return -EOPNOTSUPP;
2607 }
2608
2609 spin_lock_irqsave(&priv->lock, flags);
2610 priv->vif = conf->vif;
2611 priv->iw_mode = conf->type;
2612
2613 spin_unlock_irqrestore(&priv->lock, flags);
2614
2615 mutex_lock(&priv->mutex);
2616
2617 if (conf->mac_addr) {
2618 IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
2619 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
2620 }
2621
2622 if (iwl_set_mode(priv, conf->type) == -EAGAIN)
2623 /* we are not ready, will run again when ready */
2624 set_bit(STATUS_MODE_PENDING, &priv->status);
2625
2626 mutex_unlock(&priv->mutex);
2627
2628 IWL_DEBUG_MAC80211(priv, "leave\n");
2629 return 0;
2630}
2631EXPORT_SYMBOL(iwl_mac_add_interface);
2632
d8052319
AK		 2633void iwl_mac_remove_interface(struct ieee80211_hw *hw,
2634 struct ieee80211_if_init_conf *conf)
2635{
2636 struct iwl_priv *priv = hw->priv;
2637
2638 IWL_DEBUG_MAC80211(priv, "enter\n");
2639
2640 mutex_lock(&priv->mutex);
2641
2642 if (iwl_is_ready_rf(priv)) {
2643 iwl_scan_cancel_timeout(priv, 100);
2644 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2645 iwlcore_commit_rxon(priv);
2646 }
2647 if (priv->vif == conf->vif) {
2648 priv->vif = NULL;
2649 memset(priv->bssid, 0, ETH_ALEN);
2650 }
2651 mutex_unlock(&priv->mutex);
2652
2653 IWL_DEBUG_MAC80211(priv, "leave\n");
2654
2655}
2656EXPORT_SYMBOL(iwl_mac_remove_interface);
2657
4808368d
AK		 2658/**
2659 * iwl_mac_config - mac80211 config callback
2660 *
2661 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
2662 * be set inappropriately and the driver currently sets the hardware up to
2663 * use it whenever needed.
2664 */
2665int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
2666{
2667 struct iwl_priv *priv = hw->priv;
2668 const struct iwl_channel_info *ch_info;
2669 struct ieee80211_conf *conf = &hw->conf;
fad95bf5 2670 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
4808368d
AK		 2671 unsigned long flags = 0;
2672 int ret = 0;
2673 u16 ch;
2674 int scan_active = 0;
2675
2676 mutex_lock(&priv->mutex);
2677
4808368d
AK		 2678 IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
2679 conf->channel->hw_value, changed);
2680
2681 if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
2682 test_bit(STATUS_SCANNING, &priv->status))) {
2683 scan_active = 1;
2684 IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
2685 }
2686
2687
2688 /* during scanning mac80211 will delay channel setting until
2689 * scan finish with changed = 0
2690 */
2691 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
2692 if (scan_active)
2693 goto set_ch_out;
2694
2695 ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
2696 ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
2697 if (!is_channel_valid(ch_info)) {
2698 IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
2699 ret = -EINVAL;
2700 goto set_ch_out;
2701 }
2702
2703 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
2704 !is_channel_ibss(ch_info)) {
2705 IWL_ERR(priv, "channel %d in band %d not "
2706 "IBSS channel\n",
2707 conf->channel->hw_value, conf->channel->band);
2708 ret = -EINVAL;
2709 goto set_ch_out;
2710 }
2711
4808368d
AK		 2712 spin_lock_irqsave(&priv->lock, flags);
2713
28bd723b
DH		 2714 /* Configure HT40 channels */
2715 ht_conf->is_ht = conf_is_ht(conf);
2716 if (ht_conf->is_ht) {
2717 if (conf_is_ht40_minus(conf)) {
2718 ht_conf->extension_chan_offset =
2719 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
c812ee24 2720 ht_conf->is_40mhz = true;
28bd723b
DH		 2721 } else if (conf_is_ht40_plus(conf)) {
2722 ht_conf->extension_chan_offset =
2723 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
c812ee24 2724 ht_conf->is_40mhz = true;
28bd723b
DH		 2725 } else {
2726 ht_conf->extension_chan_offset =
2727 IEEE80211_HT_PARAM_CHA_SEC_NONE;
c812ee24 2728 ht_conf->is_40mhz = false;
28bd723b
DH		 2729 }
2730 } else
c812ee24 2731 ht_conf->is_40mhz = false;
28bd723b
DH		 2732 /* Default to no protection. Protection mode will later be set
2733 * from BSS config in iwl_ht_conf */
2734 ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
4808368d
AK		 2735
2736 /* if we are switching from ht to 2.4 clear flags
2737 * from any ht related info since 2.4 does not
2738 * support ht */
2739 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
2740 priv->staging_rxon.flags = 0;
2741
2742 iwl_set_rxon_channel(priv, conf->channel);
2743
2744 iwl_set_flags_for_band(priv, conf->channel->band);
2745 spin_unlock_irqrestore(&priv->lock, flags);
0924e519
WYG		 2746 if (iwl_is_associated(priv) &&
2747 (le16_to_cpu(priv->active_rxon.channel) != ch) &&
2748 priv->cfg->ops->lib->set_channel_switch) {
2749 iwl_set_rate(priv);
2750 /*
2751 * at this point, staging_rxon has the
2752 * configuration for channel switch
2753 */
2754 ret = priv->cfg->ops->lib->set_channel_switch(priv,
2755 ch);
2756 if (!ret) {
2757 iwl_print_rx_config_cmd(priv);
2758 goto out;
2759 }
2760 priv->switch_rxon.switch_in_progress = false;
2761 }
4808368d
AK		 2762 set_ch_out:
2763 /* The list of supported rates and rate mask can be different
2764 * for each band; since the band may have changed, reset
2765 * the rate mask to what mac80211 lists */
2766 iwl_set_rate(priv);
2767 }
2768
78f5fb7f
JB		 2769 if (changed & (IEEE80211_CONF_CHANGE_PS |
2770 IEEE80211_CONF_CHANGE_IDLE)) {
e312c24c 2771 ret = iwl_power_update_mode(priv, false);
4808368d 2772 if (ret)
e312c24c 2773 IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
4808368d
AK		 2774 }
2775
2776 if (changed & IEEE80211_CONF_CHANGE_POWER) {
2777 IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
2778 priv->tx_power_user_lmt, conf->power_level);
2779
2780 iwl_set_tx_power(priv, conf->power_level, false);
2781 }
2782
2783 /* call to ensure that 4965 rx_chain is set properly in monitor mode */
2784 if (priv->cfg->ops->hcmd->set_rxon_chain)
2785 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2786
0cf4c01e
MA		 2787 if (!iwl_is_ready(priv)) {
2788 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2789 goto out;
2790 }
2791
4808368d
AK		 2792 if (scan_active)
2793 goto out;
2794
2795 if (memcmp(&priv->active_rxon,
2796 &priv->staging_rxon, sizeof(priv->staging_rxon)))
2797 iwlcore_commit_rxon(priv);
2798 else
2799 IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
2800
2801
2802out:
2803 IWL_DEBUG_MAC80211(priv, "leave\n");
2804 mutex_unlock(&priv->mutex);
2805 return ret;
2806}
2807EXPORT_SYMBOL(iwl_mac_config);
2808
aa89f31e
AK		 2809int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
2810 struct ieee80211_tx_queue_stats *stats)
2811{
2812 struct iwl_priv *priv = hw->priv;
2813 int i, avail;
2814 struct iwl_tx_queue *txq;
2815 struct iwl_queue *q;
2816 unsigned long flags;
2817
2818 IWL_DEBUG_MAC80211(priv, "enter\n");
2819
2820 if (!iwl_is_ready_rf(priv)) {
2821 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
2822 return -EIO;
2823 }
2824
2825 spin_lock_irqsave(&priv->lock, flags);
2826
2827 for (i = 0; i < AC_NUM; i++) {
2828 txq = &priv->txq[i];
2829 q = &txq->q;
2830 avail = iwl_queue_space(q);
2831
2832 stats[i].len = q->n_window - avail;
2833 stats[i].limit = q->n_window - q->high_mark;
2834 stats[i].count = q->n_window;
2835
2836 }
2837 spin_unlock_irqrestore(&priv->lock, flags);
2838
2839 IWL_DEBUG_MAC80211(priv, "leave\n");
2840
2841 return 0;
2842}
2843EXPORT_SYMBOL(iwl_mac_get_tx_stats);
2844
bd564261
AK		 2845void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
2846{
2847 struct iwl_priv *priv = hw->priv;
2848 unsigned long flags;
2849
2850 mutex_lock(&priv->mutex);
2851 IWL_DEBUG_MAC80211(priv, "enter\n");
2852
2853 spin_lock_irqsave(&priv->lock, flags);
fad95bf5 2854 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
bd564261
AK		 2855 spin_unlock_irqrestore(&priv->lock, flags);
2856
2857 iwl_reset_qos(priv);
2858
2859 spin_lock_irqsave(&priv->lock, flags);
2860 priv->assoc_id = 0;
2861 priv->assoc_capability = 0;
2862 priv->assoc_station_added = 0;
2863
2864 /* new association get rid of ibss beacon skb */
2865 if (priv->ibss_beacon)
2866 dev_kfree_skb(priv->ibss_beacon);
2867
2868 priv->ibss_beacon = NULL;
2869
57c4d7b4 2870 priv->beacon_int = priv->vif->bss_conf.beacon_int;
bd564261
AK		 2871 priv->timestamp = 0;
2872 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
2873 priv->beacon_int = 0;
2874
2875 spin_unlock_irqrestore(&priv->lock, flags);
2876
2877 if (!iwl_is_ready_rf(priv)) {
2878 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
2879 mutex_unlock(&priv->mutex);
2880 return;
2881 }
2882
2883 /* we are restarting association process
2884 * clear RXON_FILTER_ASSOC_MSK bit
2885 */
2886 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2887 iwl_scan_cancel_timeout(priv, 100);
2888 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2889 iwlcore_commit_rxon(priv);
2890 }
2891
bd564261 2892 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
bd564261
AK		 2893 IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
2894 mutex_unlock(&priv->mutex);
2895 return;
2896 }
2897
2898 iwl_set_rate(priv);
2899
2900 mutex_unlock(&priv->mutex);
2901
2902 IWL_DEBUG_MAC80211(priv, "leave\n");
2903}
2904EXPORT_SYMBOL(iwl_mac_reset_tsf);
2905
88804e2b
WYG		 2906int iwl_alloc_txq_mem(struct iwl_priv *priv)
2907{
2908 if (!priv->txq)
2909 priv->txq = kzalloc(
2910 sizeof(struct iwl_tx_queue) * priv->cfg->num_of_queues,
2911 GFP_KERNEL);
2912 if (!priv->txq) {
2913 IWL_ERR(priv, "Not enough memory for txq \n");
2914 return -ENOMEM;
2915 }
2916 return 0;
2917}
2918EXPORT_SYMBOL(iwl_alloc_txq_mem);
2919
2920void iwl_free_txq_mem(struct iwl_priv *priv)
2921{
2922 kfree(priv->txq);
2923 priv->txq = NULL;
2924}
2925EXPORT_SYMBOL(iwl_free_txq_mem);
2926
1933ac4d
WYG		 2927int iwl_send_wimax_coex(struct iwl_priv *priv)
2928{
2929 struct iwl_wimax_coex_cmd uninitialized_var(coex_cmd);
2930
2931 if (priv->cfg->support_wimax_coexist) {
2932 /* UnMask wake up src at associated sleep */
2933 coex_cmd.flags |= COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
2934
2935 /* UnMask wake up src at unassociated sleep */
2936 coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
2937 memcpy(coex_cmd.sta_prio, cu_priorities,
2938 sizeof(struct iwl_wimax_coex_event_entry) *
2939 COEX_NUM_OF_EVENTS);
2940
2941 /* enabling the coexistence feature */
2942 coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
2943
2944 /* enabling the priorities tables */
2945 coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
2946 } else {
2947 /* coexistence is disabled */
2948 memset(&coex_cmd, 0, sizeof(coex_cmd));
2949 }
2950 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
2951 sizeof(coex_cmd), &coex_cmd);
2952}
2953EXPORT_SYMBOL(iwl_send_wimax_coex);
2954
20594eb0
WYG		 2955#ifdef CONFIG_IWLWIFI_DEBUGFS
2956
2957#define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
2958
2959void iwl_reset_traffic_log(struct iwl_priv *priv)
2960{
2961 priv->tx_traffic_idx = 0;
2962 priv->rx_traffic_idx = 0;
2963 if (priv->tx_traffic)
2964 memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2965 if (priv->rx_traffic)
2966 memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
2967}
2968
2969int iwl_alloc_traffic_mem(struct iwl_priv *priv)
2970{
2971 u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
2972
2973 if (iwl_debug_level & IWL_DL_TX) {
2974 if (!priv->tx_traffic) {
2975 priv->tx_traffic =
2976 kzalloc(traffic_size, GFP_KERNEL);
2977 if (!priv->tx_traffic)
2978 return -ENOMEM;
2979 }
2980 }
2981 if (iwl_debug_level & IWL_DL_RX) {
2982 if (!priv->rx_traffic) {
2983 priv->rx_traffic =
2984 kzalloc(traffic_size, GFP_KERNEL);
2985 if (!priv->rx_traffic)
2986 return -ENOMEM;
2987 }
2988 }
2989 iwl_reset_traffic_log(priv);
2990 return 0;
2991}
2992EXPORT_SYMBOL(iwl_alloc_traffic_mem);
2993
2994void iwl_free_traffic_mem(struct iwl_priv *priv)
2995{
2996 kfree(priv->tx_traffic);
2997 priv->tx_traffic = NULL;
2998
2999 kfree(priv->rx_traffic);
3000 priv->rx_traffic = NULL;
3001}
3002EXPORT_SYMBOL(iwl_free_traffic_mem);
3003
3004void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
3005 u16 length, struct ieee80211_hdr *header)
3006{
3007 __le16 fc;
3008 u16 len;
3009
3010 if (likely(!(iwl_debug_level & IWL_DL_TX)))
3011 return;
3012
3013 if (!priv->tx_traffic)
3014 return;
3015
3016 fc = header->frame_control;
3017 if (ieee80211_is_data(fc)) {
3018 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
3019 ? IWL_TRAFFIC_ENTRY_SIZE : length;
3020 memcpy((priv->tx_traffic +
3021 (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3022 header, len);
3023 priv->tx_traffic_idx =
3024 (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3025 }
3026}
3027EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
3028
3029void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
3030 u16 length, struct ieee80211_hdr *header)
3031{
3032 __le16 fc;
3033 u16 len;
3034
3035 if (likely(!(iwl_debug_level & IWL_DL_RX)))
3036 return;
3037
3038 if (!priv->rx_traffic)
3039 return;
3040
3041 fc = header->frame_control;
3042 if (ieee80211_is_data(fc)) {
3043 len = (length > IWL_TRAFFIC_ENTRY_SIZE)
3044 ? IWL_TRAFFIC_ENTRY_SIZE : length;
3045 memcpy((priv->rx_traffic +
3046 (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
3047 header, len);
3048 priv->rx_traffic_idx =
3049 (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
3050 }
3051}
3052EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
22fdf3c9
WYG		 3053
3054const char *get_mgmt_string(int cmd)
3055{
3056 switch (cmd) {
3057 IWL_CMD(MANAGEMENT_ASSOC_REQ);
3058 IWL_CMD(MANAGEMENT_ASSOC_RESP);
3059 IWL_CMD(MANAGEMENT_REASSOC_REQ);
3060 IWL_CMD(MANAGEMENT_REASSOC_RESP);
3061 IWL_CMD(MANAGEMENT_PROBE_REQ);
3062 IWL_CMD(MANAGEMENT_PROBE_RESP);
3063 IWL_CMD(MANAGEMENT_BEACON);
3064 IWL_CMD(MANAGEMENT_ATIM);
3065 IWL_CMD(MANAGEMENT_DISASSOC);
3066 IWL_CMD(MANAGEMENT_AUTH);
3067 IWL_CMD(MANAGEMENT_DEAUTH);
3068 IWL_CMD(MANAGEMENT_ACTION);
3069 default:
3070 return "UNKNOWN";
3071
3072 }
3073}
3074
3075const char *get_ctrl_string(int cmd)
3076{
3077 switch (cmd) {
3078 IWL_CMD(CONTROL_BACK_REQ);
3079 IWL_CMD(CONTROL_BACK);
3080 IWL_CMD(CONTROL_PSPOLL);
3081 IWL_CMD(CONTROL_RTS);
3082 IWL_CMD(CONTROL_CTS);
3083 IWL_CMD(CONTROL_ACK);
3084 IWL_CMD(CONTROL_CFEND);
3085 IWL_CMD(CONTROL_CFENDACK);
3086 default:
3087 return "UNKNOWN";
3088
3089 }
3090}
3091
7163b8a4 3092void iwl_clear_traffic_stats(struct iwl_priv *priv)
22fdf3c9
WYG		 3093{
3094 memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
22fdf3c9 3095 memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
7163b8a4 3096 priv->led_tpt = 0;
22fdf3c9
WYG		 3097}
3098
3099/*
3100 * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
3101 * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
3102 * Use debugFs to display the rx/rx_statistics
3103 * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
3104 * information will be recorded, but DATA pkt still will be recorded
3105 * for the reason of iwl_led.c need to control the led blinking based on
3106 * number of tx and rx data.
3107 *
3108 */
3109void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
3110{
3111 struct traffic_stats *stats;
3112
3113 if (is_tx)
3114 stats = &priv->tx_stats;
3115 else
3116 stats = &priv->rx_stats;
3117
3118 if (ieee80211_is_mgmt(fc)) {
3119 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3120 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
3121 stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
3122 break;
3123 case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
3124 stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
3125 break;
3126 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
3127 stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
3128 break;
3129 case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
3130 stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
3131 break;
3132 case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
3133 stats->mgmt[MANAGEMENT_PROBE_REQ]++;
3134 break;
3135 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
3136 stats->mgmt[MANAGEMENT_PROBE_RESP]++;
3137 break;
3138 case cpu_to_le16(IEEE80211_STYPE_BEACON):
3139 stats->mgmt[MANAGEMENT_BEACON]++;
3140 break;
3141 case cpu_to_le16(IEEE80211_STYPE_ATIM):
3142 stats->mgmt[MANAGEMENT_ATIM]++;
3143 break;
3144 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
3145 stats->mgmt[MANAGEMENT_DISASSOC]++;
3146 break;
3147 case cpu_to_le16(IEEE80211_STYPE_AUTH):
3148 stats->mgmt[MANAGEMENT_AUTH]++;
3149 break;
3150 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
3151 stats->mgmt[MANAGEMENT_DEAUTH]++;
3152 break;
3153 case cpu_to_le16(IEEE80211_STYPE_ACTION):
3154 stats->mgmt[MANAGEMENT_ACTION]++;
3155 break;
3156 }
3157 } else if (ieee80211_is_ctl(fc)) {
3158 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
3159 case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
3160 stats->ctrl[CONTROL_BACK_REQ]++;
3161 break;
3162 case cpu_to_le16(IEEE80211_STYPE_BACK):
3163 stats->ctrl[CONTROL_BACK]++;
3164 break;
3165 case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
3166 stats->ctrl[CONTROL_PSPOLL]++;
3167 break;
3168 case cpu_to_le16(IEEE80211_STYPE_RTS):
3169 stats->ctrl[CONTROL_RTS]++;
3170 break;
3171 case cpu_to_le16(IEEE80211_STYPE_CTS):
3172 stats->ctrl[CONTROL_CTS]++;
3173 break;
3174 case cpu_to_le16(IEEE80211_STYPE_ACK):
3175 stats->ctrl[CONTROL_ACK]++;
3176 break;
3177 case cpu_to_le16(IEEE80211_STYPE_CFEND):
3178 stats->ctrl[CONTROL_CFEND]++;
3179 break;
3180 case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
3181 stats->ctrl[CONTROL_CFENDACK]++;
3182 break;
3183 }
3184 } else {
3185 /* data */
3186 stats->data_cnt++;
3187 stats->data_bytes += len;
3188 }
d5f4cf71 3189 iwl_leds_background(priv);
22fdf3c9
WYG		 3190}
3191EXPORT_SYMBOL(iwl_update_stats);
20594eb0
WYG		 3192#endif
3193
6da3a13e
WYG		 3194#ifdef CONFIG_PM
3195
3196int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
3197{
3198 struct iwl_priv *priv = pci_get_drvdata(pdev);
3199
3200 /*
3201 * This function is called when system goes into suspend state
3202 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
3203 * first but since iwl_mac_stop() has no knowledge of who the caller is,
3204 * it will not call apm_ops.stop() to stop the DMA operation.
3205 * Calling apm_ops.stop here to make sure we stop the DMA.
3206 */
3207 priv->cfg->ops->lib->apm_ops.stop(priv);
3208
3209 pci_save_state(pdev);
3210 pci_disable_device(pdev);
3211 pci_set_power_state(pdev, PCI_D3hot);
3212
3213 return 0;
3214}
3215EXPORT_SYMBOL(iwl_pci_suspend);
3216
3217int iwl_pci_resume(struct pci_dev *pdev)
3218{
3219 struct iwl_priv *priv = pci_get_drvdata(pdev);
3220 int ret;
3221
3222 pci_set_power_state(pdev, PCI_D0);
3223 ret = pci_enable_device(pdev);
3224 if (ret)
3225 return ret;
3226 pci_restore_state(pdev);
3227 iwl_enable_interrupts(priv);
3228
3229 return 0;
3230}
3231EXPORT_SYMBOL(iwl_pci_resume);
3232
3233#endif /* CONFIG_PM */
Clone of davem's net-next-2.6 tree