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iwl3945: use iwl rx handlers
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-core.c
CommitLineData
df48c323 1/******************************************************************************
df48c323
TW		 2 *
3 * GPL LICENSE SUMMARY
4 *
01f8162a 5 * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
df48c323
TW		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
df48c323
TW		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
8ccde88a 31#include <linux/etherdevice.h>
1d0a082d 32#include <net/mac80211.h>
df48c323 33
6bc913bd 34#include "iwl-eeprom.h"
3e0d4cb1 35#include "iwl-dev.h" /* FIXME: remove */
19335774 36#include "iwl-debug.h"
df48c323 37#include "iwl-core.h"
b661c819 38#include "iwl-io.h"
ad97edd2 39#include "iwl-rfkill.h"
5da4b55f 40#include "iwl-power.h"
83dde8c9 41#include "iwl-sta.h"
df48c323 42
1d0a082d 43
df48c323
TW		 44MODULE_DESCRIPTION("iwl core");
45MODULE_VERSION(IWLWIFI_VERSION);
a7b75207 46MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
712b6cf5 47MODULE_LICENSE("GPL");
df48c323 48
c7de35cd
RR		 49#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
61
62/*
63 * Parameter order:
64 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
65 *
66 * If there isn't a valid next or previous rate then INV is used which
67 * maps to IWL_RATE_INVALID
68 *
69 */
1826dcc0 70const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
c7de35cd
RR		 71 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
72 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
73 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
74 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
75 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
76 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
77 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
78 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
79 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
80 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
81 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
82 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
83 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
84 /* FIXME:RS: ^^ should be INV (legacy) */
85};
1826dcc0 86EXPORT_SYMBOL(iwl_rates);
c7de35cd 87
e7d326ac
TW		 88/**
89 * translate ucode response to mac80211 tx status control values
90 */
91void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e6a9854b 92 struct ieee80211_tx_info *info)
e7d326ac
TW		 93{
94 int rate_index;
e6a9854b 95 struct ieee80211_tx_rate *r = &info->control.rates[0];
e7d326ac 96
e6a9854b 97 info->antenna_sel_tx =
e7d326ac
TW		 98 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
99 if (rate_n_flags & RATE_MCS_HT_MSK)
e6a9854b 100 r->flags |= IEEE80211_TX_RC_MCS;
e7d326ac 101 if (rate_n_flags & RATE_MCS_GF_MSK)
e6a9854b 102 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
e7d326ac 103 if (rate_n_flags & RATE_MCS_FAT_MSK)
e6a9854b 104 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
e7d326ac 105 if (rate_n_flags & RATE_MCS_DUP_MSK)
e6a9854b 106 r->flags |= IEEE80211_TX_RC_DUP_DATA;
e7d326ac 107 if (rate_n_flags & RATE_MCS_SGI_MSK)
e6a9854b 108 r->flags |= IEEE80211_TX_RC_SHORT_GI;
e7d326ac 109 rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
e6a9854b 110 if (info->band == IEEE80211_BAND_5GHZ)
e7d326ac 111 rate_index -= IWL_FIRST_OFDM_RATE;
e6a9854b 112 r->idx = rate_index;
e7d326ac
TW		 113}
114EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
115
116int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
117{
118 int idx = 0;
119
120 /* HT rate format */
121 if (rate_n_flags & RATE_MCS_HT_MSK) {
122 idx = (rate_n_flags & 0xff);
123
60d32215
DH		 124 if (idx >= IWL_RATE_MIMO3_6M_PLCP)
125 idx = idx - IWL_RATE_MIMO3_6M_PLCP;
126 else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
e7d326ac
TW		 127 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
128
129 idx += IWL_FIRST_OFDM_RATE;
130 /* skip 9M not supported in ht*/
131 if (idx >= IWL_RATE_9M_INDEX)
132 idx += 1;
133 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
134 return idx;
135
136 /* legacy rate format, search for match in table */
137 } else {
138 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
139 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
140 return idx;
141 }
142
143 return -1;
144}
145EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
146
76eff18b
TW		 147u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
148{
149 int i;
150 u8 ind = ant;
151 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
152 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
153 if (priv->hw_params.valid_tx_ant & BIT(ind))
154 return ind;
155 }
156 return ant;
157}
57bd1bea
TW		 158
159const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
160EXPORT_SYMBOL(iwl_bcast_addr);
161
162
1d0a082d
AK		 163/* This function both allocates and initializes hw and priv. */
164struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
165 struct ieee80211_ops *hw_ops)
166{
167 struct iwl_priv *priv;
168
169 /* mac80211 allocates memory for this device instance, including
170 * space for this driver's private structure */
171 struct ieee80211_hw *hw =
172 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
173 if (hw == NULL) {
a3139c59
SO		 174 printk(KERN_ERR "%s: Can not allocate network device\n",
175 cfg->name);
1d0a082d
AK		 176 goto out;
177 }
178
179 priv = hw->priv;
180 priv->hw = hw;
181
182out:
183 return hw;
184}
185EXPORT_SYMBOL(iwl_alloc_all);
186
b661c819
TW		 187void iwl_hw_detect(struct iwl_priv *priv)
188{
189 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
190 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
191 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
192}
193EXPORT_SYMBOL(iwl_hw_detect);
194
1053d35f
RR		 195int iwl_hw_nic_init(struct iwl_priv *priv)
196{
197 unsigned long flags;
198 struct iwl_rx_queue *rxq = &priv->rxq;
199 int ret;
200
201 /* nic_init */
1053d35f 202 spin_lock_irqsave(&priv->lock, flags);
1b73af82 203 priv->cfg->ops->lib->apm_ops.init(priv);
1053d35f
RR		 204 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
205 spin_unlock_irqrestore(&priv->lock, flags);
206
207 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
208
209 priv->cfg->ops->lib->apm_ops.config(priv);
210
211 /* Allocate the RX queue, or reset if it is already allocated */
212 if (!rxq->bd) {
213 ret = iwl_rx_queue_alloc(priv);
214 if (ret) {
15b1687c 215 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1053d35f
RR		 216 return -ENOMEM;
217 }
218 } else
219 iwl_rx_queue_reset(priv, rxq);
220
221 iwl_rx_replenish(priv);
222
223 iwl_rx_init(priv, rxq);
224
225 spin_lock_irqsave(&priv->lock, flags);
226
227 rxq->need_update = 1;
228 iwl_rx_queue_update_write_ptr(priv, rxq);
229
230 spin_unlock_irqrestore(&priv->lock, flags);
231
232 /* Allocate and init all Tx and Command queues */
233 ret = iwl_txq_ctx_reset(priv);
234 if (ret)
235 return ret;
236
237 set_bit(STATUS_INIT, &priv->status);
238
239 return 0;
240}
241EXPORT_SYMBOL(iwl_hw_nic_init);
242
c7de35cd 243void iwl_reset_qos(struct iwl_priv *priv)
bf85ea4f
AK		 244{
245 u16 cw_min = 15;
246 u16 cw_max = 1023;
247 u8 aifs = 2;
30dab79e 248 bool is_legacy = false;
bf85ea4f
AK		 249 unsigned long flags;
250 int i;
251
252 spin_lock_irqsave(&priv->lock, flags);
30dab79e
WT		 253 /* QoS always active in AP and ADHOC mode
254 * In STA mode wait for association
255 */
256 if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
257 priv->iw_mode == NL80211_IFTYPE_AP)
258 priv->qos_data.qos_active = 1;
259 else
260 priv->qos_data.qos_active = 0;
bf85ea4f 261
30dab79e
WT		 262 /* check for legacy mode */
263 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
264 (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
265 (priv->iw_mode == NL80211_IFTYPE_STATION &&
266 (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
bf85ea4f
AK		 267 cw_min = 31;
268 is_legacy = 1;
269 }
270
271 if (priv->qos_data.qos_active)
272 aifs = 3;
273
274 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
275 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
276 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
277 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
278 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
279
280 if (priv->qos_data.qos_active) {
281 i = 1;
282 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
283 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
284 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
285 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
286 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
287
288 i = 2;
289 priv->qos_data.def_qos_parm.ac[i].cw_min =
290 cpu_to_le16((cw_min + 1) / 2 - 1);
291 priv->qos_data.def_qos_parm.ac[i].cw_max =
292 cpu_to_le16(cw_max);
293 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
294 if (is_legacy)
295 priv->qos_data.def_qos_parm.ac[i].edca_txop =
296 cpu_to_le16(6016);
297 else
298 priv->qos_data.def_qos_parm.ac[i].edca_txop =
299 cpu_to_le16(3008);
300 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
301
302 i = 3;
303 priv->qos_data.def_qos_parm.ac[i].cw_min =
304 cpu_to_le16((cw_min + 1) / 4 - 1);
305 priv->qos_data.def_qos_parm.ac[i].cw_max =
306 cpu_to_le16((cw_max + 1) / 2 - 1);
307 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
308 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
309 if (is_legacy)
310 priv->qos_data.def_qos_parm.ac[i].edca_txop =
311 cpu_to_le16(3264);
312 else
313 priv->qos_data.def_qos_parm.ac[i].edca_txop =
314 cpu_to_le16(1504);
315 } else {
316 for (i = 1; i < 4; i++) {
317 priv->qos_data.def_qos_parm.ac[i].cw_min =
318 cpu_to_le16(cw_min);
319 priv->qos_data.def_qos_parm.ac[i].cw_max =
320 cpu_to_le16(cw_max);
321 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
322 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
323 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
324 }
325 }
e1623446 326 IWL_DEBUG_QOS(priv, "set QoS to default \n");
bf85ea4f
AK		 327
328 spin_unlock_irqrestore(&priv->lock, flags);
329}
c7de35cd
RR		 330EXPORT_SYMBOL(iwl_reset_qos);
331
d9fe60de
JB		 332#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
333#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
c7de35cd 334static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
d9fe60de 335 struct ieee80211_sta_ht_cap *ht_info,
c7de35cd
RR		 336 enum ieee80211_band band)
337{
39130df3
RR		 338 u16 max_bit_rate = 0;
339 u8 rx_chains_num = priv->hw_params.rx_chains_num;
340 u8 tx_chains_num = priv->hw_params.tx_chains_num;
341
c7de35cd 342 ht_info->cap = 0;
d9fe60de 343 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
c7de35cd 344
d9fe60de 345 ht_info->ht_supported = true;
c7de35cd 346
d9fe60de
JB		 347 ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
348 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
349 ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
00c5ae2f 350 (WLAN_HT_CAP_SM_PS_DISABLED << 2));
39130df3
RR		 351
352 max_bit_rate = MAX_BIT_RATE_20_MHZ;
c7de35cd 353 if (priv->hw_params.fat_channel & BIT(band)) {
d9fe60de
JB		 354 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
355 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
356 ht_info->mcs.rx_mask[4] = 0x01;
39130df3 357 max_bit_rate = MAX_BIT_RATE_40_MHZ;
c7de35cd 358 }
c7de35cd
RR		 359
360 if (priv->cfg->mod_params->amsdu_size_8K)
d9fe60de 361 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
c7de35cd
RR		 362
363 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
364 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
365
d9fe60de 366 ht_info->mcs.rx_mask[0] = 0xFF;
39130df3 367 if (rx_chains_num >= 2)
d9fe60de 368 ht_info->mcs.rx_mask[1] = 0xFF;
39130df3 369 if (rx_chains_num >= 3)
d9fe60de 370 ht_info->mcs.rx_mask[2] = 0xFF;
39130df3
RR		 371
372 /* Highest supported Rx data rate */
373 max_bit_rate *= rx_chains_num;
d9fe60de
JB		 374 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
375 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
39130df3
RR		 376
377 /* Tx MCS capabilities */
d9fe60de 378 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
39130df3 379 if (tx_chains_num != rx_chains_num) {
d9fe60de
JB		 380 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
381 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
382 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
39130df3 383 }
c7de35cd 384}
c7de35cd
RR		 385
386static void iwlcore_init_hw_rates(struct iwl_priv *priv,
387 struct ieee80211_rate *rates)
388{
389 int i;
390
391 for (i = 0; i < IWL_RATE_COUNT; i++) {
1826dcc0 392 rates[i].bitrate = iwl_rates[i].ieee * 5;
c7de35cd
RR		 393 rates[i].hw_value = i; /* Rate scaling will work on indexes */
394 rates[i].hw_value_short = i;
395 rates[i].flags = 0;
396 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
397 /*
398 * If CCK != 1M then set short preamble rate flag.
399 */
400 rates[i].flags |=
1826dcc0 401 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
c7de35cd
RR		 402 0 : IEEE80211_RATE_SHORT_PREAMBLE;
403 }
404 }
405}
406
8ccde88a 407
c7de35cd
RR		 408/**
409 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
410 */
534166de 411int iwlcore_init_geos(struct iwl_priv *priv)
c7de35cd
RR		 412{
413 struct iwl_channel_info *ch;
414 struct ieee80211_supported_band *sband;
415 struct ieee80211_channel *channels;
416 struct ieee80211_channel *geo_ch;
417 struct ieee80211_rate *rates;
418 int i = 0;
419
420 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
421 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
e1623446 422 IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
c7de35cd
RR		 423 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
424 return 0;
425 }
426
427 channels = kzalloc(sizeof(struct ieee80211_channel) *
428 priv->channel_count, GFP_KERNEL);
429 if (!channels)
430 return -ENOMEM;
431
432 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
433 GFP_KERNEL);
434 if (!rates) {
435 kfree(channels);
436 return -ENOMEM;
437 }
438
439 /* 5.2GHz channels start after the 2.4GHz channels */
440 sband = &priv->bands[IEEE80211_BAND_5GHZ];
441 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
442 /* just OFDM */
443 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
444 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
445
49779293 446 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 447 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 448 IEEE80211_BAND_5GHZ);
c7de35cd
RR		 449
450 sband = &priv->bands[IEEE80211_BAND_2GHZ];
451 sband->channels = channels;
452 /* OFDM & CCK */
453 sband->bitrates = rates;
454 sband->n_bitrates = IWL_RATE_COUNT;
455
49779293 456 if (priv->cfg->sku & IWL_SKU_N)
d9fe60de 457 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
49779293 458 IEEE80211_BAND_2GHZ);
c7de35cd
RR		 459
460 priv->ieee_channels = channels;
461 priv->ieee_rates = rates;
462
c7de35cd
RR		 463 for (i = 0; i < priv->channel_count; i++) {
464 ch = &priv->channel_info[i];
465
466 /* FIXME: might be removed if scan is OK */
467 if (!is_channel_valid(ch))
468 continue;
469
470 if (is_channel_a_band(ch))
471 sband = &priv->bands[IEEE80211_BAND_5GHZ];
472 else
473 sband = &priv->bands[IEEE80211_BAND_2GHZ];
474
475 geo_ch = &sband->channels[sband->n_channels++];
476
477 geo_ch->center_freq =
478 ieee80211_channel_to_frequency(ch->channel);
479 geo_ch->max_power = ch->max_power_avg;
480 geo_ch->max_antenna_gain = 0xff;
481 geo_ch->hw_value = ch->channel;
482
483 if (is_channel_valid(ch)) {
484 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
485 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
486
487 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
488 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
489
490 if (ch->flags & EEPROM_CHANNEL_RADAR)
491 geo_ch->flags |= IEEE80211_CHAN_RADAR;
492
963f5517 493 geo_ch->flags |= ch->fat_extension_channel;
4d38c2e8 494
630fe9b6
TW		 495 if (ch->max_power_avg > priv->tx_power_channel_lmt)
496 priv->tx_power_channel_lmt = ch->max_power_avg;
c7de35cd
RR		 497 } else {
498 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
499 }
500
501 /* Save flags for reg domain usage */
502 geo_ch->orig_flags = geo_ch->flags;
503
e1623446 504 IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
c7de35cd
RR		 505 ch->channel, geo_ch->center_freq,
506 is_channel_a_band(ch) ? "5.2" : "2.4",
507 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
508 "restricted" : "valid",
509 geo_ch->flags);
510 }
511
512 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
513 priv->cfg->sku & IWL_SKU_A) {
978785a3
TW		 514 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
515 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
a3139c59
SO		 516 priv->pci_dev->device,
517 priv->pci_dev->subsystem_device);
c7de35cd
RR		 518 priv->cfg->sku &= ~IWL_SKU_A;
519 }
520
978785a3 521 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
a3139c59
SO		 522 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
523 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
c7de35cd
RR		 524
525 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
526
527 return 0;
528}
534166de 529EXPORT_SYMBOL(iwlcore_init_geos);
c7de35cd
RR		 530
531/*
532 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
533 */
534166de 534void iwlcore_free_geos(struct iwl_priv *priv)
c7de35cd
RR		 535{
536 kfree(priv->ieee_channels);
537 kfree(priv->ieee_rates);
538 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
539}
534166de 540EXPORT_SYMBOL(iwlcore_free_geos);
c7de35cd 541
28a6b07a 542static bool is_single_rx_stream(struct iwl_priv *priv)
c7de35cd
RR		 543{
544 return !priv->current_ht_config.is_ht ||
d9fe60de
JB		 545 ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
546 (priv->current_ht_config.mcs.rx_mask[2] == 0));
c7de35cd 547}
963f5517 548
47c5196e
TW		 549static u8 iwl_is_channel_extension(struct iwl_priv *priv,
550 enum ieee80211_band band,
551 u16 channel, u8 extension_chan_offset)
552{
553 const struct iwl_channel_info *ch_info;
554
555 ch_info = iwl_get_channel_info(priv, band, channel);
556 if (!is_channel_valid(ch_info))
557 return 0;
558
d9fe60de 559 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
963f5517
EG		 560 return !(ch_info->fat_extension_channel &
561 IEEE80211_CHAN_NO_FAT_ABOVE);
d9fe60de 562 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
963f5517
EG		 563 return !(ch_info->fat_extension_channel &
564 IEEE80211_CHAN_NO_FAT_BELOW);
47c5196e
TW		 565
566 return 0;
567}
568
569u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
d9fe60de 570 struct ieee80211_sta_ht_cap *sta_ht_inf)
47c5196e
TW		 571{
572 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
573
574 if ((!iwl_ht_conf->is_ht) ||
575 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
d9fe60de 576 (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE))
47c5196e
TW		 577 return 0;
578
579 if (sta_ht_inf) {
580 if ((!sta_ht_inf->ht_supported) ||
d9fe60de 581 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)))
47c5196e
TW		 582 return 0;
583 }
584
585 return iwl_is_channel_extension(priv, priv->band,
ae5eb026
JB		 586 le16_to_cpu(priv->staging_rxon.channel),
587 iwl_ht_conf->extension_chan_offset);
47c5196e
TW		 588}
589EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
590
8ccde88a
SO		 591void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
592{
593 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
594
595 if (hw_decrypt)
596 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
597 else
598 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
599
600}
601EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
602
603/**
604 * iwl_check_rxon_cmd - validate RXON structure is valid
605 *
606 * NOTE: This is really only useful during development and can eventually
607 * be #ifdef'd out once the driver is stable and folks aren't actively
608 * making changes
609 */
610int iwl_check_rxon_cmd(struct iwl_priv *priv)
611{
612 int error = 0;
613 int counter = 1;
614 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
615
616 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
617 error |= le32_to_cpu(rxon->flags &
618 (RXON_FLG_TGJ_NARROW_BAND_MSK |
619 RXON_FLG_RADAR_DETECT_MSK));
620 if (error)
621 IWL_WARN(priv, "check 24G fields %d | %d\n",
622 counter++, error);
623 } else {
624 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
625 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
626 if (error)
627 IWL_WARN(priv, "check 52 fields %d | %d\n",
628 counter++, error);
629 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
630 if (error)
631 IWL_WARN(priv, "check 52 CCK %d | %d\n",
632 counter++, error);
633 }
634 error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
635 if (error)
636 IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
637
638 /* make sure basic rates 6Mbps and 1Mbps are supported */
639 error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
640 ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
641 if (error)
642 IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
643
644 error |= (le16_to_cpu(rxon->assoc_id) > 2007);
645 if (error)
646 IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
647
648 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
649 == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
650 if (error)
651 IWL_WARN(priv, "check CCK and short slot %d | %d\n",
652 counter++, error);
653
654 error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
655 == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
656 if (error)
657 IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
658 counter++, error);
659
660 error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
661 RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
662 if (error)
663 IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
664 counter++, error);
665
666 if (error)
667 IWL_WARN(priv, "Tuning to channel %d\n",
668 le16_to_cpu(rxon->channel));
669
670 if (error) {
671 IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
672 return -1;
673 }
674 return 0;
675}
676EXPORT_SYMBOL(iwl_check_rxon_cmd);
677
678/**
679 * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
680 * @priv: staging_rxon is compared to active_rxon
681 *
682 * If the RXON structure is changing enough to require a new tune,
683 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
684 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
685 */
686int iwl_full_rxon_required(struct iwl_priv *priv)
687{
688
689 /* These items are only settable from the full RXON command */
690 if (!(iwl_is_associated(priv)) ||
691 compare_ether_addr(priv->staging_rxon.bssid_addr,
692 priv->active_rxon.bssid_addr) ||
693 compare_ether_addr(priv->staging_rxon.node_addr,
694 priv->active_rxon.node_addr) ||
695 compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
696 priv->active_rxon.wlap_bssid_addr) ||
697 (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
698 (priv->staging_rxon.channel != priv->active_rxon.channel) ||
699 (priv->staging_rxon.air_propagation !=
700 priv->active_rxon.air_propagation) ||
701 (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
702 priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
703 (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
704 priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
705 (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
706 return 1;
707
708 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
709 * be updated with the RXON_ASSOC command -- however only some
710 * flag transitions are allowed using RXON_ASSOC */
711
712 /* Check if we are not switching bands */
713 if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
714 (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
715 return 1;
716
717 /* Check if we are switching association toggle */
718 if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
719 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
720 return 1;
721
722 return 0;
723}
724EXPORT_SYMBOL(iwl_full_rxon_required);
725
726u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
727{
728 int i;
729 int rate_mask;
730
731 /* Set rate mask*/
732 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
733 rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
734 else
735 rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
736
737 /* Find lowest valid rate */
738 for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
739 i = iwl_rates[i].next_ieee) {
740 if (rate_mask & (1 << i))
741 return iwl_rates[i].plcp;
742 }
743
744 /* No valid rate was found. Assign the lowest one */
745 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
746 return IWL_RATE_1M_PLCP;
747 else
748 return IWL_RATE_6M_PLCP;
749}
750EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
751
47c5196e
TW		 752void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
753{
c1adf9fb 754 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
47c5196e
TW		 755 u32 val;
756
42eb7c64
EG		 757 if (!ht_info->is_ht) {
758 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
759 RXON_FLG_CHANNEL_MODE_PURE_40_MSK |
760 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
761 RXON_FLG_FAT_PROT_MSK |
762 RXON_FLG_HT_PROT_MSK);
47c5196e 763 return;
42eb7c64 764 }
47c5196e
TW		 765
766 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
767 if (iwl_is_fat_tx_allowed(priv, NULL))
768 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
769 else
770 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
771 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
772
47c5196e
TW		 773 /* Note: control channel is opposite of extension channel */
774 switch (ht_info->extension_chan_offset) {
d9fe60de 775 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
47c5196e
TW		 776 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
777 break;
d9fe60de 778 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
47c5196e
TW		 779 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
780 break;
d9fe60de 781 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
47c5196e
TW		 782 default:
783 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
784 break;
785 }
786
787 val = ht_info->ht_protection;
788
789 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
790
791 iwl_set_rxon_chain(priv);
792
e1623446 793 IWL_DEBUG_ASSOC(priv, "supported HT rate 0x%X 0x%X 0x%X "
47c5196e 794 "rxon flags 0x%X operation mode :0x%X "
ae5eb026 795 "extension channel offset 0x%x\n",
d9fe60de
JB		 796 ht_info->mcs.rx_mask[0],
797 ht_info->mcs.rx_mask[1],
798 ht_info->mcs.rx_mask[2],
47c5196e 799 le32_to_cpu(rxon->flags), ht_info->ht_protection,
ae5eb026 800 ht_info->extension_chan_offset);
47c5196e
TW		 801 return;
802}
803EXPORT_SYMBOL(iwl_set_rxon_ht);
804
9e5e6c32
TW		 805#define IWL_NUM_RX_CHAINS_MULTIPLE 3
806#define IWL_NUM_RX_CHAINS_SINGLE 2
807#define IWL_NUM_IDLE_CHAINS_DUAL 2
808#define IWL_NUM_IDLE_CHAINS_SINGLE 1
809
810/* Determine how many receiver/antenna chains to use.
c7de35cd
RR		 811 * More provides better reception via diversity. Fewer saves power.
812 * MIMO (dual stream) requires at least 2, but works better with 3.
813 * This does not determine *which* chains to use, just how many.
814 */
28a6b07a 815static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
c7de35cd 816{
28a6b07a
TW		 817 bool is_single = is_single_rx_stream(priv);
818 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd
RR		 819
820 /* # of Rx chains to use when expecting MIMO. */
12837be1
RR		 821 if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
822 WLAN_HT_CAP_SM_PS_STATIC)))
9e5e6c32 823 return IWL_NUM_RX_CHAINS_SINGLE;
c7de35cd 824 else
9e5e6c32 825 return IWL_NUM_RX_CHAINS_MULTIPLE;
28a6b07a 826}
c7de35cd 827
28a6b07a
TW		 828static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
829{
830 int idle_cnt;
831 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
c7de35cd 832 /* # Rx chains when idling and maybe trying to save power */
12837be1 833 switch (priv->current_ht_config.sm_ps) {
00c5ae2f
TW		 834 case WLAN_HT_CAP_SM_PS_STATIC:
835 case WLAN_HT_CAP_SM_PS_DYNAMIC:
9e5e6c32
TW		 836 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
837 IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 838 break;
00c5ae2f 839 case WLAN_HT_CAP_SM_PS_DISABLED:
9e5e6c32 840 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
c7de35cd 841 break;
00c5ae2f 842 case WLAN_HT_CAP_SM_PS_INVALID:
c7de35cd 843 default:
15b1687c 844 IWL_ERR(priv, "invalid mimo ps mode %d\n",
12837be1 845 priv->current_ht_config.sm_ps);
28a6b07a
TW		 846 WARN_ON(1);
847 idle_cnt = -1;
c7de35cd
RR		 848 break;
849 }
28a6b07a 850 return idle_cnt;
c7de35cd
RR		 851}
852
04816448
GE		 853/* up to 4 chains */
854static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
855{
856 u8 res;
857 res = (chain_bitmap & BIT(0)) >> 0;
858 res += (chain_bitmap & BIT(1)) >> 1;
859 res += (chain_bitmap & BIT(2)) >> 2;
860 res += (chain_bitmap & BIT(4)) >> 4;
861 return res;
862}
863
4c4df78f
CR		 864/**
865 * iwl_is_monitor_mode - Determine if interface in monitor mode
866 *
867 * priv->iw_mode is set in add_interface, but add_interface is
868 * never called for monitor mode. The only way mac80211 informs us about
869 * monitor mode is through configuring filters (call to configure_filter).
870 */
871static bool iwl_is_monitor_mode(struct iwl_priv *priv)
872{
873 return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
874}
875
c7de35cd
RR		 876/**
877 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
878 *
879 * Selects how many and which Rx receivers/antennas/chains to use.
880 * This should not be used for scan command ... it puts data in wrong place.
881 */
882void iwl_set_rxon_chain(struct iwl_priv *priv)
883{
28a6b07a
TW		 884 bool is_single = is_single_rx_stream(priv);
885 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
04816448
GE		 886 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
887 u32 active_chains;
28a6b07a 888 u16 rx_chain;
c7de35cd
RR		 889
890 /* Tell uCode which antennas are actually connected.
891 * Before first association, we assume all antennas are connected.
892 * Just after first association, iwl_chain_noise_calibration()
893 * checks which antennas actually *are* connected. */
04816448
GE		 894 if (priv->chain_noise_data.active_chains)
895 active_chains = priv->chain_noise_data.active_chains;
896 else
897 active_chains = priv->hw_params.valid_rx_ant;
898
899 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
c7de35cd
RR		 900
901 /* How many receivers should we use? */
28a6b07a
TW		 902 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
903 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
904
28a6b07a 905
04816448
GE		 906 /* correct rx chain count according hw settings
907 * and chain noise calibration
908 */
909 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
910 if (valid_rx_cnt < active_rx_cnt)
911 active_rx_cnt = valid_rx_cnt;
912
913 if (valid_rx_cnt < idle_rx_cnt)
914 idle_rx_cnt = valid_rx_cnt;
28a6b07a
TW		 915
916 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
917 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
918
7b841727
RF		 919 /* copied from 'iwl_bg_request_scan()' */
920 /* Force use of chains B and C (0x6) for Rx for 4965
921 * Avoid A (0x1) because of its off-channel reception on A-band.
922 * MIMO is not used here, but value is required */
923 if (iwl_is_monitor_mode(priv) &&
924 !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
925 ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
926 rx_chain = 0x07 << RXON_RX_CHAIN_VALID_POS;
927 rx_chain |= 0x06 << RXON_RX_CHAIN_FORCE_SEL_POS;
928 rx_chain |= 0x07 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
929 rx_chain |= 0x01 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
930 }
931
28a6b07a
TW		 932 priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
933
9e5e6c32 934 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
c7de35cd
RR		 935 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
936 else
937 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
938
e1623446 939 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
28a6b07a
TW		 940 priv->staging_rxon.rx_chain,
941 active_rx_cnt, idle_rx_cnt);
942
943 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
944 active_rx_cnt < idle_rx_cnt);
c7de35cd
RR		 945}
946EXPORT_SYMBOL(iwl_set_rxon_chain);
bf85ea4f
AK		 947
948/**
17e72782 949 * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
bf85ea4f
AK		 950 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
951 * @channel: Any channel valid for the requested phymode
952
953 * In addition to setting the staging RXON, priv->phymode is also set.
954 *
955 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
956 * in the staging RXON flag structure based on the phymode
957 */
17e72782 958int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
bf85ea4f 959{
17e72782
TW		 960 enum ieee80211_band band = ch->band;
961 u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
962
8622e705 963 if (!iwl_get_channel_info(priv, band, channel)) {
e1623446 964 IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
bf85ea4f
AK		 965 channel, band);
966 return -EINVAL;
967 }
968
969 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
970 (priv->band == band))
971 return 0;
972
973 priv->staging_rxon.channel = cpu_to_le16(channel);
974 if (band == IEEE80211_BAND_5GHZ)
975 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
976 else
977 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
978
979 priv->band = band;
980
e1623446 981 IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
bf85ea4f
AK		 982
983 return 0;
984}
c7de35cd 985EXPORT_SYMBOL(iwl_set_rxon_channel);
bf85ea4f 986
8ccde88a
SO		 987void iwl_set_flags_for_band(struct iwl_priv *priv,
988 enum ieee80211_band band)
989{
990 if (band == IEEE80211_BAND_5GHZ) {
991 priv->staging_rxon.flags &=
992 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
993 | RXON_FLG_CCK_MSK);
994 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
995 } else {
996 /* Copied from iwl_post_associate() */
997 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
998 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
999 else
1000 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1001
1002 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
1003 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
1004
1005 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
1006 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
1007 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
1008 }
1009}
1010EXPORT_SYMBOL(iwl_set_flags_for_band);
1011
1012/*
1013 * initialize rxon structure with default values from eeprom
1014 */
1015void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
1016{
1017 const struct iwl_channel_info *ch_info;
1018
1019 memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
1020
1021 switch (mode) {
1022 case NL80211_IFTYPE_AP:
1023 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
1024 break;
1025
1026 case NL80211_IFTYPE_STATION:
1027 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
1028 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
1029 break;
1030
1031 case NL80211_IFTYPE_ADHOC:
1032 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
1033 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
1034 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
1035 RXON_FILTER_ACCEPT_GRP_MSK;
1036 break;
1037
1038 case NL80211_IFTYPE_MONITOR:
1039 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
1040 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
1041 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
1042 break;
1043 default:
1044 IWL_ERR(priv, "Unsupported interface type %d\n", mode);
1045 break;
1046 }
1047
1048#if 0
1049 /* TODO: Figure out when short_preamble would be set and cache from
1050 * that */
1051 if (!hw_to_local(priv->hw)->short_preamble)
1052 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
1053 else
1054 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
1055#endif
1056
1057 ch_info = iwl_get_channel_info(priv, priv->band,
1058 le16_to_cpu(priv->active_rxon.channel));
1059
1060 if (!ch_info)
1061 ch_info = &priv->channel_info[0];
1062
1063 /*
1064 * in some case A channels are all non IBSS
1065 * in this case force B/G channel
1066 */
1067 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
1068 !(is_channel_ibss(ch_info)))
1069 ch_info = &priv->channel_info[0];
1070
1071 priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
1072 priv->band = ch_info->band;
1073
1074 iwl_set_flags_for_band(priv, priv->band);
1075
1076 priv->staging_rxon.ofdm_basic_rates =
1077 (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1078 priv->staging_rxon.cck_basic_rates =
1079 (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1080
1081 priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
1082 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
1083 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1084 memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
1085 priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
1086 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
1087}
1088EXPORT_SYMBOL(iwl_connection_init_rx_config);
1089
1090void iwl_set_rate(struct iwl_priv *priv)
1091{
1092 const struct ieee80211_supported_band *hw = NULL;
1093 struct ieee80211_rate *rate;
1094 int i;
1095
1096 hw = iwl_get_hw_mode(priv, priv->band);
1097 if (!hw) {
1098 IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
1099 return;
1100 }
1101
1102 priv->active_rate = 0;
1103 priv->active_rate_basic = 0;
1104
1105 for (i = 0; i < hw->n_bitrates; i++) {
1106 rate = &(hw->bitrates[i]);
1107 if (rate->hw_value < IWL_RATE_COUNT)
1108 priv->active_rate |= (1 << rate->hw_value);
1109 }
1110
e1623446 1111 IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
8ccde88a
SO		 1112 priv->active_rate, priv->active_rate_basic);
1113
1114 /*
1115 * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
1116 * otherwise set it to the default of all CCK rates and 6, 12, 24 for
1117 * OFDM
1118 */
1119 if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
1120 priv->staging_rxon.cck_basic_rates =
1121 ((priv->active_rate_basic &
1122 IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
1123 else
1124 priv->staging_rxon.cck_basic_rates =
1125 (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
1126
1127 if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
1128 priv->staging_rxon.ofdm_basic_rates =
1129 ((priv->active_rate_basic &
1130 (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
1131 IWL_FIRST_OFDM_RATE) & 0xFF;
1132 else
1133 priv->staging_rxon.ofdm_basic_rates =
1134 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
1135}
1136EXPORT_SYMBOL(iwl_set_rate);
1137
1138void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1139{
1140 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1141 struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
1142 struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
e1623446 1143 IWL_DEBUG_11H(priv, "CSA notif: channel %d, status %d\n",
8ccde88a
SO		 1144 le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
1145 rxon->channel = csa->channel;
1146 priv->staging_rxon.channel = csa->channel;
1147}
1148EXPORT_SYMBOL(iwl_rx_csa);
1149
1150#ifdef CONFIG_IWLWIFI_DEBUG
1151static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
1152{
1153 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
1154
e1623446 1155 IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
8ccde88a 1156 iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e1623446
TW		 1157 IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
1158 IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
1159 IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
8ccde88a 1160 le32_to_cpu(rxon->filter_flags));
e1623446
TW		 1161 IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
1162 IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
8ccde88a 1163 rxon->ofdm_basic_rates);
e1623446
TW		 1164 IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
1165 IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
1166 IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
1167 IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
8ccde88a
SO		 1168}
1169#endif
1170
1171/**
1172 * iwl_irq_handle_error - called for HW or SW error interrupt from card
1173 */
1174void iwl_irq_handle_error(struct iwl_priv *priv)
1175{
1176 /* Set the FW error flag -- cleared on iwl_down */
1177 set_bit(STATUS_FW_ERROR, &priv->status);
1178
1179 /* Cancel currently queued command. */
1180 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1181
1182#ifdef CONFIG_IWLWIFI_DEBUG
1183 if (priv->debug_level & IWL_DL_FW_ERRORS) {
1184 iwl_dump_nic_error_log(priv);
1185 iwl_dump_nic_event_log(priv);
1186 iwl_print_rx_config_cmd(priv);
1187 }
1188#endif
1189
1190 wake_up_interruptible(&priv->wait_command_queue);
1191
1192 /* Keep the restart process from trying to send host
1193 * commands by clearing the INIT status bit */
1194 clear_bit(STATUS_READY, &priv->status);
1195
1196 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 1197 IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
8ccde88a
SO		 1198 "Restarting adapter due to uCode error.\n");
1199
1200 if (iwl_is_associated(priv)) {
1201 memcpy(&priv->recovery_rxon, &priv->active_rxon,
1202 sizeof(priv->recovery_rxon));
1203 priv->error_recovering = 1;
1204 }
1205 if (priv->cfg->mod_params->restart_fw)
1206 queue_work(priv->workqueue, &priv->restart);
1207 }
1208}
1209EXPORT_SYMBOL(iwl_irq_handle_error);
1210
1211void iwl_configure_filter(struct ieee80211_hw *hw,
1212 unsigned int changed_flags,
1213 unsigned int *total_flags,
1214 int mc_count, struct dev_addr_list *mc_list)
1215{
1216 struct iwl_priv *priv = hw->priv;
1217 __le32 *filter_flags = &priv->staging_rxon.filter_flags;
1218
e1623446 1219 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
8ccde88a
SO		 1220 changed_flags, *total_flags);
1221
1222 if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
1223 if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
1224 *filter_flags |= RXON_FILTER_PROMISC_MSK;
1225 else
1226 *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
1227 }
1228 if (changed_flags & FIF_ALLMULTI) {
1229 if (*total_flags & FIF_ALLMULTI)
1230 *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
1231 else
1232 *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
1233 }
1234 if (changed_flags & FIF_CONTROL) {
1235 if (*total_flags & FIF_CONTROL)
1236 *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
1237 else
1238 *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
1239 }
1240 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1241 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1242 *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
1243 else
1244 *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
1245 }
1246
1247 /* We avoid iwl_commit_rxon here to commit the new filter flags
1248 * since mac80211 will call ieee80211_hw_config immediately.
1249 * (mc_list is not supported at this time). Otherwise, we need to
1250 * queue a background iwl_commit_rxon work.
1251 */
1252
1253 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
1254 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
1255}
1256EXPORT_SYMBOL(iwl_configure_filter);
1257
6ba87956 1258int iwl_setup_mac(struct iwl_priv *priv)
bf85ea4f 1259{
6ba87956 1260 int ret;
bf85ea4f 1261 struct ieee80211_hw *hw = priv->hw;
e227ceac 1262 hw->rate_control_algorithm = "iwl-agn-rs";
bf85ea4f 1263
566bfe5a 1264 /* Tell mac80211 our characteristics */
605a0bd6 1265 hw->flags = IEEE80211_HW_SIGNAL_DBM |
8b30b1fe 1266 IEEE80211_HW_NOISE_DBM |
4be8c387
JB		 1267 IEEE80211_HW_AMPDU_AGGREGATION |
1268 IEEE80211_HW_SUPPORTS_PS;
f59ac048 1269 hw->wiphy->interface_modes =
f59ac048
LR		 1270 BIT(NL80211_IFTYPE_STATION) |
1271 BIT(NL80211_IFTYPE_ADHOC);
ea4a82dc 1272
2a44f911 1273 hw->wiphy->custom_regulatory = true;
2a519311 1274 hw->wiphy->max_scan_ssids = 1;
ea4a82dc 1275
bf85ea4f
AK		 1276 /* Default value; 4 EDCA QOS priorities */
1277 hw->queues = 4;
49779293
RR		 1278 /* queues to support 11n aggregation */
1279 if (priv->cfg->sku & IWL_SKU_N)
9f17b318 1280 hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues;
6ba87956
TW		 1281
1282 hw->conf.beacon_int = 100;
b5d7be5e 1283 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
6ba87956
TW		 1284
1285 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
1286 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1287 &priv->bands[IEEE80211_BAND_2GHZ];
1288 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
1289 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1290 &priv->bands[IEEE80211_BAND_5GHZ];
1291
1292 ret = ieee80211_register_hw(priv->hw);
1293 if (ret) {
15b1687c 1294 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
6ba87956
TW		 1295 return ret;
1296 }
1297 priv->mac80211_registered = 1;
1298
1299 return 0;
bf85ea4f 1300}
6ba87956 1301EXPORT_SYMBOL(iwl_setup_mac);
bf85ea4f 1302
da154e30
RR		 1303int iwl_set_hw_params(struct iwl_priv *priv)
1304{
1305 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
1306 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1307 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1308 if (priv->cfg->mod_params->amsdu_size_8K)
1309 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1310 else
1311 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1312 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1313
49779293
RR		 1314 if (priv->cfg->mod_params->disable_11n)
1315 priv->cfg->sku &= ~IWL_SKU_N;
1316
da154e30
RR		 1317 /* Device-specific setup */
1318 return priv->cfg->ops->lib->set_hw_params(priv);
1319}
1320EXPORT_SYMBOL(iwl_set_hw_params);
6ba87956
TW		 1321
1322int iwl_init_drv(struct iwl_priv *priv)
c7de35cd
RR		 1323{
1324 int ret;
c7de35cd 1325
c7de35cd
RR		 1326 priv->ibss_beacon = NULL;
1327
1328 spin_lock_init(&priv->lock);
1329 spin_lock_init(&priv->power_data.lock);
1330 spin_lock_init(&priv->sta_lock);
1331 spin_lock_init(&priv->hcmd_lock);
c7de35cd 1332
c7de35cd
RR		 1333 INIT_LIST_HEAD(&priv->free_frames);
1334
1335 mutex_init(&priv->mutex);
1336
1337 /* Clear the driver's (not device's) station table */
37deb2a0 1338 iwl_clear_stations_table(priv);
c7de35cd
RR		 1339
1340 priv->data_retry_limit = -1;
1341 priv->ieee_channels = NULL;
1342 priv->ieee_rates = NULL;
1343 priv->band = IEEE80211_BAND_2GHZ;
1344
05c914fe 1345 priv->iw_mode = NL80211_IFTYPE_STATION;
c7de35cd 1346
12837be1 1347 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
c7de35cd
RR		 1348
1349 /* Choose which receivers/antennas to use */
1350 iwl_set_rxon_chain(priv);
f53696de 1351 iwl_init_scan_params(priv);
c7de35cd
RR		 1352
1353 iwl_reset_qos(priv);
1354
1355 priv->qos_data.qos_active = 0;
1356 priv->qos_data.qos_cap.val = 0;
1357
c7de35cd 1358 priv->rates_mask = IWL_RATES_MASK;
d25aabb0
WT		 1359 /* If power management is turned on, default to CAM mode */
1360 priv->power_mode = IWL_POWER_MODE_CAM;
630fe9b6 1361 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
c7de35cd
RR		 1362
1363 ret = iwl_init_channel_map(priv);
1364 if (ret) {
15b1687c 1365 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
c7de35cd
RR		 1366 goto err;
1367 }
1368
1369 ret = iwlcore_init_geos(priv);
1370 if (ret) {
15b1687c 1371 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
c7de35cd
RR		 1372 goto err_free_channel_map;
1373 }
534166de 1374 iwlcore_init_hw_rates(priv, priv->ieee_rates);
c7de35cd 1375
c7de35cd
RR		 1376 return 0;
1377
c7de35cd
RR		 1378err_free_channel_map:
1379 iwl_free_channel_map(priv);
1380err:
1381 return ret;
1382}
6ba87956 1383EXPORT_SYMBOL(iwl_init_drv);
c7de35cd 1384
630fe9b6
TW		 1385int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1386{
1387 int ret = 0;
1388 if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
daf518de
WF		 1389 IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
1390 tx_power,
1391 IWL_TX_POWER_TARGET_POWER_MIN);
630fe9b6
TW		 1392 return -EINVAL;
1393 }
1394
1395 if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
daf518de
WF		 1396 IWL_WARN(priv, "Requested user TXPOWER %d above upper limit %d.\n",
1397 tx_power,
1398 IWL_TX_POWER_TARGET_POWER_MAX);
630fe9b6
TW		 1399 return -EINVAL;
1400 }
1401
1402 if (priv->tx_power_user_lmt != tx_power)
1403 force = true;
1404
1405 priv->tx_power_user_lmt = tx_power;
1406
1407 if (force && priv->cfg->ops->lib->send_tx_power)
1408 ret = priv->cfg->ops->lib->send_tx_power(priv);
1409
1410 return ret;
1411}
1412EXPORT_SYMBOL(iwl_set_tx_power);
1413
6ba87956 1414void iwl_uninit_drv(struct iwl_priv *priv)
bf85ea4f 1415{
6e21f2c1 1416 iwl_calib_free_results(priv);
6ba87956
TW		 1417 iwlcore_free_geos(priv);
1418 iwl_free_channel_map(priv);
261415f7 1419 kfree(priv->scan);
bf85ea4f 1420}
6ba87956 1421EXPORT_SYMBOL(iwl_uninit_drv);
bf85ea4f 1422
0ad91a35
WT		 1423
1424void iwl_disable_interrupts(struct iwl_priv *priv)
1425{
1426 clear_bit(STATUS_INT_ENABLED, &priv->status);
1427
1428 /* disable interrupts from uCode/NIC to host */
1429 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
1430
1431 /* acknowledge/clear/reset any interrupts still pending
1432 * from uCode or flow handler (Rx/Tx DMA) */
1433 iwl_write32(priv, CSR_INT, 0xffffffff);
1434 iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
e1623446 1435 IWL_DEBUG_ISR(priv, "Disabled interrupts\n");
0ad91a35
WT		 1436}
1437EXPORT_SYMBOL(iwl_disable_interrupts);
1438
1439void iwl_enable_interrupts(struct iwl_priv *priv)
1440{
e1623446 1441 IWL_DEBUG_ISR(priv, "Enabling interrupts\n");
0ad91a35
WT		 1442 set_bit(STATUS_INT_ENABLED, &priv->status);
1443 iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
1444}
1445EXPORT_SYMBOL(iwl_enable_interrupts);
1446
17f841cd
SO		 1447int iwl_send_bt_config(struct iwl_priv *priv)
1448{
1449 struct iwl_bt_cmd bt_cmd = {
1450 .flags = 3,
1451 .lead_time = 0xAA,
1452 .max_kill = 1,
1453 .kill_ack_mask = 0,
1454 .kill_cts_mask = 0,
1455 };
1456
1457 return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1458 sizeof(struct iwl_bt_cmd), &bt_cmd);
1459}
1460EXPORT_SYMBOL(iwl_send_bt_config);
1461
49ea8596
EG		 1462int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
1463{
1464 u32 stat_flags = 0;
1465 struct iwl_host_cmd cmd = {
1466 .id = REPLY_STATISTICS_CMD,
1467 .meta.flags = flags,
1468 .len = sizeof(stat_flags),
1469 .data = (u8 *) &stat_flags,
1470 };
1471 return iwl_send_cmd(priv, &cmd);
1472}
1473EXPORT_SYMBOL(iwl_send_statistics_request);
7e8c519e 1474
b0692f2f
EG		 1475/**
1476 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1477 * using sample data 100 bytes apart. If these sample points are good,
1478 * it's a pretty good bet that everything between them is good, too.
1479 */
1480static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1481{
1482 u32 val;
1483 int ret = 0;
1484 u32 errcnt = 0;
1485 u32 i;
1486
e1623446 1487 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f
EG		 1488
1489 ret = iwl_grab_nic_access(priv);
1490 if (ret)
1491 return ret;
1492
1493 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1494 /* read data comes through single port, auto-incr addr */
1495 /* NOTE: Use the debugless read so we don't flood kernel log
1496 * if IWL_DL_IO is set */
1497 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 1498 i + IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 1499 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1500 if (val != le32_to_cpu(*image)) {
1501 ret = -EIO;
1502 errcnt++;
1503 if (errcnt >= 3)
1504 break;
1505 }
1506 }
1507
1508 iwl_release_nic_access(priv);
1509
1510 return ret;
1511}
1512
1513/**
1514 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1515 * looking at all data.
1516 */
1517static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1518 u32 len)
1519{
1520 u32 val;
1521 u32 save_len = len;
1522 int ret = 0;
1523 u32 errcnt;
1524
e1623446 1525 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b0692f2f
EG		 1526
1527 ret = iwl_grab_nic_access(priv);
1528 if (ret)
1529 return ret;
1530
250bdd21
SO		 1531 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1532 IWL49_RTC_INST_LOWER_BOUND);
b0692f2f
EG		 1533
1534 errcnt = 0;
1535 for (; len > 0; len -= sizeof(u32), image++) {
1536 /* read data comes through single port, auto-incr addr */
1537 /* NOTE: Use the debugless read so we don't flood kernel log
1538 * if IWL_DL_IO is set */
1539 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1540 if (val != le32_to_cpu(*image)) {
15b1687c 1541 IWL_ERR(priv, "uCode INST section is invalid at "
b0692f2f
EG		 1542 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1543 save_len - len, val, le32_to_cpu(*image));
1544 ret = -EIO;
1545 errcnt++;
1546 if (errcnt >= 20)
1547 break;
1548 }
1549 }
1550
1551 iwl_release_nic_access(priv);
1552
1553 if (!errcnt)
e1623446
TW		 1554 IWL_DEBUG_INFO(priv,
1555 "ucode image in INSTRUCTION memory is good\n");
b0692f2f
EG		 1556
1557 return ret;
1558}
1559
1560/**
1561 * iwl_verify_ucode - determine which instruction image is in SRAM,
1562 * and verify its contents
1563 */
1564int iwl_verify_ucode(struct iwl_priv *priv)
1565{
1566 __le32 *image;
1567 u32 len;
1568 int ret;
1569
1570 /* Try bootstrap */
1571 image = (__le32 *)priv->ucode_boot.v_addr;
1572 len = priv->ucode_boot.len;
1573 ret = iwlcore_verify_inst_sparse(priv, image, len);
1574 if (!ret) {
e1623446 1575 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b0692f2f
EG		 1576 return 0;
1577 }
1578
1579 /* Try initialize */
1580 image = (__le32 *)priv->ucode_init.v_addr;
1581 len = priv->ucode_init.len;
1582 ret = iwlcore_verify_inst_sparse(priv, image, len);
1583 if (!ret) {
e1623446 1584 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b0692f2f
EG		 1585 return 0;
1586 }
1587
1588 /* Try runtime/protocol */
1589 image = (__le32 *)priv->ucode_code.v_addr;
1590 len = priv->ucode_code.len;
1591 ret = iwlcore_verify_inst_sparse(priv, image, len);
1592 if (!ret) {
e1623446 1593 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b0692f2f
EG		 1594 return 0;
1595 }
1596
15b1687c 1597 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b0692f2f
EG		 1598
1599 /* Since nothing seems to match, show first several data entries in
1600 * instruction SRAM, so maybe visual inspection will give a clue.
1601 * Selection of bootstrap image (vs. other images) is arbitrary. */
1602 image = (__le32 *)priv->ucode_boot.v_addr;
1603 len = priv->ucode_boot.len;
1604 ret = iwl_verify_inst_full(priv, image, len);
1605
1606 return ret;
1607}
1608EXPORT_SYMBOL(iwl_verify_ucode);
1609
56e12615
JS		 1610
1611static const char *desc_lookup_text[] = {
1612 "OK",
1613 "FAIL",
1614 "BAD_PARAM",
1615 "BAD_CHECKSUM",
1616 "NMI_INTERRUPT_WDG",
1617 "SYSASSERT",
1618 "FATAL_ERROR",
1619 "BAD_COMMAND",
1620 "HW_ERROR_TUNE_LOCK",
1621 "HW_ERROR_TEMPERATURE",
1622 "ILLEGAL_CHAN_FREQ",
1623 "VCC_NOT_STABLE",
1624 "FH_ERROR",
1625 "NMI_INTERRUPT_HOST",
1626 "NMI_INTERRUPT_ACTION_PT",
1627 "NMI_INTERRUPT_UNKNOWN",
1628 "UCODE_VERSION_MISMATCH",
1629 "HW_ERROR_ABS_LOCK",
1630 "HW_ERROR_CAL_LOCK_FAIL",
1631 "NMI_INTERRUPT_INST_ACTION_PT",
1632 "NMI_INTERRUPT_DATA_ACTION_PT",
1633 "NMI_TRM_HW_ER",
1634 "NMI_INTERRUPT_TRM",
1635 "NMI_INTERRUPT_BREAK_POINT"
1636 "DEBUG_0",
1637 "DEBUG_1",
1638 "DEBUG_2",
1639 "DEBUG_3",
1640 "UNKNOWN"
1641};
1642
ede0cba4
EK		 1643static const char *desc_lookup(int i)
1644{
56e12615
JS		 1645 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1646
1647 if (i < 0 || i > max)
1648 i = max;
ede0cba4 1649
56e12615 1650 return desc_lookup_text[i];
ede0cba4
EK		 1651}
1652
1653#define ERROR_START_OFFSET (1 * sizeof(u32))
1654#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1655
1656void iwl_dump_nic_error_log(struct iwl_priv *priv)
1657{
1658 u32 data2, line;
1659 u32 desc, time, count, base, data1;
1660 u32 blink1, blink2, ilink1, ilink2;
e1dfc085 1661 int ret;
ede0cba4 1662
e1dfc085
GG		 1663 if (priv->ucode_type == UCODE_INIT)
1664 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1665 else
1666 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
ede0cba4
EK		 1667
1668 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
15b1687c 1669 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
ede0cba4
EK		 1670 return;
1671 }
1672
e1dfc085
GG		 1673 ret = iwl_grab_nic_access(priv);
1674 if (ret) {
39aadf8c 1675 IWL_WARN(priv, "Can not read from adapter at this time.\n");
ede0cba4
EK		 1676 return;
1677 }
1678
1679 count = iwl_read_targ_mem(priv, base);
1680
1681 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT		 1682 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1683 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1684 priv->status, count);
ede0cba4
EK		 1685 }
1686
1687 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1688 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1689 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1690 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1691 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1692 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1693 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1694 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1695 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1696
15b1687c 1697 IWL_ERR(priv, "Desc Time "
ede0cba4 1698 "data1 data2 line\n");
15b1687c 1699 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
ede0cba4 1700 desc_lookup(desc), desc, time, data1, data2, line);
15b1687c
WT		 1701 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1702 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
ede0cba4
EK		 1703 ilink1, ilink2);
1704
1705 iwl_release_nic_access(priv);
1706}
1707EXPORT_SYMBOL(iwl_dump_nic_error_log);
1708
189a2b59
EK		 1709#define EVENT_START_OFFSET (4 * sizeof(u32))
1710
1711/**
1712 * iwl_print_event_log - Dump error event log to syslog
1713 *
a33c2f47 1714 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
189a2b59 1715 */
a33c2f47 1716static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
189a2b59
EK		 1717 u32 num_events, u32 mode)
1718{
1719 u32 i;
1720 u32 base; /* SRAM byte address of event log header */
1721 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1722 u32 ptr; /* SRAM byte address of log data */
1723 u32 ev, time, data; /* event log data */
1724
1725 if (num_events == 0)
1726 return;
e1dfc085
GG		 1727 if (priv->ucode_type == UCODE_INIT)
1728 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1729 else
1730 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
189a2b59
EK		 1731
1732 if (mode == 0)
1733 event_size = 2 * sizeof(u32);
1734 else
1735 event_size = 3 * sizeof(u32);
1736
1737 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1738
1739 /* "time" is actually "data" for mode 0 (no timestamp).
1740 * place event id # at far right for easier visual parsing. */
1741 for (i = 0; i < num_events; i++) {
1742 ev = iwl_read_targ_mem(priv, ptr);
1743 ptr += sizeof(u32);
1744 time = iwl_read_targ_mem(priv, ptr);
1745 ptr += sizeof(u32);
77c5d08e
TW		 1746 if (mode == 0) {
1747 /* data, ev */
15b1687c 1748 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
77c5d08e 1749 } else {
189a2b59
EK		 1750 data = iwl_read_targ_mem(priv, ptr);
1751 ptr += sizeof(u32);
15b1687c 1752 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
77c5d08e 1753 time, data, ev);
189a2b59
EK		 1754 }
1755 }
1756}
189a2b59
EK		 1757
1758void iwl_dump_nic_event_log(struct iwl_priv *priv)
1759{
e1dfc085 1760 int ret;
189a2b59
EK		 1761 u32 base; /* SRAM byte address of event log header */
1762 u32 capacity; /* event log capacity in # entries */
1763 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1764 u32 num_wraps; /* # times uCode wrapped to top of log */
1765 u32 next_entry; /* index of next entry to be written by uCode */
1766 u32 size; /* # entries that we'll print */
1767
e1dfc085
GG		 1768 if (priv->ucode_type == UCODE_INIT)
1769 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1770 else
1771 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1772
189a2b59 1773 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
15b1687c 1774 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
189a2b59
EK		 1775 return;
1776 }
1777
e1dfc085
GG		 1778 ret = iwl_grab_nic_access(priv);
1779 if (ret) {
39aadf8c 1780 IWL_WARN(priv, "Can not read from adapter at this time.\n");
189a2b59
EK		 1781 return;
1782 }
1783
1784 /* event log header */
1785 capacity = iwl_read_targ_mem(priv, base);
1786 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1787 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1788 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1789
1790 size = num_wraps ? capacity : next_entry;
1791
1792 /* bail out if nothing in log */
1793 if (size == 0) {
15b1687c 1794 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
189a2b59
EK		 1795 iwl_release_nic_access(priv);
1796 return;
1797 }
1798
15b1687c 1799 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
189a2b59
EK		 1800 size, num_wraps);
1801
1802 /* if uCode has wrapped back to top of log, start at the oldest entry,
1803 * i.e the next one that uCode would fill. */
1804 if (num_wraps)
1805 iwl_print_event_log(priv, next_entry,
1806 capacity - next_entry, mode);
1807 /* (then/else) start at top of log */
1808 iwl_print_event_log(priv, 0, next_entry, mode);
1809
1810 iwl_release_nic_access(priv);
1811}
1812EXPORT_SYMBOL(iwl_dump_nic_event_log);
1813
47f4a587
EG		 1814void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1815{
1816 struct iwl_ct_kill_config cmd;
1817 unsigned long flags;
1818 int ret = 0;
1819
1820 spin_lock_irqsave(&priv->lock, flags);
1821 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1822 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1823 spin_unlock_irqrestore(&priv->lock, flags);
1824
1825 cmd.critical_temperature_R =
1826 cpu_to_le32(priv->hw_params.ct_kill_threshold);
189a2b59 1827
47f4a587
EG		 1828 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1829 sizeof(cmd), &cmd);
1830 if (ret)
15b1687c 1831 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
47f4a587 1832 else
e1623446 1833 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD succeeded, "
47f4a587
EG		 1834 "critical temperature is %d\n",
1835 cmd.critical_temperature_R);
1836}
1837EXPORT_SYMBOL(iwl_rf_kill_ct_config);
14a08a7f 1838
0ad91a35 1839
14a08a7f
EG		 1840/*
1841 * CARD_STATE_CMD
1842 *
1843 * Use: Sets the device's internal card state to enable, disable, or halt
1844 *
1845 * When in the 'enable' state the card operates as normal.
1846 * When in the 'disable' state, the card enters into a low power mode.
1847 * When in the 'halt' state, the card is shut down and must be fully
1848 * restarted to come back on.
1849 */
c496294e 1850int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
14a08a7f
EG		 1851{
1852 struct iwl_host_cmd cmd = {
1853 .id = REPLY_CARD_STATE_CMD,
1854 .len = sizeof(u32),
1855 .data = &flags,
1856 .meta.flags = meta_flag,
1857 };
1858
1859 return iwl_send_cmd(priv, &cmd);
1860}
c496294e 1861EXPORT_SYMBOL(iwl_send_card_state);
14a08a7f
EG		 1862
1863void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1864{
1865 unsigned long flags;
1866
1867 if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1868 return;
1869
e1623446 1870 IWL_DEBUG_RF_KILL(priv, "Manual SW RF KILL set to: RADIO OFF\n");
14a08a7f
EG		 1871
1872 iwl_scan_cancel(priv);
1873 /* FIXME: This is a workaround for AP */
05c914fe 1874 if (priv->iw_mode != NL80211_IFTYPE_AP) {
14a08a7f
EG		 1875 spin_lock_irqsave(&priv->lock, flags);
1876 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1877 CSR_UCODE_SW_BIT_RFKILL);
1878 spin_unlock_irqrestore(&priv->lock, flags);
1879 /* call the host command only if no hw rf-kill set */
1880 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1881 iwl_is_ready(priv))
1882 iwl_send_card_state(priv,
1883 CARD_STATE_CMD_DISABLE, 0);
1884 set_bit(STATUS_RF_KILL_SW, &priv->status);
1885 /* make sure mac80211 stop sending Tx frame */
1886 if (priv->mac80211_registered)
1887 ieee80211_stop_queues(priv->hw);
1888 }
1889}
1890EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1891
1892int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1893{
1894 unsigned long flags;
1895
1896 if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1897 return 0;
1898
e1623446 1899 IWL_DEBUG_RF_KILL(priv, "Manual SW RF KILL set to: RADIO ON\n");
14a08a7f
EG		 1900
1901 spin_lock_irqsave(&priv->lock, flags);
1902 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1903
a9efa652
EG		 1904 /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1905 * notification where it will clear SW rfkill status.
1906 * Setting it here would break the handler. Only if the
1907 * interface is down we can set here since we don't
1908 * receive any further notification.
1909 */
1910 if (!priv->is_open)
1911 clear_bit(STATUS_RF_KILL_SW, &priv->status);
14a08a7f
EG		 1912 spin_unlock_irqrestore(&priv->lock, flags);
1913
1914 /* wake up ucode */
1915 msleep(10);
1916
1917 spin_lock_irqsave(&priv->lock, flags);
1918 iwl_read32(priv, CSR_UCODE_DRV_GP1);
1919 if (!iwl_grab_nic_access(priv))
1920 iwl_release_nic_access(priv);
1921 spin_unlock_irqrestore(&priv->lock, flags);
1922
1923 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
e1623446 1924 IWL_DEBUG_RF_KILL(priv, "Can not turn radio back on - "
14a08a7f
EG		 1925 "disabled by HW switch\n");
1926 return 0;
1927 }
1928
edb34228
MA		 1929 /* when driver is up while rfkill is on, it wont receive
1930 * any CARD_STATE_NOTIFICATION notifications so we have to
1931 * restart it in here
1932 */
1933 if (priv->is_open && !test_bit(STATUS_ALIVE, &priv->status)) {
1934 clear_bit(STATUS_RF_KILL_SW, &priv->status);
1935 if (!iwl_is_rfkill(priv))
1936 queue_work(priv->workqueue, &priv->up);
1937 }
1938
a9efa652
EG		 1939 /* If the driver is already loaded, it will receive
1940 * CARD_STATE_NOTIFICATION notifications and the handler will
1941 * call restart to reload the driver.
1942 */
14a08a7f
EG		 1943 return 1;
1944}
1945EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);
c0af96a6
SO		 1946
1947void iwl_bg_rf_kill(struct work_struct *work)
1948{
1949 struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill);
1950
1951 wake_up_interruptible(&priv->wait_command_queue);
1952
1953 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1954 return;
1955
1956 mutex_lock(&priv->mutex);
1957
1958 if (!iwl_is_rfkill(priv)) {
e1623446 1959 IWL_DEBUG_RF_KILL(priv,
c0af96a6
SO		 1960 "HW and/or SW RF Kill no longer active, restarting "
1961 "device\n");
1962 if (!test_bit(STATUS_EXIT_PENDING, &priv->status) &&
1963 test_bit(STATUS_ALIVE, &priv->status))
1964 queue_work(priv->workqueue, &priv->restart);
1965 } else {
1966 /* make sure mac80211 stop sending Tx frame */
1967 if (priv->mac80211_registered)
1968 ieee80211_stop_queues(priv->hw);
1969
1970 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
e1623446 1971 IWL_DEBUG_RF_KILL(priv, "Can not turn radio back on - "
c0af96a6
SO		 1972 "disabled by SW switch\n");
1973 else
1974 IWL_WARN(priv, "Radio Frequency Kill Switch is On:\n"
1975 "Kill switch must be turned off for "
1976 "wireless networking to work.\n");
1977 }
1978 mutex_unlock(&priv->mutex);
1979 iwl_rfkill_set_hw_state(priv);
1980}
1981EXPORT_SYMBOL(iwl_bg_rf_kill);
030f05ed
AK		 1982
1983void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
1984 struct iwl_rx_mem_buffer *rxb)
1985{
1986#ifdef CONFIG_IWLWIFI_DEBUG
1987 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1988 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
1989 IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
1990 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
1991#endif
1992}
1993EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
1994
1995void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
1996 struct iwl_rx_mem_buffer *rxb)
1997{
1998 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1999 IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
2000 "notification for %s:\n",
2001 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
2002 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
2003}
2004EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
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