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iwlwifi: use the DMA state API instead of the pci equivalents
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn-tx.c
CommitLineData
b305a080
WYG		 1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/sched.h>
34
35#include "iwl-dev.h"
36#include "iwl-core.h"
37#include "iwl-sta.h"
38#include "iwl-io.h"
74bcdb33 39#include "iwl-helpers.h"
19e6cda0 40#include "iwl-agn-hw.h"
8d801080 41#include "iwl-agn.h"
b305a080 42
74bcdb33
WYG		 43/*
44 * mac80211 queues, ACs, hardware queues, FIFOs.
45 *
46 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
47 *
48 * Mac80211 uses the following numbers, which we get as from it
49 * by way of skb_get_queue_mapping(skb):
50 *
51 * VO 0
52 * VI 1
53 * BE 2
54 * BK 3
55 *
56 *
57 * Regular (not A-MPDU) frames are put into hardware queues corresponding
58 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
59 * own queue per aggregation session (RA/TID combination), such queues are
60 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
61 * order to map frames to the right queue, we also need an AC->hw queue
62 * mapping. This is implemented here.
63 *
64 * Due to the way hw queues are set up (by the hw specific modules like
65 * iwl-4965.c, iwl-5000.c etc.), the AC->hw queue mapping is the identity
66 * mapping.
67 */
68
69static const u8 tid_to_ac[] = {
70 /* this matches the mac80211 numbers */
71 2, 3, 3, 2, 1, 1, 0, 0
72};
73
74static const u8 ac_to_fifo[] = {
75 IWL_TX_FIFO_VO,
76 IWL_TX_FIFO_VI,
77 IWL_TX_FIFO_BE,
78 IWL_TX_FIFO_BK,
79};
80
81static inline int get_fifo_from_ac(u8 ac)
82{
83 return ac_to_fifo[ac];
84}
85
c2845d01
SZ		 86static inline int get_ac_from_tid(u16 tid)
87{
88 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
89 return tid_to_ac[tid];
90
91 /* no support for TIDs 8-15 yet */
92 return -EINVAL;
93}
94
74bcdb33
WYG		 95static inline int get_fifo_from_tid(u16 tid)
96{
97 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
98 return get_fifo_from_ac(tid_to_ac[tid]);
99
100 /* no support for TIDs 8-15 yet */
101 return -EINVAL;
102}
103
b305a080
WYG		 104/**
105 * iwlagn_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
106 */
107void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
108 struct iwl_tx_queue *txq,
109 u16 byte_cnt)
110{
19e6cda0 111 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
b305a080
WYG		 112 int write_ptr = txq->q.write_ptr;
113 int txq_id = txq->q.id;
114 u8 sec_ctl = 0;
115 u8 sta_id = 0;
116 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
117 __le16 bc_ent;
118
119 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
120
121 if (txq_id != IWL_CMD_QUEUE_NUM) {
122 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
123 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
124
125 switch (sec_ctl & TX_CMD_SEC_MSK) {
126 case TX_CMD_SEC_CCM:
127 len += CCMP_MIC_LEN;
128 break;
129 case TX_CMD_SEC_TKIP:
130 len += TKIP_ICV_LEN;
131 break;
132 case TX_CMD_SEC_WEP:
133 len += WEP_IV_LEN + WEP_ICV_LEN;
134 break;
135 }
136 }
137
138 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
139
140 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
141
142 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
143 scd_bc_tbl[txq_id].
144 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
145}
146
147void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
148 struct iwl_tx_queue *txq)
149{
19e6cda0 150 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
b305a080
WYG		 151 int txq_id = txq->q.id;
152 int read_ptr = txq->q.read_ptr;
153 u8 sta_id = 0;
154 __le16 bc_ent;
155
156 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
157
158 if (txq_id != IWL_CMD_QUEUE_NUM)
159 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
160
161 bc_ent = cpu_to_le16(1 | (sta_id << 12));
162 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
163
164 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
165 scd_bc_tbl[txq_id].
166 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
167}
168
169static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
170 u16 txq_id)
171{
172 u32 tbl_dw_addr;
173 u32 tbl_dw;
174 u16 scd_q2ratid;
175
176 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
177
178 tbl_dw_addr = priv->scd_base_addr +
f4388adc 179 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
b305a080
WYG		 180
181 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
182
183 if (txq_id & 0x1)
184 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
185 else
186 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
187
188 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
189
190 return 0;
191}
192
193static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
194{
195 /* Simply stop the queue, but don't change any configuration;
196 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
197 iwl_write_prph(priv,
f4388adc
WYG		 198 IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
199 (0 << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
200 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
b305a080
WYG		 201}
202
203void iwlagn_set_wr_ptrs(struct iwl_priv *priv,
204 int txq_id, u32 index)
205{
206 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
207 (index & 0xff) | (txq_id << 8));
f4388adc 208 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(txq_id), index);
b305a080
WYG		 209}
210
211void iwlagn_tx_queue_set_status(struct iwl_priv *priv,
212 struct iwl_tx_queue *txq,
213 int tx_fifo_id, int scd_retry)
214{
215 int txq_id = txq->q.id;
216 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
217
f4388adc
WYG		 218 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
219 (active << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
220 (tx_fifo_id << IWLAGN_SCD_QUEUE_STTS_REG_POS_TXF) |
221 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_WSL) |
222 IWLAGN_SCD_QUEUE_STTS_REG_MSK);
b305a080
WYG		 223
224 txq->sched_retry = scd_retry;
225
226 IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
227 active ? "Activate" : "Deactivate",
228 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
229}
230
231int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id,
232 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
233{
234 unsigned long flags;
235 u16 ra_tid;
236
19e6cda0
WYG		 237 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
238 (IWLAGN_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
b305a080
WYG		 239 <= txq_id)) {
240 IWL_WARN(priv,
241 "queue number out of range: %d, must be %d to %d\n",
19e6cda0
WYG		 242 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
243 IWLAGN_FIRST_AMPDU_QUEUE +
b305a080
WYG		 244 priv->cfg->num_of_ampdu_queues - 1);
245 return -EINVAL;
246 }
247
248 ra_tid = BUILD_RAxTID(sta_id, tid);
249
250 /* Modify device's station table to Tx this TID */
251 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
252
253 spin_lock_irqsave(&priv->lock, flags);
254
255 /* Stop this Tx queue before configuring it */
256 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
257
258 /* Map receiver-address / traffic-ID to this queue */
259 iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
260
261 /* Set this queue as a chain-building queue */
f4388adc 262 iwl_set_bits_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL, (1<<txq_id));
b305a080
WYG		 263
264 /* enable aggregations for the queue */
f4388adc 265 iwl_set_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1<<txq_id));
b305a080
WYG		 266
267 /* Place first TFD at index corresponding to start sequence number.
268 * Assumes that ssn_idx is valid (!= 0xFFF) */
269 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
270 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
271 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
272
273 /* Set up Tx window size and frame limit for this queue */
274 iwl_write_targ_mem(priv, priv->scd_base_addr +
f4388adc 275 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
b305a080
WYG		 276 sizeof(u32),
277 ((SCD_WIN_SIZE <<
f4388adc
WYG		 278 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
279 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
b305a080 280 ((SCD_FRAME_LIMIT <<
f4388adc
WYG		 281 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
282 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
b305a080 283
f4388adc 284 iwl_set_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
b305a080
WYG		 285
286 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
287 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
288
289 spin_unlock_irqrestore(&priv->lock, flags);
290
291 return 0;
292}
293
294int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
295 u16 ssn_idx, u8 tx_fifo)
296{
19e6cda0
WYG		 297 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
298 (IWLAGN_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
b305a080
WYG		 299 <= txq_id)) {
300 IWL_ERR(priv,
301 "queue number out of range: %d, must be %d to %d\n",
19e6cda0
WYG		 302 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
303 IWLAGN_FIRST_AMPDU_QUEUE +
b305a080
WYG		 304 priv->cfg->num_of_ampdu_queues - 1);
305 return -EINVAL;
306 }
307
308 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
309
f4388adc 310 iwl_clear_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1 << txq_id));
b305a080
WYG		 311
312 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
313 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
314 /* supposes that ssn_idx is valid (!= 0xFFF) */
315 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
316
f4388adc 317 iwl_clear_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
b305a080
WYG		 318 iwl_txq_ctx_deactivate(priv, txq_id);
319 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
320
321 return 0;
322}
323
324/*
325 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
326 * must be called under priv->lock and mac access
327 */
328void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask)
329{
f4388adc 330 iwl_write_prph(priv, IWLAGN_SCD_TXFACT, mask);
b305a080 331}
74bcdb33
WYG		 332
333static inline int get_queue_from_ac(u16 ac)
334{
335 return ac;
336}
337
338/*
339 * handle build REPLY_TX command notification.
340 */
341static void iwlagn_tx_cmd_build_basic(struct iwl_priv *priv,
342 struct iwl_tx_cmd *tx_cmd,
343 struct ieee80211_tx_info *info,
344 struct ieee80211_hdr *hdr,
345 u8 std_id)
346{
347 __le16 fc = hdr->frame_control;
348 __le32 tx_flags = tx_cmd->tx_flags;
349
350 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
351 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
352 tx_flags |= TX_CMD_FLG_ACK_MSK;
353 if (ieee80211_is_mgmt(fc))
354 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
355 if (ieee80211_is_probe_resp(fc) &&
356 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
357 tx_flags |= TX_CMD_FLG_TSF_MSK;
358 } else {
359 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
360 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
361 }
362
363 if (ieee80211_is_back_req(fc))
364 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
365
366
367 tx_cmd->sta_id = std_id;
368 if (ieee80211_has_morefrags(fc))
369 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
370
371 if (ieee80211_is_data_qos(fc)) {
372 u8 *qc = ieee80211_get_qos_ctl(hdr);
373 tx_cmd->tid_tspec = qc[0] & 0xf;
374 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
375 } else {
376 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
377 }
378
379 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
380
381 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
382 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
383
384 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
385 if (ieee80211_is_mgmt(fc)) {
386 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
387 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
388 else
389 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
390 } else {
391 tx_cmd->timeout.pm_frame_timeout = 0;
392 }
393
394 tx_cmd->driver_txop = 0;
395 tx_cmd->tx_flags = tx_flags;
396 tx_cmd->next_frame_len = 0;
397}
398
399#define RTS_DFAULT_RETRY_LIMIT 60
400
401static void iwlagn_tx_cmd_build_rate(struct iwl_priv *priv,
402 struct iwl_tx_cmd *tx_cmd,
403 struct ieee80211_tx_info *info,
404 __le16 fc)
405{
406 u32 rate_flags;
407 int rate_idx;
408 u8 rts_retry_limit;
409 u8 data_retry_limit;
410 u8 rate_plcp;
411
412 /* Set retry limit on DATA packets and Probe Responses*/
413 if (ieee80211_is_probe_resp(fc))
414 data_retry_limit = 3;
415 else
b744cb79 416 data_retry_limit = IWLAGN_DEFAULT_TX_RETRY;
74bcdb33
WYG		 417 tx_cmd->data_retry_limit = data_retry_limit;
418
419 /* Set retry limit on RTS packets */
420 rts_retry_limit = RTS_DFAULT_RETRY_LIMIT;
421 if (data_retry_limit < rts_retry_limit)
422 rts_retry_limit = data_retry_limit;
423 tx_cmd->rts_retry_limit = rts_retry_limit;
424
425 /* DATA packets will use the uCode station table for rate/antenna
426 * selection */
427 if (ieee80211_is_data(fc)) {
428 tx_cmd->initial_rate_index = 0;
429 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
430 return;
431 }
432
433 /**
434 * If the current TX rate stored in mac80211 has the MCS bit set, it's
435 * not really a TX rate. Thus, we use the lowest supported rate for
436 * this band. Also use the lowest supported rate if the stored rate
437 * index is invalid.
438 */
439 rate_idx = info->control.rates[0].idx;
440 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
441 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
442 rate_idx = rate_lowest_index(&priv->bands[info->band],
443 info->control.sta);
444 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
445 if (info->band == IEEE80211_BAND_5GHZ)
446 rate_idx += IWL_FIRST_OFDM_RATE;
447 /* Get PLCP rate for tx_cmd->rate_n_flags */
448 rate_plcp = iwl_rates[rate_idx].plcp;
449 /* Zero out flags for this packet */
450 rate_flags = 0;
451
452 /* Set CCK flag as needed */
453 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
454 rate_flags |= RATE_MCS_CCK_MSK;
455
456 /* Set up RTS and CTS flags for certain packets */
457 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
458 case cpu_to_le16(IEEE80211_STYPE_AUTH):
459 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
460 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
461 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
462 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
463 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
464 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
465 }
466 break;
467 default:
468 break;
469 }
470
471 /* Set up antennas */
472 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
473 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
474
475 /* Set the rate in the TX cmd */
476 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
477}
478
479static void iwlagn_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
480 struct ieee80211_tx_info *info,
481 struct iwl_tx_cmd *tx_cmd,
482 struct sk_buff *skb_frag,
483 int sta_id)
484{
485 struct ieee80211_key_conf *keyconf = info->control.hw_key;
486
487 switch (keyconf->alg) {
488 case ALG_CCMP:
489 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
490 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
491 if (info->flags & IEEE80211_TX_CTL_AMPDU)
492 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
493 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
494 break;
495
496 case ALG_TKIP:
497 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
498 ieee80211_get_tkip_key(keyconf, skb_frag,
499 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
500 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
501 break;
502
503 case ALG_WEP:
504 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
505 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
506
507 if (keyconf->keylen == WEP_KEY_LEN_128)
508 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
509
510 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
511
512 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
513 "with key %d\n", keyconf->keyidx);
514 break;
515
516 default:
517 IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
518 break;
519 }
520}
521
522/*
523 * start REPLY_TX command process
524 */
525int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
526{
527 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
528 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
529 struct ieee80211_sta *sta = info->control.sta;
530 struct iwl_station_priv *sta_priv = NULL;
531 struct iwl_tx_queue *txq;
532 struct iwl_queue *q;
533 struct iwl_device_cmd *out_cmd;
534 struct iwl_cmd_meta *out_meta;
535 struct iwl_tx_cmd *tx_cmd;
536 int swq_id, txq_id;
537 dma_addr_t phys_addr;
538 dma_addr_t txcmd_phys;
539 dma_addr_t scratch_phys;
540 u16 len, len_org, firstlen, secondlen;
541 u16 seq_number = 0;
542 __le16 fc;
543 u8 hdr_len;
544 u8 sta_id;
545 u8 wait_write_ptr = 0;
546 u8 tid = 0;
547 u8 *qc = NULL;
548 unsigned long flags;
549
550 spin_lock_irqsave(&priv->lock, flags);
551 if (iwl_is_rfkill(priv)) {
552 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
553 goto drop_unlock;
554 }
555
556 fc = hdr->frame_control;
557
558#ifdef CONFIG_IWLWIFI_DEBUG
559 if (ieee80211_is_auth(fc))
560 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
561 else if (ieee80211_is_assoc_req(fc))
562 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
563 else if (ieee80211_is_reassoc_req(fc))
564 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
565#endif
566
567 hdr_len = ieee80211_hdrlen(fc);
568
2a87c26b 569 /* Find index into station table for destination station */
0af8bcae 570 sta_id = iwl_sta_id_or_broadcast(priv, info->control.sta);
74bcdb33
WYG		 571 if (sta_id == IWL_INVALID_STATION) {
572 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
573 hdr->addr1);
574 goto drop_unlock;
575 }
576
577 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
578
579 if (sta)
580 sta_priv = (void *)sta->drv_priv;
581
582 if (sta_priv && sta_id != priv->hw_params.bcast_sta_id &&
583 sta_priv->asleep) {
584 WARN_ON(!(info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE));
585 /*
586 * This sends an asynchronous command to the device,
587 * but we can rely on it being processed before the
588 * next frame is processed -- and the next frame to
589 * this station is the one that will consume this
590 * counter.
591 * For now set the counter to just 1 since we do not
592 * support uAPSD yet.
593 */
594 iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
595 }
596
597 txq_id = get_queue_from_ac(skb_get_queue_mapping(skb));
9c5ac091
RC		 598
599 /* irqs already disabled/saved above when locking priv->lock */
600 spin_lock(&priv->sta_lock);
601
74bcdb33
WYG		 602 if (ieee80211_is_data_qos(fc)) {
603 qc = ieee80211_get_qos_ctl(hdr);
604 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
9c5ac091
RC		 605 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
606 spin_unlock(&priv->sta_lock);
74bcdb33 607 goto drop_unlock;
9c5ac091 608 }
74bcdb33
WYG		 609 seq_number = priv->stations[sta_id].tid[tid].seq_number;
610 seq_number &= IEEE80211_SCTL_SEQ;
611 hdr->seq_ctrl = hdr->seq_ctrl &
612 cpu_to_le16(IEEE80211_SCTL_FRAG);
613 hdr->seq_ctrl |= cpu_to_le16(seq_number);
614 seq_number += 0x10;
615 /* aggregation is on for this <sta,tid> */
616 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
617 priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) {
618 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
619 }
620 }
621
622 txq = &priv->txq[txq_id];
623 swq_id = txq->swq_id;
624 q = &txq->q;
625
9c5ac091
RC		 626 if (unlikely(iwl_queue_space(q) < q->high_mark)) {
627 spin_unlock(&priv->sta_lock);
74bcdb33 628 goto drop_unlock;
9c5ac091 629 }
74bcdb33 630
9c5ac091 631 if (ieee80211_is_data_qos(fc)) {
74bcdb33 632 priv->stations[sta_id].tid[tid].tfds_in_queue++;
9c5ac091
RC		 633 if (!ieee80211_has_morefrags(fc))
634 priv->stations[sta_id].tid[tid].seq_number = seq_number;
635 }
636
637 spin_unlock(&priv->sta_lock);
74bcdb33
WYG		 638
639 /* Set up driver data for this TFD */
640 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
641 txq->txb[q->write_ptr].skb[0] = skb;
642
643 /* Set up first empty entry in queue's array of Tx/cmd buffers */
644 out_cmd = txq->cmd[q->write_ptr];
645 out_meta = &txq->meta[q->write_ptr];
646 tx_cmd = &out_cmd->cmd.tx;
647 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
648 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
649
650 /*
651 * Set up the Tx-command (not MAC!) header.
652 * Store the chosen Tx queue and TFD index within the sequence field;
653 * after Tx, uCode's Tx response will return this value so driver can
654 * locate the frame within the tx queue and do post-tx processing.
655 */
656 out_cmd->hdr.cmd = REPLY_TX;
657 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
658 INDEX_TO_SEQ(q->write_ptr)));
659
660 /* Copy MAC header from skb into command buffer */
661 memcpy(tx_cmd->hdr, hdr, hdr_len);
662
663
664 /* Total # bytes to be transmitted */
665 len = (u16)skb->len;
666 tx_cmd->len = cpu_to_le16(len);
667
668 if (info->control.hw_key)
669 iwlagn_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
670
671 /* TODO need this for burst mode later on */
672 iwlagn_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
673 iwl_dbg_log_tx_data_frame(priv, len, hdr);
674
675 iwlagn_tx_cmd_build_rate(priv, tx_cmd, info, fc);
676
677 iwl_update_stats(priv, true, fc, len);
678 /*
679 * Use the first empty entry in this queue's command buffer array
680 * to contain the Tx command and MAC header concatenated together
681 * (payload data will be in another buffer).
682 * Size of this varies, due to varying MAC header length.
683 * If end is not dword aligned, we'll have 2 extra bytes at the end
684 * of the MAC header (device reads on dword boundaries).
685 * We'll tell device about this padding later.
686 */
687 len = sizeof(struct iwl_tx_cmd) +
688 sizeof(struct iwl_cmd_header) + hdr_len;
689
690 len_org = len;
691 firstlen = len = (len + 3) & ~3;
692
693 if (len_org != len)
694 len_org = 1;
695 else
696 len_org = 0;
697
698 /* Tell NIC about any 2-byte padding after MAC header */
699 if (len_org)
700 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
701
702 /* Physical address of this Tx command's header (not MAC header!),
703 * within command buffer array. */
704 txcmd_phys = pci_map_single(priv->pci_dev,
705 &out_cmd->hdr, len,
706 PCI_DMA_BIDIRECTIONAL);
2e724443
FT		 707 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
708 dma_unmap_len_set(out_meta, len, len);
74bcdb33
WYG		 709 /* Add buffer containing Tx command and MAC(!) header to TFD's
710 * first entry */
711 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
712 txcmd_phys, len, 1, 0);
713
714 if (!ieee80211_has_morefrags(hdr->frame_control)) {
715 txq->need_update = 1;
74bcdb33
WYG		 716 } else {
717 wait_write_ptr = 1;
718 txq->need_update = 0;
719 }
720
721 /* Set up TFD's 2nd entry to point directly to remainder of skb,
722 * if any (802.11 null frames have no payload). */
723 secondlen = len = skb->len - hdr_len;
724 if (len) {
725 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
726 len, PCI_DMA_TODEVICE);
727 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
728 phys_addr, len,
729 0, 0);
730 }
731
732 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
733 offsetof(struct iwl_tx_cmd, scratch);
734
735 len = sizeof(struct iwl_tx_cmd) +
736 sizeof(struct iwl_cmd_header) + hdr_len;
737 /* take back ownership of DMA buffer to enable update */
738 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
739 len, PCI_DMA_BIDIRECTIONAL);
740 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
741 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
742
91dd6c27 743 IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
74bcdb33 744 le16_to_cpu(out_cmd->hdr.sequence));
91dd6c27 745 IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
74bcdb33
WYG		 746 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
747 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
748
749 /* Set up entry for this TFD in Tx byte-count array */
750 if (info->flags & IEEE80211_TX_CTL_AMPDU)
751 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
752 le16_to_cpu(tx_cmd->len));
753
754 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
755 len, PCI_DMA_BIDIRECTIONAL);
756
757 trace_iwlwifi_dev_tx(priv,
758 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
759 sizeof(struct iwl_tfd),
760 &out_cmd->hdr, firstlen,
761 skb->data + hdr_len, secondlen);
762
763 /* Tell device the write index *just past* this latest filled TFD */
764 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
765 iwl_txq_update_write_ptr(priv, txq);
766 spin_unlock_irqrestore(&priv->lock, flags);
767
768 /*
769 * At this point the frame is "transmitted" successfully
770 * and we will get a TX status notification eventually,
771 * regardless of the value of ret. "ret" only indicates
772 * whether or not we should update the write pointer.
773 */
774
775 /* avoid atomic ops if it isn't an associated client */
776 if (sta_priv && sta_priv->client)
777 atomic_inc(&sta_priv->pending_frames);
778
779 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
780 if (wait_write_ptr) {
781 spin_lock_irqsave(&priv->lock, flags);
782 txq->need_update = 1;
783 iwl_txq_update_write_ptr(priv, txq);
784 spin_unlock_irqrestore(&priv->lock, flags);
785 } else {
786 iwl_stop_queue(priv, txq->swq_id);
787 }
788 }
789
790 return 0;
791
792drop_unlock:
793 spin_unlock_irqrestore(&priv->lock, flags);
794 return -1;
795}
796
797static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
798 struct iwl_dma_ptr *ptr, size_t size)
799{
800 ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma,
801 GFP_KERNEL);
802 if (!ptr->addr)
803 return -ENOMEM;
804 ptr->size = size;
805 return 0;
806}
807
808static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
809 struct iwl_dma_ptr *ptr)
810{
811 if (unlikely(!ptr->addr))
812 return;
813
814 dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
815 memset(ptr, 0, sizeof(*ptr));
816}
817
818/**
819 * iwlagn_hw_txq_ctx_free - Free TXQ Context
820 *
821 * Destroy all TX DMA queues and structures
822 */
823void iwlagn_hw_txq_ctx_free(struct iwl_priv *priv)
824{
825 int txq_id;
826
827 /* Tx queues */
828 if (priv->txq) {
470058e0 829 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
74bcdb33
WYG		 830 if (txq_id == IWL_CMD_QUEUE_NUM)
831 iwl_cmd_queue_free(priv);
832 else
833 iwl_tx_queue_free(priv, txq_id);
834 }
835 iwlagn_free_dma_ptr(priv, &priv->kw);
836
837 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
838
839 /* free tx queue structure */
840 iwl_free_txq_mem(priv);
841}
842
843/**
470058e0
ZY		 844 * iwlagn_txq_ctx_alloc - allocate TX queue context
845 * Allocate all Tx DMA structures and initialize them
74bcdb33
WYG		 846 *
847 * @param priv
848 * @return error code
849 */
470058e0 850int iwlagn_txq_ctx_alloc(struct iwl_priv *priv)
74bcdb33 851{
470058e0 852 int ret;
74bcdb33
WYG		 853 int txq_id, slots_num;
854 unsigned long flags;
855
856 /* Free all tx/cmd queues and keep-warm buffer */
857 iwlagn_hw_txq_ctx_free(priv);
858
859 ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
860 priv->hw_params.scd_bc_tbls_size);
861 if (ret) {
862 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
863 goto error_bc_tbls;
864 }
865 /* Alloc keep-warm buffer */
866 ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
867 if (ret) {
868 IWL_ERR(priv, "Keep Warm allocation failed\n");
869 goto error_kw;
870 }
871
872 /* allocate tx queue structure */
873 ret = iwl_alloc_txq_mem(priv);
874 if (ret)
875 goto error;
876
877 spin_lock_irqsave(&priv->lock, flags);
878
879 /* Turn off all Tx DMA fifos */
880 priv->cfg->ops->lib->txq_set_sched(priv, 0);
881
882 /* Tell NIC where to find the "keep warm" buffer */
883 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
884
885 spin_unlock_irqrestore(&priv->lock, flags);
886
887 /* Alloc and init all Tx queues, including the command queue (#4) */
888 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
889 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
890 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
891 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
892 txq_id);
893 if (ret) {
894 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
895 goto error;
896 }
897 }
898
899 return ret;
900
901 error:
902 iwlagn_hw_txq_ctx_free(priv);
903 iwlagn_free_dma_ptr(priv, &priv->kw);
904 error_kw:
905 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
906 error_bc_tbls:
907 return ret;
908}
909
470058e0
ZY		 910void iwlagn_txq_ctx_reset(struct iwl_priv *priv)
911{
912 int txq_id, slots_num;
913 unsigned long flags;
914
915 spin_lock_irqsave(&priv->lock, flags);
916
917 /* Turn off all Tx DMA fifos */
918 priv->cfg->ops->lib->txq_set_sched(priv, 0);
919
920 /* Tell NIC where to find the "keep warm" buffer */
921 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
922
923 spin_unlock_irqrestore(&priv->lock, flags);
924
925 /* Alloc and init all Tx queues, including the command queue (#4) */
926 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
927 slots_num = txq_id == IWL_CMD_QUEUE_NUM ?
928 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
929 iwl_tx_queue_reset(priv, &priv->txq[txq_id], slots_num, txq_id);
930 }
931}
932
74bcdb33 933/**
470058e0 934 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
74bcdb33
WYG		 935 */
936void iwlagn_txq_ctx_stop(struct iwl_priv *priv)
937{
938 int ch;
939 unsigned long flags;
940
941 /* Turn off all Tx DMA fifos */
942 spin_lock_irqsave(&priv->lock, flags);
943
944 priv->cfg->ops->lib->txq_set_sched(priv, 0);
945
946 /* Stop each Tx DMA channel, and wait for it to be idle */
947 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
948 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
949 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
950 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
951 1000);
952 }
953 spin_unlock_irqrestore(&priv->lock, flags);
74bcdb33
WYG		 954}
955
956/*
957 * Find first available (lowest unused) Tx Queue, mark it "active".
958 * Called only when finding queue for aggregation.
959 * Should never return anything < 7, because they should already
960 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
961 */
962static int iwlagn_txq_ctx_activate_free(struct iwl_priv *priv)
963{
964 int txq_id;
965
966 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
967 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
968 return txq_id;
969 return -1;
970}
971
832f47e3 972int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif,
619753ff 973 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
74bcdb33
WYG		 974{
975 int sta_id;
976 int tx_fifo;
977 int txq_id;
978 int ret;
979 unsigned long flags;
980 struct iwl_tid_data *tid_data;
981
982 tx_fifo = get_fifo_from_tid(tid);
983 if (unlikely(tx_fifo < 0))
984 return tx_fifo;
985
986 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
619753ff 987 __func__, sta->addr, tid);
74bcdb33 988
619753ff 989 sta_id = iwl_sta_id(sta);
74bcdb33
WYG		 990 if (sta_id == IWL_INVALID_STATION) {
991 IWL_ERR(priv, "Start AGG on invalid station\n");
992 return -ENXIO;
993 }
994 if (unlikely(tid >= MAX_TID_COUNT))
995 return -EINVAL;
996
997 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
998 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
999 return -ENXIO;
1000 }
1001
1002 txq_id = iwlagn_txq_ctx_activate_free(priv);
1003 if (txq_id == -1) {
1004 IWL_ERR(priv, "No free aggregation queue available\n");
1005 return -ENXIO;
1006 }
1007
1008 spin_lock_irqsave(&priv->sta_lock, flags);
1009 tid_data = &priv->stations[sta_id].tid[tid];
1010 *ssn = SEQ_TO_SN(tid_data->seq_number);
1011 tid_data->agg.txq_id = txq_id;
c2845d01 1012 priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(get_ac_from_tid(tid), txq_id);
74bcdb33
WYG		 1013 spin_unlock_irqrestore(&priv->sta_lock, flags);
1014
1015 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1016 sta_id, tid, *ssn);
1017 if (ret)
1018 return ret;
1019
9c5ac091
RC		 1020 spin_lock_irqsave(&priv->sta_lock, flags);
1021 tid_data = &priv->stations[sta_id].tid[tid];
74bcdb33
WYG		 1022 if (tid_data->tfds_in_queue == 0) {
1023 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1024 tid_data->agg.state = IWL_AGG_ON;
619753ff 1025 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
74bcdb33
WYG		 1026 } else {
1027 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1028 tid_data->tfds_in_queue);
1029 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1030 }
9c5ac091 1031 spin_unlock_irqrestore(&priv->sta_lock, flags);
74bcdb33
WYG		 1032 return ret;
1033}
1034
832f47e3 1035int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif,
619753ff 1036 struct ieee80211_sta *sta, u16 tid)
74bcdb33
WYG		 1037{
1038 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1039 struct iwl_tid_data *tid_data;
1040 int write_ptr, read_ptr;
1041 unsigned long flags;
1042
74bcdb33
WYG		 1043 tx_fifo_id = get_fifo_from_tid(tid);
1044 if (unlikely(tx_fifo_id < 0))
1045 return tx_fifo_id;
1046
619753ff 1047 sta_id = iwl_sta_id(sta);
74bcdb33
WYG		 1048
1049 if (sta_id == IWL_INVALID_STATION) {
1050 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1051 return -ENXIO;
1052 }
1053
9c5ac091
RC		 1054 spin_lock_irqsave(&priv->sta_lock, flags);
1055
74bcdb33
WYG		 1056 if (priv->stations[sta_id].tid[tid].agg.state ==
1057 IWL_EMPTYING_HW_QUEUE_ADDBA) {
1058 IWL_DEBUG_HT(priv, "AGG stop before setup done\n");
619753ff 1059 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
74bcdb33 1060 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
9c5ac091 1061 spin_unlock_irqrestore(&priv->sta_lock, flags);
74bcdb33
WYG		 1062 return 0;
1063 }
1064
1065 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1066 IWL_WARN(priv, "Stopping AGG while state not ON or starting\n");
1067
1068 tid_data = &priv->stations[sta_id].tid[tid];
1069 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1070 txq_id = tid_data->agg.txq_id;
1071 write_ptr = priv->txq[txq_id].q.write_ptr;
1072 read_ptr = priv->txq[txq_id].q.read_ptr;
1073
1074 /* The queue is not empty */
1075 if (write_ptr != read_ptr) {
1076 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1077 priv->stations[sta_id].tid[tid].agg.state =
1078 IWL_EMPTYING_HW_QUEUE_DELBA;
9c5ac091 1079 spin_unlock_irqrestore(&priv->sta_lock, flags);
74bcdb33
WYG		 1080 return 0;
1081 }
1082
1083 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1084 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1085
9c5ac091
RC		 1086 /* do not restore/save irqs */
1087 spin_unlock(&priv->sta_lock);
1088 spin_lock(&priv->lock);
1089
74bcdb33
WYG		 1090 /*
1091 * the only reason this call can fail is queue number out of range,
1092 * which can happen if uCode is reloaded and all the station
1093 * information are lost. if it is outside the range, there is no need
1094 * to deactivate the uCode queue, just return "success" to allow
1095 * mac80211 to clean up it own data.
1096 */
1097 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1098 tx_fifo_id);
1099 spin_unlock_irqrestore(&priv->lock, flags);
1100
619753ff 1101 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
74bcdb33
WYG		 1102
1103 return 0;
1104}
1105
1106int iwlagn_txq_check_empty(struct iwl_priv *priv,
1107 int sta_id, u8 tid, int txq_id)
1108{
1109 struct iwl_queue *q = &priv->txq[txq_id].q;
1110 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1111 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1112
9c5ac091
RC		 1113 WARN_ON(!spin_is_locked(&priv->sta_lock));
1114
74bcdb33
WYG		 1115 switch (priv->stations[sta_id].tid[tid].agg.state) {
1116 case IWL_EMPTYING_HW_QUEUE_DELBA:
1117 /* We are reclaiming the last packet of the */
1118 /* aggregated HW queue */
1119 if ((txq_id == tid_data->agg.txq_id) &&
1120 (q->read_ptr == q->write_ptr)) {
1121 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1122 int tx_fifo = get_fifo_from_tid(tid);
1123 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1124 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1125 ssn, tx_fifo);
1126 tid_data->agg.state = IWL_AGG_OFF;
1127 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1128 }
1129 break;
1130 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1131 /* We are reclaiming the last packet of the queue */
1132 if (tid_data->tfds_in_queue == 0) {
1133 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1134 tid_data->agg.state = IWL_AGG_ON;
1135 ieee80211_start_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1136 }
1137 break;
1138 }
9c5ac091 1139
74bcdb33
WYG		 1140 return 0;
1141}
1142
1143static void iwlagn_tx_status(struct iwl_priv *priv, struct sk_buff *skb)
1144{
1145 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1146 struct ieee80211_sta *sta;
1147 struct iwl_station_priv *sta_priv;
1148
1149 sta = ieee80211_find_sta(priv->vif, hdr->addr1);
1150 if (sta) {
1151 sta_priv = (void *)sta->drv_priv;
1152 /* avoid atomic ops if this isn't a client */
1153 if (sta_priv->client &&
1154 atomic_dec_return(&sta_priv->pending_frames) == 0)
1155 ieee80211_sta_block_awake(priv->hw, sta, false);
1156 }
1157
1158 ieee80211_tx_status_irqsafe(priv->hw, skb);
1159}
1160
1161int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1162{
1163 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1164 struct iwl_queue *q = &txq->q;
1165 struct iwl_tx_info *tx_info;
1166 int nfreed = 0;
1167 struct ieee80211_hdr *hdr;
1168
1169 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1170 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1171 "is out of range [0-%d] %d %d.\n", txq_id,
1172 index, q->n_bd, q->write_ptr, q->read_ptr);
1173 return 0;
1174 }
1175
1176 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1177 q->read_ptr != index;
1178 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1179
1180 tx_info = &txq->txb[txq->q.read_ptr];
1181 iwlagn_tx_status(priv, tx_info->skb[0]);
1182
1183 hdr = (struct ieee80211_hdr *)tx_info->skb[0]->data;
1184 if (hdr && ieee80211_is_data_qos(hdr->frame_control))
1185 nfreed++;
1186 tx_info->skb[0] = NULL;
1187
1188 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1189 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1190
1191 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1192 }
1193 return nfreed;
1194}
1195
1196/**
1197 * iwlagn_tx_status_reply_compressed_ba - Update tx status from block-ack
1198 *
1199 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1200 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1201 */
1202static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1203 struct iwl_ht_agg *agg,
1204 struct iwl_compressed_ba_resp *ba_resp)
1205
1206{
1207 int i, sh, ack;
1208 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1209 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1210 u64 bitmap;
1211 int successes = 0;
1212 struct ieee80211_tx_info *info;
1213
1214 if (unlikely(!agg->wait_for_ba)) {
1215 IWL_ERR(priv, "Received BA when not expected\n");
1216 return -EINVAL;
1217 }
1218
1219 /* Mark that the expected block-ack response arrived */
1220 agg->wait_for_ba = 0;
1221 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1222
1223 /* Calculate shift to align block-ack bits with our Tx window bits */
1224 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1225 if (sh < 0) /* tbw something is wrong with indices */
1226 sh += 0x100;
1227
1228 /* don't use 64-bit values for now */
1229 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1230
1231 if (agg->frame_count > (64 - sh)) {
1232 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1233 return -1;
1234 }
1235
1236 /* check for success or failure according to the
1237 * transmitted bitmap and block-ack bitmap */
1238 bitmap &= agg->bitmap;
1239
1240 /* For each frame attempted in aggregation,
1241 * update driver's record of tx frame's status. */
1242 for (i = 0; i < agg->frame_count ; i++) {
1243 ack = bitmap & (1ULL << i);
1244 successes += !!ack;
1245 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1246 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1247 agg->start_idx + i);
1248 }
1249
1250 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1251 memset(&info->status, 0, sizeof(info->status));
1252 info->flags |= IEEE80211_TX_STAT_ACK;
1253 info->flags |= IEEE80211_TX_STAT_AMPDU;
e3a3cd87 1254 info->status.ampdu_ack_len = successes;
e3a3cd87 1255 info->status.ampdu_len = agg->frame_count;
8d801080 1256 iwlagn_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
74bcdb33
WYG		 1257
1258 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1259
1260 return 0;
1261}
1262
8d801080
WYG		 1263/**
1264 * translate ucode response to mac80211 tx status control values
1265 */
1266void iwlagn_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
1267 struct ieee80211_tx_info *info)
1268{
1269 struct ieee80211_tx_rate *r = &info->control.rates[0];
1270
1271 info->antenna_sel_tx =
1272 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
1273 if (rate_n_flags & RATE_MCS_HT_MSK)
1274 r->flags |= IEEE80211_TX_RC_MCS;
1275 if (rate_n_flags & RATE_MCS_GF_MSK)
1276 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
1277 if (rate_n_flags & RATE_MCS_HT40_MSK)
1278 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
1279 if (rate_n_flags & RATE_MCS_DUP_MSK)
1280 r->flags |= IEEE80211_TX_RC_DUP_DATA;
1281 if (rate_n_flags & RATE_MCS_SGI_MSK)
1282 r->flags |= IEEE80211_TX_RC_SHORT_GI;
1283 r->idx = iwlagn_hwrate_to_mac80211_idx(rate_n_flags, info->band);
1284}
1285
74bcdb33
WYG		 1286/**
1287 * iwlagn_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1288 *
1289 * Handles block-acknowledge notification from device, which reports success
1290 * of frames sent via aggregation.
1291 */
1292void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv,
1293 struct iwl_rx_mem_buffer *rxb)
1294{
1295 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1296 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1297 struct iwl_tx_queue *txq = NULL;
1298 struct iwl_ht_agg *agg;
1299 int index;
1300 int sta_id;
1301 int tid;
9c5ac091 1302 unsigned long flags;
74bcdb33
WYG		 1303
1304 /* "flow" corresponds to Tx queue */
1305 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1306
1307 /* "ssn" is start of block-ack Tx window, corresponds to index
1308 * (in Tx queue's circular buffer) of first TFD/frame in window */
1309 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1310
1311 if (scd_flow >= priv->hw_params.max_txq_num) {
1312 IWL_ERR(priv,
1313 "BUG_ON scd_flow is bigger than number of queues\n");
1314 return;
1315 }
1316
1317 txq = &priv->txq[scd_flow];
1318 sta_id = ba_resp->sta_id;
1319 tid = ba_resp->tid;
1320 agg = &priv->stations[sta_id].tid[tid].agg;
1321
1322 /* Find index just before block-ack window */
1323 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1324
9c5ac091 1325 spin_lock_irqsave(&priv->sta_lock, flags);
74bcdb33
WYG		 1326
1327 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1328 "sta_id = %d\n",
1329 agg->wait_for_ba,
1330 (u8 *) &ba_resp->sta_addr_lo32,
1331 ba_resp->sta_id);
1332 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1333 "%d, scd_ssn = %d\n",
1334 ba_resp->tid,
1335 ba_resp->seq_ctl,
1336 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1337 ba_resp->scd_flow,
1338 ba_resp->scd_ssn);
91dd6c27 1339 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx\n",
74bcdb33
WYG		 1340 agg->start_idx,
1341 (unsigned long long)agg->bitmap);
1342
1343 /* Update driver's record of ACK vs. not for each frame in window */
1344 iwlagn_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1345
1346 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1347 * block-ack window (we assume that they've been successfully
1348 * transmitted ... if not, it's too late anyway). */
1349 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1350 /* calculate mac80211 ampdu sw queue to wake */
1351 int freed = iwlagn_tx_queue_reclaim(priv, scd_flow, index);
1352 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
1353
1354 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1355 priv->mac80211_registered &&
1356 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1357 iwl_wake_queue(priv, txq->swq_id);
1358
1359 iwlagn_txq_check_empty(priv, sta_id, tid, scd_flow);
1360 }
9c5ac091
RC		 1361
1362 spin_unlock_irqrestore(&priv->sta_lock, flags);
74bcdb33 1363}
Clone of davem's net-next-2.6 tree