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iwlwifi: fix priv->iw_mode setting when multiple vif are configured
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
CommitLineData
5a6a256e
TW		 1/******************************************************************************
2 *
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
5a6a256e
TW		 28#include <linux/init.h>
29#include <linux/pci.h>
30#include <linux/dma-mapping.h>
31#include <linux/delay.h>
32#include <linux/skbuff.h>
33#include <linux/netdevice.h>
34#include <linux/wireless.h>
35#include <net/mac80211.h>
36#include <linux/etherdevice.h>
37#include <asm/unaligned.h>
38
39#include "iwl-eeprom.h"
3e0d4cb1 40#include "iwl-dev.h"
5a6a256e
TW		 41#include "iwl-core.h"
42#include "iwl-io.h"
e26e47d9 43#include "iwl-sta.h"
5a6a256e
TW		 44#include "iwl-helpers.h"
45#include "iwl-5000-hw.h"
46
47#define IWL5000_UCODE_API "-1"
48
4e062f99
JS		 49#define IWL5000_MODULE_FIRMWARE "iwlwifi-5000" IWL5000_UCODE_API ".ucode"
50
99da1b48
RR		 51static const u16 iwl5000_default_queue_to_tx_fifo[] = {
52 IWL_TX_FIFO_AC3,
53 IWL_TX_FIFO_AC2,
54 IWL_TX_FIFO_AC1,
55 IWL_TX_FIFO_AC0,
56 IWL50_CMD_FIFO_NUM,
57 IWL_TX_FIFO_HCCA_1,
58 IWL_TX_FIFO_HCCA_2
59};
60
46315e01
TW		 61/* FIXME: same implementation as 4965 */
62static int iwl5000_apm_stop_master(struct iwl_priv *priv)
63{
64 int ret = 0;
65 unsigned long flags;
66
67 spin_lock_irqsave(&priv->lock, flags);
68
69 /* set stop master bit */
70 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
71
72 ret = iwl_poll_bit(priv, CSR_RESET,
73 CSR_RESET_REG_FLAG_MASTER_DISABLED,
74 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
75 if (ret < 0)
76 goto out;
77
78out:
79 spin_unlock_irqrestore(&priv->lock, flags);
80 IWL_DEBUG_INFO("stop master\n");
81
82 return ret;
83}
84
85
30d59260
TW		 86static int iwl5000_apm_init(struct iwl_priv *priv)
87{
88 int ret = 0;
89
90 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
92
8f061891
TW		 93 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
94 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
95 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
96
a96a27f9 97 /* Set FH wait threshold to maximum (HW error during stress W/A) */
4c43e0d0
TW		 98 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
99
100 /* enable HAP INTA to move device L1a -> L0s */
101 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
102 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
103
30d59260
TW		 104 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
105
106 /* set "initialization complete" bit to move adapter
107 * D0U* --> D0A* state */
108 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
109
110 /* wait for clock stabilization */
111 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
112 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
113 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
114 if (ret < 0) {
115 IWL_DEBUG_INFO("Failed to init the card\n");
116 return ret;
117 }
118
119 ret = iwl_grab_nic_access(priv);
120 if (ret)
121 return ret;
122
123 /* enable DMA */
8f061891 124 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
30d59260
TW		 125
126 udelay(20);
127
8f061891 128 /* disable L1-Active */
30d59260 129 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
8f061891 130 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
30d59260
TW		 131
132 iwl_release_nic_access(priv);
133
134 return ret;
135}
136
a96a27f9 137/* FIXME: this is identical to 4965 */
f118a91d
TW		 138static void iwl5000_apm_stop(struct iwl_priv *priv)
139{
140 unsigned long flags;
141
46315e01 142 iwl5000_apm_stop_master(priv);
f118a91d
TW		 143
144 spin_lock_irqsave(&priv->lock, flags);
145
146 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
147
148 udelay(10);
149
1d3e6c61
MA		 150 /* clear "init complete" move adapter D0A* --> D0U state */
151 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d
TW		 152
153 spin_unlock_irqrestore(&priv->lock, flags);
154}
155
156
7f066108
TW		 157static int iwl5000_apm_reset(struct iwl_priv *priv)
158{
159 int ret = 0;
160 unsigned long flags;
161
46315e01 162 iwl5000_apm_stop_master(priv);
7f066108
TW		 163
164 spin_lock_irqsave(&priv->lock, flags);
165
166 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
167
168 udelay(10);
169
170
171 /* FIXME: put here L1A -L0S w/a */
172
173 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
174
175 /* set "initialization complete" bit to move adapter
176 * D0U* --> D0A* state */
177 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
178
179 /* wait for clock stabilization */
180 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
182 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
183 if (ret < 0) {
184 IWL_DEBUG_INFO("Failed to init the card\n");
185 goto out;
186 }
187
188 ret = iwl_grab_nic_access(priv);
189 if (ret)
190 goto out;
191
192 /* enable DMA */
193 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
194
195 udelay(20);
196
197 /* disable L1-Active */
198 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
199 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
200
201 iwl_release_nic_access(priv);
202
203out:
204 spin_unlock_irqrestore(&priv->lock, flags);
205
206 return ret;
207}
208
209
5a835353 210static void iwl5000_nic_config(struct iwl_priv *priv)
e86fe9f6
TW		 211{
212 unsigned long flags;
213 u16 radio_cfg;
e7b63581 214 u16 link;
e86fe9f6
TW		 215
216 spin_lock_irqsave(&priv->lock, flags);
217
e7b63581 218 pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
e86fe9f6 219
8f061891 220 /* L1 is enabled by BIOS */
e7b63581 221 if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
a96a27f9 222 /* disable L0S disabled L1A enabled */
8f061891
TW		 223 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
224 else
225 /* L0S enabled L1A disabled */
226 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
e86fe9f6
TW		 227
228 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
229
230 /* write radio config values to register */
231 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
232 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
233 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
234 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
235 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
236
237 /* set CSR_HW_CONFIG_REG for uCode use */
238 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
239 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
240 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
241
4c43e0d0
TW		 242 /* W/A : NIC is stuck in a reset state after Early PCIe power off
243 * (PCIe power is lost before PERST# is asserted),
244 * causing ME FW to lose ownership and not being able to obtain it back.
245 */
2d3db679
TW		 246 iwl_grab_nic_access(priv);
247 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
4c43e0d0
TW		 248 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
249 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
2d3db679 250 iwl_release_nic_access(priv);
4c43e0d0 251
e86fe9f6
TW		 252 spin_unlock_irqrestore(&priv->lock, flags);
253}
254
255
256
25ae3986
TW		 257/*
258 * EEPROM
259 */
260static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
261{
262 u16 offset = 0;
263
264 if ((address & INDIRECT_ADDRESS) == 0)
265 return address;
266
267 switch (address & INDIRECT_TYPE_MSK) {
268 case INDIRECT_HOST:
269 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
270 break;
271 case INDIRECT_GENERAL:
272 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
273 break;
274 case INDIRECT_REGULATORY:
275 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
276 break;
277 case INDIRECT_CALIBRATION:
278 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
279 break;
280 case INDIRECT_PROCESS_ADJST:
281 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
282 break;
283 case INDIRECT_OTHERS:
284 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
285 break;
286 default:
287 IWL_ERROR("illegal indirect type: 0x%X\n",
288 address & INDIRECT_TYPE_MSK);
289 break;
290 }
291
292 /* translate the offset from words to byte */
293 return (address & ADDRESS_MSK) + (offset << 1);
294}
295
0ef2ca67 296static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
f1f69415 297{
f1f69415
TW		 298 struct iwl_eeprom_calib_hdr {
299 u8 version;
300 u8 pa_type;
301 u16 voltage;
302 } *hdr;
303
f1f69415
TW		 304 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
305 EEPROM_5000_CALIB_ALL);
0ef2ca67 306 return hdr->version;
f1f69415
TW		 307
308}
309
33fd5033
EG		 310static void iwl5000_gain_computation(struct iwl_priv *priv,
311 u32 average_noise[NUM_RX_CHAINS],
312 u16 min_average_noise_antenna_i,
313 u32 min_average_noise)
314{
315 int i;
316 s32 delta_g;
317 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
318
319 /* Find Gain Code for the antennas B and C */
320 for (i = 1; i < NUM_RX_CHAINS; i++) {
321 if ((data->disconn_array[i])) {
322 data->delta_gain_code[i] = 0;
323 continue;
324 }
325 delta_g = (1000 * ((s32)average_noise[0] -
326 (s32)average_noise[i])) / 1500;
327 /* bound gain by 2 bits value max, 3rd bit is sign */
328 data->delta_gain_code[i] =
329 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
330
331 if (delta_g < 0)
332 /* set negative sign */
333 data->delta_gain_code[i] |= (1 << 2);
334 }
335
336 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
337 data->delta_gain_code[1], data->delta_gain_code[2]);
338
339 if (!data->radio_write) {
f69f42a6 340 struct iwl_calib_chain_noise_gain_cmd cmd;
33fd5033
EG		 341 memset(&cmd, 0, sizeof(cmd));
342
f69f42a6 343 cmd.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
33fd5033
EG		 344 cmd.delta_gain_1 = data->delta_gain_code[1];
345 cmd.delta_gain_2 = data->delta_gain_code[2];
346 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
347 sizeof(cmd), &cmd, NULL);
348
349 data->radio_write = 1;
350 data->state = IWL_CHAIN_NOISE_CALIBRATED;
351 }
352
353 data->chain_noise_a = 0;
354 data->chain_noise_b = 0;
355 data->chain_noise_c = 0;
356 data->chain_signal_a = 0;
357 data->chain_signal_b = 0;
358 data->chain_signal_c = 0;
359 data->beacon_count = 0;
360}
361
362static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
363{
364 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
365
366 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
f69f42a6 367 struct iwl_calib_chain_noise_reset_cmd cmd;
33fd5033
EG		 368
369 memset(&cmd, 0, sizeof(cmd));
f69f42a6 370 cmd.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
33fd5033
EG		 371 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
372 sizeof(cmd), &cmd))
373 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
374 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
375 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
376 }
377}
378
a326a5d0
EG		 379static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
380 __le32 *tx_flags)
381{
e6a9854b
JB		 382 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
383 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
a326a5d0
EG		 384 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
385 else
386 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
387}
388
33fd5033
EG		 389static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
390 .min_nrg_cck = 95,
391 .max_nrg_cck = 0,
392 .auto_corr_min_ofdm = 90,
393 .auto_corr_min_ofdm_mrc = 170,
394 .auto_corr_min_ofdm_x1 = 120,
395 .auto_corr_min_ofdm_mrc_x1 = 240,
396
397 .auto_corr_max_ofdm = 120,
398 .auto_corr_max_ofdm_mrc = 210,
399 .auto_corr_max_ofdm_x1 = 155,
400 .auto_corr_max_ofdm_mrc_x1 = 290,
401
402 .auto_corr_min_cck = 125,
403 .auto_corr_max_cck = 200,
404 .auto_corr_min_cck_mrc = 170,
405 .auto_corr_max_cck_mrc = 400,
406 .nrg_th_cck = 95,
407 .nrg_th_ofdm = 95,
408};
409
25ae3986
TW		 410static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
411 size_t offset)
412{
413 u32 address = eeprom_indirect_address(priv, offset);
414 BUG_ON(address >= priv->cfg->eeprom_size);
415 return &priv->eeprom[address];
416}
417
7c616cba
TW		 418/*
419 * Calibration
420 */
be5d56ed 421static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
7c616cba 422{
f69f42a6 423 u8 data[sizeof(struct iwl_calib_hdr) +
be5d56ed 424 sizeof(struct iwl_cal_xtal_freq)];
f69f42a6 425 struct iwl_calib_cmd *cmd = (struct iwl_calib_cmd *)data;
be5d56ed 426 struct iwl_cal_xtal_freq *xtal = (struct iwl_cal_xtal_freq *)cmd->data;
7c616cba
TW		 427 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
428
f69f42a6 429 cmd->hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
be5d56ed
TW		 430 xtal->cap_pin1 = (u8)xtal_calib[0];
431 xtal->cap_pin2 = (u8)xtal_calib[1];
f69f42a6 432 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
be5d56ed 433 data, sizeof(data));
7c616cba
TW		 434}
435
7c616cba
TW		 436static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
437{
f69f42a6 438 struct iwl_calib_cfg_cmd calib_cfg_cmd;
7c616cba
TW		 439 struct iwl_host_cmd cmd = {
440 .id = CALIBRATION_CFG_CMD,
f69f42a6 441 .len = sizeof(struct iwl_calib_cfg_cmd),
7c616cba
TW		 442 .data = &calib_cfg_cmd,
443 };
444
445 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
446 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
447 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
448 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
449 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
450
451 return iwl_send_cmd(priv, &cmd);
452}
453
454static void iwl5000_rx_calib_result(struct iwl_priv *priv,
455 struct iwl_rx_mem_buffer *rxb)
456{
457 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
f69f42a6 458 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
7c616cba 459 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
6e21f2c1 460 int index;
7c616cba
TW		 461
462 /* reduce the size of the length field itself */
463 len -= 4;
464
6e21f2c1
TW		 465 /* Define the order in which the results will be sent to the runtime
466 * uCode. iwl_send_calib_results sends them in a row according to their
467 * index. We sort them here */
7c616cba 468 switch (hdr->op_code) {
f69f42a6
TW		 469 case IWL_PHY_CALIBRATE_LO_CMD:
470 index = IWL_CALIB_LO;
7c616cba 471 break;
f69f42a6
TW		 472 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
473 index = IWL_CALIB_TX_IQ;
7c616cba 474 break;
f69f42a6
TW		 475 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
476 index = IWL_CALIB_TX_IQ_PERD;
7c616cba
TW		 477 break;
478 default:
479 IWL_ERROR("Unknown calibration notification %d\n",
480 hdr->op_code);
481 return;
482 }
6e21f2c1 483 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
7c616cba
TW		 484}
485
486static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
487 struct iwl_rx_mem_buffer *rxb)
488{
489 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
490 queue_work(priv->workqueue, &priv->restart);
491}
492
dbb983b7
RR		 493/*
494 * ucode
495 */
496static int iwl5000_load_section(struct iwl_priv *priv,
497 struct fw_desc *image,
498 u32 dst_addr)
499{
500 int ret = 0;
501 unsigned long flags;
502
503 dma_addr_t phy_addr = image->p_addr;
504 u32 byte_cnt = image->len;
505
506 spin_lock_irqsave(&priv->lock, flags);
507 ret = iwl_grab_nic_access(priv);
508 if (ret) {
509 spin_unlock_irqrestore(&priv->lock, flags);
510 return ret;
511 }
512
513 iwl_write_direct32(priv,
514 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
515 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
516
517 iwl_write_direct32(priv,
518 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
519
520 iwl_write_direct32(priv,
521 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
522 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
523
dbb983b7 524 iwl_write_direct32(priv,
f0b9f5cb 525 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
499b1883 526 (iwl_get_dma_hi_addr(phy_addr)
f0b9f5cb
TW		 527 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
528
dbb983b7
RR		 529 iwl_write_direct32(priv,
530 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
531 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
532 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
533 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
534
535 iwl_write_direct32(priv,
536 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
537 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
9c80c502 538 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
dbb983b7
RR		 539 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
540
541 iwl_release_nic_access(priv);
542 spin_unlock_irqrestore(&priv->lock, flags);
543 return 0;
544}
545
546static int iwl5000_load_given_ucode(struct iwl_priv *priv,
547 struct fw_desc *inst_image,
548 struct fw_desc *data_image)
549{
550 int ret = 0;
551
9c80c502 552 ret = iwl5000_load_section(priv, inst_image, RTC_INST_LOWER_BOUND);
dbb983b7
RR		 553 if (ret)
554 return ret;
555
556 IWL_DEBUG_INFO("INST uCode section being loaded...\n");
557 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
9c80c502 558 priv->ucode_write_complete, 5 * HZ);
dbb983b7
RR		 559 if (ret == -ERESTARTSYS) {
560 IWL_ERROR("Could not load the INST uCode section due "
561 "to interrupt\n");
562 return ret;
563 }
564 if (!ret) {
565 IWL_ERROR("Could not load the INST uCode section\n");
566 return -ETIMEDOUT;
567 }
568
569 priv->ucode_write_complete = 0;
570
571 ret = iwl5000_load_section(
572 priv, data_image, RTC_DATA_LOWER_BOUND);
573 if (ret)
574 return ret;
575
576 IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
577
578 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
579 priv->ucode_write_complete, 5 * HZ);
580 if (ret == -ERESTARTSYS) {
581 IWL_ERROR("Could not load the INST uCode section due "
582 "to interrupt\n");
583 return ret;
584 } else if (!ret) {
585 IWL_ERROR("Could not load the DATA uCode section\n");
586 return -ETIMEDOUT;
587 } else
588 ret = 0;
589
590 priv->ucode_write_complete = 0;
591
592 return ret;
593}
594
595static int iwl5000_load_ucode(struct iwl_priv *priv)
596{
597 int ret = 0;
598
599 /* check whether init ucode should be loaded, or rather runtime ucode */
600 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
601 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
602 ret = iwl5000_load_given_ucode(priv,
603 &priv->ucode_init, &priv->ucode_init_data);
604 if (!ret) {
605 IWL_DEBUG_INFO("Init ucode load complete.\n");
606 priv->ucode_type = UCODE_INIT;
607 }
608 } else {
609 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
610 "Loading runtime ucode...\n");
611 ret = iwl5000_load_given_ucode(priv,
612 &priv->ucode_code, &priv->ucode_data);
613 if (!ret) {
614 IWL_DEBUG_INFO("Runtime ucode load complete.\n");
615 priv->ucode_type = UCODE_RT;
616 }
617 }
618
619 return ret;
620}
621
99da1b48
RR		 622static void iwl5000_init_alive_start(struct iwl_priv *priv)
623{
624 int ret = 0;
625
626 /* Check alive response for "valid" sign from uCode */
627 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
628 /* We had an error bringing up the hardware, so take it
629 * all the way back down so we can try again */
630 IWL_DEBUG_INFO("Initialize Alive failed.\n");
631 goto restart;
632 }
633
634 /* initialize uCode was loaded... verify inst image.
635 * This is a paranoid check, because we would not have gotten the
636 * "initialize" alive if code weren't properly loaded. */
637 if (iwl_verify_ucode(priv)) {
638 /* Runtime instruction load was bad;
639 * take it all the way back down so we can try again */
640 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
641 goto restart;
642 }
643
37deb2a0 644 iwl_clear_stations_table(priv);
99da1b48
RR		 645 ret = priv->cfg->ops->lib->alive_notify(priv);
646 if (ret) {
647 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
648 goto restart;
649 }
650
7c616cba 651 iwl5000_send_calib_cfg(priv);
99da1b48
RR		 652 return;
653
654restart:
655 /* real restart (first load init_ucode) */
656 queue_work(priv->workqueue, &priv->restart);
657}
658
659static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
660 int txq_id, u32 index)
661{
662 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
663 (index & 0xff) | (txq_id << 8));
664 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
665}
666
667static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
668 struct iwl_tx_queue *txq,
669 int tx_fifo_id, int scd_retry)
670{
671 int txq_id = txq->q.id;
3fd07a1e 672 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
99da1b48
RR		 673
674 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
675 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
676 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
677 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
678 IWL50_SCD_QUEUE_STTS_REG_MSK);
679
680 txq->sched_retry = scd_retry;
681
682 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
683 active ? "Activate" : "Deactivate",
684 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
685}
686
9636e583
RR		 687static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
688{
689 struct iwl_wimax_coex_cmd coex_cmd;
690
691 memset(&coex_cmd, 0, sizeof(coex_cmd));
692
693 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
694 sizeof(coex_cmd), &coex_cmd);
695}
696
99da1b48
RR		 697static int iwl5000_alive_notify(struct iwl_priv *priv)
698{
699 u32 a;
700 int i = 0;
701 unsigned long flags;
702 int ret;
703
704 spin_lock_irqsave(&priv->lock, flags);
705
706 ret = iwl_grab_nic_access(priv);
707 if (ret) {
708 spin_unlock_irqrestore(&priv->lock, flags);
709 return ret;
710 }
711
712 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
713 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
714 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
715 a += 4)
716 iwl_write_targ_mem(priv, a, 0);
717 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
718 a += 4)
719 iwl_write_targ_mem(priv, a, 0);
720 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
721 iwl_write_targ_mem(priv, a, 0);
722
723 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
724 (priv->shared_phys +
127901ab 725 offsetof(struct iwl5000_shared, queues_bc_tbls)) >> 10);
99da1b48
RR		 726 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
727 IWL50_SCD_QUEUECHAIN_SEL_ALL(
728 priv->hw_params.max_txq_num));
729 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
730
731 /* initiate the queues */
732 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
733 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
734 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
735 iwl_write_targ_mem(priv, priv->scd_base_addr +
736 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
737 iwl_write_targ_mem(priv, priv->scd_base_addr +
738 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
739 sizeof(u32),
740 ((SCD_WIN_SIZE <<
741 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
742 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
743 ((SCD_FRAME_LIMIT <<
744 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
745 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
746 }
747
748 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
da1bc453 749 IWL_MASK(0, priv->hw_params.max_txq_num));
99da1b48 750
da1bc453
TW		 751 /* Activate all Tx DMA/FIFO channels */
752 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
99da1b48
RR		 753
754 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
9c80c502 755
99da1b48
RR		 756 /* map qos queues to fifos one-to-one */
757 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
758 int ac = iwl5000_default_queue_to_tx_fifo[i];
759 iwl_txq_ctx_activate(priv, i);
760 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
761 }
762 /* TODO - need to initialize those FIFOs inside the loop above,
763 * not only mark them as active */
764 iwl_txq_ctx_activate(priv, 4);
765 iwl_txq_ctx_activate(priv, 7);
766 iwl_txq_ctx_activate(priv, 8);
767 iwl_txq_ctx_activate(priv, 9);
768
769 iwl_release_nic_access(priv);
770 spin_unlock_irqrestore(&priv->lock, flags);
771
7c616cba 772
9636e583
RR		 773 iwl5000_send_wimax_coex(priv);
774
be5d56ed
TW		 775 iwl5000_set_Xtal_calib(priv);
776 iwl_send_calib_results(priv);
7c616cba 777
99da1b48
RR		 778 return 0;
779}
780
fdd3e8a4
TW		 781static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
782{
783 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
784 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
785 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
786 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
787 return -EINVAL;
788 }
25ae3986 789
fdd3e8a4 790 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
fdd3e8a4
TW		 791 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
792 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
793 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
794 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
da154e30 795 priv->hw_params.max_bsm_size = 0;
fdd3e8a4
TW		 796 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
797 BIT(IEEE80211_BAND_5GHZ);
33fd5033 798 priv->hw_params.sens = &iwl5000_sensitivity;
fdd3e8a4
TW		 799
800 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
801 case CSR_HW_REV_TYPE_5100:
5d664a41
TW		 802 priv->hw_params.tx_chains_num = 1;
803 priv->hw_params.rx_chains_num = 2;
804 priv->hw_params.valid_tx_ant = ANT_B;
805 priv->hw_params.valid_rx_ant = ANT_AB;
806 break;
fdd3e8a4
TW		 807 case CSR_HW_REV_TYPE_5150:
808 priv->hw_params.tx_chains_num = 1;
809 priv->hw_params.rx_chains_num = 2;
1179f18d
TW		 810 priv->hw_params.valid_tx_ant = ANT_A;
811 priv->hw_params.valid_rx_ant = ANT_AB;
fdd3e8a4
TW		 812 break;
813 case CSR_HW_REV_TYPE_5300:
814 case CSR_HW_REV_TYPE_5350:
815 priv->hw_params.tx_chains_num = 3;
816 priv->hw_params.rx_chains_num = 3;
1179f18d
TW		 817 priv->hw_params.valid_tx_ant = ANT_ABC;
818 priv->hw_params.valid_rx_ant = ANT_ABC;
fdd3e8a4
TW		 819 break;
820 }
c031bf80
EG		 821
822 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
823 case CSR_HW_REV_TYPE_5100:
824 case CSR_HW_REV_TYPE_5300:
d5d7c584
TW		 825 case CSR_HW_REV_TYPE_5350:
826 /* 5X00 and 5350 wants in Celsius */
c031bf80
EG		 827 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
828 break;
829 case CSR_HW_REV_TYPE_5150:
d5d7c584 830 /* 5150 wants in Kelvin */
c031bf80
EG		 831 priv->hw_params.ct_kill_threshold =
832 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
833 break;
834 }
835
be5d56ed
TW		 836 /* Set initial calibration set */
837 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
838 case CSR_HW_REV_TYPE_5100:
839 case CSR_HW_REV_TYPE_5300:
840 case CSR_HW_REV_TYPE_5350:
841 priv->hw_params.calib_init_cfg =
f69f42a6
TW		 842 BIT(IWL_CALIB_XTAL) |
843 BIT(IWL_CALIB_LO) |
844 BIT(IWL_CALIB_TX_IQ) |
845 BIT(IWL_CALIB_TX_IQ_PERD);
be5d56ed
TW		 846 break;
847 case CSR_HW_REV_TYPE_5150:
848 priv->hw_params.calib_init_cfg = 0;
849 break;
850 }
851
852
fdd3e8a4
TW		 853 return 0;
854}
d4100dd9
RR		 855
856static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
857{
858 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
859 sizeof(struct iwl5000_shared),
860 &priv->shared_phys);
861 if (!priv->shared_virt)
862 return -ENOMEM;
863
864 memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
865
d67f5489
RR		 866 priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
867
d4100dd9
RR		 868 return 0;
869}
870
871static void iwl5000_free_shared_mem(struct iwl_priv *priv)
872{
873 if (priv->shared_virt)
874 pci_free_consistent(priv->pci_dev,
875 sizeof(struct iwl5000_shared),
876 priv->shared_virt,
877 priv->shared_phys);
878}
879
d67f5489
RR		 880static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
881{
882 struct iwl5000_shared *s = priv->shared_virt;
883 return le32_to_cpu(s->rb_closed) & 0xFFF;
884}
885
7839fc03
EG		 886/**
887 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
888 */
889static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 890 struct iwl_tx_queue *txq,
7839fc03
EG		 891 u16 byte_cnt)
892{
893 struct iwl5000_shared *shared_data = priv->shared_virt;
127901ab 894 int write_ptr = txq->q.write_ptr;
7839fc03
EG		 895 int txq_id = txq->q.id;
896 u8 sec_ctl = 0;
127901ab
TW		 897 u8 sta_id = 0;
898 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
899 __le16 bc_ent;
7839fc03 900
127901ab 901 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
7839fc03
EG		 902
903 if (txq_id != IWL_CMD_QUEUE_NUM) {
127901ab 904 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
da99c4b6 905 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
7839fc03
EG		 906
907 switch (sec_ctl & TX_CMD_SEC_MSK) {
908 case TX_CMD_SEC_CCM:
909 len += CCMP_MIC_LEN;
910 break;
911 case TX_CMD_SEC_TKIP:
912 len += TKIP_ICV_LEN;
913 break;
914 case TX_CMD_SEC_WEP:
915 len += WEP_IV_LEN + WEP_ICV_LEN;
916 break;
917 }
918 }
919
127901ab 920 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
7839fc03 921
127901ab 922 shared_data->queues_bc_tbls[txq_id].tfd_offset[write_ptr] = bc_ent;
7839fc03 923
127901ab
TW		 924 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
925 shared_data->queues_bc_tbls[txq_id].
926 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
7839fc03
EG		 927}
928
972cf447
TW		 929static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
930 struct iwl_tx_queue *txq)
931{
972cf447 932 struct iwl5000_shared *shared_data = priv->shared_virt;
127901ab
TW		 933 int txq_id = txq->q.id;
934 int read_ptr = txq->q.read_ptr;
935 u8 sta_id = 0;
936 __le16 bc_ent;
937
938 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
972cf447
TW		 939
940 if (txq_id != IWL_CMD_QUEUE_NUM)
127901ab 941 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
972cf447 942
127901ab
TW		 943 bc_ent = cpu_to_le16(1 | (sta_id << 12));
944 shared_data->queues_bc_tbls[txq_id].
945 tfd_offset[read_ptr] = bc_ent;
972cf447 946
127901ab
TW		 947 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
948 shared_data->queues_bc_tbls[txq_id].
949 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
972cf447
TW		 950}
951
e26e47d9
TW		 952static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
953 u16 txq_id)
954{
955 u32 tbl_dw_addr;
956 u32 tbl_dw;
957 u16 scd_q2ratid;
958
959 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
960
961 tbl_dw_addr = priv->scd_base_addr +
962 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
963
964 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
965
966 if (txq_id & 0x1)
967 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
968 else
969 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
970
971 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
972
973 return 0;
974}
975static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
976{
977 /* Simply stop the queue, but don't change any configuration;
978 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
979 iwl_write_prph(priv,
980 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
981 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
982 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
983}
984
985static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
986 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
987{
988 unsigned long flags;
989 int ret;
990 u16 ra_tid;
991
9f17b318
TW		 992 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
993 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
994 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
995 txq_id, IWL50_FIRST_AMPDU_QUEUE,
996 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
997 return -EINVAL;
998 }
e26e47d9
TW		 999
1000 ra_tid = BUILD_RAxTID(sta_id, tid);
1001
1002 /* Modify device's station table to Tx this TID */
1003 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
1004
1005 spin_lock_irqsave(&priv->lock, flags);
1006 ret = iwl_grab_nic_access(priv);
1007 if (ret) {
1008 spin_unlock_irqrestore(&priv->lock, flags);
1009 return ret;
1010 }
1011
1012 /* Stop this Tx queue before configuring it */
1013 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1014
1015 /* Map receiver-address / traffic-ID to this queue */
1016 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1017
1018 /* Set this queue as a chain-building queue */
1019 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1020
1021 /* enable aggregations for the queue */
1022 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1023
1024 /* Place first TFD at index corresponding to start sequence number.
1025 * Assumes that ssn_idx is valid (!= 0xFFF) */
1026 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1027 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1028 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1029
1030 /* Set up Tx window size and frame limit for this queue */
1031 iwl_write_targ_mem(priv, priv->scd_base_addr +
1032 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1033 sizeof(u32),
1034 ((SCD_WIN_SIZE <<
1035 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1036 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1037 ((SCD_FRAME_LIMIT <<
1038 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1039 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1040
1041 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1042
1043 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1044 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1045
1046 iwl_release_nic_access(priv);
1047 spin_unlock_irqrestore(&priv->lock, flags);
1048
1049 return 0;
1050}
1051
1052static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1053 u16 ssn_idx, u8 tx_fifo)
1054{
1055 int ret;
1056
9f17b318
TW		 1057 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1058 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1059 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1060 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1061 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
e26e47d9
TW		 1062 return -EINVAL;
1063 }
1064
1065 ret = iwl_grab_nic_access(priv);
1066 if (ret)
1067 return ret;
1068
1069 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1070
1071 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1072
1073 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1074 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1075 /* supposes that ssn_idx is valid (!= 0xFFF) */
1076 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1077
1078 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1079 iwl_txq_ctx_deactivate(priv, txq_id);
1080 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1081
1082 iwl_release_nic_access(priv);
1083
1084 return 0;
1085}
1086
2469bf2e
TW		 1087static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1088{
1089 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1090 memcpy(data, cmd, size);
1091 return size;
1092}
1093
1094
da1bc453 1095/*
a96a27f9 1096 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
da1bc453
TW		 1097 * must be called under priv->lock and mac access
1098 */
1099static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
5a676bbe 1100{
da1bc453 1101 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
5a676bbe
RR		 1102}
1103
e532fa0e
RR		 1104
1105static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1106{
3ac7f146 1107 return le32_to_cpup((__le32 *)&tx_resp->status +
25a6572c 1108 tx_resp->frame_count) & MAX_SN;
e532fa0e
RR		 1109}
1110
1111static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1112 struct iwl_ht_agg *agg,
1113 struct iwl5000_tx_resp *tx_resp,
25a6572c 1114 int txq_id, u16 start_idx)
e532fa0e
RR		 1115{
1116 u16 status;
1117 struct agg_tx_status *frame_status = &tx_resp->status;
1118 struct ieee80211_tx_info *info = NULL;
1119 struct ieee80211_hdr *hdr = NULL;
e7d326ac 1120 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 1121 int i, sh, idx;
e532fa0e
RR		 1122 u16 seq;
1123
1124 if (agg->wait_for_ba)
1125 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1126
1127 agg->frame_count = tx_resp->frame_count;
1128 agg->start_idx = start_idx;
e7d326ac 1129 agg->rate_n_flags = rate_n_flags;
e532fa0e
RR		 1130 agg->bitmap = 0;
1131
1132 /* # frames attempted by Tx command */
1133 if (agg->frame_count == 1) {
1134 /* Only one frame was attempted; no block-ack will arrive */
1135 status = le16_to_cpu(frame_status[0].status);
25a6572c 1136 idx = start_idx;
e532fa0e
RR		 1137
1138 /* FIXME: code repetition */
1139 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1140 agg->frame_count, agg->start_idx, idx);
1141
1142 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
e6a9854b 1143 info->status.rates[0].count = tx_resp->failure_frame + 1;
e532fa0e
RR		 1144 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1145 info->flags |= iwl_is_tx_success(status)?
3fd07a1e 1146 IEEE80211_TX_STAT_ACK : 0;
e7d326ac
TW		 1147 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1148
e532fa0e
RR		 1149 /* FIXME: code repetition end */
1150
1151 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1152 status & 0xff, tx_resp->failure_frame);
e7d326ac 1153 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
e532fa0e
RR		 1154
1155 agg->wait_for_ba = 0;
1156 } else {
1157 /* Two or more frames were attempted; expect block-ack */
1158 u64 bitmap = 0;
1159 int start = agg->start_idx;
1160
1161 /* Construct bit-map of pending frames within Tx window */
1162 for (i = 0; i < agg->frame_count; i++) {
1163 u16 sc;
1164 status = le16_to_cpu(frame_status[i].status);
1165 seq = le16_to_cpu(frame_status[i].sequence);
1166 idx = SEQ_TO_INDEX(seq);
1167 txq_id = SEQ_TO_QUEUE(seq);
1168
1169 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1170 AGG_TX_STATE_ABORT_MSK))
1171 continue;
1172
1173 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1174 agg->frame_count, txq_id, idx);
1175
1176 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1177
1178 sc = le16_to_cpu(hdr->seq_ctrl);
1179 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1180 IWL_ERROR("BUG_ON idx doesn't match seq control"
1181 " idx=%d, seq_idx=%d, seq=%d\n",
1182 idx, SEQ_TO_SN(sc),
1183 hdr->seq_ctrl);
1184 return -1;
1185 }
1186
1187 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1188 i, idx, SEQ_TO_SN(sc));
1189
1190 sh = idx - start;
1191 if (sh > 64) {
1192 sh = (start - idx) + 0xff;
1193 bitmap = bitmap << sh;
1194 sh = 0;
1195 start = idx;
1196 } else if (sh < -64)
1197 sh = 0xff - (start - idx);
1198 else if (sh < 0) {
1199 sh = start - idx;
1200 start = idx;
1201 bitmap = bitmap << sh;
1202 sh = 0;
1203 }
4aa41f12
EG		 1204 bitmap |= 1ULL << sh;
1205 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
1206 start, (unsigned long long)bitmap);
e532fa0e
RR		 1207 }
1208
1209 agg->bitmap = bitmap;
1210 agg->start_idx = start;
e532fa0e
RR		 1211 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1212 agg->frame_count, agg->start_idx,
1213 (unsigned long long)agg->bitmap);
1214
1215 if (bitmap)
1216 agg->wait_for_ba = 1;
1217 }
1218 return 0;
1219}
1220
1221static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1222 struct iwl_rx_mem_buffer *rxb)
1223{
1224 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1225 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1226 int txq_id = SEQ_TO_QUEUE(sequence);
1227 int index = SEQ_TO_INDEX(sequence);
1228 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1229 struct ieee80211_tx_info *info;
1230 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1231 u32 status = le16_to_cpu(tx_resp->status.status);
3fd07a1e
TW		 1232 int tid;
1233 int sta_id;
1234 int freed;
e532fa0e
RR		 1235
1236 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1237 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1238 "is out of range [0-%d] %d %d\n", txq_id,
1239 index, txq->q.n_bd, txq->q.write_ptr,
1240 txq->q.read_ptr);
1241 return;
1242 }
1243
1244 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1245 memset(&info->status, 0, sizeof(info->status));
1246
3fd07a1e
TW		 1247 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1248 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
e532fa0e
RR		 1249
1250 if (txq->sched_retry) {
1251 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1252 struct iwl_ht_agg *agg = NULL;
1253
e532fa0e
RR		 1254 agg = &priv->stations[sta_id].tid[tid].agg;
1255
25a6572c 1256 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
e532fa0e 1257
3235427e
RR		 1258 /* check if BAR is needed */
1259 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1260 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
e532fa0e
RR		 1261
1262 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
e532fa0e 1263 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
3fd07a1e
TW		 1264 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim "
1265 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1266 scd_ssn , index, txq_id, txq->swq_id);
1267
17b88929 1268 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
e532fa0e
RR		 1269 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1270
3fd07a1e
TW		 1271 if (priv->mac80211_registered &&
1272 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1273 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
e532fa0e
RR		 1274 if (agg->state == IWL_AGG_OFF)
1275 ieee80211_wake_queue(priv->hw, txq_id);
1276 else
3fd07a1e
TW		 1277 ieee80211_wake_queue(priv->hw,
1278 txq->swq_id);
e532fa0e 1279 }
e532fa0e
RR		 1280 }
1281 } else {
3fd07a1e
TW		 1282 BUG_ON(txq_id != txq->swq_id);
1283
e6a9854b 1284 info->status.rates[0].count = tx_resp->failure_frame + 1;
3fd07a1e
TW		 1285 info->flags |= iwl_is_tx_success(status) ?
1286 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 1287 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 1288 le32_to_cpu(tx_resp->rate_n_flags),
1289 info);
1290
3fd07a1e
TW		 1291 IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) rate_n_flags "
1292 "0x%x retries %d\n",
1293 txq_id,
1294 iwl_get_tx_fail_reason(status), status,
1295 le32_to_cpu(tx_resp->rate_n_flags),
1296 tx_resp->failure_frame);
4f85f5b3 1297
3fd07a1e
TW		 1298 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1299 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
e532fa0e 1300 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3fd07a1e
TW		 1301
1302 if (priv->mac80211_registered &&
1303 (iwl_queue_space(&txq->q) > txq->q.low_mark))
e532fa0e 1304 ieee80211_wake_queue(priv->hw, txq_id);
e532fa0e 1305 }
e532fa0e 1306
3fd07a1e
TW		 1307 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1308 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1309
e532fa0e
RR		 1310 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1311 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
1312}
1313
a96a27f9 1314/* Currently 5000 is the superset of everything */
c1adf9fb
GG		 1315static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1316{
1317 return len;
1318}
1319
203566f3
EG		 1320static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1321{
1322 /* in 5000 the tx power calibration is done in uCode */
1323 priv->disable_tx_power_cal = 1;
1324}
1325
b600e4e1
RR		 1326static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1327{
7c616cba
TW		 1328 /* init calibration handlers */
1329 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1330 iwl5000_rx_calib_result;
1331 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1332 iwl5000_rx_calib_complete;
e532fa0e 1333 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
b600e4e1
RR		 1334}
1335
7c616cba 1336
87283cc1
RR		 1337static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1338{
1339 return (addr >= RTC_DATA_LOWER_BOUND) &&
1340 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1341}
1342
fe7a90c2
RR		 1343static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1344{
1345 int ret = 0;
1346 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1347 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1348 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1349
1350 if ((rxon1->flags == rxon2->flags) &&
1351 (rxon1->filter_flags == rxon2->filter_flags) &&
1352 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1353 (rxon1->ofdm_ht_single_stream_basic_rates ==
1354 rxon2->ofdm_ht_single_stream_basic_rates) &&
1355 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1356 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1357 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1358 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1359 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1360 (rxon1->rx_chain == rxon2->rx_chain) &&
1361 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1362 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1363 return 0;
1364 }
1365
1366 rxon_assoc.flags = priv->staging_rxon.flags;
1367 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1368 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1369 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1370 rxon_assoc.reserved1 = 0;
1371 rxon_assoc.reserved2 = 0;
1372 rxon_assoc.reserved3 = 0;
1373 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1374 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1375 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1376 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1377 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1378 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1379 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1380 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1381
1382 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1383 sizeof(rxon_assoc), &rxon_assoc, NULL);
1384 if (ret)
1385 return ret;
1386
1387 return ret;
1388}
630fe9b6
TW		 1389static int iwl5000_send_tx_power(struct iwl_priv *priv)
1390{
1391 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1392
1393 /* half dBm need to multiply */
1394 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
853554ac 1395 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
630fe9b6
TW		 1396 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1397 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1398 sizeof(tx_power_cmd), &tx_power_cmd,
1399 NULL);
1400}
1401
5225640b 1402static void iwl5000_temperature(struct iwl_priv *priv)
8f91aecb
EG		 1403{
1404 /* store temperature from statistics (in Celsius) */
5225640b 1405 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
8f91aecb 1406}
fe7a90c2 1407
caab8f1a
TW		 1408/* Calc max signal level (dBm) among 3 possible receivers */
1409static int iwl5000_calc_rssi(struct iwl_priv *priv,
1410 struct iwl_rx_phy_res *rx_resp)
1411{
1412 /* data from PHY/DSP regarding signal strength, etc.,
1413 * contents are always there, not configurable by host
1414 */
1415 struct iwl5000_non_cfg_phy *ncphy =
1416 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1417 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1418 u8 agc;
1419
1420 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1421 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1422
1423 /* Find max rssi among 3 possible receivers.
1424 * These values are measured by the digital signal processor (DSP).
1425 * They should stay fairly constant even as the signal strength varies,
1426 * if the radio's automatic gain control (AGC) is working right.
1427 * AGC value (see below) will provide the "interesting" info.
1428 */
1429 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1430 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1431 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1432 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1433 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1434
1435 max_rssi = max_t(u32, rssi_a, rssi_b);
1436 max_rssi = max_t(u32, max_rssi, rssi_c);
1437
1438 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1439 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1440
1441 /* dBm = max_rssi dB - agc dB - constant.
1442 * Higher AGC (higher radio gain) means lower signal. */
1443 return max_rssi - agc - IWL_RSSI_OFFSET;
1444}
1445
da8dec29 1446static struct iwl_hcmd_ops iwl5000_hcmd = {
fe7a90c2 1447 .rxon_assoc = iwl5000_send_rxon_assoc,
da8dec29
TW		 1448};
1449
1450static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
c1adf9fb 1451 .get_hcmd_size = iwl5000_get_hcmd_size,
2469bf2e 1452 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
33fd5033
EG		 1453 .gain_computation = iwl5000_gain_computation,
1454 .chain_noise_reset = iwl5000_chain_noise_reset,
a326a5d0 1455 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
caab8f1a 1456 .calc_rssi = iwl5000_calc_rssi,
da8dec29
TW		 1457};
1458
1459static struct iwl_lib_ops iwl5000_lib = {
fdd3e8a4 1460 .set_hw_params = iwl5000_hw_set_hw_params,
d4100dd9
RR		 1461 .alloc_shared_mem = iwl5000_alloc_shared_mem,
1462 .free_shared_mem = iwl5000_free_shared_mem,
d67f5489 1463 .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
7839fc03 1464 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
972cf447 1465 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
da1bc453 1466 .txq_set_sched = iwl5000_txq_set_sched,
e26e47d9
TW		 1467 .txq_agg_enable = iwl5000_txq_agg_enable,
1468 .txq_agg_disable = iwl5000_txq_agg_disable,
b600e4e1 1469 .rx_handler_setup = iwl5000_rx_handler_setup,
203566f3 1470 .setup_deferred_work = iwl5000_setup_deferred_work,
87283cc1 1471 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
dbb983b7 1472 .load_ucode = iwl5000_load_ucode,
99da1b48
RR		 1473 .init_alive_start = iwl5000_init_alive_start,
1474 .alive_notify = iwl5000_alive_notify,
630fe9b6 1475 .send_tx_power = iwl5000_send_tx_power,
8f91aecb 1476 .temperature = iwl5000_temperature,
ca579617 1477 .update_chain_flags = iwl4965_update_chain_flags,
30d59260
TW		 1478 .apm_ops = {
1479 .init = iwl5000_apm_init,
7f066108 1480 .reset = iwl5000_apm_reset,
f118a91d 1481 .stop = iwl5000_apm_stop,
5a835353 1482 .config = iwl5000_nic_config,
88acbd3b 1483 .set_pwr_src = iwl4965_set_pwr_src,
30d59260 1484 },
da8dec29 1485 .eeprom_ops = {
25ae3986
TW		 1486 .regulatory_bands = {
1487 EEPROM_5000_REG_BAND_1_CHANNELS,
1488 EEPROM_5000_REG_BAND_2_CHANNELS,
1489 EEPROM_5000_REG_BAND_3_CHANNELS,
1490 EEPROM_5000_REG_BAND_4_CHANNELS,
1491 EEPROM_5000_REG_BAND_5_CHANNELS,
1492 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1493 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1494 },
da8dec29
TW		 1495 .verify_signature = iwlcore_eeprom_verify_signature,
1496 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1497 .release_semaphore = iwlcore_eeprom_release_semaphore,
0ef2ca67 1498 .calib_version = iwl5000_eeprom_calib_version,
25ae3986 1499 .query_addr = iwl5000_eeprom_query_addr,
da8dec29
TW		 1500 },
1501};
1502
1503static struct iwl_ops iwl5000_ops = {
1504 .lib = &iwl5000_lib,
1505 .hcmd = &iwl5000_hcmd,
1506 .utils = &iwl5000_hcmd_utils,
1507};
1508
5a6a256e
TW		 1509static struct iwl_mod_params iwl50_mod_params = {
1510 .num_of_queues = IWL50_NUM_QUEUES,
9f17b318 1511 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e
TW		 1512 .enable_qos = 1,
1513 .amsdu_size_8K = 1,
3a1081e8 1514 .restart_fw = 1,
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TW		 1515 /* the rest are 0 by default */
1516};
1517
1518
1519struct iwl_cfg iwl5300_agn_cfg = {
1520 .name = "5300AGN",
4e062f99 1521 .fw_name = IWL5000_MODULE_FIRMWARE,
5a6a256e 1522 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1523 .ops = &iwl5000_ops,
25ae3986 1524 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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TW		 1525 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1526 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
5a6a256e
TW		 1527 .mod_params = &iwl50_mod_params,
1528};
1529
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EK		 1530struct iwl_cfg iwl5100_bg_cfg = {
1531 .name = "5100BG",
4e062f99 1532 .fw_name = IWL5000_MODULE_FIRMWARE,
47408639
EK		 1533 .sku = IWL_SKU_G,
1534 .ops = &iwl5000_ops,
1535 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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TW		 1536 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1537 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
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EK		 1538 .mod_params = &iwl50_mod_params,
1539};
1540
1541struct iwl_cfg iwl5100_abg_cfg = {
1542 .name = "5100ABG",
4e062f99 1543 .fw_name = IWL5000_MODULE_FIRMWARE,
47408639
EK		 1544 .sku = IWL_SKU_A|IWL_SKU_G,
1545 .ops = &iwl5000_ops,
1546 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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TW		 1547 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1548 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
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EK		 1549 .mod_params = &iwl50_mod_params,
1550};
1551
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TW		 1552struct iwl_cfg iwl5100_agn_cfg = {
1553 .name = "5100AGN",
4e062f99 1554 .fw_name = IWL5000_MODULE_FIRMWARE,
5a6a256e 1555 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1556 .ops = &iwl5000_ops,
25ae3986 1557 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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TW		 1558 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1559 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
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TW		 1560 .mod_params = &iwl50_mod_params,
1561};
1562
1563struct iwl_cfg iwl5350_agn_cfg = {
1564 .name = "5350AGN",
4e062f99 1565 .fw_name = IWL5000_MODULE_FIRMWARE,
5a6a256e 1566 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1567 .ops = &iwl5000_ops,
25ae3986 1568 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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TW		 1569 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1570 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
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TW		 1571 .mod_params = &iwl50_mod_params,
1572};
1573
4e062f99 1574MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE);
c9f79ed2 1575
5a6a256e
TW		 1576module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1577MODULE_PARM_DESC(disable50,
1578 "manually disable the 50XX radio (default 0 [radio on])");
1579module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1580MODULE_PARM_DESC(swcrypto50,
1581 "using software crypto engine (default 0 [hardware])\n");
1582module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1583MODULE_PARM_DESC(debug50, "50XX debug output mask");
1584module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1585MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1586module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1587MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
49779293
RR		 1588module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1589MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
5a6a256e
TW		 1590module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1591MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
3a1081e8
EK		 1592module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1593MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
Clone of davem's net-next-2.6 tree