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iwlwifi: decrement rx skb counter in scan abort handler
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
CommitLineData
5a6a256e
TW		 1/******************************************************************************
2 *
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/version.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <net/mac80211.h>
37#include <linux/etherdevice.h>
38#include <asm/unaligned.h>
39
40#include "iwl-eeprom.h"
3e0d4cb1 41#include "iwl-dev.h"
5a6a256e
TW		 42#include "iwl-core.h"
43#include "iwl-io.h"
e26e47d9 44#include "iwl-sta.h"
5a6a256e
TW		 45#include "iwl-helpers.h"
46#include "iwl-5000-hw.h"
47
48#define IWL5000_UCODE_API "-1"
49
99da1b48
RR		 50static const u16 iwl5000_default_queue_to_tx_fifo[] = {
51 IWL_TX_FIFO_AC3,
52 IWL_TX_FIFO_AC2,
53 IWL_TX_FIFO_AC1,
54 IWL_TX_FIFO_AC0,
55 IWL50_CMD_FIFO_NUM,
56 IWL_TX_FIFO_HCCA_1,
57 IWL_TX_FIFO_HCCA_2
58};
59
46315e01
TW		 60/* FIXME: same implementation as 4965 */
61static int iwl5000_apm_stop_master(struct iwl_priv *priv)
62{
63 int ret = 0;
64 unsigned long flags;
65
66 spin_lock_irqsave(&priv->lock, flags);
67
68 /* set stop master bit */
69 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
70
71 ret = iwl_poll_bit(priv, CSR_RESET,
72 CSR_RESET_REG_FLAG_MASTER_DISABLED,
73 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
74 if (ret < 0)
75 goto out;
76
77out:
78 spin_unlock_irqrestore(&priv->lock, flags);
79 IWL_DEBUG_INFO("stop master\n");
80
81 return ret;
82}
83
84
30d59260
TW		 85static int iwl5000_apm_init(struct iwl_priv *priv)
86{
87 int ret = 0;
88
89 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
90 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
91
8f061891
TW		 92 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
93 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
94 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
95
4c43e0d0
TW		 96 /* Set FH wait treshold to maximum (HW error during stress W/A) */
97 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
98
99 /* enable HAP INTA to move device L1a -> L0s */
100 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
101 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
102
30d59260
TW		 103 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
104
105 /* set "initialization complete" bit to move adapter
106 * D0U* --> D0A* state */
107 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
108
109 /* wait for clock stabilization */
110 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
111 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
112 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
113 if (ret < 0) {
114 IWL_DEBUG_INFO("Failed to init the card\n");
115 return ret;
116 }
117
118 ret = iwl_grab_nic_access(priv);
119 if (ret)
120 return ret;
121
122 /* enable DMA */
8f061891 123 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
30d59260
TW		 124
125 udelay(20);
126
8f061891 127 /* disable L1-Active */
30d59260 128 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
8f061891 129 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
30d59260
TW		 130
131 iwl_release_nic_access(priv);
132
133 return ret;
134}
135
f118a91d
TW		 136/* FIXME: this is indentical to 4965 */
137static void iwl5000_apm_stop(struct iwl_priv *priv)
138{
139 unsigned long flags;
140
46315e01 141 iwl5000_apm_stop_master(priv);
f118a91d
TW		 142
143 spin_lock_irqsave(&priv->lock, flags);
144
145 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
146
147 udelay(10);
148
149 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
150
151 spin_unlock_irqrestore(&priv->lock, flags);
152}
153
154
7f066108
TW		 155static int iwl5000_apm_reset(struct iwl_priv *priv)
156{
157 int ret = 0;
158 unsigned long flags;
159
46315e01 160 iwl5000_apm_stop_master(priv);
7f066108
TW		 161
162 spin_lock_irqsave(&priv->lock, flags);
163
164 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
165
166 udelay(10);
167
168
169 /* FIXME: put here L1A -L0S w/a */
170
171 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
172
173 /* set "initialization complete" bit to move adapter
174 * D0U* --> D0A* state */
175 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
176
177 /* wait for clock stabilization */
178 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
179 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
180 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
181 if (ret < 0) {
182 IWL_DEBUG_INFO("Failed to init the card\n");
183 goto out;
184 }
185
186 ret = iwl_grab_nic_access(priv);
187 if (ret)
188 goto out;
189
190 /* enable DMA */
191 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
192
193 udelay(20);
194
195 /* disable L1-Active */
196 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
197 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
198
199 iwl_release_nic_access(priv);
200
201out:
202 spin_unlock_irqrestore(&priv->lock, flags);
203
204 return ret;
205}
206
207
5a835353 208static void iwl5000_nic_config(struct iwl_priv *priv)
e86fe9f6
TW		 209{
210 unsigned long flags;
211 u16 radio_cfg;
212 u8 val_link;
213
214 spin_lock_irqsave(&priv->lock, flags);
215
216 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
217
8f061891
TW		 218 /* L1 is enabled by BIOS */
219 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
220 /* diable L0S disabled L1A enabled */
221 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
222 else
223 /* L0S enabled L1A disabled */
224 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
e86fe9f6
TW		 225
226 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
227
228 /* write radio config values to register */
229 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
230 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
231 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
232 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
233 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
234
235 /* set CSR_HW_CONFIG_REG for uCode use */
236 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
237 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
238 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
239
4c43e0d0
TW		 240 /* W/A : NIC is stuck in a reset state after Early PCIe power off
241 * (PCIe power is lost before PERST# is asserted),
242 * causing ME FW to lose ownership and not being able to obtain it back.
243 */
244 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
245 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
246 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
247
e86fe9f6
TW		 248 spin_unlock_irqrestore(&priv->lock, flags);
249}
250
251
252
25ae3986
TW		 253/*
254 * EEPROM
255 */
256static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
257{
258 u16 offset = 0;
259
260 if ((address & INDIRECT_ADDRESS) == 0)
261 return address;
262
263 switch (address & INDIRECT_TYPE_MSK) {
264 case INDIRECT_HOST:
265 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
266 break;
267 case INDIRECT_GENERAL:
268 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
269 break;
270 case INDIRECT_REGULATORY:
271 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
272 break;
273 case INDIRECT_CALIBRATION:
274 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
275 break;
276 case INDIRECT_PROCESS_ADJST:
277 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
278 break;
279 case INDIRECT_OTHERS:
280 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
281 break;
282 default:
283 IWL_ERROR("illegal indirect type: 0x%X\n",
284 address & INDIRECT_TYPE_MSK);
285 break;
286 }
287
288 /* translate the offset from words to byte */
289 return (address & ADDRESS_MSK) + (offset << 1);
290}
291
f1f69415
TW		 292static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
293{
294 u16 eeprom_ver;
295 struct iwl_eeprom_calib_hdr {
296 u8 version;
297 u8 pa_type;
298 u16 voltage;
299 } *hdr;
300
301 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
302
303 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
304 EEPROM_5000_CALIB_ALL);
305
306 if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
307 hdr->version < EEPROM_5000_TX_POWER_VERSION)
308 goto err;
309
310 return 0;
311err:
312 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
313 eeprom_ver, EEPROM_5000_EEPROM_VERSION,
314 hdr->version, EEPROM_5000_TX_POWER_VERSION);
315 return -EINVAL;
316
317}
318
33fd5033
EG		 319static void iwl5000_gain_computation(struct iwl_priv *priv,
320 u32 average_noise[NUM_RX_CHAINS],
321 u16 min_average_noise_antenna_i,
322 u32 min_average_noise)
323{
324 int i;
325 s32 delta_g;
326 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
327
328 /* Find Gain Code for the antennas B and C */
329 for (i = 1; i < NUM_RX_CHAINS; i++) {
330 if ((data->disconn_array[i])) {
331 data->delta_gain_code[i] = 0;
332 continue;
333 }
334 delta_g = (1000 * ((s32)average_noise[0] -
335 (s32)average_noise[i])) / 1500;
336 /* bound gain by 2 bits value max, 3rd bit is sign */
337 data->delta_gain_code[i] =
338 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
339
340 if (delta_g < 0)
341 /* set negative sign */
342 data->delta_gain_code[i] |= (1 << 2);
343 }
344
345 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
346 data->delta_gain_code[1], data->delta_gain_code[2]);
347
348 if (!data->radio_write) {
349 struct iwl5000_calibration_chain_noise_gain_cmd cmd;
350 memset(&cmd, 0, sizeof(cmd));
351
352 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
353 cmd.delta_gain_1 = data->delta_gain_code[1];
354 cmd.delta_gain_2 = data->delta_gain_code[2];
355 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
356 sizeof(cmd), &cmd, NULL);
357
358 data->radio_write = 1;
359 data->state = IWL_CHAIN_NOISE_CALIBRATED;
360 }
361
362 data->chain_noise_a = 0;
363 data->chain_noise_b = 0;
364 data->chain_noise_c = 0;
365 data->chain_signal_a = 0;
366 data->chain_signal_b = 0;
367 data->chain_signal_c = 0;
368 data->beacon_count = 0;
369}
370
371static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
372{
373 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
374
375 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
376 struct iwl5000_calibration_chain_noise_reset_cmd cmd;
377
378 memset(&cmd, 0, sizeof(cmd));
379 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
380 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
381 sizeof(cmd), &cmd))
382 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
383 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
384 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
385 }
386}
387
a326a5d0
EG		 388static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
389 __le32 *tx_flags)
390{
391 if ((info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) ||
392 (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT))
393 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
394 else
395 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
396}
397
33fd5033
EG		 398static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
399 .min_nrg_cck = 95,
400 .max_nrg_cck = 0,
401 .auto_corr_min_ofdm = 90,
402 .auto_corr_min_ofdm_mrc = 170,
403 .auto_corr_min_ofdm_x1 = 120,
404 .auto_corr_min_ofdm_mrc_x1 = 240,
405
406 .auto_corr_max_ofdm = 120,
407 .auto_corr_max_ofdm_mrc = 210,
408 .auto_corr_max_ofdm_x1 = 155,
409 .auto_corr_max_ofdm_mrc_x1 = 290,
410
411 .auto_corr_min_cck = 125,
412 .auto_corr_max_cck = 200,
413 .auto_corr_min_cck_mrc = 170,
414 .auto_corr_max_cck_mrc = 400,
415 .nrg_th_cck = 95,
416 .nrg_th_ofdm = 95,
417};
418
25ae3986
TW		 419static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
420 size_t offset)
421{
422 u32 address = eeprom_indirect_address(priv, offset);
423 BUG_ON(address >= priv->cfg->eeprom_size);
424 return &priv->eeprom[address];
425}
426
7c616cba
TW		 427/*
428 * Calibration
429 */
430static int iwl5000_send_Xtal_calib(struct iwl_priv *priv)
431{
432 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
433
434 struct iwl5000_calibration cal_cmd = {
435 .op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD,
436 .data = {
437 (u8)xtal_calib[0],
438 (u8)xtal_calib[1],
439 }
440 };
441
442 return iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
443 sizeof(cal_cmd), &cal_cmd);
444}
445
446static int iwl5000_send_calib_results(struct iwl_priv *priv)
447{
448 int ret = 0;
449
d2f18bfd
EG		 450 struct iwl_host_cmd hcmd = {
451 .id = REPLY_PHY_CALIBRATION_CMD,
452 .meta.flags = CMD_SIZE_HUGE,
453 };
7c616cba 454
d2f18bfd
EG		 455 if (priv->calib_results.lo_res) {
456 hcmd.len = priv->calib_results.lo_res_len;
457 hcmd.data = priv->calib_results.lo_res;
458 ret = iwl_send_cmd_sync(priv, &hcmd);
7c616cba 459
d2f18bfd
EG		 460 if (ret)
461 goto err;
462 }
7c616cba 463
d2f18bfd
EG		 464 if (priv->calib_results.tx_iq_res) {
465 hcmd.len = priv->calib_results.tx_iq_res_len;
466 hcmd.data = priv->calib_results.tx_iq_res;
467 ret = iwl_send_cmd_sync(priv, &hcmd);
7c616cba 468
d2f18bfd
EG		 469 if (ret)
470 goto err;
471 }
472
473 if (priv->calib_results.tx_iq_perd_res) {
474 hcmd.len = priv->calib_results.tx_iq_perd_res_len;
475 hcmd.data = priv->calib_results.tx_iq_perd_res;
476 ret = iwl_send_cmd_sync(priv, &hcmd);
477
478 if (ret)
479 goto err;
480 }
7c616cba
TW		 481
482 return 0;
483err:
484 IWL_ERROR("Error %d\n", ret);
485 return ret;
486}
487
488static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
489{
490 struct iwl5000_calib_cfg_cmd calib_cfg_cmd;
491 struct iwl_host_cmd cmd = {
492 .id = CALIBRATION_CFG_CMD,
493 .len = sizeof(struct iwl5000_calib_cfg_cmd),
494 .data = &calib_cfg_cmd,
495 };
496
497 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
498 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
499 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
500 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
501 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
502
503 return iwl_send_cmd(priv, &cmd);
504}
505
506static void iwl5000_rx_calib_result(struct iwl_priv *priv,
507 struct iwl_rx_mem_buffer *rxb)
508{
509 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
510 struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw;
511 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
512
513 iwl_free_calib_results(priv);
514
515 /* reduce the size of the length field itself */
516 len -= 4;
517
518 switch (hdr->op_code) {
519 case IWL5000_PHY_CALIBRATE_LO_CMD:
520 priv->calib_results.lo_res = kzalloc(len, GFP_ATOMIC);
521 priv->calib_results.lo_res_len = len;
522 memcpy(priv->calib_results.lo_res, pkt->u.raw, len);
523 break;
524 case IWL5000_PHY_CALIBRATE_TX_IQ_CMD:
525 priv->calib_results.tx_iq_res = kzalloc(len, GFP_ATOMIC);
526 priv->calib_results.tx_iq_res_len = len;
527 memcpy(priv->calib_results.tx_iq_res, pkt->u.raw, len);
528 break;
529 case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD:
530 priv->calib_results.tx_iq_perd_res = kzalloc(len, GFP_ATOMIC);
531 priv->calib_results.tx_iq_perd_res_len = len;
532 memcpy(priv->calib_results.tx_iq_perd_res, pkt->u.raw, len);
533 break;
534 default:
535 IWL_ERROR("Unknown calibration notification %d\n",
536 hdr->op_code);
537 return;
538 }
539}
540
541static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
542 struct iwl_rx_mem_buffer *rxb)
543{
544 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
545 queue_work(priv->workqueue, &priv->restart);
546}
547
dbb983b7
RR		 548/*
549 * ucode
550 */
551static int iwl5000_load_section(struct iwl_priv *priv,
552 struct fw_desc *image,
553 u32 dst_addr)
554{
555 int ret = 0;
556 unsigned long flags;
557
558 dma_addr_t phy_addr = image->p_addr;
559 u32 byte_cnt = image->len;
560
561 spin_lock_irqsave(&priv->lock, flags);
562 ret = iwl_grab_nic_access(priv);
563 if (ret) {
564 spin_unlock_irqrestore(&priv->lock, flags);
565 return ret;
566 }
567
568 iwl_write_direct32(priv,
569 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
570 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
571
572 iwl_write_direct32(priv,
573 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
574
575 iwl_write_direct32(priv,
576 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
577 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
578
579 /* FIME: write the MSB of the phy_addr in CTRL1
580 * iwl_write_direct32(priv,
581 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL),
582 ((phy_addr & MSB_MSK)
583 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count);
584 */
585 iwl_write_direct32(priv,
586 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt);
587 iwl_write_direct32(priv,
588 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
589 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
590 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
591 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
592
593 iwl_write_direct32(priv,
594 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
595 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
596 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
597 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
598
599 iwl_release_nic_access(priv);
600 spin_unlock_irqrestore(&priv->lock, flags);
601 return 0;
602}
603
604static int iwl5000_load_given_ucode(struct iwl_priv *priv,
605 struct fw_desc *inst_image,
606 struct fw_desc *data_image)
607{
608 int ret = 0;
609
610 ret = iwl5000_load_section(
611 priv, inst_image, RTC_INST_LOWER_BOUND);
612 if (ret)
613 return ret;
614
615 IWL_DEBUG_INFO("INST uCode section being loaded...\n");
616 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
617 priv->ucode_write_complete, 5 * HZ);
618 if (ret == -ERESTARTSYS) {
619 IWL_ERROR("Could not load the INST uCode section due "
620 "to interrupt\n");
621 return ret;
622 }
623 if (!ret) {
624 IWL_ERROR("Could not load the INST uCode section\n");
625 return -ETIMEDOUT;
626 }
627
628 priv->ucode_write_complete = 0;
629
630 ret = iwl5000_load_section(
631 priv, data_image, RTC_DATA_LOWER_BOUND);
632 if (ret)
633 return ret;
634
635 IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
636
637 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
638 priv->ucode_write_complete, 5 * HZ);
639 if (ret == -ERESTARTSYS) {
640 IWL_ERROR("Could not load the INST uCode section due "
641 "to interrupt\n");
642 return ret;
643 } else if (!ret) {
644 IWL_ERROR("Could not load the DATA uCode section\n");
645 return -ETIMEDOUT;
646 } else
647 ret = 0;
648
649 priv->ucode_write_complete = 0;
650
651 return ret;
652}
653
654static int iwl5000_load_ucode(struct iwl_priv *priv)
655{
656 int ret = 0;
657
658 /* check whether init ucode should be loaded, or rather runtime ucode */
659 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
660 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
661 ret = iwl5000_load_given_ucode(priv,
662 &priv->ucode_init, &priv->ucode_init_data);
663 if (!ret) {
664 IWL_DEBUG_INFO("Init ucode load complete.\n");
665 priv->ucode_type = UCODE_INIT;
666 }
667 } else {
668 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
669 "Loading runtime ucode...\n");
670 ret = iwl5000_load_given_ucode(priv,
671 &priv->ucode_code, &priv->ucode_data);
672 if (!ret) {
673 IWL_DEBUG_INFO("Runtime ucode load complete.\n");
674 priv->ucode_type = UCODE_RT;
675 }
676 }
677
678 return ret;
679}
680
99da1b48
RR		 681static void iwl5000_init_alive_start(struct iwl_priv *priv)
682{
683 int ret = 0;
684
685 /* Check alive response for "valid" sign from uCode */
686 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
687 /* We had an error bringing up the hardware, so take it
688 * all the way back down so we can try again */
689 IWL_DEBUG_INFO("Initialize Alive failed.\n");
690 goto restart;
691 }
692
693 /* initialize uCode was loaded... verify inst image.
694 * This is a paranoid check, because we would not have gotten the
695 * "initialize" alive if code weren't properly loaded. */
696 if (iwl_verify_ucode(priv)) {
697 /* Runtime instruction load was bad;
698 * take it all the way back down so we can try again */
699 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
700 goto restart;
701 }
702
37deb2a0 703 iwl_clear_stations_table(priv);
99da1b48
RR		 704 ret = priv->cfg->ops->lib->alive_notify(priv);
705 if (ret) {
706 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
707 goto restart;
708 }
709
7c616cba 710 iwl5000_send_calib_cfg(priv);
99da1b48
RR		 711 return;
712
713restart:
714 /* real restart (first load init_ucode) */
715 queue_work(priv->workqueue, &priv->restart);
716}
717
718static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
719 int txq_id, u32 index)
720{
721 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
722 (index & 0xff) | (txq_id << 8));
723 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
724}
725
726static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
727 struct iwl_tx_queue *txq,
728 int tx_fifo_id, int scd_retry)
729{
730 int txq_id = txq->q.id;
731 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
732
733 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
734 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
735 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
736 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
737 IWL50_SCD_QUEUE_STTS_REG_MSK);
738
739 txq->sched_retry = scd_retry;
740
741 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
742 active ? "Activate" : "Deactivate",
743 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
744}
745
9636e583
RR		 746static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
747{
748 struct iwl_wimax_coex_cmd coex_cmd;
749
750 memset(&coex_cmd, 0, sizeof(coex_cmd));
751
752 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
753 sizeof(coex_cmd), &coex_cmd);
754}
755
99da1b48
RR		 756static int iwl5000_alive_notify(struct iwl_priv *priv)
757{
758 u32 a;
759 int i = 0;
760 unsigned long flags;
761 int ret;
762
763 spin_lock_irqsave(&priv->lock, flags);
764
765 ret = iwl_grab_nic_access(priv);
766 if (ret) {
767 spin_unlock_irqrestore(&priv->lock, flags);
768 return ret;
769 }
770
771 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
772 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
773 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
774 a += 4)
775 iwl_write_targ_mem(priv, a, 0);
776 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
777 a += 4)
778 iwl_write_targ_mem(priv, a, 0);
779 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
780 iwl_write_targ_mem(priv, a, 0);
781
782 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
783 (priv->shared_phys +
784 offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
785 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
786 IWL50_SCD_QUEUECHAIN_SEL_ALL(
787 priv->hw_params.max_txq_num));
788 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
789
790 /* initiate the queues */
791 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
792 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
793 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
794 iwl_write_targ_mem(priv, priv->scd_base_addr +
795 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
796 iwl_write_targ_mem(priv, priv->scd_base_addr +
797 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
798 sizeof(u32),
799 ((SCD_WIN_SIZE <<
800 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
801 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
802 ((SCD_FRAME_LIMIT <<
803 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
804 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
805 }
806
807 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
da1bc453 808 IWL_MASK(0, priv->hw_params.max_txq_num));
99da1b48 809
da1bc453
TW		 810 /* Activate all Tx DMA/FIFO channels */
811 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
99da1b48
RR		 812
813 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
814 /* map qos queues to fifos one-to-one */
815 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
816 int ac = iwl5000_default_queue_to_tx_fifo[i];
817 iwl_txq_ctx_activate(priv, i);
818 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
819 }
820 /* TODO - need to initialize those FIFOs inside the loop above,
821 * not only mark them as active */
822 iwl_txq_ctx_activate(priv, 4);
823 iwl_txq_ctx_activate(priv, 7);
824 iwl_txq_ctx_activate(priv, 8);
825 iwl_txq_ctx_activate(priv, 9);
826
827 iwl_release_nic_access(priv);
828 spin_unlock_irqrestore(&priv->lock, flags);
829
7c616cba 830
9636e583
RR		 831 iwl5000_send_wimax_coex(priv);
832
7c616cba
TW		 833 iwl5000_send_Xtal_calib(priv);
834
0a078ffa 835 if (priv->ucode_type == UCODE_RT)
7c616cba
TW		 836 iwl5000_send_calib_results(priv);
837
99da1b48
RR		 838 return 0;
839}
840
fdd3e8a4
TW		 841static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
842{
843 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
844 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
845 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
846 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
847 return -EINVAL;
848 }
25ae3986 849
fdd3e8a4 850 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
7f3e4bb6 851 priv->hw_params.first_ampdu_q = IWL50_FIRST_AMPDU_QUEUE;
fdd3e8a4
TW		 852 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
853 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
854 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
855 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
da154e30 856 priv->hw_params.max_bsm_size = 0;
fdd3e8a4
TW		 857 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
858 BIT(IEEE80211_BAND_5GHZ);
33fd5033 859 priv->hw_params.sens = &iwl5000_sensitivity;
fdd3e8a4
TW		 860
861 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
862 case CSR_HW_REV_TYPE_5100:
863 case CSR_HW_REV_TYPE_5150:
864 priv->hw_params.tx_chains_num = 1;
865 priv->hw_params.rx_chains_num = 2;
866 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
1179f18d
TW		 867 priv->hw_params.valid_tx_ant = ANT_A;
868 priv->hw_params.valid_rx_ant = ANT_AB;
fdd3e8a4
TW		 869 break;
870 case CSR_HW_REV_TYPE_5300:
871 case CSR_HW_REV_TYPE_5350:
872 priv->hw_params.tx_chains_num = 3;
873 priv->hw_params.rx_chains_num = 3;
1179f18d
TW		 874 priv->hw_params.valid_tx_ant = ANT_ABC;
875 priv->hw_params.valid_rx_ant = ANT_ABC;
fdd3e8a4
TW		 876 break;
877 }
c031bf80
EG		 878
879 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
880 case CSR_HW_REV_TYPE_5100:
881 case CSR_HW_REV_TYPE_5300:
882 /* 5X00 wants in Celsius */
883 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
884 break;
885 case CSR_HW_REV_TYPE_5150:
886 case CSR_HW_REV_TYPE_5350:
887 /* 5X50 wants in Kelvin */
888 priv->hw_params.ct_kill_threshold =
889 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
890 break;
891 }
892
fdd3e8a4
TW		 893 return 0;
894}
d4100dd9
RR		 895
896static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
897{
898 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
899 sizeof(struct iwl5000_shared),
900 &priv->shared_phys);
901 if (!priv->shared_virt)
902 return -ENOMEM;
903
904 memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
905
d67f5489
RR		 906 priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
907
d4100dd9
RR		 908 return 0;
909}
910
911static void iwl5000_free_shared_mem(struct iwl_priv *priv)
912{
913 if (priv->shared_virt)
914 pci_free_consistent(priv->pci_dev,
915 sizeof(struct iwl5000_shared),
916 priv->shared_virt,
917 priv->shared_phys);
918}
919
d67f5489
RR		 920static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
921{
922 struct iwl5000_shared *s = priv->shared_virt;
923 return le32_to_cpu(s->rb_closed) & 0xFFF;
924}
925
7839fc03
EG		 926/**
927 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
928 */
929static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 930 struct iwl_tx_queue *txq,
7839fc03
EG		 931 u16 byte_cnt)
932{
933 struct iwl5000_shared *shared_data = priv->shared_virt;
934 int txq_id = txq->q.id;
935 u8 sec_ctl = 0;
936 u8 sta = 0;
937 int len;
938
939 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
940
941 if (txq_id != IWL_CMD_QUEUE_NUM) {
da99c4b6
GG		 942 sta = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
943 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
7839fc03
EG		 944
945 switch (sec_ctl & TX_CMD_SEC_MSK) {
946 case TX_CMD_SEC_CCM:
947 len += CCMP_MIC_LEN;
948 break;
949 case TX_CMD_SEC_TKIP:
950 len += TKIP_ICV_LEN;
951 break;
952 case TX_CMD_SEC_WEP:
953 len += WEP_IV_LEN + WEP_ICV_LEN;
954 break;
955 }
956 }
957
958 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
959 tfd_offset[txq->q.write_ptr], byte_cnt, len);
960
961 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
962 tfd_offset[txq->q.write_ptr], sta_id, sta);
963
964 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
965 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
966 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
967 byte_cnt, len);
968 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
969 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
970 sta_id, sta);
971 }
972}
973
972cf447
TW		 974static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
975 struct iwl_tx_queue *txq)
976{
977 int txq_id = txq->q.id;
978 struct iwl5000_shared *shared_data = priv->shared_virt;
979 u8 sta = 0;
980
981 if (txq_id != IWL_CMD_QUEUE_NUM)
da99c4b6 982 sta = txq->cmd[txq->q.read_ptr]->cmd.tx.sta_id;
972cf447
TW		 983
984 shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr].
985 val = cpu_to_le16(1 | (sta << 12));
986
987 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
988 shared_data->queues_byte_cnt_tbls[txq_id].
989 tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr].
990 val = cpu_to_le16(1 | (sta << 12));
991 }
992}
993
e26e47d9
TW		 994static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
995 u16 txq_id)
996{
997 u32 tbl_dw_addr;
998 u32 tbl_dw;
999 u16 scd_q2ratid;
1000
1001 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1002
1003 tbl_dw_addr = priv->scd_base_addr +
1004 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
1005
1006 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
1007
1008 if (txq_id & 0x1)
1009 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1010 else
1011 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1012
1013 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
1014
1015 return 0;
1016}
1017static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
1018{
1019 /* Simply stop the queue, but don't change any configuration;
1020 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1021 iwl_write_prph(priv,
1022 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
1023 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1024 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1025}
1026
1027static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1028 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1029{
1030 unsigned long flags;
1031 int ret;
1032 u16 ra_tid;
1033
9f17b318
TW		 1034 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1035 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1036 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1037 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1038 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1039 return -EINVAL;
1040 }
e26e47d9
TW		 1041
1042 ra_tid = BUILD_RAxTID(sta_id, tid);
1043
1044 /* Modify device's station table to Tx this TID */
1045 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
1046
1047 spin_lock_irqsave(&priv->lock, flags);
1048 ret = iwl_grab_nic_access(priv);
1049 if (ret) {
1050 spin_unlock_irqrestore(&priv->lock, flags);
1051 return ret;
1052 }
1053
1054 /* Stop this Tx queue before configuring it */
1055 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1056
1057 /* Map receiver-address / traffic-ID to this queue */
1058 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1059
1060 /* Set this queue as a chain-building queue */
1061 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1062
1063 /* enable aggregations for the queue */
1064 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1065
1066 /* Place first TFD at index corresponding to start sequence number.
1067 * Assumes that ssn_idx is valid (!= 0xFFF) */
1068 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1069 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1070 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1071
1072 /* Set up Tx window size and frame limit for this queue */
1073 iwl_write_targ_mem(priv, priv->scd_base_addr +
1074 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1075 sizeof(u32),
1076 ((SCD_WIN_SIZE <<
1077 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1078 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1079 ((SCD_FRAME_LIMIT <<
1080 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1081 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1082
1083 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1084
1085 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1086 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1087
1088 iwl_release_nic_access(priv);
1089 spin_unlock_irqrestore(&priv->lock, flags);
1090
1091 return 0;
1092}
1093
1094static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1095 u16 ssn_idx, u8 tx_fifo)
1096{
1097 int ret;
1098
9f17b318
TW		 1099 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1100 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1101 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1102 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1103 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
e26e47d9
TW		 1104 return -EINVAL;
1105 }
1106
1107 ret = iwl_grab_nic_access(priv);
1108 if (ret)
1109 return ret;
1110
1111 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1112
1113 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1114
1115 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1116 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1117 /* supposes that ssn_idx is valid (!= 0xFFF) */
1118 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1119
1120 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1121 iwl_txq_ctx_deactivate(priv, txq_id);
1122 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1123
1124 iwl_release_nic_access(priv);
1125
1126 return 0;
1127}
1128
2469bf2e
TW		 1129static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1130{
1131 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1132 memcpy(data, cmd, size);
1133 return size;
1134}
1135
1136
da1bc453
TW		 1137/*
1138 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
1139 * must be called under priv->lock and mac access
1140 */
1141static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
5a676bbe 1142{
da1bc453 1143 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
5a676bbe
RR		 1144}
1145
e532fa0e
RR		 1146
1147static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1148{
3ac7f146 1149 return le32_to_cpup((__le32 *)&tx_resp->status +
25a6572c 1150 tx_resp->frame_count) & MAX_SN;
e532fa0e
RR		 1151}
1152
1153static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1154 struct iwl_ht_agg *agg,
1155 struct iwl5000_tx_resp *tx_resp,
25a6572c 1156 int txq_id, u16 start_idx)
e532fa0e
RR		 1157{
1158 u16 status;
1159 struct agg_tx_status *frame_status = &tx_resp->status;
1160 struct ieee80211_tx_info *info = NULL;
1161 struct ieee80211_hdr *hdr = NULL;
e7d326ac 1162 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 1163 int i, sh, idx;
e532fa0e
RR		 1164 u16 seq;
1165
1166 if (agg->wait_for_ba)
1167 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1168
1169 agg->frame_count = tx_resp->frame_count;
1170 agg->start_idx = start_idx;
e7d326ac 1171 agg->rate_n_flags = rate_n_flags;
e532fa0e
RR		 1172 agg->bitmap = 0;
1173
1174 /* # frames attempted by Tx command */
1175 if (agg->frame_count == 1) {
1176 /* Only one frame was attempted; no block-ack will arrive */
1177 status = le16_to_cpu(frame_status[0].status);
25a6572c 1178 idx = start_idx;
e532fa0e
RR		 1179
1180 /* FIXME: code repetition */
1181 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1182 agg->frame_count, agg->start_idx, idx);
1183
1184 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1185 info->status.retry_count = tx_resp->failure_frame;
1186 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1187 info->flags |= iwl_is_tx_success(status)?
1188 IEEE80211_TX_STAT_ACK : 0;
e7d326ac
TW		 1189 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1190
e532fa0e
RR		 1191 /* FIXME: code repetition end */
1192
1193 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1194 status & 0xff, tx_resp->failure_frame);
e7d326ac 1195 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
e532fa0e
RR		 1196
1197 agg->wait_for_ba = 0;
1198 } else {
1199 /* Two or more frames were attempted; expect block-ack */
1200 u64 bitmap = 0;
1201 int start = agg->start_idx;
1202
1203 /* Construct bit-map of pending frames within Tx window */
1204 for (i = 0; i < agg->frame_count; i++) {
1205 u16 sc;
1206 status = le16_to_cpu(frame_status[i].status);
1207 seq = le16_to_cpu(frame_status[i].sequence);
1208 idx = SEQ_TO_INDEX(seq);
1209 txq_id = SEQ_TO_QUEUE(seq);
1210
1211 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1212 AGG_TX_STATE_ABORT_MSK))
1213 continue;
1214
1215 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1216 agg->frame_count, txq_id, idx);
1217
1218 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1219
1220 sc = le16_to_cpu(hdr->seq_ctrl);
1221 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1222 IWL_ERROR("BUG_ON idx doesn't match seq control"
1223 " idx=%d, seq_idx=%d, seq=%d\n",
1224 idx, SEQ_TO_SN(sc),
1225 hdr->seq_ctrl);
1226 return -1;
1227 }
1228
1229 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1230 i, idx, SEQ_TO_SN(sc));
1231
1232 sh = idx - start;
1233 if (sh > 64) {
1234 sh = (start - idx) + 0xff;
1235 bitmap = bitmap << sh;
1236 sh = 0;
1237 start = idx;
1238 } else if (sh < -64)
1239 sh = 0xff - (start - idx);
1240 else if (sh < 0) {
1241 sh = start - idx;
1242 start = idx;
1243 bitmap = bitmap << sh;
1244 sh = 0;
1245 }
4aa41f12
EG		 1246 bitmap |= 1ULL << sh;
1247 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
1248 start, (unsigned long long)bitmap);
e532fa0e
RR		 1249 }
1250
1251 agg->bitmap = bitmap;
1252 agg->start_idx = start;
e532fa0e
RR		 1253 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1254 agg->frame_count, agg->start_idx,
1255 (unsigned long long)agg->bitmap);
1256
1257 if (bitmap)
1258 agg->wait_for_ba = 1;
1259 }
1260 return 0;
1261}
1262
1263static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1264 struct iwl_rx_mem_buffer *rxb)
1265{
1266 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1267 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1268 int txq_id = SEQ_TO_QUEUE(sequence);
1269 int index = SEQ_TO_INDEX(sequence);
1270 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1271 struct ieee80211_tx_info *info;
1272 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1273 u32 status = le16_to_cpu(tx_resp->status.status);
e532fa0e 1274 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
e532fa0e
RR		 1275 struct ieee80211_hdr *hdr;
1276 u8 *qc = NULL;
e532fa0e
RR		 1277
1278 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1279 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1280 "is out of range [0-%d] %d %d\n", txq_id,
1281 index, txq->q.n_bd, txq->q.write_ptr,
1282 txq->q.read_ptr);
1283 return;
1284 }
1285
1286 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1287 memset(&info->status, 0, sizeof(info->status));
1288
e532fa0e 1289 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
fd7c8a40
HH		 1290 if (ieee80211_is_data_qos(hdr->frame_control)) {
1291 qc = ieee80211_get_qos_ctl(hdr);
e532fa0e
RR		 1292 tid = qc[0] & 0xf;
1293 }
1294
1295 sta_id = iwl_get_ra_sta_id(priv, hdr);
1296 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
1297 IWL_ERROR("Station not known\n");
1298 return;
1299 }
1300
1301 if (txq->sched_retry) {
1302 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1303 struct iwl_ht_agg *agg = NULL;
1304
1305 if (!qc)
1306 return;
1307
1308 agg = &priv->stations[sta_id].tid[tid].agg;
1309
25a6572c 1310 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
e532fa0e 1311
3235427e
RR		 1312 /* check if BAR is needed */
1313 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1314 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
e532fa0e
RR		 1315
1316 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1317 int freed, ampdu_q;
1318 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1319 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
1320 "%d index %d\n", scd_ssn , index);
17b88929 1321 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
e532fa0e
RR		 1322 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1323
1324 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1325 txq_id >= 0 && priv->mac80211_registered &&
1326 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
1327 /* calculate mac80211 ampdu sw queue to wake */
7f3e4bb6 1328 ampdu_q = txq_id - IWL50_FIRST_AMPDU_QUEUE +
e532fa0e
RR		 1329 priv->hw->queues;
1330 if (agg->state == IWL_AGG_OFF)
1331 ieee80211_wake_queue(priv->hw, txq_id);
1332 else
1333 ieee80211_wake_queue(priv->hw, ampdu_q);
1334 }
30e553e3 1335 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
e532fa0e
RR		 1336 }
1337 } else {
4f85f5b3
RR		 1338 info->status.retry_count = tx_resp->failure_frame;
1339 info->flags =
1340 iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
e7d326ac 1341 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 1342 le32_to_cpu(tx_resp->rate_n_flags),
1343 info);
1344
1345 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
1346 "0x%x retries %d\n", txq_id,
1347 iwl_get_tx_fail_reason(status),
1348 status, le32_to_cpu(tx_resp->rate_n_flags),
1349 tx_resp->failure_frame);
1350
1351 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
1352 if (index != -1) {
1353 int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1354 if (tid != MAX_TID_COUNT)
e532fa0e 1355 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
4f85f5b3 1356 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
e532fa0e
RR		 1357 (txq_id >= 0) && priv->mac80211_registered)
1358 ieee80211_wake_queue(priv->hw, txq_id);
4f85f5b3 1359 if (tid != MAX_TID_COUNT)
30e553e3 1360 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
4f85f5b3 1361 }
e532fa0e 1362 }
e532fa0e
RR		 1363
1364 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1365 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
1366}
1367
c1adf9fb
GG		 1368/* Currently 5000 is the supperset of everything */
1369static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1370{
1371 return len;
1372}
1373
203566f3
EG		 1374static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1375{
1376 /* in 5000 the tx power calibration is done in uCode */
1377 priv->disable_tx_power_cal = 1;
1378}
1379
b600e4e1
RR		 1380static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1381{
7c616cba
TW		 1382 /* init calibration handlers */
1383 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1384 iwl5000_rx_calib_result;
1385 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1386 iwl5000_rx_calib_complete;
e532fa0e 1387 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
b600e4e1
RR		 1388}
1389
7c616cba 1390
87283cc1
RR		 1391static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1392{
1393 return (addr >= RTC_DATA_LOWER_BOUND) &&
1394 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1395}
1396
fe7a90c2
RR		 1397static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1398{
1399 int ret = 0;
1400 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1401 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1402 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1403
1404 if ((rxon1->flags == rxon2->flags) &&
1405 (rxon1->filter_flags == rxon2->filter_flags) &&
1406 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1407 (rxon1->ofdm_ht_single_stream_basic_rates ==
1408 rxon2->ofdm_ht_single_stream_basic_rates) &&
1409 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1410 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1411 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1412 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1413 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1414 (rxon1->rx_chain == rxon2->rx_chain) &&
1415 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1416 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1417 return 0;
1418 }
1419
1420 rxon_assoc.flags = priv->staging_rxon.flags;
1421 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1422 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1423 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1424 rxon_assoc.reserved1 = 0;
1425 rxon_assoc.reserved2 = 0;
1426 rxon_assoc.reserved3 = 0;
1427 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1428 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1429 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1430 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1431 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1432 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1433 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1434 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1435
1436 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1437 sizeof(rxon_assoc), &rxon_assoc, NULL);
1438 if (ret)
1439 return ret;
1440
1441 return ret;
1442}
630fe9b6
TW		 1443static int iwl5000_send_tx_power(struct iwl_priv *priv)
1444{
1445 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1446
1447 /* half dBm need to multiply */
1448 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
853554ac 1449 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
630fe9b6
TW		 1450 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1451 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1452 sizeof(tx_power_cmd), &tx_power_cmd,
1453 NULL);
1454}
1455
5225640b 1456static void iwl5000_temperature(struct iwl_priv *priv)
8f91aecb
EG		 1457{
1458 /* store temperature from statistics (in Celsius) */
5225640b 1459 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
8f91aecb 1460}
fe7a90c2 1461
caab8f1a
TW		 1462/* Calc max signal level (dBm) among 3 possible receivers */
1463static int iwl5000_calc_rssi(struct iwl_priv *priv,
1464 struct iwl_rx_phy_res *rx_resp)
1465{
1466 /* data from PHY/DSP regarding signal strength, etc.,
1467 * contents are always there, not configurable by host
1468 */
1469 struct iwl5000_non_cfg_phy *ncphy =
1470 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1471 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1472 u8 agc;
1473
1474 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1475 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1476
1477 /* Find max rssi among 3 possible receivers.
1478 * These values are measured by the digital signal processor (DSP).
1479 * They should stay fairly constant even as the signal strength varies,
1480 * if the radio's automatic gain control (AGC) is working right.
1481 * AGC value (see below) will provide the "interesting" info.
1482 */
1483 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1484 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1485 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1486 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1487 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1488
1489 max_rssi = max_t(u32, rssi_a, rssi_b);
1490 max_rssi = max_t(u32, max_rssi, rssi_c);
1491
1492 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1493 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1494
1495 /* dBm = max_rssi dB - agc dB - constant.
1496 * Higher AGC (higher radio gain) means lower signal. */
1497 return max_rssi - agc - IWL_RSSI_OFFSET;
1498}
1499
da8dec29 1500static struct iwl_hcmd_ops iwl5000_hcmd = {
fe7a90c2 1501 .rxon_assoc = iwl5000_send_rxon_assoc,
da8dec29
TW		 1502};
1503
1504static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
c1adf9fb 1505 .get_hcmd_size = iwl5000_get_hcmd_size,
2469bf2e 1506 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
33fd5033
EG		 1507 .gain_computation = iwl5000_gain_computation,
1508 .chain_noise_reset = iwl5000_chain_noise_reset,
a326a5d0 1509 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
caab8f1a 1510 .calc_rssi = iwl5000_calc_rssi,
da8dec29
TW		 1511};
1512
1513static struct iwl_lib_ops iwl5000_lib = {
fdd3e8a4 1514 .set_hw_params = iwl5000_hw_set_hw_params,
d4100dd9
RR		 1515 .alloc_shared_mem = iwl5000_alloc_shared_mem,
1516 .free_shared_mem = iwl5000_free_shared_mem,
d67f5489 1517 .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
7839fc03 1518 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
972cf447 1519 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
da1bc453 1520 .txq_set_sched = iwl5000_txq_set_sched,
e26e47d9
TW		 1521 .txq_agg_enable = iwl5000_txq_agg_enable,
1522 .txq_agg_disable = iwl5000_txq_agg_disable,
b600e4e1 1523 .rx_handler_setup = iwl5000_rx_handler_setup,
203566f3 1524 .setup_deferred_work = iwl5000_setup_deferred_work,
87283cc1 1525 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
dbb983b7 1526 .load_ucode = iwl5000_load_ucode,
99da1b48
RR		 1527 .init_alive_start = iwl5000_init_alive_start,
1528 .alive_notify = iwl5000_alive_notify,
630fe9b6 1529 .send_tx_power = iwl5000_send_tx_power,
8f91aecb 1530 .temperature = iwl5000_temperature,
ca579617 1531 .update_chain_flags = iwl4965_update_chain_flags,
30d59260
TW		 1532 .apm_ops = {
1533 .init = iwl5000_apm_init,
7f066108 1534 .reset = iwl5000_apm_reset,
f118a91d 1535 .stop = iwl5000_apm_stop,
5a835353 1536 .config = iwl5000_nic_config,
88acbd3b 1537 .set_pwr_src = iwl4965_set_pwr_src,
30d59260 1538 },
da8dec29 1539 .eeprom_ops = {
25ae3986
TW		 1540 .regulatory_bands = {
1541 EEPROM_5000_REG_BAND_1_CHANNELS,
1542 EEPROM_5000_REG_BAND_2_CHANNELS,
1543 EEPROM_5000_REG_BAND_3_CHANNELS,
1544 EEPROM_5000_REG_BAND_4_CHANNELS,
1545 EEPROM_5000_REG_BAND_5_CHANNELS,
1546 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1547 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1548 },
da8dec29
TW		 1549 .verify_signature = iwlcore_eeprom_verify_signature,
1550 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1551 .release_semaphore = iwlcore_eeprom_release_semaphore,
f1f69415 1552 .check_version = iwl5000_eeprom_check_version,
25ae3986 1553 .query_addr = iwl5000_eeprom_query_addr,
da8dec29
TW		 1554 },
1555};
1556
1557static struct iwl_ops iwl5000_ops = {
1558 .lib = &iwl5000_lib,
1559 .hcmd = &iwl5000_hcmd,
1560 .utils = &iwl5000_hcmd_utils,
1561};
1562
5a6a256e
TW		 1563static struct iwl_mod_params iwl50_mod_params = {
1564 .num_of_queues = IWL50_NUM_QUEUES,
9f17b318 1565 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e
TW		 1566 .enable_qos = 1,
1567 .amsdu_size_8K = 1,
3a1081e8 1568 .restart_fw = 1,
5a6a256e
TW		 1569 /* the rest are 0 by default */
1570};
1571
1572
1573struct iwl_cfg iwl5300_agn_cfg = {
1574 .name = "5300AGN",
1575 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1576 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1577 .ops = &iwl5000_ops,
25ae3986 1578 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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TW		 1579 .mod_params = &iwl50_mod_params,
1580};
1581
47408639
EK		 1582struct iwl_cfg iwl5100_bg_cfg = {
1583 .name = "5100BG",
1584 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1585 .sku = IWL_SKU_G,
1586 .ops = &iwl5000_ops,
1587 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1588 .mod_params = &iwl50_mod_params,
1589};
1590
1591struct iwl_cfg iwl5100_abg_cfg = {
1592 .name = "5100ABG",
1593 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1594 .sku = IWL_SKU_A|IWL_SKU_G,
1595 .ops = &iwl5000_ops,
1596 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1597 .mod_params = &iwl50_mod_params,
1598};
1599
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TW		 1600struct iwl_cfg iwl5100_agn_cfg = {
1601 .name = "5100AGN",
1602 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1603 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1604 .ops = &iwl5000_ops,
25ae3986 1605 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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TW		 1606 .mod_params = &iwl50_mod_params,
1607};
1608
1609struct iwl_cfg iwl5350_agn_cfg = {
1610 .name = "5350AGN",
1611 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1612 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1613 .ops = &iwl5000_ops,
25ae3986 1614 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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TW		 1615 .mod_params = &iwl50_mod_params,
1616};
1617
1618module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1619MODULE_PARM_DESC(disable50,
1620 "manually disable the 50XX radio (default 0 [radio on])");
1621module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1622MODULE_PARM_DESC(swcrypto50,
1623 "using software crypto engine (default 0 [hardware])\n");
1624module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1625MODULE_PARM_DESC(debug50, "50XX debug output mask");
1626module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1627MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1628module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1629MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
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RR		 1630module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1631MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
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TW		 1632module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1633MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
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EK		 1634module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1635MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
Clone of davem's net-next-2.6 tree