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iwlwifi: HT antenna/chains overhaul
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <net/mac80211.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47 39#include <asm/unaligned.h>
b481de9c 40
6bc913bd 41#include "iwl-eeprom.h"
b481de9c 42#include "iwl-4965.h"
fee1247a 43#include "iwl-core.h"
3395f6e9 44#include "iwl-io.h"
b481de9c 45#include "iwl-helpers.h"
f0832f13 46#include "iwl-calib.h"
b481de9c 47
1ea87396
AK		 48/* module parameters */
49static struct iwl_mod_params iwl4965_mod_params = {
dfe7d458 50 .num_of_queues = IWL4965_MAX_NUM_QUEUES,
1ea87396
AK		 51 .enable_qos = 1,
52 .amsdu_size_8K = 1,
53 /* the rest are 0 by default */
54};
55
c79dd5b5 56static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
416e1438 57
b481de9c
ZY		 58#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
59 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
60 IWL_RATE_SISO_##s##M_PLCP, \
fde0db31
GC		 61 IWL_RATE_MIMO2_##s##M_PLCP,\
62 IWL_RATE_MIMO3_##s##M_PLCP,\
b481de9c
ZY		 63 IWL_RATE_##r##M_IEEE, \
64 IWL_RATE_##ip##M_INDEX, \
65 IWL_RATE_##in##M_INDEX, \
66 IWL_RATE_##rp##M_INDEX, \
67 IWL_RATE_##rn##M_INDEX, \
68 IWL_RATE_##pp##M_INDEX, \
69 IWL_RATE_##np##M_INDEX }
70
71/*
72 * Parameter order:
73 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
74 *
75 * If there isn't a valid next or previous rate then INV is used which
76 * maps to IWL_RATE_INVALID
77 *
78 */
bb8c093b 79const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
b481de9c
ZY		 80 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
81 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
82 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
83 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
84 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
85 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
86 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
87 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
88 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
89 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
90 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
91 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
92 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
fde0db31 93 /* FIXME:RS: ^^ should be INV (legacy) */
b481de9c
ZY		 94};
95
fe01b477
RR		 96#ifdef CONFIG_IWL4965_HT
97
98static const u16 default_tid_to_tx_fifo[] = {
99 IWL_TX_FIFO_AC1,
100 IWL_TX_FIFO_AC0,
101 IWL_TX_FIFO_AC0,
102 IWL_TX_FIFO_AC1,
103 IWL_TX_FIFO_AC2,
104 IWL_TX_FIFO_AC2,
105 IWL_TX_FIFO_AC3,
106 IWL_TX_FIFO_AC3,
107 IWL_TX_FIFO_NONE,
108 IWL_TX_FIFO_NONE,
109 IWL_TX_FIFO_NONE,
110 IWL_TX_FIFO_NONE,
111 IWL_TX_FIFO_NONE,
112 IWL_TX_FIFO_NONE,
113 IWL_TX_FIFO_NONE,
114 IWL_TX_FIFO_NONE,
115 IWL_TX_FIFO_AC3
116};
117
118#endif /*CONFIG_IWL4965_HT */
119
57aab75a
TW		 120/* check contents of special bootstrap uCode SRAM */
121static int iwl4965_verify_bsm(struct iwl_priv *priv)
122{
123 __le32 *image = priv->ucode_boot.v_addr;
124 u32 len = priv->ucode_boot.len;
125 u32 reg;
126 u32 val;
127
128 IWL_DEBUG_INFO("Begin verify bsm\n");
129
130 /* verify BSM SRAM contents */
131 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
132 for (reg = BSM_SRAM_LOWER_BOUND;
133 reg < BSM_SRAM_LOWER_BOUND + len;
134 reg += sizeof(u32), image++) {
135 val = iwl_read_prph(priv, reg);
136 if (val != le32_to_cpu(*image)) {
137 IWL_ERROR("BSM uCode verification failed at "
138 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
139 BSM_SRAM_LOWER_BOUND,
140 reg - BSM_SRAM_LOWER_BOUND, len,
141 val, le32_to_cpu(*image));
142 return -EIO;
143 }
144 }
145
146 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
147
148 return 0;
149}
150
151/**
152 * iwl4965_load_bsm - Load bootstrap instructions
153 *
154 * BSM operation:
155 *
156 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
157 * in special SRAM that does not power down during RFKILL. When powering back
158 * up after power-saving sleeps (or during initial uCode load), the BSM loads
159 * the bootstrap program into the on-board processor, and starts it.
160 *
161 * The bootstrap program loads (via DMA) instructions and data for a new
162 * program from host DRAM locations indicated by the host driver in the
163 * BSM_DRAM_* registers. Once the new program is loaded, it starts
164 * automatically.
165 *
166 * When initializing the NIC, the host driver points the BSM to the
167 * "initialize" uCode image. This uCode sets up some internal data, then
168 * notifies host via "initialize alive" that it is complete.
169 *
170 * The host then replaces the BSM_DRAM_* pointer values to point to the
171 * normal runtime uCode instructions and a backup uCode data cache buffer
172 * (filled initially with starting data values for the on-board processor),
173 * then triggers the "initialize" uCode to load and launch the runtime uCode,
174 * which begins normal operation.
175 *
176 * When doing a power-save shutdown, runtime uCode saves data SRAM into
177 * the backup data cache in DRAM before SRAM is powered down.
178 *
179 * When powering back up, the BSM loads the bootstrap program. This reloads
180 * the runtime uCode instructions and the backup data cache into SRAM,
181 * and re-launches the runtime uCode from where it left off.
182 */
183static int iwl4965_load_bsm(struct iwl_priv *priv)
184{
185 __le32 *image = priv->ucode_boot.v_addr;
186 u32 len = priv->ucode_boot.len;
187 dma_addr_t pinst;
188 dma_addr_t pdata;
189 u32 inst_len;
190 u32 data_len;
191 int i;
192 u32 done;
193 u32 reg_offset;
194 int ret;
195
196 IWL_DEBUG_INFO("Begin load bsm\n");
197
198 /* make sure bootstrap program is no larger than BSM's SRAM size */
199 if (len > IWL_MAX_BSM_SIZE)
200 return -EINVAL;
201
202 /* Tell bootstrap uCode where to find the "Initialize" uCode
203 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
204 * NOTE: iwl4965_initialize_alive_start() will replace these values,
205 * after the "initialize" uCode has run, to point to
206 * runtime/protocol instructions and backup data cache. */
207 pinst = priv->ucode_init.p_addr >> 4;
208 pdata = priv->ucode_init_data.p_addr >> 4;
209 inst_len = priv->ucode_init.len;
210 data_len = priv->ucode_init_data.len;
211
212 ret = iwl_grab_nic_access(priv);
213 if (ret)
214 return ret;
215
216 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
217 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
218 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
219 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
220
221 /* Fill BSM memory with bootstrap instructions */
222 for (reg_offset = BSM_SRAM_LOWER_BOUND;
223 reg_offset < BSM_SRAM_LOWER_BOUND + len;
224 reg_offset += sizeof(u32), image++)
225 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
226
227 ret = iwl4965_verify_bsm(priv);
228 if (ret) {
229 iwl_release_nic_access(priv);
230 return ret;
231 }
232
233 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
234 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
235 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
236 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
237
238 /* Load bootstrap code into instruction SRAM now,
239 * to prepare to load "initialize" uCode */
240 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
241
242 /* Wait for load of bootstrap uCode to finish */
243 for (i = 0; i < 100; i++) {
244 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
245 if (!(done & BSM_WR_CTRL_REG_BIT_START))
246 break;
247 udelay(10);
248 }
249 if (i < 100)
250 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
251 else {
252 IWL_ERROR("BSM write did not complete!\n");
253 return -EIO;
254 }
255
256 /* Enable future boot loads whenever power management unit triggers it
257 * (e.g. when powering back up after power-save shutdown) */
258 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
259
260 iwl_release_nic_access(priv);
261
262 return 0;
263}
264
bf85ea4f
AK		 265static int iwl4965_init_drv(struct iwl_priv *priv)
266{
267 int ret;
268 int i;
269
bf85ea4f
AK		 270 priv->retry_rate = 1;
271 priv->ibss_beacon = NULL;
272
273 spin_lock_init(&priv->lock);
274 spin_lock_init(&priv->power_data.lock);
275 spin_lock_init(&priv->sta_lock);
276 spin_lock_init(&priv->hcmd_lock);
277 spin_lock_init(&priv->lq_mngr.lock);
278
059ff826
TW		 279 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
280 sizeof(struct iwl4965_shared),
281 &priv->shared_phys);
282
283 if (!priv->shared_virt) {
284 ret = -ENOMEM;
285 goto err;
286 }
287
288 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
289
290
bf85ea4f
AK		 291 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
292 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
293
294 INIT_LIST_HEAD(&priv->free_frames);
295
296 mutex_init(&priv->mutex);
297
298 /* Clear the driver's (not device's) station table */
299 iwlcore_clear_stations_table(priv);
300
301 priv->data_retry_limit = -1;
302 priv->ieee_channels = NULL;
303 priv->ieee_rates = NULL;
304 priv->band = IEEE80211_BAND_2GHZ;
305
306 priv->iw_mode = IEEE80211_IF_TYPE_STA;
307
308 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
bf85ea4f
AK		 309 priv->ps_mode = IWL_MIMO_PS_NONE;
310
311 /* Choose which receivers/antennas to use */
312 iwl4965_set_rxon_chain(priv);
313
314 iwlcore_reset_qos(priv);
315
316 priv->qos_data.qos_active = 0;
317 priv->qos_data.qos_cap.val = 0;
318
319 iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
320
321 priv->rates_mask = IWL_RATES_MASK;
322 /* If power management is turned on, default to AC mode */
323 priv->power_mode = IWL_POWER_AC;
324 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
325
326 ret = iwl_init_channel_map(priv);
327 if (ret) {
328 IWL_ERROR("initializing regulatory failed: %d\n", ret);
329 goto err;
330 }
331
332 ret = iwl4965_init_geos(priv);
333 if (ret) {
334 IWL_ERROR("initializing geos failed: %d\n", ret);
335 goto err_free_channel_map;
336 }
337
bf85ea4f
AK		 338 ret = ieee80211_register_hw(priv->hw);
339 if (ret) {
340 IWL_ERROR("Failed to register network device (error %d)\n",
341 ret);
342 goto err_free_geos;
343 }
344
345 priv->hw->conf.beacon_int = 100;
346 priv->mac80211_registered = 1;
347
348 return 0;
349
350err_free_geos:
351 iwl4965_free_geos(priv);
352err_free_channel_map:
353 iwl_free_channel_map(priv);
354err:
355 return ret;
356}
357
b481de9c
ZY		 358static int is_fat_channel(__le32 rxon_flags)
359{
360 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
361 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
362}
363
c8b0e6e1 364#ifdef CONFIG_IWL4965_HT
fde0db31
GC		 365static u8 is_single_rx_stream(struct iwl_priv *priv)
366{
367 return !priv->current_ht_config.is_ht ||
368 ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
369 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
370 priv->ps_mode == IWL_MIMO_PS_STATIC;
371}
b481de9c 372#else
fde0db31
GC		 373static inline u8 is_single_rx_stream(struct iwl_priv *priv)
374{
b481de9c 375 return 1;
b481de9c 376}
fde0db31 377#endif /*CONFIG_IWL4965_HT */
b481de9c 378
17744ff6
TW		 379int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
380{
381 int idx = 0;
382
383 /* 4965 HT rate format */
384 if (rate_n_flags & RATE_MCS_HT_MSK) {
385 idx = (rate_n_flags & 0xff);
386
fde0db31
GC		 387 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
388 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
17744ff6
TW		 389
390 idx += IWL_FIRST_OFDM_RATE;
391 /* skip 9M not supported in ht*/
392 if (idx >= IWL_RATE_9M_INDEX)
393 idx += 1;
394 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
395 return idx;
396
397 /* 4965 legacy rate format, search for match in table */
398 } else {
399 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
400 if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
401 return idx;
402 }
403
404 return -1;
405}
406
4c424e4c
RR		 407/**
408 * translate ucode response to mac80211 tx status control values
409 */
c79dd5b5 410void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
4c424e4c
RR		 411 struct ieee80211_tx_control *control)
412{
413 int rate_index;
414
415 control->antenna_sel_tx =
fde0db31 416 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
4c424e4c
RR		 417 if (rate_n_flags & RATE_MCS_HT_MSK)
418 control->flags |= IEEE80211_TXCTL_OFDM_HT;
419 if (rate_n_flags & RATE_MCS_GF_MSK)
420 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
421 if (rate_n_flags & RATE_MCS_FAT_MSK)
422 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
423 if (rate_n_flags & RATE_MCS_DUP_MSK)
424 control->flags |= IEEE80211_TXCTL_DUP_DATA;
425 if (rate_n_flags & RATE_MCS_SGI_MSK)
426 control->flags |= IEEE80211_TXCTL_SHORT_GI;
427 /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
428 * IEEE80211_BAND_2GHZ band as it contains all the rates */
429 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
430 if (rate_index == -1)
431 control->tx_rate = NULL;
432 else
433 control->tx_rate =
434 &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
435}
17744ff6 436
b481de9c
ZY		 437/*
438 * Determine how many receiver/antenna chains to use.
439 * More provides better reception via diversity. Fewer saves power.
440 * MIMO (dual stream) requires at least 2, but works better with 3.
441 * This does not determine *which* chains to use, just how many.
442 */
c79dd5b5 443static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
b481de9c
ZY		 444 u8 *idle_state, u8 *rx_state)
445{
fde0db31 446 u8 is_single = is_single_rx_stream(priv);
b481de9c
ZY		 447 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
448
449 /* # of Rx chains to use when expecting MIMO. */
450 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
451 *rx_state = 2;
452 else
453 *rx_state = 3;
454
455 /* # Rx chains when idling and maybe trying to save power */
456 switch (priv->ps_mode) {
457 case IWL_MIMO_PS_STATIC:
458 case IWL_MIMO_PS_DYNAMIC:
459 *idle_state = (is_cam) ? 2 : 1;
460 break;
461 case IWL_MIMO_PS_NONE:
462 *idle_state = (is_cam) ? *rx_state : 1;
463 break;
464 default:
465 *idle_state = 1;
466 break;
467 }
468
469 return 0;
470}
471
c79dd5b5 472int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 473{
474 int rc;
475 unsigned long flags;
476
477 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 478 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 479 if (rc) {
480 spin_unlock_irqrestore(&priv->lock, flags);
481 return rc;
482 }
483
8b6eaea8 484 /* stop Rx DMA */
3395f6e9
TW		 485 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
486 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
b481de9c
ZY		 487 (1 << 24), 1000);
488 if (rc < 0)
489 IWL_ERROR("Can't stop Rx DMA.\n");
490
3395f6e9 491 iwl_release_nic_access(priv);
b481de9c
ZY		 492 spin_unlock_irqrestore(&priv->lock, flags);
493
494 return 0;
495}
496
079a2533 497int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 498{
d8609652 499 int ret;
b481de9c
ZY		 500 unsigned long flags;
501
502 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 503 ret = iwl_grab_nic_access(priv);
d8609652 504 if (ret) {
b481de9c 505 spin_unlock_irqrestore(&priv->lock, flags);
d8609652 506 return ret;
b481de9c
ZY		 507 }
508
6f4083aa 509 if (src == IWL_PWR_SRC_VAUX) {
b481de9c 510 u32 val;
d8609652 511 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
6f4083aa 512 &val);
b481de9c 513
6f4083aa 514 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
3395f6e9 515 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 516 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
517 ~APMG_PS_CTRL_MSK_PWR_SRC);
518 }
519 } else {
3395f6e9 520 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 521 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
522 ~APMG_PS_CTRL_MSK_PWR_SRC);
523 }
b481de9c 524
3395f6e9 525 iwl_release_nic_access(priv);
b481de9c
ZY		 526 spin_unlock_irqrestore(&priv->lock, flags);
527
d8609652 528 return ret;
b481de9c
ZY		 529}
530
c79dd5b5 531static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c 532{
059ff826 533 int ret;
b481de9c 534 unsigned long flags;
9ee1ba47 535 unsigned int rb_size;
b481de9c
ZY		 536
537 spin_lock_irqsave(&priv->lock, flags);
059ff826
TW		 538 ret = iwl_grab_nic_access(priv);
539 if (ret) {
b481de9c 540 spin_unlock_irqrestore(&priv->lock, flags);
059ff826 541 return ret;
b481de9c
ZY		 542 }
543
1ea87396 544 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47
RR		 545 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
546 else
547 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
548
8b6eaea8 549 /* Stop Rx DMA */
3395f6e9 550 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
b481de9c 551
8b6eaea8 552 /* Reset driver's Rx queue write index */
3395f6e9 553 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
8b6eaea8
BC		 554
555 /* Tell device where to find RBD circular buffer in DRAM */
3395f6e9
TW		 556 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
557 rxq->dma_addr >> 8);
b481de9c 558
8b6eaea8 559 /* Tell device where in DRAM to update its Rx status */
3395f6e9 560 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
059ff826
TW		 561 (priv->shared_phys +
562 offsetof(struct iwl4965_shared, rb_closed)) >> 4);
b481de9c 563
8b6eaea8 564 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
3395f6e9
TW		 565 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
566 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
567 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
568 rb_size |
059ff826 569 /* 0x10 << 4 | */
3395f6e9 570 (RX_QUEUE_SIZE_LOG <<
b481de9c
ZY		 571 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
572
573 /*
3395f6e9 574 * iwl_write32(priv,CSR_INT_COAL_REG,0);
b481de9c
ZY		 575 */
576
3395f6e9 577 iwl_release_nic_access(priv);
b481de9c
ZY		 578 spin_unlock_irqrestore(&priv->lock, flags);
579
580 return 0;
581}
582
8b6eaea8 583/* Tell 4965 where to find the "keep warm" buffer */
c79dd5b5 584static int iwl4965_kw_init(struct iwl_priv *priv)
b481de9c
ZY		 585{
586 unsigned long flags;
587 int rc;
588
589 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 590 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 591 if (rc)
592 goto out;
593
3395f6e9 594 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
b481de9c 595 priv->kw.dma_addr >> 4);
3395f6e9 596 iwl_release_nic_access(priv);
b481de9c
ZY		 597out:
598 spin_unlock_irqrestore(&priv->lock, flags);
599 return rc;
600}
601
c79dd5b5 602static int iwl4965_kw_alloc(struct iwl_priv *priv)
b481de9c
ZY		 603{
604 struct pci_dev *dev = priv->pci_dev;
bb8c093b 605 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 606
607 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
608 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
609 if (!kw->v_addr)
610 return -ENOMEM;
611
612 return 0;
613}
614
8b6eaea8
BC		 615/**
616 * iwl4965_kw_free - Free the "keep warm" buffer
617 */
c79dd5b5 618static void iwl4965_kw_free(struct iwl_priv *priv)
b481de9c
ZY		 619{
620 struct pci_dev *dev = priv->pci_dev;
bb8c093b 621 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 622
623 if (kw->v_addr) {
624 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
625 memset(kw, 0, sizeof(*kw));
626 }
627}
628
629/**
630 * iwl4965_txq_ctx_reset - Reset TX queue context
631 * Destroys all DMA structures and initialise them again
632 *
633 * @param priv
634 * @return error code
635 */
c79dd5b5 636static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 637{
638 int rc = 0;
639 int txq_id, slots_num;
640 unsigned long flags;
641
642 iwl4965_kw_free(priv);
643
8b6eaea8 644 /* Free all tx/cmd queues and keep-warm buffer */
bb8c093b 645 iwl4965_hw_txq_ctx_free(priv);
b481de9c 646
8b6eaea8 647 /* Alloc keep-warm buffer */
b481de9c
ZY		 648 rc = iwl4965_kw_alloc(priv);
649 if (rc) {
650 IWL_ERROR("Keep Warm allocation failed");
651 goto error_kw;
652 }
653
654 spin_lock_irqsave(&priv->lock, flags);
655
3395f6e9 656 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 657 if (unlikely(rc)) {
658 IWL_ERROR("TX reset failed");
659 spin_unlock_irqrestore(&priv->lock, flags);
660 goto error_reset;
661 }
662
8b6eaea8 663 /* Turn off all Tx DMA channels */
12a81f60 664 iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
3395f6e9 665 iwl_release_nic_access(priv);
b481de9c
ZY		 666 spin_unlock_irqrestore(&priv->lock, flags);
667
8b6eaea8 668 /* Tell 4965 where to find the keep-warm buffer */
b481de9c
ZY		 669 rc = iwl4965_kw_init(priv);
670 if (rc) {
671 IWL_ERROR("kw_init failed\n");
672 goto error_reset;
673 }
674
8b6eaea8
BC		 675 /* Alloc and init all (default 16) Tx queues,
676 * including the command queue (#4) */
5425e490 677 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 678 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
679 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 680 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 681 txq_id);
682 if (rc) {
683 IWL_ERROR("Tx %d queue init failed\n", txq_id);
684 goto error;
685 }
686 }
687
688 return rc;
689
690 error:
bb8c093b 691 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 692 error_reset:
693 iwl4965_kw_free(priv);
694 error_kw:
695 return rc;
696}
697
c79dd5b5 698int iwl4965_hw_nic_init(struct iwl_priv *priv)
b481de9c
ZY		 699{
700 int rc;
701 unsigned long flags;
bb8c093b 702 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c 703 u8 rev_id;
b481de9c 704 u8 val_link;
073d3f5f
TW		 705 u16 sku_cap;
706 u32 val;
b481de9c 707
b481de9c
ZY		 708 /* nic_init */
709 spin_lock_irqsave(&priv->lock, flags);
710
3395f6e9 711 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
b481de9c
ZY		 712 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
713
3395f6e9
TW		 714 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
715 rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 716 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
717 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
718 if (rc < 0) {
719 spin_unlock_irqrestore(&priv->lock, flags);
720 IWL_DEBUG_INFO("Failed to init the card\n");
721 return rc;
722 }
723
3395f6e9 724 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 725 if (rc) {
726 spin_unlock_irqrestore(&priv->lock, flags);
727 return rc;
728 }
729
3395f6e9 730 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
b481de9c 731
3395f6e9
TW		 732 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
733 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
734 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
b481de9c
ZY		 735
736 udelay(20);
737
3395f6e9
TW		 738 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
739 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 740
3395f6e9
TW		 741 iwl_release_nic_access(priv);
742 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
b481de9c
ZY		 743 spin_unlock_irqrestore(&priv->lock, flags);
744
745 /* Determine HW type */
746 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
747 if (rc)
748 return rc;
749
750 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
751
6f4083aa
TW		 752 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
753
b481de9c
ZY		 754 spin_lock_irqsave(&priv->lock, flags);
755
756 if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
757 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
758 /* Enable No Snoop field */
759 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
760 val & ~(1 << 11));
761 }
762
763 spin_unlock_irqrestore(&priv->lock, flags);
764
073d3f5f
TW		 765 if (iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET) <
766 EEPROM_4965_TX_POWER_VERSION) {
b481de9c
ZY		 767 IWL_ERROR("Older EEPROM detected! Aborting.\n");
768 return -EINVAL;
769 }
770
771 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
772
773 /* disable L1 entry -- workaround for pre-B1 */
774 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
775
776 spin_lock_irqsave(&priv->lock, flags);
777
778 /* set CSR_HW_CONFIG_REG for uCode use */
779
3395f6e9
TW		 780 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
781 CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
782 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
783 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 784
3395f6e9 785 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 786 if (rc < 0) {
787 spin_unlock_irqrestore(&priv->lock, flags);
788 IWL_DEBUG_INFO("Failed to init the card\n");
789 return rc;
790 }
791
3395f6e9
TW		 792 iwl_read_prph(priv, APMG_PS_CTRL_REG);
793 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c 794 udelay(5);
3395f6e9 795 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c 796
3395f6e9 797 iwl_release_nic_access(priv);
b481de9c
ZY		 798 spin_unlock_irqrestore(&priv->lock, flags);
799
bb8c093b 800 iwl4965_hw_card_show_info(priv);
b481de9c
ZY		 801
802 /* end nic_init */
803
804 /* Allocate the RX queue, or reset if it is already allocated */
805 if (!rxq->bd) {
bb8c093b 806 rc = iwl4965_rx_queue_alloc(priv);
b481de9c
ZY		 807 if (rc) {
808 IWL_ERROR("Unable to initialize Rx queue\n");
809 return -ENOMEM;
810 }
811 } else
bb8c093b 812 iwl4965_rx_queue_reset(priv, rxq);
b481de9c 813
bb8c093b 814 iwl4965_rx_replenish(priv);
b481de9c
ZY		 815
816 iwl4965_rx_init(priv, rxq);
817
818 spin_lock_irqsave(&priv->lock, flags);
819
820 rxq->need_update = 1;
bb8c093b 821 iwl4965_rx_queue_update_write_ptr(priv, rxq);
b481de9c 822
073d3f5f
TW		 823 /* init the txpower calibration pointer */
824 priv->calib_info = (struct iwl_eeprom_calib_info *)
825 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
826
b481de9c 827 spin_unlock_irqrestore(&priv->lock, flags);
8b6eaea8
BC		 828
829 /* Allocate and init all Tx and Command queues */
b481de9c
ZY		 830 rc = iwl4965_txq_ctx_reset(priv);
831 if (rc)
832 return rc;
833
073d3f5f
TW		 834 sku_cap = iwl_eeprom_query16(priv, EEPROM_SKU_CAP);
835 if (sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
b481de9c
ZY		 836 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
837
073d3f5f 838 if (sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
b481de9c
ZY		 839 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
840
841 set_bit(STATUS_INIT, &priv->status);
842
843 return 0;
844}
845
c79dd5b5 846int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
b481de9c
ZY		 847{
848 int rc = 0;
849 u32 reg_val;
850 unsigned long flags;
851
852 spin_lock_irqsave(&priv->lock, flags);
853
854 /* set stop master bit */
3395f6e9 855 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 856
3395f6e9 857 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 858
859 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
860 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
861 IWL_DEBUG_INFO("Card in power save, master is already "
862 "stopped\n");
863 else {
3395f6e9 864 rc = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 865 CSR_RESET_REG_FLAG_MASTER_DISABLED,
866 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
867 if (rc < 0) {
868 spin_unlock_irqrestore(&priv->lock, flags);
869 return rc;
870 }
871 }
872
873 spin_unlock_irqrestore(&priv->lock, flags);
874 IWL_DEBUG_INFO("stop master\n");
875
876 return rc;
877}
878
8b6eaea8
BC		 879/**
880 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
881 */
c79dd5b5 882void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c
ZY		 883{
884
885 int txq_id;
886 unsigned long flags;
887
8b6eaea8 888 /* Stop each Tx DMA channel, and wait for it to be idle */
5425e490 889 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c 890 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 891 if (iwl_grab_nic_access(priv)) {
b481de9c
ZY		 892 spin_unlock_irqrestore(&priv->lock, flags);
893 continue;
894 }
895
3395f6e9
TW		 896 iwl_write_direct32(priv,
897 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
898 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
899 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
900 (txq_id), 200);
901 iwl_release_nic_access(priv);
b481de9c
ZY		 902 spin_unlock_irqrestore(&priv->lock, flags);
903 }
904
8b6eaea8 905 /* Deallocate memory for all Tx queues */
bb8c093b 906 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 907}
908
c79dd5b5 909int iwl4965_hw_nic_reset(struct iwl_priv *priv)
b481de9c
ZY		 910{
911 int rc = 0;
912 unsigned long flags;
913
bb8c093b 914 iwl4965_hw_nic_stop_master(priv);
b481de9c
ZY		 915
916 spin_lock_irqsave(&priv->lock, flags);
917
3395f6e9 918 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 919
920 udelay(10);
921
3395f6e9
TW		 922 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
923 rc = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 924 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
925 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
926
927 udelay(10);
928
3395f6e9 929 rc = iwl_grab_nic_access(priv);
b481de9c 930 if (!rc) {
3395f6e9
TW		 931 iwl_write_prph(priv, APMG_CLK_EN_REG,
932 APMG_CLK_VAL_DMA_CLK_RQT |
933 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 934
935 udelay(10);
936
3395f6e9
TW		 937 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
938 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 939
3395f6e9 940 iwl_release_nic_access(priv);
b481de9c
ZY		 941 }
942
943 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
944 wake_up_interruptible(&priv->wait_command_queue);
945
946 spin_unlock_irqrestore(&priv->lock, flags);
947
948 return rc;
949
950}
951
952#define REG_RECALIB_PERIOD (60)
953
954/**
955 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
956 *
49ea8596 957 * This callback is provided in order to send a statistics request.
b481de9c
ZY		 958 *
959 * This timer function is continually reset to execute within
960 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
961 * was received. We need to ensure we receive the statistics in order
49ea8596 962 * to update the temperature used for calibrating the TXPOWER.
b481de9c
ZY		 963 */
964static void iwl4965_bg_statistics_periodic(unsigned long data)
965{
c79dd5b5 966 struct iwl_priv *priv = (struct iwl_priv *)data;
b481de9c 967
b481de9c
ZY		 968 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
969 return;
970
49ea8596 971 iwl_send_statistics_request(priv, CMD_ASYNC);
b481de9c
ZY		 972}
973
c79dd5b5 974void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
b481de9c 975{
bb8c093b 976 struct iwl4965_ct_kill_config cmd;
b481de9c 977 unsigned long flags;
857485c0 978 int ret = 0;
b481de9c
ZY		 979
980 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 981 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 982 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
983 spin_unlock_irqrestore(&priv->lock, flags);
984
099b40b7 985 cmd.critical_temperature_R =
b73cdf27
EG		 986 cpu_to_le32(priv->hw_params.ct_kill_threshold);
987
857485c0
TW		 988 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
989 sizeof(cmd), &cmd);
990 if (ret)
b481de9c
ZY		 991 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
992 else
b73cdf27
EG		 993 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
994 "critical temperature is %d\n",
995 cmd.critical_temperature_R);
b481de9c
ZY		 996}
997
f0832f13 998#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 999
1000/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
1001 * Called after every association, but this runs only once!
1002 * ... once chain noise is calibrated the first time, it's good forever. */
f0832f13 1003static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 1004{
f0832f13 1005 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
b481de9c 1006
3109ece1 1007 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
bb8c093b 1008 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 1009
1010 memset(&cmd, 0, sizeof(cmd));
1011 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1012 cmd.diff_gain_a = 0;
1013 cmd.diff_gain_b = 0;
1014 cmd.diff_gain_c = 0;
f0832f13
EG		 1015 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1016 sizeof(cmd), &cmd))
1017 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
b481de9c
ZY		 1018 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1019 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1020 }
b481de9c
ZY		 1021}
1022
f0832f13
EG		 1023static void iwl4965_gain_computation(struct iwl_priv *priv,
1024 u32 *average_noise,
1025 u16 min_average_noise_antenna_i,
1026 u32 min_average_noise)
b481de9c 1027{
f0832f13
EG		 1028 int i, ret;
1029 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
b481de9c 1030
f0832f13 1031 data->delta_gain_code[min_average_noise_antenna_i] = 0;
b481de9c 1032
f0832f13
EG		 1033 for (i = 0; i < NUM_RX_CHAINS; i++) {
1034 s32 delta_g = 0;
b481de9c 1035
f0832f13
EG		 1036 if (!(data->disconn_array[i]) &&
1037 (data->delta_gain_code[i] ==
b481de9c 1038 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
f0832f13
EG		 1039 delta_g = average_noise[i] - min_average_noise;
1040 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
1041 data->delta_gain_code[i] =
1042 min(data->delta_gain_code[i],
1043 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
1044
1045 data->delta_gain_code[i] =
1046 (data->delta_gain_code[i] | (1 << 2));
1047 } else {
1048 data->delta_gain_code[i] = 0;
b481de9c 1049 }
b481de9c 1050 }
f0832f13
EG		 1051 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1052 data->delta_gain_code[0],
1053 data->delta_gain_code[1],
1054 data->delta_gain_code[2]);
b481de9c 1055
f0832f13
EG		 1056 /* Differential gain gets sent to uCode only once */
1057 if (!data->radio_write) {
1058 struct iwl4965_calibration_cmd cmd;
1059 data->radio_write = 1;
b481de9c 1060
f0832f13
EG		 1061 memset(&cmd, 0, sizeof(cmd));
1062 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1063 cmd.diff_gain_a = data->delta_gain_code[0];
1064 cmd.diff_gain_b = data->delta_gain_code[1];
1065 cmd.diff_gain_c = data->delta_gain_code[2];
1066 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1067 sizeof(cmd), &cmd);
1068 if (ret)
1069 IWL_DEBUG_CALIB("fail sending cmd "
1070 "REPLY_PHY_CALIBRATION_CMD \n");
1071
1072 /* TODO we might want recalculate
1073 * rx_chain in rxon cmd */
1074
1075 /* Mark so we run this algo only once! */
1076 data->state = IWL_CHAIN_NOISE_CALIBRATED;
b481de9c 1077 }
f0832f13
EG		 1078 data->chain_noise_a = 0;
1079 data->chain_noise_b = 0;
1080 data->chain_noise_c = 0;
1081 data->chain_signal_a = 0;
1082 data->chain_signal_b = 0;
1083 data->chain_signal_c = 0;
1084 data->beacon_count = 0;
b481de9c
ZY		 1085}
1086
1087static void iwl4965_bg_sensitivity_work(struct work_struct *work)
1088{
c79dd5b5 1089 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1090 sensitivity_work);
1091
1092 mutex_lock(&priv->mutex);
1093
1094 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1095 test_bit(STATUS_SCANNING, &priv->status)) {
1096 mutex_unlock(&priv->mutex);
1097 return;
1098 }
1099
1100 if (priv->start_calib) {
f0832f13
EG		 1101 iwl_chain_noise_calibration(priv, &priv->statistics);
1102
1103 iwl_sensitivity_calibration(priv, &priv->statistics);
b481de9c
ZY		 1104 }
1105
1106 mutex_unlock(&priv->mutex);
1107 return;
1108}
f0832f13 1109#endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
b481de9c
ZY		 1110
1111static void iwl4965_bg_txpower_work(struct work_struct *work)
1112{
c79dd5b5 1113 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1114 txpower_work);
1115
1116 /* If a scan happened to start before we got here
1117 * then just return; the statistics notification will
1118 * kick off another scheduled work to compensate for
1119 * any temperature delta we missed here. */
1120 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1121 test_bit(STATUS_SCANNING, &priv->status))
1122 return;
1123
1124 mutex_lock(&priv->mutex);
1125
1126 /* Regardless of if we are assocaited, we must reconfigure the
1127 * TX power since frames can be sent on non-radar channels while
1128 * not associated */
bb8c093b 1129 iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY		 1130
1131 /* Update last_temperature to keep is_calib_needed from running
1132 * when it isn't needed... */
1133 priv->last_temperature = priv->temperature;
1134
1135 mutex_unlock(&priv->mutex);
1136}
1137
1138/*
1139 * Acquire priv->lock before calling this function !
1140 */
c79dd5b5 1141static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 1142{
3395f6e9 1143 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 1144 (index & 0xff) | (txq_id << 8));
12a81f60 1145 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 1146}
1147
8b6eaea8
BC		 1148/**
1149 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
1150 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
1151 * @scd_retry: (1) Indicates queue will be used in aggregation mode
1152 *
1153 * NOTE: Acquire priv->lock before calling this function !
b481de9c 1154 */
c79dd5b5 1155static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
bb8c093b 1156 struct iwl4965_tx_queue *txq,
b481de9c
ZY		 1157 int tx_fifo_id, int scd_retry)
1158{
1159 int txq_id = txq->q.id;
8b6eaea8
BC		 1160
1161 /* Find out whether to activate Tx queue */
b481de9c
ZY		 1162 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1163
8b6eaea8 1164 /* Set up and activate */
12a81f60 1165 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
b481de9c
ZY		 1166 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1167 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1168 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
1169 (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1170 SCD_QUEUE_STTS_REG_MSK);
1171
1172 txq->sched_retry = scd_retry;
1173
1174 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 1175 active ? "Activate" : "Deactivate",
b481de9c
ZY		 1176 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1177}
1178
1179static const u16 default_queue_to_tx_fifo[] = {
1180 IWL_TX_FIFO_AC3,
1181 IWL_TX_FIFO_AC2,
1182 IWL_TX_FIFO_AC1,
1183 IWL_TX_FIFO_AC0,
1184 IWL_CMD_FIFO_NUM,
1185 IWL_TX_FIFO_HCCA_1,
1186 IWL_TX_FIFO_HCCA_2
1187};
1188
c79dd5b5 1189static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1190{
1191 set_bit(txq_id, &priv->txq_ctx_active_msk);
1192}
1193
c79dd5b5 1194static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1195{
1196 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1197}
1198
c79dd5b5 1199int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 1200{
1201 u32 a;
1202 int i = 0;
1203 unsigned long flags;
857485c0 1204 int ret;
b481de9c
ZY		 1205
1206 spin_lock_irqsave(&priv->lock, flags);
1207
f0832f13 1208#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c 1209 memset(&(priv->sensitivity_data), 0,
f0832f13 1210 sizeof(struct iwl_sensitivity_data));
b481de9c 1211 memset(&(priv->chain_noise_data), 0,
f0832f13 1212 sizeof(struct iwl_chain_noise_data));
b481de9c
ZY		 1213 for (i = 0; i < NUM_RX_CHAINS; i++)
1214 priv->chain_noise_data.delta_gain_code[i] =
1215 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
f0832f13 1216#endif /* CONFIG_IWL4965_RUN_TIME_CALIB*/
3395f6e9 1217 ret = iwl_grab_nic_access(priv);
857485c0 1218 if (ret) {
b481de9c 1219 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 1220 return ret;
b481de9c
ZY		 1221 }
1222
8b6eaea8 1223 /* Clear 4965's internal Tx Scheduler data base */
12a81f60 1224 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
b481de9c
ZY		 1225 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1226 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
3395f6e9 1227 iwl_write_targ_mem(priv, a, 0);
b481de9c 1228 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
3395f6e9 1229 iwl_write_targ_mem(priv, a, 0);
5425e490 1230 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
3395f6e9 1231 iwl_write_targ_mem(priv, a, 0);
b481de9c 1232
8b6eaea8 1233 /* Tel 4965 where to find Tx byte count tables */
12a81f60 1234 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
059ff826 1235 (priv->shared_phys +
bb8c093b 1236 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
8b6eaea8
BC		 1237
1238 /* Disable chain mode for all queues */
12a81f60 1239 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
b481de9c 1240
8b6eaea8 1241 /* Initialize each Tx queue (including the command queue) */
5425e490 1242 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
8b6eaea8
BC		 1243
1244 /* TFD circular buffer read/write indexes */
12a81f60 1245 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
3395f6e9 1246 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
BC		 1247
1248 /* Max Tx Window size for Scheduler-ACK mode */
3395f6e9 1249 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1250 SCD_CONTEXT_QUEUE_OFFSET(i),
1251 (SCD_WIN_SIZE <<
1252 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1253 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
BC		 1254
1255 /* Frame limit */
3395f6e9 1256 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1257 SCD_CONTEXT_QUEUE_OFFSET(i) +
1258 sizeof(u32),
1259 (SCD_FRAME_LIMIT <<
1260 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1261 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1262
1263 }
12a81f60 1264 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
5425e490 1265 (1 << priv->hw_params.max_txq_num) - 1);
b481de9c 1266
8b6eaea8 1267 /* Activate all Tx DMA/FIFO channels */
12a81f60 1268 iwl_write_prph(priv, IWL49_SCD_TXFACT,
b481de9c
ZY		 1269 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1270
1271 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
BC		 1272
1273 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 1274 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1275 int ac = default_queue_to_tx_fifo[i];
1276 iwl4965_txq_ctx_activate(priv, i);
1277 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1278 }
1279
3395f6e9 1280 iwl_release_nic_access(priv);
b481de9c
ZY		 1281 spin_unlock_irqrestore(&priv->lock, flags);
1282
49ea8596
EG		 1283 /* Ask for statistics now, the uCode will send statistics notification
1284 * periodically after association */
1285 iwl_send_statistics_request(priv, CMD_ASYNC);
857485c0 1286 return ret;
b481de9c
ZY		 1287}
1288
f0832f13
EG		 1289#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1290static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
1291 .min_nrg_cck = 97,
1292 .max_nrg_cck = 0,
1293
1294 .auto_corr_min_ofdm = 85,
1295 .auto_corr_min_ofdm_mrc = 170,
1296 .auto_corr_min_ofdm_x1 = 105,
1297 .auto_corr_min_ofdm_mrc_x1 = 220,
1298
1299 .auto_corr_max_ofdm = 120,
1300 .auto_corr_max_ofdm_mrc = 210,
1301 .auto_corr_max_ofdm_x1 = 140,
1302 .auto_corr_max_ofdm_mrc_x1 = 270,
1303
1304 .auto_corr_min_cck = 125,
1305 .auto_corr_max_cck = 200,
1306 .auto_corr_min_cck_mrc = 200,
1307 .auto_corr_max_cck_mrc = 400,
1308
1309 .nrg_th_cck = 100,
1310 .nrg_th_ofdm = 100,
1311};
1312#endif
1313
8b6eaea8 1314/**
5425e490 1315 * iwl4965_hw_set_hw_params
8b6eaea8
BC		 1316 *
1317 * Called when initializing driver
1318 */
5425e490 1319int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 1320{
316c30d9 1321
dfe7d458 1322 if ((priv->cfg->mod_params->num_of_queues > IWL4965_MAX_NUM_QUEUES) ||
1ea87396 1323 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9 1324 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
dfe7d458 1325 IWL_MIN_NUM_QUEUES, IWL4965_MAX_NUM_QUEUES);
059ff826 1326 return -EINVAL;
316c30d9 1327 }
b481de9c 1328
5425e490 1329 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
099b40b7 1330 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
5425e490
TW		 1331 priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
1332 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1333 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1ea87396 1334 if (priv->cfg->mod_params->amsdu_size_8K)
5425e490 1335 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
9ee1ba47 1336 else
5425e490
TW		 1337 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1338 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1339 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
1340 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
3e82a822 1341
099b40b7
RR		 1342 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
1343 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
1344 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
1345 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
1346
ec35cf2a
TW		 1347 priv->hw_params.tx_chains_num = 2;
1348 priv->hw_params.rx_chains_num = 2;
fde0db31
GC		 1349 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
1350 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
099b40b7
RR		 1351 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
1352
f0832f13
EG		 1353#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1354 priv->hw_params.sens = &iwl4965_sensitivity;
1355#endif
3e82a822 1356
059ff826 1357 return 0;
b481de9c
ZY		 1358}
1359
1360/**
bb8c093b 1361 * iwl4965_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1362 *
1363 * Destroy all TX DMA queues and structures
1364 */
c79dd5b5 1365void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1366{
1367 int txq_id;
1368
1369 /* Tx queues */
5425e490 1370 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
bb8c093b 1371 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c 1372
8b6eaea8 1373 /* Keep-warm buffer */
b481de9c
ZY		 1374 iwl4965_kw_free(priv);
1375}
1376
1377/**
8b6eaea8 1378 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
b481de9c 1379 *
8b6eaea8
BC		 1380 * Does NOT advance any TFD circular buffer read/write indexes
1381 * Does NOT free the TFD itself (which is within circular buffer)
b481de9c 1382 */
c79dd5b5 1383int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c 1384{
bb8c093b
CH		 1385 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1386 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 1387 struct pci_dev *dev = priv->pci_dev;
1388 int i;
1389 int counter = 0;
1390 int index, is_odd;
1391
8b6eaea8 1392 /* Host command buffers stay mapped in memory, nothing to clean */
b481de9c 1393 if (txq->q.id == IWL_CMD_QUEUE_NUM)
b481de9c
ZY		 1394 return 0;
1395
8b6eaea8 1396 /* Sanity check on number of chunks */
b481de9c
ZY		 1397 counter = IWL_GET_BITS(*bd, num_tbs);
1398 if (counter > MAX_NUM_OF_TBS) {
1399 IWL_ERROR("Too many chunks: %i\n", counter);
1400 /* @todo issue fatal error, it is quite serious situation */
1401 return 0;
1402 }
1403
8b6eaea8
BC		 1404 /* Unmap chunks, if any.
1405 * TFD info for odd chunks is different format than for even chunks. */
b481de9c
ZY		 1406 for (i = 0; i < counter; i++) {
1407 index = i / 2;
1408 is_odd = i & 0x1;
1409
1410 if (is_odd)
1411 pci_unmap_single(
1412 dev,
1413 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1414 (IWL_GET_BITS(bd->pa[index],
1415 tb2_addr_hi20) << 16),
1416 IWL_GET_BITS(bd->pa[index], tb2_len),
1417 PCI_DMA_TODEVICE);
1418
1419 else if (i > 0)
1420 pci_unmap_single(dev,
1421 le32_to_cpu(bd->pa[index].tb1_addr),
1422 IWL_GET_BITS(bd->pa[index], tb1_len),
1423 PCI_DMA_TODEVICE);
1424
8b6eaea8 1425 /* Free SKB, if any, for this chunk */
fc4b6853
TW		 1426 if (txq->txb[txq->q.read_ptr].skb[i]) {
1427 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
b481de9c
ZY		 1428
1429 dev_kfree_skb(skb);
fc4b6853 1430 txq->txb[txq->q.read_ptr].skb[i] = NULL;
b481de9c
ZY		 1431 }
1432 }
1433 return 0;
1434}
1435
5da4b55f
MA		 1436/* set card power command */
1437static int iwl4965_set_power(struct iwl_priv *priv,
1438 void *cmd)
1439{
1440 int ret = 0;
1441
1442 ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
1443 sizeof(struct iwl4965_powertable_cmd),
1444 cmd, NULL);
1445 return ret;
1446}
c79dd5b5 1447int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1448{
bb8c093b 1449 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
b481de9c
ZY		 1450 return -EINVAL;
1451}
1452
1453static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
1454{
1455 s32 sign = 1;
1456
1457 if (num < 0) {
1458 sign = -sign;
1459 num = -num;
1460 }
1461 if (denom < 0) {
1462 sign = -sign;
1463 denom = -denom;
1464 }
1465 *res = 1;
1466 *res = ((num * 2 + denom) / (denom * 2)) * sign;
1467
1468 return 1;
1469}
1470
8b6eaea8
BC		 1471/**
1472 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
1473 *
1474 * Determines power supply voltage compensation for txpower calculations.
1475 * Returns number of 1/2-dB steps to subtract from gain table index,
1476 * to compensate for difference between power supply voltage during
1477 * factory measurements, vs. current power supply voltage.
1478 *
1479 * Voltage indication is higher for lower voltage.
1480 * Lower voltage requires more gain (lower gain table index).
1481 */
b481de9c
ZY		 1482static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
1483 s32 current_voltage)
1484{
1485 s32 comp = 0;
1486
1487 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
1488 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
1489 return 0;
1490
1491 iwl4965_math_div_round(current_voltage - eeprom_voltage,
1492 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
1493
1494 if (current_voltage > eeprom_voltage)
1495 comp *= 2;
1496 if ((comp < -2) || (comp > 2))
1497 comp = 0;
1498
1499 return comp;
1500}
1501
bf85ea4f 1502static const struct iwl_channel_info *
c79dd5b5 1503iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
8318d78a 1504 enum ieee80211_band band, u16 channel)
b481de9c 1505{
bf85ea4f 1506 const struct iwl_channel_info *ch_info;
b481de9c 1507
8622e705 1508 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 1509
1510 if (!is_channel_valid(ch_info))
1511 return NULL;
1512
1513 return ch_info;
1514}
1515
1516static s32 iwl4965_get_tx_atten_grp(u16 channel)
1517{
1518 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1519 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1520 return CALIB_CH_GROUP_5;
1521
1522 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1523 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1524 return CALIB_CH_GROUP_1;
1525
1526 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1527 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1528 return CALIB_CH_GROUP_2;
1529
1530 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1531 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1532 return CALIB_CH_GROUP_3;
1533
1534 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1535 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1536 return CALIB_CH_GROUP_4;
1537
1538 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1539 return -1;
1540}
1541
c79dd5b5 1542static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 1543{
1544 s32 b = -1;
1545
1546 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
073d3f5f 1547 if (priv->calib_info->band_info[b].ch_from == 0)
b481de9c
ZY		 1548 continue;
1549
073d3f5f
TW		 1550 if ((channel >= priv->calib_info->band_info[b].ch_from)
1551 && (channel <= priv->calib_info->band_info[b].ch_to))
b481de9c
ZY		 1552 break;
1553 }
1554
1555 return b;
1556}
1557
1558static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1559{
1560 s32 val;
1561
1562 if (x2 == x1)
1563 return y1;
1564 else {
1565 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
1566 return val + y2;
1567 }
1568}
1569
8b6eaea8
BC		 1570/**
1571 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
1572 *
1573 * Interpolates factory measurements from the two sample channels within a
1574 * sub-band, to apply to channel of interest. Interpolation is proportional to
1575 * differences in channel frequencies, which is proportional to differences
1576 * in channel number.
1577 */
c79dd5b5 1578static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
073d3f5f 1579 struct iwl_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 1580{
1581 s32 s = -1;
1582 u32 c;
1583 u32 m;
073d3f5f
TW		 1584 const struct iwl_eeprom_calib_measure *m1;
1585 const struct iwl_eeprom_calib_measure *m2;
1586 struct iwl_eeprom_calib_measure *omeas;
b481de9c
ZY		 1587 u32 ch_i1;
1588 u32 ch_i2;
1589
1590 s = iwl4965_get_sub_band(priv, channel);
1591 if (s >= EEPROM_TX_POWER_BANDS) {
1592 IWL_ERROR("Tx Power can not find channel %d ", channel);
1593 return -1;
1594 }
1595
073d3f5f
TW		 1596 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
1597 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
b481de9c
ZY		 1598 chan_info->ch_num = (u8) channel;
1599
1600 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1601 channel, s, ch_i1, ch_i2);
1602
1603 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1604 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
073d3f5f 1605 m1 = &(priv->calib_info->band_info[s].ch1.
b481de9c 1606 measurements[c][m]);
073d3f5f 1607 m2 = &(priv->calib_info->band_info[s].ch2.
b481de9c
ZY		 1608 measurements[c][m]);
1609 omeas = &(chan_info->measurements[c][m]);
1610
1611 omeas->actual_pow =
1612 (u8) iwl4965_interpolate_value(channel, ch_i1,
1613 m1->actual_pow,
1614 ch_i2,
1615 m2->actual_pow);
1616 omeas->gain_idx =
1617 (u8) iwl4965_interpolate_value(channel, ch_i1,
1618 m1->gain_idx, ch_i2,
1619 m2->gain_idx);
1620 omeas->temperature =
1621 (u8) iwl4965_interpolate_value(channel, ch_i1,
1622 m1->temperature,
1623 ch_i2,
1624 m2->temperature);
1625 omeas->pa_det =
1626 (s8) iwl4965_interpolate_value(channel, ch_i1,
1627 m1->pa_det, ch_i2,
1628 m2->pa_det);
1629
1630 IWL_DEBUG_TXPOWER
1631 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1632 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1633 IWL_DEBUG_TXPOWER
1634 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1635 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1636 IWL_DEBUG_TXPOWER
1637 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1638 m1->pa_det, m2->pa_det, omeas->pa_det);
1639 IWL_DEBUG_TXPOWER
1640 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1641 m1->temperature, m2->temperature,
1642 omeas->temperature);
1643 }
1644 }
1645
1646 return 0;
1647}
1648
1649/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1650 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1651static s32 back_off_table[] = {
1652 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1653 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1654 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1655 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1656 10 /* CCK */
1657};
1658
1659/* Thermal compensation values for txpower for various frequency ranges ...
1660 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 1661static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 1662 s32 degrees_per_05db_a;
1663 s32 degrees_per_05db_a_denom;
1664} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1665 {9, 2}, /* group 0 5.2, ch 34-43 */
1666 {4, 1}, /* group 1 5.2, ch 44-70 */
1667 {4, 1}, /* group 2 5.2, ch 71-124 */
1668 {4, 1}, /* group 3 5.2, ch 125-200 */
1669 {3, 1} /* group 4 2.4, ch all */
1670};
1671
1672static s32 get_min_power_index(s32 rate_power_index, u32 band)
1673{
1674 if (!band) {
1675 if ((rate_power_index & 7) <= 4)
1676 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1677 }
1678 return MIN_TX_GAIN_INDEX;
1679}
1680
1681struct gain_entry {
1682 u8 dsp;
1683 u8 radio;
1684};
1685
1686static const struct gain_entry gain_table[2][108] = {
1687 /* 5.2GHz power gain index table */
1688 {
1689 {123, 0x3F}, /* highest txpower */
1690 {117, 0x3F},
1691 {110, 0x3F},
1692 {104, 0x3F},
1693 {98, 0x3F},
1694 {110, 0x3E},
1695 {104, 0x3E},
1696 {98, 0x3E},
1697 {110, 0x3D},
1698 {104, 0x3D},
1699 {98, 0x3D},
1700 {110, 0x3C},
1701 {104, 0x3C},
1702 {98, 0x3C},
1703 {110, 0x3B},
1704 {104, 0x3B},
1705 {98, 0x3B},
1706 {110, 0x3A},
1707 {104, 0x3A},
1708 {98, 0x3A},
1709 {110, 0x39},
1710 {104, 0x39},
1711 {98, 0x39},
1712 {110, 0x38},
1713 {104, 0x38},
1714 {98, 0x38},
1715 {110, 0x37},
1716 {104, 0x37},
1717 {98, 0x37},
1718 {110, 0x36},
1719 {104, 0x36},
1720 {98, 0x36},
1721 {110, 0x35},
1722 {104, 0x35},
1723 {98, 0x35},
1724 {110, 0x34},
1725 {104, 0x34},
1726 {98, 0x34},
1727 {110, 0x33},
1728 {104, 0x33},
1729 {98, 0x33},
1730 {110, 0x32},
1731 {104, 0x32},
1732 {98, 0x32},
1733 {110, 0x31},
1734 {104, 0x31},
1735 {98, 0x31},
1736 {110, 0x30},
1737 {104, 0x30},
1738 {98, 0x30},
1739 {110, 0x25},
1740 {104, 0x25},
1741 {98, 0x25},
1742 {110, 0x24},
1743 {104, 0x24},
1744 {98, 0x24},
1745 {110, 0x23},
1746 {104, 0x23},
1747 {98, 0x23},
1748 {110, 0x22},
1749 {104, 0x18},
1750 {98, 0x18},
1751 {110, 0x17},
1752 {104, 0x17},
1753 {98, 0x17},
1754 {110, 0x16},
1755 {104, 0x16},
1756 {98, 0x16},
1757 {110, 0x15},
1758 {104, 0x15},
1759 {98, 0x15},
1760 {110, 0x14},
1761 {104, 0x14},
1762 {98, 0x14},
1763 {110, 0x13},
1764 {104, 0x13},
1765 {98, 0x13},
1766 {110, 0x12},
1767 {104, 0x08},
1768 {98, 0x08},
1769 {110, 0x07},
1770 {104, 0x07},
1771 {98, 0x07},
1772 {110, 0x06},
1773 {104, 0x06},
1774 {98, 0x06},
1775 {110, 0x05},
1776 {104, 0x05},
1777 {98, 0x05},
1778 {110, 0x04},
1779 {104, 0x04},
1780 {98, 0x04},
1781 {110, 0x03},
1782 {104, 0x03},
1783 {98, 0x03},
1784 {110, 0x02},
1785 {104, 0x02},
1786 {98, 0x02},
1787 {110, 0x01},
1788 {104, 0x01},
1789 {98, 0x01},
1790 {110, 0x00},
1791 {104, 0x00},
1792 {98, 0x00},
1793 {93, 0x00},
1794 {88, 0x00},
1795 {83, 0x00},
1796 {78, 0x00},
1797 },
1798 /* 2.4GHz power gain index table */
1799 {
1800 {110, 0x3f}, /* highest txpower */
1801 {104, 0x3f},
1802 {98, 0x3f},
1803 {110, 0x3e},
1804 {104, 0x3e},
1805 {98, 0x3e},
1806 {110, 0x3d},
1807 {104, 0x3d},
1808 {98, 0x3d},
1809 {110, 0x3c},
1810 {104, 0x3c},
1811 {98, 0x3c},
1812 {110, 0x3b},
1813 {104, 0x3b},
1814 {98, 0x3b},
1815 {110, 0x3a},
1816 {104, 0x3a},
1817 {98, 0x3a},
1818 {110, 0x39},
1819 {104, 0x39},
1820 {98, 0x39},
1821 {110, 0x38},
1822 {104, 0x38},
1823 {98, 0x38},
1824 {110, 0x37},
1825 {104, 0x37},
1826 {98, 0x37},
1827 {110, 0x36},
1828 {104, 0x36},
1829 {98, 0x36},
1830 {110, 0x35},
1831 {104, 0x35},
1832 {98, 0x35},
1833 {110, 0x34},
1834 {104, 0x34},
1835 {98, 0x34},
1836 {110, 0x33},
1837 {104, 0x33},
1838 {98, 0x33},
1839 {110, 0x32},
1840 {104, 0x32},
1841 {98, 0x32},
1842 {110, 0x31},
1843 {104, 0x31},
1844 {98, 0x31},
1845 {110, 0x30},
1846 {104, 0x30},
1847 {98, 0x30},
1848 {110, 0x6},
1849 {104, 0x6},
1850 {98, 0x6},
1851 {110, 0x5},
1852 {104, 0x5},
1853 {98, 0x5},
1854 {110, 0x4},
1855 {104, 0x4},
1856 {98, 0x4},
1857 {110, 0x3},
1858 {104, 0x3},
1859 {98, 0x3},
1860 {110, 0x2},
1861 {104, 0x2},
1862 {98, 0x2},
1863 {110, 0x1},
1864 {104, 0x1},
1865 {98, 0x1},
1866 {110, 0x0},
1867 {104, 0x0},
1868 {98, 0x0},
1869 {97, 0},
1870 {96, 0},
1871 {95, 0},
1872 {94, 0},
1873 {93, 0},
1874 {92, 0},
1875 {91, 0},
1876 {90, 0},
1877 {89, 0},
1878 {88, 0},
1879 {87, 0},
1880 {86, 0},
1881 {85, 0},
1882 {84, 0},
1883 {83, 0},
1884 {82, 0},
1885 {81, 0},
1886 {80, 0},
1887 {79, 0},
1888 {78, 0},
1889 {77, 0},
1890 {76, 0},
1891 {75, 0},
1892 {74, 0},
1893 {73, 0},
1894 {72, 0},
1895 {71, 0},
1896 {70, 0},
1897 {69, 0},
1898 {68, 0},
1899 {67, 0},
1900 {66, 0},
1901 {65, 0},
1902 {64, 0},
1903 {63, 0},
1904 {62, 0},
1905 {61, 0},
1906 {60, 0},
1907 {59, 0},
1908 }
1909};
1910
c79dd5b5 1911static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 1912 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 1913 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 1914{
1915 u8 saturation_power;
1916 s32 target_power;
1917 s32 user_target_power;
1918 s32 power_limit;
1919 s32 current_temp;
1920 s32 reg_limit;
1921 s32 current_regulatory;
1922 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1923 int i;
1924 int c;
bf85ea4f 1925 const struct iwl_channel_info *ch_info = NULL;
073d3f5f
TW		 1926 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1927 const struct iwl_eeprom_calib_measure *measurement;
b481de9c
ZY		 1928 s16 voltage;
1929 s32 init_voltage;
1930 s32 voltage_compensation;
1931 s32 degrees_per_05db_num;
1932 s32 degrees_per_05db_denom;
1933 s32 factory_temp;
1934 s32 temperature_comp[2];
1935 s32 factory_gain_index[2];
1936 s32 factory_actual_pwr[2];
1937 s32 power_index;
1938
1939 /* Sanity check requested level (dBm) */
1940 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
1941 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
1942 priv->user_txpower_limit);
1943 return -EINVAL;
1944 }
1945 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
1946 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1947 priv->user_txpower_limit);
1948 return -EINVAL;
1949 }
1950
1951 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1952 * are used for indexing into txpower table) */
1953 user_target_power = 2 * priv->user_txpower_limit;
1954
1955 /* Get current (RXON) channel, band, width */
1956 ch_info =
8318d78a 1957 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
b481de9c
ZY		 1958
1959 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1960 is_fat);
1961
1962 if (!ch_info)
1963 return -EINVAL;
1964
1965 /* get txatten group, used to select 1) thermal txpower adjustment
1966 * and 2) mimo txpower balance between Tx chains. */
1967 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1968 if (txatten_grp < 0)
1969 return -EINVAL;
1970
1971 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1972 channel, txatten_grp);
1973
1974 if (is_fat) {
1975 if (ctrl_chan_high)
1976 channel -= 2;
1977 else
1978 channel += 2;
1979 }
1980
1981 /* hardware txpower limits ...
1982 * saturation (clipping distortion) txpowers are in half-dBm */
1983 if (band)
073d3f5f 1984 saturation_power = priv->calib_info->saturation_power24;
b481de9c 1985 else
073d3f5f 1986 saturation_power = priv->calib_info->saturation_power52;
b481de9c
ZY		 1987
1988 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1989 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1990 if (band)
1991 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1992 else
1993 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1994 }
1995
1996 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1997 * max_power_avg values are in dBm, convert * 2 */
1998 if (is_fat)
1999 reg_limit = ch_info->fat_max_power_avg * 2;
2000 else
2001 reg_limit = ch_info->max_power_avg * 2;
2002
2003 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
2004 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
2005 if (band)
2006 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
2007 else
2008 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
2009 }
2010
2011 /* Interpolate txpower calibration values for this channel,
2012 * based on factory calibration tests on spaced channels. */
2013 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2014
2015 /* calculate tx gain adjustment based on power supply voltage */
073d3f5f 2016 voltage = priv->calib_info->voltage;
b481de9c
ZY		 2017 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2018 voltage_compensation =
2019 iwl4965_get_voltage_compensation(voltage, init_voltage);
2020
2021 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
2022 init_voltage,
2023 voltage, voltage_compensation);
2024
2025 /* get current temperature (Celsius) */
2026 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
2027 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
2028 current_temp = KELVIN_TO_CELSIUS(current_temp);
2029
2030 /* select thermal txpower adjustment params, based on channel group
2031 * (same frequency group used for mimo txatten adjustment) */
2032 degrees_per_05db_num =
2033 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
2034 degrees_per_05db_denom =
2035 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
2036
2037 /* get per-chain txpower values from factory measurements */
2038 for (c = 0; c < 2; c++) {
2039 measurement = &ch_eeprom_info.measurements[c][1];
2040
2041 /* txgain adjustment (in half-dB steps) based on difference
2042 * between factory and current temperature */
2043 factory_temp = measurement->temperature;
2044 iwl4965_math_div_round((current_temp - factory_temp) *
2045 degrees_per_05db_denom,
2046 degrees_per_05db_num,
2047 &temperature_comp[c]);
2048
2049 factory_gain_index[c] = measurement->gain_idx;
2050 factory_actual_pwr[c] = measurement->actual_pow;
2051
2052 IWL_DEBUG_TXPOWER("chain = %d\n", c);
2053 IWL_DEBUG_TXPOWER("fctry tmp %d, "
2054 "curr tmp %d, comp %d steps\n",
2055 factory_temp, current_temp,
2056 temperature_comp[c]);
2057
2058 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
2059 factory_gain_index[c],
2060 factory_actual_pwr[c]);
2061 }
2062
2063 /* for each of 33 bit-rates (including 1 for CCK) */
2064 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
2065 u8 is_mimo_rate;
bb8c093b 2066 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 2067
2068 /* for mimo, reduce each chain's txpower by half
2069 * (3dB, 6 steps), so total output power is regulatory
2070 * compliant. */
2071 if (i & 0x8) {
2072 current_regulatory = reg_limit -
2073 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
2074 is_mimo_rate = 1;
2075 } else {
2076 current_regulatory = reg_limit;
2077 is_mimo_rate = 0;
2078 }
2079
2080 /* find txpower limit, either hardware or regulatory */
2081 power_limit = saturation_power - back_off_table[i];
2082 if (power_limit > current_regulatory)
2083 power_limit = current_regulatory;
2084
2085 /* reduce user's txpower request if necessary
2086 * for this rate on this channel */
2087 target_power = user_target_power;
2088 if (target_power > power_limit)
2089 target_power = power_limit;
2090
2091 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
2092 i, saturation_power - back_off_table[i],
2093 current_regulatory, user_target_power,
2094 target_power);
2095
2096 /* for each of 2 Tx chains (radio transmitters) */
2097 for (c = 0; c < 2; c++) {
2098 s32 atten_value;
2099
2100 if (is_mimo_rate)
2101 atten_value =
2102 (s32)le32_to_cpu(priv->card_alive_init.
2103 tx_atten[txatten_grp][c]);
2104 else
2105 atten_value = 0;
2106
2107 /* calculate index; higher index means lower txpower */
2108 power_index = (u8) (factory_gain_index[c] -
2109 (target_power -
2110 factory_actual_pwr[c]) -
2111 temperature_comp[c] -
2112 voltage_compensation +
2113 atten_value);
2114
2115/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
2116 power_index); */
2117
2118 if (power_index < get_min_power_index(i, band))
2119 power_index = get_min_power_index(i, band);
2120
2121 /* adjust 5 GHz index to support negative indexes */
2122 if (!band)
2123 power_index += 9;
2124
2125 /* CCK, rate 32, reduce txpower for CCK */
2126 if (i == POWER_TABLE_CCK_ENTRY)
2127 power_index +=
2128 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
2129
2130 /* stay within the table! */
2131 if (power_index > 107) {
2132 IWL_WARNING("txpower index %d > 107\n",
2133 power_index);
2134 power_index = 107;
2135 }
2136 if (power_index < 0) {
2137 IWL_WARNING("txpower index %d < 0\n",
2138 power_index);
2139 power_index = 0;
2140 }
2141
2142 /* fill txpower command for this rate/chain */
2143 tx_power.s.radio_tx_gain[c] =
2144 gain_table[band][power_index].radio;
2145 tx_power.s.dsp_predis_atten[c] =
2146 gain_table[band][power_index].dsp;
2147
2148 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
2149 "gain 0x%02x dsp %d\n",
2150 c, atten_value, power_index,
2151 tx_power.s.radio_tx_gain[c],
2152 tx_power.s.dsp_predis_atten[c]);
2153 }/* for each chain */
2154
2155 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
2156
2157 }/* for each rate */
2158
2159 return 0;
2160}
2161
2162/**
bb8c093b 2163 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
b481de9c
ZY		 2164 *
2165 * Uses the active RXON for channel, band, and characteristics (fat, high)
2166 * The power limit is taken from priv->user_txpower_limit.
2167 */
c79dd5b5 2168int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
b481de9c 2169{
bb8c093b 2170 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 2171 int ret;
b481de9c
ZY		 2172 u8 band = 0;
2173 u8 is_fat = 0;
2174 u8 ctrl_chan_high = 0;
2175
2176 if (test_bit(STATUS_SCANNING, &priv->status)) {
2177 /* If this gets hit a lot, switch it to a BUG() and catch
2178 * the stack trace to find out who is calling this during
2179 * a scan. */
2180 IWL_WARNING("TX Power requested while scanning!\n");
2181 return -EAGAIN;
2182 }
2183
8318d78a 2184 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 2185
2186 is_fat = is_fat_channel(priv->active_rxon.flags);
2187
2188 if (is_fat &&
2189 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2190 ctrl_chan_high = 1;
2191
2192 cmd.band = band;
2193 cmd.channel = priv->active_rxon.channel;
2194
857485c0 2195 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 2196 le16_to_cpu(priv->active_rxon.channel),
2197 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 2198 if (ret)
2199 goto out;
b481de9c 2200
857485c0
TW		 2201 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
2202
2203out:
2204 return ret;
b481de9c
ZY		 2205}
2206
7e8c519e
TW		 2207static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
2208{
2209 int ret = 0;
2210 struct iwl4965_rxon_assoc_cmd rxon_assoc;
2211 const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
2212 const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
2213
2214 if ((rxon1->flags == rxon2->flags) &&
2215 (rxon1->filter_flags == rxon2->filter_flags) &&
2216 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
2217 (rxon1->ofdm_ht_single_stream_basic_rates ==
2218 rxon2->ofdm_ht_single_stream_basic_rates) &&
2219 (rxon1->ofdm_ht_dual_stream_basic_rates ==
2220 rxon2->ofdm_ht_dual_stream_basic_rates) &&
2221 (rxon1->rx_chain == rxon2->rx_chain) &&
2222 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
2223 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
2224 return 0;
2225 }
2226
2227 rxon_assoc.flags = priv->staging_rxon.flags;
2228 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
2229 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
2230 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
2231 rxon_assoc.reserved = 0;
2232 rxon_assoc.ofdm_ht_single_stream_basic_rates =
2233 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
2234 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
2235 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
2236 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
2237
2238 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
2239 sizeof(rxon_assoc), &rxon_assoc, NULL);
2240 if (ret)
2241 return ret;
2242
2243 return ret;
2244}
2245
2246
c79dd5b5 2247int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 2248{
2249 int rc;
2250 u8 band = 0;
2251 u8 is_fat = 0;
2252 u8 ctrl_chan_high = 0;
bb8c093b 2253 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 2254 const struct iwl_channel_info *ch_info;
b481de9c 2255
8318d78a 2256 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 2257
8622e705 2258 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 2259
2260 is_fat = is_fat_channel(priv->staging_rxon.flags);
2261
2262 if (is_fat &&
2263 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2264 ctrl_chan_high = 1;
2265
2266 cmd.band = band;
2267 cmd.expect_beacon = 0;
2268 cmd.channel = cpu_to_le16(channel);
2269 cmd.rxon_flags = priv->active_rxon.flags;
2270 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2271 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2272 if (ch_info)
2273 cmd.expect_beacon = is_channel_radar(ch_info);
2274 else
2275 cmd.expect_beacon = 1;
2276
2277 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2278 ctrl_chan_high, &cmd.tx_power);
2279 if (rc) {
2280 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2281 return rc;
2282 }
2283
857485c0 2284 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 2285 return rc;
2286}
2287
2288#define RTS_HCCA_RETRY_LIMIT 3
2289#define RTS_DFAULT_RETRY_LIMIT 60
2290
c79dd5b5 2291void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
857485c0 2292 struct iwl_cmd *cmd,
b481de9c
ZY		 2293 struct ieee80211_tx_control *ctrl,
2294 struct ieee80211_hdr *hdr, int sta_id,
2295 int is_hcca)
2296{
87e4f7df 2297 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
b481de9c
ZY		 2298 u8 rts_retry_limit = 0;
2299 u8 data_retry_limit = 0;
b481de9c 2300 u16 fc = le16_to_cpu(hdr->frame_control);
87e4f7df
TW		 2301 u8 rate_plcp;
2302 u16 rate_flags = 0;
8318d78a 2303 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c 2304
87e4f7df 2305 rate_plcp = iwl4965_rates[rate_idx].plcp;
b481de9c
ZY		 2306
2307 rts_retry_limit = (is_hcca) ?
2308 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2309
87e4f7df
TW		 2310 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2311 rate_flags |= RATE_MCS_CCK_MSK;
2312
2313
b481de9c
ZY		 2314 if (ieee80211_is_probe_response(fc)) {
2315 data_retry_limit = 3;
2316 if (data_retry_limit < rts_retry_limit)
2317 rts_retry_limit = data_retry_limit;
2318 } else
2319 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2320
2321 if (priv->data_retry_limit != -1)
2322 data_retry_limit = priv->data_retry_limit;
2323
87e4f7df
TW		 2324
2325 if (ieee80211_is_data(fc)) {
2326 tx->initial_rate_index = 0;
2327 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2328 } else {
b481de9c
ZY		 2329 switch (fc & IEEE80211_FCTL_STYPE) {
2330 case IEEE80211_STYPE_AUTH:
2331 case IEEE80211_STYPE_DEAUTH:
2332 case IEEE80211_STYPE_ASSOC_REQ:
2333 case IEEE80211_STYPE_REASSOC_REQ:
87e4f7df
TW		 2334 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2335 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2336 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
b481de9c
ZY		 2337 }
2338 break;
2339 default:
2340 break;
2341 }
87e4f7df
TW		 2342
2343 /* Alternate between antenna A and B for successive frames */
2344 if (priv->use_ant_b_for_management_frame) {
2345 priv->use_ant_b_for_management_frame = 0;
2346 rate_flags |= RATE_MCS_ANT_B_MSK;
2347 } else {
2348 priv->use_ant_b_for_management_frame = 1;
2349 rate_flags |= RATE_MCS_ANT_A_MSK;
2350 }
b481de9c
ZY		 2351 }
2352
87e4f7df
TW		 2353 tx->rts_retry_limit = rts_retry_limit;
2354 tx->data_retry_limit = data_retry_limit;
2355 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
b481de9c
ZY		 2356}
2357
c79dd5b5 2358int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
b481de9c 2359{
059ff826
TW		 2360 struct iwl4965_shared *s = priv->shared_virt;
2361 return le32_to_cpu(s->rb_closed) & 0xFFF;
b481de9c
ZY		 2362}
2363
c79dd5b5 2364int iwl4965_hw_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 2365{
2366 return priv->temperature;
2367}
2368
c79dd5b5 2369unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2370 struct iwl4965_frame *frame, u8 rate)
b481de9c 2371{
bb8c093b 2372 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2373 unsigned int frame_size;
2374
2375 tx_beacon_cmd = &frame->u.beacon;
2376 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2377
5425e490 2378 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2379 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2380
bb8c093b 2381 frame_size = iwl4965_fill_beacon_frame(priv,
b481de9c 2382 tx_beacon_cmd->frame,
bb8c093b 2383 iwl4965_broadcast_addr,
b481de9c
ZY		 2384 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2385
2386 BUG_ON(frame_size > MAX_MPDU_SIZE);
2387 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2388
2389 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2390 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 2391 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
b481de9c
ZY		 2392 else
2393 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 2394 iwl4965_hw_set_rate_n_flags(rate, 0);
b481de9c
ZY		 2395
2396 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2397 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2398 return (sizeof(*tx_beacon_cmd) + frame_size);
2399}
2400
8b6eaea8
BC		 2401/*
2402 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2403 * given Tx queue, and enable the DMA channel used for that queue.
2404 *
2405 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2406 * channels supported in hardware.
2407 */
c79dd5b5 2408int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c
ZY		 2409{
2410 int rc;
2411 unsigned long flags;
2412 int txq_id = txq->q.id;
2413
2414 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 2415 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2416 if (rc) {
2417 spin_unlock_irqrestore(&priv->lock, flags);
2418 return rc;
2419 }
2420
8b6eaea8 2421 /* Circular buffer (TFD queue in DRAM) physical base address */
3395f6e9 2422 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
b481de9c 2423 txq->q.dma_addr >> 8);
8b6eaea8
BC		 2424
2425 /* Enable DMA channel, using same id as for TFD queue */
3395f6e9 2426 iwl_write_direct32(
b481de9c
ZY		 2427 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2428 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2429 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
3395f6e9 2430 iwl_release_nic_access(priv);
b481de9c
ZY		 2431 spin_unlock_irqrestore(&priv->lock, flags);
2432
2433 return 0;
2434}
2435
c79dd5b5 2436int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
b481de9c
ZY		 2437 dma_addr_t addr, u16 len)
2438{
2439 int index, is_odd;
bb8c093b 2440 struct iwl4965_tfd_frame *tfd = ptr;
b481de9c
ZY		 2441 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2442
8b6eaea8 2443 /* Each TFD can point to a maximum 20 Tx buffers */
b481de9c
ZY		 2444 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2445 IWL_ERROR("Error can not send more than %d chunks\n",
2446 MAX_NUM_OF_TBS);
2447 return -EINVAL;
2448 }
2449
2450 index = num_tbs / 2;
2451 is_odd = num_tbs & 0x1;
2452
2453 if (!is_odd) {
2454 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2455 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
6a218f6f 2456 iwl_get_dma_hi_address(addr));
b481de9c
ZY		 2457 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2458 } else {
2459 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2460 (u32) (addr & 0xffff));
2461 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2462 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2463 }
2464
2465 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2466
2467 return 0;
2468}
2469
c79dd5b5 2470static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
b481de9c 2471{
073d3f5f 2472 u16 hw_version = iwl_eeprom_query16(priv, EEPROM_4965_BOARD_REVISION);
b481de9c
ZY		 2473
2474 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2475 ((hw_version >> 8) & 0x0F),
2476 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2477
2478 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
073d3f5f 2479 &priv->eeprom[EEPROM_4965_BOARD_PBA]);
b481de9c
ZY		 2480}
2481
2482#define IWL_TX_CRC_SIZE 4
2483#define IWL_TX_DELIMITER_SIZE 4
2484
8b6eaea8 2485/**
e2a722eb 2486 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
8b6eaea8 2487 */
e2a722eb
TW		 2488static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
2489 struct iwl4965_tx_queue *txq,
2490 u16 byte_cnt)
b481de9c
ZY		 2491{
2492 int len;
2493 int txq_id = txq->q.id;
059ff826 2494 struct iwl4965_shared *shared_data = priv->shared_virt;
b481de9c 2495
b481de9c
ZY		 2496 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2497
8b6eaea8 2498 /* Set up byte count within first 256 entries */
b481de9c 2499 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 2500 tfd_offset[txq->q.write_ptr], byte_cnt, len);
b481de9c 2501
8b6eaea8 2502 /* If within first 64 entries, duplicate at end */
fc4b6853 2503 if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
b481de9c 2504 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 2505 tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
b481de9c 2506 byte_cnt, len);
b481de9c
ZY		 2507}
2508
8b6eaea8
BC		 2509/**
2510 * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2511 *
2512 * Selects how many and which Rx receivers/antennas/chains to use.
2513 * This should not be used for scan command ... it puts data in wrong place.
2514 */
c79dd5b5 2515void iwl4965_set_rxon_chain(struct iwl_priv *priv)
b481de9c 2516{
fde0db31 2517 u8 is_single = is_single_rx_stream(priv);
b481de9c
ZY		 2518 u8 idle_state, rx_state;
2519
2520 priv->staging_rxon.rx_chain = 0;
2521 rx_state = idle_state = 3;
2522
2523 /* Tell uCode which antennas are actually connected.
2524 * Before first association, we assume all antennas are connected.
f0832f13 2525 * Just after first association, iwl_chain_noise_calibration()
b481de9c
ZY		 2526 * checks which antennas actually *are* connected. */
2527 priv->staging_rxon.rx_chain |=
fde0db31
GC		 2528 cpu_to_le16(priv->hw_params.valid_rx_ant <<
2529 RXON_RX_CHAIN_VALID_POS);
b481de9c
ZY		 2530
2531 /* How many receivers should we use? */
2532 iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
2533 priv->staging_rxon.rx_chain |=
2534 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
2535 priv->staging_rxon.rx_chain |=
2536 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
2537
2538 if (!is_single && (rx_state >= 2) &&
2539 !test_bit(STATUS_POWER_PMI, &priv->status))
2540 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2541 else
2542 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2543
2544 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
2545}
2546
b481de9c
ZY		 2547/**
2548 * sign_extend - Sign extend a value using specified bit as sign-bit
2549 *
2550 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
2551 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
2552 *
2553 * @param oper value to sign extend
2554 * @param index 0 based bit index (0<=index<32) to sign bit
2555 */
2556static s32 sign_extend(u32 oper, int index)
2557{
2558 u8 shift = 31 - index;
2559
2560 return (s32)(oper << shift) >> shift;
2561}
2562
2563/**
2564 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
2565 * @statistics: Provides the temperature reading from the uCode
2566 *
2567 * A return of <0 indicates bogus data in the statistics
2568 */
c79dd5b5 2569int iwl4965_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 2570{
2571 s32 temperature;
2572 s32 vt;
2573 s32 R1, R2, R3;
2574 u32 R4;
2575
2576 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
2577 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
2578 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
2579 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
2580 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
2581 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
2582 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
2583 } else {
2584 IWL_DEBUG_TEMP("Running temperature calibration\n");
2585 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
2586 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
2587 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
2588 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
2589 }
2590
2591 /*
8b6eaea8 2592 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 2593 *
2594 * NOTE If we haven't received a statistics notification yet
2595 * with an updated temperature, use R4 provided to us in the
8b6eaea8
BC		 2596 * "initialize" ALIVE response.
2597 */
b481de9c
ZY		 2598 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
2599 vt = sign_extend(R4, 23);
2600 else
2601 vt = sign_extend(
2602 le32_to_cpu(priv->statistics.general.temperature), 23);
2603
2604 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
2605 R1, R2, R3, vt);
2606
2607 if (R3 == R1) {
2608 IWL_ERROR("Calibration conflict R1 == R3\n");
2609 return -1;
2610 }
2611
2612 /* Calculate temperature in degrees Kelvin, adjust by 97%.
2613 * Add offset to center the adjustment around 0 degrees Centigrade. */
2614 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
2615 temperature /= (R3 - R1);
2616 temperature = (temperature * 97) / 100 +
2617 TEMPERATURE_CALIB_KELVIN_OFFSET;
2618
2619 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
2620 KELVIN_TO_CELSIUS(temperature));
2621
2622 return temperature;
2623}
2624
2625/* Adjust Txpower only if temperature variance is greater than threshold. */
2626#define IWL_TEMPERATURE_THRESHOLD 3
2627
2628/**
2629 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
2630 *
2631 * If the temperature changed has changed sufficiently, then a recalibration
2632 * is needed.
2633 *
2634 * Assumes caller will replace priv->last_temperature once calibration
2635 * executed.
2636 */
c79dd5b5 2637static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 2638{
2639 int temp_diff;
2640
2641 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
2642 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
2643 return 0;
2644 }
2645
2646 temp_diff = priv->temperature - priv->last_temperature;
2647
2648 /* get absolute value */
2649 if (temp_diff < 0) {
2650 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
2651 temp_diff = -temp_diff;
2652 } else if (temp_diff == 0)
2653 IWL_DEBUG_POWER("Same temp, \n");
2654 else
2655 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
2656
2657 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
2658 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
2659 return 0;
2660 }
2661
2662 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
2663
2664 return 1;
2665}
2666
2667/* Calculate noise level, based on measurements during network silence just
2668 * before arriving beacon. This measurement can be done only if we know
2669 * exactly when to expect beacons, therefore only when we're associated. */
c79dd5b5 2670static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
b481de9c
ZY		 2671{
2672 struct statistics_rx_non_phy *rx_info
2673 = &(priv->statistics.rx.general);
2674 int num_active_rx = 0;
2675 int total_silence = 0;
2676 int bcn_silence_a =
2677 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
2678 int bcn_silence_b =
2679 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
2680 int bcn_silence_c =
2681 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
2682
2683 if (bcn_silence_a) {
2684 total_silence += bcn_silence_a;
2685 num_active_rx++;
2686 }
2687 if (bcn_silence_b) {
2688 total_silence += bcn_silence_b;
2689 num_active_rx++;
2690 }
2691 if (bcn_silence_c) {
2692 total_silence += bcn_silence_c;
2693 num_active_rx++;
2694 }
2695
2696 /* Average among active antennas */
2697 if (num_active_rx)
2698 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
2699 else
2700 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2701
2702 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
2703 bcn_silence_a, bcn_silence_b, bcn_silence_c,
2704 priv->last_rx_noise);
2705}
2706
c79dd5b5 2707void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
b481de9c 2708{
bb8c093b 2709 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 2710 int change;
2711 s32 temp;
2712
2713 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
2714 (int)sizeof(priv->statistics), pkt->len);
2715
2716 change = ((priv->statistics.general.temperature !=
2717 pkt->u.stats.general.temperature) ||
2718 ((priv->statistics.flag &
2719 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
2720 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
2721
2722 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
2723
2724 set_bit(STATUS_STATISTICS, &priv->status);
2725
2726 /* Reschedule the statistics timer to occur in
2727 * REG_RECALIB_PERIOD seconds to ensure we get a
2728 * thermal update even if the uCode doesn't give
2729 * us one */
2730 mod_timer(&priv->statistics_periodic, jiffies +
2731 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
2732
2733 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2734 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
2735 iwl4965_rx_calc_noise(priv);
f0832f13 2736#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 2737 queue_work(priv->workqueue, &priv->sensitivity_work);
2738#endif
2739 }
2740
ab53d8af
MA		 2741 iwl_leds_background(priv);
2742
b481de9c
ZY		 2743 /* If the hardware hasn't reported a change in
2744 * temperature then don't bother computing a
2745 * calibrated temperature value */
2746 if (!change)
2747 return;
2748
2749 temp = iwl4965_get_temperature(priv);
2750 if (temp < 0)
2751 return;
2752
2753 if (priv->temperature != temp) {
2754 if (priv->temperature)
2755 IWL_DEBUG_TEMP("Temperature changed "
2756 "from %dC to %dC\n",
2757 KELVIN_TO_CELSIUS(priv->temperature),
2758 KELVIN_TO_CELSIUS(temp));
2759 else
2760 IWL_DEBUG_TEMP("Temperature "
2761 "initialized to %dC\n",
2762 KELVIN_TO_CELSIUS(temp));
2763 }
2764
2765 priv->temperature = temp;
2766 set_bit(STATUS_TEMPERATURE, &priv->status);
2767
2768 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2769 iwl4965_is_temp_calib_needed(priv))
2770 queue_work(priv->workqueue, &priv->txpower_work);
2771}
2772
c79dd5b5 2773static void iwl4965_add_radiotap(struct iwl_priv *priv,
12342c47
ZY		 2774 struct sk_buff *skb,
2775 struct iwl4965_rx_phy_res *rx_start,
2776 struct ieee80211_rx_status *stats,
2777 u32 ampdu_status)
2778{
2779 s8 signal = stats->ssi;
2780 s8 noise = 0;
8318d78a 2781 int rate = stats->rate_idx;
12342c47 2782 u64 tsf = stats->mactime;
a0b484fe 2783 __le16 antenna;
12342c47
ZY		 2784 __le16 phy_flags_hw = rx_start->phy_flags;
2785 struct iwl4965_rt_rx_hdr {
2786 struct ieee80211_radiotap_header rt_hdr;
2787 __le64 rt_tsf; /* TSF */
2788 u8 rt_flags; /* radiotap packet flags */
2789 u8 rt_rate; /* rate in 500kb/s */
2790 __le16 rt_channelMHz; /* channel in MHz */
2791 __le16 rt_chbitmask; /* channel bitfield */
2792 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
2793 s8 rt_dbmnoise;
2794 u8 rt_antenna; /* antenna number */
2795 } __attribute__ ((packed)) *iwl4965_rt;
2796
2797 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
2798 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
2799 if (net_ratelimit())
2800 printk(KERN_ERR "not enough headroom [%d] for "
01c20986 2801 "radiotap head [%zd]\n",
12342c47
ZY		 2802 skb_headroom(skb), sizeof(*iwl4965_rt));
2803 return;
2804 }
2805
2806 /* put radiotap header in front of 802.11 header and data */
2807 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
2808
2809 /* initialise radiotap header */
2810 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
2811 iwl4965_rt->rt_hdr.it_pad = 0;
2812
2813 /* total header + data */
2814 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
2815 &iwl4965_rt->rt_hdr.it_len);
2816
2817 /* Indicate all the fields we add to the radiotap header */
2818 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
2819 (1 << IEEE80211_RADIOTAP_FLAGS) |
2820 (1 << IEEE80211_RADIOTAP_RATE) |
2821 (1 << IEEE80211_RADIOTAP_CHANNEL) |
2822 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
2823 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
2824 (1 << IEEE80211_RADIOTAP_ANTENNA)),
2825 &iwl4965_rt->rt_hdr.it_present);
2826
2827 /* Zero the flags, we'll add to them as we go */
2828 iwl4965_rt->rt_flags = 0;
2829
2830 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
2831
2832 iwl4965_rt->rt_dbmsignal = signal;
2833 iwl4965_rt->rt_dbmnoise = noise;
2834
2835 /* Convert the channel frequency and set the flags */
2836 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
2837 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
2838 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2839 IEEE80211_CHAN_5GHZ),
2840 &iwl4965_rt->rt_chbitmask);
2841 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
2842 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
2843 IEEE80211_CHAN_2GHZ),
2844 &iwl4965_rt->rt_chbitmask);
2845 else /* 802.11g */
2846 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2847 IEEE80211_CHAN_2GHZ),
2848 &iwl4965_rt->rt_chbitmask);
2849
12342c47
ZY		 2850 if (rate == -1)
2851 iwl4965_rt->rt_rate = 0;
2852 else
2853 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
2854
2855 /*
2856 * "antenna number"
2857 *
2858 * It seems that the antenna field in the phy flags value
2859 * is actually a bitfield. This is undefined by radiotap,
2860 * it wants an actual antenna number but I always get "7"
2861 * for most legacy frames I receive indicating that the
2862 * same frame was received on all three RX chains.
2863 *
2864 * I think this field should be removed in favour of a
2865 * new 802.11n radiotap field "RX chains" that is defined
2866 * as a bitmask.
2867 */
a0b484fe
JB		 2868 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
2869 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
12342c47
ZY		 2870
2871 /* set the preamble flag if appropriate */
2872 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
2873 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2874
2875 stats->flag |= RX_FLAG_RADIOTAP;
2876}
2877
19758bef
TW		 2878static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2879{
2880 /* 0 - mgmt, 1 - cnt, 2 - data */
2881 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2882 priv->rx_stats[idx].cnt++;
2883 priv->rx_stats[idx].bytes += len;
2884}
2885
3ec47732
EG		 2886/*
2887 * returns non-zero if packet should be dropped
2888 */
2889static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
2890 struct ieee80211_hdr *hdr,
2891 u32 decrypt_res,
2892 struct ieee80211_rx_status *stats)
2893{
2894 u16 fc = le16_to_cpu(hdr->frame_control);
2895
2896 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2897 return 0;
2898
2899 if (!(fc & IEEE80211_FCTL_PROTECTED))
2900 return 0;
2901
2902 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2903 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2904 case RX_RES_STATUS_SEC_TYPE_TKIP:
2905 /* The uCode has got a bad phase 1 Key, pushes the packet.
2906 * Decryption will be done in SW. */
2907 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2908 RX_RES_STATUS_BAD_KEY_TTAK)
2909 break;
2910
2911 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2912 RX_RES_STATUS_BAD_ICV_MIC) {
2913 /* bad ICV, the packet is destroyed since the
2914 * decryption is inplace, drop it */
2915 IWL_DEBUG_RX("Packet destroyed\n");
2916 return -1;
2917 }
2918 case RX_RES_STATUS_SEC_TYPE_WEP:
2919 case RX_RES_STATUS_SEC_TYPE_CCMP:
2920 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2921 RX_RES_STATUS_DECRYPT_OK) {
2922 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2923 stats->flag |= RX_FLAG_DECRYPTED;
2924 }
2925 break;
2926
2927 default:
2928 break;
2929 }
2930 return 0;
2931}
2932
17e476b8
EG		 2933static u32 iwl4965_translate_rx_status(u32 decrypt_in)
2934{
2935 u32 decrypt_out = 0;
2936
2937 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
2938 RX_RES_STATUS_STATION_FOUND)
2939 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
2940 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
2941
2942 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
2943
2944 /* packet was not encrypted */
2945 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2946 RX_RES_STATUS_SEC_TYPE_NONE)
2947 return decrypt_out;
2948
2949 /* packet was encrypted with unknown alg */
2950 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2951 RX_RES_STATUS_SEC_TYPE_ERR)
2952 return decrypt_out;
2953
2954 /* decryption was not done in HW */
2955 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
2956 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
2957 return decrypt_out;
2958
2959 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
2960
2961 case RX_RES_STATUS_SEC_TYPE_CCMP:
2962 /* alg is CCM: check MIC only */
2963 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
2964 /* Bad MIC */
2965 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2966 else
2967 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2968
2969 break;
2970
2971 case RX_RES_STATUS_SEC_TYPE_TKIP:
2972 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
2973 /* Bad TTAK */
2974 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
2975 break;
2976 }
2977 /* fall through if TTAK OK */
2978 default:
2979 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
2980 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2981 else
2982 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2983 break;
2984 };
2985
2986 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
2987 decrypt_in, decrypt_out);
2988
2989 return decrypt_out;
2990}
2991
c79dd5b5 2992static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
b481de9c 2993 int include_phy,
bb8c093b 2994 struct iwl4965_rx_mem_buffer *rxb,
b481de9c
ZY		 2995 struct ieee80211_rx_status *stats)
2996{
bb8c093b 2997 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY		 2998 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
2999 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
3000 struct ieee80211_hdr *hdr;
3001 u16 len;
3002 __le32 *rx_end;
3003 unsigned int skblen;
3004 u32 ampdu_status;
17e476b8 3005 u32 ampdu_status_legacy;
b481de9c
ZY		 3006
3007 if (!include_phy && priv->last_phy_res[0])
3008 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3009
3010 if (!rx_start) {
3011 IWL_ERROR("MPDU frame without a PHY data\n");
3012 return;
3013 }
3014 if (include_phy) {
3015 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
3016 rx_start->cfg_phy_cnt);
3017
3018 len = le16_to_cpu(rx_start->byte_count);
3019
3020 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
3021 sizeof(struct iwl4965_rx_phy_res) +
3022 rx_start->cfg_phy_cnt + len);
3023
3024 } else {
3025 struct iwl4965_rx_mpdu_res_start *amsdu =
3026 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3027
3028 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
3029 sizeof(struct iwl4965_rx_mpdu_res_start));
3030 len = le16_to_cpu(amsdu->byte_count);
3031 rx_start->byte_count = amsdu->byte_count;
3032 rx_end = (__le32 *) (((u8 *) hdr) + len);
3033 }
5425e490 3034 if (len > priv->hw_params.max_pkt_size || len < 16) {
12342c47 3035 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
b481de9c
ZY		 3036 return;
3037 }
3038
3039 ampdu_status = le32_to_cpu(*rx_end);
3040 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
3041
17e476b8
EG		 3042 if (!include_phy) {
3043 /* New status scheme, need to translate */
3044 ampdu_status_legacy = ampdu_status;
3045 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
3046 }
3047
b481de9c
ZY		 3048 /* start from MAC */
3049 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
3050 skb_put(rxb->skb, len); /* end where data ends */
3051
3052 /* We only process data packets if the interface is open */
3053 if (unlikely(!priv->is_open)) {
3054 IWL_DEBUG_DROP_LIMIT
3055 ("Dropping packet while interface is not open.\n");
3056 return;
3057 }
3058
b481de9c
ZY		 3059 stats->flag = 0;
3060 hdr = (struct ieee80211_hdr *)rxb->skb->data;
3061
3ec47732 3062 /* in case of HW accelerated crypto and bad decryption, drop */
099b40b7 3063 if (!priv->hw_params.sw_crypto &&
3ec47732
EG		 3064 iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
3065 return;
b481de9c 3066
12342c47
ZY		 3067 if (priv->add_radiotap)
3068 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3069
19758bef 3070 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
b481de9c
ZY		 3071 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3072 priv->alloc_rxb_skb--;
3073 rxb->skb = NULL;
b481de9c
ZY		 3074}
3075
3076/* Calc max signal level (dBm) among 3 possible receivers */
3077static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3078{
3079 /* data from PHY/DSP regarding signal strength, etc.,
3080 * contents are always there, not configurable by host. */
3081 struct iwl4965_rx_non_cfg_phy *ncphy =
3082 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3083 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3084 >> IWL_AGC_DB_POS;
3085
3086 u32 valid_antennae =
3087 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3088 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3089 u8 max_rssi = 0;
3090 u32 i;
3091
3092 /* Find max rssi among 3 possible receivers.
3093 * These values are measured by the digital signal processor (DSP).
3094 * They should stay fairly constant even as the signal strength varies,
3095 * if the radio's automatic gain control (AGC) is working right.
3096 * AGC value (see below) will provide the "interesting" info. */
3097 for (i = 0; i < 3; i++)
3098 if (valid_antennae & (1 << i))
3099 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3100
3101 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3102 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3103 max_rssi, agc);
3104
3105 /* dBm = max_rssi dB - agc dB - constant.
3106 * Higher AGC (higher radio gain) means lower signal. */
3107 return (max_rssi - agc - IWL_RSSI_OFFSET);
3108}
3109
c8b0e6e1 3110#ifdef CONFIG_IWL4965_HT
b481de9c 3111
fde0db31 3112void iwl4965_init_ht_hw_capab(const struct iwl_priv *priv,
1ea87396 3113 struct ieee80211_ht_info *ht_info,
78330fdd 3114 enum ieee80211_band band)
326eeee8
RR		 3115{
3116 ht_info->cap = 0;
3117 memset(ht_info->supp_mcs_set, 0, 16);
3118
3119 ht_info->ht_supported = 1;
3120
099b40b7 3121 if (priv->hw_params.fat_channel & BIT(band)) {
326eeee8
RR		 3122 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3123 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3124 ht_info->supp_mcs_set[4] = 0x01;
3125 }
3126 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3127 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3128 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3129 (IWL_MIMO_PS_NONE << 2));
1ea87396
AK		 3130
3131 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47 3132 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
326eeee8
RR		 3133
3134 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3135 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3136
3137 ht_info->supp_mcs_set[0] = 0xFF;
fde0db31
GC		 3138 if (priv->hw_params.tx_chains_num >= 2)
3139 ht_info->supp_mcs_set[1] = 0xFF;
3140 if (priv->hw_params.tx_chains_num >= 3)
3141 ht_info->supp_mcs_set[2] = 0xFF;
326eeee8 3142}
c8b0e6e1 3143#endif /* CONFIG_IWL4965_HT */
b481de9c 3144
c79dd5b5 3145static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
b481de9c
ZY		 3146{
3147 unsigned long flags;
3148
3149 spin_lock_irqsave(&priv->sta_lock, flags);
3150 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3151 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3152 priv->stations[sta_id].sta.sta.modify_mask = 0;
3153 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3154 spin_unlock_irqrestore(&priv->sta_lock, flags);
3155
bb8c093b 3156 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 3157}
3158
c79dd5b5 3159static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
b481de9c
ZY		 3160{
3161 /* FIXME: need locking over ps_status ??? */
947b13a7 3162 u8 sta_id = iwl_find_station(priv, addr);
b481de9c
ZY		 3163
3164 if (sta_id != IWL_INVALID_STATION) {
3165 u8 sta_awake = priv->stations[sta_id].
3166 ps_status == STA_PS_STATUS_WAKE;
3167
3168 if (sta_awake && ps_bit)
3169 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3170 else if (!sta_awake && !ps_bit) {
3171 iwl4965_sta_modify_ps_wake(priv, sta_id);
3172 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3173 }
3174 }
3175}
0a6857e7 3176#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 3177
3178/**
3179 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
3180 *
3181 * You may hack this function to show different aspects of received frames,
3182 * including selective frame dumps.
3183 * group100 parameter selects whether to show 1 out of 100 good frames.
3184 *
3185 * TODO: This was originally written for 3945, need to audit for
3186 * proper operation with 4965.
3187 */
c79dd5b5 3188static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3189 struct iwl4965_rx_packet *pkt,
3190 struct ieee80211_hdr *header, int group100)
3191{
3192 u32 to_us;
3193 u32 print_summary = 0;
3194 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
3195 u32 hundred = 0;
3196 u32 dataframe = 0;
3197 u16 fc;
3198 u16 seq_ctl;
3199 u16 channel;
3200 u16 phy_flags;
3201 int rate_sym;
3202 u16 length;
3203 u16 status;
3204 u16 bcn_tmr;
3205 u32 tsf_low;
3206 u64 tsf;
3207 u8 rssi;
3208 u8 agc;
3209 u16 sig_avg;
3210 u16 noise_diff;
3211 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
3212 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
3213 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
3214 u8 *data = IWL_RX_DATA(pkt);
3215
0a6857e7 3216 if (likely(!(iwl_debug_level & IWL_DL_RX)))
17744ff6
TW		 3217 return;
3218
3219 /* MAC header */
3220 fc = le16_to_cpu(header->frame_control);
3221 seq_ctl = le16_to_cpu(header->seq_ctrl);
3222
3223 /* metadata */
3224 channel = le16_to_cpu(rx_hdr->channel);
3225 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3226 rate_sym = rx_hdr->rate;
3227 length = le16_to_cpu(rx_hdr->len);
3228
3229 /* end-of-frame status and timestamp */
3230 status = le32_to_cpu(rx_end->status);
3231 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3232 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3233 tsf = le64_to_cpu(rx_end->timestamp);
3234
3235 /* signal statistics */
3236 rssi = rx_stats->rssi;
3237 agc = rx_stats->agc;
3238 sig_avg = le16_to_cpu(rx_stats->sig_avg);
3239 noise_diff = le16_to_cpu(rx_stats->noise_diff);
3240
3241 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3242
3243 /* if data frame is to us and all is good,
3244 * (optionally) print summary for only 1 out of every 100 */
3245 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3246 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3247 dataframe = 1;
3248 if (!group100)
3249 print_summary = 1; /* print each frame */
3250 else if (priv->framecnt_to_us < 100) {
3251 priv->framecnt_to_us++;
3252 print_summary = 0;
3253 } else {
3254 priv->framecnt_to_us = 0;
3255 print_summary = 1;
3256 hundred = 1;
3257 }
3258 } else {
3259 /* print summary for all other frames */
3260 print_summary = 1;
3261 }
3262
3263 if (print_summary) {
3264 char *title;
3265 int rate_idx;
3266 u32 bitrate;
3267
3268 if (hundred)
3269 title = "100Frames";
3270 else if (fc & IEEE80211_FCTL_RETRY)
3271 title = "Retry";
3272 else if (ieee80211_is_assoc_response(fc))
3273 title = "AscRsp";
3274 else if (ieee80211_is_reassoc_response(fc))
3275 title = "RasRsp";
3276 else if (ieee80211_is_probe_response(fc)) {
3277 title = "PrbRsp";
3278 print_dump = 1; /* dump frame contents */
3279 } else if (ieee80211_is_beacon(fc)) {
3280 title = "Beacon";
3281 print_dump = 1; /* dump frame contents */
3282 } else if (ieee80211_is_atim(fc))
3283 title = "ATIM";
3284 else if (ieee80211_is_auth(fc))
3285 title = "Auth";
3286 else if (ieee80211_is_deauth(fc))
3287 title = "DeAuth";
3288 else if (ieee80211_is_disassoc(fc))
3289 title = "DisAssoc";
3290 else
3291 title = "Frame";
3292
3293 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3294 if (unlikely(rate_idx == -1))
3295 bitrate = 0;
3296 else
3297 bitrate = iwl4965_rates[rate_idx].ieee / 2;
3298
3299 /* print frame summary.
3300 * MAC addresses show just the last byte (for brevity),
3301 * but you can hack it to show more, if you'd like to. */
3302 if (dataframe)
3303 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3304 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3305 title, fc, header->addr1[5],
3306 length, rssi, channel, bitrate);
3307 else {
3308 /* src/dst addresses assume managed mode */
3309 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3310 "src=0x%02x, rssi=%u, tim=%lu usec, "
3311 "phy=0x%02x, chnl=%d\n",
3312 title, fc, header->addr1[5],
3313 header->addr3[5], rssi,
3314 tsf_low - priv->scan_start_tsf,
3315 phy_flags, channel);
3316 }
3317 }
3318 if (print_dump)
0a6857e7 3319 iwl_print_hex_dump(IWL_DL_RX, data, length);
17744ff6
TW		 3320}
3321#else
c79dd5b5 3322static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3323 struct iwl4965_rx_packet *pkt,
3324 struct ieee80211_hdr *header,
3325 int group100)
3326{
3327}
3328#endif
3329
b481de9c 3330
7878a5a4 3331
857485c0 3332/* Called for REPLY_RX (legacy ABG frames), or
b481de9c 3333 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
c79dd5b5 3334static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
bb8c093b 3335 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3336{
17744ff6
TW		 3337 struct ieee80211_hdr *header;
3338 struct ieee80211_rx_status rx_status;
bb8c093b 3339 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3340 /* Use phy data (Rx signal strength, etc.) contained within
3341 * this rx packet for legacy frames,
3342 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
857485c0 3343 int include_phy = (pkt->hdr.cmd == REPLY_RX);
b481de9c
ZY		 3344 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3345 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3346 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3347 __le32 *rx_end;
3348 unsigned int len = 0;
b481de9c 3349 u16 fc;
b481de9c
ZY		 3350 u8 network_packet;
3351
17744ff6 3352 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
dc92e497
TW		 3353 rx_status.freq =
3354 ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
17744ff6
TW		 3355 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3356 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
dc92e497
TW		 3357 rx_status.rate_idx =
3358 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
17744ff6
TW		 3359 if (rx_status.band == IEEE80211_BAND_5GHZ)
3360 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3361
3362 rx_status.antenna = 0;
3363 rx_status.flag = 0;
3364
b481de9c 3365 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
dc92e497
TW		 3366 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
3367 rx_start->cfg_phy_cnt);
b481de9c
ZY		 3368 return;
3369 }
17744ff6 3370
b481de9c
ZY		 3371 if (!include_phy) {
3372 if (priv->last_phy_res[0])
3373 rx_start = (struct iwl4965_rx_phy_res *)
3374 &priv->last_phy_res[1];
3375 else
3376 rx_start = NULL;
3377 }
3378
3379 if (!rx_start) {
3380 IWL_ERROR("MPDU frame without a PHY data\n");
3381 return;
3382 }
3383
3384 if (include_phy) {
3385 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3386 + rx_start->cfg_phy_cnt);
3387
3388 len = le16_to_cpu(rx_start->byte_count);
17744ff6 3389 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
b481de9c
ZY		 3390 sizeof(struct iwl4965_rx_phy_res) + len);
3391 } else {
3392 struct iwl4965_rx_mpdu_res_start *amsdu =
3393 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3394
3395 header = (void *)(pkt->u.raw +
3396 sizeof(struct iwl4965_rx_mpdu_res_start));
3397 len = le16_to_cpu(amsdu->byte_count);
3398 rx_end = (__le32 *) (pkt->u.raw +
3399 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3400 }
3401
3402 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3403 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3404 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3405 le32_to_cpu(*rx_end));
3406 return;
3407 }
3408
3409 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3410
b481de9c 3411 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
17744ff6 3412 rx_status.ssi = iwl4965_calc_rssi(rx_start);
b481de9c
ZY		 3413
3414 /* Meaningful noise values are available only from beacon statistics,
3415 * which are gathered only when associated, and indicate noise
3416 * only for the associated network channel ...
3417 * Ignore these noise values while scanning (other channels) */
3109ece1 3418 if (iwl_is_associated(priv) &&
b481de9c 3419 !test_bit(STATUS_SCANNING, &priv->status)) {
17744ff6
TW		 3420 rx_status.noise = priv->last_rx_noise;
3421 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
3422 rx_status.noise);
b481de9c 3423 } else {
17744ff6
TW		 3424 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3425 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
b481de9c
ZY		 3426 }
3427
3428 /* Reset beacon noise level if not associated. */
3109ece1 3429 if (!iwl_is_associated(priv))
b481de9c
ZY		 3430 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3431
17744ff6
TW		 3432 /* Set "1" to report good data frames in groups of 100 */
3433 /* FIXME: need to optimze the call: */
3434 iwl4965_dbg_report_frame(priv, pkt, header, 1);
3435
3436 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
3437 rx_status.ssi, rx_status.noise, rx_status.signal,
06501d29 3438 (unsigned long long)rx_status.mactime);
b481de9c 3439
bb8c093b 3440 network_packet = iwl4965_is_network_packet(priv, header);
b481de9c 3441 if (network_packet) {
17744ff6 3442 priv->last_rx_rssi = rx_status.ssi;
b481de9c
ZY		 3443 priv->last_beacon_time = priv->ucode_beacon_time;
3444 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
3445 }
3446
3447 fc = le16_to_cpu(header->frame_control);
3448 switch (fc & IEEE80211_FCTL_FTYPE) {
3449 case IEEE80211_FTYPE_MGMT:
b481de9c
ZY		 3450 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3451 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3452 header->addr2);
17744ff6 3453 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
b481de9c
ZY		 3454 break;
3455
3456 case IEEE80211_FTYPE_CTL:
9ab46173 3457#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 3458 switch (fc & IEEE80211_FCTL_STYPE) {
3459 case IEEE80211_STYPE_BACK_REQ:
3460 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
3461 iwl4965_handle_data_packet(priv, 0, include_phy,
17744ff6 3462 rxb, &rx_status);
b481de9c
ZY		 3463 break;
3464 default:
3465 break;
3466 }
3467#endif
b481de9c
ZY		 3468 break;
3469
0795af57
JP		 3470 case IEEE80211_FTYPE_DATA: {
3471 DECLARE_MAC_BUF(mac1);
3472 DECLARE_MAC_BUF(mac2);
3473 DECLARE_MAC_BUF(mac3);
3474
b481de9c
ZY		 3475 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3476 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3477 header->addr2);
3478
3479 if (unlikely(!network_packet))
3480 IWL_DEBUG_DROP("Dropping (non network): "
0795af57
JP		 3481 "%s, %s, %s\n",
3482 print_mac(mac1, header->addr1),
3483 print_mac(mac2, header->addr2),
3484 print_mac(mac3, header->addr3));
bb8c093b 3485 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
0795af57
JP		 3486 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
3487 print_mac(mac1, header->addr1),
3488 print_mac(mac2, header->addr2),
3489 print_mac(mac3, header->addr3));
b481de9c
ZY		 3490 else
3491 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
17744ff6 3492 &rx_status);
b481de9c 3493 break;
0795af57 3494 }
b481de9c
ZY		 3495 default:
3496 break;
3497
3498 }
3499}
3500
3501/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
3502 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
c79dd5b5 3503static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
bb8c093b 3504 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3505{
bb8c093b 3506 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3507 priv->last_phy_res[0] = 1;
3508 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
3509 sizeof(struct iwl4965_rx_phy_res));
3510}
c79dd5b5 3511static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
bb8c093b 3512 struct iwl4965_rx_mem_buffer *rxb)
b481de9c
ZY		 3513
3514{
f0832f13 3515#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
bb8c093b
CH		 3516 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3517 struct iwl4965_missed_beacon_notif *missed_beacon;
b481de9c
ZY		 3518
3519 missed_beacon = &pkt->u.missed_beacon;
3520 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
3521 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
3522 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
3523 le32_to_cpu(missed_beacon->total_missed_becons),
3524 le32_to_cpu(missed_beacon->num_recvd_beacons),
3525 le32_to_cpu(missed_beacon->num_expected_beacons));
f0832f13
EG		 3526 if (!test_bit(STATUS_SCANNING, &priv->status))
3527 iwl_init_sensitivity(priv);
b481de9c 3528 }
f0832f13 3529#endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
b481de9c 3530}
c8b0e6e1 3531#ifdef CONFIG_IWL4965_HT
b481de9c 3532
8b6eaea8
BC		 3533/**
3534 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
3535 */
c79dd5b5 3536static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
b481de9c
ZY		 3537 int sta_id, int tid)
3538{
3539 unsigned long flags;
3540
8b6eaea8 3541 /* Remove "disable" flag, to enable Tx for this TID */
b481de9c
ZY		 3542 spin_lock_irqsave(&priv->sta_lock, flags);
3543 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3544 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3545 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3546 spin_unlock_irqrestore(&priv->sta_lock, flags);
3547
bb8c093b 3548 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 3549}
3550
8b6eaea8
BC		 3551/**
3552 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
3553 *
3554 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
3555 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
3556 */
c79dd5b5 3557static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b
CH		 3558 struct iwl4965_ht_agg *agg,
3559 struct iwl4965_compressed_ba_resp*
b481de9c
ZY		 3560 ba_resp)
3561
3562{
3563 int i, sh, ack;
fe01b477
RR		 3564 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
3565 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3566 u64 bitmap;
3567 int successes = 0;
3568 struct ieee80211_tx_status *tx_status;
b481de9c
ZY		 3569
3570 if (unlikely(!agg->wait_for_ba)) {
3571 IWL_ERROR("Received BA when not expected\n");
3572 return -EINVAL;
3573 }
8b6eaea8
BC		 3574
3575 /* Mark that the expected block-ack response arrived */
b481de9c 3576 agg->wait_for_ba = 0;
fe01b477 3577 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
8b6eaea8
BC		 3578
3579 /* Calculate shift to align block-ack bits with our Tx window bits */
fe01b477 3580 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
01ebd063 3581 if (sh < 0) /* tbw something is wrong with indices */
b481de9c
ZY		 3582 sh += 0x100;
3583
8b6eaea8 3584 /* don't use 64-bit values for now */
fe01b477 3585 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
b481de9c
ZY		 3586
3587 if (agg->frame_count > (64 - sh)) {
3588 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
3589 return -1;
3590 }
3591
3592 /* check for success or failure according to the
8b6eaea8 3593 * transmitted bitmap and block-ack bitmap */
fe01b477 3594 bitmap &= agg->bitmap;
b481de9c 3595
8b6eaea8
BC		 3596 /* For each frame attempted in aggregation,
3597 * update driver's record of tx frame's status. */
b481de9c 3598 for (i = 0; i < agg->frame_count ; i++) {
fe01b477
RR		 3599 ack = bitmap & (1 << i);
3600 successes += !!ack;
b481de9c 3601 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
fe01b477
RR		 3602 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
3603 agg->start_idx + i);
3604 }
3605
3606 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
3607 tx_status->flags = IEEE80211_TX_STATUS_ACK;
99556438
RR		 3608 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
3609 tx_status->ampdu_ack_map = successes;
3610 tx_status->ampdu_ack_len = agg->frame_count;
4c424e4c
RR		 3611 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
3612 &tx_status->control);
fe01b477 3613
f868f4e1 3614 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
fe01b477
RR		 3615
3616 return 0;
3617}
3618
3619/**
3620 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
3621 */
c79dd5b5 3622static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 3623 u16 txq_id)
3624{
3625 /* Simply stop the queue, but don't change any configuration;
3626 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3395f6e9 3627 iwl_write_prph(priv,
12a81f60 3628 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
fe01b477
RR		 3629 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
3630 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
3631}
b481de9c 3632
fe01b477
RR		 3633/**
3634 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
b095d03a 3635 * priv->lock must be held by the caller
fe01b477 3636 */
c79dd5b5 3637static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
fe01b477
RR		 3638 u16 ssn_idx, u8 tx_fifo)
3639{
b095d03a
RR		 3640 int ret = 0;
3641
fe01b477
RR		 3642 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
3643 IWL_WARNING("queue number too small: %d, must be > %d\n",
3644 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3645 return -EINVAL;
b481de9c
ZY		 3646 }
3647
3395f6e9 3648 ret = iwl_grab_nic_access(priv);
b095d03a
RR		 3649 if (ret)
3650 return ret;
3651
fe01b477
RR		 3652 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3653
12a81f60 3654 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
fe01b477
RR		 3655
3656 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3657 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3658 /* supposes that ssn_idx is valid (!= 0xFFF) */
3659 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3660
12a81f60 3661 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
fe01b477
RR		 3662 iwl4965_txq_ctx_deactivate(priv, txq_id);
3663 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
3664
3395f6e9 3665 iwl_release_nic_access(priv);
b095d03a 3666
fe01b477
RR		 3667 return 0;
3668}
b481de9c 3669
c79dd5b5 3670int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
fe01b477
RR		 3671 u8 tid, int txq_id)
3672{
3673 struct iwl4965_queue *q = &priv->txq[txq_id].q;
3674 u8 *addr = priv->stations[sta_id].sta.sta.addr;
3675 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
3676
3677 switch (priv->stations[sta_id].tid[tid].agg.state) {
3678 case IWL_EMPTYING_HW_QUEUE_DELBA:
3679 /* We are reclaiming the last packet of the */
3680 /* aggregated HW queue */
3681 if (txq_id == tid_data->agg.txq_id &&
3682 q->read_ptr == q->write_ptr) {
3683 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
3684 int tx_fifo = default_tid_to_tx_fifo[tid];
3685 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
3686 iwl4965_tx_queue_agg_disable(priv, txq_id,
3687 ssn, tx_fifo);
3688 tid_data->agg.state = IWL_AGG_OFF;
3689 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3690 }
3691 break;
3692 case IWL_EMPTYING_HW_QUEUE_ADDBA:
3693 /* We are reclaiming the last packet of the queue */
3694 if (tid_data->tfds_in_queue == 0) {
3695 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
3696 tid_data->agg.state = IWL_AGG_ON;
3697 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3698 }
3699 break;
3700 }
b481de9c
ZY		 3701 return 0;
3702}
3703
8b6eaea8
BC		 3704/**
3705 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
3706 * @index -- current index
3707 * @n_bd -- total number of entries in queue (s/b power of 2)
3708 */
bb8c093b 3709static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
b481de9c
ZY		 3710{
3711 return (index == 0) ? n_bd - 1 : index - 1;
3712}
3713
8b6eaea8
BC		 3714/**
3715 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
3716 *
3717 * Handles block-acknowledge notification from device, which reports success
3718 * of frames sent via aggregation.
3719 */
c79dd5b5 3720static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b 3721 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3722{
bb8c093b
CH		 3723 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3724 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
b481de9c 3725 int index;
bb8c093b
CH		 3726 struct iwl4965_tx_queue *txq = NULL;
3727 struct iwl4965_ht_agg *agg;
fe01b477 3728 DECLARE_MAC_BUF(mac);
8b6eaea8
BC		 3729
3730 /* "flow" corresponds to Tx queue */
fe01b477 3731 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
8b6eaea8
BC		 3732
3733 /* "ssn" is start of block-ack Tx window, corresponds to index
3734 * (in Tx queue's circular buffer) of first TFD/frame in window */
b481de9c
ZY		 3735 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
3736
dfe7d458 3737 if (scd_flow >= priv->hw_params.max_txq_num) {
b481de9c
ZY		 3738 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
3739 return;
3740 }
3741
fe01b477 3742 txq = &priv->txq[scd_flow];
b481de9c 3743 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
8b6eaea8
BC		 3744
3745 /* Find index just before block-ack window */
bb8c093b 3746 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
b481de9c 3747
01ebd063 3748 /* TODO: Need to get this copy more safely - now good for debug */
fe01b477 3749
0795af57
JP		 3750 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
3751 "sta_id = %d\n",
b481de9c 3752 agg->wait_for_ba,
0795af57 3753 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
b481de9c 3754 ba_resp->sta_id);
fe01b477 3755 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
b481de9c
ZY		 3756 "%d, scd_ssn = %d\n",
3757 ba_resp->tid,
fe01b477 3758 ba_resp->seq_ctl,
0310ae72 3759 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
b481de9c
ZY		 3760 ba_resp->scd_flow,
3761 ba_resp->scd_ssn);
fe01b477 3762 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
b481de9c 3763 agg->start_idx,
f868f4e1 3764 (unsigned long long)agg->bitmap);
8b6eaea8
BC		 3765
3766 /* Update driver's record of ACK vs. not for each frame in window */
b481de9c 3767 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
8b6eaea8
BC		 3768
3769 /* Release all TFDs before the SSN, i.e. all TFDs in front of
3770 * block-ack window (we assume that they've been successfully
3771 * transmitted ... if not, it's too late anyway). */
fe01b477
RR		 3772 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
3773 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
3774 priv->stations[ba_resp->sta_id].
3775 tid[ba_resp->tid].tfds_in_queue -= freed;
3776 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3777 priv->mac80211_registered &&
3778 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3779 ieee80211_wake_queue(priv->hw, scd_flow);
3780 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
3781 ba_resp->tid, scd_flow);
3782 }
b481de9c
ZY		 3783}
3784
8b6eaea8
BC		 3785/**
3786 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
3787 */
c79dd5b5 3788static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 3789 u16 txq_id)
3790{
3791 u32 tbl_dw_addr;
3792 u32 tbl_dw;
3793 u16 scd_q2ratid;
3794
3795 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
3796
3797 tbl_dw_addr = priv->scd_base_addr +
3798 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
3799
3395f6e9 3800 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 3801
3802 if (txq_id & 0x1)
3803 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
3804 else
3805 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
3806
3395f6e9 3807 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 3808
3809 return 0;
3810}
3811
fe01b477 3812
b481de9c 3813/**
8b6eaea8
BC		 3814 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
3815 *
3816 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
3817 * i.e. it must be one of the higher queues used for aggregation
b481de9c 3818 */
c79dd5b5 3819static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
b481de9c
ZY		 3820 int tx_fifo, int sta_id, int tid,
3821 u16 ssn_idx)
3822{
3823 unsigned long flags;
3824 int rc;
3825 u16 ra_tid;
3826
3827 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
3828 IWL_WARNING("queue number too small: %d, must be > %d\n",
3829 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3830
3831 ra_tid = BUILD_RAxTID(sta_id, tid);
3832
8b6eaea8 3833 /* Modify device's station table to Tx this TID */
bb8c093b 3834 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
b481de9c
ZY		 3835
3836 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 3837 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 3838 if (rc) {
3839 spin_unlock_irqrestore(&priv->lock, flags);
3840 return rc;
3841 }
3842
8b6eaea8 3843 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 3844 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3845
8b6eaea8 3846 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 3847 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
3848
8b6eaea8 3849 /* Set this queue as a chain-building queue */
12a81f60 3850 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 3851
8b6eaea8
BC		 3852 /* Place first TFD at index corresponding to start sequence number.
3853 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 3854 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3855 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 3856 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3857
8b6eaea8 3858 /* Set up Tx window size and frame limit for this queue */
3395f6e9 3859 iwl_write_targ_mem(priv,
b481de9c
ZY		 3860 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
3861 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
3862 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
3863
3395f6e9 3864 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 3865 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
3866 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
3867 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
3868
12a81f60 3869 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 3870
8b6eaea8 3871 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 3872 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
3873
3395f6e9 3874 iwl_release_nic_access(priv);
b481de9c
ZY		 3875 spin_unlock_irqrestore(&priv->lock, flags);
3876
3877 return 0;
3878}
3879
c8b0e6e1 3880#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 3881
3882/**
3883 * iwl4965_add_station - Initialize a station's hardware rate table
3884 *
8b6eaea8 3885 * The uCode's station table contains a table of fallback rates
b481de9c
ZY		 3886 * for automatic fallback during transmission.
3887 *
8b6eaea8
BC		 3888 * NOTE: This sets up a default set of values. These will be replaced later
3889 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
3890 * rc80211_simple.
b481de9c 3891 *
8b6eaea8
BC		 3892 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
3893 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
3894 * which requires station table entry to exist).
b481de9c 3895 */
c79dd5b5 3896void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 3897{
3898 int i, r;
66c73db7 3899 struct iwl_link_quality_cmd link_cmd = {
b481de9c
ZY		 3900 .reserved1 = 0,
3901 };
3902 u16 rate_flags;
3903
8b6eaea8
BC		 3904 /* Set up the rate scaling to start at selected rate, fall back
3905 * all the way down to 1M in IEEE order, and then spin on 1M */
b481de9c
ZY		 3906 if (is_ap)
3907 r = IWL_RATE_54M_INDEX;
8318d78a 3908 else if (priv->band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 3909 r = IWL_RATE_6M_INDEX;
3910 else
3911 r = IWL_RATE_1M_INDEX;
3912
3913 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
3914 rate_flags = 0;
3915 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
3916 rate_flags |= RATE_MCS_CCK_MSK;
3917
8b6eaea8 3918 /* Use Tx antenna B only */
fde0db31 3919 rate_flags |= RATE_MCS_ANT_B_MSK; /*FIXME:RS*/
8b6eaea8 3920
b481de9c 3921 link_cmd.rs_table[i].rate_n_flags =
bb8c093b
CH		 3922 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
3923 r = iwl4965_get_prev_ieee_rate(r);
b481de9c
ZY		 3924 }
3925
3926 link_cmd.general_params.single_stream_ant_msk = 2;
3927 link_cmd.general_params.dual_stream_ant_msk = 3;
3928 link_cmd.agg_params.agg_dis_start_th = 3;
3929 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
3930
3931 /* Update the rate scaling for control frame Tx to AP */
5425e490 3932 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_params.bcast_sta_id;
b481de9c 3933
e5472978
TW		 3934 iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
3935 sizeof(link_cmd), &link_cmd, NULL);
b481de9c
ZY		 3936}
3937
c8b0e6e1 3938#ifdef CONFIG_IWL4965_HT
b481de9c 3939
c79dd5b5 3940static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
8318d78a 3941 enum ieee80211_band band,
78330fdd 3942 u16 channel, u8 extension_chan_offset)
b481de9c 3943{
bf85ea4f 3944 const struct iwl_channel_info *ch_info;
b481de9c 3945
8622e705 3946 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 3947 if (!is_channel_valid(ch_info))
3948 return 0;
3949
134eb5d3 3950 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
b481de9c
ZY		 3951 return 0;
3952
3953 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
3954 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
3955 return 1;
3956
3957 return 0;
3958}
3959
c79dd5b5 3960static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
fd105e79 3961 struct ieee80211_ht_info *sta_ht_inf)
b481de9c 3962{
fd105e79 3963 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
b481de9c 3964
fd105e79
RR		 3965 if ((!iwl_ht_conf->is_ht) ||
3966 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
134eb5d3 3967 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
b481de9c
ZY		 3968 return 0;
3969
fd105e79
RR		 3970 if (sta_ht_inf) {
3971 if ((!sta_ht_inf->ht_supported) ||
194c7ca6 3972 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
fd105e79
RR		 3973 return 0;
3974 }
b481de9c 3975
78330fdd 3976 return (iwl4965_is_channel_extension(priv, priv->band,
fd105e79
RR		 3977 iwl_ht_conf->control_channel,
3978 iwl_ht_conf->extension_chan_offset));
b481de9c
ZY		 3979}
3980
c79dd5b5 3981void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
b481de9c 3982{
bb8c093b 3983 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 3984 u32 val;
3985
3986 if (!ht_info->is_ht)
3987 return;
3988
8b6eaea8 3989 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
fd105e79 3990 if (iwl4965_is_fat_tx_allowed(priv, NULL))
b481de9c
ZY		 3991 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
3992 else
3993 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
3994 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
3995
3996 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
3997 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
3998 le16_to_cpu(rxon->channel),
3999 ht_info->control_channel);
4000 rxon->channel = cpu_to_le16(ht_info->control_channel);
4001 return;
4002 }
4003
8b6eaea8 4004 /* Note: control channel is opposite of extension channel */
b481de9c
ZY		 4005 switch (ht_info->extension_chan_offset) {
4006 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
4007 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
4008 break;
4009 case IWL_EXT_CHANNEL_OFFSET_BELOW:
4010 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
4011 break;
134eb5d3 4012 case IWL_EXT_CHANNEL_OFFSET_NONE:
b481de9c
ZY		 4013 default:
4014 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4015 break;
4016 }
4017
fd105e79 4018 val = ht_info->ht_protection;
b481de9c
ZY		 4019
4020 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
4021
b481de9c
ZY		 4022 iwl4965_set_rxon_chain(priv);
4023
fde0db31 4024 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
b481de9c
ZY		 4025 "rxon flags 0x%X operation mode :0x%X "
4026 "extension channel offset 0x%x "
4027 "control chan %d\n",
fde0db31
GC		 4028 ht_info->supp_mcs_set[0],
4029 ht_info->supp_mcs_set[1],
4030 ht_info->supp_mcs_set[2],
fd105e79 4031 le32_to_cpu(rxon->flags), ht_info->ht_protection,
b481de9c
ZY		 4032 ht_info->extension_chan_offset,
4033 ht_info->control_channel);
4034 return;
4035}
4036
c79dd5b5 4037void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
67d62035 4038 struct ieee80211_ht_info *sta_ht_inf)
b481de9c
ZY		 4039{
4040 __le32 sta_flags;
e53cfe0e 4041 u8 mimo_ps_mode;
b481de9c 4042
67d62035 4043 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
b481de9c
ZY		 4044 goto done;
4045
e53cfe0e
TW		 4046 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
4047
b481de9c
ZY		 4048 sta_flags = priv->stations[index].sta.station_flags;
4049
e53cfe0e
TW		 4050 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
4051
4052 switch (mimo_ps_mode) {
4053 case WLAN_HT_CAP_MIMO_PS_STATIC:
4054 sta_flags |= STA_FLG_MIMO_DIS_MSK;
4055 break;
4056 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
b481de9c 4057 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
e53cfe0e
TW		 4058 break;
4059 case WLAN_HT_CAP_MIMO_PS_DISABLED:
4060 break;
4061 default:
4062 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
4063 break;
4064 }
b481de9c
ZY		 4065
4066 sta_flags |= cpu_to_le32(
67d62035 4067 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
b481de9c
ZY		 4068
4069 sta_flags |= cpu_to_le32(
67d62035 4070 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
b481de9c 4071
67d62035 4072 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
b481de9c 4073 sta_flags |= STA_FLG_FAT_EN_MSK;
67d62035 4074 else
e53cfe0e 4075 sta_flags &= ~STA_FLG_FAT_EN_MSK;
67d62035 4076
b481de9c
ZY		 4077 priv->stations[index].sta.station_flags = sta_flags;
4078 done:
4079 return;
4080}
4081
fe07aa7a
RR		 4082static int iwl4965_rx_agg_start(struct iwl_priv *priv,
4083 const u8 *addr, int tid, u16 ssn)
b481de9c
ZY		 4084{
4085 unsigned long flags;
fe07aa7a
RR		 4086 int sta_id;
4087
4088 sta_id = iwl_find_station(priv, addr);
4089 if (sta_id == IWL_INVALID_STATION)
4090 return -ENXIO;
b481de9c
ZY		 4091
4092 spin_lock_irqsave(&priv->sta_lock, flags);
4093 priv->stations[sta_id].sta.station_flags_msk = 0;
4094 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
4095 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
4096 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
4097 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4098 spin_unlock_irqrestore(&priv->sta_lock, flags);
4099
fe07aa7a
RR		 4100 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
4101 CMD_ASYNC);
b481de9c
ZY		 4102}
4103
fe07aa7a
RR		 4104static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
4105 const u8 *addr, int tid)
b481de9c
ZY		 4106{
4107 unsigned long flags;
fe07aa7a
RR		 4108 int sta_id;
4109
4110 sta_id = iwl_find_station(priv, addr);
4111 if (sta_id == IWL_INVALID_STATION)
4112 return -ENXIO;
b481de9c
ZY		 4113
4114 spin_lock_irqsave(&priv->sta_lock, flags);
4115 priv->stations[sta_id].sta.station_flags_msk = 0;
4116 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4117 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4118 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4119 spin_unlock_irqrestore(&priv->sta_lock, flags);
4120
fe07aa7a
RR		 4121 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
4122 CMD_ASYNC);
b481de9c
ZY		 4123}
4124
8b6eaea8
BC		 4125/*
4126 * Find first available (lowest unused) Tx Queue, mark it "active".
4127 * Called only when finding queue for aggregation.
4128 * Should never return anything < 7, because they should already
4129 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4130 */
c79dd5b5 4131static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
b481de9c
ZY		 4132{
4133 int txq_id;
4134
5425e490 4135 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
b481de9c
ZY		 4136 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4137 return txq_id;
4138 return -1;
4139}
4140
fe07aa7a
RR		 4141static int iwl4965_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra,
4142 u16 tid, u16 *start_seq_num)
b481de9c 4143{
c79dd5b5 4144 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 4145 int sta_id;
4146 int tx_fifo;
4147 int txq_id;
4148 int ssn = -1;
b095d03a 4149 int ret = 0;
b481de9c 4150 unsigned long flags;
bb8c093b 4151 struct iwl4965_tid_data *tid_data;
0795af57 4152 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 4153
4154 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4155 tx_fifo = default_tid_to_tx_fifo[tid];
4156 else
4157 return -EINVAL;
4158
fe07aa7a
RR		 4159 IWL_WARNING("%s on ra = %s tid = %d\n",
4160 __func__, print_mac(mac, ra), tid);
b481de9c 4161
fe07aa7a 4162 sta_id = iwl_find_station(priv, ra);
b481de9c
ZY		 4163 if (sta_id == IWL_INVALID_STATION)
4164 return -ENXIO;
4165
fe01b477
RR		 4166 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
4167 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
4168 return -ENXIO;
4169 }
4170
bb8c093b 4171 txq_id = iwl4965_txq_ctx_activate_free(priv);
b481de9c
ZY		 4172 if (txq_id == -1)
4173 return -ENXIO;
4174
4175 spin_lock_irqsave(&priv->sta_lock, flags);
4176 tid_data = &priv->stations[sta_id].tid[tid];
4177 ssn = SEQ_TO_SN(tid_data->seq_number);
4178 tid_data->agg.txq_id = txq_id;
4179 spin_unlock_irqrestore(&priv->sta_lock, flags);
4180
4181 *start_seq_num = ssn;
b095d03a
RR		 4182 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
4183 sta_id, tid, ssn);
4184 if (ret)
4185 return ret;
b481de9c 4186
b095d03a 4187 ret = 0;
fe01b477
RR		 4188 if (tid_data->tfds_in_queue == 0) {
4189 printk(KERN_ERR "HW queue is empty\n");
4190 tid_data->agg.state = IWL_AGG_ON;
fe07aa7a 4191 ieee80211_start_tx_ba_cb_irqsafe(hw, ra, tid);
fe01b477
RR		 4192 } else {
4193 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4194 tid_data->tfds_in_queue);
4195 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4196 }
b095d03a 4197 return ret;
fe01b477 4198}
b481de9c 4199
fe07aa7a 4200static int iwl4965_tx_agg_stop(struct ieee80211_hw *hw, const u8 *ra, u16 tid)
b481de9c 4201{
c79dd5b5 4202 struct iwl_priv *priv = hw->priv;
b481de9c 4203 int tx_fifo_id, txq_id, sta_id, ssn = -1;
bb8c093b 4204 struct iwl4965_tid_data *tid_data;
b095d03a 4205 int ret, write_ptr, read_ptr;
fe01b477 4206 unsigned long flags;
0795af57
JP		 4207 DECLARE_MAC_BUF(mac);
4208
fe07aa7a
RR		 4209 if (!ra) {
4210 IWL_ERROR("ra = NULL\n");
b481de9c
ZY		 4211 return -EINVAL;
4212 }
4213
4214 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4215 tx_fifo_id = default_tid_to_tx_fifo[tid];
4216 else
4217 return -EINVAL;
4218
fe07aa7a 4219 sta_id = iwl_find_station(priv, ra);
b481de9c
ZY		 4220
4221 if (sta_id == IWL_INVALID_STATION)
4222 return -ENXIO;
4223
fe01b477
RR		 4224 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4225 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4226
b481de9c
ZY		 4227 tid_data = &priv->stations[sta_id].tid[tid];
4228 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4229 txq_id = tid_data->agg.txq_id;
fe01b477
RR		 4230 write_ptr = priv->txq[txq_id].q.write_ptr;
4231 read_ptr = priv->txq[txq_id].q.read_ptr;
4232
4233 /* The queue is not empty */
4234 if (write_ptr != read_ptr) {
4235 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4236 priv->stations[sta_id].tid[tid].agg.state =
4237 IWL_EMPTYING_HW_QUEUE_DELBA;
4238 return 0;
4239 }
4240
fe07aa7a 4241 IWL_DEBUG_HT("HW queue is empty\n");
fe01b477 4242 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
b481de9c 4243
fe01b477 4244 spin_lock_irqsave(&priv->lock, flags);
b095d03a 4245 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
fe01b477
RR		 4246 spin_unlock_irqrestore(&priv->lock, flags);
4247
b095d03a
RR		 4248 if (ret)
4249 return ret;
b481de9c 4250
fe07aa7a 4251 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
8114fcf1 4252
8114fcf1
RR		 4253 return 0;
4254}
4255
4256int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4257 enum ieee80211_ampdu_mlme_action action,
4258 const u8 *addr, u16 tid, u16 *ssn)
4259{
c79dd5b5 4260 struct iwl_priv *priv = hw->priv;
8114fcf1
RR		 4261 DECLARE_MAC_BUF(mac);
4262
fe07aa7a
RR		 4263 IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
4264 print_mac(mac, addr), tid);
4265
8114fcf1
RR		 4266 switch (action) {
4267 case IEEE80211_AMPDU_RX_START:
4268 IWL_DEBUG_HT("start Rx\n");
fe07aa7a 4269 return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
8114fcf1
RR		 4270 case IEEE80211_AMPDU_RX_STOP:
4271 IWL_DEBUG_HT("stop Rx\n");
fe07aa7a 4272 return iwl4965_rx_agg_stop(priv, addr, tid);
8114fcf1
RR		 4273 case IEEE80211_AMPDU_TX_START:
4274 IWL_DEBUG_HT("start Tx\n");
fe07aa7a 4275 return iwl4965_tx_agg_start(hw, addr, tid, ssn);
8114fcf1
RR		 4276 case IEEE80211_AMPDU_TX_STOP:
4277 IWL_DEBUG_HT("stop Tx\n");
fe07aa7a 4278 return iwl4965_tx_agg_stop(hw, addr, tid);
8114fcf1
RR		 4279 default:
4280 IWL_DEBUG_HT("unknown\n");
4281 return -EINVAL;
4282 break;
4283 }
4284 return 0;
4285}
4286
c8b0e6e1 4287#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4288
4289/* Set up 4965-specific Rx frame reply handlers */
c79dd5b5 4290void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 4291{
4292 /* Legacy Rx frames */
857485c0 4293 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
b481de9c
ZY		 4294
4295 /* High-throughput (HT) Rx frames */
4296 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4297 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4298
4299 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4300 iwl4965_rx_missed_beacon_notif;
4301
c8b0e6e1 4302#ifdef CONFIG_IWL4965_HT
b481de9c 4303 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
c8b0e6e1 4304#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4305}
4306
c79dd5b5 4307void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4308{
4309 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
f0832f13 4310#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 4311 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4312#endif
b481de9c
ZY		 4313 init_timer(&priv->statistics_periodic);
4314 priv->statistics_periodic.data = (unsigned long)priv;
4315 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4316}
4317
c79dd5b5 4318void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4319{
4320 del_timer_sync(&priv->statistics_periodic);
4321
4322 cancel_delayed_work(&priv->init_alive_start);
4323}
4324
3c424c28
TW		 4325
4326static struct iwl_hcmd_ops iwl4965_hcmd = {
7e8c519e 4327 .rxon_assoc = iwl4965_send_rxon_assoc,
3c424c28
TW		 4328};
4329
857485c0
TW		 4330static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4331 .enqueue_hcmd = iwl4965_enqueue_hcmd,
f0832f13
EG		 4332#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4333 .chain_noise_reset = iwl4965_chain_noise_reset,
4334 .gain_computation = iwl4965_gain_computation,
4335#endif
857485c0
TW		 4336};
4337
6bc913bd 4338static struct iwl_lib_ops iwl4965_lib = {
bf85ea4f 4339 .init_drv = iwl4965_init_drv,
5425e490 4340 .set_hw_params = iwl4965_hw_set_hw_params,
e2a722eb 4341 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
57aab75a
TW		 4342 .hw_nic_init = iwl4965_hw_nic_init,
4343 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
4344 .alive_notify = iwl4965_alive_notify,
4345 .load_ucode = iwl4965_load_bsm,
6f4083aa
TW		 4346 .apm_ops = {
4347 .set_pwr_src = iwl4965_set_pwr_src,
4348 },
6bc913bd 4349 .eeprom_ops = {
073d3f5f
TW		 4350 .regulatory_bands = {
4351 EEPROM_REGULATORY_BAND_1_CHANNELS,
4352 EEPROM_REGULATORY_BAND_2_CHANNELS,
4353 EEPROM_REGULATORY_BAND_3_CHANNELS,
4354 EEPROM_REGULATORY_BAND_4_CHANNELS,
4355 EEPROM_REGULATORY_BAND_5_CHANNELS,
4356 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
4357 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
4358 },
6bc913bd
AK		 4359 .verify_signature = iwlcore_eeprom_verify_signature,
4360 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4361 .release_semaphore = iwlcore_eeprom_release_semaphore,
073d3f5f 4362 .query_addr = iwlcore_eeprom_query_addr,
6bc913bd 4363 },
ad97edd2 4364 .radio_kill_sw = iwl4965_radio_kill_sw,
5da4b55f
MA		 4365 .set_power = iwl4965_set_power,
4366 .update_chain_flags = iwl4965_update_chain_flags,
6bc913bd
AK		 4367};
4368
4369static struct iwl_ops iwl4965_ops = {
4370 .lib = &iwl4965_lib,
3c424c28 4371 .hcmd = &iwl4965_hcmd,
857485c0 4372 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 4373};
4374
fed9017e 4375struct iwl_cfg iwl4965_agn_cfg = {
82b9a121 4376 .name = "4965AGN",
4bf775cd 4377 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
82b9a121 4378 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
073d3f5f 4379 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
6bc913bd 4380 .ops = &iwl4965_ops,
1ea87396 4381 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 4382};
4383
1ea87396
AK		 4384module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4385MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4386module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
4387MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
fcc76c6b
EG		 4388module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
4389MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
1ea87396
AK		 4390module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
4391MODULE_PARM_DESC(debug, "debug output mask");
4392module_param_named(
4393 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
4394MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4395
4396module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
4397MODULE_PARM_DESC(queues_num, "number of hw queues.");
4398
4399/* QoS */
4400module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
4401MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
4402module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
4403MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4404
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