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iwlwifi: store ucode version number
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <net/mac80211.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47 38#include <asm/unaligned.h>
b481de9c 39
6bc913bd 40#include "iwl-eeprom.h"
3e0d4cb1 41#include "iwl-dev.h"
fee1247a 42#include "iwl-core.h"
3395f6e9 43#include "iwl-io.h"
b481de9c 44#include "iwl-helpers.h"
f0832f13 45#include "iwl-calib.h"
5083e563 46#include "iwl-sta.h"
b481de9c 47
630fe9b6 48static int iwl4965_send_tx_power(struct iwl_priv *priv);
91dbc5bd 49static int iwl4965_hw_get_temperature(const struct iwl_priv *priv);
630fe9b6 50
d16dc48a
TW		 51/* Change firmware file name, using "-" and incrementing number,
52 * *only* when uCode interface or architecture changes so that it
53 * is not compatible with earlier drivers.
54 * This number will also appear in << 8 position of 1st dword of uCode file */
55#define IWL4965_UCODE_API "-2"
25e35a56 56#define IWL4965_MODULE_FIRMWARE "iwlwifi-4965" IWL4965_UCODE_API ".ucode"
d16dc48a
TW		 57
58
1ea87396
AK		 59/* module parameters */
60static struct iwl_mod_params iwl4965_mod_params = {
038669e4 61 .num_of_queues = IWL49_NUM_QUEUES,
9f17b318 62 .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
1ea87396
AK		 63 .enable_qos = 1,
64 .amsdu_size_8K = 1,
3a1081e8 65 .restart_fw = 1,
1ea87396
AK		 66 /* the rest are 0 by default */
67};
68
57aab75a
TW		 69/* check contents of special bootstrap uCode SRAM */
70static int iwl4965_verify_bsm(struct iwl_priv *priv)
71{
72 __le32 *image = priv->ucode_boot.v_addr;
73 u32 len = priv->ucode_boot.len;
74 u32 reg;
75 u32 val;
76
77 IWL_DEBUG_INFO("Begin verify bsm\n");
78
79 /* verify BSM SRAM contents */
80 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
81 for (reg = BSM_SRAM_LOWER_BOUND;
82 reg < BSM_SRAM_LOWER_BOUND + len;
83 reg += sizeof(u32), image++) {
84 val = iwl_read_prph(priv, reg);
85 if (val != le32_to_cpu(*image)) {
86 IWL_ERROR("BSM uCode verification failed at "
87 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
88 BSM_SRAM_LOWER_BOUND,
89 reg - BSM_SRAM_LOWER_BOUND, len,
90 val, le32_to_cpu(*image));
91 return -EIO;
92 }
93 }
94
95 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
96
97 return 0;
98}
99
100/**
101 * iwl4965_load_bsm - Load bootstrap instructions
102 *
103 * BSM operation:
104 *
105 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
106 * in special SRAM that does not power down during RFKILL. When powering back
107 * up after power-saving sleeps (or during initial uCode load), the BSM loads
108 * the bootstrap program into the on-board processor, and starts it.
109 *
110 * The bootstrap program loads (via DMA) instructions and data for a new
111 * program from host DRAM locations indicated by the host driver in the
112 * BSM_DRAM_* registers. Once the new program is loaded, it starts
113 * automatically.
114 *
115 * When initializing the NIC, the host driver points the BSM to the
116 * "initialize" uCode image. This uCode sets up some internal data, then
117 * notifies host via "initialize alive" that it is complete.
118 *
119 * The host then replaces the BSM_DRAM_* pointer values to point to the
120 * normal runtime uCode instructions and a backup uCode data cache buffer
121 * (filled initially with starting data values for the on-board processor),
122 * then triggers the "initialize" uCode to load and launch the runtime uCode,
123 * which begins normal operation.
124 *
125 * When doing a power-save shutdown, runtime uCode saves data SRAM into
126 * the backup data cache in DRAM before SRAM is powered down.
127 *
128 * When powering back up, the BSM loads the bootstrap program. This reloads
129 * the runtime uCode instructions and the backup data cache into SRAM,
130 * and re-launches the runtime uCode from where it left off.
131 */
132static int iwl4965_load_bsm(struct iwl_priv *priv)
133{
134 __le32 *image = priv->ucode_boot.v_addr;
135 u32 len = priv->ucode_boot.len;
136 dma_addr_t pinst;
137 dma_addr_t pdata;
138 u32 inst_len;
139 u32 data_len;
140 int i;
141 u32 done;
142 u32 reg_offset;
143 int ret;
144
145 IWL_DEBUG_INFO("Begin load bsm\n");
146
fe9b6b72
RR		 147 priv->ucode_type = UCODE_RT;
148
57aab75a
TW		 149 /* make sure bootstrap program is no larger than BSM's SRAM size */
150 if (len > IWL_MAX_BSM_SIZE)
151 return -EINVAL;
152
153 /* Tell bootstrap uCode where to find the "Initialize" uCode
154 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
2d87889f 155 * NOTE: iwl_init_alive_start() will replace these values,
57aab75a 156 * after the "initialize" uCode has run, to point to
2d87889f
TW		 157 * runtime/protocol instructions and backup data cache.
158 */
57aab75a
TW		 159 pinst = priv->ucode_init.p_addr >> 4;
160 pdata = priv->ucode_init_data.p_addr >> 4;
161 inst_len = priv->ucode_init.len;
162 data_len = priv->ucode_init_data.len;
163
164 ret = iwl_grab_nic_access(priv);
165 if (ret)
166 return ret;
167
168 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
169 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
170 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
171 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
172
173 /* Fill BSM memory with bootstrap instructions */
174 for (reg_offset = BSM_SRAM_LOWER_BOUND;
175 reg_offset < BSM_SRAM_LOWER_BOUND + len;
176 reg_offset += sizeof(u32), image++)
177 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
178
179 ret = iwl4965_verify_bsm(priv);
180 if (ret) {
181 iwl_release_nic_access(priv);
182 return ret;
183 }
184
185 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
186 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
187 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
188 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
189
190 /* Load bootstrap code into instruction SRAM now,
191 * to prepare to load "initialize" uCode */
192 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
193
194 /* Wait for load of bootstrap uCode to finish */
195 for (i = 0; i < 100; i++) {
196 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
197 if (!(done & BSM_WR_CTRL_REG_BIT_START))
198 break;
199 udelay(10);
200 }
201 if (i < 100)
202 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
203 else {
204 IWL_ERROR("BSM write did not complete!\n");
205 return -EIO;
206 }
207
208 /* Enable future boot loads whenever power management unit triggers it
209 * (e.g. when powering back up after power-save shutdown) */
210 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
211
212 iwl_release_nic_access(priv);
213
214 return 0;
215}
216
f3ccc08c
EG		 217/**
218 * iwl4965_set_ucode_ptrs - Set uCode address location
219 *
220 * Tell initialization uCode where to find runtime uCode.
221 *
222 * BSM registers initially contain pointers to initialization uCode.
223 * We need to replace them to load runtime uCode inst and data,
224 * and to save runtime data when powering down.
225 */
226static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
227{
228 dma_addr_t pinst;
229 dma_addr_t pdata;
230 unsigned long flags;
231 int ret = 0;
232
233 /* bits 35:4 for 4965 */
234 pinst = priv->ucode_code.p_addr >> 4;
235 pdata = priv->ucode_data_backup.p_addr >> 4;
236
237 spin_lock_irqsave(&priv->lock, flags);
238 ret = iwl_grab_nic_access(priv);
239 if (ret) {
240 spin_unlock_irqrestore(&priv->lock, flags);
241 return ret;
242 }
243
244 /* Tell bootstrap uCode where to find image to load */
245 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
246 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
247 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
248 priv->ucode_data.len);
249
a96a27f9 250 /* Inst byte count must be last to set up, bit 31 signals uCode
f3ccc08c
EG		 251 * that all new ptr/size info is in place */
252 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
253 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
254 iwl_release_nic_access(priv);
255
256 spin_unlock_irqrestore(&priv->lock, flags);
257
258 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
259
260 return ret;
261}
262
263/**
264 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
265 *
266 * Called after REPLY_ALIVE notification received from "initialize" uCode.
267 *
268 * The 4965 "initialize" ALIVE reply contains calibration data for:
269 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
270 * (3945 does not contain this data).
271 *
272 * Tell "initialize" uCode to go ahead and load the runtime uCode.
273*/
274static void iwl4965_init_alive_start(struct iwl_priv *priv)
275{
276 /* Check alive response for "valid" sign from uCode */
277 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
278 /* We had an error bringing up the hardware, so take it
279 * all the way back down so we can try again */
280 IWL_DEBUG_INFO("Initialize Alive failed.\n");
281 goto restart;
282 }
283
284 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
285 * This is a paranoid check, because we would not have gotten the
286 * "initialize" alive if code weren't properly loaded. */
287 if (iwl_verify_ucode(priv)) {
288 /* Runtime instruction load was bad;
289 * take it all the way back down so we can try again */
290 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
291 goto restart;
292 }
293
294 /* Calculate temperature */
91dbc5bd 295 priv->temperature = iwl4965_hw_get_temperature(priv);
f3ccc08c
EG		 296
297 /* Send pointers to protocol/runtime uCode image ... init code will
298 * load and launch runtime uCode, which will send us another "Alive"
299 * notification. */
300 IWL_DEBUG_INFO("Initialization Alive received.\n");
301 if (iwl4965_set_ucode_ptrs(priv)) {
302 /* Runtime instruction load won't happen;
303 * take it all the way back down so we can try again */
304 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
305 goto restart;
306 }
307 return;
308
309restart:
310 queue_work(priv->workqueue, &priv->restart);
311}
312
b481de9c
ZY		 313static int is_fat_channel(__le32 rxon_flags)
314{
315 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
316 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
317}
318
8614f360
TW		 319/*
320 * EEPROM handlers
321 */
0ef2ca67 322static u16 iwl4965_eeprom_calib_version(struct iwl_priv *priv)
8614f360 323{
0ef2ca67 324 return iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
8614f360 325}
b481de9c 326
da1bc453 327/*
a96a27f9 328 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
da1bc453
TW		 329 * must be called under priv->lock and mac access
330 */
331static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
b481de9c 332{
da1bc453 333 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
b481de9c
ZY		 334}
335
91238714 336static int iwl4965_apm_init(struct iwl_priv *priv)
b481de9c 337{
91238714 338 int ret = 0;
b481de9c 339
3395f6e9 340 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91238714 341 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
b481de9c 342
8f061891
TW		 343 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
344 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
345 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
346
91238714
TW		 347 /* set "initialization complete" bit to move adapter
348 * D0U* --> D0A* state */
3395f6e9 349 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 350
91238714
TW		 351 /* wait for clock stabilization */
352 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
353 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
354 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
355 if (ret < 0) {
356 IWL_DEBUG_INFO("Failed to init the card\n");
357 goto out;
b481de9c
ZY		 358 }
359
91238714
TW		 360 ret = iwl_grab_nic_access(priv);
361 if (ret)
362 goto out;
b481de9c 363
91238714 364 /* enable DMA */
8f061891
TW		 365 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
366 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 367
368 udelay(20);
369
8f061891 370 /* disable L1-Active */
3395f6e9 371 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
91238714 372 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 373
3395f6e9 374 iwl_release_nic_access(priv);
91238714 375out:
91238714
TW		 376 return ret;
377}
378
694cc56d
TW		 379
380static void iwl4965_nic_config(struct iwl_priv *priv)
91238714
TW		 381{
382 unsigned long flags;
91238714 383 u32 val;
694cc56d 384 u16 radio_cfg;
e7b63581 385 u16 link;
6f4083aa 386
b481de9c
ZY		 387 spin_lock_irqsave(&priv->lock, flags);
388
b661c819 389 if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
b481de9c
ZY		 390 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
391 /* Enable No Snoop field */
392 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
393 val & ~(1 << 11));
394 }
395
e7b63581 396 pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
b481de9c 397
8f061891 398 /* L1 is enabled by BIOS */
e7b63581 399 if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
a96a27f9 400 /* disable L0S disabled L1A enabled */
8f061891
TW		 401 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
402 else
403 /* L0S enabled L1A disabled */
404 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
b481de9c 405
694cc56d 406 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
b481de9c 407
694cc56d
TW		 408 /* write radio config values to register */
409 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
410 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
411 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
412 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
413 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
b481de9c 414
694cc56d 415 /* set CSR_HW_CONFIG_REG for uCode use */
3395f6e9 416 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
a395b920
TW		 417 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
418 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 419
694cc56d
TW		 420 priv->calib_info = (struct iwl_eeprom_calib_info *)
421 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
422
423 spin_unlock_irqrestore(&priv->lock, flags);
424}
425
46315e01
TW		 426static int iwl4965_apm_stop_master(struct iwl_priv *priv)
427{
428 int ret = 0;
429 unsigned long flags;
430
431 spin_lock_irqsave(&priv->lock, flags);
432
433 /* set stop master bit */
434 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
435
436 ret = iwl_poll_bit(priv, CSR_RESET,
437 CSR_RESET_REG_FLAG_MASTER_DISABLED,
438 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
439 if (ret < 0)
440 goto out;
441
442out:
443 spin_unlock_irqrestore(&priv->lock, flags);
444 IWL_DEBUG_INFO("stop master\n");
445
446 return ret;
447}
448
f118a91d
TW		 449static void iwl4965_apm_stop(struct iwl_priv *priv)
450{
451 unsigned long flags;
452
46315e01 453 iwl4965_apm_stop_master(priv);
f118a91d
TW		 454
455 spin_lock_irqsave(&priv->lock, flags);
456
457 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
458
459 udelay(10);
1d3e6c61
MA		 460 /* clear "init complete" move adapter D0A* --> D0U state */
461 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d
TW		 462 spin_unlock_irqrestore(&priv->lock, flags);
463}
464
7f066108 465static int iwl4965_apm_reset(struct iwl_priv *priv)
b481de9c 466{
7f066108 467 int ret = 0;
b481de9c
ZY		 468 unsigned long flags;
469
46315e01 470 iwl4965_apm_stop_master(priv);
b481de9c
ZY		 471
472 spin_lock_irqsave(&priv->lock, flags);
473
3395f6e9 474 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 475
476 udelay(10);
477
7f066108
TW		 478 /* FIXME: put here L1A -L0S w/a */
479
3395f6e9 480 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d 481
7f066108 482 ret = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 483 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
484 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
485
7f066108
TW		 486 if (ret)
487 goto out;
488
b481de9c
ZY		 489 udelay(10);
490
7f066108
TW		 491 ret = iwl_grab_nic_access(priv);
492 if (ret)
493 goto out;
494 /* Enable DMA and BSM Clock */
495 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
496 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c 497
7f066108 498 udelay(10);
b481de9c 499
7f066108
TW		 500 /* disable L1A */
501 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
502 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 503
7f066108 504 iwl_release_nic_access(priv);
b481de9c
ZY		 505
506 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
507 wake_up_interruptible(&priv->wait_command_queue);
508
7f066108 509out:
b481de9c
ZY		 510 spin_unlock_irqrestore(&priv->lock, flags);
511
7f066108 512 return ret;
b481de9c
ZY		 513}
514
b481de9c
ZY		 515/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
516 * Called after every association, but this runs only once!
517 * ... once chain noise is calibrated the first time, it's good forever. */
f0832f13 518static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 519{
f0832f13 520 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
b481de9c 521
3109ece1 522 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
f69f42a6 523 struct iwl_calib_diff_gain_cmd cmd;
b481de9c
ZY		 524
525 memset(&cmd, 0, sizeof(cmd));
0d950d84 526 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
b481de9c
ZY		 527 cmd.diff_gain_a = 0;
528 cmd.diff_gain_b = 0;
529 cmd.diff_gain_c = 0;
f0832f13
EG		 530 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
531 sizeof(cmd), &cmd))
532 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
b481de9c
ZY		 533 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
534 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
535 }
b481de9c
ZY		 536}
537
f0832f13
EG		 538static void iwl4965_gain_computation(struct iwl_priv *priv,
539 u32 *average_noise,
540 u16 min_average_noise_antenna_i,
541 u32 min_average_noise)
b481de9c 542{
f0832f13
EG		 543 int i, ret;
544 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
b481de9c 545
f0832f13 546 data->delta_gain_code[min_average_noise_antenna_i] = 0;
b481de9c 547
f0832f13
EG		 548 for (i = 0; i < NUM_RX_CHAINS; i++) {
549 s32 delta_g = 0;
b481de9c 550
f0832f13
EG		 551 if (!(data->disconn_array[i]) &&
552 (data->delta_gain_code[i] ==
b481de9c 553 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
f0832f13
EG		 554 delta_g = average_noise[i] - min_average_noise;
555 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
556 data->delta_gain_code[i] =
557 min(data->delta_gain_code[i],
558 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
559
560 data->delta_gain_code[i] =
561 (data->delta_gain_code[i] | (1 << 2));
562 } else {
563 data->delta_gain_code[i] = 0;
b481de9c 564 }
b481de9c 565 }
f0832f13
EG		 566 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
567 data->delta_gain_code[0],
568 data->delta_gain_code[1],
569 data->delta_gain_code[2]);
b481de9c 570
f0832f13
EG		 571 /* Differential gain gets sent to uCode only once */
572 if (!data->radio_write) {
f69f42a6 573 struct iwl_calib_diff_gain_cmd cmd;
f0832f13 574 data->radio_write = 1;
b481de9c 575
f0832f13 576 memset(&cmd, 0, sizeof(cmd));
0d950d84 577 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
f0832f13
EG		 578 cmd.diff_gain_a = data->delta_gain_code[0];
579 cmd.diff_gain_b = data->delta_gain_code[1];
580 cmd.diff_gain_c = data->delta_gain_code[2];
581 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
582 sizeof(cmd), &cmd);
583 if (ret)
584 IWL_DEBUG_CALIB("fail sending cmd "
585 "REPLY_PHY_CALIBRATION_CMD \n");
586
587 /* TODO we might want recalculate
588 * rx_chain in rxon cmd */
589
590 /* Mark so we run this algo only once! */
591 data->state = IWL_CHAIN_NOISE_CALIBRATED;
b481de9c 592 }
f0832f13
EG		 593 data->chain_noise_a = 0;
594 data->chain_noise_b = 0;
595 data->chain_noise_c = 0;
596 data->chain_signal_a = 0;
597 data->chain_signal_b = 0;
598 data->chain_signal_c = 0;
599 data->beacon_count = 0;
b481de9c
ZY		 600}
601
a326a5d0
EG		 602static void iwl4965_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
603 __le32 *tx_flags)
604{
e6a9854b 605 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
a326a5d0
EG		 606 *tx_flags |= TX_CMD_FLG_RTS_MSK;
607 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 608 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
a326a5d0
EG		 609 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
610 *tx_flags |= TX_CMD_FLG_CTS_MSK;
611 }
612}
613
b481de9c
ZY		 614static void iwl4965_bg_txpower_work(struct work_struct *work)
615{
c79dd5b5 616 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 617 txpower_work);
618
619 /* If a scan happened to start before we got here
620 * then just return; the statistics notification will
621 * kick off another scheduled work to compensate for
622 * any temperature delta we missed here. */
623 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
624 test_bit(STATUS_SCANNING, &priv->status))
625 return;
626
627 mutex_lock(&priv->mutex);
628
a96a27f9 629 /* Regardless of if we are associated, we must reconfigure the
b481de9c
ZY		 630 * TX power since frames can be sent on non-radar channels while
631 * not associated */
630fe9b6 632 iwl4965_send_tx_power(priv);
b481de9c
ZY		 633
634 /* Update last_temperature to keep is_calib_needed from running
635 * when it isn't needed... */
636 priv->last_temperature = priv->temperature;
637
638 mutex_unlock(&priv->mutex);
639}
640
641/*
642 * Acquire priv->lock before calling this function !
643 */
c79dd5b5 644static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 645{
3395f6e9 646 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 647 (index & 0xff) | (txq_id << 8));
12a81f60 648 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 649}
650
8b6eaea8
BC		 651/**
652 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
653 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
654 * @scd_retry: (1) Indicates queue will be used in aggregation mode
655 *
656 * NOTE: Acquire priv->lock before calling this function !
b481de9c 657 */
c79dd5b5 658static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
16466903 659 struct iwl_tx_queue *txq,
b481de9c
ZY		 660 int tx_fifo_id, int scd_retry)
661{
662 int txq_id = txq->q.id;
8b6eaea8
BC		 663
664 /* Find out whether to activate Tx queue */
c3056065 665 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
b481de9c 666
8b6eaea8 667 /* Set up and activate */
12a81f60 668 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 669 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
670 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
671 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
672 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
673 IWL49_SCD_QUEUE_STTS_REG_MSK);
b481de9c
ZY		 674
675 txq->sched_retry = scd_retry;
676
677 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 678 active ? "Activate" : "Deactivate",
b481de9c
ZY		 679 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
680}
681
682static const u16 default_queue_to_tx_fifo[] = {
683 IWL_TX_FIFO_AC3,
684 IWL_TX_FIFO_AC2,
685 IWL_TX_FIFO_AC1,
686 IWL_TX_FIFO_AC0,
038669e4 687 IWL49_CMD_FIFO_NUM,
b481de9c
ZY		 688 IWL_TX_FIFO_HCCA_1,
689 IWL_TX_FIFO_HCCA_2
690};
691
be1f3ab6 692static int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 693{
694 u32 a;
b481de9c 695 unsigned long flags;
857485c0 696 int ret;
31a73fe4 697 int i, chan;
40fc95d5 698 u32 reg_val;
b481de9c
ZY		 699
700 spin_lock_irqsave(&priv->lock, flags);
701
3395f6e9 702 ret = iwl_grab_nic_access(priv);
857485c0 703 if (ret) {
b481de9c 704 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 705 return ret;
b481de9c
ZY		 706 }
707
8b6eaea8 708 /* Clear 4965's internal Tx Scheduler data base */
12a81f60 709 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
038669e4
EG		 710 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
711 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
3395f6e9 712 iwl_write_targ_mem(priv, a, 0);
038669e4 713 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
3395f6e9 714 iwl_write_targ_mem(priv, a, 0);
5425e490 715 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
3395f6e9 716 iwl_write_targ_mem(priv, a, 0);
b481de9c 717
8b6eaea8 718 /* Tel 4965 where to find Tx byte count tables */
12a81f60 719 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
4ddbb7d0 720 priv->scd_bc_tbls.dma >> 10);
8b6eaea8 721
31a73fe4
WT		 722 /* Enable DMA channel */
723 for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
724 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
725 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
726 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
727
40fc95d5
WT		 728 /* Update FH chicken bits */
729 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
730 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
731 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
732
8b6eaea8 733 /* Disable chain mode for all queues */
12a81f60 734 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
b481de9c 735
8b6eaea8 736 /* Initialize each Tx queue (including the command queue) */
5425e490 737 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
8b6eaea8
BC		 738
739 /* TFD circular buffer read/write indexes */
12a81f60 740 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
3395f6e9 741 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
BC		 742
743 /* Max Tx Window size for Scheduler-ACK mode */
3395f6e9 744 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 745 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
746 (SCD_WIN_SIZE <<
747 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
748 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
BC		 749
750 /* Frame limit */
3395f6e9 751 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 752 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
753 sizeof(u32),
754 (SCD_FRAME_LIMIT <<
755 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
756 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c
ZY		 757
758 }
12a81f60 759 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
5425e490 760 (1 << priv->hw_params.max_txq_num) - 1);
b481de9c 761
8b6eaea8 762 /* Activate all Tx DMA/FIFO channels */
31a73fe4 763 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6));
b481de9c
ZY		 764
765 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
BC		 766
767 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 768 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
769 int ac = default_queue_to_tx_fifo[i];
36470749 770 iwl_txq_ctx_activate(priv, i);
b481de9c
ZY		 771 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
772 }
773
3395f6e9 774 iwl_release_nic_access(priv);
b481de9c
ZY		 775 spin_unlock_irqrestore(&priv->lock, flags);
776
857485c0 777 return ret;
b481de9c
ZY		 778}
779
f0832f13
EG		 780static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
781 .min_nrg_cck = 97,
782 .max_nrg_cck = 0,
783
784 .auto_corr_min_ofdm = 85,
785 .auto_corr_min_ofdm_mrc = 170,
786 .auto_corr_min_ofdm_x1 = 105,
787 .auto_corr_min_ofdm_mrc_x1 = 220,
788
789 .auto_corr_max_ofdm = 120,
790 .auto_corr_max_ofdm_mrc = 210,
791 .auto_corr_max_ofdm_x1 = 140,
792 .auto_corr_max_ofdm_mrc_x1 = 270,
793
794 .auto_corr_min_cck = 125,
795 .auto_corr_max_cck = 200,
796 .auto_corr_min_cck_mrc = 200,
797 .auto_corr_max_cck_mrc = 400,
798
799 .nrg_th_cck = 100,
800 .nrg_th_ofdm = 100,
801};
f0832f13 802
8b6eaea8 803/**
5425e490 804 * iwl4965_hw_set_hw_params
8b6eaea8
BC		 805 *
806 * Called when initializing driver
807 */
be1f3ab6 808static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 809{
316c30d9 810
038669e4 811 if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
1ea87396 812 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9 813 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
038669e4 814 IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
059ff826 815 return -EINVAL;
316c30d9 816 }
b481de9c 817
5425e490 818 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
f3f911d1 819 priv->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
4ddbb7d0
TW		 820 priv->hw_params.scd_bc_tbls_size =
821 IWL49_NUM_QUEUES * sizeof(struct iwl4965_scd_bc_tbl);
5425e490
TW		 822 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
823 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
099b40b7
RR		 824 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
825 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
826 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
827 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
828
ec35cf2a
TW		 829 priv->hw_params.tx_chains_num = 2;
830 priv->hw_params.rx_chains_num = 2;
fde0db31
GC		 831 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
832 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
099b40b7
RR		 833 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
834
f0832f13 835 priv->hw_params.sens = &iwl4965_sensitivity;
3e82a822 836
059ff826 837 return 0;
b481de9c
ZY		 838}
839
b481de9c
ZY		 840static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
841{
842 s32 sign = 1;
843
844 if (num < 0) {
845 sign = -sign;
846 num = -num;
847 }
848 if (denom < 0) {
849 sign = -sign;
850 denom = -denom;
851 }
852 *res = 1;
853 *res = ((num * 2 + denom) / (denom * 2)) * sign;
854
855 return 1;
856}
857
8b6eaea8
BC		 858/**
859 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
860 *
861 * Determines power supply voltage compensation for txpower calculations.
862 * Returns number of 1/2-dB steps to subtract from gain table index,
863 * to compensate for difference between power supply voltage during
864 * factory measurements, vs. current power supply voltage.
865 *
866 * Voltage indication is higher for lower voltage.
867 * Lower voltage requires more gain (lower gain table index).
868 */
b481de9c
ZY		 869static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
870 s32 current_voltage)
871{
872 s32 comp = 0;
873
874 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
875 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
876 return 0;
877
878 iwl4965_math_div_round(current_voltage - eeprom_voltage,
879 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
880
881 if (current_voltage > eeprom_voltage)
882 comp *= 2;
883 if ((comp < -2) || (comp > 2))
884 comp = 0;
885
886 return comp;
887}
888
b481de9c
ZY		 889static s32 iwl4965_get_tx_atten_grp(u16 channel)
890{
891 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
892 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
893 return CALIB_CH_GROUP_5;
894
895 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
896 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
897 return CALIB_CH_GROUP_1;
898
899 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
900 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
901 return CALIB_CH_GROUP_2;
902
903 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
904 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
905 return CALIB_CH_GROUP_3;
906
907 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
908 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
909 return CALIB_CH_GROUP_4;
910
911 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
912 return -1;
913}
914
c79dd5b5 915static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 916{
917 s32 b = -1;
918
919 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
073d3f5f 920 if (priv->calib_info->band_info[b].ch_from == 0)
b481de9c
ZY		 921 continue;
922
073d3f5f
TW		 923 if ((channel >= priv->calib_info->band_info[b].ch_from)
924 && (channel <= priv->calib_info->band_info[b].ch_to))
b481de9c
ZY		 925 break;
926 }
927
928 return b;
929}
930
931static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
932{
933 s32 val;
934
935 if (x2 == x1)
936 return y1;
937 else {
938 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
939 return val + y2;
940 }
941}
942
8b6eaea8
BC		 943/**
944 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
945 *
946 * Interpolates factory measurements from the two sample channels within a
947 * sub-band, to apply to channel of interest. Interpolation is proportional to
948 * differences in channel frequencies, which is proportional to differences
949 * in channel number.
950 */
c79dd5b5 951static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
073d3f5f 952 struct iwl_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 953{
954 s32 s = -1;
955 u32 c;
956 u32 m;
073d3f5f
TW		 957 const struct iwl_eeprom_calib_measure *m1;
958 const struct iwl_eeprom_calib_measure *m2;
959 struct iwl_eeprom_calib_measure *omeas;
b481de9c
ZY		 960 u32 ch_i1;
961 u32 ch_i2;
962
963 s = iwl4965_get_sub_band(priv, channel);
964 if (s >= EEPROM_TX_POWER_BANDS) {
6f147926 965 IWL_ERROR("Tx Power can not find channel %d\n", channel);
b481de9c
ZY		 966 return -1;
967 }
968
073d3f5f
TW		 969 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
970 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
b481de9c
ZY		 971 chan_info->ch_num = (u8) channel;
972
973 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
974 channel, s, ch_i1, ch_i2);
975
976 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
977 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
073d3f5f 978 m1 = &(priv->calib_info->band_info[s].ch1.
b481de9c 979 measurements[c][m]);
073d3f5f 980 m2 = &(priv->calib_info->band_info[s].ch2.
b481de9c
ZY		 981 measurements[c][m]);
982 omeas = &(chan_info->measurements[c][m]);
983
984 omeas->actual_pow =
985 (u8) iwl4965_interpolate_value(channel, ch_i1,
986 m1->actual_pow,
987 ch_i2,
988 m2->actual_pow);
989 omeas->gain_idx =
990 (u8) iwl4965_interpolate_value(channel, ch_i1,
991 m1->gain_idx, ch_i2,
992 m2->gain_idx);
993 omeas->temperature =
994 (u8) iwl4965_interpolate_value(channel, ch_i1,
995 m1->temperature,
996 ch_i2,
997 m2->temperature);
998 omeas->pa_det =
999 (s8) iwl4965_interpolate_value(channel, ch_i1,
1000 m1->pa_det, ch_i2,
1001 m2->pa_det);
1002
1003 IWL_DEBUG_TXPOWER
1004 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1005 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1006 IWL_DEBUG_TXPOWER
1007 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1008 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1009 IWL_DEBUG_TXPOWER
1010 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1011 m1->pa_det, m2->pa_det, omeas->pa_det);
1012 IWL_DEBUG_TXPOWER
1013 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1014 m1->temperature, m2->temperature,
1015 omeas->temperature);
1016 }
1017 }
1018
1019 return 0;
1020}
1021
1022/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1023 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1024static s32 back_off_table[] = {
1025 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1026 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1027 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1028 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1029 10 /* CCK */
1030};
1031
1032/* Thermal compensation values for txpower for various frequency ranges ...
1033 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 1034static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 1035 s32 degrees_per_05db_a;
1036 s32 degrees_per_05db_a_denom;
1037} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1038 {9, 2}, /* group 0 5.2, ch 34-43 */
1039 {4, 1}, /* group 1 5.2, ch 44-70 */
1040 {4, 1}, /* group 2 5.2, ch 71-124 */
1041 {4, 1}, /* group 3 5.2, ch 125-200 */
1042 {3, 1} /* group 4 2.4, ch all */
1043};
1044
1045static s32 get_min_power_index(s32 rate_power_index, u32 band)
1046{
1047 if (!band) {
1048 if ((rate_power_index & 7) <= 4)
1049 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1050 }
1051 return MIN_TX_GAIN_INDEX;
1052}
1053
1054struct gain_entry {
1055 u8 dsp;
1056 u8 radio;
1057};
1058
1059static const struct gain_entry gain_table[2][108] = {
1060 /* 5.2GHz power gain index table */
1061 {
1062 {123, 0x3F}, /* highest txpower */
1063 {117, 0x3F},
1064 {110, 0x3F},
1065 {104, 0x3F},
1066 {98, 0x3F},
1067 {110, 0x3E},
1068 {104, 0x3E},
1069 {98, 0x3E},
1070 {110, 0x3D},
1071 {104, 0x3D},
1072 {98, 0x3D},
1073 {110, 0x3C},
1074 {104, 0x3C},
1075 {98, 0x3C},
1076 {110, 0x3B},
1077 {104, 0x3B},
1078 {98, 0x3B},
1079 {110, 0x3A},
1080 {104, 0x3A},
1081 {98, 0x3A},
1082 {110, 0x39},
1083 {104, 0x39},
1084 {98, 0x39},
1085 {110, 0x38},
1086 {104, 0x38},
1087 {98, 0x38},
1088 {110, 0x37},
1089 {104, 0x37},
1090 {98, 0x37},
1091 {110, 0x36},
1092 {104, 0x36},
1093 {98, 0x36},
1094 {110, 0x35},
1095 {104, 0x35},
1096 {98, 0x35},
1097 {110, 0x34},
1098 {104, 0x34},
1099 {98, 0x34},
1100 {110, 0x33},
1101 {104, 0x33},
1102 {98, 0x33},
1103 {110, 0x32},
1104 {104, 0x32},
1105 {98, 0x32},
1106 {110, 0x31},
1107 {104, 0x31},
1108 {98, 0x31},
1109 {110, 0x30},
1110 {104, 0x30},
1111 {98, 0x30},
1112 {110, 0x25},
1113 {104, 0x25},
1114 {98, 0x25},
1115 {110, 0x24},
1116 {104, 0x24},
1117 {98, 0x24},
1118 {110, 0x23},
1119 {104, 0x23},
1120 {98, 0x23},
1121 {110, 0x22},
1122 {104, 0x18},
1123 {98, 0x18},
1124 {110, 0x17},
1125 {104, 0x17},
1126 {98, 0x17},
1127 {110, 0x16},
1128 {104, 0x16},
1129 {98, 0x16},
1130 {110, 0x15},
1131 {104, 0x15},
1132 {98, 0x15},
1133 {110, 0x14},
1134 {104, 0x14},
1135 {98, 0x14},
1136 {110, 0x13},
1137 {104, 0x13},
1138 {98, 0x13},
1139 {110, 0x12},
1140 {104, 0x08},
1141 {98, 0x08},
1142 {110, 0x07},
1143 {104, 0x07},
1144 {98, 0x07},
1145 {110, 0x06},
1146 {104, 0x06},
1147 {98, 0x06},
1148 {110, 0x05},
1149 {104, 0x05},
1150 {98, 0x05},
1151 {110, 0x04},
1152 {104, 0x04},
1153 {98, 0x04},
1154 {110, 0x03},
1155 {104, 0x03},
1156 {98, 0x03},
1157 {110, 0x02},
1158 {104, 0x02},
1159 {98, 0x02},
1160 {110, 0x01},
1161 {104, 0x01},
1162 {98, 0x01},
1163 {110, 0x00},
1164 {104, 0x00},
1165 {98, 0x00},
1166 {93, 0x00},
1167 {88, 0x00},
1168 {83, 0x00},
1169 {78, 0x00},
1170 },
1171 /* 2.4GHz power gain index table */
1172 {
1173 {110, 0x3f}, /* highest txpower */
1174 {104, 0x3f},
1175 {98, 0x3f},
1176 {110, 0x3e},
1177 {104, 0x3e},
1178 {98, 0x3e},
1179 {110, 0x3d},
1180 {104, 0x3d},
1181 {98, 0x3d},
1182 {110, 0x3c},
1183 {104, 0x3c},
1184 {98, 0x3c},
1185 {110, 0x3b},
1186 {104, 0x3b},
1187 {98, 0x3b},
1188 {110, 0x3a},
1189 {104, 0x3a},
1190 {98, 0x3a},
1191 {110, 0x39},
1192 {104, 0x39},
1193 {98, 0x39},
1194 {110, 0x38},
1195 {104, 0x38},
1196 {98, 0x38},
1197 {110, 0x37},
1198 {104, 0x37},
1199 {98, 0x37},
1200 {110, 0x36},
1201 {104, 0x36},
1202 {98, 0x36},
1203 {110, 0x35},
1204 {104, 0x35},
1205 {98, 0x35},
1206 {110, 0x34},
1207 {104, 0x34},
1208 {98, 0x34},
1209 {110, 0x33},
1210 {104, 0x33},
1211 {98, 0x33},
1212 {110, 0x32},
1213 {104, 0x32},
1214 {98, 0x32},
1215 {110, 0x31},
1216 {104, 0x31},
1217 {98, 0x31},
1218 {110, 0x30},
1219 {104, 0x30},
1220 {98, 0x30},
1221 {110, 0x6},
1222 {104, 0x6},
1223 {98, 0x6},
1224 {110, 0x5},
1225 {104, 0x5},
1226 {98, 0x5},
1227 {110, 0x4},
1228 {104, 0x4},
1229 {98, 0x4},
1230 {110, 0x3},
1231 {104, 0x3},
1232 {98, 0x3},
1233 {110, 0x2},
1234 {104, 0x2},
1235 {98, 0x2},
1236 {110, 0x1},
1237 {104, 0x1},
1238 {98, 0x1},
1239 {110, 0x0},
1240 {104, 0x0},
1241 {98, 0x0},
1242 {97, 0},
1243 {96, 0},
1244 {95, 0},
1245 {94, 0},
1246 {93, 0},
1247 {92, 0},
1248 {91, 0},
1249 {90, 0},
1250 {89, 0},
1251 {88, 0},
1252 {87, 0},
1253 {86, 0},
1254 {85, 0},
1255 {84, 0},
1256 {83, 0},
1257 {82, 0},
1258 {81, 0},
1259 {80, 0},
1260 {79, 0},
1261 {78, 0},
1262 {77, 0},
1263 {76, 0},
1264 {75, 0},
1265 {74, 0},
1266 {73, 0},
1267 {72, 0},
1268 {71, 0},
1269 {70, 0},
1270 {69, 0},
1271 {68, 0},
1272 {67, 0},
1273 {66, 0},
1274 {65, 0},
1275 {64, 0},
1276 {63, 0},
1277 {62, 0},
1278 {61, 0},
1279 {60, 0},
1280 {59, 0},
1281 }
1282};
1283
c79dd5b5 1284static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 1285 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 1286 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 1287{
1288 u8 saturation_power;
1289 s32 target_power;
1290 s32 user_target_power;
1291 s32 power_limit;
1292 s32 current_temp;
1293 s32 reg_limit;
1294 s32 current_regulatory;
1295 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1296 int i;
1297 int c;
bf85ea4f 1298 const struct iwl_channel_info *ch_info = NULL;
073d3f5f
TW		 1299 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1300 const struct iwl_eeprom_calib_measure *measurement;
b481de9c
ZY		 1301 s16 voltage;
1302 s32 init_voltage;
1303 s32 voltage_compensation;
1304 s32 degrees_per_05db_num;
1305 s32 degrees_per_05db_denom;
1306 s32 factory_temp;
1307 s32 temperature_comp[2];
1308 s32 factory_gain_index[2];
1309 s32 factory_actual_pwr[2];
1310 s32 power_index;
1311
b481de9c
ZY		 1312 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1313 * are used for indexing into txpower table) */
630fe9b6 1314 user_target_power = 2 * priv->tx_power_user_lmt;
b481de9c
ZY		 1315
1316 /* Get current (RXON) channel, band, width */
b481de9c
ZY		 1317 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1318 is_fat);
1319
630fe9b6
TW		 1320 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1321
1322 if (!is_channel_valid(ch_info))
b481de9c
ZY		 1323 return -EINVAL;
1324
1325 /* get txatten group, used to select 1) thermal txpower adjustment
1326 * and 2) mimo txpower balance between Tx chains. */
1327 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1328 if (txatten_grp < 0)
1329 return -EINVAL;
1330
1331 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1332 channel, txatten_grp);
1333
1334 if (is_fat) {
1335 if (ctrl_chan_high)
1336 channel -= 2;
1337 else
1338 channel += 2;
1339 }
1340
1341 /* hardware txpower limits ...
1342 * saturation (clipping distortion) txpowers are in half-dBm */
1343 if (band)
073d3f5f 1344 saturation_power = priv->calib_info->saturation_power24;
b481de9c 1345 else
073d3f5f 1346 saturation_power = priv->calib_info->saturation_power52;
b481de9c
ZY		 1347
1348 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1349 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1350 if (band)
1351 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1352 else
1353 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1354 }
1355
1356 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1357 * max_power_avg values are in dBm, convert * 2 */
1358 if (is_fat)
1359 reg_limit = ch_info->fat_max_power_avg * 2;
1360 else
1361 reg_limit = ch_info->max_power_avg * 2;
1362
1363 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1364 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1365 if (band)
1366 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1367 else
1368 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1369 }
1370
1371 /* Interpolate txpower calibration values for this channel,
1372 * based on factory calibration tests on spaced channels. */
1373 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1374
1375 /* calculate tx gain adjustment based on power supply voltage */
073d3f5f 1376 voltage = priv->calib_info->voltage;
b481de9c
ZY		 1377 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1378 voltage_compensation =
1379 iwl4965_get_voltage_compensation(voltage, init_voltage);
1380
1381 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
1382 init_voltage,
1383 voltage, voltage_compensation);
1384
1385 /* get current temperature (Celsius) */
1386 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1387 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1388 current_temp = KELVIN_TO_CELSIUS(current_temp);
1389
1390 /* select thermal txpower adjustment params, based on channel group
1391 * (same frequency group used for mimo txatten adjustment) */
1392 degrees_per_05db_num =
1393 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1394 degrees_per_05db_denom =
1395 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1396
1397 /* get per-chain txpower values from factory measurements */
1398 for (c = 0; c < 2; c++) {
1399 measurement = &ch_eeprom_info.measurements[c][1];
1400
1401 /* txgain adjustment (in half-dB steps) based on difference
1402 * between factory and current temperature */
1403 factory_temp = measurement->temperature;
1404 iwl4965_math_div_round((current_temp - factory_temp) *
1405 degrees_per_05db_denom,
1406 degrees_per_05db_num,
1407 &temperature_comp[c]);
1408
1409 factory_gain_index[c] = measurement->gain_idx;
1410 factory_actual_pwr[c] = measurement->actual_pow;
1411
1412 IWL_DEBUG_TXPOWER("chain = %d\n", c);
1413 IWL_DEBUG_TXPOWER("fctry tmp %d, "
1414 "curr tmp %d, comp %d steps\n",
1415 factory_temp, current_temp,
1416 temperature_comp[c]);
1417
1418 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
1419 factory_gain_index[c],
1420 factory_actual_pwr[c]);
1421 }
1422
1423 /* for each of 33 bit-rates (including 1 for CCK) */
1424 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1425 u8 is_mimo_rate;
bb8c093b 1426 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 1427
1428 /* for mimo, reduce each chain's txpower by half
1429 * (3dB, 6 steps), so total output power is regulatory
1430 * compliant. */
1431 if (i & 0x8) {
1432 current_regulatory = reg_limit -
1433 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1434 is_mimo_rate = 1;
1435 } else {
1436 current_regulatory = reg_limit;
1437 is_mimo_rate = 0;
1438 }
1439
1440 /* find txpower limit, either hardware or regulatory */
1441 power_limit = saturation_power - back_off_table[i];
1442 if (power_limit > current_regulatory)
1443 power_limit = current_regulatory;
1444
1445 /* reduce user's txpower request if necessary
1446 * for this rate on this channel */
1447 target_power = user_target_power;
1448 if (target_power > power_limit)
1449 target_power = power_limit;
1450
1451 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
1452 i, saturation_power - back_off_table[i],
1453 current_regulatory, user_target_power,
1454 target_power);
1455
1456 /* for each of 2 Tx chains (radio transmitters) */
1457 for (c = 0; c < 2; c++) {
1458 s32 atten_value;
1459
1460 if (is_mimo_rate)
1461 atten_value =
1462 (s32)le32_to_cpu(priv->card_alive_init.
1463 tx_atten[txatten_grp][c]);
1464 else
1465 atten_value = 0;
1466
1467 /* calculate index; higher index means lower txpower */
1468 power_index = (u8) (factory_gain_index[c] -
1469 (target_power -
1470 factory_actual_pwr[c]) -
1471 temperature_comp[c] -
1472 voltage_compensation +
1473 atten_value);
1474
1475/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
1476 power_index); */
1477
1478 if (power_index < get_min_power_index(i, band))
1479 power_index = get_min_power_index(i, band);
1480
1481 /* adjust 5 GHz index to support negative indexes */
1482 if (!band)
1483 power_index += 9;
1484
1485 /* CCK, rate 32, reduce txpower for CCK */
1486 if (i == POWER_TABLE_CCK_ENTRY)
1487 power_index +=
1488 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1489
1490 /* stay within the table! */
1491 if (power_index > 107) {
1492 IWL_WARNING("txpower index %d > 107\n",
1493 power_index);
1494 power_index = 107;
1495 }
1496 if (power_index < 0) {
1497 IWL_WARNING("txpower index %d < 0\n",
1498 power_index);
1499 power_index = 0;
1500 }
1501
1502 /* fill txpower command for this rate/chain */
1503 tx_power.s.radio_tx_gain[c] =
1504 gain_table[band][power_index].radio;
1505 tx_power.s.dsp_predis_atten[c] =
1506 gain_table[band][power_index].dsp;
1507
1508 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
1509 "gain 0x%02x dsp %d\n",
1510 c, atten_value, power_index,
1511 tx_power.s.radio_tx_gain[c],
1512 tx_power.s.dsp_predis_atten[c]);
3ac7f146 1513 } /* for each chain */
b481de9c
ZY		 1514
1515 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1516
3ac7f146 1517 } /* for each rate */
b481de9c
ZY		 1518
1519 return 0;
1520}
1521
1522/**
630fe9b6 1523 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
b481de9c
ZY		 1524 *
1525 * Uses the active RXON for channel, band, and characteristics (fat, high)
630fe9b6 1526 * The power limit is taken from priv->tx_power_user_lmt.
b481de9c 1527 */
630fe9b6 1528static int iwl4965_send_tx_power(struct iwl_priv *priv)
b481de9c 1529{
bb8c093b 1530 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 1531 int ret;
b481de9c
ZY		 1532 u8 band = 0;
1533 u8 is_fat = 0;
1534 u8 ctrl_chan_high = 0;
1535
1536 if (test_bit(STATUS_SCANNING, &priv->status)) {
1537 /* If this gets hit a lot, switch it to a BUG() and catch
1538 * the stack trace to find out who is calling this during
1539 * a scan. */
1540 IWL_WARNING("TX Power requested while scanning!\n");
1541 return -EAGAIN;
1542 }
1543
8318d78a 1544 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 1545
1546 is_fat = is_fat_channel(priv->active_rxon.flags);
1547
1548 if (is_fat &&
1549 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1550 ctrl_chan_high = 1;
1551
1552 cmd.band = band;
1553 cmd.channel = priv->active_rxon.channel;
1554
857485c0 1555 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 1556 le16_to_cpu(priv->active_rxon.channel),
1557 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 1558 if (ret)
1559 goto out;
b481de9c 1560
857485c0
TW		 1561 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1562
1563out:
1564 return ret;
b481de9c
ZY		 1565}
1566
7e8c519e
TW		 1567static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1568{
1569 int ret = 0;
1570 struct iwl4965_rxon_assoc_cmd rxon_assoc;
c1adf9fb
GG		 1571 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1572 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
7e8c519e
TW		 1573
1574 if ((rxon1->flags == rxon2->flags) &&
1575 (rxon1->filter_flags == rxon2->filter_flags) &&
1576 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1577 (rxon1->ofdm_ht_single_stream_basic_rates ==
1578 rxon2->ofdm_ht_single_stream_basic_rates) &&
1579 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1580 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1581 (rxon1->rx_chain == rxon2->rx_chain) &&
1582 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1583 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1584 return 0;
1585 }
1586
1587 rxon_assoc.flags = priv->staging_rxon.flags;
1588 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1589 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1590 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1591 rxon_assoc.reserved = 0;
1592 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1593 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1594 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1595 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1596 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1597
1598 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1599 sizeof(rxon_assoc), &rxon_assoc, NULL);
1600 if (ret)
1601 return ret;
1602
1603 return ret;
1604}
1605
3c935522 1606#ifdef IEEE80211_CONF_CHANNEL_SWITCH
a33c2f47 1607static int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1608{
1609 int rc;
1610 u8 band = 0;
1611 u8 is_fat = 0;
1612 u8 ctrl_chan_high = 0;
bb8c093b 1613 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 1614 const struct iwl_channel_info *ch_info;
b481de9c 1615
8318d78a 1616 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 1617
8622e705 1618 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 1619
1620 is_fat = is_fat_channel(priv->staging_rxon.flags);
1621
1622 if (is_fat &&
1623 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1624 ctrl_chan_high = 1;
1625
1626 cmd.band = band;
1627 cmd.expect_beacon = 0;
1628 cmd.channel = cpu_to_le16(channel);
1629 cmd.rxon_flags = priv->active_rxon.flags;
1630 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
1631 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1632 if (ch_info)
1633 cmd.expect_beacon = is_channel_radar(ch_info);
1634 else
1635 cmd.expect_beacon = 1;
1636
1637 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
1638 ctrl_chan_high, &cmd.tx_power);
1639 if (rc) {
1640 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
1641 return rc;
1642 }
1643
857485c0 1644 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 1645 return rc;
1646}
3c935522 1647#endif
b481de9c 1648
8b6eaea8 1649/**
e2a722eb 1650 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
8b6eaea8 1651 */
e2a722eb 1652static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 1653 struct iwl_tx_queue *txq,
e2a722eb 1654 u16 byte_cnt)
b481de9c 1655{
4ddbb7d0 1656 struct iwl4965_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab
TW		 1657 int txq_id = txq->q.id;
1658 int write_ptr = txq->q.write_ptr;
1659 int len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1660 __le16 bc_ent;
b481de9c 1661
127901ab 1662 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
b481de9c 1663
127901ab 1664 bc_ent = cpu_to_le16(len & 0xFFF);
8b6eaea8 1665 /* Set up byte count within first 256 entries */
4ddbb7d0 1666 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
b481de9c 1667
8b6eaea8 1668 /* If within first 64 entries, duplicate at end */
127901ab 1669 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 1670 scd_bc_tbl[txq_id].
127901ab 1671 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
b481de9c
ZY		 1672}
1673
b481de9c
ZY		 1674/**
1675 * sign_extend - Sign extend a value using specified bit as sign-bit
1676 *
1677 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1678 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1679 *
1680 * @param oper value to sign extend
1681 * @param index 0 based bit index (0<=index<32) to sign bit
1682 */
1683static s32 sign_extend(u32 oper, int index)
1684{
1685 u8 shift = 31 - index;
1686
1687 return (s32)(oper << shift) >> shift;
1688}
1689
1690/**
91dbc5bd 1691 * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
b481de9c
ZY		 1692 * @statistics: Provides the temperature reading from the uCode
1693 *
1694 * A return of <0 indicates bogus data in the statistics
1695 */
91dbc5bd 1696static int iwl4965_hw_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 1697{
1698 s32 temperature;
1699 s32 vt;
1700 s32 R1, R2, R3;
1701 u32 R4;
1702
1703 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1704 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
1705 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
1706 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1707 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1708 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1709 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1710 } else {
1711 IWL_DEBUG_TEMP("Running temperature calibration\n");
1712 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1713 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1714 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1715 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1716 }
1717
1718 /*
8b6eaea8 1719 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 1720 *
1721 * NOTE If we haven't received a statistics notification yet
1722 * with an updated temperature, use R4 provided to us in the
8b6eaea8
BC		 1723 * "initialize" ALIVE response.
1724 */
b481de9c
ZY		 1725 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1726 vt = sign_extend(R4, 23);
1727 else
1728 vt = sign_extend(
1729 le32_to_cpu(priv->statistics.general.temperature), 23);
1730
91dbc5bd 1731 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
b481de9c
ZY		 1732
1733 if (R3 == R1) {
1734 IWL_ERROR("Calibration conflict R1 == R3\n");
1735 return -1;
1736 }
1737
1738 /* Calculate temperature in degrees Kelvin, adjust by 97%.
1739 * Add offset to center the adjustment around 0 degrees Centigrade. */
1740 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1741 temperature /= (R3 - R1);
91dbc5bd 1742 temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
b481de9c 1743
91dbc5bd
EG		 1744 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n",
1745 temperature, KELVIN_TO_CELSIUS(temperature));
b481de9c
ZY		 1746
1747 return temperature;
1748}
1749
1750/* Adjust Txpower only if temperature variance is greater than threshold. */
1751#define IWL_TEMPERATURE_THRESHOLD 3
1752
1753/**
1754 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1755 *
1756 * If the temperature changed has changed sufficiently, then a recalibration
1757 * is needed.
1758 *
1759 * Assumes caller will replace priv->last_temperature once calibration
1760 * executed.
1761 */
c79dd5b5 1762static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1763{
1764 int temp_diff;
1765
1766 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
1767 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
1768 return 0;
1769 }
1770
1771 temp_diff = priv->temperature - priv->last_temperature;
1772
1773 /* get absolute value */
1774 if (temp_diff < 0) {
1775 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
1776 temp_diff = -temp_diff;
1777 } else if (temp_diff == 0)
1778 IWL_DEBUG_POWER("Same temp, \n");
1779 else
1780 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
1781
1782 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
1783 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
1784 return 0;
1785 }
1786
1787 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
1788
1789 return 1;
1790}
1791
5225640b 1792static void iwl4965_temperature_calib(struct iwl_priv *priv)
b481de9c 1793{
b481de9c 1794 s32 temp;
b481de9c 1795
91dbc5bd 1796 temp = iwl4965_hw_get_temperature(priv);
b481de9c
ZY		 1797 if (temp < 0)
1798 return;
1799
1800 if (priv->temperature != temp) {
1801 if (priv->temperature)
1802 IWL_DEBUG_TEMP("Temperature changed "
1803 "from %dC to %dC\n",
1804 KELVIN_TO_CELSIUS(priv->temperature),
1805 KELVIN_TO_CELSIUS(temp));
1806 else
1807 IWL_DEBUG_TEMP("Temperature "
1808 "initialized to %dC\n",
1809 KELVIN_TO_CELSIUS(temp));
1810 }
1811
1812 priv->temperature = temp;
1813 set_bit(STATUS_TEMPERATURE, &priv->status);
1814
203566f3
EG		 1815 if (!priv->disable_tx_power_cal &&
1816 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1817 iwl4965_is_temp_calib_needed(priv))
b481de9c
ZY		 1818 queue_work(priv->workqueue, &priv->txpower_work);
1819}
1820
fe01b477
RR		 1821/**
1822 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
1823 */
c79dd5b5 1824static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 1825 u16 txq_id)
1826{
1827 /* Simply stop the queue, but don't change any configuration;
1828 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3395f6e9 1829 iwl_write_prph(priv,
12a81f60 1830 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 1831 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1832 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
fe01b477 1833}
b481de9c 1834
fe01b477 1835/**
7f3e4bb6 1836 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
b095d03a 1837 * priv->lock must be held by the caller
fe01b477 1838 */
30e553e3
TW		 1839static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1840 u16 ssn_idx, u8 tx_fifo)
fe01b477 1841{
b095d03a
RR		 1842 int ret = 0;
1843
9f17b318
TW		 1844 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1845 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
1846 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1847 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1848 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
fe01b477 1849 return -EINVAL;
b481de9c
ZY		 1850 }
1851
3395f6e9 1852 ret = iwl_grab_nic_access(priv);
b095d03a
RR		 1853 if (ret)
1854 return ret;
1855
fe01b477
RR		 1856 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1857
12a81f60 1858 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
fe01b477
RR		 1859
1860 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1861 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1862 /* supposes that ssn_idx is valid (!= 0xFFF) */
1863 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1864
12a81f60 1865 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
36470749 1866 iwl_txq_ctx_deactivate(priv, txq_id);
fe01b477
RR		 1867 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1868
3395f6e9 1869 iwl_release_nic_access(priv);
b095d03a 1870
fe01b477
RR		 1871 return 0;
1872}
b481de9c 1873
8b6eaea8
BC		 1874/**
1875 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
1876 */
c79dd5b5 1877static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 1878 u16 txq_id)
1879{
1880 u32 tbl_dw_addr;
1881 u32 tbl_dw;
1882 u16 scd_q2ratid;
1883
30e553e3 1884 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
b481de9c
ZY		 1885
1886 tbl_dw_addr = priv->scd_base_addr +
038669e4 1887 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
b481de9c 1888
3395f6e9 1889 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 1890
1891 if (txq_id & 0x1)
1892 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1893 else
1894 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1895
3395f6e9 1896 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 1897
1898 return 0;
1899}
1900
fe01b477 1901
b481de9c 1902/**
8b6eaea8
BC		 1903 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
1904 *
7f3e4bb6 1905 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
8b6eaea8 1906 * i.e. it must be one of the higher queues used for aggregation
b481de9c 1907 */
30e553e3
TW		 1908static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1909 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
b481de9c
ZY		 1910{
1911 unsigned long flags;
30e553e3 1912 int ret;
b481de9c
ZY		 1913 u16 ra_tid;
1914
9f17b318
TW		 1915 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1916 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
1917 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1918 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1919 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
1920 return -EINVAL;
1921 }
b481de9c
ZY		 1922
1923 ra_tid = BUILD_RAxTID(sta_id, tid);
1924
8b6eaea8 1925 /* Modify device's station table to Tx this TID */
9f58671e 1926 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
b481de9c
ZY		 1927
1928 spin_lock_irqsave(&priv->lock, flags);
30e553e3
TW		 1929 ret = iwl_grab_nic_access(priv);
1930 if (ret) {
b481de9c 1931 spin_unlock_irqrestore(&priv->lock, flags);
30e553e3 1932 return ret;
b481de9c
ZY		 1933 }
1934
8b6eaea8 1935 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 1936 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1937
8b6eaea8 1938 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 1939 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1940
8b6eaea8 1941 /* Set this queue as a chain-building queue */
12a81f60 1942 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 1943
8b6eaea8
BC		 1944 /* Place first TFD at index corresponding to start sequence number.
1945 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 1946 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1947 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 1948 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1949
8b6eaea8 1950 /* Set up Tx window size and frame limit for this queue */
3395f6e9 1951 iwl_write_targ_mem(priv,
038669e4
EG		 1952 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
1953 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1954 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
b481de9c 1955
3395f6e9 1956 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 1957 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1958 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
1959 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c 1960
12a81f60 1961 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 1962
8b6eaea8 1963 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 1964 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1965
3395f6e9 1966 iwl_release_nic_access(priv);
b481de9c
ZY		 1967 spin_unlock_irqrestore(&priv->lock, flags);
1968
1969 return 0;
1970}
1971
133636de 1972
c1adf9fb
GG		 1973static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
1974{
1975 switch (cmd_id) {
1976 case REPLY_RXON:
1977 return (u16) sizeof(struct iwl4965_rxon_cmd);
1978 default:
1979 return len;
1980 }
1981}
1982
133636de
TW		 1983static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1984{
1985 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
1986 addsta->mode = cmd->mode;
1987 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
1988 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
1989 addsta->station_flags = cmd->station_flags;
1990 addsta->station_flags_msk = cmd->station_flags_msk;
1991 addsta->tid_disable_tx = cmd->tid_disable_tx;
1992 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
1993 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
1994 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
1995 addsta->reserved1 = __constant_cpu_to_le16(0);
1996 addsta->reserved2 = __constant_cpu_to_le32(0);
1997
1998 return (u16)sizeof(struct iwl4965_addsta_cmd);
1999}
f20217d9 2000
f20217d9
TW		 2001static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
2002{
25a6572c 2003 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
f20217d9
TW		 2004}
2005
2006/**
a96a27f9 2007 * iwl4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
f20217d9
TW		 2008 */
2009static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
2010 struct iwl_ht_agg *agg,
25a6572c
TW		 2011 struct iwl4965_tx_resp *tx_resp,
2012 int txq_id, u16 start_idx)
f20217d9
TW		 2013{
2014 u16 status;
25a6572c 2015 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
f20217d9
TW		 2016 struct ieee80211_tx_info *info = NULL;
2017 struct ieee80211_hdr *hdr = NULL;
e7d326ac 2018 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 2019 int i, sh, idx;
f20217d9 2020 u16 seq;
f20217d9
TW		 2021 if (agg->wait_for_ba)
2022 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
2023
2024 agg->frame_count = tx_resp->frame_count;
2025 agg->start_idx = start_idx;
e7d326ac 2026 agg->rate_n_flags = rate_n_flags;
f20217d9
TW		 2027 agg->bitmap = 0;
2028
3fd07a1e 2029 /* num frames attempted by Tx command */
f20217d9
TW		 2030 if (agg->frame_count == 1) {
2031 /* Only one frame was attempted; no block-ack will arrive */
2032 status = le16_to_cpu(frame_status[0].status);
25a6572c 2033 idx = start_idx;
f20217d9
TW		 2034
2035 /* FIXME: code repetition */
2036 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
2037 agg->frame_count, agg->start_idx, idx);
2038
2039 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
e6a9854b 2040 info->status.rates[0].count = tx_resp->failure_frame + 1;
f20217d9 2041 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
c3056065 2042 info->flags |= iwl_is_tx_success(status) ?
f20217d9 2043 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 2044 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
f20217d9
TW		 2045 /* FIXME: code repetition end */
2046
2047 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
2048 status & 0xff, tx_resp->failure_frame);
e7d326ac 2049 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
f20217d9
TW		 2050
2051 agg->wait_for_ba = 0;
2052 } else {
2053 /* Two or more frames were attempted; expect block-ack */
2054 u64 bitmap = 0;
2055 int start = agg->start_idx;
2056
2057 /* Construct bit-map of pending frames within Tx window */
2058 for (i = 0; i < agg->frame_count; i++) {
2059 u16 sc;
2060 status = le16_to_cpu(frame_status[i].status);
2061 seq = le16_to_cpu(frame_status[i].sequence);
2062 idx = SEQ_TO_INDEX(seq);
2063 txq_id = SEQ_TO_QUEUE(seq);
2064
2065 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
2066 AGG_TX_STATE_ABORT_MSK))
2067 continue;
2068
2069 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2070 agg->frame_count, txq_id, idx);
2071
2072 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
2073
2074 sc = le16_to_cpu(hdr->seq_ctrl);
2075 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
2076 IWL_ERROR("BUG_ON idx doesn't match seq control"
2077 " idx=%d, seq_idx=%d, seq=%d\n",
2078 idx, SEQ_TO_SN(sc),
2079 hdr->seq_ctrl);
2080 return -1;
2081 }
2082
2083 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
2084 i, idx, SEQ_TO_SN(sc));
2085
2086 sh = idx - start;
2087 if (sh > 64) {
2088 sh = (start - idx) + 0xff;
2089 bitmap = bitmap << sh;
2090 sh = 0;
2091 start = idx;
2092 } else if (sh < -64)
2093 sh = 0xff - (start - idx);
2094 else if (sh < 0) {
2095 sh = start - idx;
2096 start = idx;
2097 bitmap = bitmap << sh;
2098 sh = 0;
2099 }
4aa41f12
EG		 2100 bitmap |= 1ULL << sh;
2101 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
2102 start, (unsigned long long)bitmap);
f20217d9
TW		 2103 }
2104
2105 agg->bitmap = bitmap;
2106 agg->start_idx = start;
f20217d9
TW		 2107 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
2108 agg->frame_count, agg->start_idx,
2109 (unsigned long long)agg->bitmap);
2110
2111 if (bitmap)
2112 agg->wait_for_ba = 1;
2113 }
2114 return 0;
2115}
f20217d9
TW		 2116
2117/**
2118 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
2119 */
2120static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
2121 struct iwl_rx_mem_buffer *rxb)
2122{
2123 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2124 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2125 int txq_id = SEQ_TO_QUEUE(sequence);
2126 int index = SEQ_TO_INDEX(sequence);
2127 struct iwl_tx_queue *txq = &priv->txq[txq_id];
3fd07a1e 2128 struct ieee80211_hdr *hdr;
f20217d9
TW		 2129 struct ieee80211_tx_info *info;
2130 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
25a6572c 2131 u32 status = le32_to_cpu(tx_resp->u.status);
3fd07a1e
TW		 2132 int tid = MAX_TID_COUNT;
2133 int sta_id;
2134 int freed;
f20217d9 2135 u8 *qc = NULL;
f20217d9
TW		 2136
2137 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
2138 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
2139 "is out of range [0-%d] %d %d\n", txq_id,
2140 index, txq->q.n_bd, txq->q.write_ptr,
2141 txq->q.read_ptr);
2142 return;
2143 }
2144
2145 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
2146 memset(&info->status, 0, sizeof(info->status));
2147
f20217d9 2148 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
3fd07a1e 2149 if (ieee80211_is_data_qos(hdr->frame_control)) {
fd7c8a40 2150 qc = ieee80211_get_qos_ctl(hdr);
f20217d9
TW		 2151 tid = qc[0] & 0xf;
2152 }
2153
2154 sta_id = iwl_get_ra_sta_id(priv, hdr);
2155 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
2156 IWL_ERROR("Station not known\n");
2157 return;
2158 }
2159
2160 if (txq->sched_retry) {
2161 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2162 struct iwl_ht_agg *agg = NULL;
2163
3fd07a1e 2164 WARN_ON(!qc);
f20217d9
TW		 2165
2166 agg = &priv->stations[sta_id].tid[tid].agg;
2167
25a6572c 2168 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
f20217d9 2169
3235427e
RR		 2170 /* check if BAR is needed */
2171 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
2172 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
f20217d9
TW		 2173
2174 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
f20217d9
TW		 2175 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2176 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
2177 "%d index %d\n", scd_ssn , index);
17b88929 2178 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
f20217d9
TW		 2179 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2180
3fd07a1e
TW		 2181 if (priv->mac80211_registered &&
2182 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
2183 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
f20217d9
TW		 2184 if (agg->state == IWL_AGG_OFF)
2185 ieee80211_wake_queue(priv->hw, txq_id);
2186 else
3fd07a1e
TW		 2187 ieee80211_wake_queue(priv->hw,
2188 txq->swq_id);
f20217d9 2189 }
f20217d9
TW		 2190 }
2191 } else {
e6a9854b 2192 info->status.rates[0].count = tx_resp->failure_frame + 1;
3fd07a1e
TW		 2193 info->flags |= iwl_is_tx_success(status) ?
2194 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 2195 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 2196 le32_to_cpu(tx_resp->rate_n_flags),
2197 info);
2198
3fd07a1e
TW		 2199 IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) "
2200 "rate_n_flags 0x%x retries %d\n",
2201 txq_id,
2202 iwl_get_tx_fail_reason(status), status,
2203 le32_to_cpu(tx_resp->rate_n_flags),
2204 tx_resp->failure_frame);
e7d326ac 2205
3fd07a1e 2206 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
ed7fafec 2207 if (qc && likely(sta_id != IWL_INVALID_STATION))
f20217d9 2208 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3fd07a1e
TW		 2209
2210 if (priv->mac80211_registered &&
2211 (iwl_queue_space(&txq->q) > txq->q.low_mark))
f20217d9 2212 ieee80211_wake_queue(priv->hw, txq_id);
f20217d9 2213 }
f20217d9 2214
ed7fafec 2215 if (qc && likely(sta_id != IWL_INVALID_STATION))
3fd07a1e
TW		 2216 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
2217
f20217d9
TW		 2218 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
2219 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
2220}
2221
caab8f1a
TW		 2222static int iwl4965_calc_rssi(struct iwl_priv *priv,
2223 struct iwl_rx_phy_res *rx_resp)
2224{
2225 /* data from PHY/DSP regarding signal strength, etc.,
2226 * contents are always there, not configurable by host. */
2227 struct iwl4965_rx_non_cfg_phy *ncphy =
2228 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
2229 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK)
2230 >> IWL49_AGC_DB_POS;
2231
2232 u32 valid_antennae =
2233 (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK)
2234 >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
2235 u8 max_rssi = 0;
2236 u32 i;
2237
2238 /* Find max rssi among 3 possible receivers.
2239 * These values are measured by the digital signal processor (DSP).
2240 * They should stay fairly constant even as the signal strength varies,
2241 * if the radio's automatic gain control (AGC) is working right.
2242 * AGC value (see below) will provide the "interesting" info. */
2243 for (i = 0; i < 3; i++)
2244 if (valid_antennae & (1 << i))
2245 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2246
2247 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2248 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2249 max_rssi, agc);
2250
2251 /* dBm = max_rssi dB - agc dB - constant.
2252 * Higher AGC (higher radio gain) means lower signal. */
2253 return max_rssi - agc - IWL_RSSI_OFFSET;
2254}
2255
f20217d9 2256
b481de9c 2257/* Set up 4965-specific Rx frame reply handlers */
d4789efe 2258static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 2259{
2260 /* Legacy Rx frames */
1781a07f 2261 priv->rx_handlers[REPLY_RX] = iwl_rx_reply_rx;
37a44211 2262 /* Tx response */
f20217d9 2263 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
b481de9c
ZY		 2264}
2265
4e39317d 2266static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2267{
2268 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
b481de9c
ZY		 2269}
2270
4e39317d 2271static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2272{
4e39317d 2273 cancel_work_sync(&priv->txpower_work);
b481de9c
ZY		 2274}
2275
3c424c28
TW		 2276
2277static struct iwl_hcmd_ops iwl4965_hcmd = {
7e8c519e 2278 .rxon_assoc = iwl4965_send_rxon_assoc,
3c424c28
TW		 2279};
2280
857485c0 2281static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
c1adf9fb 2282 .get_hcmd_size = iwl4965_get_hcmd_size,
133636de 2283 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
f0832f13
EG		 2284 .chain_noise_reset = iwl4965_chain_noise_reset,
2285 .gain_computation = iwl4965_gain_computation,
a326a5d0 2286 .rts_tx_cmd_flag = iwl4965_rts_tx_cmd_flag,
caab8f1a 2287 .calc_rssi = iwl4965_calc_rssi,
857485c0
TW		 2288};
2289
6bc913bd 2290static struct iwl_lib_ops iwl4965_lib = {
5425e490 2291 .set_hw_params = iwl4965_hw_set_hw_params,
e2a722eb 2292 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
da1bc453 2293 .txq_set_sched = iwl4965_txq_set_sched,
30e553e3
TW		 2294 .txq_agg_enable = iwl4965_txq_agg_enable,
2295 .txq_agg_disable = iwl4965_txq_agg_disable,
d4789efe 2296 .rx_handler_setup = iwl4965_rx_handler_setup,
4e39317d
EG		 2297 .setup_deferred_work = iwl4965_setup_deferred_work,
2298 .cancel_deferred_work = iwl4965_cancel_deferred_work,
57aab75a
TW		 2299 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
2300 .alive_notify = iwl4965_alive_notify,
f3ccc08c 2301 .init_alive_start = iwl4965_init_alive_start,
57aab75a 2302 .load_ucode = iwl4965_load_bsm,
6f4083aa 2303 .apm_ops = {
91238714 2304 .init = iwl4965_apm_init,
7f066108 2305 .reset = iwl4965_apm_reset,
f118a91d 2306 .stop = iwl4965_apm_stop,
694cc56d 2307 .config = iwl4965_nic_config,
5b9f8cd3 2308 .set_pwr_src = iwl_set_pwr_src,
6f4083aa 2309 },
6bc913bd 2310 .eeprom_ops = {
073d3f5f
TW		 2311 .regulatory_bands = {
2312 EEPROM_REGULATORY_BAND_1_CHANNELS,
2313 EEPROM_REGULATORY_BAND_2_CHANNELS,
2314 EEPROM_REGULATORY_BAND_3_CHANNELS,
2315 EEPROM_REGULATORY_BAND_4_CHANNELS,
2316 EEPROM_REGULATORY_BAND_5_CHANNELS,
2317 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
2318 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
2319 },
6bc913bd
AK		 2320 .verify_signature = iwlcore_eeprom_verify_signature,
2321 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
2322 .release_semaphore = iwlcore_eeprom_release_semaphore,
0ef2ca67 2323 .calib_version = iwl4965_eeprom_calib_version,
073d3f5f 2324 .query_addr = iwlcore_eeprom_query_addr,
6bc913bd 2325 },
630fe9b6 2326 .send_tx_power = iwl4965_send_tx_power,
5b9f8cd3 2327 .update_chain_flags = iwl_update_chain_flags,
8f91aecb 2328 .temperature = iwl4965_temperature_calib,
6bc913bd
AK		 2329};
2330
2331static struct iwl_ops iwl4965_ops = {
2332 .lib = &iwl4965_lib,
3c424c28 2333 .hcmd = &iwl4965_hcmd,
857485c0 2334 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 2335};
2336
fed9017e 2337struct iwl_cfg iwl4965_agn_cfg = {
82b9a121 2338 .name = "4965AGN",
25e35a56 2339 .fw_name = IWL4965_MODULE_FIRMWARE,
82b9a121 2340 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
073d3f5f 2341 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
0ef2ca67
TW		 2342 .eeprom_ver = EEPROM_4965_EEPROM_VERSION,
2343 .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION,
6bc913bd 2344 .ops = &iwl4965_ops,
1ea87396 2345 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 2346};
2347
d16dc48a 2348/* Module firmware */
25e35a56 2349MODULE_FIRMWARE(IWL4965_MODULE_FIRMWARE);
d16dc48a 2350
1ea87396
AK		 2351module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
2352MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
2353module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
2354MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
fcc76c6b 2355module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
61a2d07d 2356MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
1ea87396
AK		 2357module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
2358MODULE_PARM_DESC(debug, "debug output mask");
2359module_param_named(
2360 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
2361MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
2362
2363module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
2364MODULE_PARM_DESC(queues_num, "number of hw queues.");
1ea87396
AK		 2365/* QoS */
2366module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
2367MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
49779293
RR		 2368/* 11n */
2369module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, 0444);
2370MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
1ea87396
AK		 2371module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
2372MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
49779293 2373
3a1081e8
EK		 2374module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
2375MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");
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