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iwl3945: add debugfs support
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
82b9a121 41#include "iwl-3945-core.h"
b481de9c 42#include "iwl-3945.h"
5d08cd1d 43#include "iwl-helpers.h"
b481de9c
ZY		 44#include "iwl-3945-rs.h"
45
46#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
47 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
48 IWL_RATE_##r##M_IEEE, \
49 IWL_RATE_##ip##M_INDEX, \
50 IWL_RATE_##in##M_INDEX, \
51 IWL_RATE_##rp##M_INDEX, \
52 IWL_RATE_##rn##M_INDEX, \
53 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 54 IWL_RATE_##np##M_INDEX, \
55 IWL_RATE_##r##M_INDEX_TABLE, \
56 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 57
58/*
59 * Parameter order:
60 * rate, prev rate, next rate, prev tgg rate, next tgg rate
61 *
62 * If there isn't a valid next or previous rate then INV is used which
63 * maps to IWL_RATE_INVALID
64 *
65 */
bb8c093b 66const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = {
14577f23
MA		 67 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
68 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
69 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
70 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 71 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
72 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
73 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
74 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
75 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
76 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
77 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
78 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 79};
80
bb8c093b 81/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 82#define IWL_EVT_DISABLE (0)
83#define IWL_EVT_DISABLE_SIZE (1532/32)
84
85/**
bb8c093b 86 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 87 *
88 * Disable an event by writing "1"s into "disable"
89 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
90 * Default values of 0 enable uCode events to be logged.
91 * Use for only special debugging. This function is just a placeholder as-is,
92 * you'll need to provide the special bits! ...
93 * ... and set IWL_EVT_DISABLE to 1. */
bb8c093b 94void iwl3945_disable_events(struct iwl3945_priv *priv)
b481de9c 95{
af7cca2a 96 int ret;
b481de9c
ZY		 97 int i;
98 u32 base; /* SRAM address of event log header */
99 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
100 u32 array_size; /* # of u32 entries in array */
101 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
102 0x00000000, /* 31 - 0 Event id numbers */
103 0x00000000, /* 63 - 32 */
104 0x00000000, /* 95 - 64 */
105 0x00000000, /* 127 - 96 */
106 0x00000000, /* 159 - 128 */
107 0x00000000, /* 191 - 160 */
108 0x00000000, /* 223 - 192 */
109 0x00000000, /* 255 - 224 */
110 0x00000000, /* 287 - 256 */
111 0x00000000, /* 319 - 288 */
112 0x00000000, /* 351 - 320 */
113 0x00000000, /* 383 - 352 */
114 0x00000000, /* 415 - 384 */
115 0x00000000, /* 447 - 416 */
116 0x00000000, /* 479 - 448 */
117 0x00000000, /* 511 - 480 */
118 0x00000000, /* 543 - 512 */
119 0x00000000, /* 575 - 544 */
120 0x00000000, /* 607 - 576 */
121 0x00000000, /* 639 - 608 */
122 0x00000000, /* 671 - 640 */
123 0x00000000, /* 703 - 672 */
124 0x00000000, /* 735 - 704 */
125 0x00000000, /* 767 - 736 */
126 0x00000000, /* 799 - 768 */
127 0x00000000, /* 831 - 800 */
128 0x00000000, /* 863 - 832 */
129 0x00000000, /* 895 - 864 */
130 0x00000000, /* 927 - 896 */
131 0x00000000, /* 959 - 928 */
132 0x00000000, /* 991 - 960 */
133 0x00000000, /* 1023 - 992 */
134 0x00000000, /* 1055 - 1024 */
135 0x00000000, /* 1087 - 1056 */
136 0x00000000, /* 1119 - 1088 */
137 0x00000000, /* 1151 - 1120 */
138 0x00000000, /* 1183 - 1152 */
139 0x00000000, /* 1215 - 1184 */
140 0x00000000, /* 1247 - 1216 */
141 0x00000000, /* 1279 - 1248 */
142 0x00000000, /* 1311 - 1280 */
143 0x00000000, /* 1343 - 1312 */
144 0x00000000, /* 1375 - 1344 */
145 0x00000000, /* 1407 - 1376 */
146 0x00000000, /* 1439 - 1408 */
147 0x00000000, /* 1471 - 1440 */
148 0x00000000, /* 1503 - 1472 */
149 };
150
151 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 152 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 153 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
154 return;
155 }
156
bb8c093b 157 ret = iwl3945_grab_nic_access(priv);
af7cca2a 158 if (ret) {
b481de9c
ZY		 159 IWL_WARNING("Can not read from adapter at this time.\n");
160 return;
161 }
162
bb8c093b
CH		 163 disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32)));
164 array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32)));
165 iwl3945_release_nic_access(priv);
b481de9c
ZY		 166
167 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
168 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
169 disable_ptr);
bb8c093b 170 ret = iwl3945_grab_nic_access(priv);
b481de9c 171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
bb8c093b 172 iwl3945_write_targ_mem(priv,
af7cca2a
TW		 173 disable_ptr + (i * sizeof(u32)),
174 evt_disable[i]);
b481de9c 175
bb8c093b 176 iwl3945_release_nic_access(priv);
b481de9c
ZY		 177 } else {
178 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
179 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
180 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
181 disable_ptr, array_size);
182 }
183
184}
185
17744ff6
TW		 186static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
187{
188 int idx;
189
190 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
191 if (iwl3945_rates[idx].plcp == plcp)
192 return idx;
193 return -1;
194}
195
b481de9c
ZY		 196/**
197 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
198 * @priv: eeprom and antenna fields are used to determine antenna flags
199 *
200 * priv->eeprom is used to determine if antenna AUX/MAIN are reversed
201 * priv->antenna specifies the antenna diversity mode:
202 *
a96a27f9 203 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
b481de9c
ZY		 204 * IWL_ANTENNA_MAIN - Force MAIN antenna
205 * IWL_ANTENNA_AUX - Force AUX antenna
206 */
bb8c093b 207__le32 iwl3945_get_antenna_flags(const struct iwl3945_priv *priv)
b481de9c
ZY		 208{
209 switch (priv->antenna) {
210 case IWL_ANTENNA_DIVERSITY:
211 return 0;
212
213 case IWL_ANTENNA_MAIN:
214 if (priv->eeprom.antenna_switch_type)
215 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
216 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
217
218 case IWL_ANTENNA_AUX:
219 if (priv->eeprom.antenna_switch_type)
220 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
221 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
222 }
223
224 /* bad antenna selector value */
225 IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
226 return 0; /* "diversity" is default if error */
227}
228
91c066f2
TW		 229#ifdef CONFIG_IWL3945_DEBUG
230#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
231
232static const char *iwl3945_get_tx_fail_reason(u32 status)
233{
234 switch (status & TX_STATUS_MSK) {
235 case TX_STATUS_SUCCESS:
236 return "SUCCESS";
237 TX_STATUS_ENTRY(SHORT_LIMIT);
238 TX_STATUS_ENTRY(LONG_LIMIT);
239 TX_STATUS_ENTRY(FIFO_UNDERRUN);
240 TX_STATUS_ENTRY(MGMNT_ABORT);
241 TX_STATUS_ENTRY(NEXT_FRAG);
242 TX_STATUS_ENTRY(LIFE_EXPIRE);
243 TX_STATUS_ENTRY(DEST_PS);
244 TX_STATUS_ENTRY(ABORTED);
245 TX_STATUS_ENTRY(BT_RETRY);
246 TX_STATUS_ENTRY(STA_INVALID);
247 TX_STATUS_ENTRY(FRAG_DROPPED);
248 TX_STATUS_ENTRY(TID_DISABLE);
249 TX_STATUS_ENTRY(FRAME_FLUSHED);
250 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
251 TX_STATUS_ENTRY(TX_LOCKED);
252 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
253 }
254
255 return "UNKNOWN";
256}
257#else
258static inline const char *iwl3945_get_tx_fail_reason(u32 status)
259{
260 return "";
261}
262#endif
263
e6a9854b
JB		 264/*
265 * get ieee prev rate from rate scale table.
266 * for A and B mode we need to overright prev
267 * value
268 */
269int iwl3945_rs_next_rate(struct iwl3945_priv *priv, int rate)
270{
271 int next_rate = iwl3945_get_prev_ieee_rate(rate);
272
273 switch (priv->band) {
274 case IEEE80211_BAND_5GHZ:
275 if (rate == IWL_RATE_12M_INDEX)
276 next_rate = IWL_RATE_9M_INDEX;
277 else if (rate == IWL_RATE_6M_INDEX)
278 next_rate = IWL_RATE_6M_INDEX;
279 break;
280/* XXX cannot be invoked in current mac80211 so not a regression
281 case MODE_IEEE80211B:
282 if (rate == IWL_RATE_11M_INDEX_TABLE)
283 next_rate = IWL_RATE_5M_INDEX_TABLE;
284 break;
285 */
286 default:
287 break;
288 }
289
290 return next_rate;
291}
292
91c066f2
TW		 293
294/**
295 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
296 *
297 * When FW advances 'R' index, all entries between old and new 'R' index
298 * need to be reclaimed. As result, some free space forms. If there is
299 * enough free space (> low mark), wake the stack that feeds us.
300 */
301static void iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv,
302 int txq_id, int index)
303{
304 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
305 struct iwl3945_queue *q = &txq->q;
306 struct iwl3945_tx_info *tx_info;
307
308 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
309
310 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
311 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
312
313 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 314 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2
TW		 315 tx_info->skb[0] = NULL;
316 iwl3945_hw_txq_free_tfd(priv, txq);
317 }
318
319 if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
320 (txq_id != IWL_CMD_QUEUE_NUM) &&
321 priv->mac80211_registered)
322 ieee80211_wake_queue(priv->hw, txq_id);
323}
324
325/**
326 * iwl3945_rx_reply_tx - Handle Tx response
327 */
328static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
329 struct iwl3945_rx_mem_buffer *rxb)
330{
331 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
332 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
333 int txq_id = SEQ_TO_QUEUE(sequence);
334 int index = SEQ_TO_INDEX(sequence);
335 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 336 struct ieee80211_tx_info *info;
91c066f2
TW		 337 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
338 u32 status = le32_to_cpu(tx_resp->status);
339 int rate_idx;
e6a9854b 340 int fail, i;
91c066f2
TW		 341
342 if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
343 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
344 "is out of range [0-%d] %d %d\n", txq_id,
345 index, txq->q.n_bd, txq->q.write_ptr,
346 txq->q.read_ptr);
347 return;
348 }
349
e039fa4a 350 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 351 ieee80211_tx_info_clear_status(info);
352
353 /* Fill the MRR chain with some info about on-chip retransmissions */
354 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
355 if (info->band == IEEE80211_BAND_5GHZ)
356 rate_idx -= IWL_FIRST_OFDM_RATE;
357
358 fail = tx_resp->failure_frame;
359 for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
360 int next = iwl3945_rs_next_rate(priv, rate_idx);
361
362 info->status.rates[i].idx = rate_idx;
363
364 /*
365 * Put remaining into the last count as best approximation
366 * of saying exactly what the hardware would have done...
367 */
368 if ((rate_idx == next) || (i == IEEE80211_TX_MAX_RATES - 1)) {
369 info->status.rates[i].count = fail;
370 break;
371 }
372
373 info->status.rates[i].count = priv->retry_rate;
374 fail -= priv->retry_rate;
375 rate_idx = next;
376 if (fail <= 0)
377 break;
378 }
379 info->status.rates[i].count++; /* add final attempt */
91c066f2 380
91c066f2 381 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 382 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
383 IEEE80211_TX_STAT_ACK : 0;
91c066f2
TW		 384
385 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
386 txq_id, iwl3945_get_tx_fail_reason(status), status,
387 tx_resp->rate, tx_resp->failure_frame);
388
91c066f2
TW		 389 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
390 iwl3945_tx_queue_reclaim(priv, txq_id, index);
391
392 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
393 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
394}
395
396
397
b481de9c
ZY		 398/*****************************************************************************
399 *
400 * Intel PRO/Wireless 3945ABG/BG Network Connection
401 *
402 * RX handler implementations
403 *
b481de9c
ZY		 404 *****************************************************************************/
405
bb8c093b 406void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 407{
bb8c093b 408 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 409 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
bb8c093b 410 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 411 le32_to_cpu(pkt->len));
412
413 memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics));
414
ab53d8af
MA		 415 iwl3945_led_background(priv);
416
b481de9c
ZY		 417 priv->last_statistics_time = jiffies;
418}
419
17744ff6
TW		 420/******************************************************************************
421 *
422 * Misc. internal state and helper functions
423 *
424 ******************************************************************************/
425#ifdef CONFIG_IWL3945_DEBUG
426
427/**
428 * iwl3945_report_frame - dump frame to syslog during debug sessions
429 *
430 * You may hack this function to show different aspects of received frames,
431 * including selective frame dumps.
432 * group100 parameter selects whether to show 1 out of 100 good frames.
433 */
434static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
435 struct iwl3945_rx_packet *pkt,
436 struct ieee80211_hdr *header, int group100)
437{
438 u32 to_us;
439 u32 print_summary = 0;
440 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
441 u32 hundred = 0;
442 u32 dataframe = 0;
fd7c8a40 443 __le16 fc;
17744ff6
TW		 444 u16 seq_ctl;
445 u16 channel;
446 u16 phy_flags;
447 u16 length;
448 u16 status;
449 u16 bcn_tmr;
450 u32 tsf_low;
451 u64 tsf;
452 u8 rssi;
453 u8 agc;
454 u16 sig_avg;
455 u16 noise_diff;
456 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
457 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
458 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
459 u8 *data = IWL_RX_DATA(pkt);
460
461 /* MAC header */
fd7c8a40 462 fc = header->frame_control;
17744ff6
TW		 463 seq_ctl = le16_to_cpu(header->seq_ctrl);
464
465 /* metadata */
466 channel = le16_to_cpu(rx_hdr->channel);
467 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
468 length = le16_to_cpu(rx_hdr->len);
469
470 /* end-of-frame status and timestamp */
471 status = le32_to_cpu(rx_end->status);
472 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
473 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
474 tsf = le64_to_cpu(rx_end->timestamp);
475
476 /* signal statistics */
477 rssi = rx_stats->rssi;
478 agc = rx_stats->agc;
479 sig_avg = le16_to_cpu(rx_stats->sig_avg);
480 noise_diff = le16_to_cpu(rx_stats->noise_diff);
481
482 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
483
484 /* if data frame is to us and all is good,
485 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 486 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
487 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 488 dataframe = 1;
489 if (!group100)
490 print_summary = 1; /* print each frame */
491 else if (priv->framecnt_to_us < 100) {
492 priv->framecnt_to_us++;
493 print_summary = 0;
494 } else {
495 priv->framecnt_to_us = 0;
496 print_summary = 1;
497 hundred = 1;
498 }
499 } else {
500 /* print summary for all other frames */
501 print_summary = 1;
502 }
503
504 if (print_summary) {
505 char *title;
0ff1cca0 506 int rate;
17744ff6
TW		 507
508 if (hundred)
509 title = "100Frames";
fd7c8a40 510 else if (ieee80211_has_retry(fc))
17744ff6 511 title = "Retry";
fd7c8a40 512 else if (ieee80211_is_assoc_resp(fc))
17744ff6 513 title = "AscRsp";
fd7c8a40 514 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 515 title = "RasRsp";
fd7c8a40 516 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 517 title = "PrbRsp";
518 print_dump = 1; /* dump frame contents */
519 } else if (ieee80211_is_beacon(fc)) {
520 title = "Beacon";
521 print_dump = 1; /* dump frame contents */
522 } else if (ieee80211_is_atim(fc))
523 title = "ATIM";
524 else if (ieee80211_is_auth(fc))
525 title = "Auth";
526 else if (ieee80211_is_deauth(fc))
527 title = "DeAuth";
528 else if (ieee80211_is_disassoc(fc))
529 title = "DisAssoc";
530 else
531 title = "Frame";
532
533 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
534 if (rate == -1)
535 rate = 0;
536 else
537 rate = iwl3945_rates[rate].ieee / 2;
538
539 /* print frame summary.
540 * MAC addresses show just the last byte (for brevity),
541 * but you can hack it to show more, if you'd like to. */
542 if (dataframe)
543 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 544 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 545 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 546 length, rssi, channel, rate);
547 else {
548 /* src/dst addresses assume managed mode */
549 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
550 "src=0x%02x, rssi=%u, tim=%lu usec, "
551 "phy=0x%02x, chnl=%d\n",
fd7c8a40 552 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 553 header->addr3[5], rssi,
554 tsf_low - priv->scan_start_tsf,
555 phy_flags, channel);
556 }
557 }
558 if (print_dump)
559 iwl3945_print_hex_dump(IWL_DL_RX, data, length);
560}
561#else
562static inline void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
563 struct iwl3945_rx_packet *pkt,
564 struct ieee80211_hdr *header, int group100)
565{
566}
567#endif
568
4bd9b4f3
AG		 569/* This is necessary only for a number of statistics, see the caller. */
570static int iwl3945_is_network_packet(struct iwl3945_priv *priv,
571 struct ieee80211_hdr *header)
572{
573 /* Filter incoming packets to determine if they are targeted toward
574 * this network, discarding packets coming from ourselves */
575 switch (priv->iw_mode) {
05c914fe 576 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 577 /* packets to our IBSS update information */
578 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 579 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 580 /* packets to our IBSS update information */
581 return !compare_ether_addr(header->addr2, priv->bssid);
582 default:
583 return 1;
584 }
585}
17744ff6 586
4bd9b4f3 587static void iwl3945_pass_packet_to_mac80211(struct iwl3945_priv *priv,
bb8c093b 588 struct iwl3945_rx_mem_buffer *rxb,
12342c47 589 struct ieee80211_rx_status *stats)
b481de9c 590{
bb8c093b 591 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
699669f3 592#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 593 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699669f3 594#endif
bb8c093b
CH		 595 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
596 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 597 short len = le16_to_cpu(rx_hdr->len);
598
599 /* We received data from the HW, so stop the watchdog */
600 if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
601 IWL_DEBUG_DROP("Corruption detected!\n");
602 return;
603 }
604
605 /* We only process data packets if the interface is open */
606 if (unlikely(!priv->is_open)) {
607 IWL_DEBUG_DROP_LIMIT
608 ("Dropping packet while interface is not open.\n");
609 return;
610 }
b481de9c
ZY		 611
612 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
613 /* Set the size of the skb to the size of the frame */
614 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
615
bb8c093b
CH		 616 if (iwl3945_param_hwcrypto)
617 iwl3945_set_decrypted_flag(priv, rxb->skb,
b481de9c
ZY		 618 le32_to_cpu(rx_end->status), stats);
619
ab53d8af 620#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 621 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 622 priv->rxtxpackets += len;
623#endif
b481de9c
ZY		 624 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
625 rxb->skb = NULL;
626}
627
7878a5a4
MA		 628#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
629
bb8c093b
CH		 630static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
631 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 632{
17744ff6
TW		 633 struct ieee80211_hdr *header;
634 struct ieee80211_rx_status rx_status;
bb8c093b
CH		 635 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
636 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
637 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
638 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 639 int snr;
b481de9c
ZY		 640 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
641 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 642 u8 network_packet;
17744ff6 643
17744ff6
TW		 644 rx_status.flag = 0;
645 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 646 rx_status.freq =
c0186078 647 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 648 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
649 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
650
651 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 652 if (rx_status.band == IEEE80211_BAND_5GHZ)
653 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 654
6f0a2c4d
BR		 655 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
656 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
657
658 /* set the preamble flag if appropriate */
659 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
660 rx_status.flag |= RX_FLAG_SHORTPRE;
661
b481de9c
ZY		 662 if ((unlikely(rx_stats->phy_count > 20))) {
663 IWL_DEBUG_DROP
664 ("dsp size out of range [0,20]: "
665 "%d/n", rx_stats->phy_count);
666 return;
667 }
668
669 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
670 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
671 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
672 return;
673 }
674
56decd3c 675
b481de9c
ZY		 676
677 /* Convert 3945's rssi indicator to dBm */
566bfe5a 678 rx_status.signal = rx_stats->rssi - IWL_RSSI_OFFSET;
b481de9c
ZY		 679
680 /* Set default noise value to -127 */
681 if (priv->last_rx_noise == 0)
682 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
683
684 /* 3945 provides noise info for OFDM frames only.
685 * sig_avg and noise_diff are measured by the 3945's digital signal
686 * processor (DSP), and indicate linear levels of signal level and
687 * distortion/noise within the packet preamble after
688 * automatic gain control (AGC). sig_avg should stay fairly
689 * constant if the radio's AGC is working well.
690 * Since these values are linear (not dB or dBm), linear
691 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
692 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
693 * to obtain noise level in dBm.
17744ff6 694 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 695 if (rx_stats_noise_diff) {
696 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 697 rx_status.noise = rx_status.signal -
17744ff6 698 iwl3945_calc_db_from_ratio(snr);
566bfe5a 699 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 700 rx_status.noise);
b481de9c
ZY		 701
702 /* If noise info not available, calculate signal quality indicator (%)
703 * using just the dBm signal level. */
704 } else {
17744ff6 705 rx_status.noise = priv->last_rx_noise;
566bfe5a 706 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 707 }
708
709
710 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 711 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 712 rx_stats_sig_avg, rx_stats_noise_diff);
713
b481de9c
ZY		 714 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
715
bb8c093b 716 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 717
17744ff6
TW		 718 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
719 network_packet ? '*' : ' ',
720 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 721 rx_status.signal, rx_status.signal,
722 rx_status.noise, rx_status.rate_idx);
b481de9c 723
17744ff6 724#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 725 if (iwl3945_debug_level & (IWL_DL_RX))
b481de9c 726 /* Set "1" to report good data frames in groups of 100 */
17744ff6 727 iwl3945_dbg_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 728#endif
729
730 if (network_packet) {
731 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
732 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 733 priv->last_rx_rssi = rx_status.signal;
17744ff6 734 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 735 }
736
12e5e22d 737 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 738}
739
bb8c093b 740int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr,
b481de9c
ZY		 741 dma_addr_t addr, u16 len)
742{
743 int count;
744 u32 pad;
bb8c093b 745 struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
b481de9c
ZY		 746
747 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
748 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
749
750 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
751 IWL_ERROR("Error can not send more than %d chunks\n",
752 NUM_TFD_CHUNKS);
753 return -EINVAL;
754 }
755
756 tfd->pa[count].addr = cpu_to_le32(addr);
757 tfd->pa[count].len = cpu_to_le32(len);
758
759 count++;
760
761 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
762 TFD_CTL_PAD_SET(pad));
763
764 return 0;
765}
766
767/**
bb8c093b 768 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 769 *
770 * Does NOT advance any indexes
771 */
bb8c093b 772int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 773{
bb8c093b
CH		 774 struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
775 struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 776 struct pci_dev *dev = priv->pci_dev;
777 int i;
778 int counter;
779
780 /* classify bd */
781 if (txq->q.id == IWL_CMD_QUEUE_NUM)
782 /* nothing to cleanup after for host commands */
783 return 0;
784
785 /* sanity check */
786 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
787 if (counter > NUM_TFD_CHUNKS) {
788 IWL_ERROR("Too many chunks: %i\n", counter);
789 /* @todo issue fatal error, it is quite serious situation */
790 return 0;
791 }
792
793 /* unmap chunks if any */
794
795 for (i = 1; i < counter; i++) {
796 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
797 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 798 if (txq->txb[txq->q.read_ptr].skb[0]) {
799 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
800 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 801 /* Can be called from interrupt context */
802 dev_kfree_skb_any(skb);
fc4b6853 803 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 804 }
805 }
806 }
807 return 0;
808}
809
bb8c093b 810u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
b481de9c 811{
c93007ef 812 int i, start = IWL_AP_ID;
b481de9c
ZY		 813 int ret = IWL_INVALID_STATION;
814 unsigned long flags;
815
c93007ef
SO		 816 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
817 (priv->iw_mode == NL80211_IFTYPE_AP))
818 start = IWL_STA_ID;
819
820 if (is_broadcast_ether_addr(addr))
821 return priv->hw_setting.bcast_sta_id;
822
b481de9c 823 spin_lock_irqsave(&priv->sta_lock, flags);
c93007ef 824 for (i = start; i < priv->hw_setting.max_stations; i++)
b481de9c
ZY		 825 if ((priv->stations[i].used) &&
826 (!compare_ether_addr
827 (priv->stations[i].sta.sta.addr, addr))) {
828 ret = i;
829 goto out;
830 }
831
e174961c
JB		 832 IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
833 addr, priv->num_stations);
b481de9c
ZY		 834 out:
835 spin_unlock_irqrestore(&priv->sta_lock, flags);
836 return ret;
837}
838
839/**
bb8c093b 840 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 841 *
842*/
bb8c093b
CH		 843void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
844 struct iwl3945_cmd *cmd,
e039fa4a 845 struct ieee80211_tx_info *info,
b481de9c
ZY		 846 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
847{
848 unsigned long flags;
e039fa4a 849 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 850 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 851 u16 rate_mask;
852 int rate;
853 u8 rts_retry_limit;
854 u8 data_retry_limit;
855 __le32 tx_flags;
fd7c8a40 856 __le16 fc = hdr->frame_control;
b481de9c 857
bb8c093b 858 rate = iwl3945_rates[rate_index].plcp;
b481de9c
ZY		 859 tx_flags = cmd->cmd.tx.tx_flags;
860
861 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 862 * in this running context */
b481de9c
ZY		 863 rate_mask = IWL_RATES_MASK;
864
865 spin_lock_irqsave(&priv->sta_lock, flags);
866
867 priv->stations[sta_id].current_rate.rate_n_flags = rate;
868
05c914fe 869 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
a4062b8f 870 (sta_id != priv->hw_setting.bcast_sta_id) &&
b481de9c
ZY		 871 (sta_id != IWL_MULTICAST_ID))
872 priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
873
874 spin_unlock_irqrestore(&priv->sta_lock, flags);
875
876 if (tx_id >= IWL_CMD_QUEUE_NUM)
877 rts_retry_limit = 3;
878 else
879 rts_retry_limit = 7;
880
fd7c8a40 881 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 882 data_retry_limit = 3;
883 if (data_retry_limit < rts_retry_limit)
884 rts_retry_limit = data_retry_limit;
885 } else
886 data_retry_limit = IWL_DEFAULT_TX_RETRY;
887
888 if (priv->data_retry_limit != -1)
889 data_retry_limit = priv->data_retry_limit;
890
fd7c8a40
HH		 891 if (ieee80211_is_mgmt(fc)) {
892 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
893 case cpu_to_le16(IEEE80211_STYPE_AUTH):
894 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
895 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
896 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 897 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
898 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
899 tx_flags |= TX_CMD_FLG_CTS_MSK;
900 }
901 break;
902 default:
903 break;
904 }
905 }
906
907 cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
908 cmd->cmd.tx.data_retry_limit = data_retry_limit;
909 cmd->cmd.tx.rate = rate;
910 cmd->cmd.tx.tx_flags = tx_flags;
911
912 /* OFDM */
14577f23
MA		 913 cmd->cmd.tx.supp_rates[0] =
914 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 915
916 /* CCK */
14577f23 917 cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 918
919 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
920 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
921 cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
922 cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
923}
924
bb8c093b 925u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 926{
927 unsigned long flags_spin;
bb8c093b 928 struct iwl3945_station_entry *station;
b481de9c
ZY		 929
930 if (sta_id == IWL_INVALID_STATION)
931 return IWL_INVALID_STATION;
932
933 spin_lock_irqsave(&priv->sta_lock, flags_spin);
934 station = &priv->stations[sta_id];
935
936 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
937 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
938 station->current_rate.rate_n_flags = tx_rate;
939 station->sta.mode = STA_CONTROL_MODIFY_MSK;
940
941 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
942
bb8c093b 943 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 944 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
945 sta_id, tx_rate);
946 return sta_id;
947}
948
bb8c093b 949static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max)
b481de9c
ZY		 950{
951 int rc;
952 unsigned long flags;
953
954 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 955 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 956 if (rc) {
957 spin_unlock_irqrestore(&priv->lock, flags);
958 return rc;
959 }
960
961 if (!pwr_max) {
962 u32 val;
963
964 rc = pci_read_config_dword(priv->pci_dev,
965 PCI_POWER_SOURCE, &val);
966 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
bb8c093b 967 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 968 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
969 ~APMG_PS_CTRL_MSK_PWR_SRC);
bb8c093b 970 iwl3945_release_nic_access(priv);
b481de9c 971
bb8c093b 972 iwl3945_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 973 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
974 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
975 } else
bb8c093b 976 iwl3945_release_nic_access(priv);
b481de9c 977 } else {
bb8c093b 978 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 979 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
980 ~APMG_PS_CTRL_MSK_PWR_SRC);
981
bb8c093b
CH		 982 iwl3945_release_nic_access(priv);
983 iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 984 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
985 }
986 spin_unlock_irqrestore(&priv->lock, flags);
987
988 return rc;
989}
990
bb8c093b 991static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 992{
993 int rc;
994 unsigned long flags;
995
996 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 997 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 998 if (rc) {
999 spin_unlock_irqrestore(&priv->lock, flags);
1000 return rc;
1001 }
1002
bb8c093b
CH		 1003 iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
1004 iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
b481de9c 1005 priv->hw_setting.shared_phys +
bb8c093b
CH		 1006 offsetof(struct iwl3945_shared, rx_read_ptr[0]));
1007 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0);
1008 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0),
b481de9c
ZY		 1009 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
1010 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
1011 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
1012 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
1013 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
1014 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
1015 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
1016 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
1017
1018 /* fake read to flush all prev I/O */
bb8c093b 1019 iwl3945_read_direct32(priv, FH_RSSR_CTRL);
b481de9c 1020
bb8c093b 1021 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1022 spin_unlock_irqrestore(&priv->lock, flags);
1023
1024 return 0;
1025}
1026
bb8c093b 1027static int iwl3945_tx_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 1028{
1029 int rc;
1030 unsigned long flags;
1031
1032 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1033 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1034 if (rc) {
1035 spin_unlock_irqrestore(&priv->lock, flags);
1036 return rc;
1037 }
1038
1039 /* bypass mode */
bb8c093b 1040 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 1041
1042 /* RA 0 is active */
bb8c093b 1043 iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 1044
1045 /* all 6 fifo are active */
bb8c093b 1046 iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 1047
bb8c093b
CH		 1048 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1049 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1050 iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1051 iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 1052
bb8c093b 1053 iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE,
b481de9c
ZY		 1054 priv->hw_setting.shared_phys);
1055
bb8c093b 1056 iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG,
b481de9c
ZY		 1057 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1058 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1059 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1060 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1061 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1062 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1063 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1064
bb8c093b 1065 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1066 spin_unlock_irqrestore(&priv->lock, flags);
1067
1068 return 0;
1069}
1070
1071/**
1072 * iwl3945_txq_ctx_reset - Reset TX queue context
1073 *
1074 * Destroys all DMA structures and initialize them again
1075 */
bb8c093b 1076static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 1077{
1078 int rc;
1079 int txq_id, slots_num;
1080
bb8c093b 1081 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1082
1083 /* Tx CMD queue */
1084 rc = iwl3945_tx_reset(priv);
1085 if (rc)
1086 goto error;
1087
1088 /* Tx queue(s) */
1089 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1090 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1091 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 1092 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 1093 txq_id);
1094 if (rc) {
1095 IWL_ERROR("Tx %d queue init failed\n", txq_id);
1096 goto error;
1097 }
1098 }
1099
1100 return rc;
1101
1102 error:
bb8c093b 1103 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1104 return rc;
1105}
1106
bb8c093b 1107int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
b481de9c
ZY		 1108{
1109 u8 rev_id;
1110 int rc;
1111 unsigned long flags;
bb8c093b 1112 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 1113
bb8c093b 1114 iwl3945_power_init_handle(priv);
b481de9c
ZY		 1115
1116 spin_lock_irqsave(&priv->lock, flags);
a693f187 1117 iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
bb8c093b 1118 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
b481de9c
ZY		 1119 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1120
bb8c093b
CH		 1121 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1122 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1123 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1124 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1125 if (rc < 0) {
1126 spin_unlock_irqrestore(&priv->lock, flags);
1127 IWL_DEBUG_INFO("Failed to init the card\n");
1128 return rc;
1129 }
1130
bb8c093b 1131 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1132 if (rc) {
1133 spin_unlock_irqrestore(&priv->lock, flags);
1134 return rc;
1135 }
bb8c093b 1136 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1137 APMG_CLK_VAL_DMA_CLK_RQT |
1138 APMG_CLK_VAL_BSM_CLK_RQT);
1139 udelay(20);
bb8c093b 1140 iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
b481de9c 1141 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
bb8c093b 1142 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1143 spin_unlock_irqrestore(&priv->lock, flags);
1144
1145 /* Determine HW type */
1146 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1147 if (rc)
1148 return rc;
1149 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1150
1151 iwl3945_nic_set_pwr_src(priv, 1);
1152 spin_lock_irqsave(&priv->lock, flags);
1153
1154 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1155 IWL_DEBUG_INFO("RTP type \n");
1156 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
6f83eaa1 1157 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
bb8c093b 1158 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1159 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1160 } else {
6f83eaa1 1161 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
bb8c093b 1162 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1163 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1164 }
1165
b481de9c
ZY		 1166 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
1167 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
bb8c093b 1168 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1169 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c
ZY		 1170 } else
1171 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1172
1173 if ((priv->eeprom.board_revision & 0xF0) == 0xD0) {
1174 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1175 priv->eeprom.board_revision);
bb8c093b 1176 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1177 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1178 } else {
1179 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1180 priv->eeprom.board_revision);
bb8c093b 1181 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1182 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1183 }
1184
1185 if (priv->eeprom.almgor_m_version <= 1) {
bb8c093b 1186 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1187 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
b481de9c
ZY		 1188 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1189 priv->eeprom.almgor_m_version);
1190 } else {
1191 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1192 priv->eeprom.almgor_m_version);
bb8c093b 1193 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1194 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1195 }
1196 spin_unlock_irqrestore(&priv->lock, flags);
1197
1198 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1199 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1200
1201 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1202 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1203
1204 /* Allocate the RX queue, or reset if it is already allocated */
1205 if (!rxq->bd) {
bb8c093b 1206 rc = iwl3945_rx_queue_alloc(priv);
b481de9c
ZY		 1207 if (rc) {
1208 IWL_ERROR("Unable to initialize Rx queue\n");
1209 return -ENOMEM;
1210 }
1211 } else
bb8c093b 1212 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1213
bb8c093b 1214 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1215
1216 iwl3945_rx_init(priv, rxq);
1217
1218 spin_lock_irqsave(&priv->lock, flags);
1219
1220 /* Look at using this instead:
1221 rxq->need_update = 1;
bb8c093b 1222 iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1223 */
1224
bb8c093b 1225 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1226 if (rc) {
1227 spin_unlock_irqrestore(&priv->lock, flags);
1228 return rc;
1229 }
bb8c093b
CH		 1230 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
1231 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1232
1233 spin_unlock_irqrestore(&priv->lock, flags);
1234
1235 rc = iwl3945_txq_ctx_reset(priv);
1236 if (rc)
1237 return rc;
1238
1239 set_bit(STATUS_INIT, &priv->status);
1240
1241 return 0;
1242}
1243
1244/**
bb8c093b 1245 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1246 *
1247 * Destroy all TX DMA queues and structures
1248 */
bb8c093b 1249void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
b481de9c
ZY		 1250{
1251 int txq_id;
1252
1253 /* Tx queues */
1254 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
bb8c093b 1255 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c
ZY		 1256}
1257
bb8c093b 1258void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
b481de9c
ZY		 1259{
1260 int queue;
1261 unsigned long flags;
1262
1263 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1264 if (iwl3945_grab_nic_access(priv)) {
b481de9c 1265 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 1266 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1267 return;
1268 }
1269
1270 /* stop SCD */
bb8c093b 1271 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1272
1273 /* reset TFD queues */
1274 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
bb8c093b
CH		 1275 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
1276 iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
b481de9c
ZY		 1277 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1278 1000);
1279 }
1280
bb8c093b 1281 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1282 spin_unlock_irqrestore(&priv->lock, flags);
1283
bb8c093b 1284 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1285}
1286
bb8c093b 1287int iwl3945_hw_nic_stop_master(struct iwl3945_priv *priv)
b481de9c
ZY		 1288{
1289 int rc = 0;
1290 u32 reg_val;
1291 unsigned long flags;
1292
1293 spin_lock_irqsave(&priv->lock, flags);
1294
1295 /* set stop master bit */
bb8c093b 1296 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1297
bb8c093b 1298 reg_val = iwl3945_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 1299
1300 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1301 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1302 IWL_DEBUG_INFO("Card in power save, master is already "
1303 "stopped\n");
1304 else {
bb8c093b 1305 rc = iwl3945_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 1306 CSR_RESET_REG_FLAG_MASTER_DISABLED,
1307 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1308 if (rc < 0) {
1309 spin_unlock_irqrestore(&priv->lock, flags);
1310 return rc;
1311 }
1312 }
1313
1314 spin_unlock_irqrestore(&priv->lock, flags);
1315 IWL_DEBUG_INFO("stop master\n");
1316
1317 return rc;
1318}
1319
bb8c093b 1320int iwl3945_hw_nic_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 1321{
1322 int rc;
1323 unsigned long flags;
1324
bb8c093b 1325 iwl3945_hw_nic_stop_master(priv);
b481de9c
ZY		 1326
1327 spin_lock_irqsave(&priv->lock, flags);
1328
bb8c093b 1329 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c 1330
bb8c093b 1331 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1332 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1333 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1334
bb8c093b 1335 rc = iwl3945_grab_nic_access(priv);
b481de9c 1336 if (!rc) {
bb8c093b 1337 iwl3945_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1338 APMG_CLK_VAL_BSM_CLK_RQT);
1339
1340 udelay(10);
1341
bb8c093b 1342 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1343 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1344
bb8c093b
CH		 1345 iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1346 iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1347 0xFFFFFFFF);
1348
1349 /* enable DMA */
bb8c093b 1350 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1351 APMG_CLK_VAL_DMA_CLK_RQT |
1352 APMG_CLK_VAL_BSM_CLK_RQT);
1353 udelay(10);
1354
bb8c093b 1355 iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1356 APMG_PS_CTRL_VAL_RESET_REQ);
1357 udelay(5);
bb8c093b 1358 iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1359 APMG_PS_CTRL_VAL_RESET_REQ);
bb8c093b 1360 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1361 }
1362
1363 /* Clear the 'host command active' bit... */
1364 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1365
1366 wake_up_interruptible(&priv->wait_command_queue);
1367 spin_unlock_irqrestore(&priv->lock, flags);
1368
1369 return rc;
1370}
1371
1372/**
bb8c093b 1373 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1374 * return index delta into power gain settings table
1375*/
bb8c093b 1376static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1377{
1378 return (new_reading - old_reading) * (-11) / 100;
1379}
1380
1381/**
bb8c093b 1382 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1383 */
bb8c093b 1384static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1385{
3ac7f146 1386 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1387}
1388
bb8c093b 1389int iwl3945_hw_get_temperature(struct iwl3945_priv *priv)
b481de9c 1390{
bb8c093b 1391 return iwl3945_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1392}
1393
1394/**
bb8c093b 1395 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1396 * get the current temperature by reading from NIC
1397*/
bb8c093b 1398static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv)
b481de9c
ZY		 1399{
1400 int temperature;
1401
bb8c093b 1402 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1403
1404 /* driver's okay range is -260 to +25.
1405 * human readable okay range is 0 to +285 */
1406 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1407
1408 /* handle insane temp reading */
bb8c093b 1409 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
b481de9c
ZY		 1410 IWL_ERROR("Error bad temperature value %d\n", temperature);
1411
1412 /* if really really hot(?),
1413 * substitute the 3rd band/group's temp measured at factory */
1414 if (priv->last_temperature > 100)
1415 temperature = priv->eeprom.groups[2].temperature;
1416 else /* else use most recent "sane" value from driver */
1417 temperature = priv->last_temperature;
1418 }
1419
1420 return temperature; /* raw, not "human readable" */
1421}
1422
1423/* Adjust Txpower only if temperature variance is greater than threshold.
1424 *
1425 * Both are lower than older versions' 9 degrees */
1426#define IWL_TEMPERATURE_LIMIT_TIMER 6
1427
1428/**
1429 * is_temp_calib_needed - determines if new calibration is needed
1430 *
1431 * records new temperature in tx_mgr->temperature.
1432 * replaces tx_mgr->last_temperature *only* if calib needed
1433 * (assumes caller will actually do the calibration!). */
bb8c093b 1434static int is_temp_calib_needed(struct iwl3945_priv *priv)
b481de9c
ZY		 1435{
1436 int temp_diff;
1437
bb8c093b 1438 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1439 temp_diff = priv->temperature - priv->last_temperature;
1440
1441 /* get absolute value */
1442 if (temp_diff < 0) {
1443 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1444 temp_diff = -temp_diff;
1445 } else if (temp_diff == 0)
1446 IWL_DEBUG_POWER("Same temp,\n");
1447 else
1448 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1449
1450 /* if we don't need calibration, *don't* update last_temperature */
1451 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1452 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1453 return 0;
1454 }
1455
1456 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1457
1458 /* assume that caller will actually do calib ...
1459 * update the "last temperature" value */
1460 priv->last_temperature = priv->temperature;
1461 return 1;
1462}
1463
1464#define IWL_MAX_GAIN_ENTRIES 78
1465#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1466#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1467
1468/* radio and DSP power table, each step is 1/2 dB.
1469 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1470static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1471 {
1472 {251, 127}, /* 2.4 GHz, highest power */
1473 {251, 127},
1474 {251, 127},
1475 {251, 127},
1476 {251, 125},
1477 {251, 110},
1478 {251, 105},
1479 {251, 98},
1480 {187, 125},
1481 {187, 115},
1482 {187, 108},
1483 {187, 99},
1484 {243, 119},
1485 {243, 111},
1486 {243, 105},
1487 {243, 97},
1488 {243, 92},
1489 {211, 106},
1490 {211, 100},
1491 {179, 120},
1492 {179, 113},
1493 {179, 107},
1494 {147, 125},
1495 {147, 119},
1496 {147, 112},
1497 {147, 106},
1498 {147, 101},
1499 {147, 97},
1500 {147, 91},
1501 {115, 107},
1502 {235, 121},
1503 {235, 115},
1504 {235, 109},
1505 {203, 127},
1506 {203, 121},
1507 {203, 115},
1508 {203, 108},
1509 {203, 102},
1510 {203, 96},
1511 {203, 92},
1512 {171, 110},
1513 {171, 104},
1514 {171, 98},
1515 {139, 116},
1516 {227, 125},
1517 {227, 119},
1518 {227, 113},
1519 {227, 107},
1520 {227, 101},
1521 {227, 96},
1522 {195, 113},
1523 {195, 106},
1524 {195, 102},
1525 {195, 95},
1526 {163, 113},
1527 {163, 106},
1528 {163, 102},
1529 {163, 95},
1530 {131, 113},
1531 {131, 106},
1532 {131, 102},
1533 {131, 95},
1534 {99, 113},
1535 {99, 106},
1536 {99, 102},
1537 {99, 95},
1538 {67, 113},
1539 {67, 106},
1540 {67, 102},
1541 {67, 95},
1542 {35, 113},
1543 {35, 106},
1544 {35, 102},
1545 {35, 95},
1546 {3, 113},
1547 {3, 106},
1548 {3, 102},
1549 {3, 95} }, /* 2.4 GHz, lowest power */
1550 {
1551 {251, 127}, /* 5.x GHz, highest power */
1552 {251, 120},
1553 {251, 114},
1554 {219, 119},
1555 {219, 101},
1556 {187, 113},
1557 {187, 102},
1558 {155, 114},
1559 {155, 103},
1560 {123, 117},
1561 {123, 107},
1562 {123, 99},
1563 {123, 92},
1564 {91, 108},
1565 {59, 125},
1566 {59, 118},
1567 {59, 109},
1568 {59, 102},
1569 {59, 96},
1570 {59, 90},
1571 {27, 104},
1572 {27, 98},
1573 {27, 92},
1574 {115, 118},
1575 {115, 111},
1576 {115, 104},
1577 {83, 126},
1578 {83, 121},
1579 {83, 113},
1580 {83, 105},
1581 {83, 99},
1582 {51, 118},
1583 {51, 111},
1584 {51, 104},
1585 {51, 98},
1586 {19, 116},
1587 {19, 109},
1588 {19, 102},
1589 {19, 98},
1590 {19, 93},
1591 {171, 113},
1592 {171, 107},
1593 {171, 99},
1594 {139, 120},
1595 {139, 113},
1596 {139, 107},
1597 {139, 99},
1598 {107, 120},
1599 {107, 113},
1600 {107, 107},
1601 {107, 99},
1602 {75, 120},
1603 {75, 113},
1604 {75, 107},
1605 {75, 99},
1606 {43, 120},
1607 {43, 113},
1608 {43, 107},
1609 {43, 99},
1610 {11, 120},
1611 {11, 113},
1612 {11, 107},
1613 {11, 99},
1614 {131, 107},
1615 {131, 99},
1616 {99, 120},
1617 {99, 113},
1618 {99, 107},
1619 {99, 99},
1620 {67, 120},
1621 {67, 113},
1622 {67, 107},
1623 {67, 99},
1624 {35, 120},
1625 {35, 113},
1626 {35, 107},
1627 {35, 99},
1628 {3, 120} } /* 5.x GHz, lowest power */
1629};
1630
bb8c093b 1631static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1632{
1633 if (index < 0)
1634 return 0;
1635 if (index >= IWL_MAX_GAIN_ENTRIES)
1636 return IWL_MAX_GAIN_ENTRIES - 1;
1637 return (u8) index;
1638}
1639
1640/* Kick off thermal recalibration check every 60 seconds */
1641#define REG_RECALIB_PERIOD (60)
1642
1643/**
bb8c093b 1644 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1645 *
1646 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1647 * or 6 Mbit (OFDM) rates.
1648 */
bb8c093b 1649static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tbl_index,
b481de9c 1650 s32 rate_index, const s8 *clip_pwrs,
bb8c093b 1651 struct iwl3945_channel_info *ch_info,
b481de9c
ZY		 1652 int band_index)
1653{
bb8c093b 1654 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1655 s8 power;
1656 u8 power_index;
1657
1658 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1659
1660 /* use this channel group's 6Mbit clipping/saturation pwr,
1661 * but cap at regulatory scan power restriction (set during init
1662 * based on eeprom channel data) for this channel. */
14577f23 1663 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1664
1665 /* further limit to user's max power preference.
1666 * FIXME: Other spectrum management power limitations do not
1667 * seem to apply?? */
1668 power = min(power, priv->user_txpower_limit);
1669 scan_power_info->requested_power = power;
1670
1671 /* find difference between new scan *power* and current "normal"
1672 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1673 * current "normal" temperature-compensated Tx power *index* for
1674 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1675 * *index*. */
1676 power_index = ch_info->power_info[rate_index].power_table_index
1677 - (power - ch_info->power_info
14577f23 1678 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1679
1680 /* store reference index that we use when adjusting *all* scan
1681 * powers. So we can accommodate user (all channel) or spectrum
1682 * management (single channel) power changes "between" temperature
1683 * feedback compensation procedures.
1684 * don't force fit this reference index into gain table; it may be a
1685 * negative number. This will help avoid errors when we're at
1686 * the lower bounds (highest gains, for warmest temperatures)
1687 * of the table. */
1688
1689 /* don't exceed table bounds for "real" setting */
bb8c093b 1690 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1691
1692 scan_power_info->power_table_index = power_index;
1693 scan_power_info->tpc.tx_gain =
1694 power_gain_table[band_index][power_index].tx_gain;
1695 scan_power_info->tpc.dsp_atten =
1696 power_gain_table[band_index][power_index].dsp_atten;
1697}
1698
1699/**
bb8c093b 1700 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
b481de9c
ZY		 1701 *
1702 * Configures power settings for all rates for the current channel,
1703 * using values from channel info struct, and send to NIC
1704 */
bb8c093b 1705int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
b481de9c 1706{
14577f23 1707 int rate_idx, i;
bb8c093b
CH		 1708 const struct iwl3945_channel_info *ch_info = NULL;
1709 struct iwl3945_txpowertable_cmd txpower = {
b481de9c
ZY		 1710 .channel = priv->active_rxon.channel,
1711 };
1712
8318d78a 1713 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
bb8c093b 1714 ch_info = iwl3945_get_channel_info(priv,
8318d78a 1715 priv->band,
b481de9c
ZY		 1716 le16_to_cpu(priv->active_rxon.channel));
1717 if (!ch_info) {
1718 IWL_ERROR
1719 ("Failed to get channel info for channel %d [%d]\n",
8318d78a 1720 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1721 return -EINVAL;
1722 }
1723
1724 if (!is_channel_valid(ch_info)) {
1725 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1726 "non-Tx channel.\n");
1727 return 0;
1728 }
1729
1730 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1731 /* Fill OFDM rate */
1732 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1733 rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) {
1734
1735 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1736 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c
ZY		 1737
1738 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1739 le16_to_cpu(txpower.channel),
1740 txpower.band,
14577f23
MA		 1741 txpower.power[i].tpc.tx_gain,
1742 txpower.power[i].tpc.dsp_atten,
1743 txpower.power[i].rate);
1744 }
1745 /* Fill CCK rates */
1746 for (rate_idx = IWL_FIRST_CCK_RATE;
1747 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1748 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1749 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23
MA		 1750
1751 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1752 le16_to_cpu(txpower.channel),
1753 txpower.band,
1754 txpower.power[i].tpc.tx_gain,
1755 txpower.power[i].tpc.dsp_atten,
1756 txpower.power[i].rate);
b481de9c
ZY		 1757 }
1758
bb8c093b
CH		 1759 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1760 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
b481de9c
ZY		 1761
1762}
1763
1764/**
bb8c093b 1765 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1766 * @ch_info: Channel to update. Uses power_info.requested_power.
1767 *
1768 * Replace requested_power and base_power_index ch_info fields for
1769 * one channel.
1770 *
1771 * Called if user or spectrum management changes power preferences.
1772 * Takes into account h/w and modulation limitations (clip power).
1773 *
1774 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1775 *
1776 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1777 * properly fill out the scan powers, and actual h/w gain settings,
1778 * and send changes to NIC
1779 */
bb8c093b
CH		 1780static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv,
1781 struct iwl3945_channel_info *ch_info)
b481de9c 1782{
bb8c093b 1783 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1784 int power_changed = 0;
1785 int i;
1786 const s8 *clip_pwrs;
1787 int power;
1788
1789 /* Get this chnlgrp's rate-to-max/clip-powers table */
1790 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1791
1792 /* Get this channel's rate-to-current-power settings table */
1793 power_info = ch_info->power_info;
1794
1795 /* update OFDM Txpower settings */
14577f23 1796 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1797 i++, ++power_info) {
1798 int delta_idx;
1799
1800 /* limit new power to be no more than h/w capability */
1801 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1802 if (power == power_info->requested_power)
1803 continue;
1804
1805 /* find difference between old and new requested powers,
1806 * update base (non-temp-compensated) power index */
1807 delta_idx = (power - power_info->requested_power) * 2;
1808 power_info->base_power_index -= delta_idx;
1809
1810 /* save new requested power value */
1811 power_info->requested_power = power;
1812
1813 power_changed = 1;
1814 }
1815
1816 /* update CCK Txpower settings, based on OFDM 12M setting ...
1817 * ... all CCK power settings for a given channel are the *same*. */
1818 if (power_changed) {
1819 power =
14577f23 1820 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1821 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1822
bb8c093b 1823 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1824 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1825 power_info->requested_power = power;
1826 power_info->base_power_index =
14577f23 1827 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1828 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1829 ++power_info;
1830 }
1831 }
1832
1833 return 0;
1834}
1835
1836/**
bb8c093b 1837 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1838 *
1839 * NOTE: Returned power limit may be less (but not more) than requested,
1840 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1841 * (no consideration for h/w clipping limitations).
1842 */
bb8c093b 1843static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_info)
b481de9c
ZY		 1844{
1845 s8 max_power;
1846
1847#if 0
1848 /* if we're using TGd limits, use lower of TGd or EEPROM */
1849 if (ch_info->tgd_data.max_power != 0)
1850 max_power = min(ch_info->tgd_data.max_power,
1851 ch_info->eeprom.max_power_avg);
1852
1853 /* else just use EEPROM limits */
1854 else
1855#endif
1856 max_power = ch_info->eeprom.max_power_avg;
1857
1858 return min(max_power, ch_info->max_power_avg);
1859}
1860
1861/**
bb8c093b 1862 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1863 *
1864 * Compensate txpower settings of *all* channels for temperature.
1865 * This only accounts for the difference between current temperature
1866 * and the factory calibration temperatures, and bases the new settings
1867 * on the channel's base_power_index.
1868 *
1869 * If RxOn is "associated", this sends the new Txpower to NIC!
1870 */
bb8c093b 1871static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
b481de9c 1872{
bb8c093b 1873 struct iwl3945_channel_info *ch_info = NULL;
b481de9c
ZY		 1874 int delta_index;
1875 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1876 u8 a_band;
1877 u8 rate_index;
1878 u8 scan_tbl_index;
1879 u8 i;
1880 int ref_temp;
1881 int temperature = priv->temperature;
1882
1883 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1884 for (i = 0; i < priv->channel_count; i++) {
1885 ch_info = &priv->channel_info[i];
1886 a_band = is_channel_a_band(ch_info);
1887
1888 /* Get this chnlgrp's factory calibration temperature */
1889 ref_temp = (s16)priv->eeprom.groups[ch_info->group_index].
1890 temperature;
1891
a96a27f9 1892 /* get power index adjustment based on current and factory
b481de9c 1893 * temps */
bb8c093b 1894 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1895 ref_temp);
1896
1897 /* set tx power value for all rates, OFDM and CCK */
1898 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1899 rate_index++) {
1900 int power_idx =
1901 ch_info->power_info[rate_index].base_power_index;
1902
1903 /* temperature compensate */
1904 power_idx += delta_index;
1905
1906 /* stay within table range */
bb8c093b 1907 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1908 ch_info->power_info[rate_index].
1909 power_table_index = (u8) power_idx;
1910 ch_info->power_info[rate_index].tpc =
1911 power_gain_table[a_band][power_idx];
1912 }
1913
1914 /* Get this chnlgrp's rate-to-max/clip-powers table */
1915 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1916
1917 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1918 for (scan_tbl_index = 0;
1919 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1920 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1921 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1922 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1923 actual_index, clip_pwrs,
1924 ch_info, a_band);
1925 }
1926 }
1927
1928 /* send Txpower command for current channel to ucode */
bb8c093b 1929 return iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1930}
1931
bb8c093b 1932int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power)
b481de9c 1933{
bb8c093b 1934 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 1935 s8 max_power;
1936 u8 a_band;
1937 u8 i;
1938
1939 if (priv->user_txpower_limit == power) {
1940 IWL_DEBUG_POWER("Requested Tx power same as current "
1941 "limit: %ddBm.\n", power);
1942 return 0;
1943 }
1944
1945 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1946 priv->user_txpower_limit = power;
1947
1948 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1949
1950 for (i = 0; i < priv->channel_count; i++) {
1951 ch_info = &priv->channel_info[i];
1952 a_band = is_channel_a_band(ch_info);
1953
1954 /* find minimum power of all user and regulatory constraints
1955 * (does not consider h/w clipping limitations) */
bb8c093b 1956 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1957 max_power = min(power, max_power);
1958 if (max_power != ch_info->curr_txpow) {
1959 ch_info->curr_txpow = max_power;
1960
1961 /* this considers the h/w clipping limitations */
bb8c093b 1962 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1963 }
1964 }
1965
1966 /* update txpower settings for all channels,
1967 * send to NIC if associated. */
1968 is_temp_calib_needed(priv);
bb8c093b 1969 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1970
1971 return 0;
1972}
1973
1974/* will add 3945 channel switch cmd handling later */
bb8c093b 1975int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel)
b481de9c
ZY		 1976{
1977 return 0;
1978}
1979
1980/**
1981 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1982 *
1983 * -- reset periodic timer
1984 * -- see if temp has changed enough to warrant re-calibration ... if so:
1985 * -- correct coeffs for temp (can reset temp timer)
1986 * -- save this temp as "last",
1987 * -- send new set of gain settings to NIC
1988 * NOTE: This should continue working, even when we're not associated,
1989 * so we can keep our internal table of scan powers current. */
bb8c093b 1990void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv)
b481de9c
ZY		 1991{
1992 /* This will kick in the "brute force"
bb8c093b 1993 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1994 if (!is_temp_calib_needed(priv))
1995 goto reschedule;
1996
1997 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1998 * This is based *only* on current temperature,
1999 * ignoring any previous power measurements */
bb8c093b 2000 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2001
2002 reschedule:
2003 queue_delayed_work(priv->workqueue,
2004 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2005}
2006
416e1438 2007static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2008{
bb8c093b 2009 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv,
b481de9c
ZY		 2010 thermal_periodic.work);
2011
2012 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2013 return;
2014
2015 mutex_lock(&priv->mutex);
2016 iwl3945_reg_txpower_periodic(priv);
2017 mutex_unlock(&priv->mutex);
2018}
2019
2020/**
bb8c093b 2021 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2022 * for the channel.
2023 *
2024 * This function is used when initializing channel-info structs.
2025 *
2026 * NOTE: These channel groups do *NOT* match the bands above!
2027 * These channel groups are based on factory-tested channels;
2028 * on A-band, EEPROM's "group frequency" entries represent the top
2029 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2030 */
bb8c093b
CH		 2031static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv,
2032 const struct iwl3945_channel_info *ch_info)
b481de9c 2033{
bb8c093b 2034 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0];
b481de9c
ZY		 2035 u8 group;
2036 u16 group_index = 0; /* based on factory calib frequencies */
2037 u8 grp_channel;
2038
2039 /* Find the group index for the channel ... don't use index 1(?) */
2040 if (is_channel_a_band(ch_info)) {
2041 for (group = 1; group < 5; group++) {
2042 grp_channel = ch_grp[group].group_channel;
2043 if (ch_info->channel <= grp_channel) {
2044 group_index = group;
2045 break;
2046 }
2047 }
2048 /* group 4 has a few channels *above* its factory cal freq */
2049 if (group == 5)
2050 group_index = 4;
2051 } else
2052 group_index = 0; /* 2.4 GHz, group 0 */
2053
2054 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2055 group_index);
2056 return group_index;
2057}
2058
2059/**
bb8c093b 2060 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2061 *
2062 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2063 * into radio/DSP gain settings table for requested power.
2064 */
bb8c093b 2065static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv,
b481de9c
ZY		 2066 s8 requested_power,
2067 s32 setting_index, s32 *new_index)
2068{
bb8c093b 2069 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
b481de9c
ZY		 2070 s32 index0, index1;
2071 s32 power = 2 * requested_power;
2072 s32 i;
bb8c093b 2073 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2074 s32 gains0, gains1;
2075 s32 res;
2076 s32 denominator;
2077
2078 chnl_grp = &priv->eeprom.groups[setting_index];
2079 samples = chnl_grp->samples;
2080 for (i = 0; i < 5; i++) {
2081 if (power == samples[i].power) {
2082 *new_index = samples[i].gain_index;
2083 return 0;
2084 }
2085 }
2086
2087 if (power > samples[1].power) {
2088 index0 = 0;
2089 index1 = 1;
2090 } else if (power > samples[2].power) {
2091 index0 = 1;
2092 index1 = 2;
2093 } else if (power > samples[3].power) {
2094 index0 = 2;
2095 index1 = 3;
2096 } else {
2097 index0 = 3;
2098 index1 = 4;
2099 }
2100
2101 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2102 if (denominator == 0)
2103 return -EINVAL;
2104 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2105 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2106 res = gains0 + (gains1 - gains0) *
2107 ((s32) power - (s32) samples[index0].power) / denominator +
2108 (1 << 18);
2109 *new_index = res >> 19;
2110 return 0;
2111}
2112
bb8c093b 2113static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
b481de9c
ZY		 2114{
2115 u32 i;
2116 s32 rate_index;
bb8c093b 2117 const struct iwl3945_eeprom_txpower_group *group;
b481de9c
ZY		 2118
2119 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2120
2121 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2122 s8 *clip_pwrs; /* table of power levels for each rate */
2123 s8 satur_pwr; /* saturation power for each chnl group */
2124 group = &priv->eeprom.groups[i];
2125
2126 /* sanity check on factory saturation power value */
2127 if (group->saturation_power < 40) {
2128 IWL_WARNING("Error: saturation power is %d, "
2129 "less than minimum expected 40\n",
2130 group->saturation_power);
2131 return;
2132 }
2133
2134 /*
2135 * Derive requested power levels for each rate, based on
2136 * hardware capabilities (saturation power for band).
2137 * Basic value is 3dB down from saturation, with further
2138 * power reductions for highest 3 data rates. These
2139 * backoffs provide headroom for high rate modulation
2140 * power peaks, without too much distortion (clipping).
2141 */
2142 /* we'll fill in this array with h/w max power levels */
2143 clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers;
2144
2145 /* divide factory saturation power by 2 to find -3dB level */
2146 satur_pwr = (s8) (group->saturation_power >> 1);
2147
2148 /* fill in channel group's nominal powers for each rate */
2149 for (rate_index = 0;
2150 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2151 switch (rate_index) {
14577f23 2152 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2153 if (i == 0) /* B/G */
2154 *clip_pwrs = satur_pwr;
2155 else /* A */
2156 *clip_pwrs = satur_pwr - 5;
2157 break;
14577f23 2158 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2159 if (i == 0)
2160 *clip_pwrs = satur_pwr - 7;
2161 else
2162 *clip_pwrs = satur_pwr - 10;
2163 break;
14577f23 2164 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2165 if (i == 0)
2166 *clip_pwrs = satur_pwr - 9;
2167 else
2168 *clip_pwrs = satur_pwr - 12;
2169 break;
2170 default:
2171 *clip_pwrs = satur_pwr;
2172 break;
2173 }
2174 }
2175 }
2176}
2177
2178/**
2179 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2180 *
2181 * Second pass (during init) to set up priv->channel_info
2182 *
2183 * Set up Tx-power settings in our channel info database for each VALID
2184 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2185 * and current temperature.
2186 *
2187 * Since this is based on current temperature (at init time), these values may
2188 * not be valid for very long, but it gives us a starting/default point,
2189 * and allows us to active (i.e. using Tx) scan.
2190 *
2191 * This does *not* write values to NIC, just sets up our internal table.
2192 */
bb8c093b 2193int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
b481de9c 2194{
bb8c093b
CH		 2195 struct iwl3945_channel_info *ch_info = NULL;
2196 struct iwl3945_channel_power_info *pwr_info;
b481de9c
ZY		 2197 int delta_index;
2198 u8 rate_index;
2199 u8 scan_tbl_index;
2200 const s8 *clip_pwrs; /* array of power levels for each rate */
2201 u8 gain, dsp_atten;
2202 s8 power;
2203 u8 pwr_index, base_pwr_index, a_band;
2204 u8 i;
2205 int temperature;
2206
2207 /* save temperature reference,
2208 * so we can determine next time to calibrate */
bb8c093b 2209 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2210 priv->last_temperature = temperature;
2211
bb8c093b 2212 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2213
2214 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2215 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2216 i++, ch_info++) {
2217 a_band = is_channel_a_band(ch_info);
2218 if (!is_channel_valid(ch_info))
2219 continue;
2220
2221 /* find this channel's channel group (*not* "band") index */
2222 ch_info->group_index =
bb8c093b 2223 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2224
2225 /* Get this chnlgrp's rate->max/clip-powers table */
2226 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
2227
2228 /* calculate power index *adjustment* value according to
2229 * diff between current temperature and factory temperature */
bb8c093b 2230 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 2231 priv->eeprom.groups[ch_info->group_index].
2232 temperature);
2233
2234 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2235 ch_info->channel, delta_index, temperature +
2236 IWL_TEMP_CONVERT);
2237
2238 /* set tx power value for all OFDM rates */
2239 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2240 rate_index++) {
2241 s32 power_idx;
2242 int rc;
2243
2244 /* use channel group's clip-power table,
2245 * but don't exceed channel's max power */
2246 s8 pwr = min(ch_info->max_power_avg,
2247 clip_pwrs[rate_index]);
2248
2249 pwr_info = &ch_info->power_info[rate_index];
2250
2251 /* get base (i.e. at factory-measured temperature)
2252 * power table index for this rate's power */
bb8c093b 2253 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2254 ch_info->group_index,
2255 &power_idx);
2256 if (rc) {
2257 IWL_ERROR("Invalid power index\n");
2258 return rc;
2259 }
2260 pwr_info->base_power_index = (u8) power_idx;
2261
2262 /* temperature compensate */
2263 power_idx += delta_index;
2264
2265 /* stay within range of gain table */
bb8c093b 2266 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2267
bb8c093b 2268 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2269 pwr_info->requested_power = pwr;
2270 pwr_info->power_table_index = (u8) power_idx;
2271 pwr_info->tpc.tx_gain =
2272 power_gain_table[a_band][power_idx].tx_gain;
2273 pwr_info->tpc.dsp_atten =
2274 power_gain_table[a_band][power_idx].dsp_atten;
2275 }
2276
2277 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2278 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2279 power = pwr_info->requested_power +
2280 IWL_CCK_FROM_OFDM_POWER_DIFF;
2281 pwr_index = pwr_info->power_table_index +
2282 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2283 base_pwr_index = pwr_info->base_power_index +
2284 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2285
2286 /* stay within table range */
bb8c093b 2287 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2288 gain = power_gain_table[a_band][pwr_index].tx_gain;
2289 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2290
bb8c093b 2291 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2292 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2293 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2294 for (rate_index = 0;
2295 rate_index < IWL_CCK_RATES; rate_index++) {
2296 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2297 pwr_info->requested_power = power;
2298 pwr_info->power_table_index = pwr_index;
2299 pwr_info->base_power_index = base_pwr_index;
2300 pwr_info->tpc.tx_gain = gain;
2301 pwr_info->tpc.dsp_atten = dsp_atten;
2302 }
2303
2304 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2305 for (scan_tbl_index = 0;
2306 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2307 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2308 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2309 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2310 actual_index, clip_pwrs, ch_info, a_band);
2311 }
2312 }
2313
2314 return 0;
2315}
2316
bb8c093b 2317int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
b481de9c
ZY		 2318{
2319 int rc;
2320 unsigned long flags;
2321
2322 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2323 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 2324 if (rc) {
2325 spin_unlock_irqrestore(&priv->lock, flags);
2326 return rc;
2327 }
2328
bb8c093b
CH		 2329 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
2330 rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
b481de9c
ZY		 2331 if (rc < 0)
2332 IWL_ERROR("Can't stop Rx DMA.\n");
2333
bb8c093b 2334 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2335 spin_unlock_irqrestore(&priv->lock, flags);
2336
2337 return 0;
2338}
2339
bb8c093b 2340int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c
ZY		 2341{
2342 int rc;
2343 unsigned long flags;
2344 int txq_id = txq->q.id;
2345
bb8c093b 2346 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 2347
2348 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2349
2350 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2351 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 2352 if (rc) {
2353 spin_unlock_irqrestore(&priv->lock, flags);
2354 return rc;
2355 }
bb8c093b
CH		 2356 iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
2357 iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
b481de9c 2358
bb8c093b 2359 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
b481de9c
ZY		 2360 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2361 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2362 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2363 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2364 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
bb8c093b 2365 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2366
2367 /* fake read to flush all prev. writes */
bb8c093b 2368 iwl3945_read32(priv, FH_TSSR_CBB_BASE);
b481de9c
ZY		 2369 spin_unlock_irqrestore(&priv->lock, flags);
2370
2371 return 0;
2372}
2373
bb8c093b 2374int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv)
b481de9c 2375{
bb8c093b 2376 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 2377
2378 return le32_to_cpu(shared_data->rx_read_ptr[0]);
2379}
2380
2381/**
2382 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2383 */
bb8c093b 2384int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv)
b481de9c 2385{
14577f23 2386 int rc, i, index, prev_index;
bb8c093b 2387 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2388 .reserved = {0, 0, 0},
2389 };
bb8c093b 2390 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2391
bb8c093b
CH		 2392 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2393 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2394
2395 table[index].rate_n_flags =
bb8c093b 2396 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2397 table[index].try_cnt = priv->retry_rate;
bb8c093b
CH		 2398 prev_index = iwl3945_get_prev_ieee_rate(i);
2399 table[index].next_rate_index = iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2400 }
2401
8318d78a
JB		 2402 switch (priv->band) {
2403 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 2404 IWL_DEBUG_RATE("Select A mode rate scale\n");
2405 /* If one of the following CCK rates is used,
2406 * have it fall back to the 6M OFDM rate */
14577f23 2407 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++)
bb8c093b 2408 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2409
2410 /* Don't fall back to CCK rates */
14577f23 2411 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2412
2413 /* Don't drop out of OFDM rates */
14577f23 2414 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2415 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2416 break;
2417
8318d78a
JB		 2418 case IEEE80211_BAND_2GHZ:
2419 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
b481de9c
ZY		 2420 /* If an OFDM rate is used, have it fall back to the
2421 * 1M CCK rates */
14577f23 2422 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; i++)
bb8c093b 2423 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_CCK_RATE].table_rs_index;
b481de9c
ZY		 2424
2425 /* CCK shouldn't fall back to OFDM... */
14577f23 2426 table[IWL_RATE_11M_INDEX_TABLE].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
b481de9c
ZY		 2427 break;
2428
2429 default:
8318d78a 2430 WARN_ON(1);
b481de9c
ZY		 2431 break;
2432 }
2433
2434 /* Update the rate scaling for control frame Tx */
2435 rate_cmd.table_id = 0;
bb8c093b 2436 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2437 &rate_cmd);
2438 if (rc)
2439 return rc;
2440
2441 /* Update the rate scaling for data frame Tx */
2442 rate_cmd.table_id = 1;
bb8c093b 2443 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2444 &rate_cmd);
2445}
2446
796083cb 2447/* Called when initializing driver */
bb8c093b 2448int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 2449{
2450 memset((void *)&priv->hw_setting, 0,
bb8c093b 2451 sizeof(struct iwl3945_driver_hw_info));
b481de9c
ZY		 2452
2453 priv->hw_setting.shared_virt =
2454 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2455 sizeof(struct iwl3945_shared),
b481de9c
ZY		 2456 &priv->hw_setting.shared_phys);
2457
2458 if (!priv->hw_setting.shared_virt) {
2459 IWL_ERROR("failed to allocate pci memory\n");
2460 mutex_unlock(&priv->mutex);
2461 return -ENOMEM;
2462 }
2463
9ee1ba47
RR		 2464 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE;
2465 priv->hw_setting.max_pkt_size = 2342;
bb8c093b 2466 priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd);
b481de9c
ZY		 2467 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2468 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
b481de9c
ZY		 2469 priv->hw_setting.max_stations = IWL3945_STATION_COUNT;
2470 priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822
TW		 2471
2472 priv->hw_setting.tx_ant_num = 2;
b481de9c
ZY		 2473 return 0;
2474}
2475
bb8c093b
CH		 2476unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
2477 struct iwl3945_frame *frame, u8 rate)
b481de9c 2478{
bb8c093b 2479 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2480 unsigned int frame_size;
2481
bb8c093b 2482 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2483 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2484
a4062b8f 2485 tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
b481de9c
ZY		 2486 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2487
bb8c093b 2488 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2489 tx_beacon_cmd->frame,
bb8c093b 2490 iwl3945_broadcast_addr,
b481de9c
ZY		 2491 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2492
2493 BUG_ON(frame_size > MAX_MPDU_SIZE);
2494 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2495
2496 tx_beacon_cmd->tx.rate = rate;
2497 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2498 TX_CMD_FLG_TSF_MSK);
2499
14577f23
MA		 2500 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2501 tx_beacon_cmd->tx.supp_rates[0] =
2502 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2503
b481de9c 2504 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2505 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2506
3ac7f146 2507 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2508}
2509
bb8c093b 2510void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv)
b481de9c 2511{
91c066f2 2512 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2513 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2514}
2515
bb8c093b 2516void iwl3945_hw_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 2517{
2518 INIT_DELAYED_WORK(&priv->thermal_periodic,
2519 iwl3945_bg_reg_txpower_periodic);
2520}
2521
bb8c093b 2522void iwl3945_hw_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 2523{
2524 cancel_delayed_work(&priv->thermal_periodic);
2525}
2526
82b9a121
TW		 2527static struct iwl_3945_cfg iwl3945_bg_cfg = {
2528 .name = "3945BG",
4bf775cd 2529 .fw_name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode",
82b9a121
TW		 2530 .sku = IWL_SKU_G,
2531};
2532
2533static struct iwl_3945_cfg iwl3945_abg_cfg = {
2534 .name = "3945ABG",
4bf775cd 2535 .fw_name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode",
82b9a121
TW		 2536 .sku = IWL_SKU_A|IWL_SKU_G,
2537};
2538
bb8c093b 2539struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2540 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2541 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2542 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2543 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2544 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2545 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2546 {0}
2547};
2548
bb8c093b 2549MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Clone of davem's net-next-2.6 tree